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Merge remote-tracking branch 'battery/for-next'
[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7 106{
1c1008c7 107 dmadesc_set_addr(priv, d, addr);
7ee40625 108 dmadesc_set_length_status(priv, d, val);
1c1008c7
FF		 109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
4a29645b
FF		 208 DMA_RING0_TIMEOUT,
209 DMA_RING1_TIMEOUT,
210 DMA_RING2_TIMEOUT,
211 DMA_RING3_TIMEOUT,
212 DMA_RING4_TIMEOUT,
213 DMA_RING5_TIMEOUT,
214 DMA_RING6_TIMEOUT,
215 DMA_RING7_TIMEOUT,
216 DMA_RING8_TIMEOUT,
217 DMA_RING9_TIMEOUT,
218 DMA_RING10_TIMEOUT,
219 DMA_RING11_TIMEOUT,
220 DMA_RING12_TIMEOUT,
221 DMA_RING13_TIMEOUT,
222 DMA_RING14_TIMEOUT,
223 DMA_RING15_TIMEOUT,
224 DMA_RING16_TIMEOUT,
1c1008c7
FF		 225};
226
227static const u8 bcmgenet_dma_regs_v3plus[] = {
228 [DMA_RING_CFG] = 0x00,
229 [DMA_CTRL] = 0x04,
230 [DMA_STATUS] = 0x08,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 233 [DMA_PRIORITY_0] = 0x30,
234 [DMA_PRIORITY_1] = 0x34,
235 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 236 [DMA_RING0_TIMEOUT] = 0x2C,
237 [DMA_RING1_TIMEOUT] = 0x30,
238 [DMA_RING2_TIMEOUT] = 0x34,
239 [DMA_RING3_TIMEOUT] = 0x38,
240 [DMA_RING4_TIMEOUT] = 0x3c,
241 [DMA_RING5_TIMEOUT] = 0x40,
242 [DMA_RING6_TIMEOUT] = 0x44,
243 [DMA_RING7_TIMEOUT] = 0x48,
244 [DMA_RING8_TIMEOUT] = 0x4c,
245 [DMA_RING9_TIMEOUT] = 0x50,
246 [DMA_RING10_TIMEOUT] = 0x54,
247 [DMA_RING11_TIMEOUT] = 0x58,
248 [DMA_RING12_TIMEOUT] = 0x5c,
249 [DMA_RING13_TIMEOUT] = 0x60,
250 [DMA_RING14_TIMEOUT] = 0x64,
251 [DMA_RING15_TIMEOUT] = 0x68,
252 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 253 [DMA_INDEX2RING_0] = 0x70,
254 [DMA_INDEX2RING_1] = 0x74,
255 [DMA_INDEX2RING_2] = 0x78,
256 [DMA_INDEX2RING_3] = 0x7C,
257 [DMA_INDEX2RING_4] = 0x80,
258 [DMA_INDEX2RING_5] = 0x84,
259 [DMA_INDEX2RING_6] = 0x88,
260 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 261};
262
263static const u8 bcmgenet_dma_regs_v2[] = {
264 [DMA_RING_CFG] = 0x00,
265 [DMA_CTRL] = 0x04,
266 [DMA_STATUS] = 0x08,
267 [DMA_SCB_BURST_SIZE] = 0x0C,
268 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 269 [DMA_PRIORITY_0] = 0x34,
270 [DMA_PRIORITY_1] = 0x38,
271 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 272 [DMA_RING0_TIMEOUT] = 0x2C,
273 [DMA_RING1_TIMEOUT] = 0x30,
274 [DMA_RING2_TIMEOUT] = 0x34,
275 [DMA_RING3_TIMEOUT] = 0x38,
276 [DMA_RING4_TIMEOUT] = 0x3c,
277 [DMA_RING5_TIMEOUT] = 0x40,
278 [DMA_RING6_TIMEOUT] = 0x44,
279 [DMA_RING7_TIMEOUT] = 0x48,
280 [DMA_RING8_TIMEOUT] = 0x4c,
281 [DMA_RING9_TIMEOUT] = 0x50,
282 [DMA_RING10_TIMEOUT] = 0x54,
283 [DMA_RING11_TIMEOUT] = 0x58,
284 [DMA_RING12_TIMEOUT] = 0x5c,
285 [DMA_RING13_TIMEOUT] = 0x60,
286 [DMA_RING14_TIMEOUT] = 0x64,
287 [DMA_RING15_TIMEOUT] = 0x68,
288 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 289};
290
291static const u8 bcmgenet_dma_regs_v1[] = {
292 [DMA_CTRL] = 0x00,
293 [DMA_STATUS] = 0x04,
294 [DMA_SCB_BURST_SIZE] = 0x0C,
295 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 296 [DMA_PRIORITY_0] = 0x34,
297 [DMA_PRIORITY_1] = 0x38,
298 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 299 [DMA_RING0_TIMEOUT] = 0x2C,
300 [DMA_RING1_TIMEOUT] = 0x30,
301 [DMA_RING2_TIMEOUT] = 0x34,
302 [DMA_RING3_TIMEOUT] = 0x38,
303 [DMA_RING4_TIMEOUT] = 0x3c,
304 [DMA_RING5_TIMEOUT] = 0x40,
305 [DMA_RING6_TIMEOUT] = 0x44,
306 [DMA_RING7_TIMEOUT] = 0x48,
307 [DMA_RING8_TIMEOUT] = 0x4c,
308 [DMA_RING9_TIMEOUT] = 0x50,
309 [DMA_RING10_TIMEOUT] = 0x54,
310 [DMA_RING11_TIMEOUT] = 0x58,
311 [DMA_RING12_TIMEOUT] = 0x5c,
312 [DMA_RING13_TIMEOUT] = 0x60,
313 [DMA_RING14_TIMEOUT] = 0x64,
314 [DMA_RING15_TIMEOUT] = 0x68,
315 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 316};
317
318/* Set at runtime once bcmgenet version is known */
319static const u8 *bcmgenet_dma_regs;
320
321static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322{
323 return netdev_priv(dev_get_drvdata(dev));
324}
325
326static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 327 enum dma_reg r)
1c1008c7
FF		 328{
329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331}
332
333static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334 u32 val, enum dma_reg r)
335{
336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338}
339
340static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 341 enum dma_reg r)
1c1008c7
FF		 342{
343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345}
346
347static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348 u32 val, enum dma_reg r)
349{
350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352}
353
354/* RDMA/TDMA ring registers and accessors
355 * we merge the common fields and just prefix with T/D the registers
356 * having different meaning depending on the direction
357 */
358enum dma_ring_reg {
359 TDMA_READ_PTR = 0,
360 RDMA_WRITE_PTR = TDMA_READ_PTR,
361 TDMA_READ_PTR_HI,
362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363 TDMA_CONS_INDEX,
364 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365 TDMA_PROD_INDEX,
366 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367 DMA_RING_BUF_SIZE,
368 DMA_START_ADDR,
369 DMA_START_ADDR_HI,
370 DMA_END_ADDR,
371 DMA_END_ADDR_HI,
372 DMA_MBUF_DONE_THRESH,
373 TDMA_FLOW_PERIOD,
374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375 TDMA_WRITE_PTR,
376 RDMA_READ_PTR = TDMA_WRITE_PTR,
377 TDMA_WRITE_PTR_HI,
378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379};
380
381/* GENET v4 supports 40-bits pointer addressing
382 * for obvious reasons the LO and HI word parts
383 * are contiguous, but this offsets the other
384 * registers.
385 */
386static const u8 genet_dma_ring_regs_v4[] = {
387 [TDMA_READ_PTR] = 0x00,
388 [TDMA_READ_PTR_HI] = 0x04,
389 [TDMA_CONS_INDEX] = 0x08,
390 [TDMA_PROD_INDEX] = 0x0C,
391 [DMA_RING_BUF_SIZE] = 0x10,
392 [DMA_START_ADDR] = 0x14,
393 [DMA_START_ADDR_HI] = 0x18,
394 [DMA_END_ADDR] = 0x1C,
395 [DMA_END_ADDR_HI] = 0x20,
396 [DMA_MBUF_DONE_THRESH] = 0x24,
397 [TDMA_FLOW_PERIOD] = 0x28,
398 [TDMA_WRITE_PTR] = 0x2C,
399 [TDMA_WRITE_PTR_HI] = 0x30,
400};
401
402static const u8 genet_dma_ring_regs_v123[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_CONS_INDEX] = 0x04,
405 [TDMA_PROD_INDEX] = 0x08,
406 [DMA_RING_BUF_SIZE] = 0x0C,
407 [DMA_START_ADDR] = 0x10,
408 [DMA_END_ADDR] = 0x14,
409 [DMA_MBUF_DONE_THRESH] = 0x18,
410 [TDMA_FLOW_PERIOD] = 0x1C,
411 [TDMA_WRITE_PTR] = 0x20,
412};
413
414/* Set at runtime once GENET version is known */
415static const u8 *genet_dma_ring_regs;
416
417static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 418 unsigned int ring,
419 enum dma_ring_reg r)
1c1008c7
FF		 420{
421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424}
425
426static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring, u32 val,
428 enum dma_ring_reg r)
1c1008c7
FF		 429{
430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433}
434
435static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring,
437 enum dma_ring_reg r)
1c1008c7
FF		 438{
439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
444static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 445 unsigned int ring, u32 val,
446 enum dma_ring_reg r)
1c1008c7
FF		 447{
448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451}
452
bac65c4b
PR		 453static int bcmgenet_get_settings(struct net_device *dev,
454 struct ethtool_cmd *cmd)
455{
456 if (!netif_running(dev))
457 return -EINVAL;
458
459 if (!dev->phydev)
460 return -ENODEV;
461
462 return phy_ethtool_gset(dev->phydev, cmd);
463}
464
465static int bcmgenet_set_settings(struct net_device *dev,
466 struct ethtool_cmd *cmd)
467{
468 if (!netif_running(dev))
469 return -EINVAL;
470
471 if (!dev->phydev)
472 return -ENODEV;
473
474 return phy_ethtool_sset(dev->phydev, cmd);
475}
476
1c1008c7
FF		 477static int bcmgenet_set_rx_csum(struct net_device *dev,
478 netdev_features_t wanted)
479{
480 struct bcmgenet_priv *priv = netdev_priv(dev);
481 u32 rbuf_chk_ctrl;
482 bool rx_csum_en;
483
484 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
485
486 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
487
488 /* enable rx checksumming */
489 if (rx_csum_en)
490 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
491 else
492 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
493 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 494
495 /* If UniMAC forwards CRC, we need to skip over it to get
496 * a valid CHK bit to be set in the per-packet status word
497 */
498 if (rx_csum_en && priv->crc_fwd_en)
499 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
500 else
501 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
502
1c1008c7
FF		 503 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
504
505 return 0;
506}
507
508static int bcmgenet_set_tx_csum(struct net_device *dev,
509 netdev_features_t wanted)
510{
511 struct bcmgenet_priv *priv = netdev_priv(dev);
512 bool desc_64b_en;
513 u32 tbuf_ctrl, rbuf_ctrl;
514
515 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
516 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
517
518 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
519
520 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
521 if (desc_64b_en) {
522 tbuf_ctrl |= RBUF_64B_EN;
523 rbuf_ctrl |= RBUF_64B_EN;
524 } else {
525 tbuf_ctrl &= ~RBUF_64B_EN;
526 rbuf_ctrl &= ~RBUF_64B_EN;
527 }
528 priv->desc_64b_en = desc_64b_en;
529
530 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
531 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
532
533 return 0;
534}
535
536static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 537 netdev_features_t features)
1c1008c7
FF		 538{
539 netdev_features_t changed = features ^ dev->features;
540 netdev_features_t wanted = dev->wanted_features;
541 int ret = 0;
542
543 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
544 ret = bcmgenet_set_tx_csum(dev, wanted);
545 if (changed & (NETIF_F_RXCSUM))
546 ret = bcmgenet_set_rx_csum(dev, wanted);
547
548 return ret;
549}
550
551static u32 bcmgenet_get_msglevel(struct net_device *dev)
552{
553 struct bcmgenet_priv *priv = netdev_priv(dev);
554
555 return priv->msg_enable;
556}
557
558static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
559{
560 struct bcmgenet_priv *priv = netdev_priv(dev);
561
562 priv->msg_enable = level;
563}
564
2f913070
FF		 565static int bcmgenet_get_coalesce(struct net_device *dev,
566 struct ethtool_coalesce *ec)
567{
568 struct bcmgenet_priv *priv = netdev_priv(dev);
569
570 ec->tx_max_coalesced_frames =
571 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
572 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 573 ec->rx_max_coalesced_frames =
574 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
575 DMA_MBUF_DONE_THRESH);
576 ec->rx_coalesce_usecs =
577 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070
FF		 578
579 return 0;
580}
581
582static int bcmgenet_set_coalesce(struct net_device *dev,
583 struct ethtool_coalesce *ec)
584{
585 struct bcmgenet_priv *priv = netdev_priv(dev);
586 unsigned int i;
4a29645b 587 u32 reg;
2f913070 588
4a29645b
FF		 589 /* Base system clock is 125Mhz, DMA timeout is this reference clock
590 * divided by 1024, which yields roughly 8.192us, our maximum value
591 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
592 */
2f913070 593 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 594 ec->tx_max_coalesced_frames == 0 ||
595 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
596 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
597 return -EINVAL;
598
599 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 600 return -EINVAL;
601
602 /* GENET TDMA hardware does not support a configurable timeout, but will
603 * always generate an interrupt either after MBDONE packets have been
604 * transmitted, or when the ring is emtpy.
605 */
606 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
852bcafb 607 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
2f913070
FF		 608 return -EOPNOTSUPP;
609
610 /* Program all TX queues with the same values, as there is no
611 * ethtool knob to do coalescing on a per-queue basis
612 */
613 for (i = 0; i < priv->hw_params->tx_queues; i++)
614 bcmgenet_tdma_ring_writel(priv, i,
615 ec->tx_max_coalesced_frames,
616 DMA_MBUF_DONE_THRESH);
617 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
618 ec->tx_max_coalesced_frames,
619 DMA_MBUF_DONE_THRESH);
620
4a29645b
FF		 621 for (i = 0; i < priv->hw_params->rx_queues; i++) {
622 bcmgenet_rdma_ring_writel(priv, i,
623 ec->rx_max_coalesced_frames,
624 DMA_MBUF_DONE_THRESH);
625
626 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
627 reg &= ~DMA_TIMEOUT_MASK;
628 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
629 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
630 }
631
632 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
633 ec->rx_max_coalesced_frames,
634 DMA_MBUF_DONE_THRESH);
635
636 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
637 reg &= ~DMA_TIMEOUT_MASK;
638 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
639 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
640
2f913070
FF		 641 return 0;
642}
643
1c1008c7
FF		 644/* standard ethtool support functions. */
645enum bcmgenet_stat_type {
646 BCMGENET_STAT_NETDEV = -1,
647 BCMGENET_STAT_MIB_RX,
648 BCMGENET_STAT_MIB_TX,
649 BCMGENET_STAT_RUNT,
650 BCMGENET_STAT_MISC,
f62ba9c1 651 BCMGENET_STAT_SOFT,
1c1008c7
FF		 652};
653
654struct bcmgenet_stats {
655 char stat_string[ETH_GSTRING_LEN];
656 int stat_sizeof;
657 int stat_offset;
658 enum bcmgenet_stat_type type;
659 /* reg offset from UMAC base for misc counters */
660 u16 reg_offset;
661};
662
663#define STAT_NETDEV(m) { \
664 .stat_string = __stringify(m), \
665 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
666 .stat_offset = offsetof(struct net_device_stats, m), \
667 .type = BCMGENET_STAT_NETDEV, \
668}
669
670#define STAT_GENET_MIB(str, m, _type) { \
671 .stat_string = str, \
672 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
673 .stat_offset = offsetof(struct bcmgenet_priv, m), \
674 .type = _type, \
675}
676
677#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
678#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
679#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 680#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 681
682#define STAT_GENET_MISC(str, m, offset) { \
683 .stat_string = str, \
684 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
685 .stat_offset = offsetof(struct bcmgenet_priv, m), \
686 .type = BCMGENET_STAT_MISC, \
687 .reg_offset = offset, \
688}
689
690
691/* There is a 0xC gap between the end of RX and beginning of TX stats and then
692 * between the end of TX stats and the beginning of the RX RUNT
693 */
694#define BCMGENET_STAT_OFFSET 0xc
695
696/* Hardware counters must be kept in sync because the order/offset
697 * is important here (order in structure declaration = order in hardware)
698 */
699static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
700 /* general stats */
701 STAT_NETDEV(rx_packets),
702 STAT_NETDEV(tx_packets),
703 STAT_NETDEV(rx_bytes),
704 STAT_NETDEV(tx_bytes),
705 STAT_NETDEV(rx_errors),
706 STAT_NETDEV(tx_errors),
707 STAT_NETDEV(rx_dropped),
708 STAT_NETDEV(tx_dropped),
709 STAT_NETDEV(multicast),
710 /* UniMAC RSV counters */
711 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
712 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
713 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
714 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
715 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
716 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
717 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
718 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
719 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
720 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
721 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
722 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
723 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
724 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
725 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
726 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
727 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
728 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
729 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
730 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
731 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
732 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
733 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
734 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
735 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
736 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
737 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
738 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
739 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
740 /* UniMAC TSV counters */
741 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
742 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
743 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
744 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
745 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
746 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
747 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
748 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
749 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
750 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
751 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
752 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
753 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
754 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
755 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
756 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
757 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
758 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
759 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
760 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
761 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
762 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
763 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
764 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
765 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
766 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
767 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
768 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
769 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
770 /* UniMAC RUNT counters */
771 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
772 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
773 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
774 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
775 /* Misc UniMAC counters */
776 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
777 UMAC_RBUF_OVFL_CNT),
778 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
779 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 780 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
781 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
782 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 783};
784
785#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
786
787static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 788 struct ethtool_drvinfo *info)
1c1008c7
FF		 789{
790 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
791 strlcpy(info->version, "v2.0", sizeof(info->version));
1c1008c7
FF		 792}
793
794static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
795{
796 switch (string_set) {
797 case ETH_SS_STATS:
798 return BCMGENET_STATS_LEN;
799 default:
800 return -EOPNOTSUPP;
801 }
802}
803
c91b7f66
FF		 804static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
805 u8 *data)
1c1008c7
FF		 806{
807 int i;
808
809 switch (stringset) {
810 case ETH_SS_STATS:
811 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
812 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 813 bcmgenet_gstrings_stats[i].stat_string,
814 ETH_GSTRING_LEN);
1c1008c7
FF		 815 }
816 break;
817 }
818}
819
820static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
821{
822 int i, j = 0;
823
824 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
825 const struct bcmgenet_stats *s;
826 u8 offset = 0;
827 u32 val = 0;
828 char *p;
829
830 s = &bcmgenet_gstrings_stats[i];
831 switch (s->type) {
832 case BCMGENET_STAT_NETDEV:
f62ba9c1 833 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 834 continue;
835 case BCMGENET_STAT_MIB_RX:
836 case BCMGENET_STAT_MIB_TX:
837 case BCMGENET_STAT_RUNT:
838 if (s->type != BCMGENET_STAT_MIB_RX)
839 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 840 val = bcmgenet_umac_readl(priv,
841 UMAC_MIB_START + j + offset);
1c1008c7
FF		 842 break;
843 case BCMGENET_STAT_MISC:
844 val = bcmgenet_umac_readl(priv, s->reg_offset);
845 /* clear if overflowed */
846 if (val == ~0)
847 bcmgenet_umac_writel(priv, 0, s->reg_offset);
848 break;
849 }
850
851 j += s->stat_sizeof;
852 p = (char *)priv + s->stat_offset;
853 *(u32 *)p = val;
854 }
855}
856
857static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 858 struct ethtool_stats *stats,
859 u64 *data)
1c1008c7
FF		 860{
861 struct bcmgenet_priv *priv = netdev_priv(dev);
862 int i;
863
864 if (netif_running(dev))
865 bcmgenet_update_mib_counters(priv);
866
867 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
868 const struct bcmgenet_stats *s;
869 char *p;
870
871 s = &bcmgenet_gstrings_stats[i];
872 if (s->type == BCMGENET_STAT_NETDEV)
873 p = (char *)&dev->stats;
874 else
875 p = (char *)priv;
876 p += s->stat_offset;
6517eb59
ED		 877 if (sizeof(unsigned long) != sizeof(u32) &&
878 s->stat_sizeof == sizeof(unsigned long))
879 data[i] = *(unsigned long *)p;
880 else
881 data[i] = *(u32 *)p;
1c1008c7
FF		 882 }
883}
884
6ef398ea
FF		 885static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
886{
887 struct bcmgenet_priv *priv = netdev_priv(dev);
888 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
889 u32 reg;
890
891 if (enable && !priv->clk_eee_enabled) {
892 clk_prepare_enable(priv->clk_eee);
893 priv->clk_eee_enabled = true;
894 }
895
896 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
897 if (enable)
898 reg |= EEE_EN;
899 else
900 reg &= ~EEE_EN;
901 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
902
903 /* Enable EEE and switch to a 27Mhz clock automatically */
904 reg = __raw_readl(priv->base + off);
905 if (enable)
906 reg |= TBUF_EEE_EN | TBUF_PM_EN;
907 else
908 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
909 __raw_writel(reg, priv->base + off);
910
911 /* Do the same for thing for RBUF */
912 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
913 if (enable)
914 reg |= RBUF_EEE_EN | RBUF_PM_EN;
915 else
916 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
917 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
918
919 if (!enable && priv->clk_eee_enabled) {
920 clk_disable_unprepare(priv->clk_eee);
921 priv->clk_eee_enabled = false;
922 }
923
924 priv->eee.eee_enabled = enable;
925 priv->eee.eee_active = enable;
926}
927
928static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
929{
930 struct bcmgenet_priv *priv = netdev_priv(dev);
931 struct ethtool_eee *p = &priv->eee;
932
933 if (GENET_IS_V1(priv))
934 return -EOPNOTSUPP;
935
936 e->eee_enabled = p->eee_enabled;
937 e->eee_active = p->eee_active;
938 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
939
62469c76 940 return phy_ethtool_get_eee(dev->phydev, e);
6ef398ea
FF		 941}
942
943static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
944{
945 struct bcmgenet_priv *priv = netdev_priv(dev);
946 struct ethtool_eee *p = &priv->eee;
947 int ret = 0;
948
949 if (GENET_IS_V1(priv))
950 return -EOPNOTSUPP;
951
952 p->eee_enabled = e->eee_enabled;
953
954 if (!p->eee_enabled) {
955 bcmgenet_eee_enable_set(dev, false);
956 } else {
62469c76 957 ret = phy_init_eee(dev->phydev, 0);
6ef398ea
FF		 958 if (ret) {
959 netif_err(priv, hw, dev, "EEE initialization failed\n");
960 return ret;
961 }
962
963 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
964 bcmgenet_eee_enable_set(dev, true);
965 }
966
62469c76 967 return phy_ethtool_set_eee(dev->phydev, e);
6ef398ea
FF		 968}
969
6b0c5406
FF		 970static int bcmgenet_nway_reset(struct net_device *dev)
971{
62469c76 972 return genphy_restart_aneg(dev->phydev);
6b0c5406
FF		 973}
974
1c1008c7 975/* standard ethtool support functions. */
70591ab9 976static const struct ethtool_ops bcmgenet_ethtool_ops = {
1c1008c7
FF		 977 .get_strings = bcmgenet_get_strings,
978 .get_sset_count = bcmgenet_get_sset_count,
979 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
bac65c4b
PR		 980 .get_settings = bcmgenet_get_settings,
981 .set_settings = bcmgenet_set_settings,
1c1008c7
FF		 982 .get_drvinfo = bcmgenet_get_drvinfo,
983 .get_link = ethtool_op_get_link,
984 .get_msglevel = bcmgenet_get_msglevel,
985 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 986 .get_wol = bcmgenet_get_wol,
987 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 988 .get_eee = bcmgenet_get_eee,
989 .set_eee = bcmgenet_set_eee,
6b0c5406 990 .nway_reset = bcmgenet_nway_reset,
2f913070
FF		 991 .get_coalesce = bcmgenet_get_coalesce,
992 .set_coalesce = bcmgenet_set_coalesce,
1c1008c7
FF		 993};
994
995/* Power down the unimac, based on mode. */
ca8cf341 996static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 997 enum bcmgenet_power_mode mode)
998{
62469c76 999 struct net_device *ndev = priv->dev;
ca8cf341 1000 int ret = 0;
1c1008c7
FF		 1001 u32 reg;
1002
1003 switch (mode) {
1004 case GENET_POWER_CABLE_SENSE:
62469c76 1005 phy_detach(ndev->phydev);
1c1008c7
FF		 1006 break;
1007
c3ae64ae 1008 case GENET_POWER_WOL_MAGIC:
ca8cf341 1009 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1010 break;
1011
1c1008c7
FF		 1012 case GENET_POWER_PASSIVE:
1013 /* Power down LED */
1c1008c7
FF		 1014 if (priv->hw_params->flags & GENET_HAS_EXT) {
1015 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1016 reg |= (EXT_PWR_DOWN_PHY |
1017 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1018 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1019
1020 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1021 }
1022 break;
1023 default:
1024 break;
1025 }
ca8cf341
FF		 1026
1027 return 0;
1c1008c7
FF		 1028}
1029
1030static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1031 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1032{
1033 u32 reg;
1034
1035 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1036 return;
1037
1038 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1039
1040 switch (mode) {
1041 case GENET_POWER_PASSIVE:
1042 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1043 EXT_PWR_DOWN_BIAS);
1044 /* fallthrough */
1045 case GENET_POWER_CABLE_SENSE:
1046 /* enable APD */
1047 reg |= EXT_PWR_DN_EN_LD;
1048 break;
c3ae64ae
FF		 1049 case GENET_POWER_WOL_MAGIC:
1050 bcmgenet_wol_power_up_cfg(priv, mode);
1051 return;
1c1008c7
FF		 1052 default:
1053 break;
1054 }
1055
1056 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
5dbebbb4 1057 if (mode == GENET_POWER_PASSIVE) {
bd4060a6 1058 bcmgenet_phy_power_set(priv->dev, true);
5dbebbb4
FF		 1059 bcmgenet_mii_reset(priv->dev);
1060 }
1c1008c7
FF		 1061}
1062
1063/* ioctl handle special commands that are not present in ethtool. */
1064static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1065{
1c1008c7
FF		 1066 int val = 0;
1067
1068 if (!netif_running(dev))
1069 return -EINVAL;
1070
1071 switch (cmd) {
1072 case SIOCGMIIPHY:
1073 case SIOCGMIIREG:
1074 case SIOCSMIIREG:
62469c76 1075 if (!dev->phydev)
1c1008c7
FF		 1076 val = -ENODEV;
1077 else
62469c76 1078 val = phy_mii_ioctl(dev->phydev, rq, cmd);
1c1008c7
FF		 1079 break;
1080
1081 default:
1082 val = -EINVAL;
1083 break;
1084 }
1085
1086 return val;
1087}
1088
1089static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1090 struct bcmgenet_tx_ring *ring)
1091{
1092 struct enet_cb *tx_cb_ptr;
1093
1094 tx_cb_ptr = ring->cbs;
1095 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1096
1c1008c7
FF		 1097 /* Advancing local write pointer */
1098 if (ring->write_ptr == ring->end_ptr)
1099 ring->write_ptr = ring->cb_ptr;
1100 else
1101 ring->write_ptr++;
1102
1103 return tx_cb_ptr;
1104}
1105
1106/* Simple helper to free a control block's resources */
1107static void bcmgenet_free_cb(struct enet_cb *cb)
1108{
1109 dev_kfree_skb_any(cb->skb);
1110 cb->skb = NULL;
1111 dma_unmap_addr_set(cb, dma_addr, 0);
1112}
1113
4055eaef
PG		 1114static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1115{
ee7d8c20 1116 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1117 INTRL2_CPU_MASK_SET);
1118}
1119
1120static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1121{
ee7d8c20 1122 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1123 INTRL2_CPU_MASK_CLEAR);
1124}
1125
1126static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1127{
1128 bcmgenet_intrl2_1_writel(ring->priv,
1129 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1130 INTRL2_CPU_MASK_SET);
1131}
1132
1133static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1134{
1135 bcmgenet_intrl2_1_writel(ring->priv,
1136 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1137 INTRL2_CPU_MASK_CLEAR);
1138}
1139
9dbac28f 1140static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1141{
ee7d8c20 1142 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1143 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1144}
1145
9dbac28f 1146static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1147{
ee7d8c20 1148 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1149 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1150}
1151
9dbac28f 1152static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1153{
9dbac28f 1154 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1155 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1156}
1157
9dbac28f 1158static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1159{
9dbac28f 1160 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1161 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1162}
1163
1164/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1165static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1166 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1167{
1168 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1169 struct enet_cb *tx_cb_ptr;
b2cde2cc 1170 struct netdev_queue *txq;
4092e6ac 1171 unsigned int pkts_compl = 0;
55868120 1172 unsigned int bytes_compl = 0;
1c1008c7 1173 unsigned int c_index;
66d06757
PG		 1174 unsigned int txbds_ready;
1175 unsigned int txbds_processed = 0;
1c1008c7 1176
7fc527f9 1177 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1178 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1179 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1180
66d06757
PG		 1181 if (likely(c_index >= ring->c_index))
1182 txbds_ready = c_index - ring->c_index;
1c1008c7 1183 else
66d06757 1184 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1185
1186 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1187 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1188 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1189
1190 /* Reclaim transmitted buffers */
66d06757
PG		 1191 while (txbds_processed < txbds_ready) {
1192 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1193 if (tx_cb_ptr->skb) {
4092e6ac 1194 pkts_compl++;
55868120 1195 bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
1c1008c7 1196 dma_unmap_single(&dev->dev,
c91b7f66 1197 dma_unmap_addr(tx_cb_ptr, dma_addr),
eee57723 1198 dma_unmap_len(tx_cb_ptr, dma_len),
c91b7f66 1199 DMA_TO_DEVICE);
1c1008c7
FF		 1200 bcmgenet_free_cb(tx_cb_ptr);
1201 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1c1008c7 1202 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1203 dma_unmap_addr(tx_cb_ptr, dma_addr),
1204 dma_unmap_len(tx_cb_ptr, dma_len),
1205 DMA_TO_DEVICE);
1c1008c7
FF		 1206 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1207 }
1c1008c7 1208
66d06757
PG		 1209 txbds_processed++;
1210 if (likely(ring->clean_ptr < ring->end_ptr))
1211 ring->clean_ptr++;
1212 else
1213 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1214 }
1215
66d06757
PG		 1216 ring->free_bds += txbds_processed;
1217 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1218
55868120
PG		 1219 dev->stats.tx_packets += pkts_compl;
1220 dev->stats.tx_bytes += bytes_compl;
1221
e178c8c2
PG		 1222 txq = netdev_get_tx_queue(dev, ring->queue);
1223 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
1224
4092e6ac
JS		 1225 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1226 if (netif_tx_queue_stopped(txq))
1227 netif_tx_wake_queue(txq);
1228 }
1c1008c7 1229
4092e6ac 1230 return pkts_compl;
1c1008c7
FF		 1231}
1232
4092e6ac 1233static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1234 struct bcmgenet_tx_ring *ring)
1c1008c7 1235{
4092e6ac 1236 unsigned int released;
1c1008c7
FF		 1237 unsigned long flags;
1238
1239 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1240 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1241 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1242
1243 return released;
1244}
1245
1246static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1247{
1248 struct bcmgenet_tx_ring *ring =
1249 container_of(napi, struct bcmgenet_tx_ring, napi);
1250 unsigned int work_done = 0;
1251
1252 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1253
1254 if (work_done == 0) {
1255 napi_complete(napi);
9dbac28f 1256 ring->int_enable(ring);
4092e6ac
JS		 1257
1258 return 0;
1259 }
1260
1261 return budget;
1c1008c7
FF		 1262}
1263
1264static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1265{
1266 struct bcmgenet_priv *priv = netdev_priv(dev);
1267 int i;
1268
1269 if (netif_is_multiqueue(dev)) {
1270 for (i = 0; i < priv->hw_params->tx_queues; i++)
1271 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1272 }
1273
1274 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1275}
1276
1277/* Transmits a single SKB (either head of a fragment or a single SKB)
1278 * caller must hold priv->lock
1279 */
1280static int bcmgenet_xmit_single(struct net_device *dev,
1281 struct sk_buff *skb,
1282 u16 dma_desc_flags,
1283 struct bcmgenet_tx_ring *ring)
1284{
1285 struct bcmgenet_priv *priv = netdev_priv(dev);
1286 struct device *kdev = &priv->pdev->dev;
1287 struct enet_cb *tx_cb_ptr;
1288 unsigned int skb_len;
1289 dma_addr_t mapping;
1290 u32 length_status;
1291 int ret;
1292
1293 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1294
1295 if (unlikely(!tx_cb_ptr))
1296 BUG();
1297
1298 tx_cb_ptr->skb = skb;
1299
7dd39913 1300 skb_len = skb_headlen(skb);
1c1008c7
FF		 1301
1302 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1303 ret = dma_mapping_error(kdev, mapping);
1304 if (ret) {
44c8bc3c 1305 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1306 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1307 dev_kfree_skb(skb);
1308 return ret;
1309 }
1310
1311 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
eee57723 1312 dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1c1008c7
FF		 1313 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1314 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1315 DMA_TX_APPEND_CRC;
1316
1317 if (skb->ip_summed == CHECKSUM_PARTIAL)
1318 length_status |= DMA_TX_DO_CSUM;
1319
1320 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1321
1c1008c7
FF		 1322 return 0;
1323}
1324
7fc527f9 1325/* Transmit a SKB fragment */
1c1008c7 1326static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1327 skb_frag_t *frag,
1328 u16 dma_desc_flags,
1329 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1330{
1331 struct bcmgenet_priv *priv = netdev_priv(dev);
1332 struct device *kdev = &priv->pdev->dev;
1333 struct enet_cb *tx_cb_ptr;
824ba603 1334 unsigned int frag_size;
1c1008c7
FF		 1335 dma_addr_t mapping;
1336 int ret;
1337
1338 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1339
1340 if (unlikely(!tx_cb_ptr))
1341 BUG();
824ba603 1342
1c1008c7
FF		 1343 tx_cb_ptr->skb = NULL;
1344
824ba603
PG		 1345 frag_size = skb_frag_size(frag);
1346
1347 mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1c1008c7
FF		 1348 ret = dma_mapping_error(kdev, mapping);
1349 if (ret) {
44c8bc3c 1350 priv->mib.tx_dma_failed++;
1c1008c7 1351 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1352 __func__);
1c1008c7
FF		 1353 return ret;
1354 }
1355
1356 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
824ba603 1357 dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1c1008c7
FF		 1358
1359 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
824ba603 1360 (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
c91b7f66 1361 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1362
1c1008c7
FF		 1363 return 0;
1364}
1365
1366/* Reallocate the SKB to put enough headroom in front of it and insert
1367 * the transmit checksum offsets in the descriptors
1368 */
bc23333b
PG		 1369static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1370 struct sk_buff *skb)
1c1008c7
FF		 1371{
1372 struct status_64 *status = NULL;
1373 struct sk_buff *new_skb;
1374 u16 offset;
1375 u8 ip_proto;
1376 u16 ip_ver;
1377 u32 tx_csum_info;
1378
1379 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1380 /* If 64 byte status block enabled, must make sure skb has
1381 * enough headroom for us to insert 64B status block.
1382 */
1383 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1384 dev_kfree_skb(skb);
1385 if (!new_skb) {
1c1008c7 1386 dev->stats.tx_dropped++;
bc23333b 1387 return NULL;
1c1008c7
FF		 1388 }
1389 skb = new_skb;
1390 }
1391
1392 skb_push(skb, sizeof(*status));
1393 status = (struct status_64 *)skb->data;
1394
1395 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1396 ip_ver = htons(skb->protocol);
1397 switch (ip_ver) {
1398 case ETH_P_IP:
1399 ip_proto = ip_hdr(skb)->protocol;
1400 break;
1401 case ETH_P_IPV6:
1402 ip_proto = ipv6_hdr(skb)->nexthdr;
1403 break;
1404 default:
bc23333b 1405 return skb;
1c1008c7
FF		 1406 }
1407
1408 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1409 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1410 (offset + skb->csum_offset);
1411
1412 /* Set the length valid bit for TCP and UDP and just set
1413 * the special UDP flag for IPv4, else just set to 0.
1414 */
1415 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1416 tx_csum_info |= STATUS_TX_CSUM_LV;
1417 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1418 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1419 } else {
1c1008c7 1420 tx_csum_info = 0;
8900ea57 1421 }
1c1008c7
FF		 1422
1423 status->tx_csum_info = tx_csum_info;
1424 }
1425
bc23333b 1426 return skb;
1c1008c7
FF		 1427}
1428
1429static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1430{
1431 struct bcmgenet_priv *priv = netdev_priv(dev);
1432 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1433 struct netdev_queue *txq;
1c1008c7
FF		 1434 unsigned long flags = 0;
1435 int nr_frags, index;
1436 u16 dma_desc_flags;
1437 int ret;
1438 int i;
1439
1440 index = skb_get_queue_mapping(skb);
1441 /* Mapping strategy:
1442 * queue_mapping = 0, unclassified, packet xmited through ring16
1443 * queue_mapping = 1, goes to ring 0. (highest priority queue
1444 * queue_mapping = 2, goes to ring 1.
1445 * queue_mapping = 3, goes to ring 2.
1446 * queue_mapping = 4, goes to ring 3.
1447 */
1448 if (index == 0)
1449 index = DESC_INDEX;
1450 else
1451 index -= 1;
1452
1c1008c7 1453 ring = &priv->tx_rings[index];
b2cde2cc 1454 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7 1455
f5a9ec20
PG		 1456 nr_frags = skb_shinfo(skb)->nr_frags;
1457
1c1008c7 1458 spin_lock_irqsave(&ring->lock, flags);
f5a9ec20
PG		 1459 if (ring->free_bds <= (nr_frags + 1)) {
1460 if (!netif_tx_queue_stopped(txq)) {
1461 netif_tx_stop_queue(txq);
1462 netdev_err(dev,
1463 "%s: tx ring %d full when queue %d awake\n",
1464 __func__, index, ring->queue);
1465 }
1c1008c7
FF		 1466 ret = NETDEV_TX_BUSY;
1467 goto out;
1468 }
1469
474ea9ca
FF		 1470 if (skb_padto(skb, ETH_ZLEN)) {
1471 ret = NETDEV_TX_OK;
1472 goto out;
1473 }
1474
55868120
PG		 1475 /* Retain how many bytes will be sent on the wire, without TSB inserted
1476 * by transmit checksum offload
1477 */
1478 GENET_CB(skb)->bytes_sent = skb->len;
1479
1c1008c7
FF		 1480 /* set the SKB transmit checksum */
1481 if (priv->desc_64b_en) {
bc23333b
PG		 1482 skb = bcmgenet_put_tx_csum(dev, skb);
1483 if (!skb) {
1c1008c7
FF		 1484 ret = NETDEV_TX_OK;
1485 goto out;
1486 }
1487 }
1488
1489 dma_desc_flags = DMA_SOP;
1490 if (nr_frags == 0)
1491 dma_desc_flags |= DMA_EOP;
1492
1493 /* Transmit single SKB or head of fragment list */
1494 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1495 if (ret) {
1496 ret = NETDEV_TX_OK;
1497 goto out;
1498 }
1499
1500 /* xmit fragment */
1501 for (i = 0; i < nr_frags; i++) {
1502 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1503 &skb_shinfo(skb)->frags[i],
1504 (i == nr_frags - 1) ? DMA_EOP : 0,
1505 ring);
1c1008c7
FF		 1506 if (ret) {
1507 ret = NETDEV_TX_OK;
1508 goto out;
1509 }
1510 }
1511
d03825fb
FF		 1512 skb_tx_timestamp(skb);
1513
ae67bf01
FF		 1514 /* Decrement total BD count and advance our write pointer */
1515 ring->free_bds -= nr_frags + 1;
1516 ring->prod_index += nr_frags + 1;
1517 ring->prod_index &= DMA_P_INDEX_MASK;
1518
e178c8c2
PG		 1519 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1520
4092e6ac 1521 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1522 netif_tx_stop_queue(txq);
1c1008c7 1523
ddd0ca5d
FF		 1524 if (!skb->xmit_more || netif_xmit_stopped(txq))
1525 /* Packets are ready, update producer index */
1526 bcmgenet_tdma_ring_writel(priv, ring->index,
1527 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1528out:
1529 spin_unlock_irqrestore(&ring->lock, flags);
1530
1531 return ret;
1532}
1533
d6707bec
PG		 1534static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1535 struct enet_cb *cb)
1c1008c7
FF		 1536{
1537 struct device *kdev = &priv->pdev->dev;
1538 struct sk_buff *skb;
d6707bec 1539 struct sk_buff *rx_skb;
1c1008c7 1540 dma_addr_t mapping;
1c1008c7 1541
d6707bec 1542 /* Allocate a new Rx skb */
c91b7f66 1543 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1544 if (!skb) {
1545 priv->mib.alloc_rx_buff_failed++;
1546 netif_err(priv, rx_err, priv->dev,
1547 "%s: Rx skb allocation failed\n", __func__);
1548 return NULL;
1549 }
1c1008c7 1550
d6707bec
PG		 1551 /* DMA-map the new Rx skb */
1552 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1553 DMA_FROM_DEVICE);
1554 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1555 priv->mib.rx_dma_failed++;
d6707bec 1556 dev_kfree_skb_any(skb);
1c1008c7 1557 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1558 "%s: Rx skb DMA mapping failed\n", __func__);
1559 return NULL;
1c1008c7
FF		 1560 }
1561
d6707bec
PG		 1562 /* Grab the current Rx skb from the ring and DMA-unmap it */
1563 rx_skb = cb->skb;
1564 if (likely(rx_skb))
1565 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1566 priv->rx_buf_len, DMA_FROM_DEVICE);
1567
1568 /* Put the new Rx skb on the ring */
1569 cb->skb = skb;
1c1008c7 1570 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1571 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1572
d6707bec
PG		 1573 /* Return the current Rx skb to caller */
1574 return rx_skb;
1c1008c7
FF		 1575}
1576
1577/* bcmgenet_desc_rx - descriptor based rx process.
1578 * this could be called from bottom half, or from NAPI polling method.
1579 */
4055eaef 1580static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1581 unsigned int budget)
1582{
4055eaef 1583 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1584 struct net_device *dev = priv->dev;
1585 struct enet_cb *cb;
1586 struct sk_buff *skb;
1587 u32 dma_length_status;
1588 unsigned long dma_flag;
d6707bec 1589 int len;
1c1008c7
FF		 1590 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1591 unsigned int p_index;
d26ea6cc 1592 unsigned int discards;
1c1008c7
FF		 1593 unsigned int chksum_ok = 0;
1594
4055eaef 1595 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1596
1597 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1598 DMA_P_INDEX_DISCARD_CNT_MASK;
1599 if (discards > ring->old_discards) {
1600 discards = discards - ring->old_discards;
1601 dev->stats.rx_missed_errors += discards;
1602 dev->stats.rx_errors += discards;
1603 ring->old_discards += discards;
1604
1605 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1606 if (ring->old_discards >= 0xC000) {
1607 ring->old_discards = 0;
4055eaef 1608 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1609 RDMA_PROD_INDEX);
1610 }
1611 }
1612
1c1008c7
FF		 1613 p_index &= DMA_P_INDEX_MASK;
1614
8ac467e8
PG		 1615 if (likely(p_index >= ring->c_index))
1616 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1617 else
8ac467e8
PG		 1618 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1619 p_index;
1c1008c7
FF		 1620
1621 netif_dbg(priv, rx_status, dev,
c91b7f66 1622 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1623
1624 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1625 (rxpktprocessed < budget)) {
8ac467e8 1626 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1627 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1628
b629be5c
FF		 1629 if (unlikely(!skb)) {
1630 dev->stats.rx_dropped++;
d6707bec 1631 goto next;
b629be5c
FF		 1632 }
1633
1c1008c7 1634 if (!priv->desc_64b_en) {
c91b7f66 1635 dma_length_status =
8ac467e8 1636 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1637 } else {
1638 struct status_64 *status;
164d4f20 1639
1c1008c7
FF		 1640 status = (struct status_64 *)skb->data;
1641 dma_length_status = status->length_status;
1642 }
1643
1644 /* DMA flags and length are still valid no matter how
1645 * we got the Receive Status Vector (64B RSB or register)
1646 */
1647 dma_flag = dma_length_status & 0xffff;
1648 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1649
1650 netif_dbg(priv, rx_status, dev,
c91b7f66 1651 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1652 __func__, p_index, ring->c_index,
1653 ring->read_ptr, dma_length_status);
1c1008c7 1654
1c1008c7
FF		 1655 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1656 netif_err(priv, rx_status, dev,
c91b7f66 1657 "dropping fragmented packet!\n");
1c1008c7 1658 dev->stats.rx_errors++;
d6707bec
PG		 1659 dev_kfree_skb_any(skb);
1660 goto next;
1c1008c7 1661 }
d6707bec 1662
1c1008c7
FF		 1663 /* report errors */
1664 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1665 DMA_RX_OV |
1666 DMA_RX_NO |
1667 DMA_RX_LG |
1668 DMA_RX_RXER))) {
1669 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1670 (unsigned int)dma_flag);
1c1008c7
FF		 1671 if (dma_flag & DMA_RX_CRC_ERROR)
1672 dev->stats.rx_crc_errors++;
1673 if (dma_flag & DMA_RX_OV)
1674 dev->stats.rx_over_errors++;
1675 if (dma_flag & DMA_RX_NO)
1676 dev->stats.rx_frame_errors++;
1677 if (dma_flag & DMA_RX_LG)
1678 dev->stats.rx_length_errors++;
1c1008c7 1679 dev->stats.rx_errors++;
d6707bec
PG		 1680 dev_kfree_skb_any(skb);
1681 goto next;
1c1008c7
FF		 1682 } /* error packet */
1683
1684 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1685 priv->desc_rxchk_en;
1c1008c7
FF		 1686
1687 skb_put(skb, len);
1688 if (priv->desc_64b_en) {
1689 skb_pull(skb, 64);
1690 len -= 64;
1691 }
1692
1693 if (likely(chksum_ok))
1694 skb->ip_summed = CHECKSUM_UNNECESSARY;
1695
1696 /* remove hardware 2bytes added for IP alignment */
1697 skb_pull(skb, 2);
1698 len -= 2;
1699
1700 if (priv->crc_fwd_en) {
1701 skb_trim(skb, len - ETH_FCS_LEN);
1702 len -= ETH_FCS_LEN;
1703 }
1704
1705 /*Finish setting up the received SKB and send it to the kernel*/
1706 skb->protocol = eth_type_trans(skb, priv->dev);
1707 dev->stats.rx_packets++;
1708 dev->stats.rx_bytes += len;
1709 if (dma_flag & DMA_RX_MULT)
1710 dev->stats.multicast++;
1711
1712 /* Notify kernel */
4055eaef 1713 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1714 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1715
d6707bec 1716next:
cf377d88 1717 rxpktprocessed++;
8ac467e8
PG		 1718 if (likely(ring->read_ptr < ring->end_ptr))
1719 ring->read_ptr++;
1720 else
1721 ring->read_ptr = ring->cb_ptr;
1722
1723 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1724 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1725 }
1726
1727 return rxpktprocessed;
1728}
1729
3ab11339
PG		 1730/* Rx NAPI polling method */
1731static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1732{
4055eaef
PG		 1733 struct bcmgenet_rx_ring *ring = container_of(napi,
1734 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1735 unsigned int work_done;
1736
4055eaef 1737 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1738
1739 if (work_done < budget) {
eb96ce01 1740 napi_complete_done(napi, work_done);
4055eaef 1741 ring->int_enable(ring);
3ab11339
PG		 1742 }
1743
1744 return work_done;
1745}
1746
1c1008c7 1747/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1748static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1749 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1750{
1751 struct enet_cb *cb;
d6707bec 1752 struct sk_buff *skb;
1c1008c7
FF		 1753 int i;
1754
8ac467e8 1755 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1756
1757 /* loop here for each buffer needing assign */
8ac467e8
PG		 1758 for (i = 0; i < ring->size; i++) {
1759 cb = ring->cbs + i;
d6707bec
PG		 1760 skb = bcmgenet_rx_refill(priv, cb);
1761 if (skb)
1762 dev_kfree_skb_any(skb);
1763 if (!cb->skb)
1764 return -ENOMEM;
1c1008c7
FF		 1765 }
1766
d6707bec 1767 return 0;
1c1008c7
FF		 1768}
1769
1770static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1771{
1772 struct enet_cb *cb;
1773 int i;
1774
1775 for (i = 0; i < priv->num_rx_bds; i++) {
1776 cb = &priv->rx_cbs[i];
1777
1778 if (dma_unmap_addr(cb, dma_addr)) {
1779 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1780 dma_unmap_addr(cb, dma_addr),
1781 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1782 dma_unmap_addr_set(cb, dma_addr, 0);
1783 }
1784
1785 if (cb->skb)
1786 bcmgenet_free_cb(cb);
1787 }
1788}
1789
c91b7f66 1790static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1791{
1792 u32 reg;
1793
1794 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1795 if (enable)
1796 reg |= mask;
1797 else
1798 reg &= ~mask;
1799 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1800
1801 /* UniMAC stops on a packet boundary, wait for a full-size packet
1802 * to be processed
1803 */
1804 if (enable == 0)
1805 usleep_range(1000, 2000);
1806}
1807
1c1008c7
FF		 1808static int reset_umac(struct bcmgenet_priv *priv)
1809{
1810 struct device *kdev = &priv->pdev->dev;
1811 unsigned int timeout = 0;
1812 u32 reg;
1813
1814 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1815 bcmgenet_rbuf_ctrl_set(priv, 0);
1816 udelay(10);
1817
1818 /* disable MAC while updating its registers */
1819 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1820
1821 /* issue soft reset, wait for it to complete */
1822 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1823 while (timeout++ < 1000) {
1824 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1825 if (!(reg & CMD_SW_RESET))
1826 return 0;
1827
1828 udelay(1);
1829 }
1830
1831 if (timeout == 1000) {
1832 dev_err(kdev,
7fc527f9 1833 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1834 return -ETIMEDOUT;
1835 }
1836
1837 return 0;
1838}
1839
909ff5ef
FF		 1840static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1841{
1842 /* Mask all interrupts.*/
1843 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1844 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1845 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1846 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1847 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1848 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1849}
1850
37850e37
FF		 1851static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1852{
1853 u32 int0_enable = 0;
1854
1855 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1856 * and MoCA PHY
1857 */
1858 if (priv->internal_phy) {
1859 int0_enable |= UMAC_IRQ_LINK_EVENT;
1860 } else if (priv->ext_phy) {
1861 int0_enable |= UMAC_IRQ_LINK_EVENT;
1862 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1863 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1864 int0_enable |= UMAC_IRQ_LINK_EVENT;
1865 }
1866 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1867}
1868
1c1008c7
FF		 1869static int init_umac(struct bcmgenet_priv *priv)
1870{
1871 struct device *kdev = &priv->pdev->dev;
1872 int ret;
b2e97eca
PG		 1873 u32 reg;
1874 u32 int0_enable = 0;
1875 u32 int1_enable = 0;
1876 int i;
1c1008c7
FF		 1877
1878 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1879
1880 ret = reset_umac(priv);
1881 if (ret)
1882 return ret;
1883
1884 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1885 /* clear tx/rx counter */
1886 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1887 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1888 UMAC_MIB_CTRL);
1c1008c7
FF		 1889 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1890
1891 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1892
1893 /* init rx registers, enable ip header optimization */
1894 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1895 reg |= RBUF_ALIGN_2B;
1896 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1897
1898 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1899 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1900
909ff5ef 1901 bcmgenet_intr_disable(priv);
1c1008c7 1902
b2e97eca 1903 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1904 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1905
b2e97eca 1906 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1907 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1908
37850e37
FF		 1909 /* Configure backpressure vectors for MoCA */
1910 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1911 reg = bcmgenet_bp_mc_get(priv);
1912 reg |= BIT(priv->hw_params->bp_in_en_shift);
1913
1914 /* bp_mask: back pressure mask */
1915 if (netif_is_multiqueue(priv->dev))
1916 reg |= priv->hw_params->bp_in_mask;
1917 else
1918 reg &= ~priv->hw_params->bp_in_mask;
1919 bcmgenet_bp_mc_set(priv, reg);
1920 }
1921
1922 /* Enable MDIO interrupts on GENET v3+ */
1923 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1924 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1925
4055eaef
PG		 1926 /* Enable Rx priority queue interrupts */
1927 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1928 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1929
b2e97eca
PG		 1930 /* Enable Tx priority queue interrupts */
1931 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1932 int1_enable |= (1 << i);
1c1008c7 1933
b2e97eca
PG		 1934 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1935 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1936
1c1008c7
FF		 1937 /* Enable rx/tx engine.*/
1938 dev_dbg(kdev, "done init umac\n");
1939
1940 return 0;
1941}
1942
4f8b2d7d 1943/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1944static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1945 unsigned int index, unsigned int size,
4f8b2d7d 1946 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1947{
1948 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1949 u32 words_per_bd = WORDS_PER_BD(priv);
1950 u32 flow_period_val = 0;
1c1008c7
FF		 1951
1952 spin_lock_init(&ring->lock);
4092e6ac 1953 ring->priv = priv;
1c1008c7
FF		 1954 ring->index = index;
1955 if (index == DESC_INDEX) {
1956 ring->queue = 0;
1957 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1958 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1959 } else {
1960 ring->queue = index + 1;
1961 ring->int_enable = bcmgenet_tx_ring_int_enable;
1962 ring->int_disable = bcmgenet_tx_ring_int_disable;
1963 }
4f8b2d7d 1964 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1965 ring->size = size;
66d06757 1966 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1967 ring->c_index = 0;
1968 ring->free_bds = size;
4f8b2d7d
PG		 1969 ring->write_ptr = start_ptr;
1970 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1971 ring->end_ptr = end_ptr - 1;
1972 ring->prod_index = 0;
1973
1974 /* Set flow period for ring != 16 */
1975 if (index != DESC_INDEX)
1976 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1977
1978 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1979 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1980 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1981 /* Disable rate control for now */
1982 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1983 TDMA_FLOW_PERIOD);
1c1008c7 1984 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1985 ((size << DMA_RING_SIZE_SHIFT) |
1986 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1987
1c1008c7 1988 /* Set start and end address, read and write pointers */
4f8b2d7d 1989 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1990 DMA_START_ADDR);
4f8b2d7d 1991 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1992 TDMA_READ_PTR);
4f8b2d7d 1993 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1994 TDMA_WRITE_PTR);
1c1008c7 1995 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1996 DMA_END_ADDR);
1c1008c7
FF		 1997}
1998
1999/* Initialize a RDMA ring */
2000static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 2001 unsigned int index, unsigned int size,
2002 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 2003{
8ac467e8 2004 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 2005 u32 words_per_bd = WORDS_PER_BD(priv);
2006 int ret;
2007
4055eaef 2008 ring->priv = priv;
8ac467e8 2009 ring->index = index;
4055eaef
PG		 2010 if (index == DESC_INDEX) {
2011 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2012 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2013 } else {
2014 ring->int_enable = bcmgenet_rx_ring_int_enable;
2015 ring->int_disable = bcmgenet_rx_ring_int_disable;
2016 }
8ac467e8
PG		 2017 ring->cbs = priv->rx_cbs + start_ptr;
2018 ring->size = size;
2019 ring->c_index = 0;
2020 ring->read_ptr = start_ptr;
2021 ring->cb_ptr = start_ptr;
2022 ring->end_ptr = end_ptr - 1;
1c1008c7 2023
8ac467e8
PG		 2024 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2025 if (ret)
1c1008c7 2026 return ret;
1c1008c7 2027
1c1008c7
FF		 2028 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2029 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 2030 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 2031 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2032 ((size << DMA_RING_SIZE_SHIFT) |
2033 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2034 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2035 (DMA_FC_THRESH_LO <<
2036 DMA_XOFF_THRESHOLD_SHIFT) |
2037 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2038
2039 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2040 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2041 DMA_START_ADDR);
2042 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2043 RDMA_READ_PTR);
2044 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2045 RDMA_WRITE_PTR);
2046 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2047 DMA_END_ADDR);
1c1008c7
FF		 2048
2049 return ret;
2050}
2051
e2aadb4a
PG		 2052static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2053{
2054 unsigned int i;
2055 struct bcmgenet_tx_ring *ring;
2056
2057 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2058 ring = &priv->tx_rings[i];
d64b5e85 2059 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2060 }
2061
2062 ring = &priv->tx_rings[DESC_INDEX];
d64b5e85 2063 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2064}
2065
2066static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2067{
2068 unsigned int i;
2069 struct bcmgenet_tx_ring *ring;
2070
2071 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2072 ring = &priv->tx_rings[i];
2073 napi_enable(&ring->napi);
2074 }
2075
2076 ring = &priv->tx_rings[DESC_INDEX];
2077 napi_enable(&ring->napi);
2078}
2079
2080static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2081{
2082 unsigned int i;
2083 struct bcmgenet_tx_ring *ring;
2084
2085 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2086 ring = &priv->tx_rings[i];
2087 napi_disable(&ring->napi);
2088 }
2089
2090 ring = &priv->tx_rings[DESC_INDEX];
2091 napi_disable(&ring->napi);
2092}
2093
2094static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2095{
2096 unsigned int i;
2097 struct bcmgenet_tx_ring *ring;
2098
2099 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2100 ring = &priv->tx_rings[i];
2101 netif_napi_del(&ring->napi);
2102 }
2103
2104 ring = &priv->tx_rings[DESC_INDEX];
2105 netif_napi_del(&ring->napi);
2106}
2107
16c6d667 2108/* Initialize Tx queues
1c1008c7 2109 *
16c6d667 2110 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2111 * with queue 0 being the highest priority queue.
2112 *
16c6d667 2113 * Queue 16 is the default Tx queue with
51a966a7 2114 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2115 *
16c6d667
PG		 2116 * The transmit control block pool is then partitioned as follows:
2117 * - Tx queue 0 uses tx_cbs[0..31]
2118 * - Tx queue 1 uses tx_cbs[32..63]
2119 * - Tx queue 2 uses tx_cbs[64..95]
2120 * - Tx queue 3 uses tx_cbs[96..127]
2121 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2122 */
16c6d667 2123static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2124{
2125 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2126 u32 i, dma_enable;
2127 u32 dma_ctrl, ring_cfg;
37742166 2128 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2129
1c1008c7
FF		 2130 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2131 dma_enable = dma_ctrl & DMA_EN;
2132 dma_ctrl &= ~DMA_EN;
2133 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2134
16c6d667
PG		 2135 dma_ctrl = 0;
2136 ring_cfg = 0;
2137
1c1008c7
FF		 2138 /* Enable strict priority arbiter mode */
2139 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2140
16c6d667 2141 /* Initialize Tx priority queues */
1c1008c7 2142 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2143 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2144 i * priv->hw_params->tx_bds_per_q,
2145 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2146 ring_cfg |= (1 << i);
2147 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2148 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2149 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2150 }
2151
16c6d667 2152 /* Initialize Tx default queue 16 */
51a966a7 2153 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2154 priv->hw_params->tx_queues *
51a966a7 2155 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2156 TOTAL_DESC);
2157 ring_cfg |= (1 << DESC_INDEX);
2158 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2159 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2160 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2161 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2162
2163 /* Set Tx queue priorities */
37742166
PG		 2164 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2165 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2166 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2167
e2aadb4a
PG		 2168 /* Initialize Tx NAPI */
2169 bcmgenet_init_tx_napi(priv);
2170
16c6d667
PG		 2171 /* Enable Tx queues */
2172 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2173
16c6d667 2174 /* Enable Tx DMA */
1c1008c7 2175 if (dma_enable)
16c6d667
PG		 2176 dma_ctrl |= DMA_EN;
2177 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2178}
2179
3ab11339
PG		 2180static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2181{
4055eaef
PG		 2182 unsigned int i;
2183 struct bcmgenet_rx_ring *ring;
2184
2185 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2186 ring = &priv->rx_rings[i];
2187 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2188 }
2189
2190 ring = &priv->rx_rings[DESC_INDEX];
2191 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2192}
2193
2194static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2195{
4055eaef
PG		 2196 unsigned int i;
2197 struct bcmgenet_rx_ring *ring;
2198
2199 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2200 ring = &priv->rx_rings[i];
2201 napi_enable(&ring->napi);
2202 }
2203
2204 ring = &priv->rx_rings[DESC_INDEX];
2205 napi_enable(&ring->napi);
3ab11339
PG		 2206}
2207
2208static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2209{
4055eaef
PG		 2210 unsigned int i;
2211 struct bcmgenet_rx_ring *ring;
2212
2213 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2214 ring = &priv->rx_rings[i];
2215 napi_disable(&ring->napi);
2216 }
2217
2218 ring = &priv->rx_rings[DESC_INDEX];
2219 napi_disable(&ring->napi);
3ab11339
PG		 2220}
2221
2222static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2223{
4055eaef
PG		 2224 unsigned int i;
2225 struct bcmgenet_rx_ring *ring;
2226
2227 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2228 ring = &priv->rx_rings[i];
2229 netif_napi_del(&ring->napi);
2230 }
2231
2232 ring = &priv->rx_rings[DESC_INDEX];
2233 netif_napi_del(&ring->napi);
3ab11339
PG		 2234}
2235
8ac467e8
PG		 2236/* Initialize Rx queues
2237 *
2238 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2239 * used to direct traffic to these queues.
2240 *
2241 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2242 */
2243static int bcmgenet_init_rx_queues(struct net_device *dev)
2244{
2245 struct bcmgenet_priv *priv = netdev_priv(dev);
2246 u32 i;
2247 u32 dma_enable;
2248 u32 dma_ctrl;
2249 u32 ring_cfg;
2250 int ret;
2251
2252 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2253 dma_enable = dma_ctrl & DMA_EN;
2254 dma_ctrl &= ~DMA_EN;
2255 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2256
2257 dma_ctrl = 0;
2258 ring_cfg = 0;
2259
2260 /* Initialize Rx priority queues */
2261 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2262 ret = bcmgenet_init_rx_ring(priv, i,
2263 priv->hw_params->rx_bds_per_q,
2264 i * priv->hw_params->rx_bds_per_q,
2265 (i + 1) *
2266 priv->hw_params->rx_bds_per_q);
2267 if (ret)
2268 return ret;
2269
2270 ring_cfg |= (1 << i);
2271 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2272 }
2273
2274 /* Initialize Rx default queue 16 */
2275 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2276 priv->hw_params->rx_queues *
2277 priv->hw_params->rx_bds_per_q,
2278 TOTAL_DESC);
2279 if (ret)
2280 return ret;
2281
2282 ring_cfg |= (1 << DESC_INDEX);
2283 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2284
3ab11339
PG		 2285 /* Initialize Rx NAPI */
2286 bcmgenet_init_rx_napi(priv);
2287
8ac467e8
PG		 2288 /* Enable rings */
2289 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2290
2291 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2292 if (dma_enable)
2293 dma_ctrl |= DMA_EN;
2294 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2295
2296 return 0;
2297}
2298
4a0c081e
FF		 2299static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2300{
2301 int ret = 0;
2302 int timeout = 0;
2303 u32 reg;
b6df7d61
JS		 2304 u32 dma_ctrl;
2305 int i;
4a0c081e
FF		 2306
2307 /* Disable TDMA to stop add more frames in TX DMA */
2308 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2309 reg &= ~DMA_EN;
2310 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2311
2312 /* Check TDMA status register to confirm TDMA is disabled */
2313 while (timeout++ < DMA_TIMEOUT_VAL) {
2314 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2315 if (reg & DMA_DISABLED)
2316 break;
2317
2318 udelay(1);
2319 }
2320
2321 if (timeout == DMA_TIMEOUT_VAL) {
2322 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2323 ret = -ETIMEDOUT;
2324 }
2325
2326 /* Wait 10ms for packet drain in both tx and rx dma */
2327 usleep_range(10000, 20000);
2328
2329 /* Disable RDMA */
2330 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2331 reg &= ~DMA_EN;
2332 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2333
2334 timeout = 0;
2335 /* Check RDMA status register to confirm RDMA is disabled */
2336 while (timeout++ < DMA_TIMEOUT_VAL) {
2337 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2338 if (reg & DMA_DISABLED)
2339 break;
2340
2341 udelay(1);
2342 }
2343
2344 if (timeout == DMA_TIMEOUT_VAL) {
2345 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2346 ret = -ETIMEDOUT;
2347 }
2348
b6df7d61
JS		 2349 dma_ctrl = 0;
2350 for (i = 0; i < priv->hw_params->rx_queues; i++)
2351 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2352 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2353 reg &= ~dma_ctrl;
2354 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2355
2356 dma_ctrl = 0;
2357 for (i = 0; i < priv->hw_params->tx_queues; i++)
2358 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2359 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2360 reg &= ~dma_ctrl;
2361 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2362
4a0c081e
FF		 2363 return ret;
2364}
2365
9abab96d 2366static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2367{
2368 int i;
e178c8c2 2369 struct netdev_queue *txq;
1c1008c7 2370
9abab96d
PG		 2371 bcmgenet_fini_rx_napi(priv);
2372 bcmgenet_fini_tx_napi(priv);
2373
1c1008c7 2374 /* disable DMA */
4a0c081e 2375 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2376
2377 for (i = 0; i < priv->num_tx_bds; i++) {
2378 if (priv->tx_cbs[i].skb != NULL) {
2379 dev_kfree_skb(priv->tx_cbs[i].skb);
2380 priv->tx_cbs[i].skb = NULL;
2381 }
2382 }
2383
e178c8c2
PG		 2384 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2385 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2386 netdev_tx_reset_queue(txq);
2387 }
2388
2389 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2390 netdev_tx_reset_queue(txq);
2391
1c1008c7
FF		 2392 bcmgenet_free_rx_buffers(priv);
2393 kfree(priv->rx_cbs);
2394 kfree(priv->tx_cbs);
2395}
2396
2397/* init_edma: Initialize DMA control register */
2398static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2399{
2400 int ret;
014012a4
PG		 2401 unsigned int i;
2402 struct enet_cb *cb;
1c1008c7 2403
6f5a272c 2404 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2405
6f5a272c
PG		 2406 /* Initialize common Rx ring structures */
2407 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2408 priv->num_rx_bds = TOTAL_DESC;
2409 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2410 GFP_KERNEL);
2411 if (!priv->rx_cbs)
2412 return -ENOMEM;
2413
2414 for (i = 0; i < priv->num_rx_bds; i++) {
2415 cb = priv->rx_cbs + i;
2416 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2417 }
2418
7fc527f9 2419 /* Initialize common TX ring structures */
1c1008c7
FF		 2420 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2421 priv->num_tx_bds = TOTAL_DESC;
c489be08 2422 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2423 GFP_KERNEL);
1c1008c7 2424 if (!priv->tx_cbs) {
ebbd96fb 2425 kfree(priv->rx_cbs);
1c1008c7
FF		 2426 return -ENOMEM;
2427 }
2428
014012a4
PG		 2429 for (i = 0; i < priv->num_tx_bds; i++) {
2430 cb = priv->tx_cbs + i;
2431 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2432 }
2433
ebbd96fb
PG		 2434 /* Init rDma */
2435 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2436
2437 /* Initialize Rx queues */
2438 ret = bcmgenet_init_rx_queues(priv->dev);
2439 if (ret) {
2440 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2441 bcmgenet_free_rx_buffers(priv);
2442 kfree(priv->rx_cbs);
2443 kfree(priv->tx_cbs);
2444 return ret;
2445 }
2446
2447 /* Init tDma */
2448 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2449
16c6d667
PG		 2450 /* Initialize Tx queues */
2451 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2452
2453 return 0;
2454}
2455
1c1008c7
FF		 2456/* Interrupt bottom half */
2457static void bcmgenet_irq_task(struct work_struct *work)
2458{
2459 struct bcmgenet_priv *priv = container_of(
2460 work, struct bcmgenet_priv, bcmgenet_irq_work);
62469c76 2461 struct net_device *ndev = priv->dev;
1c1008c7
FF		 2462
2463 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2464
8fdb0e0f
FF		 2465 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2466 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2467 netif_dbg(priv, wol, priv->dev,
2468 "magic packet detected, waking up\n");
2469 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2470 }
2471
1c1008c7 2472 /* Link UP/DOWN event */
d07c0278 2473 if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
62469c76 2474 phy_mac_interrupt(ndev->phydev,
451e1ca2 2475 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
e122966d 2476 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2477 }
2478}
2479
4055eaef 2480/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2481static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2482{
2483 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2484 struct bcmgenet_rx_ring *rx_ring;
2485 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2486 unsigned int index;
2487
2488 /* Save irq status for bottom-half processing. */
2489 priv->irq1_stat =
2490 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2491 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2492
7fc527f9 2493 /* clear interrupts */
1c1008c7
FF		 2494 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2495
2496 netif_dbg(priv, intr, priv->dev,
c91b7f66 2497 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2498
4055eaef
PG		 2499 /* Check Rx priority queue interrupts */
2500 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2501 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2502 continue;
2503
2504 rx_ring = &priv->rx_rings[index];
2505
2506 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2507 rx_ring->int_disable(rx_ring);
dac916f8 2508 __napi_schedule_irqoff(&rx_ring->napi);
4055eaef
PG		 2509 }
2510 }
2511
2512 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2513 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2514 if (!(priv->irq1_stat & BIT(index)))
2515 continue;
2516
4055eaef 2517 tx_ring = &priv->tx_rings[index];
4092e6ac 2518
4055eaef
PG		 2519 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2520 tx_ring->int_disable(tx_ring);
dac916f8 2521 __napi_schedule_irqoff(&tx_ring->napi);
1c1008c7
FF		 2522 }
2523 }
4092e6ac 2524
1c1008c7
FF		 2525 return IRQ_HANDLED;
2526}
2527
4055eaef 2528/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2529static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2530{
2531 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2532 struct bcmgenet_rx_ring *rx_ring;
2533 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2534
2535 /* Save irq status for bottom-half processing. */
2536 priv->irq0_stat =
2537 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2538 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2539
7fc527f9 2540 /* clear interrupts */
1c1008c7
FF		 2541 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2542
2543 netif_dbg(priv, intr, priv->dev,
c91b7f66 2544 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2545
ee7d8c20 2546 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2547 rx_ring = &priv->rx_rings[DESC_INDEX];
2548
2549 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2550 rx_ring->int_disable(rx_ring);
dac916f8 2551 __napi_schedule_irqoff(&rx_ring->napi);
1c1008c7
FF		 2552 }
2553 }
4092e6ac 2554
ee7d8c20 2555 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2556 tx_ring = &priv->tx_rings[DESC_INDEX];
2557
2558 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2559 tx_ring->int_disable(tx_ring);
dac916f8 2560 __napi_schedule_irqoff(&tx_ring->napi);
4092e6ac 2561 }
1c1008c7 2562 }
4055eaef 2563
1c1008c7
FF		 2564 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2565 UMAC_IRQ_PHY_DET_F |
e122966d 2566 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2567 UMAC_IRQ_HFB_SM |
2568 UMAC_IRQ_HFB_MM |
2569 UMAC_IRQ_MPD_R)) {
2570 /* all other interested interrupts handled in bottom half */
2571 schedule_work(&priv->bcmgenet_irq_work);
2572 }
2573
2574 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2575 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2576 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2577 wake_up(&priv->wq);
2578 }
2579
2580 return IRQ_HANDLED;
2581}
2582
8562056f
FF		 2583static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2584{
2585 struct bcmgenet_priv *priv = dev_id;
2586
2587 pm_wakeup_event(&priv->pdev->dev, 0);
2588
2589 return IRQ_HANDLED;
2590}
2591
4d2e8882
FF		 2592#ifdef CONFIG_NET_POLL_CONTROLLER
2593static void bcmgenet_poll_controller(struct net_device *dev)
2594{
2595 struct bcmgenet_priv *priv = netdev_priv(dev);
2596
2597 /* Invoke the main RX/TX interrupt handler */
2598 disable_irq(priv->irq0);
2599 bcmgenet_isr0(priv->irq0, priv);
2600 enable_irq(priv->irq0);
2601
2602 /* And the interrupt handler for RX/TX priority queues */
2603 disable_irq(priv->irq1);
2604 bcmgenet_isr1(priv->irq1, priv);
2605 enable_irq(priv->irq1);
2606}
2607#endif
2608
1c1008c7
FF		 2609static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2610{
2611 u32 reg;
2612
2613 reg = bcmgenet_rbuf_ctrl_get(priv);
2614 reg |= BIT(1);
2615 bcmgenet_rbuf_ctrl_set(priv, reg);
2616 udelay(10);
2617
2618 reg &= ~BIT(1);
2619 bcmgenet_rbuf_ctrl_set(priv, reg);
2620 udelay(10);
2621}
2622
2623static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2624 unsigned char *addr)
1c1008c7
FF		 2625{
2626 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2627 (addr[2] << 8) | addr[3], UMAC_MAC0);
2628 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2629}
2630
1c1008c7
FF		 2631/* Returns a reusable dma control register value */
2632static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2633{
2634 u32 reg;
2635 u32 dma_ctrl;
2636
2637 /* disable DMA */
2638 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2639 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2640 reg &= ~dma_ctrl;
2641 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2642
2643 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2644 reg &= ~dma_ctrl;
2645 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2646
2647 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2648 udelay(10);
2649 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2650
2651 return dma_ctrl;
2652}
2653
2654static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2655{
2656 u32 reg;
2657
2658 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2659 reg |= dma_ctrl;
2660 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2661
2662 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2663 reg |= dma_ctrl;
2664 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2665}
2666
0034de41
PG		 2667static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2668 u32 f_index)
2669{
2670 u32 offset;
2671 u32 reg;
2672
2673 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2674 reg = bcmgenet_hfb_reg_readl(priv, offset);
2675 return !!(reg & (1 << (f_index % 32)));
2676}
2677
2678static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2679{
2680 u32 offset;
2681 u32 reg;
2682
2683 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2684 reg = bcmgenet_hfb_reg_readl(priv, offset);
2685 reg |= (1 << (f_index % 32));
2686 bcmgenet_hfb_reg_writel(priv, reg, offset);
2687}
2688
2689static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2690 u32 f_index, u32 rx_queue)
2691{
2692 u32 offset;
2693 u32 reg;
2694
2695 offset = f_index / 8;
2696 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2697 reg &= ~(0xF << (4 * (f_index % 8)));
2698 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2699 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2700}
2701
2702static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2703 u32 f_index, u32 f_length)
2704{
2705 u32 offset;
2706 u32 reg;
2707
2708 offset = HFB_FLT_LEN_V3PLUS +
2709 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2710 sizeof(u32);
2711 reg = bcmgenet_hfb_reg_readl(priv, offset);
2712 reg &= ~(0xFF << (8 * (f_index % 4)));
2713 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2714 bcmgenet_hfb_reg_writel(priv, reg, offset);
2715}
2716
2717static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2718{
2719 u32 f_index;
2720
2721 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2722 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2723 return f_index;
2724
2725 return -ENOMEM;
2726}
2727
2728/* bcmgenet_hfb_add_filter
2729 *
2730 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2731 * desired Rx queue.
2732 *
2733 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2734 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2735 *
2736 * bits 31:20 - unused
2737 * bit 19 - nibble 0 match enable
2738 * bit 18 - nibble 1 match enable
2739 * bit 17 - nibble 2 match enable
2740 * bit 16 - nibble 3 match enable
2741 * bits 15:12 - nibble 0 data
2742 * bits 11:8 - nibble 1 data
2743 * bits 7:4 - nibble 2 data
2744 * bits 3:0 - nibble 3 data
2745 *
2746 * Example:
2747 * In order to match:
2748 * - Ethernet frame type = 0x0800 (IP)
2749 * - IP version field = 4
2750 * - IP protocol field = 0x11 (UDP)
2751 *
2752 * The following filter is needed:
2753 * u32 hfb_filter_ipv4_udp[] = {
2754 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2755 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2756 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2757 * };
2758 *
2759 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2760 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2761 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2762 */
2763int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2764 u32 f_length, u32 rx_queue)
2765{
2766 int f_index;
2767 u32 i;
2768
2769 f_index = bcmgenet_hfb_find_unused_filter(priv);
2770 if (f_index < 0)
2771 return -ENOMEM;
2772
2773 if (f_length > priv->hw_params->hfb_filter_size)
2774 return -EINVAL;
2775
2776 for (i = 0; i < f_length; i++)
2777 bcmgenet_hfb_writel(priv, f_data[i],
2778 (f_index * priv->hw_params->hfb_filter_size + i) *
2779 sizeof(u32));
2780
2781 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2782 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2783 bcmgenet_hfb_enable_filter(priv, f_index);
2784 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2785
2786 return 0;
2787}
2788
2789/* bcmgenet_hfb_clear
2790 *
2791 * Clear Hardware Filter Block and disable all filtering.
2792 */
2793static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2794{
2795 u32 i;
2796
2797 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2798 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2799 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2800
2801 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2802 bcmgenet_rdma_writel(priv, 0x0, i);
2803
2804 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2805 bcmgenet_hfb_reg_writel(priv, 0x0,
2806 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2807
2808 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2809 priv->hw_params->hfb_filter_size; i++)
2810 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2811}
2812
2813static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2814{
2815 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2816 return;
2817
2818 bcmgenet_hfb_clear(priv);
2819}
2820
909ff5ef
FF		 2821static void bcmgenet_netif_start(struct net_device *dev)
2822{
2823 struct bcmgenet_priv *priv = netdev_priv(dev);
2824
2825 /* Start the network engine */
3ab11339 2826 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2827 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2828
2829 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2830
909ff5ef
FF		 2831 netif_tx_start_all_queues(dev);
2832
37850e37
FF		 2833 /* Monitor link interrupts now */
2834 bcmgenet_link_intr_enable(priv);
2835
62469c76 2836 phy_start(dev->phydev);
909ff5ef
FF		 2837}
2838
1c1008c7
FF		 2839static int bcmgenet_open(struct net_device *dev)
2840{
2841 struct bcmgenet_priv *priv = netdev_priv(dev);
2842 unsigned long dma_ctrl;
2843 u32 reg;
2844 int ret;
2845
2846 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2847
2848 /* Turn on the clock */
7d5d3075 2849 clk_prepare_enable(priv->clk);
1c1008c7 2850
a642c4f7
FF		 2851 /* If this is an internal GPHY, power it back on now, before UniMAC is
2852 * brought out of reset as absolutely no UniMAC activity is allowed
2853 */
c624f891 2854 if (priv->internal_phy)
a642c4f7
FF		 2855 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2856
1c1008c7
FF		 2857 /* take MAC out of reset */
2858 bcmgenet_umac_reset(priv);
2859
2860 ret = init_umac(priv);
2861 if (ret)
2862 goto err_clk_disable;
2863
2864 /* disable ethernet MAC while updating its registers */
e29585b8 2865 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2866
909ff5ef
FF		 2867 /* Make sure we reflect the value of CRC_CMD_FWD */
2868 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2869 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2870
1c1008c7
FF		 2871 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2872
c624f891 2873 if (priv->internal_phy) {
1c1008c7
FF		 2874 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2875 reg |= EXT_ENERGY_DET_MASK;
2876 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2877 }
2878
2879 /* Disable RX/TX DMA and flush TX queues */
2880 dma_ctrl = bcmgenet_dma_disable(priv);
2881
2882 /* Reinitialize TDMA and RDMA and SW housekeeping */
2883 ret = bcmgenet_init_dma(priv);
2884 if (ret) {
2885 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2886 goto err_clk_disable;
1c1008c7
FF		 2887 }
2888
2889 /* Always enable ring 16 - descriptor ring */
2890 bcmgenet_enable_dma(priv, dma_ctrl);
2891
0034de41
PG		 2892 /* HFB init */
2893 bcmgenet_hfb_init(priv);
2894
1c1008c7 2895 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2896 dev->name, priv);
1c1008c7
FF		 2897 if (ret < 0) {
2898 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2899 goto err_fini_dma;
2900 }
2901
2902 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2903 dev->name, priv);
1c1008c7
FF		 2904 if (ret < 0) {
2905 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2906 goto err_irq0;
2907 }
2908
6cc8e6d4
FF		 2909 ret = bcmgenet_mii_probe(dev);
2910 if (ret) {
2911 netdev_err(dev, "failed to connect to PHY\n");
2912 goto err_irq1;
2913 }
c96e731c 2914
909ff5ef 2915 bcmgenet_netif_start(dev);
1c1008c7
FF		 2916
2917 return 0;
2918
6cc8e6d4
FF		 2919err_irq1:
2920 free_irq(priv->irq1, priv);
1c1008c7 2921err_irq0:
978ffac4 2922 free_irq(priv->irq0, priv);
1c1008c7
FF		 2923err_fini_dma:
2924 bcmgenet_fini_dma(priv);
2925err_clk_disable:
7d5d3075 2926 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 2927 return ret;
2928}
2929
909ff5ef
FF		 2930static void bcmgenet_netif_stop(struct net_device *dev)
2931{
2932 struct bcmgenet_priv *priv = netdev_priv(dev);
2933
2934 netif_tx_stop_all_queues(dev);
62469c76 2935 phy_stop(dev->phydev);
909ff5ef 2936 bcmgenet_intr_disable(priv);
3ab11339 2937 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2938 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2939
2940 /* Wait for pending work items to complete. Since interrupts are
2941 * disabled no new work will be scheduled.
2942 */
2943 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2944
cc013fb4 2945 priv->old_link = -1;
5ad6e6c5 2946 priv->old_speed = -1;
cc013fb4 2947 priv->old_duplex = -1;
5ad6e6c5 2948 priv->old_pause = -1;
909ff5ef
FF		 2949}
2950
1c1008c7
FF		 2951static int bcmgenet_close(struct net_device *dev)
2952{
2953 struct bcmgenet_priv *priv = netdev_priv(dev);
2954 int ret;
1c1008c7
FF		 2955
2956 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2957
909ff5ef 2958 bcmgenet_netif_stop(dev);
1c1008c7 2959
c96e731c 2960 /* Really kill the PHY state machine and disconnect from it */
62469c76 2961 phy_disconnect(dev->phydev);
c96e731c 2962
1c1008c7 2963 /* Disable MAC receive */
e29585b8 2964 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2965
1c1008c7
FF		 2966 ret = bcmgenet_dma_teardown(priv);
2967 if (ret)
2968 return ret;
2969
2970 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2971 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2972
1c1008c7
FF		 2973 /* tx reclaim */
2974 bcmgenet_tx_reclaim_all(dev);
2975 bcmgenet_fini_dma(priv);
2976
2977 free_irq(priv->irq0, priv);
2978 free_irq(priv->irq1, priv);
2979
c624f891 2980 if (priv->internal_phy)
ca8cf341 2981 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2982
7d5d3075 2983 clk_disable_unprepare(priv->clk);
1c1008c7 2984
ca8cf341 2985 return ret;
1c1008c7
FF		 2986}
2987
13ea6578
FF		 2988static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2989{
2990 struct bcmgenet_priv *priv = ring->priv;
2991 u32 p_index, c_index, intsts, intmsk;
2992 struct netdev_queue *txq;
2993 unsigned int free_bds;
2994 unsigned long flags;
2995 bool txq_stopped;
2996
2997 if (!netif_msg_tx_err(priv))
2998 return;
2999
3000 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3001
3002 spin_lock_irqsave(&ring->lock, flags);
3003 if (ring->index == DESC_INDEX) {
3004 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3005 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3006 } else {
3007 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3008 intmsk = 1 << ring->index;
3009 }
3010 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3011 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3012 txq_stopped = netif_tx_queue_stopped(txq);
3013 free_bds = ring->free_bds;
3014 spin_unlock_irqrestore(&ring->lock, flags);
3015
3016 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3017 "TX queue status: %s, interrupts: %s\n"
3018 "(sw)free_bds: %d (sw)size: %d\n"
3019 "(sw)p_index: %d (hw)p_index: %d\n"
3020 "(sw)c_index: %d (hw)c_index: %d\n"
3021 "(sw)clean_p: %d (sw)write_p: %d\n"
3022 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3023 ring->index, ring->queue,
3024 txq_stopped ? "stopped" : "active",
3025 intsts & intmsk ? "enabled" : "disabled",
3026 free_bds, ring->size,
3027 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3028 ring->c_index, c_index & DMA_C_INDEX_MASK,
3029 ring->clean_ptr, ring->write_ptr,
3030 ring->cb_ptr, ring->end_ptr);
3031}
3032
1c1008c7
FF		 3033static void bcmgenet_timeout(struct net_device *dev)
3034{
3035 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3036 u32 int0_enable = 0;
3037 u32 int1_enable = 0;
3038 unsigned int q;
1c1008c7
FF		 3039
3040 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3041
13ea6578
FF		 3042 for (q = 0; q < priv->hw_params->tx_queues; q++)
3043 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3044 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3045
3046 bcmgenet_tx_reclaim_all(dev);
3047
3048 for (q = 0; q < priv->hw_params->tx_queues; q++)
3049 int1_enable |= (1 << q);
3050
3051 int0_enable = UMAC_IRQ_TXDMA_DONE;
3052
3053 /* Re-enable TX interrupts if disabled */
3054 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3055 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3056
860e9538 3057 netif_trans_update(dev);
1c1008c7
FF		 3058
3059 dev->stats.tx_errors++;
3060
3061 netif_tx_wake_all_queues(dev);
3062}
3063
3064#define MAX_MC_COUNT 16
3065
3066static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3067 unsigned char *addr,
3068 int *i,
3069 int *mc)
3070{
3071 u32 reg;
3072
c91b7f66
FF		 3073 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3074 UMAC_MDF_ADDR + (*i * 4));
3075 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3076 addr[4] << 8 | addr[5],
3077 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 3078 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3079 reg |= (1 << (MAX_MC_COUNT - *mc));
3080 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3081 *i += 2;
3082 (*mc)++;
3083}
3084
3085static void bcmgenet_set_rx_mode(struct net_device *dev)
3086{
3087 struct bcmgenet_priv *priv = netdev_priv(dev);
3088 struct netdev_hw_addr *ha;
3089 int i, mc;
3090 u32 reg;
3091
3092 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3093
7fc527f9 3094 /* Promiscuous mode */
1c1008c7
FF		 3095 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3096 if (dev->flags & IFF_PROMISC) {
3097 reg |= CMD_PROMISC;
3098 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3099 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3100 return;
3101 } else {
3102 reg &= ~CMD_PROMISC;
3103 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3104 }
3105
3106 /* UniMac doesn't support ALLMULTI */
3107 if (dev->flags & IFF_ALLMULTI) {
3108 netdev_warn(dev, "ALLMULTI is not supported\n");
3109 return;
3110 }
3111
3112 /* update MDF filter */
3113 i = 0;
3114 mc = 0;
3115 /* Broadcast */
3116 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3117 /* my own address.*/
3118 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3119 /* Unicast list*/
3120 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3121 return;
3122
3123 if (!netdev_uc_empty(dev))
3124 netdev_for_each_uc_addr(ha, dev)
3125 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3126 /* Multicast */
3127 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3128 return;
3129
3130 netdev_for_each_mc_addr(ha, dev)
3131 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3132}
3133
3134/* Set the hardware MAC address. */
3135static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3136{
3137 struct sockaddr *addr = p;
3138
3139 /* Setting the MAC address at the hardware level is not possible
3140 * without disabling the UniMAC RX/TX enable bits.
3141 */
3142 if (netif_running(dev))
3143 return -EBUSY;
3144
3145 ether_addr_copy(dev->dev_addr, addr->sa_data);
3146
3147 return 0;
3148}
3149
1c1008c7
FF		 3150static const struct net_device_ops bcmgenet_netdev_ops = {
3151 .ndo_open = bcmgenet_open,
3152 .ndo_stop = bcmgenet_close,
3153 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3154 .ndo_tx_timeout = bcmgenet_timeout,
3155 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3156 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3157 .ndo_do_ioctl = bcmgenet_ioctl,
3158 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3159#ifdef CONFIG_NET_POLL_CONTROLLER
3160 .ndo_poll_controller = bcmgenet_poll_controller,
3161#endif
1c1008c7
FF		 3162};
3163
3164/* Array of GENET hardware parameters/characteristics */
3165static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3166 [GENET_V1] = {
3167 .tx_queues = 0,
51a966a7 3168 .tx_bds_per_q = 0,
1c1008c7 3169 .rx_queues = 0,
3feafa02 3170 .rx_bds_per_q = 0,
1c1008c7
FF		 3171 .bp_in_en_shift = 16,
3172 .bp_in_mask = 0xffff,
3173 .hfb_filter_cnt = 16,
3174 .qtag_mask = 0x1F,
3175 .hfb_offset = 0x1000,
3176 .rdma_offset = 0x2000,
3177 .tdma_offset = 0x3000,
3178 .words_per_bd = 2,
3179 },
3180 [GENET_V2] = {
3181 .tx_queues = 4,
51a966a7 3182 .tx_bds_per_q = 32,
7e906e02 3183 .rx_queues = 0,
3feafa02 3184 .rx_bds_per_q = 0,
1c1008c7
FF		 3185 .bp_in_en_shift = 16,
3186 .bp_in_mask = 0xffff,
3187 .hfb_filter_cnt = 16,
3188 .qtag_mask = 0x1F,
3189 .tbuf_offset = 0x0600,
3190 .hfb_offset = 0x1000,
3191 .hfb_reg_offset = 0x2000,
3192 .rdma_offset = 0x3000,
3193 .tdma_offset = 0x4000,
3194 .words_per_bd = 2,
3195 .flags = GENET_HAS_EXT,
3196 },
3197 [GENET_V3] = {
3198 .tx_queues = 4,
51a966a7 3199 .tx_bds_per_q = 32,
7e906e02 3200 .rx_queues = 0,
3feafa02 3201 .rx_bds_per_q = 0,
1c1008c7
FF		 3202 .bp_in_en_shift = 17,
3203 .bp_in_mask = 0x1ffff,
3204 .hfb_filter_cnt = 48,
0034de41 3205 .hfb_filter_size = 128,
1c1008c7
FF		 3206 .qtag_mask = 0x3F,
3207 .tbuf_offset = 0x0600,
3208 .hfb_offset = 0x8000,
3209 .hfb_reg_offset = 0xfc00,
3210 .rdma_offset = 0x10000,
3211 .tdma_offset = 0x11000,
3212 .words_per_bd = 2,
8d88c6eb
PG		 3213 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3214 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3215 },
3216 [GENET_V4] = {
3217 .tx_queues = 4,
51a966a7 3218 .tx_bds_per_q = 32,
7e906e02 3219 .rx_queues = 0,
3feafa02 3220 .rx_bds_per_q = 0,
1c1008c7
FF		 3221 .bp_in_en_shift = 17,
3222 .bp_in_mask = 0x1ffff,
3223 .hfb_filter_cnt = 48,
0034de41 3224 .hfb_filter_size = 128,
1c1008c7
FF		 3225 .qtag_mask = 0x3F,
3226 .tbuf_offset = 0x0600,
3227 .hfb_offset = 0x8000,
3228 .hfb_reg_offset = 0xfc00,
3229 .rdma_offset = 0x2000,
3230 .tdma_offset = 0x4000,
3231 .words_per_bd = 3,
8d88c6eb
PG		 3232 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3233 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3234 },
3235};
3236
3237/* Infer hardware parameters from the detected GENET version */
3238static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3239{
3240 struct bcmgenet_hw_params *params;
3241 u32 reg;
3242 u8 major;
b04a2f5b 3243 u16 gphy_rev;
1c1008c7
FF		 3244
3245 if (GENET_IS_V4(priv)) {
3246 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3247 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3248 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3249 priv->version = GENET_V4;
3250 } else if (GENET_IS_V3(priv)) {
3251 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3252 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3253 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3254 priv->version = GENET_V3;
3255 } else if (GENET_IS_V2(priv)) {
3256 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3257 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3258 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3259 priv->version = GENET_V2;
3260 } else if (GENET_IS_V1(priv)) {
3261 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3262 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3263 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3264 priv->version = GENET_V1;
3265 }
3266
3267 /* enum genet_version starts at 1 */
3268 priv->hw_params = &bcmgenet_hw_params[priv->version];
3269 params = priv->hw_params;
3270
3271 /* Read GENET HW version */
3272 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3273 major = (reg >> 24 & 0x0f);
3274 if (major == 5)
3275 major = 4;
3276 else if (major == 0)
3277 major = 1;
3278 if (major != priv->version) {
3279 dev_err(&priv->pdev->dev,
3280 "GENET version mismatch, got: %d, configured for: %d\n",
3281 major, priv->version);
3282 }
3283
3284 /* Print the GENET core version */
3285 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3286 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3287
487320c5
FF		 3288 /* Store the integrated PHY revision for the MDIO probing function
3289 * to pass this information to the PHY driver. The PHY driver expects
3290 * to find the PHY major revision in bits 15:8 while the GENET register
3291 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3292 *
3293 * On newer chips, starting with PHY revision G0, a new scheme is
3294 * deployed similar to the Starfighter 2 switch with GPHY major
3295 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3296 * is reserved as well as special value 0x01ff, we have a small
3297 * heuristic to check for the new GPHY revision and re-arrange things
3298 * so the GPHY driver is happy.
487320c5 3299 */
b04a2f5b
FF		 3300 gphy_rev = reg & 0xffff;
3301
3302 /* This is the good old scheme, just GPHY major, no minor nor patch */
3303 if ((gphy_rev & 0xf0) != 0)
3304 priv->gphy_rev = gphy_rev << 8;
3305
3306 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3307 else if ((gphy_rev & 0xff00) != 0)
3308 priv->gphy_rev = gphy_rev;
3309
3310 /* This is reserved so should require special treatment */
3311 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3312 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3313 return;
3314 }
487320c5 3315
1c1008c7
FF		 3316#ifdef CONFIG_PHYS_ADDR_T_64BIT
3317 if (!(params->flags & GENET_HAS_40BITS))
3318 pr_warn("GENET does not support 40-bits PA\n");
3319#endif
3320
3321 pr_debug("Configuration for version: %d\n"
3feafa02 3322 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3323 "BP << en: %2d, BP msk: 0x%05x\n"
3324 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3325 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3326 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3327 "Words/BD: %d\n",
3328 priv->version,
51a966a7 3329 params->tx_queues, params->tx_bds_per_q,
3feafa02 3330 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3331 params->bp_in_en_shift, params->bp_in_mask,
3332 params->hfb_filter_cnt, params->qtag_mask,
3333 params->tbuf_offset, params->hfb_offset,
3334 params->hfb_reg_offset,
3335 params->rdma_offset, params->tdma_offset,
3336 params->words_per_bd);
3337}
3338
3339static const struct of_device_id bcmgenet_match[] = {
3340 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3341 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3342 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3343 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3344 { },
3345};
e8048e55 3346MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3347
3348static int bcmgenet_probe(struct platform_device *pdev)
3349{
b0ba512e 3350 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3351 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3352 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3353 struct bcmgenet_priv *priv;
3354 struct net_device *dev;
3355 const void *macaddr;
3356 struct resource *r;
3357 int err = -EIO;
3358
3feafeed
PG		 3359 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3360 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3361 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3362 if (!dev) {
3363 dev_err(&pdev->dev, "can't allocate net device\n");
3364 return -ENOMEM;
3365 }
3366
b0ba512e
PG		 3367 if (dn) {
3368 of_id = of_match_node(bcmgenet_match, dn);
3369 if (!of_id)
3370 return -EINVAL;
3371 }
1c1008c7
FF		 3372
3373 priv = netdev_priv(dev);
3374 priv->irq0 = platform_get_irq(pdev, 0);
3375 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3376 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3377 if (!priv->irq0 || !priv->irq1) {
3378 dev_err(&pdev->dev, "can't find IRQs\n");
3379 err = -EINVAL;
3380 goto err;
3381 }
3382
b0ba512e
PG		 3383 if (dn) {
3384 macaddr = of_get_mac_address(dn);
3385 if (!macaddr) {
3386 dev_err(&pdev->dev, "can't find MAC address\n");
3387 err = -EINVAL;
3388 goto err;
3389 }
3390 } else {
3391 macaddr = pd->mac_address;
1c1008c7
FF		 3392 }
3393
3394 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3395 priv->base = devm_ioremap_resource(&pdev->dev, r);
3396 if (IS_ERR(priv->base)) {
3397 err = PTR_ERR(priv->base);
1c1008c7
FF		 3398 goto err;
3399 }
3400
3401 SET_NETDEV_DEV(dev, &pdev->dev);
3402 dev_set_drvdata(&pdev->dev, dev);
3403 ether_addr_copy(dev->dev_addr, macaddr);
3404 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3405 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3406 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3407
3408 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3409
3410 /* Set hardware features */
3411 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3412 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3413
8562056f
FF		 3414 /* Request the WOL interrupt and advertise suspend if available */
3415 priv->wol_irq_disabled = true;
3416 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3417 dev->name, priv);
3418 if (!err)
3419 device_set_wakeup_capable(&pdev->dev, 1);
3420
1c1008c7
FF		 3421 /* Set the needed headroom to account for any possible
3422 * features enabling/disabling at runtime
3423 */
3424 dev->needed_headroom += 64;
3425
3426 netdev_boot_setup_check(dev);
3427
3428 priv->dev = dev;
3429 priv->pdev = pdev;
b0ba512e
PG		 3430 if (of_id)
3431 priv->version = (enum bcmgenet_version)of_id->data;
3432 else
3433 priv->version = pd->genet_version;
1c1008c7 3434
e4a60a93 3435 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
7d5d3075 3436 if (IS_ERR(priv->clk)) {
e4a60a93 3437 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
7d5d3075
FF		 3438 priv->clk = NULL;
3439 }
e4a60a93 3440
7d5d3075 3441 clk_prepare_enable(priv->clk);
e4a60a93 3442
1c1008c7
FF		 3443 bcmgenet_set_hw_params(priv);
3444
1c1008c7
FF		 3445 /* Mii wait queue */
3446 init_waitqueue_head(&priv->wq);
3447 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3448 priv->rx_buf_len = RX_BUF_LENGTH;
3449 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3450
1c1008c7 3451 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
7d5d3075 3452 if (IS_ERR(priv->clk_wol)) {
1c1008c7 3453 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
7d5d3075
FF		 3454 priv->clk_wol = NULL;
3455 }
1c1008c7 3456
6ef398ea
FF		 3457 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3458 if (IS_ERR(priv->clk_eee)) {
3459 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3460 priv->clk_eee = NULL;
3461 }
3462
1c1008c7
FF		 3463 err = reset_umac(priv);
3464 if (err)
3465 goto err_clk_disable;
3466
3467 err = bcmgenet_mii_init(dev);
3468 if (err)
3469 goto err_clk_disable;
3470
3471 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3472 * just the ring 16 descriptor based TX
3473 */
3474 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3475 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3476
219575eb
FF		 3477 /* libphy will determine the link state */
3478 netif_carrier_off(dev);
3479
1c1008c7 3480 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 3481 clk_disable_unprepare(priv->clk);
1c1008c7 3482
0f50ce96
FF		 3483 err = register_netdev(dev);
3484 if (err)
3485 goto err;
3486
1c1008c7
FF		 3487 return err;
3488
3489err_clk_disable:
7d5d3075 3490 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3491err:
3492 free_netdev(dev);
3493 return err;
3494}
3495
3496static int bcmgenet_remove(struct platform_device *pdev)
3497{
3498 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3499
3500 dev_set_drvdata(&pdev->dev, NULL);
3501 unregister_netdev(priv->dev);
3502 bcmgenet_mii_exit(priv->dev);
3503 free_netdev(priv->dev);
3504
3505 return 0;
3506}
3507
b6e978e5
FF		 3508#ifdef CONFIG_PM_SLEEP
3509static int bcmgenet_suspend(struct device *d)
3510{
3511 struct net_device *dev = dev_get_drvdata(d);
3512 struct bcmgenet_priv *priv = netdev_priv(dev);
3513 int ret;
3514
3515 if (!netif_running(dev))
3516 return 0;
3517
3518 bcmgenet_netif_stop(dev);
3519
62469c76 3520 phy_suspend(dev->phydev);
cc013fb4 3521
b6e978e5
FF		 3522 netif_device_detach(dev);
3523
3524 /* Disable MAC receive */
3525 umac_enable_set(priv, CMD_RX_EN, false);
3526
3527 ret = bcmgenet_dma_teardown(priv);
3528 if (ret)
3529 return ret;
3530
3531 /* Disable MAC transmit. TX DMA disabled have to done before this */
3532 umac_enable_set(priv, CMD_TX_EN, false);
3533
3534 /* tx reclaim */
3535 bcmgenet_tx_reclaim_all(dev);
3536 bcmgenet_fini_dma(priv);
3537
8c90db72
FF		 3538 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3539 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3540 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3541 clk_prepare_enable(priv->clk_wol);
c624f891 3542 } else if (priv->internal_phy) {
a6f31f5e 3543 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3544 }
3545
b6e978e5
FF		 3546 /* Turn off the clocks */
3547 clk_disable_unprepare(priv->clk);
3548
ca8cf341 3549 return ret;
b6e978e5
FF		 3550}
3551
3552static int bcmgenet_resume(struct device *d)
3553{
3554 struct net_device *dev = dev_get_drvdata(d);
3555 struct bcmgenet_priv *priv = netdev_priv(dev);
3556 unsigned long dma_ctrl;
3557 int ret;
3558 u32 reg;
3559
3560 if (!netif_running(dev))
3561 return 0;
3562
3563 /* Turn on the clock */
3564 ret = clk_prepare_enable(priv->clk);
3565 if (ret)
3566 return ret;
3567
a6f31f5e
FF		 3568 /* If this is an internal GPHY, power it back on now, before UniMAC is
3569 * brought out of reset as absolutely no UniMAC activity is allowed
3570 */
c624f891 3571 if (priv->internal_phy)
a6f31f5e
FF		 3572 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3573
b6e978e5
FF		 3574 bcmgenet_umac_reset(priv);
3575
3576 ret = init_umac(priv);
3577 if (ret)
3578 goto out_clk_disable;
3579
0a29b3da
TK		 3580 /* From WOL-enabled suspend, switch to regular clock */
3581 if (priv->wolopts)
3582 clk_disable_unprepare(priv->clk_wol);
3583
62469c76 3584 phy_init_hw(dev->phydev);
0a29b3da 3585 /* Speed settings must be restored */
28b45910 3586 bcmgenet_mii_config(priv->dev);
8c90db72 3587
b6e978e5
FF		 3588 /* disable ethernet MAC while updating its registers */
3589 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3590
3591 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3592
c624f891 3593 if (priv->internal_phy) {
b6e978e5
FF		 3594 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3595 reg |= EXT_ENERGY_DET_MASK;
3596 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3597 }
3598
98bb7399
FF		 3599 if (priv->wolopts)
3600 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3601
b6e978e5
FF		 3602 /* Disable RX/TX DMA and flush TX queues */
3603 dma_ctrl = bcmgenet_dma_disable(priv);
3604
3605 /* Reinitialize TDMA and RDMA and SW housekeeping */
3606 ret = bcmgenet_init_dma(priv);
3607 if (ret) {
3608 netdev_err(dev, "failed to initialize DMA\n");
3609 goto out_clk_disable;
3610 }
3611
3612 /* Always enable ring 16 - descriptor ring */
3613 bcmgenet_enable_dma(priv, dma_ctrl);
3614
3615 netif_device_attach(dev);
3616
62469c76 3617 phy_resume(dev->phydev);
cc013fb4 3618
6ef398ea
FF		 3619 if (priv->eee.eee_enabled)
3620 bcmgenet_eee_enable_set(dev, true);
3621
b6e978e5
FF		 3622 bcmgenet_netif_start(dev);
3623
3624 return 0;
3625
3626out_clk_disable:
3627 clk_disable_unprepare(priv->clk);
3628 return ret;
3629}
3630#endif /* CONFIG_PM_SLEEP */
3631
3632static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3633
1c1008c7
FF		 3634static struct platform_driver bcmgenet_driver = {
3635 .probe = bcmgenet_probe,
3636 .remove = bcmgenet_remove,
3637 .driver = {
3638 .name = "bcmgenet",
1c1008c7 3639 .of_match_table = bcmgenet_match,
b6e978e5 3640 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3641 },
3642};
3643module_platform_driver(bcmgenet_driver);
3644
3645MODULE_AUTHOR("Broadcom Corporation");
3646MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3647MODULE_ALIAS("platform:bcmgenet");
3648MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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