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net/mlx4_core: Fix backward compatibility on VFs
[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
4a29645b
FF		 208 DMA_RING0_TIMEOUT,
209 DMA_RING1_TIMEOUT,
210 DMA_RING2_TIMEOUT,
211 DMA_RING3_TIMEOUT,
212 DMA_RING4_TIMEOUT,
213 DMA_RING5_TIMEOUT,
214 DMA_RING6_TIMEOUT,
215 DMA_RING7_TIMEOUT,
216 DMA_RING8_TIMEOUT,
217 DMA_RING9_TIMEOUT,
218 DMA_RING10_TIMEOUT,
219 DMA_RING11_TIMEOUT,
220 DMA_RING12_TIMEOUT,
221 DMA_RING13_TIMEOUT,
222 DMA_RING14_TIMEOUT,
223 DMA_RING15_TIMEOUT,
224 DMA_RING16_TIMEOUT,
1c1008c7
FF		 225};
226
227static const u8 bcmgenet_dma_regs_v3plus[] = {
228 [DMA_RING_CFG] = 0x00,
229 [DMA_CTRL] = 0x04,
230 [DMA_STATUS] = 0x08,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 233 [DMA_PRIORITY_0] = 0x30,
234 [DMA_PRIORITY_1] = 0x34,
235 [DMA_PRIORITY_2] = 0x38,
4a29645b
FF		 236 [DMA_RING0_TIMEOUT] = 0x2C,
237 [DMA_RING1_TIMEOUT] = 0x30,
238 [DMA_RING2_TIMEOUT] = 0x34,
239 [DMA_RING3_TIMEOUT] = 0x38,
240 [DMA_RING4_TIMEOUT] = 0x3c,
241 [DMA_RING5_TIMEOUT] = 0x40,
242 [DMA_RING6_TIMEOUT] = 0x44,
243 [DMA_RING7_TIMEOUT] = 0x48,
244 [DMA_RING8_TIMEOUT] = 0x4c,
245 [DMA_RING9_TIMEOUT] = 0x50,
246 [DMA_RING10_TIMEOUT] = 0x54,
247 [DMA_RING11_TIMEOUT] = 0x58,
248 [DMA_RING12_TIMEOUT] = 0x5c,
249 [DMA_RING13_TIMEOUT] = 0x60,
250 [DMA_RING14_TIMEOUT] = 0x64,
251 [DMA_RING15_TIMEOUT] = 0x68,
252 [DMA_RING16_TIMEOUT] = 0x6C,
0034de41
PG		 253 [DMA_INDEX2RING_0] = 0x70,
254 [DMA_INDEX2RING_1] = 0x74,
255 [DMA_INDEX2RING_2] = 0x78,
256 [DMA_INDEX2RING_3] = 0x7C,
257 [DMA_INDEX2RING_4] = 0x80,
258 [DMA_INDEX2RING_5] = 0x84,
259 [DMA_INDEX2RING_6] = 0x88,
260 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 261};
262
263static const u8 bcmgenet_dma_regs_v2[] = {
264 [DMA_RING_CFG] = 0x00,
265 [DMA_CTRL] = 0x04,
266 [DMA_STATUS] = 0x08,
267 [DMA_SCB_BURST_SIZE] = 0x0C,
268 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 269 [DMA_PRIORITY_0] = 0x34,
270 [DMA_PRIORITY_1] = 0x38,
271 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 272 [DMA_RING0_TIMEOUT] = 0x2C,
273 [DMA_RING1_TIMEOUT] = 0x30,
274 [DMA_RING2_TIMEOUT] = 0x34,
275 [DMA_RING3_TIMEOUT] = 0x38,
276 [DMA_RING4_TIMEOUT] = 0x3c,
277 [DMA_RING5_TIMEOUT] = 0x40,
278 [DMA_RING6_TIMEOUT] = 0x44,
279 [DMA_RING7_TIMEOUT] = 0x48,
280 [DMA_RING8_TIMEOUT] = 0x4c,
281 [DMA_RING9_TIMEOUT] = 0x50,
282 [DMA_RING10_TIMEOUT] = 0x54,
283 [DMA_RING11_TIMEOUT] = 0x58,
284 [DMA_RING12_TIMEOUT] = 0x5c,
285 [DMA_RING13_TIMEOUT] = 0x60,
286 [DMA_RING14_TIMEOUT] = 0x64,
287 [DMA_RING15_TIMEOUT] = 0x68,
288 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 289};
290
291static const u8 bcmgenet_dma_regs_v1[] = {
292 [DMA_CTRL] = 0x00,
293 [DMA_STATUS] = 0x04,
294 [DMA_SCB_BURST_SIZE] = 0x0C,
295 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 296 [DMA_PRIORITY_0] = 0x34,
297 [DMA_PRIORITY_1] = 0x38,
298 [DMA_PRIORITY_2] = 0x3C,
4a29645b
FF		 299 [DMA_RING0_TIMEOUT] = 0x2C,
300 [DMA_RING1_TIMEOUT] = 0x30,
301 [DMA_RING2_TIMEOUT] = 0x34,
302 [DMA_RING3_TIMEOUT] = 0x38,
303 [DMA_RING4_TIMEOUT] = 0x3c,
304 [DMA_RING5_TIMEOUT] = 0x40,
305 [DMA_RING6_TIMEOUT] = 0x44,
306 [DMA_RING7_TIMEOUT] = 0x48,
307 [DMA_RING8_TIMEOUT] = 0x4c,
308 [DMA_RING9_TIMEOUT] = 0x50,
309 [DMA_RING10_TIMEOUT] = 0x54,
310 [DMA_RING11_TIMEOUT] = 0x58,
311 [DMA_RING12_TIMEOUT] = 0x5c,
312 [DMA_RING13_TIMEOUT] = 0x60,
313 [DMA_RING14_TIMEOUT] = 0x64,
314 [DMA_RING15_TIMEOUT] = 0x68,
315 [DMA_RING16_TIMEOUT] = 0x6C,
1c1008c7
FF		 316};
317
318/* Set at runtime once bcmgenet version is known */
319static const u8 *bcmgenet_dma_regs;
320
321static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322{
323 return netdev_priv(dev_get_drvdata(dev));
324}
325
326static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 327 enum dma_reg r)
1c1008c7
FF		 328{
329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331}
332
333static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334 u32 val, enum dma_reg r)
335{
336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338}
339
340static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 341 enum dma_reg r)
1c1008c7
FF		 342{
343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345}
346
347static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348 u32 val, enum dma_reg r)
349{
350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352}
353
354/* RDMA/TDMA ring registers and accessors
355 * we merge the common fields and just prefix with T/D the registers
356 * having different meaning depending on the direction
357 */
358enum dma_ring_reg {
359 TDMA_READ_PTR = 0,
360 RDMA_WRITE_PTR = TDMA_READ_PTR,
361 TDMA_READ_PTR_HI,
362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363 TDMA_CONS_INDEX,
364 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365 TDMA_PROD_INDEX,
366 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367 DMA_RING_BUF_SIZE,
368 DMA_START_ADDR,
369 DMA_START_ADDR_HI,
370 DMA_END_ADDR,
371 DMA_END_ADDR_HI,
372 DMA_MBUF_DONE_THRESH,
373 TDMA_FLOW_PERIOD,
374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375 TDMA_WRITE_PTR,
376 RDMA_READ_PTR = TDMA_WRITE_PTR,
377 TDMA_WRITE_PTR_HI,
378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379};
380
381/* GENET v4 supports 40-bits pointer addressing
382 * for obvious reasons the LO and HI word parts
383 * are contiguous, but this offsets the other
384 * registers.
385 */
386static const u8 genet_dma_ring_regs_v4[] = {
387 [TDMA_READ_PTR] = 0x00,
388 [TDMA_READ_PTR_HI] = 0x04,
389 [TDMA_CONS_INDEX] = 0x08,
390 [TDMA_PROD_INDEX] = 0x0C,
391 [DMA_RING_BUF_SIZE] = 0x10,
392 [DMA_START_ADDR] = 0x14,
393 [DMA_START_ADDR_HI] = 0x18,
394 [DMA_END_ADDR] = 0x1C,
395 [DMA_END_ADDR_HI] = 0x20,
396 [DMA_MBUF_DONE_THRESH] = 0x24,
397 [TDMA_FLOW_PERIOD] = 0x28,
398 [TDMA_WRITE_PTR] = 0x2C,
399 [TDMA_WRITE_PTR_HI] = 0x30,
400};
401
402static const u8 genet_dma_ring_regs_v123[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_CONS_INDEX] = 0x04,
405 [TDMA_PROD_INDEX] = 0x08,
406 [DMA_RING_BUF_SIZE] = 0x0C,
407 [DMA_START_ADDR] = 0x10,
408 [DMA_END_ADDR] = 0x14,
409 [DMA_MBUF_DONE_THRESH] = 0x18,
410 [TDMA_FLOW_PERIOD] = 0x1C,
411 [TDMA_WRITE_PTR] = 0x20,
412};
413
414/* Set at runtime once GENET version is known */
415static const u8 *genet_dma_ring_regs;
416
417static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 418 unsigned int ring,
419 enum dma_ring_reg r)
1c1008c7
FF		 420{
421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424}
425
426static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 427 unsigned int ring, u32 val,
428 enum dma_ring_reg r)
1c1008c7
FF		 429{
430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433}
434
435static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 436 unsigned int ring,
437 enum dma_ring_reg r)
1c1008c7
FF		 438{
439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442}
443
444static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 445 unsigned int ring, u32 val,
446 enum dma_ring_reg r)
1c1008c7
FF		 447{
448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451}
452
453static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 454 struct ethtool_cmd *cmd)
1c1008c7
FF		 455{
456 struct bcmgenet_priv *priv = netdev_priv(dev);
457
458 if (!netif_running(dev))
459 return -EINVAL;
460
461 if (!priv->phydev)
462 return -ENODEV;
463
464 return phy_ethtool_gset(priv->phydev, cmd);
465}
466
467static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 468 struct ethtool_cmd *cmd)
1c1008c7
FF		 469{
470 struct bcmgenet_priv *priv = netdev_priv(dev);
471
472 if (!netif_running(dev))
473 return -EINVAL;
474
475 if (!priv->phydev)
476 return -ENODEV;
477
478 return phy_ethtool_sset(priv->phydev, cmd);
479}
480
481static int bcmgenet_set_rx_csum(struct net_device *dev,
482 netdev_features_t wanted)
483{
484 struct bcmgenet_priv *priv = netdev_priv(dev);
485 u32 rbuf_chk_ctrl;
486 bool rx_csum_en;
487
488 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
489
490 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
491
492 /* enable rx checksumming */
493 if (rx_csum_en)
494 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
495 else
496 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
497 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 498
499 /* If UniMAC forwards CRC, we need to skip over it to get
500 * a valid CHK bit to be set in the per-packet status word
501 */
502 if (rx_csum_en && priv->crc_fwd_en)
503 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
504 else
505 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
506
1c1008c7
FF		 507 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
508
509 return 0;
510}
511
512static int bcmgenet_set_tx_csum(struct net_device *dev,
513 netdev_features_t wanted)
514{
515 struct bcmgenet_priv *priv = netdev_priv(dev);
516 bool desc_64b_en;
517 u32 tbuf_ctrl, rbuf_ctrl;
518
519 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
520 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
521
522 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
523
524 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
525 if (desc_64b_en) {
526 tbuf_ctrl |= RBUF_64B_EN;
527 rbuf_ctrl |= RBUF_64B_EN;
528 } else {
529 tbuf_ctrl &= ~RBUF_64B_EN;
530 rbuf_ctrl &= ~RBUF_64B_EN;
531 }
532 priv->desc_64b_en = desc_64b_en;
533
534 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
535 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
536
537 return 0;
538}
539
540static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 541 netdev_features_t features)
1c1008c7
FF		 542{
543 netdev_features_t changed = features ^ dev->features;
544 netdev_features_t wanted = dev->wanted_features;
545 int ret = 0;
546
547 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
548 ret = bcmgenet_set_tx_csum(dev, wanted);
549 if (changed & (NETIF_F_RXCSUM))
550 ret = bcmgenet_set_rx_csum(dev, wanted);
551
552 return ret;
553}
554
555static u32 bcmgenet_get_msglevel(struct net_device *dev)
556{
557 struct bcmgenet_priv *priv = netdev_priv(dev);
558
559 return priv->msg_enable;
560}
561
562static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
563{
564 struct bcmgenet_priv *priv = netdev_priv(dev);
565
566 priv->msg_enable = level;
567}
568
2f913070
FF		 569static int bcmgenet_get_coalesce(struct net_device *dev,
570 struct ethtool_coalesce *ec)
571{
572 struct bcmgenet_priv *priv = netdev_priv(dev);
573
574 ec->tx_max_coalesced_frames =
575 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
576 DMA_MBUF_DONE_THRESH);
4a29645b
FF		 577 ec->rx_max_coalesced_frames =
578 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
579 DMA_MBUF_DONE_THRESH);
580 ec->rx_coalesce_usecs =
581 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
2f913070
FF		 582
583 return 0;
584}
585
586static int bcmgenet_set_coalesce(struct net_device *dev,
587 struct ethtool_coalesce *ec)
588{
589 struct bcmgenet_priv *priv = netdev_priv(dev);
590 unsigned int i;
4a29645b 591 u32 reg;
2f913070 592
4a29645b
FF		 593 /* Base system clock is 125Mhz, DMA timeout is this reference clock
594 * divided by 1024, which yields roughly 8.192us, our maximum value
595 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
596 */
2f913070 597 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
4a29645b
FF		 598 ec->tx_max_coalesced_frames == 0 ||
599 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
600 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
601 return -EINVAL;
602
603 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
2f913070
FF		 604 return -EINVAL;
605
606 /* GENET TDMA hardware does not support a configurable timeout, but will
607 * always generate an interrupt either after MBDONE packets have been
608 * transmitted, or when the ring is emtpy.
609 */
610 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
852bcafb 611 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
2f913070
FF		 612 return -EOPNOTSUPP;
613
614 /* Program all TX queues with the same values, as there is no
615 * ethtool knob to do coalescing on a per-queue basis
616 */
617 for (i = 0; i < priv->hw_params->tx_queues; i++)
618 bcmgenet_tdma_ring_writel(priv, i,
619 ec->tx_max_coalesced_frames,
620 DMA_MBUF_DONE_THRESH);
621 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
622 ec->tx_max_coalesced_frames,
623 DMA_MBUF_DONE_THRESH);
624
4a29645b
FF		 625 for (i = 0; i < priv->hw_params->rx_queues; i++) {
626 bcmgenet_rdma_ring_writel(priv, i,
627 ec->rx_max_coalesced_frames,
628 DMA_MBUF_DONE_THRESH);
629
630 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
631 reg &= ~DMA_TIMEOUT_MASK;
632 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
633 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
634 }
635
636 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
637 ec->rx_max_coalesced_frames,
638 DMA_MBUF_DONE_THRESH);
639
640 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
641 reg &= ~DMA_TIMEOUT_MASK;
642 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
643 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
644
2f913070
FF		 645 return 0;
646}
647
1c1008c7
FF		 648/* standard ethtool support functions. */
649enum bcmgenet_stat_type {
650 BCMGENET_STAT_NETDEV = -1,
651 BCMGENET_STAT_MIB_RX,
652 BCMGENET_STAT_MIB_TX,
653 BCMGENET_STAT_RUNT,
654 BCMGENET_STAT_MISC,
f62ba9c1 655 BCMGENET_STAT_SOFT,
1c1008c7
FF		 656};
657
658struct bcmgenet_stats {
659 char stat_string[ETH_GSTRING_LEN];
660 int stat_sizeof;
661 int stat_offset;
662 enum bcmgenet_stat_type type;
663 /* reg offset from UMAC base for misc counters */
664 u16 reg_offset;
665};
666
667#define STAT_NETDEV(m) { \
668 .stat_string = __stringify(m), \
669 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
670 .stat_offset = offsetof(struct net_device_stats, m), \
671 .type = BCMGENET_STAT_NETDEV, \
672}
673
674#define STAT_GENET_MIB(str, m, _type) { \
675 .stat_string = str, \
676 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
677 .stat_offset = offsetof(struct bcmgenet_priv, m), \
678 .type = _type, \
679}
680
681#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
682#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
683#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 684#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 685
686#define STAT_GENET_MISC(str, m, offset) { \
687 .stat_string = str, \
688 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
689 .stat_offset = offsetof(struct bcmgenet_priv, m), \
690 .type = BCMGENET_STAT_MISC, \
691 .reg_offset = offset, \
692}
693
694
695/* There is a 0xC gap between the end of RX and beginning of TX stats and then
696 * between the end of TX stats and the beginning of the RX RUNT
697 */
698#define BCMGENET_STAT_OFFSET 0xc
699
700/* Hardware counters must be kept in sync because the order/offset
701 * is important here (order in structure declaration = order in hardware)
702 */
703static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
704 /* general stats */
705 STAT_NETDEV(rx_packets),
706 STAT_NETDEV(tx_packets),
707 STAT_NETDEV(rx_bytes),
708 STAT_NETDEV(tx_bytes),
709 STAT_NETDEV(rx_errors),
710 STAT_NETDEV(tx_errors),
711 STAT_NETDEV(rx_dropped),
712 STAT_NETDEV(tx_dropped),
713 STAT_NETDEV(multicast),
714 /* UniMAC RSV counters */
715 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
716 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
717 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
718 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
719 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
720 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
721 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
722 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
723 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
724 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
725 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
726 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
727 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
728 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
729 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
730 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
731 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
732 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
733 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
734 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
735 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
736 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
737 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
738 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
739 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
740 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
741 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
742 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
743 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
744 /* UniMAC TSV counters */
745 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
746 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
747 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
748 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
749 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
750 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
751 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
752 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
753 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
754 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
755 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
756 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
757 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
758 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
759 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
760 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
761 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
762 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
763 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
764 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
765 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
766 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
767 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
768 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
769 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
770 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
771 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
772 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
773 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
774 /* UniMAC RUNT counters */
775 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
776 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
777 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
778 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
779 /* Misc UniMAC counters */
780 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
781 UMAC_RBUF_OVFL_CNT),
782 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
783 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 784 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
785 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
786 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 787};
788
789#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
790
791static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 792 struct ethtool_drvinfo *info)
1c1008c7
FF		 793{
794 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
795 strlcpy(info->version, "v2.0", sizeof(info->version));
1c1008c7
FF		 796}
797
798static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
799{
800 switch (string_set) {
801 case ETH_SS_STATS:
802 return BCMGENET_STATS_LEN;
803 default:
804 return -EOPNOTSUPP;
805 }
806}
807
c91b7f66
FF		 808static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
809 u8 *data)
1c1008c7
FF		 810{
811 int i;
812
813 switch (stringset) {
814 case ETH_SS_STATS:
815 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
816 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 817 bcmgenet_gstrings_stats[i].stat_string,
818 ETH_GSTRING_LEN);
1c1008c7
FF		 819 }
820 break;
821 }
822}
823
824static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
825{
826 int i, j = 0;
827
828 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
829 const struct bcmgenet_stats *s;
830 u8 offset = 0;
831 u32 val = 0;
832 char *p;
833
834 s = &bcmgenet_gstrings_stats[i];
835 switch (s->type) {
836 case BCMGENET_STAT_NETDEV:
f62ba9c1 837 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 838 continue;
839 case BCMGENET_STAT_MIB_RX:
840 case BCMGENET_STAT_MIB_TX:
841 case BCMGENET_STAT_RUNT:
842 if (s->type != BCMGENET_STAT_MIB_RX)
843 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 844 val = bcmgenet_umac_readl(priv,
845 UMAC_MIB_START + j + offset);
1c1008c7
FF		 846 break;
847 case BCMGENET_STAT_MISC:
848 val = bcmgenet_umac_readl(priv, s->reg_offset);
849 /* clear if overflowed */
850 if (val == ~0)
851 bcmgenet_umac_writel(priv, 0, s->reg_offset);
852 break;
853 }
854
855 j += s->stat_sizeof;
856 p = (char *)priv + s->stat_offset;
857 *(u32 *)p = val;
858 }
859}
860
861static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 862 struct ethtool_stats *stats,
863 u64 *data)
1c1008c7
FF		 864{
865 struct bcmgenet_priv *priv = netdev_priv(dev);
866 int i;
867
868 if (netif_running(dev))
869 bcmgenet_update_mib_counters(priv);
870
871 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
872 const struct bcmgenet_stats *s;
873 char *p;
874
875 s = &bcmgenet_gstrings_stats[i];
876 if (s->type == BCMGENET_STAT_NETDEV)
877 p = (char *)&dev->stats;
878 else
879 p = (char *)priv;
880 p += s->stat_offset;
881 data[i] = *(u32 *)p;
882 }
883}
884
6ef398ea
FF		 885static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
886{
887 struct bcmgenet_priv *priv = netdev_priv(dev);
888 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
889 u32 reg;
890
891 if (enable && !priv->clk_eee_enabled) {
892 clk_prepare_enable(priv->clk_eee);
893 priv->clk_eee_enabled = true;
894 }
895
896 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
897 if (enable)
898 reg |= EEE_EN;
899 else
900 reg &= ~EEE_EN;
901 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
902
903 /* Enable EEE and switch to a 27Mhz clock automatically */
904 reg = __raw_readl(priv->base + off);
905 if (enable)
906 reg |= TBUF_EEE_EN | TBUF_PM_EN;
907 else
908 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
909 __raw_writel(reg, priv->base + off);
910
911 /* Do the same for thing for RBUF */
912 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
913 if (enable)
914 reg |= RBUF_EEE_EN | RBUF_PM_EN;
915 else
916 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
917 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
918
919 if (!enable && priv->clk_eee_enabled) {
920 clk_disable_unprepare(priv->clk_eee);
921 priv->clk_eee_enabled = false;
922 }
923
924 priv->eee.eee_enabled = enable;
925 priv->eee.eee_active = enable;
926}
927
928static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
929{
930 struct bcmgenet_priv *priv = netdev_priv(dev);
931 struct ethtool_eee *p = &priv->eee;
932
933 if (GENET_IS_V1(priv))
934 return -EOPNOTSUPP;
935
936 e->eee_enabled = p->eee_enabled;
937 e->eee_active = p->eee_active;
938 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
939
940 return phy_ethtool_get_eee(priv->phydev, e);
941}
942
943static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
944{
945 struct bcmgenet_priv *priv = netdev_priv(dev);
946 struct ethtool_eee *p = &priv->eee;
947 int ret = 0;
948
949 if (GENET_IS_V1(priv))
950 return -EOPNOTSUPP;
951
952 p->eee_enabled = e->eee_enabled;
953
954 if (!p->eee_enabled) {
955 bcmgenet_eee_enable_set(dev, false);
956 } else {
957 ret = phy_init_eee(priv->phydev, 0);
958 if (ret) {
959 netif_err(priv, hw, dev, "EEE initialization failed\n");
960 return ret;
961 }
962
963 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
964 bcmgenet_eee_enable_set(dev, true);
965 }
966
967 return phy_ethtool_set_eee(priv->phydev, e);
968}
969
6b0c5406
FF		 970static int bcmgenet_nway_reset(struct net_device *dev)
971{
972 struct bcmgenet_priv *priv = netdev_priv(dev);
973
974 return genphy_restart_aneg(priv->phydev);
975}
976
1c1008c7
FF		 977/* standard ethtool support functions. */
978static struct ethtool_ops bcmgenet_ethtool_ops = {
979 .get_strings = bcmgenet_get_strings,
980 .get_sset_count = bcmgenet_get_sset_count,
981 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
982 .get_settings = bcmgenet_get_settings,
983 .set_settings = bcmgenet_set_settings,
984 .get_drvinfo = bcmgenet_get_drvinfo,
985 .get_link = ethtool_op_get_link,
986 .get_msglevel = bcmgenet_get_msglevel,
987 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 988 .get_wol = bcmgenet_get_wol,
989 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 990 .get_eee = bcmgenet_get_eee,
991 .set_eee = bcmgenet_set_eee,
6b0c5406 992 .nway_reset = bcmgenet_nway_reset,
2f913070
FF		 993 .get_coalesce = bcmgenet_get_coalesce,
994 .set_coalesce = bcmgenet_set_coalesce,
1c1008c7
FF		 995};
996
997/* Power down the unimac, based on mode. */
ca8cf341 998static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 999 enum bcmgenet_power_mode mode)
1000{
ca8cf341 1001 int ret = 0;
1c1008c7
FF		 1002 u32 reg;
1003
1004 switch (mode) {
1005 case GENET_POWER_CABLE_SENSE:
80d8e96d 1006 phy_detach(priv->phydev);
1c1008c7
FF		 1007 break;
1008
c3ae64ae 1009 case GENET_POWER_WOL_MAGIC:
ca8cf341 1010 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 1011 break;
1012
1c1008c7
FF		 1013 case GENET_POWER_PASSIVE:
1014 /* Power down LED */
1c1008c7
FF		 1015 if (priv->hw_params->flags & GENET_HAS_EXT) {
1016 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1017 reg |= (EXT_PWR_DOWN_PHY |
1018 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1019 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
a642c4f7
FF		 1020
1021 bcmgenet_phy_power_set(priv->dev, false);
1c1008c7
FF		 1022 }
1023 break;
1024 default:
1025 break;
1026 }
ca8cf341
FF		 1027
1028 return 0;
1c1008c7
FF		 1029}
1030
1031static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 1032 enum bcmgenet_power_mode mode)
1c1008c7
FF		 1033{
1034 u32 reg;
1035
1036 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1037 return;
1038
1039 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1040
1041 switch (mode) {
1042 case GENET_POWER_PASSIVE:
1043 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1044 EXT_PWR_DOWN_BIAS);
1045 /* fallthrough */
1046 case GENET_POWER_CABLE_SENSE:
1047 /* enable APD */
1048 reg |= EXT_PWR_DN_EN_LD;
1049 break;
c3ae64ae
FF		 1050 case GENET_POWER_WOL_MAGIC:
1051 bcmgenet_wol_power_up_cfg(priv, mode);
1052 return;
1c1008c7
FF		 1053 default:
1054 break;
1055 }
1056
1057 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
5dbebbb4 1058 if (mode == GENET_POWER_PASSIVE) {
bd4060a6 1059 bcmgenet_phy_power_set(priv->dev, true);
5dbebbb4
FF		 1060 bcmgenet_mii_reset(priv->dev);
1061 }
1c1008c7
FF		 1062}
1063
1064/* ioctl handle special commands that are not present in ethtool. */
1065static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1066{
1067 struct bcmgenet_priv *priv = netdev_priv(dev);
1068 int val = 0;
1069
1070 if (!netif_running(dev))
1071 return -EINVAL;
1072
1073 switch (cmd) {
1074 case SIOCGMIIPHY:
1075 case SIOCGMIIREG:
1076 case SIOCSMIIREG:
1077 if (!priv->phydev)
1078 val = -ENODEV;
1079 else
1080 val = phy_mii_ioctl(priv->phydev, rq, cmd);
1081 break;
1082
1083 default:
1084 val = -EINVAL;
1085 break;
1086 }
1087
1088 return val;
1089}
1090
1091static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1092 struct bcmgenet_tx_ring *ring)
1093{
1094 struct enet_cb *tx_cb_ptr;
1095
1096 tx_cb_ptr = ring->cbs;
1097 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 1098
1c1008c7
FF		 1099 /* Advancing local write pointer */
1100 if (ring->write_ptr == ring->end_ptr)
1101 ring->write_ptr = ring->cb_ptr;
1102 else
1103 ring->write_ptr++;
1104
1105 return tx_cb_ptr;
1106}
1107
1108/* Simple helper to free a control block's resources */
1109static void bcmgenet_free_cb(struct enet_cb *cb)
1110{
1111 dev_kfree_skb_any(cb->skb);
1112 cb->skb = NULL;
1113 dma_unmap_addr_set(cb, dma_addr, 0);
1114}
1115
4055eaef
PG		 1116static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1117{
ee7d8c20 1118 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1119 INTRL2_CPU_MASK_SET);
1120}
1121
1122static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1123{
ee7d8c20 1124 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
4055eaef
PG		 1125 INTRL2_CPU_MASK_CLEAR);
1126}
1127
1128static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1129{
1130 bcmgenet_intrl2_1_writel(ring->priv,
1131 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1132 INTRL2_CPU_MASK_SET);
1133}
1134
1135static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1136{
1137 bcmgenet_intrl2_1_writel(ring->priv,
1138 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1139 INTRL2_CPU_MASK_CLEAR);
1140}
1141
9dbac28f 1142static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1143{
ee7d8c20 1144 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1145 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1146}
1147
9dbac28f 1148static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1149{
ee7d8c20 1150 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
c91b7f66 1151 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1152}
1153
9dbac28f 1154static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1c1008c7 1155{
9dbac28f 1156 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1157 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 1158}
1159
9dbac28f 1160static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1c1008c7 1161{
9dbac28f 1162 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
c91b7f66 1163 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 1164}
1165
1166/* Unlocked version of the reclaim routine */
4092e6ac
JS		 1167static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1168 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1169{
1170 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1171 struct enet_cb *tx_cb_ptr;
b2cde2cc 1172 struct netdev_queue *txq;
4092e6ac 1173 unsigned int pkts_compl = 0;
1c1008c7 1174 unsigned int c_index;
66d06757
PG		 1175 unsigned int txbds_ready;
1176 unsigned int txbds_processed = 0;
1c1008c7 1177
7fc527f9 1178 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1179 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1180 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1181
66d06757
PG		 1182 if (likely(c_index >= ring->c_index))
1183 txbds_ready = c_index - ring->c_index;
1c1008c7 1184 else
66d06757 1185 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1186
1187 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1188 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1189 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1190
1191 /* Reclaim transmitted buffers */
66d06757
PG		 1192 while (txbds_processed < txbds_ready) {
1193 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1194 if (tx_cb_ptr->skb) {
4092e6ac 1195 pkts_compl++;
66d06757 1196 dev->stats.tx_packets++;
1c1008c7
FF		 1197 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1198 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1199 dma_unmap_addr(tx_cb_ptr, dma_addr),
1200 tx_cb_ptr->skb->len,
1201 DMA_TO_DEVICE);
1c1008c7
FF		 1202 bcmgenet_free_cb(tx_cb_ptr);
1203 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1204 dev->stats.tx_bytes +=
1205 dma_unmap_len(tx_cb_ptr, dma_len);
1206 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1207 dma_unmap_addr(tx_cb_ptr, dma_addr),
1208 dma_unmap_len(tx_cb_ptr, dma_len),
1209 DMA_TO_DEVICE);
1c1008c7
FF		 1210 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1211 }
1c1008c7 1212
66d06757
PG		 1213 txbds_processed++;
1214 if (likely(ring->clean_ptr < ring->end_ptr))
1215 ring->clean_ptr++;
1216 else
1217 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1218 }
1219
66d06757
PG		 1220 ring->free_bds += txbds_processed;
1221 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1222
4092e6ac 1223 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1224 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1225 if (netif_tx_queue_stopped(txq))
1226 netif_tx_wake_queue(txq);
1227 }
1c1008c7 1228
4092e6ac 1229 return pkts_compl;
1c1008c7
FF		 1230}
1231
4092e6ac 1232static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1233 struct bcmgenet_tx_ring *ring)
1c1008c7 1234{
4092e6ac 1235 unsigned int released;
1c1008c7
FF		 1236 unsigned long flags;
1237
1238 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1239 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1240 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1241
1242 return released;
1243}
1244
1245static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1246{
1247 struct bcmgenet_tx_ring *ring =
1248 container_of(napi, struct bcmgenet_tx_ring, napi);
1249 unsigned int work_done = 0;
1250
1251 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1252
1253 if (work_done == 0) {
1254 napi_complete(napi);
9dbac28f 1255 ring->int_enable(ring);
4092e6ac
JS		 1256
1257 return 0;
1258 }
1259
1260 return budget;
1c1008c7
FF		 1261}
1262
1263static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1264{
1265 struct bcmgenet_priv *priv = netdev_priv(dev);
1266 int i;
1267
1268 if (netif_is_multiqueue(dev)) {
1269 for (i = 0; i < priv->hw_params->tx_queues; i++)
1270 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1271 }
1272
1273 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1274}
1275
1276/* Transmits a single SKB (either head of a fragment or a single SKB)
1277 * caller must hold priv->lock
1278 */
1279static int bcmgenet_xmit_single(struct net_device *dev,
1280 struct sk_buff *skb,
1281 u16 dma_desc_flags,
1282 struct bcmgenet_tx_ring *ring)
1283{
1284 struct bcmgenet_priv *priv = netdev_priv(dev);
1285 struct device *kdev = &priv->pdev->dev;
1286 struct enet_cb *tx_cb_ptr;
1287 unsigned int skb_len;
1288 dma_addr_t mapping;
1289 u32 length_status;
1290 int ret;
1291
1292 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1293
1294 if (unlikely(!tx_cb_ptr))
1295 BUG();
1296
1297 tx_cb_ptr->skb = skb;
1298
1299 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1300
1301 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1302 ret = dma_mapping_error(kdev, mapping);
1303 if (ret) {
44c8bc3c 1304 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1305 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1306 dev_kfree_skb(skb);
1307 return ret;
1308 }
1309
1310 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1311 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1312 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1313 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1314 DMA_TX_APPEND_CRC;
1315
1316 if (skb->ip_summed == CHECKSUM_PARTIAL)
1317 length_status |= DMA_TX_DO_CSUM;
1318
1319 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1320
1c1008c7
FF		 1321 return 0;
1322}
1323
7fc527f9 1324/* Transmit a SKB fragment */
1c1008c7 1325static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1326 skb_frag_t *frag,
1327 u16 dma_desc_flags,
1328 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1329{
1330 struct bcmgenet_priv *priv = netdev_priv(dev);
1331 struct device *kdev = &priv->pdev->dev;
1332 struct enet_cb *tx_cb_ptr;
1333 dma_addr_t mapping;
1334 int ret;
1335
1336 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1337
1338 if (unlikely(!tx_cb_ptr))
1339 BUG();
1340 tx_cb_ptr->skb = NULL;
1341
1342 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1343 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1344 ret = dma_mapping_error(kdev, mapping);
1345 if (ret) {
44c8bc3c 1346 priv->mib.tx_dma_failed++;
1c1008c7 1347 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1348 __func__);
1c1008c7
FF		 1349 return ret;
1350 }
1351
1352 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1353 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1354
1355 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1356 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1357 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1358
1c1008c7
FF		 1359 return 0;
1360}
1361
1362/* Reallocate the SKB to put enough headroom in front of it and insert
1363 * the transmit checksum offsets in the descriptors
1364 */
bc23333b
PG		 1365static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1366 struct sk_buff *skb)
1c1008c7
FF		 1367{
1368 struct status_64 *status = NULL;
1369 struct sk_buff *new_skb;
1370 u16 offset;
1371 u8 ip_proto;
1372 u16 ip_ver;
1373 u32 tx_csum_info;
1374
1375 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1376 /* If 64 byte status block enabled, must make sure skb has
1377 * enough headroom for us to insert 64B status block.
1378 */
1379 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1380 dev_kfree_skb(skb);
1381 if (!new_skb) {
1c1008c7 1382 dev->stats.tx_dropped++;
bc23333b 1383 return NULL;
1c1008c7
FF		 1384 }
1385 skb = new_skb;
1386 }
1387
1388 skb_push(skb, sizeof(*status));
1389 status = (struct status_64 *)skb->data;
1390
1391 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1392 ip_ver = htons(skb->protocol);
1393 switch (ip_ver) {
1394 case ETH_P_IP:
1395 ip_proto = ip_hdr(skb)->protocol;
1396 break;
1397 case ETH_P_IPV6:
1398 ip_proto = ipv6_hdr(skb)->nexthdr;
1399 break;
1400 default:
bc23333b 1401 return skb;
1c1008c7
FF		 1402 }
1403
1404 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1405 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1406 (offset + skb->csum_offset);
1407
1408 /* Set the length valid bit for TCP and UDP and just set
1409 * the special UDP flag for IPv4, else just set to 0.
1410 */
1411 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1412 tx_csum_info |= STATUS_TX_CSUM_LV;
1413 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1414 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1415 } else {
1c1008c7 1416 tx_csum_info = 0;
8900ea57 1417 }
1c1008c7
FF		 1418
1419 status->tx_csum_info = tx_csum_info;
1420 }
1421
bc23333b 1422 return skb;
1c1008c7
FF		 1423}
1424
1425static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1426{
1427 struct bcmgenet_priv *priv = netdev_priv(dev);
1428 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1429 struct netdev_queue *txq;
1c1008c7
FF		 1430 unsigned long flags = 0;
1431 int nr_frags, index;
1432 u16 dma_desc_flags;
1433 int ret;
1434 int i;
1435
1436 index = skb_get_queue_mapping(skb);
1437 /* Mapping strategy:
1438 * queue_mapping = 0, unclassified, packet xmited through ring16
1439 * queue_mapping = 1, goes to ring 0. (highest priority queue
1440 * queue_mapping = 2, goes to ring 1.
1441 * queue_mapping = 3, goes to ring 2.
1442 * queue_mapping = 4, goes to ring 3.
1443 */
1444 if (index == 0)
1445 index = DESC_INDEX;
1446 else
1447 index -= 1;
1448
1c1008c7
FF		 1449 nr_frags = skb_shinfo(skb)->nr_frags;
1450 ring = &priv->tx_rings[index];
b2cde2cc 1451 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1452
1453 spin_lock_irqsave(&ring->lock, flags);
1454 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1455 netif_tx_stop_queue(txq);
1c1008c7 1456 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1457 __func__, index, ring->queue);
1c1008c7
FF		 1458 ret = NETDEV_TX_BUSY;
1459 goto out;
1460 }
1461
474ea9ca
FF		 1462 if (skb_padto(skb, ETH_ZLEN)) {
1463 ret = NETDEV_TX_OK;
1464 goto out;
1465 }
1466
1c1008c7
FF		 1467 /* set the SKB transmit checksum */
1468 if (priv->desc_64b_en) {
bc23333b
PG		 1469 skb = bcmgenet_put_tx_csum(dev, skb);
1470 if (!skb) {
1c1008c7
FF		 1471 ret = NETDEV_TX_OK;
1472 goto out;
1473 }
1474 }
1475
1476 dma_desc_flags = DMA_SOP;
1477 if (nr_frags == 0)
1478 dma_desc_flags |= DMA_EOP;
1479
1480 /* Transmit single SKB or head of fragment list */
1481 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1482 if (ret) {
1483 ret = NETDEV_TX_OK;
1484 goto out;
1485 }
1486
1487 /* xmit fragment */
1488 for (i = 0; i < nr_frags; i++) {
1489 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1490 &skb_shinfo(skb)->frags[i],
1491 (i == nr_frags - 1) ? DMA_EOP : 0,
1492 ring);
1c1008c7
FF		 1493 if (ret) {
1494 ret = NETDEV_TX_OK;
1495 goto out;
1496 }
1497 }
1498
d03825fb
FF		 1499 skb_tx_timestamp(skb);
1500
ae67bf01
FF		 1501 /* Decrement total BD count and advance our write pointer */
1502 ring->free_bds -= nr_frags + 1;
1503 ring->prod_index += nr_frags + 1;
1504 ring->prod_index &= DMA_P_INDEX_MASK;
1505
4092e6ac 1506 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1507 netif_tx_stop_queue(txq);
1c1008c7 1508
ddd0ca5d
FF		 1509 if (!skb->xmit_more || netif_xmit_stopped(txq))
1510 /* Packets are ready, update producer index */
1511 bcmgenet_tdma_ring_writel(priv, ring->index,
1512 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1513out:
1514 spin_unlock_irqrestore(&ring->lock, flags);
1515
1516 return ret;
1517}
1518
d6707bec
PG		 1519static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1520 struct enet_cb *cb)
1c1008c7
FF		 1521{
1522 struct device *kdev = &priv->pdev->dev;
1523 struct sk_buff *skb;
d6707bec 1524 struct sk_buff *rx_skb;
1c1008c7 1525 dma_addr_t mapping;
1c1008c7 1526
d6707bec 1527 /* Allocate a new Rx skb */
c91b7f66 1528 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1529 if (!skb) {
1530 priv->mib.alloc_rx_buff_failed++;
1531 netif_err(priv, rx_err, priv->dev,
1532 "%s: Rx skb allocation failed\n", __func__);
1533 return NULL;
1534 }
1c1008c7 1535
d6707bec
PG		 1536 /* DMA-map the new Rx skb */
1537 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1538 DMA_FROM_DEVICE);
1539 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1540 priv->mib.rx_dma_failed++;
d6707bec 1541 dev_kfree_skb_any(skb);
1c1008c7 1542 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1543 "%s: Rx skb DMA mapping failed\n", __func__);
1544 return NULL;
1c1008c7
FF		 1545 }
1546
d6707bec
PG		 1547 /* Grab the current Rx skb from the ring and DMA-unmap it */
1548 rx_skb = cb->skb;
1549 if (likely(rx_skb))
1550 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1551 priv->rx_buf_len, DMA_FROM_DEVICE);
1552
1553 /* Put the new Rx skb on the ring */
1554 cb->skb = skb;
1c1008c7 1555 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1556 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1557
d6707bec
PG		 1558 /* Return the current Rx skb to caller */
1559 return rx_skb;
1c1008c7
FF		 1560}
1561
1562/* bcmgenet_desc_rx - descriptor based rx process.
1563 * this could be called from bottom half, or from NAPI polling method.
1564 */
4055eaef 1565static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1c1008c7
FF		 1566 unsigned int budget)
1567{
4055eaef 1568 struct bcmgenet_priv *priv = ring->priv;
1c1008c7
FF		 1569 struct net_device *dev = priv->dev;
1570 struct enet_cb *cb;
1571 struct sk_buff *skb;
1572 u32 dma_length_status;
1573 unsigned long dma_flag;
d6707bec 1574 int len;
1c1008c7
FF		 1575 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1576 unsigned int p_index;
d26ea6cc 1577 unsigned int discards;
1c1008c7
FF		 1578 unsigned int chksum_ok = 0;
1579
4055eaef 1580 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1581
1582 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1583 DMA_P_INDEX_DISCARD_CNT_MASK;
1584 if (discards > ring->old_discards) {
1585 discards = discards - ring->old_discards;
1586 dev->stats.rx_missed_errors += discards;
1587 dev->stats.rx_errors += discards;
1588 ring->old_discards += discards;
1589
1590 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1591 if (ring->old_discards >= 0xC000) {
1592 ring->old_discards = 0;
4055eaef 1593 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
d26ea6cc
PG		 1594 RDMA_PROD_INDEX);
1595 }
1596 }
1597
1c1008c7
FF		 1598 p_index &= DMA_P_INDEX_MASK;
1599
8ac467e8
PG		 1600 if (likely(p_index >= ring->c_index))
1601 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1602 else
8ac467e8
PG		 1603 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1604 p_index;
1c1008c7
FF		 1605
1606 netif_dbg(priv, rx_status, dev,
c91b7f66 1607 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1608
1609 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1610 (rxpktprocessed < budget)) {
8ac467e8 1611 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1612 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1613
b629be5c
FF		 1614 if (unlikely(!skb)) {
1615 dev->stats.rx_dropped++;
d6707bec 1616 goto next;
b629be5c
FF		 1617 }
1618
1c1008c7 1619 if (!priv->desc_64b_en) {
c91b7f66 1620 dma_length_status =
8ac467e8 1621 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1622 } else {
1623 struct status_64 *status;
164d4f20 1624
1c1008c7
FF		 1625 status = (struct status_64 *)skb->data;
1626 dma_length_status = status->length_status;
1627 }
1628
1629 /* DMA flags and length are still valid no matter how
1630 * we got the Receive Status Vector (64B RSB or register)
1631 */
1632 dma_flag = dma_length_status & 0xffff;
1633 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1634
1635 netif_dbg(priv, rx_status, dev,
c91b7f66 1636 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1637 __func__, p_index, ring->c_index,
1638 ring->read_ptr, dma_length_status);
1c1008c7 1639
1c1008c7
FF		 1640 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1641 netif_err(priv, rx_status, dev,
c91b7f66 1642 "dropping fragmented packet!\n");
1c1008c7 1643 dev->stats.rx_errors++;
d6707bec
PG		 1644 dev_kfree_skb_any(skb);
1645 goto next;
1c1008c7 1646 }
d6707bec 1647
1c1008c7
FF		 1648 /* report errors */
1649 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1650 DMA_RX_OV |
1651 DMA_RX_NO |
1652 DMA_RX_LG |
1653 DMA_RX_RXER))) {
1654 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1655 (unsigned int)dma_flag);
1c1008c7
FF		 1656 if (dma_flag & DMA_RX_CRC_ERROR)
1657 dev->stats.rx_crc_errors++;
1658 if (dma_flag & DMA_RX_OV)
1659 dev->stats.rx_over_errors++;
1660 if (dma_flag & DMA_RX_NO)
1661 dev->stats.rx_frame_errors++;
1662 if (dma_flag & DMA_RX_LG)
1663 dev->stats.rx_length_errors++;
1c1008c7 1664 dev->stats.rx_errors++;
d6707bec
PG		 1665 dev_kfree_skb_any(skb);
1666 goto next;
1c1008c7
FF		 1667 } /* error packet */
1668
1669 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1670 priv->desc_rxchk_en;
1c1008c7
FF		 1671
1672 skb_put(skb, len);
1673 if (priv->desc_64b_en) {
1674 skb_pull(skb, 64);
1675 len -= 64;
1676 }
1677
1678 if (likely(chksum_ok))
1679 skb->ip_summed = CHECKSUM_UNNECESSARY;
1680
1681 /* remove hardware 2bytes added for IP alignment */
1682 skb_pull(skb, 2);
1683 len -= 2;
1684
1685 if (priv->crc_fwd_en) {
1686 skb_trim(skb, len - ETH_FCS_LEN);
1687 len -= ETH_FCS_LEN;
1688 }
1689
1690 /*Finish setting up the received SKB and send it to the kernel*/
1691 skb->protocol = eth_type_trans(skb, priv->dev);
1692 dev->stats.rx_packets++;
1693 dev->stats.rx_bytes += len;
1694 if (dma_flag & DMA_RX_MULT)
1695 dev->stats.multicast++;
1696
1697 /* Notify kernel */
4055eaef 1698 napi_gro_receive(&ring->napi, skb);
1c1008c7
FF		 1699 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1700
d6707bec 1701next:
cf377d88 1702 rxpktprocessed++;
8ac467e8
PG		 1703 if (likely(ring->read_ptr < ring->end_ptr))
1704 ring->read_ptr++;
1705 else
1706 ring->read_ptr = ring->cb_ptr;
1707
1708 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
4055eaef 1709 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1710 }
1711
1712 return rxpktprocessed;
1713}
1714
3ab11339
PG		 1715/* Rx NAPI polling method */
1716static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1717{
4055eaef
PG		 1718 struct bcmgenet_rx_ring *ring = container_of(napi,
1719 struct bcmgenet_rx_ring, napi);
3ab11339
PG		 1720 unsigned int work_done;
1721
4055eaef 1722 work_done = bcmgenet_desc_rx(ring, budget);
3ab11339
PG		 1723
1724 if (work_done < budget) {
1725 napi_complete(napi);
4055eaef 1726 ring->int_enable(ring);
3ab11339
PG		 1727 }
1728
1729 return work_done;
1730}
1731
1c1008c7 1732/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1733static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1734 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1735{
1736 struct enet_cb *cb;
d6707bec 1737 struct sk_buff *skb;
1c1008c7
FF		 1738 int i;
1739
8ac467e8 1740 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1741
1742 /* loop here for each buffer needing assign */
8ac467e8
PG		 1743 for (i = 0; i < ring->size; i++) {
1744 cb = ring->cbs + i;
d6707bec
PG		 1745 skb = bcmgenet_rx_refill(priv, cb);
1746 if (skb)
1747 dev_kfree_skb_any(skb);
1748 if (!cb->skb)
1749 return -ENOMEM;
1c1008c7
FF		 1750 }
1751
d6707bec 1752 return 0;
1c1008c7
FF		 1753}
1754
1755static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1756{
1757 struct enet_cb *cb;
1758 int i;
1759
1760 for (i = 0; i < priv->num_rx_bds; i++) {
1761 cb = &priv->rx_cbs[i];
1762
1763 if (dma_unmap_addr(cb, dma_addr)) {
1764 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1765 dma_unmap_addr(cb, dma_addr),
1766 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1767 dma_unmap_addr_set(cb, dma_addr, 0);
1768 }
1769
1770 if (cb->skb)
1771 bcmgenet_free_cb(cb);
1772 }
1773}
1774
c91b7f66 1775static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1776{
1777 u32 reg;
1778
1779 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1780 if (enable)
1781 reg |= mask;
1782 else
1783 reg &= ~mask;
1784 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1785
1786 /* UniMAC stops on a packet boundary, wait for a full-size packet
1787 * to be processed
1788 */
1789 if (enable == 0)
1790 usleep_range(1000, 2000);
1791}
1792
1c1008c7
FF		 1793static int reset_umac(struct bcmgenet_priv *priv)
1794{
1795 struct device *kdev = &priv->pdev->dev;
1796 unsigned int timeout = 0;
1797 u32 reg;
1798
1799 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1800 bcmgenet_rbuf_ctrl_set(priv, 0);
1801 udelay(10);
1802
1803 /* disable MAC while updating its registers */
1804 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1805
1806 /* issue soft reset, wait for it to complete */
1807 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1808 while (timeout++ < 1000) {
1809 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1810 if (!(reg & CMD_SW_RESET))
1811 return 0;
1812
1813 udelay(1);
1814 }
1815
1816 if (timeout == 1000) {
1817 dev_err(kdev,
7fc527f9 1818 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1819 return -ETIMEDOUT;
1820 }
1821
1822 return 0;
1823}
1824
909ff5ef
FF		 1825static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1826{
1827 /* Mask all interrupts.*/
1828 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1829 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1830 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1831 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1832 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1833 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1834}
1835
37850e37
FF		 1836static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1837{
1838 u32 int0_enable = 0;
1839
1840 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1841 * and MoCA PHY
1842 */
1843 if (priv->internal_phy) {
1844 int0_enable |= UMAC_IRQ_LINK_EVENT;
1845 } else if (priv->ext_phy) {
1846 int0_enable |= UMAC_IRQ_LINK_EVENT;
1847 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1848 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1849 int0_enable |= UMAC_IRQ_LINK_EVENT;
1850 }
1851 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1852}
1853
1c1008c7
FF		 1854static int init_umac(struct bcmgenet_priv *priv)
1855{
1856 struct device *kdev = &priv->pdev->dev;
1857 int ret;
b2e97eca
PG		 1858 u32 reg;
1859 u32 int0_enable = 0;
1860 u32 int1_enable = 0;
1861 int i;
1c1008c7
FF		 1862
1863 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1864
1865 ret = reset_umac(priv);
1866 if (ret)
1867 return ret;
1868
1869 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1870 /* clear tx/rx counter */
1871 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1872 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1873 UMAC_MIB_CTRL);
1c1008c7
FF		 1874 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1875
1876 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1877
1878 /* init rx registers, enable ip header optimization */
1879 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1880 reg |= RBUF_ALIGN_2B;
1881 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1882
1883 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1884 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1885
909ff5ef 1886 bcmgenet_intr_disable(priv);
1c1008c7 1887
b2e97eca 1888 /* Enable Rx default queue 16 interrupts */
ee7d8c20 1889 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1c1008c7 1890
b2e97eca 1891 /* Enable Tx default queue 16 interrupts */
ee7d8c20 1892 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1c1008c7 1893
37850e37
FF		 1894 /* Configure backpressure vectors for MoCA */
1895 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1896 reg = bcmgenet_bp_mc_get(priv);
1897 reg |= BIT(priv->hw_params->bp_in_en_shift);
1898
1899 /* bp_mask: back pressure mask */
1900 if (netif_is_multiqueue(priv->dev))
1901 reg |= priv->hw_params->bp_in_mask;
1902 else
1903 reg &= ~priv->hw_params->bp_in_mask;
1904 bcmgenet_bp_mc_set(priv, reg);
1905 }
1906
1907 /* Enable MDIO interrupts on GENET v3+ */
1908 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
b2e97eca 1909 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1c1008c7 1910
4055eaef
PG		 1911 /* Enable Rx priority queue interrupts */
1912 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1913 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1914
b2e97eca
PG		 1915 /* Enable Tx priority queue interrupts */
1916 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1917 int1_enable |= (1 << i);
1c1008c7 1918
b2e97eca
PG		 1919 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1920 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
4092e6ac 1921
1c1008c7
FF		 1922 /* Enable rx/tx engine.*/
1923 dev_dbg(kdev, "done init umac\n");
1924
1925 return 0;
1926}
1927
4f8b2d7d 1928/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1929static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1930 unsigned int index, unsigned int size,
4f8b2d7d 1931 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1932{
1933 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1934 u32 words_per_bd = WORDS_PER_BD(priv);
1935 u32 flow_period_val = 0;
1c1008c7
FF		 1936
1937 spin_lock_init(&ring->lock);
4092e6ac 1938 ring->priv = priv;
1c1008c7
FF		 1939 ring->index = index;
1940 if (index == DESC_INDEX) {
1941 ring->queue = 0;
1942 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1943 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1944 } else {
1945 ring->queue = index + 1;
1946 ring->int_enable = bcmgenet_tx_ring_int_enable;
1947 ring->int_disable = bcmgenet_tx_ring_int_disable;
1948 }
4f8b2d7d 1949 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1950 ring->size = size;
66d06757 1951 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1952 ring->c_index = 0;
1953 ring->free_bds = size;
4f8b2d7d
PG		 1954 ring->write_ptr = start_ptr;
1955 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1956 ring->end_ptr = end_ptr - 1;
1957 ring->prod_index = 0;
1958
1959 /* Set flow period for ring != 16 */
1960 if (index != DESC_INDEX)
1961 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1962
1963 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1964 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1965 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1966 /* Disable rate control for now */
1967 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1968 TDMA_FLOW_PERIOD);
1c1008c7 1969 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1970 ((size << DMA_RING_SIZE_SHIFT) |
1971 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1972
1c1008c7 1973 /* Set start and end address, read and write pointers */
4f8b2d7d 1974 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1975 DMA_START_ADDR);
4f8b2d7d 1976 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1977 TDMA_READ_PTR);
4f8b2d7d 1978 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1979 TDMA_WRITE_PTR);
1c1008c7 1980 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1981 DMA_END_ADDR);
1c1008c7
FF		 1982}
1983
1984/* Initialize a RDMA ring */
1985static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1986 unsigned int index, unsigned int size,
1987 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1988{
8ac467e8 1989 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1990 u32 words_per_bd = WORDS_PER_BD(priv);
1991 int ret;
1992
4055eaef 1993 ring->priv = priv;
8ac467e8 1994 ring->index = index;
4055eaef
PG		 1995 if (index == DESC_INDEX) {
1996 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1997 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1998 } else {
1999 ring->int_enable = bcmgenet_rx_ring_int_enable;
2000 ring->int_disable = bcmgenet_rx_ring_int_disable;
2001 }
8ac467e8
PG		 2002 ring->cbs = priv->rx_cbs + start_ptr;
2003 ring->size = size;
2004 ring->c_index = 0;
2005 ring->read_ptr = start_ptr;
2006 ring->cb_ptr = start_ptr;
2007 ring->end_ptr = end_ptr - 1;
1c1008c7 2008
8ac467e8
PG		 2009 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2010 if (ret)
1c1008c7 2011 return ret;
1c1008c7 2012
1c1008c7
FF		 2013 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2014 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 2015 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 2016 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2017 ((size << DMA_RING_SIZE_SHIFT) |
2018 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 2019 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 2020 (DMA_FC_THRESH_LO <<
2021 DMA_XOFF_THRESHOLD_SHIFT) |
2022 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 2023
2024 /* Set start and end address, read and write pointers */
8ac467e8
PG		 2025 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2026 DMA_START_ADDR);
2027 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2028 RDMA_READ_PTR);
2029 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2030 RDMA_WRITE_PTR);
2031 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 2032 DMA_END_ADDR);
1c1008c7
FF		 2033
2034 return ret;
2035}
2036
e2aadb4a
PG		 2037static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2038{
2039 unsigned int i;
2040 struct bcmgenet_tx_ring *ring;
2041
2042 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2043 ring = &priv->tx_rings[i];
d64b5e85 2044 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2045 }
2046
2047 ring = &priv->tx_rings[DESC_INDEX];
d64b5e85 2048 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
e2aadb4a
PG		 2049}
2050
2051static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2052{
2053 unsigned int i;
2054 struct bcmgenet_tx_ring *ring;
2055
2056 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2057 ring = &priv->tx_rings[i];
2058 napi_enable(&ring->napi);
2059 }
2060
2061 ring = &priv->tx_rings[DESC_INDEX];
2062 napi_enable(&ring->napi);
2063}
2064
2065static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2066{
2067 unsigned int i;
2068 struct bcmgenet_tx_ring *ring;
2069
2070 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2071 ring = &priv->tx_rings[i];
2072 napi_disable(&ring->napi);
2073 }
2074
2075 ring = &priv->tx_rings[DESC_INDEX];
2076 napi_disable(&ring->napi);
2077}
2078
2079static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2080{
2081 unsigned int i;
2082 struct bcmgenet_tx_ring *ring;
2083
2084 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2085 ring = &priv->tx_rings[i];
2086 netif_napi_del(&ring->napi);
2087 }
2088
2089 ring = &priv->tx_rings[DESC_INDEX];
2090 netif_napi_del(&ring->napi);
2091}
2092
16c6d667 2093/* Initialize Tx queues
1c1008c7 2094 *
16c6d667 2095 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 2096 * with queue 0 being the highest priority queue.
2097 *
16c6d667 2098 * Queue 16 is the default Tx queue with
51a966a7 2099 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 2100 *
16c6d667
PG		 2101 * The transmit control block pool is then partitioned as follows:
2102 * - Tx queue 0 uses tx_cbs[0..31]
2103 * - Tx queue 1 uses tx_cbs[32..63]
2104 * - Tx queue 2 uses tx_cbs[64..95]
2105 * - Tx queue 3 uses tx_cbs[96..127]
2106 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 2107 */
16c6d667 2108static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 2109{
2110 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 2111 u32 i, dma_enable;
2112 u32 dma_ctrl, ring_cfg;
37742166 2113 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 2114
1c1008c7
FF		 2115 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2116 dma_enable = dma_ctrl & DMA_EN;
2117 dma_ctrl &= ~DMA_EN;
2118 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2119
16c6d667
PG		 2120 dma_ctrl = 0;
2121 ring_cfg = 0;
2122
1c1008c7
FF		 2123 /* Enable strict priority arbiter mode */
2124 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2125
16c6d667 2126 /* Initialize Tx priority queues */
1c1008c7 2127 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 2128 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2129 i * priv->hw_params->tx_bds_per_q,
2130 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 2131 ring_cfg |= (1 << i);
2132 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2133 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2134 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 2135 }
2136
16c6d667 2137 /* Initialize Tx default queue 16 */
51a966a7 2138 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 2139 priv->hw_params->tx_queues *
51a966a7 2140 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 2141 TOTAL_DESC);
2142 ring_cfg |= (1 << DESC_INDEX);
2143 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 2144 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2145 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2146 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 2147
2148 /* Set Tx queue priorities */
37742166
PG		 2149 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2150 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2151 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2152
e2aadb4a
PG		 2153 /* Initialize Tx NAPI */
2154 bcmgenet_init_tx_napi(priv);
2155
16c6d667
PG		 2156 /* Enable Tx queues */
2157 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 2158
16c6d667 2159 /* Enable Tx DMA */
1c1008c7 2160 if (dma_enable)
16c6d667
PG		 2161 dma_ctrl |= DMA_EN;
2162 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 2163}
2164
3ab11339
PG		 2165static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2166{
4055eaef
PG		 2167 unsigned int i;
2168 struct bcmgenet_rx_ring *ring;
2169
2170 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2171 ring = &priv->rx_rings[i];
2172 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2173 }
2174
2175 ring = &priv->rx_rings[DESC_INDEX];
2176 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
3ab11339
PG		 2177}
2178
2179static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2180{
4055eaef
PG		 2181 unsigned int i;
2182 struct bcmgenet_rx_ring *ring;
2183
2184 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2185 ring = &priv->rx_rings[i];
2186 napi_enable(&ring->napi);
2187 }
2188
2189 ring = &priv->rx_rings[DESC_INDEX];
2190 napi_enable(&ring->napi);
3ab11339
PG		 2191}
2192
2193static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2194{
4055eaef
PG		 2195 unsigned int i;
2196 struct bcmgenet_rx_ring *ring;
2197
2198 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2199 ring = &priv->rx_rings[i];
2200 napi_disable(&ring->napi);
2201 }
2202
2203 ring = &priv->rx_rings[DESC_INDEX];
2204 napi_disable(&ring->napi);
3ab11339
PG		 2205}
2206
2207static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2208{
4055eaef
PG		 2209 unsigned int i;
2210 struct bcmgenet_rx_ring *ring;
2211
2212 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2213 ring = &priv->rx_rings[i];
2214 netif_napi_del(&ring->napi);
2215 }
2216
2217 ring = &priv->rx_rings[DESC_INDEX];
2218 netif_napi_del(&ring->napi);
3ab11339
PG		 2219}
2220
8ac467e8
PG		 2221/* Initialize Rx queues
2222 *
2223 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2224 * used to direct traffic to these queues.
2225 *
2226 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2227 */
2228static int bcmgenet_init_rx_queues(struct net_device *dev)
2229{
2230 struct bcmgenet_priv *priv = netdev_priv(dev);
2231 u32 i;
2232 u32 dma_enable;
2233 u32 dma_ctrl;
2234 u32 ring_cfg;
2235 int ret;
2236
2237 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2238 dma_enable = dma_ctrl & DMA_EN;
2239 dma_ctrl &= ~DMA_EN;
2240 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2241
2242 dma_ctrl = 0;
2243 ring_cfg = 0;
2244
2245 /* Initialize Rx priority queues */
2246 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2247 ret = bcmgenet_init_rx_ring(priv, i,
2248 priv->hw_params->rx_bds_per_q,
2249 i * priv->hw_params->rx_bds_per_q,
2250 (i + 1) *
2251 priv->hw_params->rx_bds_per_q);
2252 if (ret)
2253 return ret;
2254
2255 ring_cfg |= (1 << i);
2256 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2257 }
2258
2259 /* Initialize Rx default queue 16 */
2260 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2261 priv->hw_params->rx_queues *
2262 priv->hw_params->rx_bds_per_q,
2263 TOTAL_DESC);
2264 if (ret)
2265 return ret;
2266
2267 ring_cfg |= (1 << DESC_INDEX);
2268 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2269
3ab11339
PG		 2270 /* Initialize Rx NAPI */
2271 bcmgenet_init_rx_napi(priv);
2272
8ac467e8
PG		 2273 /* Enable rings */
2274 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2275
2276 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2277 if (dma_enable)
2278 dma_ctrl |= DMA_EN;
2279 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2280
2281 return 0;
2282}
2283
4a0c081e
FF		 2284static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2285{
2286 int ret = 0;
2287 int timeout = 0;
2288 u32 reg;
b6df7d61
JS		 2289 u32 dma_ctrl;
2290 int i;
4a0c081e
FF		 2291
2292 /* Disable TDMA to stop add more frames in TX DMA */
2293 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2294 reg &= ~DMA_EN;
2295 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2296
2297 /* Check TDMA status register to confirm TDMA is disabled */
2298 while (timeout++ < DMA_TIMEOUT_VAL) {
2299 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2300 if (reg & DMA_DISABLED)
2301 break;
2302
2303 udelay(1);
2304 }
2305
2306 if (timeout == DMA_TIMEOUT_VAL) {
2307 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2308 ret = -ETIMEDOUT;
2309 }
2310
2311 /* Wait 10ms for packet drain in both tx and rx dma */
2312 usleep_range(10000, 20000);
2313
2314 /* Disable RDMA */
2315 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2316 reg &= ~DMA_EN;
2317 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2318
2319 timeout = 0;
2320 /* Check RDMA status register to confirm RDMA is disabled */
2321 while (timeout++ < DMA_TIMEOUT_VAL) {
2322 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2323 if (reg & DMA_DISABLED)
2324 break;
2325
2326 udelay(1);
2327 }
2328
2329 if (timeout == DMA_TIMEOUT_VAL) {
2330 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2331 ret = -ETIMEDOUT;
2332 }
2333
b6df7d61
JS		 2334 dma_ctrl = 0;
2335 for (i = 0; i < priv->hw_params->rx_queues; i++)
2336 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2337 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2338 reg &= ~dma_ctrl;
2339 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2340
2341 dma_ctrl = 0;
2342 for (i = 0; i < priv->hw_params->tx_queues; i++)
2343 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2344 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2345 reg &= ~dma_ctrl;
2346 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2347
4a0c081e
FF		 2348 return ret;
2349}
2350
9abab96d 2351static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2352{
2353 int i;
2354
9abab96d
PG		 2355 bcmgenet_fini_rx_napi(priv);
2356 bcmgenet_fini_tx_napi(priv);
2357
1c1008c7 2358 /* disable DMA */
4a0c081e 2359 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2360
2361 for (i = 0; i < priv->num_tx_bds; i++) {
2362 if (priv->tx_cbs[i].skb != NULL) {
2363 dev_kfree_skb(priv->tx_cbs[i].skb);
2364 priv->tx_cbs[i].skb = NULL;
2365 }
2366 }
2367
2368 bcmgenet_free_rx_buffers(priv);
2369 kfree(priv->rx_cbs);
2370 kfree(priv->tx_cbs);
2371}
2372
2373/* init_edma: Initialize DMA control register */
2374static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2375{
2376 int ret;
014012a4
PG		 2377 unsigned int i;
2378 struct enet_cb *cb;
1c1008c7 2379
6f5a272c 2380 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2381
6f5a272c
PG		 2382 /* Initialize common Rx ring structures */
2383 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2384 priv->num_rx_bds = TOTAL_DESC;
2385 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2386 GFP_KERNEL);
2387 if (!priv->rx_cbs)
2388 return -ENOMEM;
2389
2390 for (i = 0; i < priv->num_rx_bds; i++) {
2391 cb = priv->rx_cbs + i;
2392 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2393 }
2394
7fc527f9 2395 /* Initialize common TX ring structures */
1c1008c7
FF		 2396 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2397 priv->num_tx_bds = TOTAL_DESC;
c489be08 2398 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2399 GFP_KERNEL);
1c1008c7 2400 if (!priv->tx_cbs) {
ebbd96fb 2401 kfree(priv->rx_cbs);
1c1008c7
FF		 2402 return -ENOMEM;
2403 }
2404
014012a4
PG		 2405 for (i = 0; i < priv->num_tx_bds; i++) {
2406 cb = priv->tx_cbs + i;
2407 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2408 }
2409
ebbd96fb
PG		 2410 /* Init rDma */
2411 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2412
2413 /* Initialize Rx queues */
2414 ret = bcmgenet_init_rx_queues(priv->dev);
2415 if (ret) {
2416 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2417 bcmgenet_free_rx_buffers(priv);
2418 kfree(priv->rx_cbs);
2419 kfree(priv->tx_cbs);
2420 return ret;
2421 }
2422
2423 /* Init tDma */
2424 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2425
16c6d667
PG		 2426 /* Initialize Tx queues */
2427 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2428
2429 return 0;
2430}
2431
1c1008c7
FF		 2432/* Interrupt bottom half */
2433static void bcmgenet_irq_task(struct work_struct *work)
2434{
2435 struct bcmgenet_priv *priv = container_of(
2436 work, struct bcmgenet_priv, bcmgenet_irq_work);
2437
2438 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2439
8fdb0e0f
FF		 2440 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2441 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2442 netif_dbg(priv, wol, priv->dev,
2443 "magic packet detected, waking up\n");
2444 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2445 }
2446
1c1008c7 2447 /* Link UP/DOWN event */
d07c0278 2448 if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
80d8e96d 2449 phy_mac_interrupt(priv->phydev,
451e1ca2 2450 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
e122966d 2451 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
1c1008c7
FF		 2452 }
2453}
2454
4055eaef 2455/* bcmgenet_isr1: handle Rx and Tx priority queues */
1c1008c7
FF		 2456static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2457{
2458 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2459 struct bcmgenet_rx_ring *rx_ring;
2460 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2461 unsigned int index;
2462
2463 /* Save irq status for bottom-half processing. */
2464 priv->irq1_stat =
2465 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2466 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2467
7fc527f9 2468 /* clear interrupts */
1c1008c7
FF		 2469 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2470
2471 netif_dbg(priv, intr, priv->dev,
c91b7f66 2472 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2473
4055eaef
PG		 2474 /* Check Rx priority queue interrupts */
2475 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2476 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2477 continue;
2478
2479 rx_ring = &priv->rx_rings[index];
2480
2481 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2482 rx_ring->int_disable(rx_ring);
2483 __napi_schedule(&rx_ring->napi);
2484 }
2485 }
2486
2487 /* Check Tx priority queue interrupts */
4092e6ac
JS		 2488 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2489 if (!(priv->irq1_stat & BIT(index)))
2490 continue;
2491
4055eaef 2492 tx_ring = &priv->tx_rings[index];
4092e6ac 2493
4055eaef
PG		 2494 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2495 tx_ring->int_disable(tx_ring);
2496 __napi_schedule(&tx_ring->napi);
1c1008c7
FF		 2497 }
2498 }
4092e6ac 2499
1c1008c7
FF		 2500 return IRQ_HANDLED;
2501}
2502
4055eaef 2503/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
1c1008c7
FF		 2504static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2505{
2506 struct bcmgenet_priv *priv = dev_id;
4055eaef
PG		 2507 struct bcmgenet_rx_ring *rx_ring;
2508 struct bcmgenet_tx_ring *tx_ring;
1c1008c7
FF		 2509
2510 /* Save irq status for bottom-half processing. */
2511 priv->irq0_stat =
2512 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2513 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
4055eaef 2514
7fc527f9 2515 /* clear interrupts */
1c1008c7
FF		 2516 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2517
2518 netif_dbg(priv, intr, priv->dev,
c91b7f66 2519 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7 2520
ee7d8c20 2521 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
4055eaef
PG		 2522 rx_ring = &priv->rx_rings[DESC_INDEX];
2523
2524 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2525 rx_ring->int_disable(rx_ring);
2526 __napi_schedule(&rx_ring->napi);
1c1008c7
FF		 2527 }
2528 }
4092e6ac 2529
ee7d8c20 2530 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
4055eaef
PG		 2531 tx_ring = &priv->tx_rings[DESC_INDEX];
2532
2533 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2534 tx_ring->int_disable(tx_ring);
2535 __napi_schedule(&tx_ring->napi);
4092e6ac 2536 }
1c1008c7 2537 }
4055eaef 2538
1c1008c7
FF		 2539 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2540 UMAC_IRQ_PHY_DET_F |
e122966d 2541 UMAC_IRQ_LINK_EVENT |
1c1008c7
FF		 2542 UMAC_IRQ_HFB_SM |
2543 UMAC_IRQ_HFB_MM |
2544 UMAC_IRQ_MPD_R)) {
2545 /* all other interested interrupts handled in bottom half */
2546 schedule_work(&priv->bcmgenet_irq_work);
2547 }
2548
2549 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2550 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2551 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2552 wake_up(&priv->wq);
2553 }
2554
2555 return IRQ_HANDLED;
2556}
2557
8562056f
FF		 2558static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2559{
2560 struct bcmgenet_priv *priv = dev_id;
2561
2562 pm_wakeup_event(&priv->pdev->dev, 0);
2563
2564 return IRQ_HANDLED;
2565}
2566
4d2e8882
FF		 2567#ifdef CONFIG_NET_POLL_CONTROLLER
2568static void bcmgenet_poll_controller(struct net_device *dev)
2569{
2570 struct bcmgenet_priv *priv = netdev_priv(dev);
2571
2572 /* Invoke the main RX/TX interrupt handler */
2573 disable_irq(priv->irq0);
2574 bcmgenet_isr0(priv->irq0, priv);
2575 enable_irq(priv->irq0);
2576
2577 /* And the interrupt handler for RX/TX priority queues */
2578 disable_irq(priv->irq1);
2579 bcmgenet_isr1(priv->irq1, priv);
2580 enable_irq(priv->irq1);
2581}
2582#endif
2583
1c1008c7
FF		 2584static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2585{
2586 u32 reg;
2587
2588 reg = bcmgenet_rbuf_ctrl_get(priv);
2589 reg |= BIT(1);
2590 bcmgenet_rbuf_ctrl_set(priv, reg);
2591 udelay(10);
2592
2593 reg &= ~BIT(1);
2594 bcmgenet_rbuf_ctrl_set(priv, reg);
2595 udelay(10);
2596}
2597
2598static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2599 unsigned char *addr)
1c1008c7
FF		 2600{
2601 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2602 (addr[2] << 8) | addr[3], UMAC_MAC0);
2603 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2604}
2605
1c1008c7
FF		 2606/* Returns a reusable dma control register value */
2607static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2608{
2609 u32 reg;
2610 u32 dma_ctrl;
2611
2612 /* disable DMA */
2613 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2614 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2615 reg &= ~dma_ctrl;
2616 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2617
2618 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2619 reg &= ~dma_ctrl;
2620 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2621
2622 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2623 udelay(10);
2624 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2625
2626 return dma_ctrl;
2627}
2628
2629static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2630{
2631 u32 reg;
2632
2633 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2634 reg |= dma_ctrl;
2635 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2636
2637 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2638 reg |= dma_ctrl;
2639 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2640}
2641
0034de41
PG		 2642static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2643 u32 f_index)
2644{
2645 u32 offset;
2646 u32 reg;
2647
2648 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2649 reg = bcmgenet_hfb_reg_readl(priv, offset);
2650 return !!(reg & (1 << (f_index % 32)));
2651}
2652
2653static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2654{
2655 u32 offset;
2656 u32 reg;
2657
2658 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2659 reg = bcmgenet_hfb_reg_readl(priv, offset);
2660 reg |= (1 << (f_index % 32));
2661 bcmgenet_hfb_reg_writel(priv, reg, offset);
2662}
2663
2664static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2665 u32 f_index, u32 rx_queue)
2666{
2667 u32 offset;
2668 u32 reg;
2669
2670 offset = f_index / 8;
2671 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2672 reg &= ~(0xF << (4 * (f_index % 8)));
2673 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2674 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2675}
2676
2677static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2678 u32 f_index, u32 f_length)
2679{
2680 u32 offset;
2681 u32 reg;
2682
2683 offset = HFB_FLT_LEN_V3PLUS +
2684 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2685 sizeof(u32);
2686 reg = bcmgenet_hfb_reg_readl(priv, offset);
2687 reg &= ~(0xFF << (8 * (f_index % 4)));
2688 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2689 bcmgenet_hfb_reg_writel(priv, reg, offset);
2690}
2691
2692static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2693{
2694 u32 f_index;
2695
2696 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2697 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2698 return f_index;
2699
2700 return -ENOMEM;
2701}
2702
2703/* bcmgenet_hfb_add_filter
2704 *
2705 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2706 * desired Rx queue.
2707 *
2708 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2709 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2710 *
2711 * bits 31:20 - unused
2712 * bit 19 - nibble 0 match enable
2713 * bit 18 - nibble 1 match enable
2714 * bit 17 - nibble 2 match enable
2715 * bit 16 - nibble 3 match enable
2716 * bits 15:12 - nibble 0 data
2717 * bits 11:8 - nibble 1 data
2718 * bits 7:4 - nibble 2 data
2719 * bits 3:0 - nibble 3 data
2720 *
2721 * Example:
2722 * In order to match:
2723 * - Ethernet frame type = 0x0800 (IP)
2724 * - IP version field = 4
2725 * - IP protocol field = 0x11 (UDP)
2726 *
2727 * The following filter is needed:
2728 * u32 hfb_filter_ipv4_udp[] = {
2729 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2730 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2731 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2732 * };
2733 *
2734 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2735 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2736 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2737 */
2738int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2739 u32 f_length, u32 rx_queue)
2740{
2741 int f_index;
2742 u32 i;
2743
2744 f_index = bcmgenet_hfb_find_unused_filter(priv);
2745 if (f_index < 0)
2746 return -ENOMEM;
2747
2748 if (f_length > priv->hw_params->hfb_filter_size)
2749 return -EINVAL;
2750
2751 for (i = 0; i < f_length; i++)
2752 bcmgenet_hfb_writel(priv, f_data[i],
2753 (f_index * priv->hw_params->hfb_filter_size + i) *
2754 sizeof(u32));
2755
2756 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2757 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2758 bcmgenet_hfb_enable_filter(priv, f_index);
2759 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2760
2761 return 0;
2762}
2763
2764/* bcmgenet_hfb_clear
2765 *
2766 * Clear Hardware Filter Block and disable all filtering.
2767 */
2768static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2769{
2770 u32 i;
2771
2772 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2773 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2774 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2775
2776 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2777 bcmgenet_rdma_writel(priv, 0x0, i);
2778
2779 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2780 bcmgenet_hfb_reg_writel(priv, 0x0,
2781 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2782
2783 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2784 priv->hw_params->hfb_filter_size; i++)
2785 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2786}
2787
2788static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2789{
2790 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2791 return;
2792
2793 bcmgenet_hfb_clear(priv);
2794}
2795
909ff5ef
FF		 2796static void bcmgenet_netif_start(struct net_device *dev)
2797{
2798 struct bcmgenet_priv *priv = netdev_priv(dev);
2799
2800 /* Start the network engine */
3ab11339 2801 bcmgenet_enable_rx_napi(priv);
e2aadb4a 2802 bcmgenet_enable_tx_napi(priv);
909ff5ef
FF		 2803
2804 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2805
909ff5ef
FF		 2806 netif_tx_start_all_queues(dev);
2807
37850e37
FF		 2808 /* Monitor link interrupts now */
2809 bcmgenet_link_intr_enable(priv);
2810
909ff5ef
FF		 2811 phy_start(priv->phydev);
2812}
2813
1c1008c7
FF		 2814static int bcmgenet_open(struct net_device *dev)
2815{
2816 struct bcmgenet_priv *priv = netdev_priv(dev);
2817 unsigned long dma_ctrl;
2818 u32 reg;
2819 int ret;
2820
2821 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2822
2823 /* Turn on the clock */
7d5d3075 2824 clk_prepare_enable(priv->clk);
1c1008c7 2825
a642c4f7
FF		 2826 /* If this is an internal GPHY, power it back on now, before UniMAC is
2827 * brought out of reset as absolutely no UniMAC activity is allowed
2828 */
c624f891 2829 if (priv->internal_phy)
a642c4f7
FF		 2830 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2831
1c1008c7
FF		 2832 /* take MAC out of reset */
2833 bcmgenet_umac_reset(priv);
2834
2835 ret = init_umac(priv);
2836 if (ret)
2837 goto err_clk_disable;
2838
2839 /* disable ethernet MAC while updating its registers */
e29585b8 2840 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2841
909ff5ef
FF		 2842 /* Make sure we reflect the value of CRC_CMD_FWD */
2843 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2844 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2845
1c1008c7
FF		 2846 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2847
c624f891 2848 if (priv->internal_phy) {
1c1008c7
FF		 2849 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2850 reg |= EXT_ENERGY_DET_MASK;
2851 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2852 }
2853
2854 /* Disable RX/TX DMA and flush TX queues */
2855 dma_ctrl = bcmgenet_dma_disable(priv);
2856
2857 /* Reinitialize TDMA and RDMA and SW housekeeping */
2858 ret = bcmgenet_init_dma(priv);
2859 if (ret) {
2860 netdev_err(dev, "failed to initialize DMA\n");
fac25940 2861 goto err_clk_disable;
1c1008c7
FF		 2862 }
2863
2864 /* Always enable ring 16 - descriptor ring */
2865 bcmgenet_enable_dma(priv, dma_ctrl);
2866
0034de41
PG		 2867 /* HFB init */
2868 bcmgenet_hfb_init(priv);
2869
1c1008c7 2870 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2871 dev->name, priv);
1c1008c7
FF		 2872 if (ret < 0) {
2873 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2874 goto err_fini_dma;
2875 }
2876
2877 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2878 dev->name, priv);
1c1008c7
FF		 2879 if (ret < 0) {
2880 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2881 goto err_irq0;
2882 }
2883
6cc8e6d4
FF		 2884 ret = bcmgenet_mii_probe(dev);
2885 if (ret) {
2886 netdev_err(dev, "failed to connect to PHY\n");
2887 goto err_irq1;
2888 }
c96e731c 2889
909ff5ef 2890 bcmgenet_netif_start(dev);
1c1008c7
FF		 2891
2892 return 0;
2893
6cc8e6d4
FF		 2894err_irq1:
2895 free_irq(priv->irq1, priv);
1c1008c7 2896err_irq0:
978ffac4 2897 free_irq(priv->irq0, priv);
1c1008c7
FF		 2898err_fini_dma:
2899 bcmgenet_fini_dma(priv);
2900err_clk_disable:
7d5d3075 2901 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 2902 return ret;
2903}
2904
909ff5ef
FF		 2905static void bcmgenet_netif_stop(struct net_device *dev)
2906{
2907 struct bcmgenet_priv *priv = netdev_priv(dev);
2908
2909 netif_tx_stop_all_queues(dev);
909ff5ef 2910 phy_stop(priv->phydev);
909ff5ef 2911 bcmgenet_intr_disable(priv);
3ab11339 2912 bcmgenet_disable_rx_napi(priv);
e2aadb4a 2913 bcmgenet_disable_tx_napi(priv);
909ff5ef
FF		 2914
2915 /* Wait for pending work items to complete. Since interrupts are
2916 * disabled no new work will be scheduled.
2917 */
2918 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2919
cc013fb4 2920 priv->old_link = -1;
5ad6e6c5 2921 priv->old_speed = -1;
cc013fb4 2922 priv->old_duplex = -1;
5ad6e6c5 2923 priv->old_pause = -1;
909ff5ef
FF		 2924}
2925
1c1008c7
FF		 2926static int bcmgenet_close(struct net_device *dev)
2927{
2928 struct bcmgenet_priv *priv = netdev_priv(dev);
2929 int ret;
1c1008c7
FF		 2930
2931 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2932
909ff5ef 2933 bcmgenet_netif_stop(dev);
1c1008c7 2934
c96e731c
FF		 2935 /* Really kill the PHY state machine and disconnect from it */
2936 phy_disconnect(priv->phydev);
2937
1c1008c7 2938 /* Disable MAC receive */
e29585b8 2939 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2940
1c1008c7
FF		 2941 ret = bcmgenet_dma_teardown(priv);
2942 if (ret)
2943 return ret;
2944
2945 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2946 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2947
1c1008c7
FF		 2948 /* tx reclaim */
2949 bcmgenet_tx_reclaim_all(dev);
2950 bcmgenet_fini_dma(priv);
2951
2952 free_irq(priv->irq0, priv);
2953 free_irq(priv->irq1, priv);
2954
c624f891 2955 if (priv->internal_phy)
ca8cf341 2956 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2957
7d5d3075 2958 clk_disable_unprepare(priv->clk);
1c1008c7 2959
ca8cf341 2960 return ret;
1c1008c7
FF		 2961}
2962
13ea6578
FF		 2963static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2964{
2965 struct bcmgenet_priv *priv = ring->priv;
2966 u32 p_index, c_index, intsts, intmsk;
2967 struct netdev_queue *txq;
2968 unsigned int free_bds;
2969 unsigned long flags;
2970 bool txq_stopped;
2971
2972 if (!netif_msg_tx_err(priv))
2973 return;
2974
2975 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2976
2977 spin_lock_irqsave(&ring->lock, flags);
2978 if (ring->index == DESC_INDEX) {
2979 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2980 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2981 } else {
2982 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2983 intmsk = 1 << ring->index;
2984 }
2985 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2986 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2987 txq_stopped = netif_tx_queue_stopped(txq);
2988 free_bds = ring->free_bds;
2989 spin_unlock_irqrestore(&ring->lock, flags);
2990
2991 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2992 "TX queue status: %s, interrupts: %s\n"
2993 "(sw)free_bds: %d (sw)size: %d\n"
2994 "(sw)p_index: %d (hw)p_index: %d\n"
2995 "(sw)c_index: %d (hw)c_index: %d\n"
2996 "(sw)clean_p: %d (sw)write_p: %d\n"
2997 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2998 ring->index, ring->queue,
2999 txq_stopped ? "stopped" : "active",
3000 intsts & intmsk ? "enabled" : "disabled",
3001 free_bds, ring->size,
3002 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3003 ring->c_index, c_index & DMA_C_INDEX_MASK,
3004 ring->clean_ptr, ring->write_ptr,
3005 ring->cb_ptr, ring->end_ptr);
3006}
3007
1c1008c7
FF		 3008static void bcmgenet_timeout(struct net_device *dev)
3009{
3010 struct bcmgenet_priv *priv = netdev_priv(dev);
13ea6578
FF		 3011 u32 int0_enable = 0;
3012 u32 int1_enable = 0;
3013 unsigned int q;
1c1008c7
FF		 3014
3015 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3016
13ea6578
FF		 3017 for (q = 0; q < priv->hw_params->tx_queues; q++)
3018 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3019 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3020
3021 bcmgenet_tx_reclaim_all(dev);
3022
3023 for (q = 0; q < priv->hw_params->tx_queues; q++)
3024 int1_enable |= (1 << q);
3025
3026 int0_enable = UMAC_IRQ_TXDMA_DONE;
3027
3028 /* Re-enable TX interrupts if disabled */
3029 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3030 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3031
1c1008c7
FF		 3032 dev->trans_start = jiffies;
3033
3034 dev->stats.tx_errors++;
3035
3036 netif_tx_wake_all_queues(dev);
3037}
3038
3039#define MAX_MC_COUNT 16
3040
3041static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3042 unsigned char *addr,
3043 int *i,
3044 int *mc)
3045{
3046 u32 reg;
3047
c91b7f66
FF		 3048 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3049 UMAC_MDF_ADDR + (*i * 4));
3050 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3051 addr[4] << 8 | addr[5],
3052 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 3053 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3054 reg |= (1 << (MAX_MC_COUNT - *mc));
3055 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3056 *i += 2;
3057 (*mc)++;
3058}
3059
3060static void bcmgenet_set_rx_mode(struct net_device *dev)
3061{
3062 struct bcmgenet_priv *priv = netdev_priv(dev);
3063 struct netdev_hw_addr *ha;
3064 int i, mc;
3065 u32 reg;
3066
3067 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3068
7fc527f9 3069 /* Promiscuous mode */
1c1008c7
FF		 3070 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3071 if (dev->flags & IFF_PROMISC) {
3072 reg |= CMD_PROMISC;
3073 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3074 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3075 return;
3076 } else {
3077 reg &= ~CMD_PROMISC;
3078 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3079 }
3080
3081 /* UniMac doesn't support ALLMULTI */
3082 if (dev->flags & IFF_ALLMULTI) {
3083 netdev_warn(dev, "ALLMULTI is not supported\n");
3084 return;
3085 }
3086
3087 /* update MDF filter */
3088 i = 0;
3089 mc = 0;
3090 /* Broadcast */
3091 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3092 /* my own address.*/
3093 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3094 /* Unicast list*/
3095 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3096 return;
3097
3098 if (!netdev_uc_empty(dev))
3099 netdev_for_each_uc_addr(ha, dev)
3100 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3101 /* Multicast */
3102 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3103 return;
3104
3105 netdev_for_each_mc_addr(ha, dev)
3106 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3107}
3108
3109/* Set the hardware MAC address. */
3110static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3111{
3112 struct sockaddr *addr = p;
3113
3114 /* Setting the MAC address at the hardware level is not possible
3115 * without disabling the UniMAC RX/TX enable bits.
3116 */
3117 if (netif_running(dev))
3118 return -EBUSY;
3119
3120 ether_addr_copy(dev->dev_addr, addr->sa_data);
3121
3122 return 0;
3123}
3124
1c1008c7
FF		 3125static const struct net_device_ops bcmgenet_netdev_ops = {
3126 .ndo_open = bcmgenet_open,
3127 .ndo_stop = bcmgenet_close,
3128 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 3129 .ndo_tx_timeout = bcmgenet_timeout,
3130 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3131 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3132 .ndo_do_ioctl = bcmgenet_ioctl,
3133 .ndo_set_features = bcmgenet_set_features,
4d2e8882
FF		 3134#ifdef CONFIG_NET_POLL_CONTROLLER
3135 .ndo_poll_controller = bcmgenet_poll_controller,
3136#endif
1c1008c7
FF		 3137};
3138
3139/* Array of GENET hardware parameters/characteristics */
3140static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3141 [GENET_V1] = {
3142 .tx_queues = 0,
51a966a7 3143 .tx_bds_per_q = 0,
1c1008c7 3144 .rx_queues = 0,
3feafa02 3145 .rx_bds_per_q = 0,
1c1008c7
FF		 3146 .bp_in_en_shift = 16,
3147 .bp_in_mask = 0xffff,
3148 .hfb_filter_cnt = 16,
3149 .qtag_mask = 0x1F,
3150 .hfb_offset = 0x1000,
3151 .rdma_offset = 0x2000,
3152 .tdma_offset = 0x3000,
3153 .words_per_bd = 2,
3154 },
3155 [GENET_V2] = {
3156 .tx_queues = 4,
51a966a7 3157 .tx_bds_per_q = 32,
7e906e02 3158 .rx_queues = 0,
3feafa02 3159 .rx_bds_per_q = 0,
1c1008c7
FF		 3160 .bp_in_en_shift = 16,
3161 .bp_in_mask = 0xffff,
3162 .hfb_filter_cnt = 16,
3163 .qtag_mask = 0x1F,
3164 .tbuf_offset = 0x0600,
3165 .hfb_offset = 0x1000,
3166 .hfb_reg_offset = 0x2000,
3167 .rdma_offset = 0x3000,
3168 .tdma_offset = 0x4000,
3169 .words_per_bd = 2,
3170 .flags = GENET_HAS_EXT,
3171 },
3172 [GENET_V3] = {
3173 .tx_queues = 4,
51a966a7 3174 .tx_bds_per_q = 32,
7e906e02 3175 .rx_queues = 0,
3feafa02 3176 .rx_bds_per_q = 0,
1c1008c7
FF		 3177 .bp_in_en_shift = 17,
3178 .bp_in_mask = 0x1ffff,
3179 .hfb_filter_cnt = 48,
0034de41 3180 .hfb_filter_size = 128,
1c1008c7
FF		 3181 .qtag_mask = 0x3F,
3182 .tbuf_offset = 0x0600,
3183 .hfb_offset = 0x8000,
3184 .hfb_reg_offset = 0xfc00,
3185 .rdma_offset = 0x10000,
3186 .tdma_offset = 0x11000,
3187 .words_per_bd = 2,
8d88c6eb
PG		 3188 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3189 GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3190 },
3191 [GENET_V4] = {
3192 .tx_queues = 4,
51a966a7 3193 .tx_bds_per_q = 32,
7e906e02 3194 .rx_queues = 0,
3feafa02 3195 .rx_bds_per_q = 0,
1c1008c7
FF		 3196 .bp_in_en_shift = 17,
3197 .bp_in_mask = 0x1ffff,
3198 .hfb_filter_cnt = 48,
0034de41 3199 .hfb_filter_size = 128,
1c1008c7
FF		 3200 .qtag_mask = 0x3F,
3201 .tbuf_offset = 0x0600,
3202 .hfb_offset = 0x8000,
3203 .hfb_reg_offset = 0xfc00,
3204 .rdma_offset = 0x2000,
3205 .tdma_offset = 0x4000,
3206 .words_per_bd = 3,
8d88c6eb
PG		 3207 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3208 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
1c1008c7
FF		 3209 },
3210};
3211
3212/* Infer hardware parameters from the detected GENET version */
3213static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3214{
3215 struct bcmgenet_hw_params *params;
3216 u32 reg;
3217 u8 major;
b04a2f5b 3218 u16 gphy_rev;
1c1008c7
FF		 3219
3220 if (GENET_IS_V4(priv)) {
3221 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3222 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3223 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3224 priv->version = GENET_V4;
3225 } else if (GENET_IS_V3(priv)) {
3226 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3227 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3228 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3229 priv->version = GENET_V3;
3230 } else if (GENET_IS_V2(priv)) {
3231 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3232 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3233 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3234 priv->version = GENET_V2;
3235 } else if (GENET_IS_V1(priv)) {
3236 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3237 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3238 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3239 priv->version = GENET_V1;
3240 }
3241
3242 /* enum genet_version starts at 1 */
3243 priv->hw_params = &bcmgenet_hw_params[priv->version];
3244 params = priv->hw_params;
3245
3246 /* Read GENET HW version */
3247 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3248 major = (reg >> 24 & 0x0f);
3249 if (major == 5)
3250 major = 4;
3251 else if (major == 0)
3252 major = 1;
3253 if (major != priv->version) {
3254 dev_err(&priv->pdev->dev,
3255 "GENET version mismatch, got: %d, configured for: %d\n",
3256 major, priv->version);
3257 }
3258
3259 /* Print the GENET core version */
3260 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 3261 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 3262
487320c5
FF		 3263 /* Store the integrated PHY revision for the MDIO probing function
3264 * to pass this information to the PHY driver. The PHY driver expects
3265 * to find the PHY major revision in bits 15:8 while the GENET register
3266 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 3267 *
3268 * On newer chips, starting with PHY revision G0, a new scheme is
3269 * deployed similar to the Starfighter 2 switch with GPHY major
3270 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3271 * is reserved as well as special value 0x01ff, we have a small
3272 * heuristic to check for the new GPHY revision and re-arrange things
3273 * so the GPHY driver is happy.
487320c5 3274 */
b04a2f5b
FF		 3275 gphy_rev = reg & 0xffff;
3276
3277 /* This is the good old scheme, just GPHY major, no minor nor patch */
3278 if ((gphy_rev & 0xf0) != 0)
3279 priv->gphy_rev = gphy_rev << 8;
3280
3281 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3282 else if ((gphy_rev & 0xff00) != 0)
3283 priv->gphy_rev = gphy_rev;
3284
3285 /* This is reserved so should require special treatment */
3286 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3287 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3288 return;
3289 }
487320c5 3290
1c1008c7
FF		 3291#ifdef CONFIG_PHYS_ADDR_T_64BIT
3292 if (!(params->flags & GENET_HAS_40BITS))
3293 pr_warn("GENET does not support 40-bits PA\n");
3294#endif
3295
3296 pr_debug("Configuration for version: %d\n"
3feafa02 3297 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 3298 "BP << en: %2d, BP msk: 0x%05x\n"
3299 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3300 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3301 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3302 "Words/BD: %d\n",
3303 priv->version,
51a966a7 3304 params->tx_queues, params->tx_bds_per_q,
3feafa02 3305 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 3306 params->bp_in_en_shift, params->bp_in_mask,
3307 params->hfb_filter_cnt, params->qtag_mask,
3308 params->tbuf_offset, params->hfb_offset,
3309 params->hfb_reg_offset,
3310 params->rdma_offset, params->tdma_offset,
3311 params->words_per_bd);
3312}
3313
3314static const struct of_device_id bcmgenet_match[] = {
3315 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3316 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3317 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3318 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3319 { },
3320};
e8048e55 3321MODULE_DEVICE_TABLE(of, bcmgenet_match);
1c1008c7
FF		 3322
3323static int bcmgenet_probe(struct platform_device *pdev)
3324{
b0ba512e 3325 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 3326 struct device_node *dn = pdev->dev.of_node;
b0ba512e 3327 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 3328 struct bcmgenet_priv *priv;
3329 struct net_device *dev;
3330 const void *macaddr;
3331 struct resource *r;
3332 int err = -EIO;
3333
3feafeed
PG		 3334 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3335 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3336 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 3337 if (!dev) {
3338 dev_err(&pdev->dev, "can't allocate net device\n");
3339 return -ENOMEM;
3340 }
3341
b0ba512e
PG		 3342 if (dn) {
3343 of_id = of_match_node(bcmgenet_match, dn);
3344 if (!of_id)
3345 return -EINVAL;
3346 }
1c1008c7
FF		 3347
3348 priv = netdev_priv(dev);
3349 priv->irq0 = platform_get_irq(pdev, 0);
3350 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 3351 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 3352 if (!priv->irq0 || !priv->irq1) {
3353 dev_err(&pdev->dev, "can't find IRQs\n");
3354 err = -EINVAL;
3355 goto err;
3356 }
3357
b0ba512e
PG		 3358 if (dn) {
3359 macaddr = of_get_mac_address(dn);
3360 if (!macaddr) {
3361 dev_err(&pdev->dev, "can't find MAC address\n");
3362 err = -EINVAL;
3363 goto err;
3364 }
3365 } else {
3366 macaddr = pd->mac_address;
1c1008c7
FF		 3367 }
3368
3369 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 3370 priv->base = devm_ioremap_resource(&pdev->dev, r);
3371 if (IS_ERR(priv->base)) {
3372 err = PTR_ERR(priv->base);
1c1008c7
FF		 3373 goto err;
3374 }
3375
3376 SET_NETDEV_DEV(dev, &pdev->dev);
3377 dev_set_drvdata(&pdev->dev, dev);
3378 ether_addr_copy(dev->dev_addr, macaddr);
3379 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 3380 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7 3381 dev->netdev_ops = &bcmgenet_netdev_ops;
1c1008c7
FF		 3382
3383 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3384
3385 /* Set hardware features */
3386 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3387 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3388
8562056f
FF		 3389 /* Request the WOL interrupt and advertise suspend if available */
3390 priv->wol_irq_disabled = true;
3391 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3392 dev->name, priv);
3393 if (!err)
3394 device_set_wakeup_capable(&pdev->dev, 1);
3395
1c1008c7
FF		 3396 /* Set the needed headroom to account for any possible
3397 * features enabling/disabling at runtime
3398 */
3399 dev->needed_headroom += 64;
3400
3401 netdev_boot_setup_check(dev);
3402
3403 priv->dev = dev;
3404 priv->pdev = pdev;
b0ba512e
PG		 3405 if (of_id)
3406 priv->version = (enum bcmgenet_version)of_id->data;
3407 else
3408 priv->version = pd->genet_version;
1c1008c7 3409
e4a60a93 3410 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
7d5d3075 3411 if (IS_ERR(priv->clk)) {
e4a60a93 3412 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
7d5d3075
FF		 3413 priv->clk = NULL;
3414 }
e4a60a93 3415
7d5d3075 3416 clk_prepare_enable(priv->clk);
e4a60a93 3417
1c1008c7
FF		 3418 bcmgenet_set_hw_params(priv);
3419
1c1008c7
FF		 3420 /* Mii wait queue */
3421 init_waitqueue_head(&priv->wq);
3422 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3423 priv->rx_buf_len = RX_BUF_LENGTH;
3424 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3425
1c1008c7 3426 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
7d5d3075 3427 if (IS_ERR(priv->clk_wol)) {
1c1008c7 3428 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
7d5d3075
FF		 3429 priv->clk_wol = NULL;
3430 }
1c1008c7 3431
6ef398ea
FF		 3432 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3433 if (IS_ERR(priv->clk_eee)) {
3434 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3435 priv->clk_eee = NULL;
3436 }
3437
1c1008c7
FF		 3438 err = reset_umac(priv);
3439 if (err)
3440 goto err_clk_disable;
3441
3442 err = bcmgenet_mii_init(dev);
3443 if (err)
3444 goto err_clk_disable;
3445
3446 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3447 * just the ring 16 descriptor based TX
3448 */
3449 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3450 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3451
219575eb
FF		 3452 /* libphy will determine the link state */
3453 netif_carrier_off(dev);
3454
1c1008c7 3455 /* Turn off the main clock, WOL clock is handled separately */
7d5d3075 3456 clk_disable_unprepare(priv->clk);
1c1008c7 3457
0f50ce96
FF		 3458 err = register_netdev(dev);
3459 if (err)
3460 goto err;
3461
1c1008c7
FF		 3462 return err;
3463
3464err_clk_disable:
7d5d3075 3465 clk_disable_unprepare(priv->clk);
1c1008c7
FF		 3466err:
3467 free_netdev(dev);
3468 return err;
3469}
3470
3471static int bcmgenet_remove(struct platform_device *pdev)
3472{
3473 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3474
3475 dev_set_drvdata(&pdev->dev, NULL);
3476 unregister_netdev(priv->dev);
3477 bcmgenet_mii_exit(priv->dev);
3478 free_netdev(priv->dev);
3479
3480 return 0;
3481}
3482
b6e978e5
FF		 3483#ifdef CONFIG_PM_SLEEP
3484static int bcmgenet_suspend(struct device *d)
3485{
3486 struct net_device *dev = dev_get_drvdata(d);
3487 struct bcmgenet_priv *priv = netdev_priv(dev);
3488 int ret;
3489
3490 if (!netif_running(dev))
3491 return 0;
3492
3493 bcmgenet_netif_stop(dev);
3494
cc013fb4
FF		 3495 phy_suspend(priv->phydev);
3496
b6e978e5
FF		 3497 netif_device_detach(dev);
3498
3499 /* Disable MAC receive */
3500 umac_enable_set(priv, CMD_RX_EN, false);
3501
3502 ret = bcmgenet_dma_teardown(priv);
3503 if (ret)
3504 return ret;
3505
3506 /* Disable MAC transmit. TX DMA disabled have to done before this */
3507 umac_enable_set(priv, CMD_TX_EN, false);
3508
3509 /* tx reclaim */
3510 bcmgenet_tx_reclaim_all(dev);
3511 bcmgenet_fini_dma(priv);
3512
8c90db72
FF		 3513 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3514 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3515 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72 3516 clk_prepare_enable(priv->clk_wol);
c624f891 3517 } else if (priv->internal_phy) {
a6f31f5e 3518 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
8c90db72
FF		 3519 }
3520
b6e978e5
FF		 3521 /* Turn off the clocks */
3522 clk_disable_unprepare(priv->clk);
3523
ca8cf341 3524 return ret;
b6e978e5
FF		 3525}
3526
3527static int bcmgenet_resume(struct device *d)
3528{
3529 struct net_device *dev = dev_get_drvdata(d);
3530 struct bcmgenet_priv *priv = netdev_priv(dev);
3531 unsigned long dma_ctrl;
3532 int ret;
3533 u32 reg;
3534
3535 if (!netif_running(dev))
3536 return 0;
3537
3538 /* Turn on the clock */
3539 ret = clk_prepare_enable(priv->clk);
3540 if (ret)
3541 return ret;
3542
a6f31f5e
FF		 3543 /* If this is an internal GPHY, power it back on now, before UniMAC is
3544 * brought out of reset as absolutely no UniMAC activity is allowed
3545 */
c624f891 3546 if (priv->internal_phy)
a6f31f5e
FF		 3547 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3548
b6e978e5
FF		 3549 bcmgenet_umac_reset(priv);
3550
3551 ret = init_umac(priv);
3552 if (ret)
3553 goto out_clk_disable;
3554
0a29b3da
TK		 3555 /* From WOL-enabled suspend, switch to regular clock */
3556 if (priv->wolopts)
3557 clk_disable_unprepare(priv->clk_wol);
3558
3559 phy_init_hw(priv->phydev);
3560 /* Speed settings must be restored */
28b45910 3561 bcmgenet_mii_config(priv->dev);
8c90db72 3562
b6e978e5
FF		 3563 /* disable ethernet MAC while updating its registers */
3564 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3565
3566 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3567
c624f891 3568 if (priv->internal_phy) {
b6e978e5
FF		 3569 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3570 reg |= EXT_ENERGY_DET_MASK;
3571 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3572 }
3573
98bb7399
FF		 3574 if (priv->wolopts)
3575 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3576
b6e978e5
FF		 3577 /* Disable RX/TX DMA and flush TX queues */
3578 dma_ctrl = bcmgenet_dma_disable(priv);
3579
3580 /* Reinitialize TDMA and RDMA and SW housekeeping */
3581 ret = bcmgenet_init_dma(priv);
3582 if (ret) {
3583 netdev_err(dev, "failed to initialize DMA\n");
3584 goto out_clk_disable;
3585 }
3586
3587 /* Always enable ring 16 - descriptor ring */
3588 bcmgenet_enable_dma(priv, dma_ctrl);
3589
3590 netif_device_attach(dev);
3591
cc013fb4
FF		 3592 phy_resume(priv->phydev);
3593
6ef398ea
FF		 3594 if (priv->eee.eee_enabled)
3595 bcmgenet_eee_enable_set(dev, true);
3596
b6e978e5
FF		 3597 bcmgenet_netif_start(dev);
3598
3599 return 0;
3600
3601out_clk_disable:
3602 clk_disable_unprepare(priv->clk);
3603 return ret;
3604}
3605#endif /* CONFIG_PM_SLEEP */
3606
3607static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3608
1c1008c7
FF		 3609static struct platform_driver bcmgenet_driver = {
3610 .probe = bcmgenet_probe,
3611 .remove = bcmgenet_remove,
3612 .driver = {
3613 .name = "bcmgenet",
1c1008c7 3614 .of_match_table = bcmgenet_match,
b6e978e5 3615 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3616 },
3617};
3618module_platform_driver(bcmgenet_driver);
3619
3620MODULE_AUTHOR("Broadcom Corporation");
3621MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3622MODULE_ALIAS("platform:bcmgenet");
3623MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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