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net: bcmgenet: set hw_params->rx_queues = 0
[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
51a966a7
PG		 57#define GENET_Q16_TX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 59
60#define RX_BUF_LENGTH 2048
61#define SKB_ALIGNMENT 32
62
63/* Tx/Rx DMA register offset, skip 256 descriptors */
64#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
65#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
66
67#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
68 TOTAL_DESC * DMA_DESC_SIZE)
69
70#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
71 TOTAL_DESC * DMA_DESC_SIZE)
72
73static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 74 void __iomem *d, u32 value)
1c1008c7
FF		 75{
76 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
77}
78
79static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 80 void __iomem *d)
1c1008c7
FF		 81{
82 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
83}
84
85static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
86 void __iomem *d,
87 dma_addr_t addr)
88{
89 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
90
91 /* Register writes to GISB bus can take couple hundred nanoseconds
92 * and are done for each packet, save these expensive writes unless
7fc527f9 93 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 94 */
95#ifdef CONFIG_PHYS_ADDR_T_64BIT
96 if (priv->hw_params->flags & GENET_HAS_40BITS)
97 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
98#endif
99}
100
101/* Combined address + length/status setter */
102static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 103 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 104{
105 dmadesc_set_length_status(priv, d, val);
106 dmadesc_set_addr(priv, d, addr);
107}
108
109static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
110 void __iomem *d)
111{
112 dma_addr_t addr;
113
114 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
115
116 /* Register writes to GISB bus can take couple hundred nanoseconds
117 * and are done for each packet, save these expensive writes unless
7fc527f9 118 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 119 */
120#ifdef CONFIG_PHYS_ADDR_T_64BIT
121 if (priv->hw_params->flags & GENET_HAS_40BITS)
122 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
123#endif
124 return addr;
125}
126
127#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
128
129#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
130 NETIF_MSG_LINK)
131
132static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
133{
134 if (GENET_IS_V1(priv))
135 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
136 else
137 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
138}
139
140static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
141{
142 if (GENET_IS_V1(priv))
143 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
144 else
145 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
146}
147
148/* These macros are defined to deal with register map change
149 * between GENET1.1 and GENET2. Only those currently being used
150 * by driver are defined.
151 */
152static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
153{
154 if (GENET_IS_V1(priv))
155 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
156 else
157 return __raw_readl(priv->base +
158 priv->hw_params->tbuf_offset + TBUF_CTRL);
159}
160
161static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162{
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
165 else
166 __raw_writel(val, priv->base +
167 priv->hw_params->tbuf_offset + TBUF_CTRL);
168}
169
170static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
171{
172 if (GENET_IS_V1(priv))
173 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
174 else
175 return __raw_readl(priv->base +
176 priv->hw_params->tbuf_offset + TBUF_BP_MC);
177}
178
179static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
180{
181 if (GENET_IS_V1(priv))
182 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
183 else
184 __raw_writel(val, priv->base +
185 priv->hw_params->tbuf_offset + TBUF_BP_MC);
186}
187
188/* RX/TX DMA register accessors */
189enum dma_reg {
190 DMA_RING_CFG = 0,
191 DMA_CTRL,
192 DMA_STATUS,
193 DMA_SCB_BURST_SIZE,
194 DMA_ARB_CTRL,
37742166
PG		 195 DMA_PRIORITY_0,
196 DMA_PRIORITY_1,
197 DMA_PRIORITY_2,
1c1008c7
FF		 198};
199
200static const u8 bcmgenet_dma_regs_v3plus[] = {
201 [DMA_RING_CFG] = 0x00,
202 [DMA_CTRL] = 0x04,
203 [DMA_STATUS] = 0x08,
204 [DMA_SCB_BURST_SIZE] = 0x0C,
205 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 206 [DMA_PRIORITY_0] = 0x30,
207 [DMA_PRIORITY_1] = 0x34,
208 [DMA_PRIORITY_2] = 0x38,
1c1008c7
FF		 209};
210
211static const u8 bcmgenet_dma_regs_v2[] = {
212 [DMA_RING_CFG] = 0x00,
213 [DMA_CTRL] = 0x04,
214 [DMA_STATUS] = 0x08,
215 [DMA_SCB_BURST_SIZE] = 0x0C,
216 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 217 [DMA_PRIORITY_0] = 0x34,
218 [DMA_PRIORITY_1] = 0x38,
219 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 220};
221
222static const u8 bcmgenet_dma_regs_v1[] = {
223 [DMA_CTRL] = 0x00,
224 [DMA_STATUS] = 0x04,
225 [DMA_SCB_BURST_SIZE] = 0x0C,
226 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 227 [DMA_PRIORITY_0] = 0x34,
228 [DMA_PRIORITY_1] = 0x38,
229 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 230};
231
232/* Set at runtime once bcmgenet version is known */
233static const u8 *bcmgenet_dma_regs;
234
235static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
236{
237 return netdev_priv(dev_get_drvdata(dev));
238}
239
240static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 241 enum dma_reg r)
1c1008c7
FF		 242{
243 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
244 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
245}
246
247static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
248 u32 val, enum dma_reg r)
249{
250 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
251 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
252}
253
254static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 255 enum dma_reg r)
1c1008c7
FF		 256{
257 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
258 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
259}
260
261static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
262 u32 val, enum dma_reg r)
263{
264 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
265 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
266}
267
268/* RDMA/TDMA ring registers and accessors
269 * we merge the common fields and just prefix with T/D the registers
270 * having different meaning depending on the direction
271 */
272enum dma_ring_reg {
273 TDMA_READ_PTR = 0,
274 RDMA_WRITE_PTR = TDMA_READ_PTR,
275 TDMA_READ_PTR_HI,
276 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
277 TDMA_CONS_INDEX,
278 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
279 TDMA_PROD_INDEX,
280 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
281 DMA_RING_BUF_SIZE,
282 DMA_START_ADDR,
283 DMA_START_ADDR_HI,
284 DMA_END_ADDR,
285 DMA_END_ADDR_HI,
286 DMA_MBUF_DONE_THRESH,
287 TDMA_FLOW_PERIOD,
288 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
289 TDMA_WRITE_PTR,
290 RDMA_READ_PTR = TDMA_WRITE_PTR,
291 TDMA_WRITE_PTR_HI,
292 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
293};
294
295/* GENET v4 supports 40-bits pointer addressing
296 * for obvious reasons the LO and HI word parts
297 * are contiguous, but this offsets the other
298 * registers.
299 */
300static const u8 genet_dma_ring_regs_v4[] = {
301 [TDMA_READ_PTR] = 0x00,
302 [TDMA_READ_PTR_HI] = 0x04,
303 [TDMA_CONS_INDEX] = 0x08,
304 [TDMA_PROD_INDEX] = 0x0C,
305 [DMA_RING_BUF_SIZE] = 0x10,
306 [DMA_START_ADDR] = 0x14,
307 [DMA_START_ADDR_HI] = 0x18,
308 [DMA_END_ADDR] = 0x1C,
309 [DMA_END_ADDR_HI] = 0x20,
310 [DMA_MBUF_DONE_THRESH] = 0x24,
311 [TDMA_FLOW_PERIOD] = 0x28,
312 [TDMA_WRITE_PTR] = 0x2C,
313 [TDMA_WRITE_PTR_HI] = 0x30,
314};
315
316static const u8 genet_dma_ring_regs_v123[] = {
317 [TDMA_READ_PTR] = 0x00,
318 [TDMA_CONS_INDEX] = 0x04,
319 [TDMA_PROD_INDEX] = 0x08,
320 [DMA_RING_BUF_SIZE] = 0x0C,
321 [DMA_START_ADDR] = 0x10,
322 [DMA_END_ADDR] = 0x14,
323 [DMA_MBUF_DONE_THRESH] = 0x18,
324 [TDMA_FLOW_PERIOD] = 0x1C,
325 [TDMA_WRITE_PTR] = 0x20,
326};
327
328/* Set at runtime once GENET version is known */
329static const u8 *genet_dma_ring_regs;
330
331static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 332 unsigned int ring,
333 enum dma_ring_reg r)
1c1008c7
FF		 334{
335 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
336 (DMA_RING_SIZE * ring) +
337 genet_dma_ring_regs[r]);
338}
339
340static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 341 unsigned int ring, u32 val,
342 enum dma_ring_reg r)
1c1008c7
FF		 343{
344 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
345 (DMA_RING_SIZE * ring) +
346 genet_dma_ring_regs[r]);
347}
348
349static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 368 struct ethtool_cmd *cmd)
1c1008c7
FF		 369{
370 struct bcmgenet_priv *priv = netdev_priv(dev);
371
372 if (!netif_running(dev))
373 return -EINVAL;
374
375 if (!priv->phydev)
376 return -ENODEV;
377
378 return phy_ethtool_gset(priv->phydev, cmd);
379}
380
381static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 382 struct ethtool_cmd *cmd)
1c1008c7
FF		 383{
384 struct bcmgenet_priv *priv = netdev_priv(dev);
385
386 if (!netif_running(dev))
387 return -EINVAL;
388
389 if (!priv->phydev)
390 return -ENODEV;
391
392 return phy_ethtool_sset(priv->phydev, cmd);
393}
394
395static int bcmgenet_set_rx_csum(struct net_device *dev,
396 netdev_features_t wanted)
397{
398 struct bcmgenet_priv *priv = netdev_priv(dev);
399 u32 rbuf_chk_ctrl;
400 bool rx_csum_en;
401
402 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
403
404 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
405
406 /* enable rx checksumming */
407 if (rx_csum_en)
408 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
409 else
410 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
411 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 412
413 /* If UniMAC forwards CRC, we need to skip over it to get
414 * a valid CHK bit to be set in the per-packet status word
415 */
416 if (rx_csum_en && priv->crc_fwd_en)
417 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
418 else
419 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
420
1c1008c7
FF		 421 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
422
423 return 0;
424}
425
426static int bcmgenet_set_tx_csum(struct net_device *dev,
427 netdev_features_t wanted)
428{
429 struct bcmgenet_priv *priv = netdev_priv(dev);
430 bool desc_64b_en;
431 u32 tbuf_ctrl, rbuf_ctrl;
432
433 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
434 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
435
436 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
437
438 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
439 if (desc_64b_en) {
440 tbuf_ctrl |= RBUF_64B_EN;
441 rbuf_ctrl |= RBUF_64B_EN;
442 } else {
443 tbuf_ctrl &= ~RBUF_64B_EN;
444 rbuf_ctrl &= ~RBUF_64B_EN;
445 }
446 priv->desc_64b_en = desc_64b_en;
447
448 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
449 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
450
451 return 0;
452}
453
454static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 455 netdev_features_t features)
1c1008c7
FF		 456{
457 netdev_features_t changed = features ^ dev->features;
458 netdev_features_t wanted = dev->wanted_features;
459 int ret = 0;
460
461 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
462 ret = bcmgenet_set_tx_csum(dev, wanted);
463 if (changed & (NETIF_F_RXCSUM))
464 ret = bcmgenet_set_rx_csum(dev, wanted);
465
466 return ret;
467}
468
469static u32 bcmgenet_get_msglevel(struct net_device *dev)
470{
471 struct bcmgenet_priv *priv = netdev_priv(dev);
472
473 return priv->msg_enable;
474}
475
476static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
477{
478 struct bcmgenet_priv *priv = netdev_priv(dev);
479
480 priv->msg_enable = level;
481}
482
483/* standard ethtool support functions. */
484enum bcmgenet_stat_type {
485 BCMGENET_STAT_NETDEV = -1,
486 BCMGENET_STAT_MIB_RX,
487 BCMGENET_STAT_MIB_TX,
488 BCMGENET_STAT_RUNT,
489 BCMGENET_STAT_MISC,
f62ba9c1 490 BCMGENET_STAT_SOFT,
1c1008c7
FF		 491};
492
493struct bcmgenet_stats {
494 char stat_string[ETH_GSTRING_LEN];
495 int stat_sizeof;
496 int stat_offset;
497 enum bcmgenet_stat_type type;
498 /* reg offset from UMAC base for misc counters */
499 u16 reg_offset;
500};
501
502#define STAT_NETDEV(m) { \
503 .stat_string = __stringify(m), \
504 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
505 .stat_offset = offsetof(struct net_device_stats, m), \
506 .type = BCMGENET_STAT_NETDEV, \
507}
508
509#define STAT_GENET_MIB(str, m, _type) { \
510 .stat_string = str, \
511 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
512 .stat_offset = offsetof(struct bcmgenet_priv, m), \
513 .type = _type, \
514}
515
516#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
517#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
518#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 519#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 520
521#define STAT_GENET_MISC(str, m, offset) { \
522 .stat_string = str, \
523 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
524 .stat_offset = offsetof(struct bcmgenet_priv, m), \
525 .type = BCMGENET_STAT_MISC, \
526 .reg_offset = offset, \
527}
528
529
530/* There is a 0xC gap between the end of RX and beginning of TX stats and then
531 * between the end of TX stats and the beginning of the RX RUNT
532 */
533#define BCMGENET_STAT_OFFSET 0xc
534
535/* Hardware counters must be kept in sync because the order/offset
536 * is important here (order in structure declaration = order in hardware)
537 */
538static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
539 /* general stats */
540 STAT_NETDEV(rx_packets),
541 STAT_NETDEV(tx_packets),
542 STAT_NETDEV(rx_bytes),
543 STAT_NETDEV(tx_bytes),
544 STAT_NETDEV(rx_errors),
545 STAT_NETDEV(tx_errors),
546 STAT_NETDEV(rx_dropped),
547 STAT_NETDEV(tx_dropped),
548 STAT_NETDEV(multicast),
549 /* UniMAC RSV counters */
550 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
551 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
552 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
553 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
554 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
555 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
556 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
557 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
558 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
559 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
560 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
561 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
562 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
563 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
564 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
565 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
566 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
567 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
568 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
569 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
570 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
571 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
572 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
573 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
574 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
575 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
576 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
577 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
578 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
579 /* UniMAC TSV counters */
580 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
581 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
582 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
583 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
584 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
585 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
586 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
587 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
588 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
589 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
590 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
591 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
592 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
593 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
594 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
595 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
596 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
597 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
598 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
599 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
600 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
601 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
602 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
603 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
604 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
605 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
606 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
607 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
608 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
609 /* UniMAC RUNT counters */
610 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
611 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
612 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
613 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
614 /* Misc UniMAC counters */
615 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
616 UMAC_RBUF_OVFL_CNT),
617 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
618 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 619 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
620 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
621 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 622};
623
624#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
625
626static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 627 struct ethtool_drvinfo *info)
1c1008c7
FF		 628{
629 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
630 strlcpy(info->version, "v2.0", sizeof(info->version));
631 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 632}
633
634static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
635{
636 switch (string_set) {
637 case ETH_SS_STATS:
638 return BCMGENET_STATS_LEN;
639 default:
640 return -EOPNOTSUPP;
641 }
642}
643
c91b7f66
FF		 644static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
645 u8 *data)
1c1008c7
FF		 646{
647 int i;
648
649 switch (stringset) {
650 case ETH_SS_STATS:
651 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
652 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 653 bcmgenet_gstrings_stats[i].stat_string,
654 ETH_GSTRING_LEN);
1c1008c7
FF		 655 }
656 break;
657 }
658}
659
660static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
661{
662 int i, j = 0;
663
664 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
665 const struct bcmgenet_stats *s;
666 u8 offset = 0;
667 u32 val = 0;
668 char *p;
669
670 s = &bcmgenet_gstrings_stats[i];
671 switch (s->type) {
672 case BCMGENET_STAT_NETDEV:
f62ba9c1 673 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 674 continue;
675 case BCMGENET_STAT_MIB_RX:
676 case BCMGENET_STAT_MIB_TX:
677 case BCMGENET_STAT_RUNT:
678 if (s->type != BCMGENET_STAT_MIB_RX)
679 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 680 val = bcmgenet_umac_readl(priv,
681 UMAC_MIB_START + j + offset);
1c1008c7
FF		 682 break;
683 case BCMGENET_STAT_MISC:
684 val = bcmgenet_umac_readl(priv, s->reg_offset);
685 /* clear if overflowed */
686 if (val == ~0)
687 bcmgenet_umac_writel(priv, 0, s->reg_offset);
688 break;
689 }
690
691 j += s->stat_sizeof;
692 p = (char *)priv + s->stat_offset;
693 *(u32 *)p = val;
694 }
695}
696
697static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 698 struct ethtool_stats *stats,
699 u64 *data)
1c1008c7
FF		 700{
701 struct bcmgenet_priv *priv = netdev_priv(dev);
702 int i;
703
704 if (netif_running(dev))
705 bcmgenet_update_mib_counters(priv);
706
707 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
708 const struct bcmgenet_stats *s;
709 char *p;
710
711 s = &bcmgenet_gstrings_stats[i];
712 if (s->type == BCMGENET_STAT_NETDEV)
713 p = (char *)&dev->stats;
714 else
715 p = (char *)priv;
716 p += s->stat_offset;
717 data[i] = *(u32 *)p;
718 }
719}
720
6ef398ea
FF		 721static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
722{
723 struct bcmgenet_priv *priv = netdev_priv(dev);
724 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
725 u32 reg;
726
727 if (enable && !priv->clk_eee_enabled) {
728 clk_prepare_enable(priv->clk_eee);
729 priv->clk_eee_enabled = true;
730 }
731
732 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
733 if (enable)
734 reg |= EEE_EN;
735 else
736 reg &= ~EEE_EN;
737 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
738
739 /* Enable EEE and switch to a 27Mhz clock automatically */
740 reg = __raw_readl(priv->base + off);
741 if (enable)
742 reg |= TBUF_EEE_EN | TBUF_PM_EN;
743 else
744 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
745 __raw_writel(reg, priv->base + off);
746
747 /* Do the same for thing for RBUF */
748 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
749 if (enable)
750 reg |= RBUF_EEE_EN | RBUF_PM_EN;
751 else
752 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
753 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
754
755 if (!enable && priv->clk_eee_enabled) {
756 clk_disable_unprepare(priv->clk_eee);
757 priv->clk_eee_enabled = false;
758 }
759
760 priv->eee.eee_enabled = enable;
761 priv->eee.eee_active = enable;
762}
763
764static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
765{
766 struct bcmgenet_priv *priv = netdev_priv(dev);
767 struct ethtool_eee *p = &priv->eee;
768
769 if (GENET_IS_V1(priv))
770 return -EOPNOTSUPP;
771
772 e->eee_enabled = p->eee_enabled;
773 e->eee_active = p->eee_active;
774 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
775
776 return phy_ethtool_get_eee(priv->phydev, e);
777}
778
779static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
780{
781 struct bcmgenet_priv *priv = netdev_priv(dev);
782 struct ethtool_eee *p = &priv->eee;
783 int ret = 0;
784
785 if (GENET_IS_V1(priv))
786 return -EOPNOTSUPP;
787
788 p->eee_enabled = e->eee_enabled;
789
790 if (!p->eee_enabled) {
791 bcmgenet_eee_enable_set(dev, false);
792 } else {
793 ret = phy_init_eee(priv->phydev, 0);
794 if (ret) {
795 netif_err(priv, hw, dev, "EEE initialization failed\n");
796 return ret;
797 }
798
799 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
800 bcmgenet_eee_enable_set(dev, true);
801 }
802
803 return phy_ethtool_set_eee(priv->phydev, e);
804}
805
6b0c5406
FF		 806static int bcmgenet_nway_reset(struct net_device *dev)
807{
808 struct bcmgenet_priv *priv = netdev_priv(dev);
809
810 return genphy_restart_aneg(priv->phydev);
811}
812
1c1008c7
FF		 813/* standard ethtool support functions. */
814static struct ethtool_ops bcmgenet_ethtool_ops = {
815 .get_strings = bcmgenet_get_strings,
816 .get_sset_count = bcmgenet_get_sset_count,
817 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
818 .get_settings = bcmgenet_get_settings,
819 .set_settings = bcmgenet_set_settings,
820 .get_drvinfo = bcmgenet_get_drvinfo,
821 .get_link = ethtool_op_get_link,
822 .get_msglevel = bcmgenet_get_msglevel,
823 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 824 .get_wol = bcmgenet_get_wol,
825 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 826 .get_eee = bcmgenet_get_eee,
827 .set_eee = bcmgenet_set_eee,
6b0c5406 828 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 829};
830
831/* Power down the unimac, based on mode. */
832static void bcmgenet_power_down(struct bcmgenet_priv *priv,
833 enum bcmgenet_power_mode mode)
834{
835 u32 reg;
836
837 switch (mode) {
838 case GENET_POWER_CABLE_SENSE:
80d8e96d 839 phy_detach(priv->phydev);
1c1008c7
FF		 840 break;
841
c3ae64ae
FF		 842 case GENET_POWER_WOL_MAGIC:
843 bcmgenet_wol_power_down_cfg(priv, mode);
844 break;
845
1c1008c7
FF		 846 case GENET_POWER_PASSIVE:
847 /* Power down LED */
1c1008c7
FF		 848 if (priv->hw_params->flags & GENET_HAS_EXT) {
849 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
850 reg |= (EXT_PWR_DOWN_PHY |
851 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
852 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
853 }
854 break;
855 default:
856 break;
857 }
858}
859
860static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 861 enum bcmgenet_power_mode mode)
1c1008c7
FF		 862{
863 u32 reg;
864
865 if (!(priv->hw_params->flags & GENET_HAS_EXT))
866 return;
867
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869
870 switch (mode) {
871 case GENET_POWER_PASSIVE:
872 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
873 EXT_PWR_DOWN_BIAS);
874 /* fallthrough */
875 case GENET_POWER_CABLE_SENSE:
876 /* enable APD */
877 reg |= EXT_PWR_DN_EN_LD;
878 break;
c3ae64ae
FF		 879 case GENET_POWER_WOL_MAGIC:
880 bcmgenet_wol_power_up_cfg(priv, mode);
881 return;
1c1008c7
FF		 882 default:
883 break;
884 }
885
886 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 887
888 if (mode == GENET_POWER_PASSIVE)
889 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 890}
891
892/* ioctl handle special commands that are not present in ethtool. */
893static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
894{
895 struct bcmgenet_priv *priv = netdev_priv(dev);
896 int val = 0;
897
898 if (!netif_running(dev))
899 return -EINVAL;
900
901 switch (cmd) {
902 case SIOCGMIIPHY:
903 case SIOCGMIIREG:
904 case SIOCSMIIREG:
905 if (!priv->phydev)
906 val = -ENODEV;
907 else
908 val = phy_mii_ioctl(priv->phydev, rq, cmd);
909 break;
910
911 default:
912 val = -EINVAL;
913 break;
914 }
915
916 return val;
917}
918
919static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
920 struct bcmgenet_tx_ring *ring)
921{
922 struct enet_cb *tx_cb_ptr;
923
924 tx_cb_ptr = ring->cbs;
925 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 926
1c1008c7
FF		 927 /* Advancing local write pointer */
928 if (ring->write_ptr == ring->end_ptr)
929 ring->write_ptr = ring->cb_ptr;
930 else
931 ring->write_ptr++;
932
933 return tx_cb_ptr;
934}
935
936/* Simple helper to free a control block's resources */
937static void bcmgenet_free_cb(struct enet_cb *cb)
938{
939 dev_kfree_skb_any(cb->skb);
940 cb->skb = NULL;
941 dma_unmap_addr_set(cb, dma_addr, 0);
942}
943
944static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
945 struct bcmgenet_tx_ring *ring)
946{
947 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 948 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
949 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 950}
951
952static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
953 struct bcmgenet_tx_ring *ring)
954{
955 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 956 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
957 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 958}
959
960static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 961 struct bcmgenet_tx_ring *ring)
1c1008c7 962{
c91b7f66
FF		 963 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
964 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 965 priv->int1_mask &= ~(1 << ring->index);
966}
967
968static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
969 struct bcmgenet_tx_ring *ring)
970{
c91b7f66
FF		 971 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
972 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 973 priv->int1_mask |= (1 << ring->index);
974}
975
976/* Unlocked version of the reclaim routine */
4092e6ac
JS		 977static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
978 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 979{
980 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 981 struct enet_cb *tx_cb_ptr;
b2cde2cc 982 struct netdev_queue *txq;
4092e6ac 983 unsigned int pkts_compl = 0;
1c1008c7 984 unsigned int c_index;
66d06757
PG		 985 unsigned int txbds_ready;
986 unsigned int txbds_processed = 0;
1c1008c7 987
7fc527f9 988 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 989 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 990 c_index &= DMA_C_INDEX_MASK;
1c1008c7 991
66d06757
PG		 992 if (likely(c_index >= ring->c_index))
993 txbds_ready = c_index - ring->c_index;
1c1008c7 994 else
66d06757 995 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 996
997 netif_dbg(priv, tx_done, dev,
66d06757
PG		 998 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
999 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1000
1001 /* Reclaim transmitted buffers */
66d06757
PG		 1002 while (txbds_processed < txbds_ready) {
1003 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1004 if (tx_cb_ptr->skb) {
4092e6ac 1005 pkts_compl++;
66d06757 1006 dev->stats.tx_packets++;
1c1008c7
FF		 1007 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1008 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1009 dma_unmap_addr(tx_cb_ptr, dma_addr),
1010 tx_cb_ptr->skb->len,
1011 DMA_TO_DEVICE);
1c1008c7
FF		 1012 bcmgenet_free_cb(tx_cb_ptr);
1013 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1014 dev->stats.tx_bytes +=
1015 dma_unmap_len(tx_cb_ptr, dma_len);
1016 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1017 dma_unmap_addr(tx_cb_ptr, dma_addr),
1018 dma_unmap_len(tx_cb_ptr, dma_len),
1019 DMA_TO_DEVICE);
1c1008c7
FF		 1020 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1021 }
1c1008c7 1022
66d06757
PG		 1023 txbds_processed++;
1024 if (likely(ring->clean_ptr < ring->end_ptr))
1025 ring->clean_ptr++;
1026 else
1027 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1028 }
1029
66d06757
PG		 1030 ring->free_bds += txbds_processed;
1031 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1032
4092e6ac 1033 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1034 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1035 if (netif_tx_queue_stopped(txq))
1036 netif_tx_wake_queue(txq);
1037 }
1c1008c7 1038
4092e6ac 1039 return pkts_compl;
1c1008c7
FF		 1040}
1041
4092e6ac 1042static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1043 struct bcmgenet_tx_ring *ring)
1c1008c7 1044{
4092e6ac 1045 unsigned int released;
1c1008c7
FF		 1046 unsigned long flags;
1047
1048 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1049 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1050 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1051
1052 return released;
1053}
1054
1055static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1056{
1057 struct bcmgenet_tx_ring *ring =
1058 container_of(napi, struct bcmgenet_tx_ring, napi);
1059 unsigned int work_done = 0;
1060
1061 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1062
1063 if (work_done == 0) {
1064 napi_complete(napi);
1065 ring->int_enable(ring->priv, ring);
1066
1067 return 0;
1068 }
1069
1070 return budget;
1c1008c7
FF		 1071}
1072
1073static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1074{
1075 struct bcmgenet_priv *priv = netdev_priv(dev);
1076 int i;
1077
1078 if (netif_is_multiqueue(dev)) {
1079 for (i = 0; i < priv->hw_params->tx_queues; i++)
1080 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1081 }
1082
1083 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1084}
1085
1086/* Transmits a single SKB (either head of a fragment or a single SKB)
1087 * caller must hold priv->lock
1088 */
1089static int bcmgenet_xmit_single(struct net_device *dev,
1090 struct sk_buff *skb,
1091 u16 dma_desc_flags,
1092 struct bcmgenet_tx_ring *ring)
1093{
1094 struct bcmgenet_priv *priv = netdev_priv(dev);
1095 struct device *kdev = &priv->pdev->dev;
1096 struct enet_cb *tx_cb_ptr;
1097 unsigned int skb_len;
1098 dma_addr_t mapping;
1099 u32 length_status;
1100 int ret;
1101
1102 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1103
1104 if (unlikely(!tx_cb_ptr))
1105 BUG();
1106
1107 tx_cb_ptr->skb = skb;
1108
1109 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1110
1111 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1112 ret = dma_mapping_error(kdev, mapping);
1113 if (ret) {
44c8bc3c 1114 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1115 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1116 dev_kfree_skb(skb);
1117 return ret;
1118 }
1119
1120 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1121 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1122 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1123 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1124 DMA_TX_APPEND_CRC;
1125
1126 if (skb->ip_summed == CHECKSUM_PARTIAL)
1127 length_status |= DMA_TX_DO_CSUM;
1128
1129 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1130
1131 /* Decrement total BD count and advance our write pointer */
1132 ring->free_bds -= 1;
1133 ring->prod_index += 1;
1134 ring->prod_index &= DMA_P_INDEX_MASK;
1135
1136 return 0;
1137}
1138
7fc527f9 1139/* Transmit a SKB fragment */
1c1008c7 1140static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1141 skb_frag_t *frag,
1142 u16 dma_desc_flags,
1143 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1144{
1145 struct bcmgenet_priv *priv = netdev_priv(dev);
1146 struct device *kdev = &priv->pdev->dev;
1147 struct enet_cb *tx_cb_ptr;
1148 dma_addr_t mapping;
1149 int ret;
1150
1151 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1152
1153 if (unlikely(!tx_cb_ptr))
1154 BUG();
1155 tx_cb_ptr->skb = NULL;
1156
1157 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1158 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1159 ret = dma_mapping_error(kdev, mapping);
1160 if (ret) {
44c8bc3c 1161 priv->mib.tx_dma_failed++;
1c1008c7 1162 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1163 __func__);
1c1008c7
FF		 1164 return ret;
1165 }
1166
1167 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1168 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1169
1170 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1171 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1172 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7
FF		 1173
1174
1175 ring->free_bds -= 1;
1176 ring->prod_index += 1;
1177 ring->prod_index &= DMA_P_INDEX_MASK;
1178
1179 return 0;
1180}
1181
1182/* Reallocate the SKB to put enough headroom in front of it and insert
1183 * the transmit checksum offsets in the descriptors
1184 */
bc23333b
PG		 1185static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1186 struct sk_buff *skb)
1c1008c7
FF		 1187{
1188 struct status_64 *status = NULL;
1189 struct sk_buff *new_skb;
1190 u16 offset;
1191 u8 ip_proto;
1192 u16 ip_ver;
1193 u32 tx_csum_info;
1194
1195 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1196 /* If 64 byte status block enabled, must make sure skb has
1197 * enough headroom for us to insert 64B status block.
1198 */
1199 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1200 dev_kfree_skb(skb);
1201 if (!new_skb) {
1202 dev->stats.tx_errors++;
1203 dev->stats.tx_dropped++;
bc23333b 1204 return NULL;
1c1008c7
FF		 1205 }
1206 skb = new_skb;
1207 }
1208
1209 skb_push(skb, sizeof(*status));
1210 status = (struct status_64 *)skb->data;
1211
1212 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1213 ip_ver = htons(skb->protocol);
1214 switch (ip_ver) {
1215 case ETH_P_IP:
1216 ip_proto = ip_hdr(skb)->protocol;
1217 break;
1218 case ETH_P_IPV6:
1219 ip_proto = ipv6_hdr(skb)->nexthdr;
1220 break;
1221 default:
bc23333b 1222 return skb;
1c1008c7
FF		 1223 }
1224
1225 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1226 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1227 (offset + skb->csum_offset);
1228
1229 /* Set the length valid bit for TCP and UDP and just set
1230 * the special UDP flag for IPv4, else just set to 0.
1231 */
1232 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1233 tx_csum_info |= STATUS_TX_CSUM_LV;
1234 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1235 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1236 } else {
1c1008c7 1237 tx_csum_info = 0;
8900ea57 1238 }
1c1008c7
FF		 1239
1240 status->tx_csum_info = tx_csum_info;
1241 }
1242
bc23333b 1243 return skb;
1c1008c7
FF		 1244}
1245
1246static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1247{
1248 struct bcmgenet_priv *priv = netdev_priv(dev);
1249 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1250 struct netdev_queue *txq;
1c1008c7
FF		 1251 unsigned long flags = 0;
1252 int nr_frags, index;
1253 u16 dma_desc_flags;
1254 int ret;
1255 int i;
1256
1257 index = skb_get_queue_mapping(skb);
1258 /* Mapping strategy:
1259 * queue_mapping = 0, unclassified, packet xmited through ring16
1260 * queue_mapping = 1, goes to ring 0. (highest priority queue
1261 * queue_mapping = 2, goes to ring 1.
1262 * queue_mapping = 3, goes to ring 2.
1263 * queue_mapping = 4, goes to ring 3.
1264 */
1265 if (index == 0)
1266 index = DESC_INDEX;
1267 else
1268 index -= 1;
1269
1c1008c7
FF		 1270 nr_frags = skb_shinfo(skb)->nr_frags;
1271 ring = &priv->tx_rings[index];
b2cde2cc 1272 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1273
1274 spin_lock_irqsave(&ring->lock, flags);
1275 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1276 netif_tx_stop_queue(txq);
1c1008c7 1277 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1278 __func__, index, ring->queue);
1c1008c7
FF		 1279 ret = NETDEV_TX_BUSY;
1280 goto out;
1281 }
1282
474ea9ca
FF		 1283 if (skb_padto(skb, ETH_ZLEN)) {
1284 ret = NETDEV_TX_OK;
1285 goto out;
1286 }
1287
1c1008c7
FF		 1288 /* set the SKB transmit checksum */
1289 if (priv->desc_64b_en) {
bc23333b
PG		 1290 skb = bcmgenet_put_tx_csum(dev, skb);
1291 if (!skb) {
1c1008c7
FF		 1292 ret = NETDEV_TX_OK;
1293 goto out;
1294 }
1295 }
1296
1297 dma_desc_flags = DMA_SOP;
1298 if (nr_frags == 0)
1299 dma_desc_flags |= DMA_EOP;
1300
1301 /* Transmit single SKB or head of fragment list */
1302 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1303 if (ret) {
1304 ret = NETDEV_TX_OK;
1305 goto out;
1306 }
1307
1308 /* xmit fragment */
1309 for (i = 0; i < nr_frags; i++) {
1310 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1311 &skb_shinfo(skb)->frags[i],
1312 (i == nr_frags - 1) ? DMA_EOP : 0,
1313 ring);
1c1008c7
FF		 1314 if (ret) {
1315 ret = NETDEV_TX_OK;
1316 goto out;
1317 }
1318 }
1319
d03825fb
FF		 1320 skb_tx_timestamp(skb);
1321
1c1008c7
FF		 1322 /* we kept a software copy of how much we should advance the TDMA
1323 * producer index, now write it down to the hardware
1324 */
1325 bcmgenet_tdma_ring_writel(priv, ring->index,
c91b7f66 1326 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7 1327
4092e6ac 1328 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1329 netif_tx_stop_queue(txq);
1c1008c7
FF		 1330
1331out:
1332 spin_unlock_irqrestore(&ring->lock, flags);
1333
1334 return ret;
1335}
1336
1337
c91b7f66 1338static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1c1008c7
FF		 1339{
1340 struct device *kdev = &priv->pdev->dev;
1341 struct sk_buff *skb;
1342 dma_addr_t mapping;
1343 int ret;
1344
c91b7f66 1345 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1c1008c7
FF		 1346 if (!skb)
1347 return -ENOMEM;
1348
1349 /* a caller did not release this control block */
1350 WARN_ON(cb->skb != NULL);
1351 cb->skb = skb;
1352 mapping = dma_map_single(kdev, skb->data,
c91b7f66 1353 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1354 ret = dma_mapping_error(kdev, mapping);
1355 if (ret) {
44c8bc3c 1356 priv->mib.rx_dma_failed++;
1c1008c7
FF		 1357 bcmgenet_free_cb(cb);
1358 netif_err(priv, rx_err, priv->dev,
c91b7f66 1359 "%s DMA map failed\n", __func__);
1c1008c7
FF		 1360 return ret;
1361 }
1362
1363 dma_unmap_addr_set(cb, dma_addr, mapping);
1364 /* assign packet, prepare descriptor, and advance pointer */
1365
1366 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1367
1368 /* turn on the newly assigned BD for DMA to use */
1369 priv->rx_bd_assign_index++;
1370 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1371
1372 priv->rx_bd_assign_ptr = priv->rx_bds +
1373 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1374
1375 return 0;
1376}
1377
1378/* bcmgenet_desc_rx - descriptor based rx process.
1379 * this could be called from bottom half, or from NAPI polling method.
1380 */
1381static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1382 unsigned int budget)
1383{
1384 struct net_device *dev = priv->dev;
1385 struct enet_cb *cb;
1386 struct sk_buff *skb;
1387 u32 dma_length_status;
1388 unsigned long dma_flag;
1389 int len, err;
1390 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1391 unsigned int p_index;
1392 unsigned int chksum_ok = 0;
1393
c91b7f66 1394 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1c1008c7
FF		 1395 p_index &= DMA_P_INDEX_MASK;
1396
1397 if (p_index < priv->rx_c_index)
1398 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1399 priv->rx_c_index + p_index;
1400 else
1401 rxpkttoprocess = p_index - priv->rx_c_index;
1402
1403 netif_dbg(priv, rx_status, dev,
c91b7f66 1404 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1405
1406 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1407 (rxpktprocessed < budget)) {
b629be5c
FF		 1408 cb = &priv->rx_cbs[priv->rx_read_ptr];
1409 skb = cb->skb;
1410
b629be5c
FF		 1411 /* We do not have a backing SKB, so we do not have a
1412 * corresponding DMA mapping for this incoming packet since
1413 * bcmgenet_rx_refill always either has both skb and mapping or
1414 * none.
1415 */
1416 if (unlikely(!skb)) {
1417 dev->stats.rx_dropped++;
1418 dev->stats.rx_errors++;
1419 goto refill;
1420 }
1421
1c1008c7
FF		 1422 /* Unmap the packet contents such that we can use the
1423 * RSV from the 64 bytes descriptor when enabled and save
1424 * a 32-bits register read
1425 */
1c1008c7 1426 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
c91b7f66 1427 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1428
1429 if (!priv->desc_64b_en) {
c91b7f66
FF		 1430 dma_length_status =
1431 dmadesc_get_length_status(priv,
1432 priv->rx_bds +
1433 (priv->rx_read_ptr *
1434 DMA_DESC_SIZE));
1c1008c7
FF		 1435 } else {
1436 struct status_64 *status;
164d4f20 1437
1c1008c7
FF		 1438 status = (struct status_64 *)skb->data;
1439 dma_length_status = status->length_status;
1440 }
1441
1442 /* DMA flags and length are still valid no matter how
1443 * we got the Receive Status Vector (64B RSB or register)
1444 */
1445 dma_flag = dma_length_status & 0xffff;
1446 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1447
1448 netif_dbg(priv, rx_status, dev,
c91b7f66
FF		 1449 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1450 __func__, p_index, priv->rx_c_index,
1451 priv->rx_read_ptr, dma_length_status);
1c1008c7 1452
1c1008c7
FF		 1453 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1454 netif_err(priv, rx_status, dev,
c91b7f66 1455 "dropping fragmented packet!\n");
1c1008c7
FF		 1456 dev->stats.rx_dropped++;
1457 dev->stats.rx_errors++;
1458 dev_kfree_skb_any(cb->skb);
1459 cb->skb = NULL;
1460 goto refill;
1461 }
1462 /* report errors */
1463 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1464 DMA_RX_OV |
1465 DMA_RX_NO |
1466 DMA_RX_LG |
1467 DMA_RX_RXER))) {
1468 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1469 (unsigned int)dma_flag);
1c1008c7
FF		 1470 if (dma_flag & DMA_RX_CRC_ERROR)
1471 dev->stats.rx_crc_errors++;
1472 if (dma_flag & DMA_RX_OV)
1473 dev->stats.rx_over_errors++;
1474 if (dma_flag & DMA_RX_NO)
1475 dev->stats.rx_frame_errors++;
1476 if (dma_flag & DMA_RX_LG)
1477 dev->stats.rx_length_errors++;
1478 dev->stats.rx_dropped++;
1479 dev->stats.rx_errors++;
1480
1481 /* discard the packet and advance consumer index.*/
1482 dev_kfree_skb_any(cb->skb);
1483 cb->skb = NULL;
1484 goto refill;
1485 } /* error packet */
1486
1487 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1488 priv->desc_rxchk_en;
1c1008c7
FF		 1489
1490 skb_put(skb, len);
1491 if (priv->desc_64b_en) {
1492 skb_pull(skb, 64);
1493 len -= 64;
1494 }
1495
1496 if (likely(chksum_ok))
1497 skb->ip_summed = CHECKSUM_UNNECESSARY;
1498
1499 /* remove hardware 2bytes added for IP alignment */
1500 skb_pull(skb, 2);
1501 len -= 2;
1502
1503 if (priv->crc_fwd_en) {
1504 skb_trim(skb, len - ETH_FCS_LEN);
1505 len -= ETH_FCS_LEN;
1506 }
1507
1508 /*Finish setting up the received SKB and send it to the kernel*/
1509 skb->protocol = eth_type_trans(skb, priv->dev);
1510 dev->stats.rx_packets++;
1511 dev->stats.rx_bytes += len;
1512 if (dma_flag & DMA_RX_MULT)
1513 dev->stats.multicast++;
1514
1515 /* Notify kernel */
1516 napi_gro_receive(&priv->napi, skb);
1517 cb->skb = NULL;
1518 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1519
1520 /* refill RX path on the current control block */
1521refill:
1522 err = bcmgenet_rx_refill(priv, cb);
44c8bc3c
FF		 1523 if (err) {
1524 priv->mib.alloc_rx_buff_failed++;
1c1008c7 1525 netif_err(priv, rx_err, dev, "Rx refill failed\n");
44c8bc3c 1526 }
cf377d88
FF		 1527
1528 rxpktprocessed++;
1529 priv->rx_read_ptr++;
1530 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1c1008c7
FF		 1531 }
1532
1533 return rxpktprocessed;
1534}
1535
1536/* Assign skb to RX DMA descriptor. */
1537static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1538{
1539 struct enet_cb *cb;
1540 int ret = 0;
1541 int i;
1542
1543 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1544
1545 /* loop here for each buffer needing assign */
1546 for (i = 0; i < priv->num_rx_bds; i++) {
1547 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1548 if (cb->skb)
1549 continue;
1550
1c1008c7
FF		 1551 ret = bcmgenet_rx_refill(priv, cb);
1552 if (ret)
1553 break;
1c1008c7
FF		 1554 }
1555
1556 return ret;
1557}
1558
1559static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1560{
1561 struct enet_cb *cb;
1562 int i;
1563
1564 for (i = 0; i < priv->num_rx_bds; i++) {
1565 cb = &priv->rx_cbs[i];
1566
1567 if (dma_unmap_addr(cb, dma_addr)) {
1568 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1569 dma_unmap_addr(cb, dma_addr),
1570 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1571 dma_unmap_addr_set(cb, dma_addr, 0);
1572 }
1573
1574 if (cb->skb)
1575 bcmgenet_free_cb(cb);
1576 }
1577}
1578
c91b7f66 1579static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1580{
1581 u32 reg;
1582
1583 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1584 if (enable)
1585 reg |= mask;
1586 else
1587 reg &= ~mask;
1588 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1589
1590 /* UniMAC stops on a packet boundary, wait for a full-size packet
1591 * to be processed
1592 */
1593 if (enable == 0)
1594 usleep_range(1000, 2000);
1595}
1596
1c1008c7
FF		 1597static int reset_umac(struct bcmgenet_priv *priv)
1598{
1599 struct device *kdev = &priv->pdev->dev;
1600 unsigned int timeout = 0;
1601 u32 reg;
1602
1603 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1604 bcmgenet_rbuf_ctrl_set(priv, 0);
1605 udelay(10);
1606
1607 /* disable MAC while updating its registers */
1608 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1609
1610 /* issue soft reset, wait for it to complete */
1611 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1612 while (timeout++ < 1000) {
1613 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1614 if (!(reg & CMD_SW_RESET))
1615 return 0;
1616
1617 udelay(1);
1618 }
1619
1620 if (timeout == 1000) {
1621 dev_err(kdev,
7fc527f9 1622 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1623 return -ETIMEDOUT;
1624 }
1625
1626 return 0;
1627}
1628
909ff5ef
FF		 1629static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1630{
1631 /* Mask all interrupts.*/
1632 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1633 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1634 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1635 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1636 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1637 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1638}
1639
1c1008c7
FF		 1640static int init_umac(struct bcmgenet_priv *priv)
1641{
1642 struct device *kdev = &priv->pdev->dev;
1643 int ret;
1644 u32 reg, cpu_mask_clear;
4092e6ac 1645 int index;
1c1008c7
FF		 1646
1647 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1648
1649 ret = reset_umac(priv);
1650 if (ret)
1651 return ret;
1652
1653 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1654 /* clear tx/rx counter */
1655 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1656 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1657 UMAC_MIB_CTRL);
1c1008c7
FF		 1658 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1659
1660 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1661
1662 /* init rx registers, enable ip header optimization */
1663 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1664 reg |= RBUF_ALIGN_2B;
1665 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1666
1667 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1668 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1669
909ff5ef 1670 bcmgenet_intr_disable(priv);
1c1008c7 1671
4092e6ac 1672 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_TXDMA_BDONE;
1c1008c7
FF		 1673
1674 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1675
7fc527f9 1676 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1677 if (phy_is_internal(priv->phydev)) {
1c1008c7 1678 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1679 } else if (priv->ext_phy) {
1c1008c7 1680 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1681 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1682 reg = bcmgenet_bp_mc_get(priv);
1683 reg |= BIT(priv->hw_params->bp_in_en_shift);
1684
1685 /* bp_mask: back pressure mask */
1686 if (netif_is_multiqueue(priv->dev))
1687 reg |= priv->hw_params->bp_in_mask;
1688 else
1689 reg &= ~priv->hw_params->bp_in_mask;
1690 bcmgenet_bp_mc_set(priv, reg);
1691 }
1692
1693 /* Enable MDIO interrupts on GENET v3+ */
1694 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1695 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1696
c91b7f66 1697 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7 1698
4092e6ac
JS		 1699 for (index = 0; index < priv->hw_params->tx_queues; index++)
1700 bcmgenet_intrl2_1_writel(priv, (1 << index),
1701 INTRL2_CPU_MASK_CLEAR);
1702
1c1008c7
FF		 1703 /* Enable rx/tx engine.*/
1704 dev_dbg(kdev, "done init umac\n");
1705
1706 return 0;
1707}
1708
4f8b2d7d 1709/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1710static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1711 unsigned int index, unsigned int size,
4f8b2d7d 1712 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1713{
1714 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1715 u32 words_per_bd = WORDS_PER_BD(priv);
1716 u32 flow_period_val = 0;
1c1008c7
FF		 1717
1718 spin_lock_init(&ring->lock);
4092e6ac
JS		 1719 ring->priv = priv;
1720 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1c1008c7
FF		 1721 ring->index = index;
1722 if (index == DESC_INDEX) {
1723 ring->queue = 0;
1724 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1725 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1726 } else {
1727 ring->queue = index + 1;
1728 ring->int_enable = bcmgenet_tx_ring_int_enable;
1729 ring->int_disable = bcmgenet_tx_ring_int_disable;
1730 }
4f8b2d7d 1731 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1732 ring->size = size;
66d06757 1733 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1734 ring->c_index = 0;
1735 ring->free_bds = size;
4f8b2d7d
PG		 1736 ring->write_ptr = start_ptr;
1737 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1738 ring->end_ptr = end_ptr - 1;
1739 ring->prod_index = 0;
1740
1741 /* Set flow period for ring != 16 */
1742 if (index != DESC_INDEX)
1743 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1744
1745 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1746 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1747 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1748 /* Disable rate control for now */
1749 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1750 TDMA_FLOW_PERIOD);
1c1008c7 1751 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1752 ((size << DMA_RING_SIZE_SHIFT) |
1753 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1754
1c1008c7 1755 /* Set start and end address, read and write pointers */
4f8b2d7d 1756 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1757 DMA_START_ADDR);
4f8b2d7d 1758 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1759 TDMA_READ_PTR);
4f8b2d7d 1760 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1761 TDMA_WRITE_PTR);
1c1008c7 1762 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1763 DMA_END_ADDR);
4092e6ac
JS		 1764
1765 napi_enable(&ring->napi);
1766}
1767
1768static void bcmgenet_fini_tx_ring(struct bcmgenet_priv *priv,
1769 unsigned int index)
1770{
1771 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1772
1773 napi_disable(&ring->napi);
1774 netif_napi_del(&ring->napi);
1c1008c7
FF		 1775}
1776
1777/* Initialize a RDMA ring */
1778static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
c91b7f66 1779 unsigned int index, unsigned int size)
1c1008c7
FF		 1780{
1781 u32 words_per_bd = WORDS_PER_BD(priv);
1782 int ret;
1783
1784 priv->num_rx_bds = TOTAL_DESC;
1785 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1786 priv->rx_bd_assign_ptr = priv->rx_bds;
1787 priv->rx_bd_assign_index = 0;
1788 priv->rx_c_index = 0;
1789 priv->rx_read_ptr = 0;
c489be08
FF		 1790 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1791 GFP_KERNEL);
1c1008c7
FF		 1792 if (!priv->rx_cbs)
1793 return -ENOMEM;
1794
1795 ret = bcmgenet_alloc_rx_buffers(priv);
1796 if (ret) {
1797 kfree(priv->rx_cbs);
1798 return ret;
1799 }
1800
1801 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1802 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1803 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1804 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1805 ((size << DMA_RING_SIZE_SHIFT) |
1806 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7
FF		 1807 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1808 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66 1809 words_per_bd * size - 1, DMA_END_ADDR);
1c1008c7 1810 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1811 (DMA_FC_THRESH_LO <<
1812 DMA_XOFF_THRESHOLD_SHIFT) |
1813 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1c1008c7
FF		 1814 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1815
1816 return ret;
1817}
1818
16c6d667 1819/* Initialize Tx queues
1c1008c7 1820 *
16c6d667 1821 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1822 * with queue 0 being the highest priority queue.
1823 *
16c6d667 1824 * Queue 16 is the default Tx queue with
51a966a7 1825 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1826 *
16c6d667
PG		 1827 * The transmit control block pool is then partitioned as follows:
1828 * - Tx queue 0 uses tx_cbs[0..31]
1829 * - Tx queue 1 uses tx_cbs[32..63]
1830 * - Tx queue 2 uses tx_cbs[64..95]
1831 * - Tx queue 3 uses tx_cbs[96..127]
1832 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1833 */
16c6d667 1834static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1835{
1836 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1837 u32 i, dma_enable;
1838 u32 dma_ctrl, ring_cfg;
37742166 1839 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1840
1c1008c7
FF		 1841 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1842 dma_enable = dma_ctrl & DMA_EN;
1843 dma_ctrl &= ~DMA_EN;
1844 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1845
16c6d667
PG		 1846 dma_ctrl = 0;
1847 ring_cfg = 0;
1848
1c1008c7
FF		 1849 /* Enable strict priority arbiter mode */
1850 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1851
16c6d667 1852 /* Initialize Tx priority queues */
1c1008c7 1853 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1854 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1855 i * priv->hw_params->tx_bds_per_q,
1856 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1857 ring_cfg |= (1 << i);
1858 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1859 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1860 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1861 }
1862
16c6d667 1863 /* Initialize Tx default queue 16 */
51a966a7 1864 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1865 priv->hw_params->tx_queues *
51a966a7 1866 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1867 TOTAL_DESC);
1868 ring_cfg |= (1 << DESC_INDEX);
1869 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1870 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1871 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1872 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1873
1874 /* Set Tx queue priorities */
37742166
PG		 1875 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1876 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1877 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1878
16c6d667
PG		 1879 /* Enable Tx queues */
1880 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1881
16c6d667 1882 /* Enable Tx DMA */
1c1008c7 1883 if (dma_enable)
16c6d667
PG		 1884 dma_ctrl |= DMA_EN;
1885 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 1886}
1887
4a0c081e
FF		 1888static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1889{
1890 int ret = 0;
1891 int timeout = 0;
1892 u32 reg;
1893
1894 /* Disable TDMA to stop add more frames in TX DMA */
1895 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1896 reg &= ~DMA_EN;
1897 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1898
1899 /* Check TDMA status register to confirm TDMA is disabled */
1900 while (timeout++ < DMA_TIMEOUT_VAL) {
1901 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1902 if (reg & DMA_DISABLED)
1903 break;
1904
1905 udelay(1);
1906 }
1907
1908 if (timeout == DMA_TIMEOUT_VAL) {
1909 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1910 ret = -ETIMEDOUT;
1911 }
1912
1913 /* Wait 10ms for packet drain in both tx and rx dma */
1914 usleep_range(10000, 20000);
1915
1916 /* Disable RDMA */
1917 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1918 reg &= ~DMA_EN;
1919 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1920
1921 timeout = 0;
1922 /* Check RDMA status register to confirm RDMA is disabled */
1923 while (timeout++ < DMA_TIMEOUT_VAL) {
1924 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1925 if (reg & DMA_DISABLED)
1926 break;
1927
1928 udelay(1);
1929 }
1930
1931 if (timeout == DMA_TIMEOUT_VAL) {
1932 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1933 ret = -ETIMEDOUT;
1934 }
1935
1936 return ret;
1937}
1938
4092e6ac 1939static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 1940{
1941 int i;
1942
1943 /* disable DMA */
4a0c081e 1944 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 1945
1946 for (i = 0; i < priv->num_tx_bds; i++) {
1947 if (priv->tx_cbs[i].skb != NULL) {
1948 dev_kfree_skb(priv->tx_cbs[i].skb);
1949 priv->tx_cbs[i].skb = NULL;
1950 }
1951 }
1952
1953 bcmgenet_free_rx_buffers(priv);
1954 kfree(priv->rx_cbs);
1955 kfree(priv->tx_cbs);
1956}
1957
4092e6ac
JS		 1958static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1959{
1960 int i;
1961
1962 bcmgenet_fini_tx_ring(priv, DESC_INDEX);
1963
1964 for (i = 0; i < priv->hw_params->tx_queues; i++)
1965 bcmgenet_fini_tx_ring(priv, i);
1966
1967 __bcmgenet_fini_dma(priv);
1968}
1969
1c1008c7
FF		 1970/* init_edma: Initialize DMA control register */
1971static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1972{
1973 int ret;
014012a4
PG		 1974 unsigned int i;
1975 struct enet_cb *cb;
1c1008c7
FF		 1976
1977 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1978
1979 /* by default, enable ring 16 (descriptor based) */
1980 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1981 if (ret) {
1982 netdev_err(priv->dev, "failed to initialize RX ring\n");
1983 return ret;
1984 }
1985
1986 /* init rDma */
1987 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1988
1989 /* Init tDma */
1990 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1991
7fc527f9 1992 /* Initialize common TX ring structures */
1c1008c7
FF		 1993 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1994 priv->num_tx_bds = TOTAL_DESC;
c489be08 1995 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 1996 GFP_KERNEL);
1c1008c7 1997 if (!priv->tx_cbs) {
4092e6ac 1998 __bcmgenet_fini_dma(priv);
1c1008c7
FF		 1999 return -ENOMEM;
2000 }
2001
014012a4
PG		 2002 for (i = 0; i < priv->num_tx_bds; i++) {
2003 cb = priv->tx_cbs + i;
2004 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2005 }
2006
16c6d667
PG		 2007 /* Initialize Tx queues */
2008 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2009
2010 return 0;
2011}
2012
2013/* NAPI polling method*/
2014static int bcmgenet_poll(struct napi_struct *napi, int budget)
2015{
2016 struct bcmgenet_priv *priv = container_of(napi,
2017 struct bcmgenet_priv, napi);
2018 unsigned int work_done;
2019
1c1008c7
FF		 2020 work_done = bcmgenet_desc_rx(priv, budget);
2021
2022 /* Advancing our consumer index*/
2023 priv->rx_c_index += work_done;
2024 priv->rx_c_index &= DMA_C_INDEX_MASK;
2025 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
c91b7f66 2026 priv->rx_c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 2027 if (work_done < budget) {
2028 napi_complete(napi);
c91b7f66
FF		 2029 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2030 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 2031 }
2032
2033 return work_done;
2034}
2035
2036/* Interrupt bottom half */
2037static void bcmgenet_irq_task(struct work_struct *work)
2038{
2039 struct bcmgenet_priv *priv = container_of(
2040 work, struct bcmgenet_priv, bcmgenet_irq_work);
2041
2042 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2043
8fdb0e0f
FF		 2044 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2045 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2046 netif_dbg(priv, wol, priv->dev,
2047 "magic packet detected, waking up\n");
2048 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2049 }
2050
1c1008c7
FF		 2051 /* Link UP/DOWN event */
2052 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2053 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 2054 phy_mac_interrupt(priv->phydev,
c91b7f66 2055 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2056 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2057 }
2058}
2059
2060/* bcmgenet_isr1: interrupt handler for ring buffer. */
2061static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2062{
2063 struct bcmgenet_priv *priv = dev_id;
4092e6ac 2064 struct bcmgenet_tx_ring *ring;
1c1008c7
FF		 2065 unsigned int index;
2066
2067 /* Save irq status for bottom-half processing. */
2068 priv->irq1_stat =
2069 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2070 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2071 /* clear interrupts */
1c1008c7
FF		 2072 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2073
2074 netif_dbg(priv, intr, priv->dev,
c91b7f66 2075 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2076
1c1008c7
FF		 2077 /* Check the MBDONE interrupts.
2078 * packet is done, reclaim descriptors
2079 */
4092e6ac
JS		 2080 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2081 if (!(priv->irq1_stat & BIT(index)))
2082 continue;
2083
2084 ring = &priv->tx_rings[index];
2085
2086 if (likely(napi_schedule_prep(&ring->napi))) {
2087 ring->int_disable(priv, ring);
2088 __napi_schedule(&ring->napi);
1c1008c7
FF		 2089 }
2090 }
4092e6ac 2091
1c1008c7
FF		 2092 return IRQ_HANDLED;
2093}
2094
2095/* bcmgenet_isr0: Handle various interrupts. */
2096static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2097{
2098 struct bcmgenet_priv *priv = dev_id;
2099
2100 /* Save irq status for bottom-half processing. */
2101 priv->irq0_stat =
2102 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2103 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2104 /* clear interrupts */
1c1008c7
FF		 2105 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2106
2107 netif_dbg(priv, intr, priv->dev,
c91b7f66 2108 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2109
2110 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2111 /* We use NAPI(software interrupt throttling, if
2112 * Rx Descriptor throttling is not used.
2113 * Disable interrupt, will be enabled in the poll method.
2114 */
2115 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 2116 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2117 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2118 __napi_schedule(&priv->napi);
2119 }
2120 }
2121 if (priv->irq0_stat &
2122 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
4092e6ac
JS		 2123 struct bcmgenet_tx_ring *ring = &priv->tx_rings[DESC_INDEX];
2124
2125 if (likely(napi_schedule_prep(&ring->napi))) {
2126 ring->int_disable(priv, ring);
2127 __napi_schedule(&ring->napi);
2128 }
1c1008c7
FF		 2129 }
2130 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2131 UMAC_IRQ_PHY_DET_F |
2132 UMAC_IRQ_LINK_UP |
2133 UMAC_IRQ_LINK_DOWN |
2134 UMAC_IRQ_HFB_SM |
2135 UMAC_IRQ_HFB_MM |
2136 UMAC_IRQ_MPD_R)) {
2137 /* all other interested interrupts handled in bottom half */
2138 schedule_work(&priv->bcmgenet_irq_work);
2139 }
2140
2141 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2142 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2143 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2144 wake_up(&priv->wq);
2145 }
2146
2147 return IRQ_HANDLED;
2148}
2149
8562056f
FF		 2150static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2151{
2152 struct bcmgenet_priv *priv = dev_id;
2153
2154 pm_wakeup_event(&priv->pdev->dev, 0);
2155
2156 return IRQ_HANDLED;
2157}
2158
1c1008c7
FF		 2159static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2160{
2161 u32 reg;
2162
2163 reg = bcmgenet_rbuf_ctrl_get(priv);
2164 reg |= BIT(1);
2165 bcmgenet_rbuf_ctrl_set(priv, reg);
2166 udelay(10);
2167
2168 reg &= ~BIT(1);
2169 bcmgenet_rbuf_ctrl_set(priv, reg);
2170 udelay(10);
2171}
2172
2173static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2174 unsigned char *addr)
1c1008c7
FF		 2175{
2176 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2177 (addr[2] << 8) | addr[3], UMAC_MAC0);
2178 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2179}
2180
1c1008c7
FF		 2181/* Returns a reusable dma control register value */
2182static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2183{
2184 u32 reg;
2185 u32 dma_ctrl;
2186
2187 /* disable DMA */
2188 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2189 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2190 reg &= ~dma_ctrl;
2191 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2192
2193 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2194 reg &= ~dma_ctrl;
2195 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2196
2197 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2198 udelay(10);
2199 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2200
2201 return dma_ctrl;
2202}
2203
2204static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2205{
2206 u32 reg;
2207
2208 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2209 reg |= dma_ctrl;
2210 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2211
2212 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2213 reg |= dma_ctrl;
2214 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2215}
2216
909ff5ef
FF		 2217static void bcmgenet_netif_start(struct net_device *dev)
2218{
2219 struct bcmgenet_priv *priv = netdev_priv(dev);
2220
2221 /* Start the network engine */
2222 napi_enable(&priv->napi);
2223
2224 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2225
2226 if (phy_is_internal(priv->phydev))
2227 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2228
2229 netif_tx_start_all_queues(dev);
2230
2231 phy_start(priv->phydev);
2232}
2233
1c1008c7
FF		 2234static int bcmgenet_open(struct net_device *dev)
2235{
2236 struct bcmgenet_priv *priv = netdev_priv(dev);
2237 unsigned long dma_ctrl;
2238 u32 reg;
2239 int ret;
2240
2241 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2242
2243 /* Turn on the clock */
2244 if (!IS_ERR(priv->clk))
2245 clk_prepare_enable(priv->clk);
2246
2247 /* take MAC out of reset */
2248 bcmgenet_umac_reset(priv);
2249
2250 ret = init_umac(priv);
2251 if (ret)
2252 goto err_clk_disable;
2253
2254 /* disable ethernet MAC while updating its registers */
e29585b8 2255 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2256
909ff5ef
FF		 2257 /* Make sure we reflect the value of CRC_CMD_FWD */
2258 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2259 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2260
1c1008c7
FF		 2261 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2262
1c1008c7
FF		 2263 if (phy_is_internal(priv->phydev)) {
2264 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2265 reg |= EXT_ENERGY_DET_MASK;
2266 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2267 }
2268
2269 /* Disable RX/TX DMA and flush TX queues */
2270 dma_ctrl = bcmgenet_dma_disable(priv);
2271
2272 /* Reinitialize TDMA and RDMA and SW housekeeping */
2273 ret = bcmgenet_init_dma(priv);
2274 if (ret) {
2275 netdev_err(dev, "failed to initialize DMA\n");
2276 goto err_fini_dma;
2277 }
2278
2279 /* Always enable ring 16 - descriptor ring */
2280 bcmgenet_enable_dma(priv, dma_ctrl);
2281
2282 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2283 dev->name, priv);
1c1008c7
FF		 2284 if (ret < 0) {
2285 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2286 goto err_fini_dma;
2287 }
2288
2289 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2290 dev->name, priv);
1c1008c7
FF		 2291 if (ret < 0) {
2292 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2293 goto err_irq0;
2294 }
2295
dbd479db
FF		 2296 /* Re-configure the port multiplexer towards the PHY device */
2297 bcmgenet_mii_config(priv->dev, false);
2298
c96e731c
FF		 2299 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2300 priv->phy_interface);
2301
909ff5ef 2302 bcmgenet_netif_start(dev);
1c1008c7
FF		 2303
2304 return 0;
2305
2306err_irq0:
2307 free_irq(priv->irq0, dev);
2308err_fini_dma:
2309 bcmgenet_fini_dma(priv);
2310err_clk_disable:
2311 if (!IS_ERR(priv->clk))
2312 clk_disable_unprepare(priv->clk);
2313 return ret;
2314}
2315
909ff5ef
FF		 2316static void bcmgenet_netif_stop(struct net_device *dev)
2317{
2318 struct bcmgenet_priv *priv = netdev_priv(dev);
2319
2320 netif_tx_stop_all_queues(dev);
2321 napi_disable(&priv->napi);
2322 phy_stop(priv->phydev);
2323
2324 bcmgenet_intr_disable(priv);
2325
2326 /* Wait for pending work items to complete. Since interrupts are
2327 * disabled no new work will be scheduled.
2328 */
2329 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2330
cc013fb4 2331 priv->old_link = -1;
5ad6e6c5 2332 priv->old_speed = -1;
cc013fb4 2333 priv->old_duplex = -1;
5ad6e6c5 2334 priv->old_pause = -1;
909ff5ef
FF		 2335}
2336
1c1008c7
FF		 2337static int bcmgenet_close(struct net_device *dev)
2338{
2339 struct bcmgenet_priv *priv = netdev_priv(dev);
2340 int ret;
1c1008c7
FF		 2341
2342 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2343
909ff5ef 2344 bcmgenet_netif_stop(dev);
1c1008c7 2345
c96e731c
FF		 2346 /* Really kill the PHY state machine and disconnect from it */
2347 phy_disconnect(priv->phydev);
2348
1c1008c7 2349 /* Disable MAC receive */
e29585b8 2350 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2351
1c1008c7
FF		 2352 ret = bcmgenet_dma_teardown(priv);
2353 if (ret)
2354 return ret;
2355
2356 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2357 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2358
1c1008c7
FF		 2359 /* tx reclaim */
2360 bcmgenet_tx_reclaim_all(dev);
2361 bcmgenet_fini_dma(priv);
2362
2363 free_irq(priv->irq0, priv);
2364 free_irq(priv->irq1, priv);
2365
1c1008c7
FF		 2366 if (phy_is_internal(priv->phydev))
2367 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2368
1c1008c7
FF		 2369 if (!IS_ERR(priv->clk))
2370 clk_disable_unprepare(priv->clk);
2371
2372 return 0;
2373}
2374
2375static void bcmgenet_timeout(struct net_device *dev)
2376{
2377 struct bcmgenet_priv *priv = netdev_priv(dev);
2378
2379 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2380
2381 dev->trans_start = jiffies;
2382
2383 dev->stats.tx_errors++;
2384
2385 netif_tx_wake_all_queues(dev);
2386}
2387
2388#define MAX_MC_COUNT 16
2389
2390static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2391 unsigned char *addr,
2392 int *i,
2393 int *mc)
2394{
2395 u32 reg;
2396
c91b7f66
FF		 2397 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2398 UMAC_MDF_ADDR + (*i * 4));
2399 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2400 addr[4] << 8 | addr[5],
2401 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2402 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2403 reg |= (1 << (MAX_MC_COUNT - *mc));
2404 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2405 *i += 2;
2406 (*mc)++;
2407}
2408
2409static void bcmgenet_set_rx_mode(struct net_device *dev)
2410{
2411 struct bcmgenet_priv *priv = netdev_priv(dev);
2412 struct netdev_hw_addr *ha;
2413 int i, mc;
2414 u32 reg;
2415
2416 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2417
7fc527f9 2418 /* Promiscuous mode */
1c1008c7
FF		 2419 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2420 if (dev->flags & IFF_PROMISC) {
2421 reg |= CMD_PROMISC;
2422 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2423 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2424 return;
2425 } else {
2426 reg &= ~CMD_PROMISC;
2427 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2428 }
2429
2430 /* UniMac doesn't support ALLMULTI */
2431 if (dev->flags & IFF_ALLMULTI) {
2432 netdev_warn(dev, "ALLMULTI is not supported\n");
2433 return;
2434 }
2435
2436 /* update MDF filter */
2437 i = 0;
2438 mc = 0;
2439 /* Broadcast */
2440 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2441 /* my own address.*/
2442 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2443 /* Unicast list*/
2444 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2445 return;
2446
2447 if (!netdev_uc_empty(dev))
2448 netdev_for_each_uc_addr(ha, dev)
2449 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2450 /* Multicast */
2451 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2452 return;
2453
2454 netdev_for_each_mc_addr(ha, dev)
2455 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2456}
2457
2458/* Set the hardware MAC address. */
2459static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2460{
2461 struct sockaddr *addr = p;
2462
2463 /* Setting the MAC address at the hardware level is not possible
2464 * without disabling the UniMAC RX/TX enable bits.
2465 */
2466 if (netif_running(dev))
2467 return -EBUSY;
2468
2469 ether_addr_copy(dev->dev_addr, addr->sa_data);
2470
2471 return 0;
2472}
2473
1c1008c7
FF		 2474static const struct net_device_ops bcmgenet_netdev_ops = {
2475 .ndo_open = bcmgenet_open,
2476 .ndo_stop = bcmgenet_close,
2477 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2478 .ndo_tx_timeout = bcmgenet_timeout,
2479 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2480 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2481 .ndo_do_ioctl = bcmgenet_ioctl,
2482 .ndo_set_features = bcmgenet_set_features,
2483};
2484
2485/* Array of GENET hardware parameters/characteristics */
2486static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2487 [GENET_V1] = {
2488 .tx_queues = 0,
51a966a7 2489 .tx_bds_per_q = 0,
1c1008c7 2490 .rx_queues = 0,
1c1008c7
FF		 2491 .bp_in_en_shift = 16,
2492 .bp_in_mask = 0xffff,
2493 .hfb_filter_cnt = 16,
2494 .qtag_mask = 0x1F,
2495 .hfb_offset = 0x1000,
2496 .rdma_offset = 0x2000,
2497 .tdma_offset = 0x3000,
2498 .words_per_bd = 2,
2499 },
2500 [GENET_V2] = {
2501 .tx_queues = 4,
51a966a7 2502 .tx_bds_per_q = 32,
7e906e02 2503 .rx_queues = 0,
1c1008c7
FF		 2504 .bp_in_en_shift = 16,
2505 .bp_in_mask = 0xffff,
2506 .hfb_filter_cnt = 16,
2507 .qtag_mask = 0x1F,
2508 .tbuf_offset = 0x0600,
2509 .hfb_offset = 0x1000,
2510 .hfb_reg_offset = 0x2000,
2511 .rdma_offset = 0x3000,
2512 .tdma_offset = 0x4000,
2513 .words_per_bd = 2,
2514 .flags = GENET_HAS_EXT,
2515 },
2516 [GENET_V3] = {
2517 .tx_queues = 4,
51a966a7 2518 .tx_bds_per_q = 32,
7e906e02 2519 .rx_queues = 0,
1c1008c7
FF		 2520 .bp_in_en_shift = 17,
2521 .bp_in_mask = 0x1ffff,
2522 .hfb_filter_cnt = 48,
2523 .qtag_mask = 0x3F,
2524 .tbuf_offset = 0x0600,
2525 .hfb_offset = 0x8000,
2526 .hfb_reg_offset = 0xfc00,
2527 .rdma_offset = 0x10000,
2528 .tdma_offset = 0x11000,
2529 .words_per_bd = 2,
2530 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2531 },
2532 [GENET_V4] = {
2533 .tx_queues = 4,
51a966a7 2534 .tx_bds_per_q = 32,
7e906e02 2535 .rx_queues = 0,
1c1008c7
FF		 2536 .bp_in_en_shift = 17,
2537 .bp_in_mask = 0x1ffff,
2538 .hfb_filter_cnt = 48,
2539 .qtag_mask = 0x3F,
2540 .tbuf_offset = 0x0600,
2541 .hfb_offset = 0x8000,
2542 .hfb_reg_offset = 0xfc00,
2543 .rdma_offset = 0x2000,
2544 .tdma_offset = 0x4000,
2545 .words_per_bd = 3,
2546 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2547 },
2548};
2549
2550/* Infer hardware parameters from the detected GENET version */
2551static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2552{
2553 struct bcmgenet_hw_params *params;
2554 u32 reg;
2555 u8 major;
b04a2f5b 2556 u16 gphy_rev;
1c1008c7
FF		 2557
2558 if (GENET_IS_V4(priv)) {
2559 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2560 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2561 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2562 priv->version = GENET_V4;
2563 } else if (GENET_IS_V3(priv)) {
2564 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2565 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2566 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2567 priv->version = GENET_V3;
2568 } else if (GENET_IS_V2(priv)) {
2569 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2570 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2571 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2572 priv->version = GENET_V2;
2573 } else if (GENET_IS_V1(priv)) {
2574 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2575 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2576 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2577 priv->version = GENET_V1;
2578 }
2579
2580 /* enum genet_version starts at 1 */
2581 priv->hw_params = &bcmgenet_hw_params[priv->version];
2582 params = priv->hw_params;
2583
2584 /* Read GENET HW version */
2585 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2586 major = (reg >> 24 & 0x0f);
2587 if (major == 5)
2588 major = 4;
2589 else if (major == 0)
2590 major = 1;
2591 if (major != priv->version) {
2592 dev_err(&priv->pdev->dev,
2593 "GENET version mismatch, got: %d, configured for: %d\n",
2594 major, priv->version);
2595 }
2596
2597 /* Print the GENET core version */
2598 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2599 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2600
487320c5
FF		 2601 /* Store the integrated PHY revision for the MDIO probing function
2602 * to pass this information to the PHY driver. The PHY driver expects
2603 * to find the PHY major revision in bits 15:8 while the GENET register
2604 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2605 *
2606 * On newer chips, starting with PHY revision G0, a new scheme is
2607 * deployed similar to the Starfighter 2 switch with GPHY major
2608 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2609 * is reserved as well as special value 0x01ff, we have a small
2610 * heuristic to check for the new GPHY revision and re-arrange things
2611 * so the GPHY driver is happy.
487320c5 2612 */
b04a2f5b
FF		 2613 gphy_rev = reg & 0xffff;
2614
2615 /* This is the good old scheme, just GPHY major, no minor nor patch */
2616 if ((gphy_rev & 0xf0) != 0)
2617 priv->gphy_rev = gphy_rev << 8;
2618
2619 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2620 else if ((gphy_rev & 0xff00) != 0)
2621 priv->gphy_rev = gphy_rev;
2622
2623 /* This is reserved so should require special treatment */
2624 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2625 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2626 return;
2627 }
487320c5 2628
1c1008c7
FF		 2629#ifdef CONFIG_PHYS_ADDR_T_64BIT
2630 if (!(params->flags & GENET_HAS_40BITS))
2631 pr_warn("GENET does not support 40-bits PA\n");
2632#endif
2633
2634 pr_debug("Configuration for version: %d\n"
51a966a7 2635 "TXq: %1d, TXqBDs: %1d, RXq: %1d\n"
1c1008c7
FF		 2636 "BP << en: %2d, BP msk: 0x%05x\n"
2637 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2638 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2639 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2640 "Words/BD: %d\n",
2641 priv->version,
51a966a7
PG		 2642 params->tx_queues, params->tx_bds_per_q,
2643 params->rx_queues,
1c1008c7
FF		 2644 params->bp_in_en_shift, params->bp_in_mask,
2645 params->hfb_filter_cnt, params->qtag_mask,
2646 params->tbuf_offset, params->hfb_offset,
2647 params->hfb_reg_offset,
2648 params->rdma_offset, params->tdma_offset,
2649 params->words_per_bd);
2650}
2651
2652static const struct of_device_id bcmgenet_match[] = {
2653 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2654 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2655 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2656 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2657 { },
2658};
2659
2660static int bcmgenet_probe(struct platform_device *pdev)
2661{
b0ba512e 2662 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2663 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2664 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2665 struct bcmgenet_priv *priv;
2666 struct net_device *dev;
2667 const void *macaddr;
2668 struct resource *r;
2669 int err = -EIO;
2670
2671 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2672 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2673 if (!dev) {
2674 dev_err(&pdev->dev, "can't allocate net device\n");
2675 return -ENOMEM;
2676 }
2677
b0ba512e
PG		 2678 if (dn) {
2679 of_id = of_match_node(bcmgenet_match, dn);
2680 if (!of_id)
2681 return -EINVAL;
2682 }
1c1008c7
FF		 2683
2684 priv = netdev_priv(dev);
2685 priv->irq0 = platform_get_irq(pdev, 0);
2686 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2687 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2688 if (!priv->irq0 || !priv->irq1) {
2689 dev_err(&pdev->dev, "can't find IRQs\n");
2690 err = -EINVAL;
2691 goto err;
2692 }
2693
b0ba512e
PG		 2694 if (dn) {
2695 macaddr = of_get_mac_address(dn);
2696 if (!macaddr) {
2697 dev_err(&pdev->dev, "can't find MAC address\n");
2698 err = -EINVAL;
2699 goto err;
2700 }
2701 } else {
2702 macaddr = pd->mac_address;
1c1008c7
FF		 2703 }
2704
2705 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2706 priv->base = devm_ioremap_resource(&pdev->dev, r);
2707 if (IS_ERR(priv->base)) {
2708 err = PTR_ERR(priv->base);
1c1008c7
FF		 2709 goto err;
2710 }
2711
2712 SET_NETDEV_DEV(dev, &pdev->dev);
2713 dev_set_drvdata(&pdev->dev, dev);
2714 ether_addr_copy(dev->dev_addr, macaddr);
2715 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2716 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2717 dev->netdev_ops = &bcmgenet_netdev_ops;
2718 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2719
2720 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2721
2722 /* Set hardware features */
2723 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2724 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2725
8562056f
FF		 2726 /* Request the WOL interrupt and advertise suspend if available */
2727 priv->wol_irq_disabled = true;
2728 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2729 dev->name, priv);
2730 if (!err)
2731 device_set_wakeup_capable(&pdev->dev, 1);
2732
1c1008c7
FF		 2733 /* Set the needed headroom to account for any possible
2734 * features enabling/disabling at runtime
2735 */
2736 dev->needed_headroom += 64;
2737
2738 netdev_boot_setup_check(dev);
2739
2740 priv->dev = dev;
2741 priv->pdev = pdev;
b0ba512e
PG		 2742 if (of_id)
2743 priv->version = (enum bcmgenet_version)of_id->data;
2744 else
2745 priv->version = pd->genet_version;
1c1008c7 2746
e4a60a93
FF		 2747 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2748 if (IS_ERR(priv->clk))
2749 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2750
2751 if (!IS_ERR(priv->clk))
2752 clk_prepare_enable(priv->clk);
2753
1c1008c7
FF		 2754 bcmgenet_set_hw_params(priv);
2755
1c1008c7
FF		 2756 /* Mii wait queue */
2757 init_waitqueue_head(&priv->wq);
2758 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2759 priv->rx_buf_len = RX_BUF_LENGTH;
2760 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2761
1c1008c7
FF		 2762 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2763 if (IS_ERR(priv->clk_wol))
2764 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2765
6ef398ea
FF		 2766 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2767 if (IS_ERR(priv->clk_eee)) {
2768 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2769 priv->clk_eee = NULL;
2770 }
2771
1c1008c7
FF		 2772 err = reset_umac(priv);
2773 if (err)
2774 goto err_clk_disable;
2775
2776 err = bcmgenet_mii_init(dev);
2777 if (err)
2778 goto err_clk_disable;
2779
2780 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2781 * just the ring 16 descriptor based TX
2782 */
2783 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2784 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2785
219575eb
FF		 2786 /* libphy will determine the link state */
2787 netif_carrier_off(dev);
2788
1c1008c7
FF		 2789 /* Turn off the main clock, WOL clock is handled separately */
2790 if (!IS_ERR(priv->clk))
2791 clk_disable_unprepare(priv->clk);
2792
0f50ce96
FF		 2793 err = register_netdev(dev);
2794 if (err)
2795 goto err;
2796
1c1008c7
FF		 2797 return err;
2798
2799err_clk_disable:
2800 if (!IS_ERR(priv->clk))
2801 clk_disable_unprepare(priv->clk);
2802err:
2803 free_netdev(dev);
2804 return err;
2805}
2806
2807static int bcmgenet_remove(struct platform_device *pdev)
2808{
2809 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2810
2811 dev_set_drvdata(&pdev->dev, NULL);
2812 unregister_netdev(priv->dev);
2813 bcmgenet_mii_exit(priv->dev);
2814 free_netdev(priv->dev);
2815
2816 return 0;
2817}
2818
b6e978e5
FF		 2819#ifdef CONFIG_PM_SLEEP
2820static int bcmgenet_suspend(struct device *d)
2821{
2822 struct net_device *dev = dev_get_drvdata(d);
2823 struct bcmgenet_priv *priv = netdev_priv(dev);
2824 int ret;
2825
2826 if (!netif_running(dev))
2827 return 0;
2828
2829 bcmgenet_netif_stop(dev);
2830
cc013fb4
FF		 2831 phy_suspend(priv->phydev);
2832
b6e978e5
FF		 2833 netif_device_detach(dev);
2834
2835 /* Disable MAC receive */
2836 umac_enable_set(priv, CMD_RX_EN, false);
2837
2838 ret = bcmgenet_dma_teardown(priv);
2839 if (ret)
2840 return ret;
2841
2842 /* Disable MAC transmit. TX DMA disabled have to done before this */
2843 umac_enable_set(priv, CMD_TX_EN, false);
2844
2845 /* tx reclaim */
2846 bcmgenet_tx_reclaim_all(dev);
2847 bcmgenet_fini_dma(priv);
2848
8c90db72
FF		 2849 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2850 if (device_may_wakeup(d) && priv->wolopts) {
2851 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2852 clk_prepare_enable(priv->clk_wol);
2853 }
2854
b6e978e5
FF		 2855 /* Turn off the clocks */
2856 clk_disable_unprepare(priv->clk);
2857
2858 return 0;
2859}
2860
2861static int bcmgenet_resume(struct device *d)
2862{
2863 struct net_device *dev = dev_get_drvdata(d);
2864 struct bcmgenet_priv *priv = netdev_priv(dev);
2865 unsigned long dma_ctrl;
2866 int ret;
2867 u32 reg;
2868
2869 if (!netif_running(dev))
2870 return 0;
2871
2872 /* Turn on the clock */
2873 ret = clk_prepare_enable(priv->clk);
2874 if (ret)
2875 return ret;
2876
2877 bcmgenet_umac_reset(priv);
2878
2879 ret = init_umac(priv);
2880 if (ret)
2881 goto out_clk_disable;
2882
0a29b3da
TK		 2883 /* From WOL-enabled suspend, switch to regular clock */
2884 if (priv->wolopts)
2885 clk_disable_unprepare(priv->clk_wol);
2886
2887 phy_init_hw(priv->phydev);
2888 /* Speed settings must be restored */
dbd479db 2889 bcmgenet_mii_config(priv->dev, false);
8c90db72 2890
b6e978e5
FF		 2891 /* disable ethernet MAC while updating its registers */
2892 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2893
2894 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2895
2896 if (phy_is_internal(priv->phydev)) {
2897 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2898 reg |= EXT_ENERGY_DET_MASK;
2899 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2900 }
2901
98bb7399
FF		 2902 if (priv->wolopts)
2903 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2904
b6e978e5
FF		 2905 /* Disable RX/TX DMA and flush TX queues */
2906 dma_ctrl = bcmgenet_dma_disable(priv);
2907
2908 /* Reinitialize TDMA and RDMA and SW housekeeping */
2909 ret = bcmgenet_init_dma(priv);
2910 if (ret) {
2911 netdev_err(dev, "failed to initialize DMA\n");
2912 goto out_clk_disable;
2913 }
2914
2915 /* Always enable ring 16 - descriptor ring */
2916 bcmgenet_enable_dma(priv, dma_ctrl);
2917
2918 netif_device_attach(dev);
2919
cc013fb4
FF		 2920 phy_resume(priv->phydev);
2921
6ef398ea
FF		 2922 if (priv->eee.eee_enabled)
2923 bcmgenet_eee_enable_set(dev, true);
2924
b6e978e5
FF		 2925 bcmgenet_netif_start(dev);
2926
2927 return 0;
2928
2929out_clk_disable:
2930 clk_disable_unprepare(priv->clk);
2931 return ret;
2932}
2933#endif /* CONFIG_PM_SLEEP */
2934
2935static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2936
1c1008c7
FF		 2937static struct platform_driver bcmgenet_driver = {
2938 .probe = bcmgenet_probe,
2939 .remove = bcmgenet_remove,
2940 .driver = {
2941 .name = "bcmgenet",
1c1008c7 2942 .of_match_table = bcmgenet_match,
b6e978e5 2943 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 2944 },
2945};
2946module_platform_driver(bcmgenet_driver);
2947
2948MODULE_AUTHOR("Broadcom Corporation");
2949MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2950MODULE_ALIAS("platform:bcmgenet");
2951MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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