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net: bcmgenet: propagate errors from bcmgenet_power_down
[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
CommitLineData
1c1008c7
FF		 1/*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
1c1008c7
FF		 9 */
10
11#define pr_fmt(fmt) "bcmgenet: " fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/types.h>
17#include <linux/fcntl.h>
18#include <linux/interrupt.h>
19#include <linux/string.h>
20#include <linux/if_ether.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/dma-mapping.h>
26#include <linux/pm.h>
27#include <linux/clk.h>
1c1008c7
FF		 28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_net.h>
32#include <linux/of_platform.h>
33#include <net/arp.h>
34
35#include <linux/mii.h>
36#include <linux/ethtool.h>
37#include <linux/netdevice.h>
38#include <linux/inetdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/in.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/phy.h>
b0ba512e 45#include <linux/platform_data/bcmgenet.h>
1c1008c7
FF		 46
47#include <asm/unaligned.h>
48
49#include "bcmgenet.h"
50
51/* Maximum number of hardware queues, downsized if needed */
52#define GENET_MAX_MQ_CNT 4
53
54/* Default highest priority queue for multi queue support */
55#define GENET_Q0_PRIORITY 0
56
3feafa02
PG		 57#define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
51a966a7
PG		 59#define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
1c1008c7
FF		 61
62#define RX_BUF_LENGTH 2048
63#define SKB_ALIGNMENT 32
64
65/* Tx/Rx DMA register offset, skip 256 descriptors */
66#define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
c91b7f66 76 void __iomem *d, u32 value)
1c1008c7
FF		 77{
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79}
80
81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
c91b7f66 82 void __iomem *d)
1c1008c7
FF		 83{
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85}
86
87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90{
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
7fc527f9 95 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 96 */
97#ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100#endif
101}
102
103/* Combined address + length/status setter */
104static inline void dmadesc_set(struct bcmgenet_priv *priv,
c91b7f66 105 void __iomem *d, dma_addr_t addr, u32 val)
1c1008c7
FF		 106{
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109}
110
111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113{
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
7fc527f9 120 * the platform is explicitly configured for 64-bits/LPAE.
1c1008c7
FF		 121 */
122#ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125#endif
126 return addr;
127}
128
129#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135{
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140}
141
142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143{
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148}
149
150/* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155{
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161}
162
163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164{
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170}
171
172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173{
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179}
180
181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182{
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188}
189
190/* RX/TX DMA register accessors */
191enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
37742166
PG		 197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
0034de41
PG		 200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
1c1008c7
FF		 208};
209
210static const u8 bcmgenet_dma_regs_v3plus[] = {
211 [DMA_RING_CFG] = 0x00,
212 [DMA_CTRL] = 0x04,
213 [DMA_STATUS] = 0x08,
214 [DMA_SCB_BURST_SIZE] = 0x0C,
215 [DMA_ARB_CTRL] = 0x2C,
37742166
PG		 216 [DMA_PRIORITY_0] = 0x30,
217 [DMA_PRIORITY_1] = 0x34,
218 [DMA_PRIORITY_2] = 0x38,
0034de41
PG		 219 [DMA_INDEX2RING_0] = 0x70,
220 [DMA_INDEX2RING_1] = 0x74,
221 [DMA_INDEX2RING_2] = 0x78,
222 [DMA_INDEX2RING_3] = 0x7C,
223 [DMA_INDEX2RING_4] = 0x80,
224 [DMA_INDEX2RING_5] = 0x84,
225 [DMA_INDEX2RING_6] = 0x88,
226 [DMA_INDEX2RING_7] = 0x8C,
1c1008c7
FF		 227};
228
229static const u8 bcmgenet_dma_regs_v2[] = {
230 [DMA_RING_CFG] = 0x00,
231 [DMA_CTRL] = 0x04,
232 [DMA_STATUS] = 0x08,
233 [DMA_SCB_BURST_SIZE] = 0x0C,
234 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 235 [DMA_PRIORITY_0] = 0x34,
236 [DMA_PRIORITY_1] = 0x38,
237 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 238};
239
240static const u8 bcmgenet_dma_regs_v1[] = {
241 [DMA_CTRL] = 0x00,
242 [DMA_STATUS] = 0x04,
243 [DMA_SCB_BURST_SIZE] = 0x0C,
244 [DMA_ARB_CTRL] = 0x30,
37742166
PG		 245 [DMA_PRIORITY_0] = 0x34,
246 [DMA_PRIORITY_1] = 0x38,
247 [DMA_PRIORITY_2] = 0x3C,
1c1008c7
FF		 248};
249
250/* Set at runtime once bcmgenet version is known */
251static const u8 *bcmgenet_dma_regs;
252
253static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
254{
255 return netdev_priv(dev_get_drvdata(dev));
256}
257
258static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
c91b7f66 259 enum dma_reg r)
1c1008c7
FF		 260{
261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263}
264
265static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267{
268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270}
271
272static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
c91b7f66 273 enum dma_reg r)
1c1008c7
FF		 274{
275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
277}
278
279static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
280 u32 val, enum dma_reg r)
281{
282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
284}
285
286/* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
289 */
290enum dma_ring_reg {
291 TDMA_READ_PTR = 0,
292 RDMA_WRITE_PTR = TDMA_READ_PTR,
293 TDMA_READ_PTR_HI,
294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
295 TDMA_CONS_INDEX,
296 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
297 TDMA_PROD_INDEX,
298 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
299 DMA_RING_BUF_SIZE,
300 DMA_START_ADDR,
301 DMA_START_ADDR_HI,
302 DMA_END_ADDR,
303 DMA_END_ADDR_HI,
304 DMA_MBUF_DONE_THRESH,
305 TDMA_FLOW_PERIOD,
306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
307 TDMA_WRITE_PTR,
308 RDMA_READ_PTR = TDMA_WRITE_PTR,
309 TDMA_WRITE_PTR_HI,
310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
311};
312
313/* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
316 * registers.
317 */
318static const u8 genet_dma_ring_regs_v4[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_READ_PTR_HI] = 0x04,
321 [TDMA_CONS_INDEX] = 0x08,
322 [TDMA_PROD_INDEX] = 0x0C,
323 [DMA_RING_BUF_SIZE] = 0x10,
324 [DMA_START_ADDR] = 0x14,
325 [DMA_START_ADDR_HI] = 0x18,
326 [DMA_END_ADDR] = 0x1C,
327 [DMA_END_ADDR_HI] = 0x20,
328 [DMA_MBUF_DONE_THRESH] = 0x24,
329 [TDMA_FLOW_PERIOD] = 0x28,
330 [TDMA_WRITE_PTR] = 0x2C,
331 [TDMA_WRITE_PTR_HI] = 0x30,
332};
333
334static const u8 genet_dma_ring_regs_v123[] = {
335 [TDMA_READ_PTR] = 0x00,
336 [TDMA_CONS_INDEX] = 0x04,
337 [TDMA_PROD_INDEX] = 0x08,
338 [DMA_RING_BUF_SIZE] = 0x0C,
339 [DMA_START_ADDR] = 0x10,
340 [DMA_END_ADDR] = 0x14,
341 [DMA_MBUF_DONE_THRESH] = 0x18,
342 [TDMA_FLOW_PERIOD] = 0x1C,
343 [TDMA_WRITE_PTR] = 0x20,
344};
345
346/* Set at runtime once GENET version is known */
347static const u8 *genet_dma_ring_regs;
348
349static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 350 unsigned int ring,
351 enum dma_ring_reg r)
1c1008c7
FF		 352{
353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356}
357
358static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
1c1008c7
FF		 361{
362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365}
366
367static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
c91b7f66
FF		 368 unsigned int ring,
369 enum dma_ring_reg r)
1c1008c7
FF		 370{
371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
372 (DMA_RING_SIZE * ring) +
373 genet_dma_ring_regs[r]);
374}
375
376static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
c91b7f66
FF		 377 unsigned int ring, u32 val,
378 enum dma_ring_reg r)
1c1008c7
FF		 379{
380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
381 (DMA_RING_SIZE * ring) +
382 genet_dma_ring_regs[r]);
383}
384
385static int bcmgenet_get_settings(struct net_device *dev,
c91b7f66 386 struct ethtool_cmd *cmd)
1c1008c7
FF		 387{
388 struct bcmgenet_priv *priv = netdev_priv(dev);
389
390 if (!netif_running(dev))
391 return -EINVAL;
392
393 if (!priv->phydev)
394 return -ENODEV;
395
396 return phy_ethtool_gset(priv->phydev, cmd);
397}
398
399static int bcmgenet_set_settings(struct net_device *dev,
c91b7f66 400 struct ethtool_cmd *cmd)
1c1008c7
FF		 401{
402 struct bcmgenet_priv *priv = netdev_priv(dev);
403
404 if (!netif_running(dev))
405 return -EINVAL;
406
407 if (!priv->phydev)
408 return -ENODEV;
409
410 return phy_ethtool_sset(priv->phydev, cmd);
411}
412
413static int bcmgenet_set_rx_csum(struct net_device *dev,
414 netdev_features_t wanted)
415{
416 struct bcmgenet_priv *priv = netdev_priv(dev);
417 u32 rbuf_chk_ctrl;
418 bool rx_csum_en;
419
420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
421
422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
423
424 /* enable rx checksumming */
425 if (rx_csum_en)
426 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
427 else
428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
429 priv->desc_rxchk_en = rx_csum_en;
ebe5e3c6
FF		 430
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
433 */
434 if (rx_csum_en && priv->crc_fwd_en)
435 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
436 else
437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
438
1c1008c7
FF		 439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
440
441 return 0;
442}
443
444static int bcmgenet_set_tx_csum(struct net_device *dev,
445 netdev_features_t wanted)
446{
447 struct bcmgenet_priv *priv = netdev_priv(dev);
448 bool desc_64b_en;
449 u32 tbuf_ctrl, rbuf_ctrl;
450
451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
453
454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
455
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
457 if (desc_64b_en) {
458 tbuf_ctrl |= RBUF_64B_EN;
459 rbuf_ctrl |= RBUF_64B_EN;
460 } else {
461 tbuf_ctrl &= ~RBUF_64B_EN;
462 rbuf_ctrl &= ~RBUF_64B_EN;
463 }
464 priv->desc_64b_en = desc_64b_en;
465
466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
468
469 return 0;
470}
471
472static int bcmgenet_set_features(struct net_device *dev,
c91b7f66 473 netdev_features_t features)
1c1008c7
FF		 474{
475 netdev_features_t changed = features ^ dev->features;
476 netdev_features_t wanted = dev->wanted_features;
477 int ret = 0;
478
479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
480 ret = bcmgenet_set_tx_csum(dev, wanted);
481 if (changed & (NETIF_F_RXCSUM))
482 ret = bcmgenet_set_rx_csum(dev, wanted);
483
484 return ret;
485}
486
487static u32 bcmgenet_get_msglevel(struct net_device *dev)
488{
489 struct bcmgenet_priv *priv = netdev_priv(dev);
490
491 return priv->msg_enable;
492}
493
494static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
495{
496 struct bcmgenet_priv *priv = netdev_priv(dev);
497
498 priv->msg_enable = level;
499}
500
501/* standard ethtool support functions. */
502enum bcmgenet_stat_type {
503 BCMGENET_STAT_NETDEV = -1,
504 BCMGENET_STAT_MIB_RX,
505 BCMGENET_STAT_MIB_TX,
506 BCMGENET_STAT_RUNT,
507 BCMGENET_STAT_MISC,
f62ba9c1 508 BCMGENET_STAT_SOFT,
1c1008c7
FF		 509};
510
511struct bcmgenet_stats {
512 char stat_string[ETH_GSTRING_LEN];
513 int stat_sizeof;
514 int stat_offset;
515 enum bcmgenet_stat_type type;
516 /* reg offset from UMAC base for misc counters */
517 u16 reg_offset;
518};
519
520#define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
525}
526
527#define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
531 .type = _type, \
532}
533
534#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
f62ba9c1 537#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1c1008c7
FF		 538
539#define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
545}
546
547
548/* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
550 */
551#define BCMGENET_STAT_OFFSET 0xc
552
553/* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
555 */
556static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
557 /* general stats */
558 STAT_NETDEV(rx_packets),
559 STAT_NETDEV(tx_packets),
560 STAT_NETDEV(rx_bytes),
561 STAT_NETDEV(tx_bytes),
562 STAT_NETDEV(rx_errors),
563 STAT_NETDEV(tx_errors),
564 STAT_NETDEV(rx_dropped),
565 STAT_NETDEV(tx_dropped),
566 STAT_NETDEV(multicast),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
634 UMAC_RBUF_OVFL_CNT),
635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
f62ba9c1
FF		 637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1c1008c7
FF		 640};
641
642#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
643
644static void bcmgenet_get_drvinfo(struct net_device *dev,
c91b7f66 645 struct ethtool_drvinfo *info)
1c1008c7
FF		 646{
647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
648 strlcpy(info->version, "v2.0", sizeof(info->version));
649 info->n_stats = BCMGENET_STATS_LEN;
1c1008c7
FF		 650}
651
652static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
653{
654 switch (string_set) {
655 case ETH_SS_STATS:
656 return BCMGENET_STATS_LEN;
657 default:
658 return -EOPNOTSUPP;
659 }
660}
661
c91b7f66
FF		 662static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
663 u8 *data)
1c1008c7
FF		 664{
665 int i;
666
667 switch (stringset) {
668 case ETH_SS_STATS:
669 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
670 memcpy(data + i * ETH_GSTRING_LEN,
c91b7f66
FF		 671 bcmgenet_gstrings_stats[i].stat_string,
672 ETH_GSTRING_LEN);
1c1008c7
FF		 673 }
674 break;
675 }
676}
677
678static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
679{
680 int i, j = 0;
681
682 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
683 const struct bcmgenet_stats *s;
684 u8 offset = 0;
685 u32 val = 0;
686 char *p;
687
688 s = &bcmgenet_gstrings_stats[i];
689 switch (s->type) {
690 case BCMGENET_STAT_NETDEV:
f62ba9c1 691 case BCMGENET_STAT_SOFT:
1c1008c7
FF		 692 continue;
693 case BCMGENET_STAT_MIB_RX:
694 case BCMGENET_STAT_MIB_TX:
695 case BCMGENET_STAT_RUNT:
696 if (s->type != BCMGENET_STAT_MIB_RX)
697 offset = BCMGENET_STAT_OFFSET;
c91b7f66
FF		 698 val = bcmgenet_umac_readl(priv,
699 UMAC_MIB_START + j + offset);
1c1008c7
FF		 700 break;
701 case BCMGENET_STAT_MISC:
702 val = bcmgenet_umac_readl(priv, s->reg_offset);
703 /* clear if overflowed */
704 if (val == ~0)
705 bcmgenet_umac_writel(priv, 0, s->reg_offset);
706 break;
707 }
708
709 j += s->stat_sizeof;
710 p = (char *)priv + s->stat_offset;
711 *(u32 *)p = val;
712 }
713}
714
715static void bcmgenet_get_ethtool_stats(struct net_device *dev,
c91b7f66
FF		 716 struct ethtool_stats *stats,
717 u64 *data)
1c1008c7
FF		 718{
719 struct bcmgenet_priv *priv = netdev_priv(dev);
720 int i;
721
722 if (netif_running(dev))
723 bcmgenet_update_mib_counters(priv);
724
725 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
726 const struct bcmgenet_stats *s;
727 char *p;
728
729 s = &bcmgenet_gstrings_stats[i];
730 if (s->type == BCMGENET_STAT_NETDEV)
731 p = (char *)&dev->stats;
732 else
733 p = (char *)priv;
734 p += s->stat_offset;
735 data[i] = *(u32 *)p;
736 }
737}
738
6ef398ea
FF		 739static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
740{
741 struct bcmgenet_priv *priv = netdev_priv(dev);
742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
743 u32 reg;
744
745 if (enable && !priv->clk_eee_enabled) {
746 clk_prepare_enable(priv->clk_eee);
747 priv->clk_eee_enabled = true;
748 }
749
750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
751 if (enable)
752 reg |= EEE_EN;
753 else
754 reg &= ~EEE_EN;
755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
756
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg = __raw_readl(priv->base + off);
759 if (enable)
760 reg |= TBUF_EEE_EN | TBUF_PM_EN;
761 else
762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
763 __raw_writel(reg, priv->base + off);
764
765 /* Do the same for thing for RBUF */
766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
767 if (enable)
768 reg |= RBUF_EEE_EN | RBUF_PM_EN;
769 else
770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
772
773 if (!enable && priv->clk_eee_enabled) {
774 clk_disable_unprepare(priv->clk_eee);
775 priv->clk_eee_enabled = false;
776 }
777
778 priv->eee.eee_enabled = enable;
779 priv->eee.eee_active = enable;
780}
781
782static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
783{
784 struct bcmgenet_priv *priv = netdev_priv(dev);
785 struct ethtool_eee *p = &priv->eee;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 e->eee_enabled = p->eee_enabled;
791 e->eee_active = p->eee_active;
792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
793
794 return phy_ethtool_get_eee(priv->phydev, e);
795}
796
797static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
798{
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 struct ethtool_eee *p = &priv->eee;
801 int ret = 0;
802
803 if (GENET_IS_V1(priv))
804 return -EOPNOTSUPP;
805
806 p->eee_enabled = e->eee_enabled;
807
808 if (!p->eee_enabled) {
809 bcmgenet_eee_enable_set(dev, false);
810 } else {
811 ret = phy_init_eee(priv->phydev, 0);
812 if (ret) {
813 netif_err(priv, hw, dev, "EEE initialization failed\n");
814 return ret;
815 }
816
817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
818 bcmgenet_eee_enable_set(dev, true);
819 }
820
821 return phy_ethtool_set_eee(priv->phydev, e);
822}
823
6b0c5406
FF		 824static int bcmgenet_nway_reset(struct net_device *dev)
825{
826 struct bcmgenet_priv *priv = netdev_priv(dev);
827
828 return genphy_restart_aneg(priv->phydev);
829}
830
1c1008c7
FF		 831/* standard ethtool support functions. */
832static struct ethtool_ops bcmgenet_ethtool_ops = {
833 .get_strings = bcmgenet_get_strings,
834 .get_sset_count = bcmgenet_get_sset_count,
835 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
836 .get_settings = bcmgenet_get_settings,
837 .set_settings = bcmgenet_set_settings,
838 .get_drvinfo = bcmgenet_get_drvinfo,
839 .get_link = ethtool_op_get_link,
840 .get_msglevel = bcmgenet_get_msglevel,
841 .set_msglevel = bcmgenet_set_msglevel,
06ba8375
FF		 842 .get_wol = bcmgenet_get_wol,
843 .set_wol = bcmgenet_set_wol,
6ef398ea
FF		 844 .get_eee = bcmgenet_get_eee,
845 .set_eee = bcmgenet_set_eee,
6b0c5406 846 .nway_reset = bcmgenet_nway_reset,
1c1008c7
FF		 847};
848
849/* Power down the unimac, based on mode. */
ca8cf341 850static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1c1008c7
FF		 851 enum bcmgenet_power_mode mode)
852{
ca8cf341 853 int ret = 0;
1c1008c7
FF		 854 u32 reg;
855
856 switch (mode) {
857 case GENET_POWER_CABLE_SENSE:
80d8e96d 858 phy_detach(priv->phydev);
1c1008c7
FF		 859 break;
860
c3ae64ae 861 case GENET_POWER_WOL_MAGIC:
ca8cf341 862 ret = bcmgenet_wol_power_down_cfg(priv, mode);
c3ae64ae
FF		 863 break;
864
1c1008c7
FF		 865 case GENET_POWER_PASSIVE:
866 /* Power down LED */
1c1008c7
FF		 867 if (priv->hw_params->flags & GENET_HAS_EXT) {
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869 reg |= (EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
872 }
873 break;
874 default:
875 break;
876 }
ca8cf341
FF		 877
878 return 0;
1c1008c7
FF		 879}
880
881static void bcmgenet_power_up(struct bcmgenet_priv *priv,
c91b7f66 882 enum bcmgenet_power_mode mode)
1c1008c7
FF		 883{
884 u32 reg;
885
886 if (!(priv->hw_params->flags & GENET_HAS_EXT))
887 return;
888
889 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
890
891 switch (mode) {
892 case GENET_POWER_PASSIVE:
893 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
894 EXT_PWR_DOWN_BIAS);
895 /* fallthrough */
896 case GENET_POWER_CABLE_SENSE:
897 /* enable APD */
898 reg |= EXT_PWR_DN_EN_LD;
899 break;
c3ae64ae
FF		 900 case GENET_POWER_WOL_MAGIC:
901 bcmgenet_wol_power_up_cfg(priv, mode);
902 return;
1c1008c7
FF		 903 default:
904 break;
905 }
906
907 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
cc013fb4
FF		 908
909 if (mode == GENET_POWER_PASSIVE)
910 bcmgenet_mii_reset(priv->dev);
1c1008c7
FF		 911}
912
913/* ioctl handle special commands that are not present in ethtool. */
914static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
915{
916 struct bcmgenet_priv *priv = netdev_priv(dev);
917 int val = 0;
918
919 if (!netif_running(dev))
920 return -EINVAL;
921
922 switch (cmd) {
923 case SIOCGMIIPHY:
924 case SIOCGMIIREG:
925 case SIOCSMIIREG:
926 if (!priv->phydev)
927 val = -ENODEV;
928 else
929 val = phy_mii_ioctl(priv->phydev, rq, cmd);
930 break;
931
932 default:
933 val = -EINVAL;
934 break;
935 }
936
937 return val;
938}
939
940static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
941 struct bcmgenet_tx_ring *ring)
942{
943 struct enet_cb *tx_cb_ptr;
944
945 tx_cb_ptr = ring->cbs;
946 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
014012a4 947
1c1008c7
FF		 948 /* Advancing local write pointer */
949 if (ring->write_ptr == ring->end_ptr)
950 ring->write_ptr = ring->cb_ptr;
951 else
952 ring->write_ptr++;
953
954 return tx_cb_ptr;
955}
956
957/* Simple helper to free a control block's resources */
958static void bcmgenet_free_cb(struct enet_cb *cb)
959{
960 dev_kfree_skb_any(cb->skb);
961 cb->skb = NULL;
962 dma_unmap_addr_set(cb, dma_addr, 0);
963}
964
965static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
966 struct bcmgenet_tx_ring *ring)
967{
968 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 969 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
970 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 971}
972
973static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
974 struct bcmgenet_tx_ring *ring)
975{
976 bcmgenet_intrl2_0_writel(priv,
c91b7f66
FF		 977 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
978 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 979}
980
981static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
c91b7f66 982 struct bcmgenet_tx_ring *ring)
1c1008c7 983{
c91b7f66
FF		 984 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
985 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 986 priv->int1_mask &= ~(1 << ring->index);
987}
988
989static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
990 struct bcmgenet_tx_ring *ring)
991{
c91b7f66
FF		 992 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
993 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 994 priv->int1_mask |= (1 << ring->index);
995}
996
997/* Unlocked version of the reclaim routine */
4092e6ac
JS		 998static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
999 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1000{
1001 struct bcmgenet_priv *priv = netdev_priv(dev);
1c1008c7 1002 struct enet_cb *tx_cb_ptr;
b2cde2cc 1003 struct netdev_queue *txq;
4092e6ac 1004 unsigned int pkts_compl = 0;
1c1008c7 1005 unsigned int c_index;
66d06757
PG		 1006 unsigned int txbds_ready;
1007 unsigned int txbds_processed = 0;
1c1008c7 1008
7fc527f9 1009 /* Compute how many buffers are transmitted since last xmit call */
1c1008c7 1010 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
66d06757 1011 c_index &= DMA_C_INDEX_MASK;
1c1008c7 1012
66d06757
PG		 1013 if (likely(c_index >= ring->c_index))
1014 txbds_ready = c_index - ring->c_index;
1c1008c7 1015 else
66d06757 1016 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1c1008c7
FF		 1017
1018 netif_dbg(priv, tx_done, dev,
66d06757
PG		 1019 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1020 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1c1008c7
FF		 1021
1022 /* Reclaim transmitted buffers */
66d06757
PG		 1023 while (txbds_processed < txbds_ready) {
1024 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1c1008c7 1025 if (tx_cb_ptr->skb) {
4092e6ac 1026 pkts_compl++;
66d06757 1027 dev->stats.tx_packets++;
1c1008c7
FF		 1028 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1029 dma_unmap_single(&dev->dev,
c91b7f66
FF		 1030 dma_unmap_addr(tx_cb_ptr, dma_addr),
1031 tx_cb_ptr->skb->len,
1032 DMA_TO_DEVICE);
1c1008c7
FF		 1033 bcmgenet_free_cb(tx_cb_ptr);
1034 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1035 dev->stats.tx_bytes +=
1036 dma_unmap_len(tx_cb_ptr, dma_len);
1037 dma_unmap_page(&dev->dev,
c91b7f66
FF		 1038 dma_unmap_addr(tx_cb_ptr, dma_addr),
1039 dma_unmap_len(tx_cb_ptr, dma_len),
1040 DMA_TO_DEVICE);
1c1008c7
FF		 1041 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1042 }
1c1008c7 1043
66d06757
PG		 1044 txbds_processed++;
1045 if (likely(ring->clean_ptr < ring->end_ptr))
1046 ring->clean_ptr++;
1047 else
1048 ring->clean_ptr = ring->cb_ptr;
1c1008c7
FF		 1049 }
1050
66d06757
PG		 1051 ring->free_bds += txbds_processed;
1052 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1053
4092e6ac 1054 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
66d06757 1055 txq = netdev_get_tx_queue(dev, ring->queue);
4092e6ac
JS		 1056 if (netif_tx_queue_stopped(txq))
1057 netif_tx_wake_queue(txq);
1058 }
1c1008c7 1059
4092e6ac 1060 return pkts_compl;
1c1008c7
FF		 1061}
1062
4092e6ac 1063static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
c91b7f66 1064 struct bcmgenet_tx_ring *ring)
1c1008c7 1065{
4092e6ac 1066 unsigned int released;
1c1008c7
FF		 1067 unsigned long flags;
1068
1069 spin_lock_irqsave(&ring->lock, flags);
4092e6ac 1070 released = __bcmgenet_tx_reclaim(dev, ring);
1c1008c7 1071 spin_unlock_irqrestore(&ring->lock, flags);
4092e6ac
JS		 1072
1073 return released;
1074}
1075
1076static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1077{
1078 struct bcmgenet_tx_ring *ring =
1079 container_of(napi, struct bcmgenet_tx_ring, napi);
1080 unsigned int work_done = 0;
1081
1082 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1083
1084 if (work_done == 0) {
1085 napi_complete(napi);
1086 ring->int_enable(ring->priv, ring);
1087
1088 return 0;
1089 }
1090
1091 return budget;
1c1008c7
FF		 1092}
1093
1094static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1095{
1096 struct bcmgenet_priv *priv = netdev_priv(dev);
1097 int i;
1098
1099 if (netif_is_multiqueue(dev)) {
1100 for (i = 0; i < priv->hw_params->tx_queues; i++)
1101 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1102 }
1103
1104 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1105}
1106
1107/* Transmits a single SKB (either head of a fragment or a single SKB)
1108 * caller must hold priv->lock
1109 */
1110static int bcmgenet_xmit_single(struct net_device *dev,
1111 struct sk_buff *skb,
1112 u16 dma_desc_flags,
1113 struct bcmgenet_tx_ring *ring)
1114{
1115 struct bcmgenet_priv *priv = netdev_priv(dev);
1116 struct device *kdev = &priv->pdev->dev;
1117 struct enet_cb *tx_cb_ptr;
1118 unsigned int skb_len;
1119 dma_addr_t mapping;
1120 u32 length_status;
1121 int ret;
1122
1123 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1124
1125 if (unlikely(!tx_cb_ptr))
1126 BUG();
1127
1128 tx_cb_ptr->skb = skb;
1129
1130 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1131
1132 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1133 ret = dma_mapping_error(kdev, mapping);
1134 if (ret) {
44c8bc3c 1135 priv->mib.tx_dma_failed++;
1c1008c7
FF		 1136 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1137 dev_kfree_skb(skb);
1138 return ret;
1139 }
1140
1141 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1142 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1143 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1144 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1145 DMA_TX_APPEND_CRC;
1146
1147 if (skb->ip_summed == CHECKSUM_PARTIAL)
1148 length_status |= DMA_TX_DO_CSUM;
1149
1150 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1151
1c1008c7
FF		 1152 return 0;
1153}
1154
7fc527f9 1155/* Transmit a SKB fragment */
1c1008c7 1156static int bcmgenet_xmit_frag(struct net_device *dev,
c91b7f66
FF		 1157 skb_frag_t *frag,
1158 u16 dma_desc_flags,
1159 struct bcmgenet_tx_ring *ring)
1c1008c7
FF		 1160{
1161 struct bcmgenet_priv *priv = netdev_priv(dev);
1162 struct device *kdev = &priv->pdev->dev;
1163 struct enet_cb *tx_cb_ptr;
1164 dma_addr_t mapping;
1165 int ret;
1166
1167 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1168
1169 if (unlikely(!tx_cb_ptr))
1170 BUG();
1171 tx_cb_ptr->skb = NULL;
1172
1173 mapping = skb_frag_dma_map(kdev, frag, 0,
c91b7f66 1174 skb_frag_size(frag), DMA_TO_DEVICE);
1c1008c7
FF		 1175 ret = dma_mapping_error(kdev, mapping);
1176 if (ret) {
44c8bc3c 1177 priv->mib.tx_dma_failed++;
1c1008c7 1178 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
c91b7f66 1179 __func__);
1c1008c7
FF		 1180 return ret;
1181 }
1182
1183 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1184 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1185
1186 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
c91b7f66
FF		 1187 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1188 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1c1008c7 1189
1c1008c7
FF		 1190 return 0;
1191}
1192
1193/* Reallocate the SKB to put enough headroom in front of it and insert
1194 * the transmit checksum offsets in the descriptors
1195 */
bc23333b
PG		 1196static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1197 struct sk_buff *skb)
1c1008c7
FF		 1198{
1199 struct status_64 *status = NULL;
1200 struct sk_buff *new_skb;
1201 u16 offset;
1202 u8 ip_proto;
1203 u16 ip_ver;
1204 u32 tx_csum_info;
1205
1206 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1207 /* If 64 byte status block enabled, must make sure skb has
1208 * enough headroom for us to insert 64B status block.
1209 */
1210 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1211 dev_kfree_skb(skb);
1212 if (!new_skb) {
1213 dev->stats.tx_errors++;
1214 dev->stats.tx_dropped++;
bc23333b 1215 return NULL;
1c1008c7
FF		 1216 }
1217 skb = new_skb;
1218 }
1219
1220 skb_push(skb, sizeof(*status));
1221 status = (struct status_64 *)skb->data;
1222
1223 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1224 ip_ver = htons(skb->protocol);
1225 switch (ip_ver) {
1226 case ETH_P_IP:
1227 ip_proto = ip_hdr(skb)->protocol;
1228 break;
1229 case ETH_P_IPV6:
1230 ip_proto = ipv6_hdr(skb)->nexthdr;
1231 break;
1232 default:
bc23333b 1233 return skb;
1c1008c7
FF		 1234 }
1235
1236 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1237 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1238 (offset + skb->csum_offset);
1239
1240 /* Set the length valid bit for TCP and UDP and just set
1241 * the special UDP flag for IPv4, else just set to 0.
1242 */
1243 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1244 tx_csum_info |= STATUS_TX_CSUM_LV;
1245 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1246 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
8900ea57 1247 } else {
1c1008c7 1248 tx_csum_info = 0;
8900ea57 1249 }
1c1008c7
FF		 1250
1251 status->tx_csum_info = tx_csum_info;
1252 }
1253
bc23333b 1254 return skb;
1c1008c7
FF		 1255}
1256
1257static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1258{
1259 struct bcmgenet_priv *priv = netdev_priv(dev);
1260 struct bcmgenet_tx_ring *ring = NULL;
b2cde2cc 1261 struct netdev_queue *txq;
1c1008c7
FF		 1262 unsigned long flags = 0;
1263 int nr_frags, index;
1264 u16 dma_desc_flags;
1265 int ret;
1266 int i;
1267
1268 index = skb_get_queue_mapping(skb);
1269 /* Mapping strategy:
1270 * queue_mapping = 0, unclassified, packet xmited through ring16
1271 * queue_mapping = 1, goes to ring 0. (highest priority queue
1272 * queue_mapping = 2, goes to ring 1.
1273 * queue_mapping = 3, goes to ring 2.
1274 * queue_mapping = 4, goes to ring 3.
1275 */
1276 if (index == 0)
1277 index = DESC_INDEX;
1278 else
1279 index -= 1;
1280
1c1008c7
FF		 1281 nr_frags = skb_shinfo(skb)->nr_frags;
1282 ring = &priv->tx_rings[index];
b2cde2cc 1283 txq = netdev_get_tx_queue(dev, ring->queue);
1c1008c7
FF		 1284
1285 spin_lock_irqsave(&ring->lock, flags);
1286 if (ring->free_bds <= nr_frags + 1) {
b2cde2cc 1287 netif_tx_stop_queue(txq);
1c1008c7 1288 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
c91b7f66 1289 __func__, index, ring->queue);
1c1008c7
FF		 1290 ret = NETDEV_TX_BUSY;
1291 goto out;
1292 }
1293
474ea9ca
FF		 1294 if (skb_padto(skb, ETH_ZLEN)) {
1295 ret = NETDEV_TX_OK;
1296 goto out;
1297 }
1298
1c1008c7
FF		 1299 /* set the SKB transmit checksum */
1300 if (priv->desc_64b_en) {
bc23333b
PG		 1301 skb = bcmgenet_put_tx_csum(dev, skb);
1302 if (!skb) {
1c1008c7
FF		 1303 ret = NETDEV_TX_OK;
1304 goto out;
1305 }
1306 }
1307
1308 dma_desc_flags = DMA_SOP;
1309 if (nr_frags == 0)
1310 dma_desc_flags |= DMA_EOP;
1311
1312 /* Transmit single SKB or head of fragment list */
1313 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1314 if (ret) {
1315 ret = NETDEV_TX_OK;
1316 goto out;
1317 }
1318
1319 /* xmit fragment */
1320 for (i = 0; i < nr_frags; i++) {
1321 ret = bcmgenet_xmit_frag(dev,
c91b7f66
FF		 1322 &skb_shinfo(skb)->frags[i],
1323 (i == nr_frags - 1) ? DMA_EOP : 0,
1324 ring);
1c1008c7
FF		 1325 if (ret) {
1326 ret = NETDEV_TX_OK;
1327 goto out;
1328 }
1329 }
1330
d03825fb
FF		 1331 skb_tx_timestamp(skb);
1332
ae67bf01
FF		 1333 /* Decrement total BD count and advance our write pointer */
1334 ring->free_bds -= nr_frags + 1;
1335 ring->prod_index += nr_frags + 1;
1336 ring->prod_index &= DMA_P_INDEX_MASK;
1337
4092e6ac 1338 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
b2cde2cc 1339 netif_tx_stop_queue(txq);
1c1008c7 1340
ddd0ca5d
FF		 1341 if (!skb->xmit_more || netif_xmit_stopped(txq))
1342 /* Packets are ready, update producer index */
1343 bcmgenet_tdma_ring_writel(priv, ring->index,
1344 ring->prod_index, TDMA_PROD_INDEX);
1c1008c7
FF		 1345out:
1346 spin_unlock_irqrestore(&ring->lock, flags);
1347
1348 return ret;
1349}
1350
d6707bec
PG		 1351static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1352 struct enet_cb *cb)
1c1008c7
FF		 1353{
1354 struct device *kdev = &priv->pdev->dev;
1355 struct sk_buff *skb;
d6707bec 1356 struct sk_buff *rx_skb;
1c1008c7 1357 dma_addr_t mapping;
1c1008c7 1358
d6707bec 1359 /* Allocate a new Rx skb */
c91b7f66 1360 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
d6707bec
PG		 1361 if (!skb) {
1362 priv->mib.alloc_rx_buff_failed++;
1363 netif_err(priv, rx_err, priv->dev,
1364 "%s: Rx skb allocation failed\n", __func__);
1365 return NULL;
1366 }
1c1008c7 1367
d6707bec
PG		 1368 /* DMA-map the new Rx skb */
1369 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1370 DMA_FROM_DEVICE);
1371 if (dma_mapping_error(kdev, mapping)) {
44c8bc3c 1372 priv->mib.rx_dma_failed++;
d6707bec 1373 dev_kfree_skb_any(skb);
1c1008c7 1374 netif_err(priv, rx_err, priv->dev,
d6707bec
PG		 1375 "%s: Rx skb DMA mapping failed\n", __func__);
1376 return NULL;
1c1008c7
FF		 1377 }
1378
d6707bec
PG		 1379 /* Grab the current Rx skb from the ring and DMA-unmap it */
1380 rx_skb = cb->skb;
1381 if (likely(rx_skb))
1382 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1383 priv->rx_buf_len, DMA_FROM_DEVICE);
1384
1385 /* Put the new Rx skb on the ring */
1386 cb->skb = skb;
1c1008c7 1387 dma_unmap_addr_set(cb, dma_addr, mapping);
8ac467e8 1388 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1c1008c7 1389
d6707bec
PG		 1390 /* Return the current Rx skb to caller */
1391 return rx_skb;
1c1008c7
FF		 1392}
1393
1394/* bcmgenet_desc_rx - descriptor based rx process.
1395 * this could be called from bottom half, or from NAPI polling method.
1396 */
1397static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
8ac467e8 1398 unsigned int index,
1c1008c7
FF		 1399 unsigned int budget)
1400{
8ac467e8 1401 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1402 struct net_device *dev = priv->dev;
1403 struct enet_cb *cb;
1404 struct sk_buff *skb;
1405 u32 dma_length_status;
1406 unsigned long dma_flag;
d6707bec 1407 int len;
1c1008c7
FF		 1408 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1409 unsigned int p_index;
d26ea6cc 1410 unsigned int discards;
1c1008c7
FF		 1411 unsigned int chksum_ok = 0;
1412
8ac467e8 1413 p_index = bcmgenet_rdma_ring_readl(priv, index, RDMA_PROD_INDEX);
d26ea6cc
PG		 1414
1415 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1416 DMA_P_INDEX_DISCARD_CNT_MASK;
1417 if (discards > ring->old_discards) {
1418 discards = discards - ring->old_discards;
1419 dev->stats.rx_missed_errors += discards;
1420 dev->stats.rx_errors += discards;
1421 ring->old_discards += discards;
1422
1423 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1424 if (ring->old_discards >= 0xC000) {
1425 ring->old_discards = 0;
1426 bcmgenet_rdma_ring_writel(priv, index, 0,
1427 RDMA_PROD_INDEX);
1428 }
1429 }
1430
1c1008c7
FF		 1431 p_index &= DMA_P_INDEX_MASK;
1432
8ac467e8
PG		 1433 if (likely(p_index >= ring->c_index))
1434 rxpkttoprocess = p_index - ring->c_index;
1c1008c7 1435 else
8ac467e8
PG		 1436 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1437 p_index;
1c1008c7
FF		 1438
1439 netif_dbg(priv, rx_status, dev,
c91b7f66 1440 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1c1008c7
FF		 1441
1442 while ((rxpktprocessed < rxpkttoprocess) &&
c91b7f66 1443 (rxpktprocessed < budget)) {
8ac467e8 1444 cb = &priv->rx_cbs[ring->read_ptr];
d6707bec 1445 skb = bcmgenet_rx_refill(priv, cb);
b629be5c 1446
b629be5c
FF		 1447 if (unlikely(!skb)) {
1448 dev->stats.rx_dropped++;
1449 dev->stats.rx_errors++;
d6707bec 1450 goto next;
b629be5c
FF		 1451 }
1452
1c1008c7 1453 if (!priv->desc_64b_en) {
c91b7f66 1454 dma_length_status =
8ac467e8 1455 dmadesc_get_length_status(priv, cb->bd_addr);
1c1008c7
FF		 1456 } else {
1457 struct status_64 *status;
164d4f20 1458
1c1008c7
FF		 1459 status = (struct status_64 *)skb->data;
1460 dma_length_status = status->length_status;
1461 }
1462
1463 /* DMA flags and length are still valid no matter how
1464 * we got the Receive Status Vector (64B RSB or register)
1465 */
1466 dma_flag = dma_length_status & 0xffff;
1467 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1468
1469 netif_dbg(priv, rx_status, dev,
c91b7f66 1470 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
8ac467e8
PG		 1471 __func__, p_index, ring->c_index,
1472 ring->read_ptr, dma_length_status);
1c1008c7 1473
1c1008c7
FF		 1474 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1475 netif_err(priv, rx_status, dev,
c91b7f66 1476 "dropping fragmented packet!\n");
1c1008c7
FF		 1477 dev->stats.rx_dropped++;
1478 dev->stats.rx_errors++;
d6707bec
PG		 1479 dev_kfree_skb_any(skb);
1480 goto next;
1c1008c7 1481 }
d6707bec 1482
1c1008c7
FF		 1483 /* report errors */
1484 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1485 DMA_RX_OV |
1486 DMA_RX_NO |
1487 DMA_RX_LG |
1488 DMA_RX_RXER))) {
1489 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
c91b7f66 1490 (unsigned int)dma_flag);
1c1008c7
FF		 1491 if (dma_flag & DMA_RX_CRC_ERROR)
1492 dev->stats.rx_crc_errors++;
1493 if (dma_flag & DMA_RX_OV)
1494 dev->stats.rx_over_errors++;
1495 if (dma_flag & DMA_RX_NO)
1496 dev->stats.rx_frame_errors++;
1497 if (dma_flag & DMA_RX_LG)
1498 dev->stats.rx_length_errors++;
1499 dev->stats.rx_dropped++;
1500 dev->stats.rx_errors++;
d6707bec
PG		 1501 dev_kfree_skb_any(skb);
1502 goto next;
1c1008c7
FF		 1503 } /* error packet */
1504
1505 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
c91b7f66 1506 priv->desc_rxchk_en;
1c1008c7
FF		 1507
1508 skb_put(skb, len);
1509 if (priv->desc_64b_en) {
1510 skb_pull(skb, 64);
1511 len -= 64;
1512 }
1513
1514 if (likely(chksum_ok))
1515 skb->ip_summed = CHECKSUM_UNNECESSARY;
1516
1517 /* remove hardware 2bytes added for IP alignment */
1518 skb_pull(skb, 2);
1519 len -= 2;
1520
1521 if (priv->crc_fwd_en) {
1522 skb_trim(skb, len - ETH_FCS_LEN);
1523 len -= ETH_FCS_LEN;
1524 }
1525
1526 /*Finish setting up the received SKB and send it to the kernel*/
1527 skb->protocol = eth_type_trans(skb, priv->dev);
1528 dev->stats.rx_packets++;
1529 dev->stats.rx_bytes += len;
1530 if (dma_flag & DMA_RX_MULT)
1531 dev->stats.multicast++;
1532
1533 /* Notify kernel */
1534 napi_gro_receive(&priv->napi, skb);
1c1008c7
FF		 1535 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1536
d6707bec 1537next:
cf377d88 1538 rxpktprocessed++;
8ac467e8
PG		 1539 if (likely(ring->read_ptr < ring->end_ptr))
1540 ring->read_ptr++;
1541 else
1542 ring->read_ptr = ring->cb_ptr;
1543
1544 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1545 bcmgenet_rdma_ring_writel(priv, index, ring->c_index, RDMA_CONS_INDEX);
1c1008c7
FF		 1546 }
1547
1548 return rxpktprocessed;
1549}
1550
1551/* Assign skb to RX DMA descriptor. */
8ac467e8
PG		 1552static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1553 struct bcmgenet_rx_ring *ring)
1c1008c7
FF		 1554{
1555 struct enet_cb *cb;
d6707bec 1556 struct sk_buff *skb;
1c1008c7
FF		 1557 int i;
1558
8ac467e8 1559 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7
FF		 1560
1561 /* loop here for each buffer needing assign */
8ac467e8
PG		 1562 for (i = 0; i < ring->size; i++) {
1563 cb = ring->cbs + i;
d6707bec
PG		 1564 skb = bcmgenet_rx_refill(priv, cb);
1565 if (skb)
1566 dev_kfree_skb_any(skb);
1567 if (!cb->skb)
1568 return -ENOMEM;
1c1008c7
FF		 1569 }
1570
d6707bec 1571 return 0;
1c1008c7
FF		 1572}
1573
1574static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1575{
1576 struct enet_cb *cb;
1577 int i;
1578
1579 for (i = 0; i < priv->num_rx_bds; i++) {
1580 cb = &priv->rx_cbs[i];
1581
1582 if (dma_unmap_addr(cb, dma_addr)) {
1583 dma_unmap_single(&priv->dev->dev,
c91b7f66
FF		 1584 dma_unmap_addr(cb, dma_addr),
1585 priv->rx_buf_len, DMA_FROM_DEVICE);
1c1008c7
FF		 1586 dma_unmap_addr_set(cb, dma_addr, 0);
1587 }
1588
1589 if (cb->skb)
1590 bcmgenet_free_cb(cb);
1591 }
1592}
1593
c91b7f66 1594static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
e29585b8
FF		 1595{
1596 u32 reg;
1597
1598 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1599 if (enable)
1600 reg |= mask;
1601 else
1602 reg &= ~mask;
1603 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1604
1605 /* UniMAC stops on a packet boundary, wait for a full-size packet
1606 * to be processed
1607 */
1608 if (enable == 0)
1609 usleep_range(1000, 2000);
1610}
1611
1c1008c7
FF		 1612static int reset_umac(struct bcmgenet_priv *priv)
1613{
1614 struct device *kdev = &priv->pdev->dev;
1615 unsigned int timeout = 0;
1616 u32 reg;
1617
1618 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1619 bcmgenet_rbuf_ctrl_set(priv, 0);
1620 udelay(10);
1621
1622 /* disable MAC while updating its registers */
1623 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1624
1625 /* issue soft reset, wait for it to complete */
1626 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1627 while (timeout++ < 1000) {
1628 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1629 if (!(reg & CMD_SW_RESET))
1630 return 0;
1631
1632 udelay(1);
1633 }
1634
1635 if (timeout == 1000) {
1636 dev_err(kdev,
7fc527f9 1637 "timeout waiting for MAC to come out of reset\n");
1c1008c7
FF		 1638 return -ETIMEDOUT;
1639 }
1640
1641 return 0;
1642}
1643
909ff5ef
FF		 1644static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1645{
1646 /* Mask all interrupts.*/
1647 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1648 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1649 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1650 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1651 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1652 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1653}
1654
1c1008c7
FF		 1655static int init_umac(struct bcmgenet_priv *priv)
1656{
1657 struct device *kdev = &priv->pdev->dev;
1658 int ret;
1659 u32 reg, cpu_mask_clear;
4092e6ac 1660 int index;
1c1008c7
FF		 1661
1662 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1663
1664 ret = reset_umac(priv);
1665 if (ret)
1666 return ret;
1667
1668 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1669 /* clear tx/rx counter */
1670 bcmgenet_umac_writel(priv,
c91b7f66
FF		 1671 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1672 UMAC_MIB_CTRL);
1c1008c7
FF		 1673 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1674
1675 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1676
1677 /* init rx registers, enable ip header optimization */
1678 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1679 reg |= RBUF_ALIGN_2B;
1680 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1681
1682 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1683 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1684
909ff5ef 1685 bcmgenet_intr_disable(priv);
1c1008c7 1686
4092e6ac 1687 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_TXDMA_BDONE;
1c1008c7
FF		 1688
1689 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1690
7fc527f9 1691 /* Monitor cable plug/unplugged event for internal PHY */
8900ea57 1692 if (phy_is_internal(priv->phydev)) {
1c1008c7 1693 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1694 } else if (priv->ext_phy) {
1c1008c7 1695 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
8900ea57 1696 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1c1008c7
FF		 1697 reg = bcmgenet_bp_mc_get(priv);
1698 reg |= BIT(priv->hw_params->bp_in_en_shift);
1699
1700 /* bp_mask: back pressure mask */
1701 if (netif_is_multiqueue(priv->dev))
1702 reg |= priv->hw_params->bp_in_mask;
1703 else
1704 reg &= ~priv->hw_params->bp_in_mask;
1705 bcmgenet_bp_mc_set(priv, reg);
1706 }
1707
1708 /* Enable MDIO interrupts on GENET v3+ */
1709 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1710 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1711
c91b7f66 1712 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1c1008c7 1713
4092e6ac
JS		 1714 for (index = 0; index < priv->hw_params->tx_queues; index++)
1715 bcmgenet_intrl2_1_writel(priv, (1 << index),
1716 INTRL2_CPU_MASK_CLEAR);
1717
1c1008c7
FF		 1718 /* Enable rx/tx engine.*/
1719 dev_dbg(kdev, "done init umac\n");
1720
1721 return 0;
1722}
1723
4f8b2d7d 1724/* Initialize a Tx ring along with corresponding hardware registers */
1c1008c7
FF		 1725static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1726 unsigned int index, unsigned int size,
4f8b2d7d 1727 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7
FF		 1728{
1729 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1730 u32 words_per_bd = WORDS_PER_BD(priv);
1731 u32 flow_period_val = 0;
1c1008c7
FF		 1732
1733 spin_lock_init(&ring->lock);
4092e6ac
JS		 1734 ring->priv = priv;
1735 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1c1008c7
FF		 1736 ring->index = index;
1737 if (index == DESC_INDEX) {
1738 ring->queue = 0;
1739 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1740 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1741 } else {
1742 ring->queue = index + 1;
1743 ring->int_enable = bcmgenet_tx_ring_int_enable;
1744 ring->int_disable = bcmgenet_tx_ring_int_disable;
1745 }
4f8b2d7d 1746 ring->cbs = priv->tx_cbs + start_ptr;
1c1008c7 1747 ring->size = size;
66d06757 1748 ring->clean_ptr = start_ptr;
1c1008c7
FF		 1749 ring->c_index = 0;
1750 ring->free_bds = size;
4f8b2d7d
PG		 1751 ring->write_ptr = start_ptr;
1752 ring->cb_ptr = start_ptr;
1c1008c7
FF		 1753 ring->end_ptr = end_ptr - 1;
1754 ring->prod_index = 0;
1755
1756 /* Set flow period for ring != 16 */
1757 if (index != DESC_INDEX)
1758 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1759
1760 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1761 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1762 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1763 /* Disable rate control for now */
1764 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
c91b7f66 1765 TDMA_FLOW_PERIOD);
1c1008c7 1766 bcmgenet_tdma_ring_writel(priv, index,
c91b7f66
FF		 1767 ((size << DMA_RING_SIZE_SHIFT) |
1768 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1769
1c1008c7 1770 /* Set start and end address, read and write pointers */
4f8b2d7d 1771 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1772 DMA_START_ADDR);
4f8b2d7d 1773 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1774 TDMA_READ_PTR);
4f8b2d7d 1775 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
c91b7f66 1776 TDMA_WRITE_PTR);
1c1008c7 1777 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
c91b7f66 1778 DMA_END_ADDR);
4092e6ac
JS		 1779
1780 napi_enable(&ring->napi);
1781}
1782
1783static void bcmgenet_fini_tx_ring(struct bcmgenet_priv *priv,
1784 unsigned int index)
1785{
1786 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1787
1788 napi_disable(&ring->napi);
1789 netif_napi_del(&ring->napi);
1c1008c7
FF		 1790}
1791
1792/* Initialize a RDMA ring */
1793static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
8ac467e8
PG		 1794 unsigned int index, unsigned int size,
1795 unsigned int start_ptr, unsigned int end_ptr)
1c1008c7 1796{
8ac467e8 1797 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1c1008c7
FF		 1798 u32 words_per_bd = WORDS_PER_BD(priv);
1799 int ret;
1800
8ac467e8
PG		 1801 ring->index = index;
1802 ring->cbs = priv->rx_cbs + start_ptr;
1803 ring->size = size;
1804 ring->c_index = 0;
1805 ring->read_ptr = start_ptr;
1806 ring->cb_ptr = start_ptr;
1807 ring->end_ptr = end_ptr - 1;
1c1008c7 1808
8ac467e8
PG		 1809 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1810 if (ret)
1c1008c7 1811 return ret;
1c1008c7 1812
1c1008c7
FF		 1813 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1814 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
6f5a272c 1815 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1c1008c7 1816 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1817 ((size << DMA_RING_SIZE_SHIFT) |
1818 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1c1008c7 1819 bcmgenet_rdma_ring_writel(priv, index,
c91b7f66
FF		 1820 (DMA_FC_THRESH_LO <<
1821 DMA_XOFF_THRESHOLD_SHIFT) |
1822 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
6f5a272c
PG		 1823
1824 /* Set start and end address, read and write pointers */
8ac467e8
PG		 1825 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1826 DMA_START_ADDR);
1827 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1828 RDMA_READ_PTR);
1829 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1830 RDMA_WRITE_PTR);
1831 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
6f5a272c 1832 DMA_END_ADDR);
1c1008c7
FF		 1833
1834 return ret;
1835}
1836
16c6d667 1837/* Initialize Tx queues
1c1008c7 1838 *
16c6d667 1839 * Queues 0-3 are priority-based, each one has 32 descriptors,
1c1008c7
FF		 1840 * with queue 0 being the highest priority queue.
1841 *
16c6d667 1842 * Queue 16 is the default Tx queue with
51a966a7 1843 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1c1008c7 1844 *
16c6d667
PG		 1845 * The transmit control block pool is then partitioned as follows:
1846 * - Tx queue 0 uses tx_cbs[0..31]
1847 * - Tx queue 1 uses tx_cbs[32..63]
1848 * - Tx queue 2 uses tx_cbs[64..95]
1849 * - Tx queue 3 uses tx_cbs[96..127]
1850 * - Tx queue 16 uses tx_cbs[128..255]
1c1008c7 1851 */
16c6d667 1852static void bcmgenet_init_tx_queues(struct net_device *dev)
1c1008c7
FF		 1853{
1854 struct bcmgenet_priv *priv = netdev_priv(dev);
16c6d667
PG		 1855 u32 i, dma_enable;
1856 u32 dma_ctrl, ring_cfg;
37742166 1857 u32 dma_priority[3] = {0, 0, 0};
1c1008c7 1858
1c1008c7
FF		 1859 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1860 dma_enable = dma_ctrl & DMA_EN;
1861 dma_ctrl &= ~DMA_EN;
1862 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1863
16c6d667
PG		 1864 dma_ctrl = 0;
1865 ring_cfg = 0;
1866
1c1008c7
FF		 1867 /* Enable strict priority arbiter mode */
1868 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1869
16c6d667 1870 /* Initialize Tx priority queues */
1c1008c7 1871 for (i = 0; i < priv->hw_params->tx_queues; i++) {
51a966a7
PG		 1872 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1873 i * priv->hw_params->tx_bds_per_q,
1874 (i + 1) * priv->hw_params->tx_bds_per_q);
16c6d667
PG		 1875 ring_cfg |= (1 << i);
1876 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1877 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1878 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1c1008c7
FF		 1879 }
1880
16c6d667 1881 /* Initialize Tx default queue 16 */
51a966a7 1882 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
16c6d667 1883 priv->hw_params->tx_queues *
51a966a7 1884 priv->hw_params->tx_bds_per_q,
16c6d667
PG		 1885 TOTAL_DESC);
1886 ring_cfg |= (1 << DESC_INDEX);
1887 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
37742166
PG		 1888 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1889 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1890 DMA_PRIO_REG_SHIFT(DESC_INDEX));
16c6d667
PG		 1891
1892 /* Set Tx queue priorities */
37742166
PG		 1893 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1894 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1895 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1896
16c6d667
PG		 1897 /* Enable Tx queues */
1898 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
1c1008c7 1899
16c6d667 1900 /* Enable Tx DMA */
1c1008c7 1901 if (dma_enable)
16c6d667
PG		 1902 dma_ctrl |= DMA_EN;
1903 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1c1008c7
FF		 1904}
1905
8ac467e8
PG		 1906/* Initialize Rx queues
1907 *
1908 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
1909 * used to direct traffic to these queues.
1910 *
1911 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
1912 */
1913static int bcmgenet_init_rx_queues(struct net_device *dev)
1914{
1915 struct bcmgenet_priv *priv = netdev_priv(dev);
1916 u32 i;
1917 u32 dma_enable;
1918 u32 dma_ctrl;
1919 u32 ring_cfg;
1920 int ret;
1921
1922 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
1923 dma_enable = dma_ctrl & DMA_EN;
1924 dma_ctrl &= ~DMA_EN;
1925 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
1926
1927 dma_ctrl = 0;
1928 ring_cfg = 0;
1929
1930 /* Initialize Rx priority queues */
1931 for (i = 0; i < priv->hw_params->rx_queues; i++) {
1932 ret = bcmgenet_init_rx_ring(priv, i,
1933 priv->hw_params->rx_bds_per_q,
1934 i * priv->hw_params->rx_bds_per_q,
1935 (i + 1) *
1936 priv->hw_params->rx_bds_per_q);
1937 if (ret)
1938 return ret;
1939
1940 ring_cfg |= (1 << i);
1941 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1942 }
1943
1944 /* Initialize Rx default queue 16 */
1945 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
1946 priv->hw_params->rx_queues *
1947 priv->hw_params->rx_bds_per_q,
1948 TOTAL_DESC);
1949 if (ret)
1950 return ret;
1951
1952 ring_cfg |= (1 << DESC_INDEX);
1953 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
1954
1955 /* Enable rings */
1956 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
1957
1958 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1959 if (dma_enable)
1960 dma_ctrl |= DMA_EN;
1961 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
1962
1963 return 0;
1964}
1965
4a0c081e
FF		 1966static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1967{
1968 int ret = 0;
1969 int timeout = 0;
1970 u32 reg;
1971
1972 /* Disable TDMA to stop add more frames in TX DMA */
1973 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1974 reg &= ~DMA_EN;
1975 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1976
1977 /* Check TDMA status register to confirm TDMA is disabled */
1978 while (timeout++ < DMA_TIMEOUT_VAL) {
1979 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1980 if (reg & DMA_DISABLED)
1981 break;
1982
1983 udelay(1);
1984 }
1985
1986 if (timeout == DMA_TIMEOUT_VAL) {
1987 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1988 ret = -ETIMEDOUT;
1989 }
1990
1991 /* Wait 10ms for packet drain in both tx and rx dma */
1992 usleep_range(10000, 20000);
1993
1994 /* Disable RDMA */
1995 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1996 reg &= ~DMA_EN;
1997 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1998
1999 timeout = 0;
2000 /* Check RDMA status register to confirm RDMA is disabled */
2001 while (timeout++ < DMA_TIMEOUT_VAL) {
2002 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2003 if (reg & DMA_DISABLED)
2004 break;
2005
2006 udelay(1);
2007 }
2008
2009 if (timeout == DMA_TIMEOUT_VAL) {
2010 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2011 ret = -ETIMEDOUT;
2012 }
2013
2014 return ret;
2015}
2016
4092e6ac 2017static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1c1008c7
FF		 2018{
2019 int i;
2020
2021 /* disable DMA */
4a0c081e 2022 bcmgenet_dma_teardown(priv);
1c1008c7
FF		 2023
2024 for (i = 0; i < priv->num_tx_bds; i++) {
2025 if (priv->tx_cbs[i].skb != NULL) {
2026 dev_kfree_skb(priv->tx_cbs[i].skb);
2027 priv->tx_cbs[i].skb = NULL;
2028 }
2029 }
2030
2031 bcmgenet_free_rx_buffers(priv);
2032 kfree(priv->rx_cbs);
2033 kfree(priv->tx_cbs);
2034}
2035
4092e6ac
JS		 2036static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2037{
2038 int i;
2039
2040 bcmgenet_fini_tx_ring(priv, DESC_INDEX);
2041
2042 for (i = 0; i < priv->hw_params->tx_queues; i++)
2043 bcmgenet_fini_tx_ring(priv, i);
2044
2045 __bcmgenet_fini_dma(priv);
2046}
2047
1c1008c7
FF		 2048/* init_edma: Initialize DMA control register */
2049static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2050{
2051 int ret;
014012a4
PG		 2052 unsigned int i;
2053 struct enet_cb *cb;
1c1008c7 2054
6f5a272c 2055 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1c1008c7 2056
6f5a272c
PG		 2057 /* Init rDma */
2058 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2059
2060 /* Initialize common Rx ring structures */
2061 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2062 priv->num_rx_bds = TOTAL_DESC;
2063 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2064 GFP_KERNEL);
2065 if (!priv->rx_cbs)
2066 return -ENOMEM;
2067
2068 for (i = 0; i < priv->num_rx_bds; i++) {
2069 cb = priv->rx_cbs + i;
2070 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2071 }
2072
8ac467e8
PG		 2073 /* Initialize Rx queues */
2074 ret = bcmgenet_init_rx_queues(priv->dev);
1c1008c7 2075 if (ret) {
8ac467e8 2076 netdev_err(priv->dev, "failed to initialize Rx queues\n");
6f5a272c
PG		 2077 bcmgenet_free_rx_buffers(priv);
2078 kfree(priv->rx_cbs);
1c1008c7
FF		 2079 return ret;
2080 }
2081
1c1008c7
FF		 2082 /* Init tDma */
2083 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2084
7fc527f9 2085 /* Initialize common TX ring structures */
1c1008c7
FF		 2086 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2087 priv->num_tx_bds = TOTAL_DESC;
c489be08 2088 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
c91b7f66 2089 GFP_KERNEL);
1c1008c7 2090 if (!priv->tx_cbs) {
4092e6ac 2091 __bcmgenet_fini_dma(priv);
1c1008c7
FF		 2092 return -ENOMEM;
2093 }
2094
014012a4
PG		 2095 for (i = 0; i < priv->num_tx_bds; i++) {
2096 cb = priv->tx_cbs + i;
2097 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2098 }
2099
16c6d667
PG		 2100 /* Initialize Tx queues */
2101 bcmgenet_init_tx_queues(priv->dev);
1c1008c7
FF		 2102
2103 return 0;
2104}
2105
2106/* NAPI polling method*/
2107static int bcmgenet_poll(struct napi_struct *napi, int budget)
2108{
2109 struct bcmgenet_priv *priv = container_of(napi,
2110 struct bcmgenet_priv, napi);
2111 unsigned int work_done;
2112
8ac467e8 2113 work_done = bcmgenet_desc_rx(priv, DESC_INDEX, budget);
1c1008c7 2114
1c1008c7
FF		 2115 if (work_done < budget) {
2116 napi_complete(napi);
c91b7f66
FF		 2117 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2118 INTRL2_CPU_MASK_CLEAR);
1c1008c7
FF		 2119 }
2120
2121 return work_done;
2122}
2123
2124/* Interrupt bottom half */
2125static void bcmgenet_irq_task(struct work_struct *work)
2126{
2127 struct bcmgenet_priv *priv = container_of(
2128 work, struct bcmgenet_priv, bcmgenet_irq_work);
2129
2130 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2131
8fdb0e0f
FF		 2132 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2133 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2134 netif_dbg(priv, wol, priv->dev,
2135 "magic packet detected, waking up\n");
2136 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2137 }
2138
1c1008c7
FF		 2139 /* Link UP/DOWN event */
2140 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2141 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
80d8e96d 2142 phy_mac_interrupt(priv->phydev,
c91b7f66 2143 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1c1008c7
FF		 2144 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2145 }
2146}
2147
2148/* bcmgenet_isr1: interrupt handler for ring buffer. */
2149static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2150{
2151 struct bcmgenet_priv *priv = dev_id;
4092e6ac 2152 struct bcmgenet_tx_ring *ring;
1c1008c7
FF		 2153 unsigned int index;
2154
2155 /* Save irq status for bottom-half processing. */
2156 priv->irq1_stat =
2157 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
4092e6ac 2158 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2159 /* clear interrupts */
1c1008c7
FF		 2160 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2161
2162 netif_dbg(priv, intr, priv->dev,
c91b7f66 2163 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
4092e6ac 2164
1c1008c7
FF		 2165 /* Check the MBDONE interrupts.
2166 * packet is done, reclaim descriptors
2167 */
4092e6ac
JS		 2168 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2169 if (!(priv->irq1_stat & BIT(index)))
2170 continue;
2171
2172 ring = &priv->tx_rings[index];
2173
2174 if (likely(napi_schedule_prep(&ring->napi))) {
2175 ring->int_disable(priv, ring);
2176 __napi_schedule(&ring->napi);
1c1008c7
FF		 2177 }
2178 }
4092e6ac 2179
1c1008c7
FF		 2180 return IRQ_HANDLED;
2181}
2182
2183/* bcmgenet_isr0: Handle various interrupts. */
2184static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2185{
2186 struct bcmgenet_priv *priv = dev_id;
2187
2188 /* Save irq status for bottom-half processing. */
2189 priv->irq0_stat =
2190 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2191 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
7fc527f9 2192 /* clear interrupts */
1c1008c7
FF		 2193 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2194
2195 netif_dbg(priv, intr, priv->dev,
c91b7f66 2196 "IRQ=0x%x\n", priv->irq0_stat);
1c1008c7
FF		 2197
2198 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2199 /* We use NAPI(software interrupt throttling, if
2200 * Rx Descriptor throttling is not used.
2201 * Disable interrupt, will be enabled in the poll method.
2202 */
2203 if (likely(napi_schedule_prep(&priv->napi))) {
c91b7f66
FF		 2204 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2205 INTRL2_CPU_MASK_SET);
1c1008c7
FF		 2206 __napi_schedule(&priv->napi);
2207 }
2208 }
2209 if (priv->irq0_stat &
2210 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
4092e6ac
JS		 2211 struct bcmgenet_tx_ring *ring = &priv->tx_rings[DESC_INDEX];
2212
2213 if (likely(napi_schedule_prep(&ring->napi))) {
2214 ring->int_disable(priv, ring);
2215 __napi_schedule(&ring->napi);
2216 }
1c1008c7
FF		 2217 }
2218 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2219 UMAC_IRQ_PHY_DET_F |
2220 UMAC_IRQ_LINK_UP |
2221 UMAC_IRQ_LINK_DOWN |
2222 UMAC_IRQ_HFB_SM |
2223 UMAC_IRQ_HFB_MM |
2224 UMAC_IRQ_MPD_R)) {
2225 /* all other interested interrupts handled in bottom half */
2226 schedule_work(&priv->bcmgenet_irq_work);
2227 }
2228
2229 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
c91b7f66 2230 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1c1008c7
FF		 2231 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2232 wake_up(&priv->wq);
2233 }
2234
2235 return IRQ_HANDLED;
2236}
2237
8562056f
FF		 2238static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2239{
2240 struct bcmgenet_priv *priv = dev_id;
2241
2242 pm_wakeup_event(&priv->pdev->dev, 0);
2243
2244 return IRQ_HANDLED;
2245}
2246
1c1008c7
FF		 2247static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2248{
2249 u32 reg;
2250
2251 reg = bcmgenet_rbuf_ctrl_get(priv);
2252 reg |= BIT(1);
2253 bcmgenet_rbuf_ctrl_set(priv, reg);
2254 udelay(10);
2255
2256 reg &= ~BIT(1);
2257 bcmgenet_rbuf_ctrl_set(priv, reg);
2258 udelay(10);
2259}
2260
2261static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
c91b7f66 2262 unsigned char *addr)
1c1008c7
FF		 2263{
2264 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2265 (addr[2] << 8) | addr[3], UMAC_MAC0);
2266 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2267}
2268
1c1008c7
FF		 2269/* Returns a reusable dma control register value */
2270static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2271{
2272 u32 reg;
2273 u32 dma_ctrl;
2274
2275 /* disable DMA */
2276 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2277 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2278 reg &= ~dma_ctrl;
2279 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2280
2281 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2282 reg &= ~dma_ctrl;
2283 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2284
2285 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2286 udelay(10);
2287 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2288
2289 return dma_ctrl;
2290}
2291
2292static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2293{
2294 u32 reg;
2295
2296 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2297 reg |= dma_ctrl;
2298 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2299
2300 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2301 reg |= dma_ctrl;
2302 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2303}
2304
0034de41
PG		 2305static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2306 u32 f_index)
2307{
2308 u32 offset;
2309 u32 reg;
2310
2311 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2312 reg = bcmgenet_hfb_reg_readl(priv, offset);
2313 return !!(reg & (1 << (f_index % 32)));
2314}
2315
2316static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2317{
2318 u32 offset;
2319 u32 reg;
2320
2321 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2322 reg = bcmgenet_hfb_reg_readl(priv, offset);
2323 reg |= (1 << (f_index % 32));
2324 bcmgenet_hfb_reg_writel(priv, reg, offset);
2325}
2326
2327static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2328 u32 f_index, u32 rx_queue)
2329{
2330 u32 offset;
2331 u32 reg;
2332
2333 offset = f_index / 8;
2334 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2335 reg &= ~(0xF << (4 * (f_index % 8)));
2336 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2337 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2338}
2339
2340static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2341 u32 f_index, u32 f_length)
2342{
2343 u32 offset;
2344 u32 reg;
2345
2346 offset = HFB_FLT_LEN_V3PLUS +
2347 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2348 sizeof(u32);
2349 reg = bcmgenet_hfb_reg_readl(priv, offset);
2350 reg &= ~(0xFF << (8 * (f_index % 4)));
2351 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2352 bcmgenet_hfb_reg_writel(priv, reg, offset);
2353}
2354
2355static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2356{
2357 u32 f_index;
2358
2359 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2360 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2361 return f_index;
2362
2363 return -ENOMEM;
2364}
2365
2366/* bcmgenet_hfb_add_filter
2367 *
2368 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2369 * desired Rx queue.
2370 *
2371 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2372 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2373 *
2374 * bits 31:20 - unused
2375 * bit 19 - nibble 0 match enable
2376 * bit 18 - nibble 1 match enable
2377 * bit 17 - nibble 2 match enable
2378 * bit 16 - nibble 3 match enable
2379 * bits 15:12 - nibble 0 data
2380 * bits 11:8 - nibble 1 data
2381 * bits 7:4 - nibble 2 data
2382 * bits 3:0 - nibble 3 data
2383 *
2384 * Example:
2385 * In order to match:
2386 * - Ethernet frame type = 0x0800 (IP)
2387 * - IP version field = 4
2388 * - IP protocol field = 0x11 (UDP)
2389 *
2390 * The following filter is needed:
2391 * u32 hfb_filter_ipv4_udp[] = {
2392 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2393 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2394 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2395 * };
2396 *
2397 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2398 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2399 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2400 */
2401int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2402 u32 f_length, u32 rx_queue)
2403{
2404 int f_index;
2405 u32 i;
2406
2407 f_index = bcmgenet_hfb_find_unused_filter(priv);
2408 if (f_index < 0)
2409 return -ENOMEM;
2410
2411 if (f_length > priv->hw_params->hfb_filter_size)
2412 return -EINVAL;
2413
2414 for (i = 0; i < f_length; i++)
2415 bcmgenet_hfb_writel(priv, f_data[i],
2416 (f_index * priv->hw_params->hfb_filter_size + i) *
2417 sizeof(u32));
2418
2419 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2420 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2421 bcmgenet_hfb_enable_filter(priv, f_index);
2422 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2423
2424 return 0;
2425}
2426
2427/* bcmgenet_hfb_clear
2428 *
2429 * Clear Hardware Filter Block and disable all filtering.
2430 */
2431static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2432{
2433 u32 i;
2434
2435 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2436 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2437 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2438
2439 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2440 bcmgenet_rdma_writel(priv, 0x0, i);
2441
2442 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2443 bcmgenet_hfb_reg_writel(priv, 0x0,
2444 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2445
2446 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2447 priv->hw_params->hfb_filter_size; i++)
2448 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2449}
2450
2451static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2452{
2453 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2454 return;
2455
2456 bcmgenet_hfb_clear(priv);
2457}
2458
909ff5ef
FF		 2459static void bcmgenet_netif_start(struct net_device *dev)
2460{
2461 struct bcmgenet_priv *priv = netdev_priv(dev);
2462
2463 /* Start the network engine */
2464 napi_enable(&priv->napi);
2465
2466 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2467
2468 if (phy_is_internal(priv->phydev))
2469 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2470
2471 netif_tx_start_all_queues(dev);
2472
2473 phy_start(priv->phydev);
2474}
2475
1c1008c7
FF		 2476static int bcmgenet_open(struct net_device *dev)
2477{
2478 struct bcmgenet_priv *priv = netdev_priv(dev);
2479 unsigned long dma_ctrl;
2480 u32 reg;
2481 int ret;
2482
2483 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2484
2485 /* Turn on the clock */
2486 if (!IS_ERR(priv->clk))
2487 clk_prepare_enable(priv->clk);
2488
2489 /* take MAC out of reset */
2490 bcmgenet_umac_reset(priv);
2491
2492 ret = init_umac(priv);
2493 if (ret)
2494 goto err_clk_disable;
2495
2496 /* disable ethernet MAC while updating its registers */
e29585b8 2497 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
1c1008c7 2498
909ff5ef
FF		 2499 /* Make sure we reflect the value of CRC_CMD_FWD */
2500 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2501 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2502
1c1008c7
FF		 2503 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2504
1c1008c7
FF		 2505 if (phy_is_internal(priv->phydev)) {
2506 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2507 reg |= EXT_ENERGY_DET_MASK;
2508 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2509 }
2510
2511 /* Disable RX/TX DMA and flush TX queues */
2512 dma_ctrl = bcmgenet_dma_disable(priv);
2513
2514 /* Reinitialize TDMA and RDMA and SW housekeeping */
2515 ret = bcmgenet_init_dma(priv);
2516 if (ret) {
2517 netdev_err(dev, "failed to initialize DMA\n");
2518 goto err_fini_dma;
2519 }
2520
2521 /* Always enable ring 16 - descriptor ring */
2522 bcmgenet_enable_dma(priv, dma_ctrl);
2523
0034de41
PG		 2524 /* HFB init */
2525 bcmgenet_hfb_init(priv);
2526
1c1008c7 2527 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
c91b7f66 2528 dev->name, priv);
1c1008c7
FF		 2529 if (ret < 0) {
2530 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2531 goto err_fini_dma;
2532 }
2533
2534 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
c91b7f66 2535 dev->name, priv);
1c1008c7
FF		 2536 if (ret < 0) {
2537 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2538 goto err_irq0;
2539 }
2540
dbd479db
FF		 2541 /* Re-configure the port multiplexer towards the PHY device */
2542 bcmgenet_mii_config(priv->dev, false);
2543
c96e731c
FF		 2544 phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2545 priv->phy_interface);
2546
909ff5ef 2547 bcmgenet_netif_start(dev);
1c1008c7
FF		 2548
2549 return 0;
2550
2551err_irq0:
2552 free_irq(priv->irq0, dev);
2553err_fini_dma:
2554 bcmgenet_fini_dma(priv);
2555err_clk_disable:
2556 if (!IS_ERR(priv->clk))
2557 clk_disable_unprepare(priv->clk);
2558 return ret;
2559}
2560
909ff5ef
FF		 2561static void bcmgenet_netif_stop(struct net_device *dev)
2562{
2563 struct bcmgenet_priv *priv = netdev_priv(dev);
2564
2565 netif_tx_stop_all_queues(dev);
2566 napi_disable(&priv->napi);
2567 phy_stop(priv->phydev);
2568
2569 bcmgenet_intr_disable(priv);
2570
2571 /* Wait for pending work items to complete. Since interrupts are
2572 * disabled no new work will be scheduled.
2573 */
2574 cancel_work_sync(&priv->bcmgenet_irq_work);
cc013fb4 2575
cc013fb4 2576 priv->old_link = -1;
5ad6e6c5 2577 priv->old_speed = -1;
cc013fb4 2578 priv->old_duplex = -1;
5ad6e6c5 2579 priv->old_pause = -1;
909ff5ef
FF		 2580}
2581
1c1008c7
FF		 2582static int bcmgenet_close(struct net_device *dev)
2583{
2584 struct bcmgenet_priv *priv = netdev_priv(dev);
2585 int ret;
1c1008c7
FF		 2586
2587 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2588
909ff5ef 2589 bcmgenet_netif_stop(dev);
1c1008c7 2590
c96e731c
FF		 2591 /* Really kill the PHY state machine and disconnect from it */
2592 phy_disconnect(priv->phydev);
2593
1c1008c7 2594 /* Disable MAC receive */
e29585b8 2595 umac_enable_set(priv, CMD_RX_EN, false);
1c1008c7 2596
1c1008c7
FF		 2597 ret = bcmgenet_dma_teardown(priv);
2598 if (ret)
2599 return ret;
2600
2601 /* Disable MAC transmit. TX DMA disabled have to done before this */
e29585b8 2602 umac_enable_set(priv, CMD_TX_EN, false);
1c1008c7 2603
1c1008c7
FF		 2604 /* tx reclaim */
2605 bcmgenet_tx_reclaim_all(dev);
2606 bcmgenet_fini_dma(priv);
2607
2608 free_irq(priv->irq0, priv);
2609 free_irq(priv->irq1, priv);
2610
1c1008c7 2611 if (phy_is_internal(priv->phydev))
ca8cf341 2612 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
1c1008c7 2613
1c1008c7
FF		 2614 if (!IS_ERR(priv->clk))
2615 clk_disable_unprepare(priv->clk);
2616
ca8cf341 2617 return ret;
1c1008c7
FF		 2618}
2619
2620static void bcmgenet_timeout(struct net_device *dev)
2621{
2622 struct bcmgenet_priv *priv = netdev_priv(dev);
2623
2624 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2625
2626 dev->trans_start = jiffies;
2627
2628 dev->stats.tx_errors++;
2629
2630 netif_tx_wake_all_queues(dev);
2631}
2632
2633#define MAX_MC_COUNT 16
2634
2635static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2636 unsigned char *addr,
2637 int *i,
2638 int *mc)
2639{
2640 u32 reg;
2641
c91b7f66
FF		 2642 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2643 UMAC_MDF_ADDR + (*i * 4));
2644 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2645 addr[4] << 8 | addr[5],
2646 UMAC_MDF_ADDR + ((*i + 1) * 4));
1c1008c7
FF		 2647 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2648 reg |= (1 << (MAX_MC_COUNT - *mc));
2649 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2650 *i += 2;
2651 (*mc)++;
2652}
2653
2654static void bcmgenet_set_rx_mode(struct net_device *dev)
2655{
2656 struct bcmgenet_priv *priv = netdev_priv(dev);
2657 struct netdev_hw_addr *ha;
2658 int i, mc;
2659 u32 reg;
2660
2661 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2662
7fc527f9 2663 /* Promiscuous mode */
1c1008c7
FF		 2664 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2665 if (dev->flags & IFF_PROMISC) {
2666 reg |= CMD_PROMISC;
2667 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2668 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2669 return;
2670 } else {
2671 reg &= ~CMD_PROMISC;
2672 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2673 }
2674
2675 /* UniMac doesn't support ALLMULTI */
2676 if (dev->flags & IFF_ALLMULTI) {
2677 netdev_warn(dev, "ALLMULTI is not supported\n");
2678 return;
2679 }
2680
2681 /* update MDF filter */
2682 i = 0;
2683 mc = 0;
2684 /* Broadcast */
2685 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2686 /* my own address.*/
2687 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2688 /* Unicast list*/
2689 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2690 return;
2691
2692 if (!netdev_uc_empty(dev))
2693 netdev_for_each_uc_addr(ha, dev)
2694 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2695 /* Multicast */
2696 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2697 return;
2698
2699 netdev_for_each_mc_addr(ha, dev)
2700 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2701}
2702
2703/* Set the hardware MAC address. */
2704static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2705{
2706 struct sockaddr *addr = p;
2707
2708 /* Setting the MAC address at the hardware level is not possible
2709 * without disabling the UniMAC RX/TX enable bits.
2710 */
2711 if (netif_running(dev))
2712 return -EBUSY;
2713
2714 ether_addr_copy(dev->dev_addr, addr->sa_data);
2715
2716 return 0;
2717}
2718
1c1008c7
FF		 2719static const struct net_device_ops bcmgenet_netdev_ops = {
2720 .ndo_open = bcmgenet_open,
2721 .ndo_stop = bcmgenet_close,
2722 .ndo_start_xmit = bcmgenet_xmit,
1c1008c7
FF		 2723 .ndo_tx_timeout = bcmgenet_timeout,
2724 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2725 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2726 .ndo_do_ioctl = bcmgenet_ioctl,
2727 .ndo_set_features = bcmgenet_set_features,
2728};
2729
2730/* Array of GENET hardware parameters/characteristics */
2731static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2732 [GENET_V1] = {
2733 .tx_queues = 0,
51a966a7 2734 .tx_bds_per_q = 0,
1c1008c7 2735 .rx_queues = 0,
3feafa02 2736 .rx_bds_per_q = 0,
1c1008c7
FF		 2737 .bp_in_en_shift = 16,
2738 .bp_in_mask = 0xffff,
2739 .hfb_filter_cnt = 16,
2740 .qtag_mask = 0x1F,
2741 .hfb_offset = 0x1000,
2742 .rdma_offset = 0x2000,
2743 .tdma_offset = 0x3000,
2744 .words_per_bd = 2,
2745 },
2746 [GENET_V2] = {
2747 .tx_queues = 4,
51a966a7 2748 .tx_bds_per_q = 32,
7e906e02 2749 .rx_queues = 0,
3feafa02 2750 .rx_bds_per_q = 0,
1c1008c7
FF		 2751 .bp_in_en_shift = 16,
2752 .bp_in_mask = 0xffff,
2753 .hfb_filter_cnt = 16,
2754 .qtag_mask = 0x1F,
2755 .tbuf_offset = 0x0600,
2756 .hfb_offset = 0x1000,
2757 .hfb_reg_offset = 0x2000,
2758 .rdma_offset = 0x3000,
2759 .tdma_offset = 0x4000,
2760 .words_per_bd = 2,
2761 .flags = GENET_HAS_EXT,
2762 },
2763 [GENET_V3] = {
2764 .tx_queues = 4,
51a966a7 2765 .tx_bds_per_q = 32,
7e906e02 2766 .rx_queues = 0,
3feafa02 2767 .rx_bds_per_q = 0,
1c1008c7
FF		 2768 .bp_in_en_shift = 17,
2769 .bp_in_mask = 0x1ffff,
2770 .hfb_filter_cnt = 48,
0034de41 2771 .hfb_filter_size = 128,
1c1008c7
FF		 2772 .qtag_mask = 0x3F,
2773 .tbuf_offset = 0x0600,
2774 .hfb_offset = 0x8000,
2775 .hfb_reg_offset = 0xfc00,
2776 .rdma_offset = 0x10000,
2777 .tdma_offset = 0x11000,
2778 .words_per_bd = 2,
2779 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2780 },
2781 [GENET_V4] = {
2782 .tx_queues = 4,
51a966a7 2783 .tx_bds_per_q = 32,
7e906e02 2784 .rx_queues = 0,
3feafa02 2785 .rx_bds_per_q = 0,
1c1008c7
FF		 2786 .bp_in_en_shift = 17,
2787 .bp_in_mask = 0x1ffff,
2788 .hfb_filter_cnt = 48,
0034de41 2789 .hfb_filter_size = 128,
1c1008c7
FF		 2790 .qtag_mask = 0x3F,
2791 .tbuf_offset = 0x0600,
2792 .hfb_offset = 0x8000,
2793 .hfb_reg_offset = 0xfc00,
2794 .rdma_offset = 0x2000,
2795 .tdma_offset = 0x4000,
2796 .words_per_bd = 3,
2797 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2798 },
2799};
2800
2801/* Infer hardware parameters from the detected GENET version */
2802static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2803{
2804 struct bcmgenet_hw_params *params;
2805 u32 reg;
2806 u8 major;
b04a2f5b 2807 u16 gphy_rev;
1c1008c7
FF		 2808
2809 if (GENET_IS_V4(priv)) {
2810 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2811 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2812 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2813 priv->version = GENET_V4;
2814 } else if (GENET_IS_V3(priv)) {
2815 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2816 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2817 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2818 priv->version = GENET_V3;
2819 } else if (GENET_IS_V2(priv)) {
2820 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2821 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2822 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2823 priv->version = GENET_V2;
2824 } else if (GENET_IS_V1(priv)) {
2825 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2826 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2827 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2828 priv->version = GENET_V1;
2829 }
2830
2831 /* enum genet_version starts at 1 */
2832 priv->hw_params = &bcmgenet_hw_params[priv->version];
2833 params = priv->hw_params;
2834
2835 /* Read GENET HW version */
2836 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2837 major = (reg >> 24 & 0x0f);
2838 if (major == 5)
2839 major = 4;
2840 else if (major == 0)
2841 major = 1;
2842 if (major != priv->version) {
2843 dev_err(&priv->pdev->dev,
2844 "GENET version mismatch, got: %d, configured for: %d\n",
2845 major, priv->version);
2846 }
2847
2848 /* Print the GENET core version */
2849 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
c91b7f66 2850 major, (reg >> 16) & 0x0f, reg & 0xffff);
1c1008c7 2851
487320c5
FF		 2852 /* Store the integrated PHY revision for the MDIO probing function
2853 * to pass this information to the PHY driver. The PHY driver expects
2854 * to find the PHY major revision in bits 15:8 while the GENET register
2855 * stores that information in bits 7:0, account for that.
b04a2f5b
FF		 2856 *
2857 * On newer chips, starting with PHY revision G0, a new scheme is
2858 * deployed similar to the Starfighter 2 switch with GPHY major
2859 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2860 * is reserved as well as special value 0x01ff, we have a small
2861 * heuristic to check for the new GPHY revision and re-arrange things
2862 * so the GPHY driver is happy.
487320c5 2863 */
b04a2f5b
FF		 2864 gphy_rev = reg & 0xffff;
2865
2866 /* This is the good old scheme, just GPHY major, no minor nor patch */
2867 if ((gphy_rev & 0xf0) != 0)
2868 priv->gphy_rev = gphy_rev << 8;
2869
2870 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2871 else if ((gphy_rev & 0xff00) != 0)
2872 priv->gphy_rev = gphy_rev;
2873
2874 /* This is reserved so should require special treatment */
2875 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2876 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2877 return;
2878 }
487320c5 2879
1c1008c7
FF		 2880#ifdef CONFIG_PHYS_ADDR_T_64BIT
2881 if (!(params->flags & GENET_HAS_40BITS))
2882 pr_warn("GENET does not support 40-bits PA\n");
2883#endif
2884
2885 pr_debug("Configuration for version: %d\n"
3feafa02 2886 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
1c1008c7
FF		 2887 "BP << en: %2d, BP msk: 0x%05x\n"
2888 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2889 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2890 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2891 "Words/BD: %d\n",
2892 priv->version,
51a966a7 2893 params->tx_queues, params->tx_bds_per_q,
3feafa02 2894 params->rx_queues, params->rx_bds_per_q,
1c1008c7
FF		 2895 params->bp_in_en_shift, params->bp_in_mask,
2896 params->hfb_filter_cnt, params->qtag_mask,
2897 params->tbuf_offset, params->hfb_offset,
2898 params->hfb_reg_offset,
2899 params->rdma_offset, params->tdma_offset,
2900 params->words_per_bd);
2901}
2902
2903static const struct of_device_id bcmgenet_match[] = {
2904 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2905 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2906 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2907 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2908 { },
2909};
2910
2911static int bcmgenet_probe(struct platform_device *pdev)
2912{
b0ba512e 2913 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
1c1008c7 2914 struct device_node *dn = pdev->dev.of_node;
b0ba512e 2915 const struct of_device_id *of_id = NULL;
1c1008c7
FF		 2916 struct bcmgenet_priv *priv;
2917 struct net_device *dev;
2918 const void *macaddr;
2919 struct resource *r;
2920 int err = -EIO;
2921
3feafeed
PG		 2922 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
2923 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
2924 GENET_MAX_MQ_CNT + 1);
1c1008c7
FF		 2925 if (!dev) {
2926 dev_err(&pdev->dev, "can't allocate net device\n");
2927 return -ENOMEM;
2928 }
2929
b0ba512e
PG		 2930 if (dn) {
2931 of_id = of_match_node(bcmgenet_match, dn);
2932 if (!of_id)
2933 return -EINVAL;
2934 }
1c1008c7
FF		 2935
2936 priv = netdev_priv(dev);
2937 priv->irq0 = platform_get_irq(pdev, 0);
2938 priv->irq1 = platform_get_irq(pdev, 1);
8562056f 2939 priv->wol_irq = platform_get_irq(pdev, 2);
1c1008c7
FF		 2940 if (!priv->irq0 || !priv->irq1) {
2941 dev_err(&pdev->dev, "can't find IRQs\n");
2942 err = -EINVAL;
2943 goto err;
2944 }
2945
b0ba512e
PG		 2946 if (dn) {
2947 macaddr = of_get_mac_address(dn);
2948 if (!macaddr) {
2949 dev_err(&pdev->dev, "can't find MAC address\n");
2950 err = -EINVAL;
2951 goto err;
2952 }
2953 } else {
2954 macaddr = pd->mac_address;
1c1008c7
FF		 2955 }
2956
2957 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5343a10d
FE		 2958 priv->base = devm_ioremap_resource(&pdev->dev, r);
2959 if (IS_ERR(priv->base)) {
2960 err = PTR_ERR(priv->base);
1c1008c7
FF		 2961 goto err;
2962 }
2963
2964 SET_NETDEV_DEV(dev, &pdev->dev);
2965 dev_set_drvdata(&pdev->dev, dev);
2966 ether_addr_copy(dev->dev_addr, macaddr);
2967 dev->watchdog_timeo = 2 * HZ;
7ad24ea4 2968 dev->ethtool_ops = &bcmgenet_ethtool_ops;
1c1008c7
FF		 2969 dev->netdev_ops = &bcmgenet_netdev_ops;
2970 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2971
2972 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2973
2974 /* Set hardware features */
2975 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2976 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2977
8562056f
FF		 2978 /* Request the WOL interrupt and advertise suspend if available */
2979 priv->wol_irq_disabled = true;
2980 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2981 dev->name, priv);
2982 if (!err)
2983 device_set_wakeup_capable(&pdev->dev, 1);
2984
1c1008c7
FF		 2985 /* Set the needed headroom to account for any possible
2986 * features enabling/disabling at runtime
2987 */
2988 dev->needed_headroom += 64;
2989
2990 netdev_boot_setup_check(dev);
2991
2992 priv->dev = dev;
2993 priv->pdev = pdev;
b0ba512e
PG		 2994 if (of_id)
2995 priv->version = (enum bcmgenet_version)of_id->data;
2996 else
2997 priv->version = pd->genet_version;
1c1008c7 2998
e4a60a93
FF		 2999 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3000 if (IS_ERR(priv->clk))
3001 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3002
3003 if (!IS_ERR(priv->clk))
3004 clk_prepare_enable(priv->clk);
3005
1c1008c7
FF		 3006 bcmgenet_set_hw_params(priv);
3007
1c1008c7
FF		 3008 /* Mii wait queue */
3009 init_waitqueue_head(&priv->wq);
3010 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3011 priv->rx_buf_len = RX_BUF_LENGTH;
3012 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3013
1c1008c7
FF		 3014 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3015 if (IS_ERR(priv->clk_wol))
3016 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3017
6ef398ea
FF		 3018 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3019 if (IS_ERR(priv->clk_eee)) {
3020 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3021 priv->clk_eee = NULL;
3022 }
3023
1c1008c7
FF		 3024 err = reset_umac(priv);
3025 if (err)
3026 goto err_clk_disable;
3027
3028 err = bcmgenet_mii_init(dev);
3029 if (err)
3030 goto err_clk_disable;
3031
3032 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3033 * just the ring 16 descriptor based TX
3034 */
3035 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3036 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3037
219575eb
FF		 3038 /* libphy will determine the link state */
3039 netif_carrier_off(dev);
3040
1c1008c7
FF		 3041 /* Turn off the main clock, WOL clock is handled separately */
3042 if (!IS_ERR(priv->clk))
3043 clk_disable_unprepare(priv->clk);
3044
0f50ce96
FF		 3045 err = register_netdev(dev);
3046 if (err)
3047 goto err;
3048
1c1008c7
FF		 3049 return err;
3050
3051err_clk_disable:
3052 if (!IS_ERR(priv->clk))
3053 clk_disable_unprepare(priv->clk);
3054err:
3055 free_netdev(dev);
3056 return err;
3057}
3058
3059static int bcmgenet_remove(struct platform_device *pdev)
3060{
3061 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3062
3063 dev_set_drvdata(&pdev->dev, NULL);
3064 unregister_netdev(priv->dev);
3065 bcmgenet_mii_exit(priv->dev);
3066 free_netdev(priv->dev);
3067
3068 return 0;
3069}
3070
b6e978e5
FF		 3071#ifdef CONFIG_PM_SLEEP
3072static int bcmgenet_suspend(struct device *d)
3073{
3074 struct net_device *dev = dev_get_drvdata(d);
3075 struct bcmgenet_priv *priv = netdev_priv(dev);
3076 int ret;
3077
3078 if (!netif_running(dev))
3079 return 0;
3080
3081 bcmgenet_netif_stop(dev);
3082
cc013fb4
FF		 3083 phy_suspend(priv->phydev);
3084
b6e978e5
FF		 3085 netif_device_detach(dev);
3086
3087 /* Disable MAC receive */
3088 umac_enable_set(priv, CMD_RX_EN, false);
3089
3090 ret = bcmgenet_dma_teardown(priv);
3091 if (ret)
3092 return ret;
3093
3094 /* Disable MAC transmit. TX DMA disabled have to done before this */
3095 umac_enable_set(priv, CMD_TX_EN, false);
3096
3097 /* tx reclaim */
3098 bcmgenet_tx_reclaim_all(dev);
3099 bcmgenet_fini_dma(priv);
3100
8c90db72
FF		 3101 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3102 if (device_may_wakeup(d) && priv->wolopts) {
ca8cf341 3103 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
8c90db72
FF		 3104 clk_prepare_enable(priv->clk_wol);
3105 }
3106
b6e978e5
FF		 3107 /* Turn off the clocks */
3108 clk_disable_unprepare(priv->clk);
3109
ca8cf341 3110 return ret;
b6e978e5
FF		 3111}
3112
3113static int bcmgenet_resume(struct device *d)
3114{
3115 struct net_device *dev = dev_get_drvdata(d);
3116 struct bcmgenet_priv *priv = netdev_priv(dev);
3117 unsigned long dma_ctrl;
3118 int ret;
3119 u32 reg;
3120
3121 if (!netif_running(dev))
3122 return 0;
3123
3124 /* Turn on the clock */
3125 ret = clk_prepare_enable(priv->clk);
3126 if (ret)
3127 return ret;
3128
3129 bcmgenet_umac_reset(priv);
3130
3131 ret = init_umac(priv);
3132 if (ret)
3133 goto out_clk_disable;
3134
0a29b3da
TK		 3135 /* From WOL-enabled suspend, switch to regular clock */
3136 if (priv->wolopts)
3137 clk_disable_unprepare(priv->clk_wol);
3138
3139 phy_init_hw(priv->phydev);
3140 /* Speed settings must be restored */
dbd479db 3141 bcmgenet_mii_config(priv->dev, false);
8c90db72 3142
b6e978e5
FF		 3143 /* disable ethernet MAC while updating its registers */
3144 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3145
3146 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3147
3148 if (phy_is_internal(priv->phydev)) {
3149 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3150 reg |= EXT_ENERGY_DET_MASK;
3151 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3152 }
3153
98bb7399
FF		 3154 if (priv->wolopts)
3155 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3156
b6e978e5
FF		 3157 /* Disable RX/TX DMA and flush TX queues */
3158 dma_ctrl = bcmgenet_dma_disable(priv);
3159
3160 /* Reinitialize TDMA and RDMA and SW housekeeping */
3161 ret = bcmgenet_init_dma(priv);
3162 if (ret) {
3163 netdev_err(dev, "failed to initialize DMA\n");
3164 goto out_clk_disable;
3165 }
3166
3167 /* Always enable ring 16 - descriptor ring */
3168 bcmgenet_enable_dma(priv, dma_ctrl);
3169
3170 netif_device_attach(dev);
3171
cc013fb4
FF		 3172 phy_resume(priv->phydev);
3173
6ef398ea
FF		 3174 if (priv->eee.eee_enabled)
3175 bcmgenet_eee_enable_set(dev, true);
3176
b6e978e5
FF		 3177 bcmgenet_netif_start(dev);
3178
3179 return 0;
3180
3181out_clk_disable:
3182 clk_disable_unprepare(priv->clk);
3183 return ret;
3184}
3185#endif /* CONFIG_PM_SLEEP */
3186
3187static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3188
1c1008c7
FF		 3189static struct platform_driver bcmgenet_driver = {
3190 .probe = bcmgenet_probe,
3191 .remove = bcmgenet_remove,
3192 .driver = {
3193 .name = "bcmgenet",
1c1008c7 3194 .of_match_table = bcmgenet_match,
b6e978e5 3195 .pm = &bcmgenet_pm_ops,
1c1008c7
FF		 3196 },
3197};
3198module_platform_driver(bcmgenet_driver);
3199
3200MODULE_AUTHOR("Broadcom Corporation");
3201MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3202MODULE_ALIAS("platform:bcmgenet");
3203MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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