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tg3: Prevent page allocation failure during TSO workaround
[deliverable/linux.git] / drivers / net / ethernet / broadcom / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
b681b65d 7 * Copyright (C) 2005-2013 Broadcom Corporation.
1da177e4
LT		 8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
1da177e4
LT		 18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
6867c843 21#include <linux/stringify.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
14c85021 27#include <linux/in.h>
a6b7a407 28#include <linux/interrupt.h>
1da177e4
LT		 29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
3110f5f5 35#include <linux/mdio.h>
1da177e4 36#include <linux/mii.h>
158d7abd 37#include <linux/phy.h>
a9daf367 38#include <linux/brcmphy.h>
e565eec3 39#include <linux/if.h>
1da177e4
LT		 40#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
61487480 44#include <linux/prefetch.h>
f9a5f7d3 45#include <linux/dma-mapping.h>
077f849d 46#include <linux/firmware.h>
7e6c63f0 47#include <linux/ssb/ssb_driver_gige.h>
aed93e0b
MC		 48#include <linux/hwmon.h>
49#include <linux/hwmon-sysfs.h>
1da177e4
LT		 50
51#include <net/checksum.h>
c9bdd4b5 52#include <net/ip.h>
1da177e4 53
27fd9de8 54#include <linux/io.h>
1da177e4 55#include <asm/byteorder.h>
27fd9de8 56#include <linux/uaccess.h>
1da177e4 57
be947307
MC		 58#include <uapi/linux/net_tstamp.h>
59#include <linux/ptp_clock_kernel.h>
60
49b6e95f 61#ifdef CONFIG_SPARC
1da177e4 62#include <asm/idprom.h>
49b6e95f 63#include <asm/prom.h>
1da177e4
LT		 64#endif
65
63532394
MC		 66#define BAR_0 0
67#define BAR_2 2
68
1da177e4
LT		 69#include "tg3.h"
70
63c3a66f
JP		 71/* Functions & macros to verify TG3_FLAGS types */
72
73static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 return test_bit(flag, bits);
76}
77
78static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 set_bit(flag, bits);
81}
82
83static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
84{
85 clear_bit(flag, bits);
86}
87
88#define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90#define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92#define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
94
1da177e4 95#define DRV_MODULE_NAME "tg3"
6867c843 96#define TG3_MAJ_NUM 3
20170e77 97#define TG3_MIN_NUM 136
6867c843
MC		 98#define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
20170e77 100#define DRV_MODULE_RELDATE "Jan 03, 2014"
1da177e4 101
fd6d3f0e
MC		 102#define RESET_KIND_SHUTDOWN 0
103#define RESET_KIND_INIT 1
104#define RESET_KIND_SUSPEND 2
105
1da177e4
LT		 106#define TG3_DEF_RX_MODE 0
107#define TG3_DEF_TX_MODE 0
108#define TG3_DEF_MSG_ENABLE \
109 (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK | \
112 NETIF_MSG_TIMER | \
113 NETIF_MSG_IFDOWN | \
114 NETIF_MSG_IFUP | \
115 NETIF_MSG_RX_ERR | \
116 NETIF_MSG_TX_ERR)
117
520b2756
MC		 118#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
119
1da177e4
LT		 120/* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
122 */
63c3a66f 123
1da177e4
LT		 124#define TG3_TX_TIMEOUT (5 * HZ)
125
126/* hardware minimum and maximum for a single frame's data payload */
127#define TG3_MIN_MTU 60
128#define TG3_MAX_MTU(tp) \
63c3a66f 129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 130
131/* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
134 */
7cb32cf2 135#define TG3_RX_STD_RING_SIZE(tp) \
63c3a66f 136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
1da177e4 138#define TG3_DEF_RX_RING_PENDING 200
7cb32cf2 139#define TG3_RX_JMB_RING_SIZE(tp) \
63c3a66f 140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
de9f5230 141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
1da177e4
LT		 142#define TG3_DEF_RX_JUMBO_RING_PENDING 100
143
144/* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
149 */
1da177e4
LT		 150
151#define TG3_TX_RING_SIZE 512
152#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
153
2c49a44d
MC		 154#define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156#define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158#define TG3_RX_RCB_RING_BYTES(tp) \
7cb32cf2 159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
1da177e4
LT		 160#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
161 TG3_TX_RING_SIZE)
1da177e4
LT		 162#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
163
287be12e
MC		 164#define TG3_DMA_BYTE_ENAB 64
165
166#define TG3_RX_STD_DMA_SZ 1536
167#define TG3_RX_JMB_DMA_SZ 9046
168
169#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
170
171#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
1da177e4 173
2c49a44d
MC		 174#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
2b2cdb65 176
2c49a44d
MC		 177#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
2b2cdb65 179
d2757fc4
MC		 180/* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
184 *
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
190 */
191#define TG3_RX_COPY_THRESHOLD 256
192#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
194#else
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196#endif
197
81389f57
MC		 198#if (NET_IP_ALIGN != 0)
199#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
200#else
9205fd9c 201#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
81389f57
MC		 202#endif
203
1da177e4 204/* minimum number of free TX descriptors required to wake up TX process */
f3f3f27e 205#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
55086ad9 206#define TG3_TX_BD_DMA_MAX_2K 2048
a4cb428d 207#define TG3_TX_BD_DMA_MAX_4K 4096
1da177e4 208
ad829268
MC		 209#define TG3_RAW_IP_ALIGN 2
210
e565eec3
MC		 211#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
213
c6cdf436 214#define TG3_FW_UPDATE_TIMEOUT_SEC 5
21f7638e 215#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
c6cdf436 216
077f849d 217#define FIRMWARE_TG3 "tigon/tg3.bin"
c4dab506 218#define FIRMWARE_TG357766 "tigon/tg357766.bin"
077f849d
JSR		 219#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
221
229b1ad1 222static char version[] =
05dbe005 223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
1da177e4
LT		 224
225MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_MODULE_VERSION);
077f849d
JSR		 229MODULE_FIRMWARE(FIRMWARE_TG3);
230MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232
1da177e4
LT		 233static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234module_param(tg3_debug, int, 0);
235MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236
3d567e0e
NNS		 237#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239
a3aa1884 240static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
13185217
HK		 241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
3d567e0e
NNS		 259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
3d567e0e
NNS		 266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
13185217 269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
126a3368 270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
7e6c63f0 271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
13185217 272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
13185217 273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
3d567e0e
NNS		 274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
3d567e0e
NNS		 280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
126a3368 286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
13185217
HK		 287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
3d567e0e
NNS		 289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217 293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
3d567e0e
NNS		 294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
13185217
HK		 296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
b5d3772c
MC		 303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
d30cdd28
MC		 305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
6c7af27c 307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
9936bcf6
MC		 308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
c88e668b
MC		 310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
2befdcea
MC		 312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
3d567e0e
NNS		 314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321d32a0
MC		 320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
3d567e0e
NNS		 322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
5e7ccf20 324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
5001e2f6 325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
79d49695 326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
5001e2f6 327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
b0f75221
MC		 328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
3d567e0e
NNS		 332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
302b500b 336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
ba1f3c76 337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
02eca3f5 338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
d3f677af 339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
c86a8560
MC		 340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
68273712
NS		 343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
13185217
HK		 348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
1dcb14d9 355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
13185217 356 {}
1da177e4
LT		 357};
358
359MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360
50da859d 361static const struct {
1da177e4 362 const char string[ETH_GSTRING_LEN];
48fa55a0 363} ethtool_stats_keys[] = {
1da177e4
LT		 364 { "rx_octets" },
365 { "rx_fragments" },
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
369 { "rx_fcs_errors" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
376 { "rx_jabbers" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
390
391 { "tx_octets" },
392 { "tx_collisions" },
393
394 { "tx_xon_sent" },
395 { "tx_xoff_sent" },
396 { "tx_flow_control" },
397 { "tx_mac_errors" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
400 { "tx_deferred" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
421 { "tx_discards" },
422 { "tx_errors" },
423
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
426 { "rxbds_empty" },
427 { "rx_discards" },
428 { "rx_errors" },
429 { "rx_threshold_hit" },
430
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
434
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
437 { "nic_irqs" },
438 { "nic_avoided_irqs" },
4452d099
MC		 439 { "nic_tx_threshold_hit" },
440
441 { "mbuf_lwm_thresh_hit" },
1da177e4
LT		 442};
443
48fa55a0 444#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
93df8b8f
NNS		 445#define TG3_NVRAM_TEST 0
446#define TG3_LINK_TEST 1
447#define TG3_REGISTER_TEST 2
448#define TG3_MEMORY_TEST 3
449#define TG3_MAC_LOOPB_TEST 4
450#define TG3_PHY_LOOPB_TEST 5
451#define TG3_EXT_LOOPB_TEST 6
452#define TG3_INTERRUPT_TEST 7
48fa55a0
MC		 453
454
50da859d 455static const struct {
4cafd3f5 456 const char string[ETH_GSTRING_LEN];
48fa55a0 457} ethtool_test_keys[] = {
93df8b8f
NNS		 458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
4cafd3f5
MC		 466};
467
48fa55a0
MC		 468#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
469
470
b401e9e2
MC		 471static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472{
473 writel(val, tp->regs + off);
474}
475
476static u32 tg3_read32(struct tg3 *tp, u32 off)
477{
de6f31eb 478 return readl(tp->regs + off);
b401e9e2
MC		 479}
480
0d3031d9
MC		 481static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482{
483 writel(val, tp->aperegs + off);
484}
485
486static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487{
de6f31eb 488 return readl(tp->aperegs + off);
0d3031d9
MC		 489}
490
1da177e4
LT		 491static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492{
6892914f
MC		 493 unsigned long flags;
494
495 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 499}
500
501static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502{
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
1da177e4
LT		 505}
506
6892914f 507static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 508{
6892914f
MC		 509 unsigned long flags;
510 u32 val;
511
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 return val;
517}
518
519static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520{
521 unsigned long flags;
522
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
526 return;
527 }
66711e66 528 if (off == TG3_RX_STD_PROD_IDX_REG) {
6892914f
MC		 529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
531 return;
1da177e4 532 }
6892914f
MC		 533
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
541 */
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 (val == 0x1)) {
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 }
547}
548
549static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
550{
551 unsigned long flags;
552 u32 val;
553
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 return val;
559}
560
b401e9e2
MC		 561/* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 */
566static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
6892914f 567{
63c3a66f 568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
b401e9e2
MC		 569 /* Non-posted methods */
570 tp->write32(tp, off, val);
571 else {
572 /* Posted method */
573 tg3_write32(tp, off, val);
574 if (usec_wait)
575 udelay(usec_wait);
576 tp->read32(tp, off);
577 }
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
580 */
581 if (usec_wait)
582 udelay(usec_wait);
1da177e4
LT		 583}
584
09ee929c
MC		 585static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586{
587 tp->write32_mbox(tp, off, val);
7e6c63f0
HM		 588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
6892914f 591 tp->read32_mbox(tp, off);
09ee929c
MC		 592}
593
20094930 594static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 595{
596 void __iomem *mbox = tp->regs + off;
597 writel(val, mbox);
63c3a66f 598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
1da177e4 599 writel(val, mbox);
7e6c63f0
HM		 600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
1da177e4
LT		 602 readl(mbox);
603}
604
b5d3772c
MC		 605static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606{
de6f31eb 607 return readl(tp->regs + off + GRCMBOX_BASE);
b5d3772c
MC		 608}
609
610static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611{
612 writel(val, tp->regs + off + GRCMBOX_BASE);
613}
614
c6cdf436 615#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 616#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
c6cdf436
MC		 617#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930 620
c6cdf436
MC		 621#define tw32(reg, val) tp->write32(tp, reg, val)
622#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 625
626static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627{
6892914f
MC		 628 unsigned long flags;
629
4153577a 630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
632 return;
633
6892914f 634 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 638
bbadf503
MC		 639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 } else {
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
28fbef78 644
bbadf503
MC		 645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 }
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
758a6139
DM		 649}
650
1da177e4
LT		 651static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652{
6892914f
MC		 653 unsigned long flags;
654
4153577a 655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
b5d3772c
MC		 656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
657 *val = 0;
658 return;
659 }
660
6892914f 661 spin_lock_irqsave(&tp->indirect_lock, flags);
63c3a66f 662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
bbadf503
MC		 663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
1da177e4 665
bbadf503
MC		 666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 } else {
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
671
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 }
6892914f 675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 676}
677
0d3031d9
MC		 678static void tg3_ape_lock_init(struct tg3 *tp)
679{
680 int i;
6f5c8f83 681 u32 regbase, bit;
f92d9dc1 682
4153577a 683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 684 regbase = TG3_APE_LOCK_GRANT;
685 else
686 regbase = TG3_APE_PER_LOCK_GRANT;
0d3031d9
MC		 687
688 /* Make sure the driver hasn't any stale locks. */
78f94dc7
MC		 689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 switch (i) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
696 break;
697 default:
698 if (!tp->pci_fn)
699 bit = APE_LOCK_GRANT_DRIVER;
700 else
701 bit = 1 << tp->pci_fn;
702 }
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
6f5c8f83
MC		 704 }
705
0d3031d9
MC		 706}
707
708static int tg3_ape_lock(struct tg3 *tp, int locknum)
709{
710 int i, off;
711 int ret = 0;
6f5c8f83 712 u32 status, req, gnt, bit;
0d3031d9 713
63c3a66f 714 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 715 return 0;
716
717 switch (locknum) {
6f5c8f83 718 case TG3_APE_LOCK_GPIO:
4153577a 719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 720 return 0;
33f401ae
MC		 721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 723 if (!tp->pci_fn)
724 bit = APE_LOCK_REQ_DRIVER;
725 else
726 bit = 1 << tp->pci_fn;
33f401ae 727 break;
8151ad57
MC		 728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
733 break;
33f401ae
MC		 734 default:
735 return -EINVAL;
0d3031d9
MC		 736 }
737
4153577a 738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
f92d9dc1
MC		 739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
741 } else {
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
744 }
745
0d3031d9
MC		 746 off = 4 * locknum;
747
6f5c8f83 748 tg3_ape_write32(tp, req + off, bit);
0d3031d9
MC		 749
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
f92d9dc1 752 status = tg3_ape_read32(tp, gnt + off);
6f5c8f83 753 if (status == bit)
0d3031d9 754 break;
6d446ec3
GS		 755 if (pci_channel_offline(tp->pdev))
756 break;
757
0d3031d9
MC		 758 udelay(10);
759 }
760
6f5c8f83 761 if (status != bit) {
0d3031d9 762 /* Revoke the lock request. */
6f5c8f83 763 tg3_ape_write32(tp, gnt + off, bit);
0d3031d9
MC		 764 ret = -EBUSY;
765 }
766
767 return ret;
768}
769
770static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771{
6f5c8f83 772 u32 gnt, bit;
0d3031d9 773
63c3a66f 774 if (!tg3_flag(tp, ENABLE_APE))
0d3031d9
MC		 775 return;
776
777 switch (locknum) {
6f5c8f83 778 case TG3_APE_LOCK_GPIO:
4153577a 779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
6f5c8f83 780 return;
33f401ae
MC		 781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
78f94dc7
MC		 783 if (!tp->pci_fn)
784 bit = APE_LOCK_GRANT_DRIVER;
785 else
786 bit = 1 << tp->pci_fn;
33f401ae 787 break;
8151ad57
MC		 788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
793 break;
33f401ae
MC		 794 default:
795 return;
0d3031d9
MC		 796 }
797
4153577a 798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
f92d9dc1
MC		 799 gnt = TG3_APE_LOCK_GRANT;
800 else
801 gnt = TG3_APE_PER_LOCK_GRANT;
802
6f5c8f83 803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
0d3031d9
MC		 804}
805
b65a372b 806static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
fd6d3f0e 807{
fd6d3f0e
MC		 808 u32 apedata;
809
b65a372b
MC		 810 while (timeout_us) {
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
812 return -EBUSY;
813
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
816 break;
817
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
819
820 udelay(10);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
822 }
823
824 return timeout_us ? 0 : -EBUSY;
825}
826
cf8d55ae
MC		 827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
86449944
MC		 843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
cf8d55ae
MC		 845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906
b65a372b
MC		 907static int tg3_ape_send_event(struct tg3 *tp, u32 event)
908{
909 int err;
910 u32 apedata;
fd6d3f0e
MC		 911
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
b65a372b 914 return -EAGAIN;
fd6d3f0e
MC		 915
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
b65a372b 918 return -EAGAIN;
fd6d3f0e
MC		 919
920 /* Wait for up to 1 millisecond for APE to service previous event. */
b65a372b
MC		 921 err = tg3_ape_event_lock(tp, 1000);
922 if (err)
923 return err;
fd6d3f0e 924
b65a372b
MC		 925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
fd6d3f0e 927
b65a372b
MC		 928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
fd6d3f0e 930
b65a372b 931 return 0;
fd6d3f0e
MC		 932}
933
934static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
935{
936 u32 event;
937 u32 apedata;
938
939 if (!tg3_flag(tp, ENABLE_APE))
940 return;
941
942 switch (kind) {
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
956
957 event = APE_EVENT_STATUS_STATE_START;
958 break;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
964 */
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
966
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
972 } else
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
974
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
976
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
978 break;
fd6d3f0e
MC		 979 default:
980 return;
981 }
982
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
984
985 tg3_ape_send_event(tp, event);
986}
987
1da177e4
LT		 988static void tg3_disable_ints(struct tg3 *tp)
989{
89aeb3bc
MC		 990 int i;
991
1da177e4
LT		 992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc
MC		 994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1da177e4
LT		 996}
997
1da177e4
LT		 998static void tg3_enable_ints(struct tg3 *tp)
999{
89aeb3bc 1000 int i;
89aeb3bc 1001
bbe832c0
MC		 1002 tp->irq_sync = 0;
1003 wmb();
1004
1da177e4
LT		 1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
89aeb3bc 1007
f89f38b8 1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
89aeb3bc
MC		 1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
c6cdf436 1011
898a56f8 1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
63c3a66f 1013 if (tg3_flag(tp, 1SHOT_MSI))
89aeb3bc 1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
f19af9c2 1015
f89f38b8 1016 tp->coal_now |= tnapi->coal_now;
89aeb3bc 1017 }
f19af9c2
MC		 1018
1019 /* Force an initial interrupt */
63c3a66f 1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
f19af9c2
MC		 1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1023 else
f89f38b8
MC		 1024 tw32(HOSTCC_MODE, tp->coal_now);
1025
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1da177e4
LT		 1027}
1028
17375d25 1029static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
04237ddd 1030{
17375d25 1031 struct tg3 *tp = tnapi->tp;
898a56f8 1032 struct tg3_hw_status *sblk = tnapi->hw_status;
04237ddd
MC		 1033 unsigned int work_exists = 0;
1034
1035 /* check for phy events */
63c3a66f 1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
04237ddd
MC		 1037 if (sblk->status & SD_STATUS_LINK_CHG)
1038 work_exists = 1;
1039 }
f891ea16
MC		 1040
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1043 work_exists = 1;
1044
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
8d9d7cfc 1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
04237ddd
MC		 1048 work_exists = 1;
1049
1050 return work_exists;
1051}
1052
17375d25 1053/* tg3_int_reenable
04237ddd
MC		 1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
6aa20a22 1056 * which reenables interrupts
1da177e4 1057 */
17375d25 1058static void tg3_int_reenable(struct tg3_napi *tnapi)
1da177e4 1059{
17375d25
MC		 1060 struct tg3 *tp = tnapi->tp;
1061
898a56f8 1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1da177e4
LT		 1063 mmiowb();
1064
fac9b83e
DM		 1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1068 */
63c3a66f 1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
04237ddd 1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1da177e4
LT		 1072}
1073
1da177e4
LT		 1074static void tg3_switch_clocks(struct tg3 *tp)
1075{
f6eb9b1f 1076 u32 clock_ctrl;
1da177e4
LT		 1077 u32 orig_clock_ctrl;
1078
63c3a66f 1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
4cf78e4f
MC		 1080 return;
1081
f6eb9b1f
MC		 1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1083
1da177e4
LT		 1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1087 0x1f);
1088 tp->pci_clock_ctrl = clock_ctrl;
1089
63c3a66f 1090 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4 1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
b401e9e2
MC		 1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1da177e4
LT		 1094 }
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
b401e9e2
MC		 1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1097 clock_ctrl |
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1099 40);
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1102 40);
1da177e4 1103 }
b401e9e2 1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1da177e4
LT		 1105}
1106
1107#define PHY_BUSY_LOOPS 5000
1108
5c358045
HM		 1109static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1110 u32 *val)
1da177e4
LT		 1111{
1112 u32 frame_val;
1113 unsigned int loops;
1114 int ret;
1115
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1117 tw32_f(MAC_MI_MODE,
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 udelay(80);
1120 }
1121
8151ad57
MC		 1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1123
1da177e4
LT		 1124 *val = 0x0;
1125
5c358045 1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
6aa20a22 1131
1da177e4
LT		 1132 tw32_f(MAC_MI_COM, frame_val);
1133
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1136 udelay(10);
1137 frame_val = tr32(MAC_MI_COM);
1138
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1140 udelay(5);
1141 frame_val = tr32(MAC_MI_COM);
1142 break;
1143 }
1144 loops -= 1;
1145 }
1146
1147 ret = -EBUSY;
1148 if (loops != 0) {
1149 *val = frame_val & MI_COM_DATA_MASK;
1150 ret = 0;
1151 }
1152
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 udelay(80);
1156 }
1157
8151ad57
MC		 1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1159
1da177e4
LT		 1160 return ret;
1161}
1162
5c358045
HM		 1163static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1164{
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1166}
1167
1168static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1169 u32 val)
1da177e4
LT		 1170{
1171 u32 frame_val;
1172 unsigned int loops;
1173 int ret;
1174
f07e9af3 1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
221c5637 1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
b5d3772c
MC		 1177 return 0;
1178
1da177e4
LT		 1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1180 tw32_f(MAC_MI_MODE,
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 udelay(80);
1183 }
1184
8151ad57
MC		 1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1186
5c358045 1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1da177e4
LT		 1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
6aa20a22 1193
1da177e4
LT		 1194 tw32_f(MAC_MI_COM, frame_val);
1195
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1198 udelay(10);
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1201 udelay(5);
1202 frame_val = tr32(MAC_MI_COM);
1203 break;
1204 }
1205 loops -= 1;
1206 }
1207
1208 ret = -EBUSY;
1209 if (loops != 0)
1210 ret = 0;
1211
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 udelay(80);
1215 }
1216
8151ad57
MC		 1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1218
1da177e4
LT		 1219 return ret;
1220}
1221
5c358045
HM		 1222static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1223{
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1225}
1226
b0988c15
MC		 1227static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228{
1229 int err;
1230
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 if (err)
1233 goto done;
1234
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 if (err)
1237 goto done;
1238
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 if (err)
1242 goto done;
1243
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1245
1246done:
1247 return err;
1248}
1249
1250static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251{
1252 int err;
1253
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 if (err)
1256 goto done;
1257
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 if (err)
1260 goto done;
1261
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 if (err)
1265 goto done;
1266
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1268
1269done:
1270 return err;
1271}
1272
1273static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274{
1275 int err;
1276
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1278 if (!err)
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1280
1281 return err;
1282}
1283
1284static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285{
1286 int err;
1287
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1289 if (!err)
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1291
1292 return err;
1293}
1294
15ee95c3
MC		 1295static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296{
1297 int err;
1298
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1302 if (!err)
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1304
1305 return err;
1306}
1307
b4bd2929
MC		 1308static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1309{
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1312
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1314}
1315
daf3ec68
NNS		 1316static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1317{
1318 u32 val;
1319 int err;
1d36ba45 1320
daf3ec68 1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1d36ba45 1322
daf3ec68
NNS		 1323 if (err)
1324 return err;
daf3ec68 1325
7c10ee32 1326 if (enable)
daf3ec68
NNS		 1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 else
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1330
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1333
1334 return err;
1335}
1d36ba45 1336
3ab71071
NS		 1337static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1338{
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1341}
1342
95e2869a
MC		 1343static int tg3_bmcr_reset(struct tg3 *tp)
1344{
1345 u32 phy_control;
1346 int limit, err;
1347
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1350 */
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1353 if (err != 0)
1354 return -EBUSY;
1355
1356 limit = 5000;
1357 while (limit--) {
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 if ((phy_control & BMCR_RESET) == 0) {
1363 udelay(40);
1364 break;
1365 }
1366 udelay(10);
1367 }
d4675b52 1368 if (limit < 0)
95e2869a
MC		 1369 return -EBUSY;
1370
1371 return 0;
1372}
1373
158d7abd
MC		 1374static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1375{
3d16543d 1376 struct tg3 *tp = bp->priv;
158d7abd
MC		 1377 u32 val;
1378
24bb4fb6 1379 spin_lock_bh(&tp->lock);
158d7abd 1380
ead2402c 1381 if (__tg3_readphy(tp, mii_id, reg, &val))
24bb4fb6
MC		 1382 val = -EIO;
1383
1384 spin_unlock_bh(&tp->lock);
158d7abd
MC		 1385
1386 return val;
1387}
1388
1389static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1390{
3d16543d 1391 struct tg3 *tp = bp->priv;
24bb4fb6 1392 u32 ret = 0;
158d7abd 1393
24bb4fb6 1394 spin_lock_bh(&tp->lock);
158d7abd 1395
ead2402c 1396 if (__tg3_writephy(tp, mii_id, reg, val))
24bb4fb6 1397 ret = -EIO;
158d7abd 1398
24bb4fb6
MC		 1399 spin_unlock_bh(&tp->lock);
1400
1401 return ret;
158d7abd
MC		 1402}
1403
9c61d6bc 1404static void tg3_mdio_config_5785(struct tg3 *tp)
a9daf367
MC		 1405{
1406 u32 val;
fcb389df 1407 struct phy_device *phydev;
a9daf367 1408
ead2402c 1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
fcb389df 1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f
MC		 1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
fcb389df
MC		 1413 val = MAC_PHYCFG2_50610_LED_MODES;
1414 break;
6a443a0f 1415 case PHY_ID_BCMAC131:
fcb389df
MC		 1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1417 break;
6a443a0f 1418 case PHY_ID_RTL8211C:
fcb389df
MC		 1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1420 break;
6a443a0f 1421 case PHY_ID_RTL8201E:
fcb389df
MC		 1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1423 break;
1424 default:
a9daf367 1425 return;
fcb389df
MC		 1426 }
1427
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1430
1431 val = tr32(MAC_PHYCFG1);
bb85fbb6
MC		 1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
fcb389df
MC		 1435 tw32(MAC_PHYCFG1, val);
1436
1437 return;
1438 }
1439
63c3a66f 1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
fcb389df
MC		 1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1447
1448 tw32(MAC_PHYCFG2, val);
a9daf367 1449
bb85fbb6
MC		 1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
63c3a66f
JP		 1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
63c3a66f 1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1458 }
bb85fbb6
MC		 1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
a9daf367 1462
a9daf367
MC		 1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
63c3a66f
JP		 1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367
MC		 1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
63c3a66f 1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367
MC		 1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1481 }
1482 tw32(MAC_EXT_RGMII_MODE, val);
1483}
1484
158d7abd
MC		 1485static void tg3_mdio_start(struct tg3 *tp)
1486{
158d7abd
MC		 1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1489 udelay(80);
a9daf367 1490
63c3a66f 1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
4153577a 1492 tg3_asic_rev(tp) == ASIC_REV_5785)
9ea4818d
MC		 1493 tg3_mdio_config_5785(tp);
1494}
1495
1496static int tg3_mdio_init(struct tg3 *tp)
1497{
1498 int i;
1499 u32 reg;
1500 struct phy_device *phydev;
1501
63c3a66f 1502 if (tg3_flag(tp, 5717_PLUS)) {
9c7df915 1503 u32 is_serdes;
882e9793 1504
69f11c99 1505 tp->phy_addr = tp->pci_fn + 1;
882e9793 1506
4153577a 1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
d1ec96af
MC		 1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1509 else
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
882e9793
MC		 1512 if (is_serdes)
1513 tp->phy_addr += 7;
ee002b64
HM		 1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1515 int addr;
1516
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1518 if (addr < 0)
1519 return addr;
1520 tp->phy_addr = addr;
882e9793 1521 } else
3f0e3ad7 1522 tp->phy_addr = TG3_PHY_MII_ADDR;
882e9793 1523
158d7abd
MC		 1524 tg3_mdio_start(tp);
1525
63c3a66f 1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
158d7abd
MC		 1527 return 0;
1528
298cf9be
LB		 1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1531 return -ENOMEM;
158d7abd 1532
298cf9be
LB		 1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
158d7abd 1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
298cf9be
LB		 1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
ead2402c 1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
298cf9be 1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
158d7abd
MC		 1542
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
298cf9be 1544 tp->mdio_bus->irq[i] = PHY_POLL;
158d7abd
MC		 1545
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1550 */
1551 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1552 tg3_bmcr_reset(tp);
1553
298cf9be 1554 i = mdiobus_register(tp->mdio_bus);
a9daf367 1555 if (i) {
ab96b241 1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
9c61d6bc 1557 mdiobus_free(tp->mdio_bus);
a9daf367
MC		 1558 return i;
1559 }
158d7abd 1560
ead2402c 1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
a9daf367 1562
9c61d6bc 1563 if (!phydev || !phydev->drv) {
ab96b241 1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
9c61d6bc
MC		 1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1567 return -ENODEV;
1568 }
1569
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
6a443a0f 1571 case PHY_ID_BCM57780:
321d32a0 1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
c704dc23 1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
321d32a0 1574 break;
6a443a0f
MC		 1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
32e5a8d6 1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
c704dc23 1578 PHY_BRCM_RX_REFCLK_UNUSED |
52fae083 1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
c704dc23 1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
63c3a66f 1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
a9daf367 1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
63c3a66f 1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
a9daf367 1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
63c3a66f 1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
a9daf367 1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
fcb389df 1587 /* fallthru */
6a443a0f 1588 case PHY_ID_RTL8211C:
fcb389df 1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
a9daf367 1590 break;
6a443a0f
MC		 1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
a9daf367 1593 phydev->interface = PHY_INTERFACE_MODE_MII;
cdd4e09d 1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
f07e9af3 1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
a9daf367
MC		 1596 break;
1597 }
1598
63c3a66f 1599 tg3_flag_set(tp, MDIOBUS_INITED);
9c61d6bc 1600
4153577a 1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
9c61d6bc 1602 tg3_mdio_config_5785(tp);
a9daf367
MC		 1603
1604 return 0;
158d7abd
MC		 1605}
1606
1607static void tg3_mdio_fini(struct tg3 *tp)
1608{
63c3a66f
JP		 1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
298cf9be
LB		 1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
158d7abd
MC		 1613 }
1614}
1615
4ba526ce
MC		 1616/* tp->lock is held. */
1617static inline void tg3_generate_fw_event(struct tg3 *tp)
1618{
1619 u32 val;
1620
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1624
1625 tp->last_event_jiffies = jiffies;
1626}
1627
1628#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1629
95e2869a
MC		 1630/* tp->lock is held. */
1631static void tg3_wait_for_event_ack(struct tg3 *tp)
1632{
1633 int i;
4ba526ce
MC		 1634 unsigned int delay_cnt;
1635 long time_remain;
1636
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1640 (long)jiffies;
1641 if (time_remain < 0)
1642 return;
1643
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
95e2869a 1649
4ba526ce 1650 for (i = 0; i < delay_cnt; i++) {
95e2869a
MC		 1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1652 break;
6d446ec3
GS		 1653 if (pci_channel_offline(tp->pdev))
1654 break;
1655
4ba526ce 1656 udelay(8);
95e2869a
MC		 1657 }
1658}
1659
1660/* tp->lock is held. */
b28f389d 1661static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
95e2869a 1662{
b28f389d 1663 u32 reg, val;
95e2869a
MC		 1664
1665 val = 0;
1666 if (!tg3_readphy(tp, MII_BMCR, &reg))
1667 val = reg << 16;
1668 if (!tg3_readphy(tp, MII_BMSR, &reg))
1669 val |= (reg & 0xffff);
b28f389d 1670 *data++ = val;
95e2869a
MC		 1671
1672 val = 0;
1673 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1674 val = reg << 16;
1675 if (!tg3_readphy(tp, MII_LPA, &reg))
1676 val |= (reg & 0xffff);
b28f389d 1677 *data++ = val;
95e2869a
MC		 1678
1679 val = 0;
f07e9af3 1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
95e2869a
MC		 1681 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1682 val = reg << 16;
1683 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1684 val |= (reg & 0xffff);
1685 }
b28f389d 1686 *data++ = val;
95e2869a
MC		 1687
1688 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1689 val = reg << 16;
1690 else
1691 val = 0;
b28f389d
MC		 1692 *data++ = val;
1693}
1694
1695/* tp->lock is held. */
1696static void tg3_ump_link_report(struct tg3 *tp)
1697{
1698 u32 data[4];
1699
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1701 return;
1702
1703 tg3_phy_gather_ump_data(tp, data);
1704
1705 tg3_wait_for_event_ack(tp);
1706
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
95e2869a 1713
4ba526ce 1714 tg3_generate_fw_event(tp);
95e2869a
MC		 1715}
1716
8d5a89b3
MC		 1717/* tp->lock is held. */
1718static void tg3_stop_fw(struct tg3 *tp)
1719{
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1723
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1725
1726 tg3_generate_fw_event(tp);
1727
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1730 }
1731}
1732
fd6d3f0e
MC		 1733/* tp->lock is held. */
1734static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1735{
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1738
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1740 switch (kind) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1743 DRV_STATE_START);
1744 break;
1745
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1748 DRV_STATE_UNLOAD);
1749 break;
1750
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1753 DRV_STATE_SUSPEND);
1754 break;
1755
1756 default:
1757 break;
1758 }
1759 }
fd6d3f0e
MC		 1760}
1761
1762/* tp->lock is held. */
1763static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1764{
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1766 switch (kind) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1770 break;
1771
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1775 break;
1776
1777 default:
1778 break;
1779 }
1780 }
fd6d3f0e
MC		 1781}
1782
1783/* tp->lock is held. */
1784static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1785{
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1787 switch (kind) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1790 DRV_STATE_START);
1791 break;
1792
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1795 DRV_STATE_UNLOAD);
1796 break;
1797
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1800 DRV_STATE_SUSPEND);
1801 break;
1802
1803 default:
1804 break;
1805 }
1806 }
1807}
1808
1809static int tg3_poll_fw(struct tg3 *tp)
1810{
1811 int i;
1812 u32 val;
1813
df465abf
NS		 1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1815 return 0;
1816
7e6c63f0
HM		 1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1819 return 0;
1820 }
1821
4153577a 1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
fd6d3f0e
MC		 1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1826 return 0;
6d446ec3
GS		 1827 if (pci_channel_offline(tp->pdev))
1828 return -ENODEV;
1829
fd6d3f0e
MC		 1830 udelay(100);
1831 }
1832 return -ENODEV;
1833 }
1834
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1839 break;
6d446ec3
GS		 1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1844 }
1845
1846 break;
1847 }
1848
fd6d3f0e
MC		 1849 udelay(10);
1850 }
1851
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1856 */
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1859
1860 netdev_info(tp->dev, "No firmware running\n");
1861 }
1862
4153577a 1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
fd6d3f0e
MC		 1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1866 */
1867 mdelay(10);
1868 }
1869
1870 return 0;
1871}
1872
95e2869a
MC		 1873static void tg3_link_report(struct tg3 *tp)
1874{
1875 if (!netif_carrier_ok(tp->dev)) {
05dbe005 1876 netif_info(tp, link, tp->dev, "Link is down\n");
95e2869a
MC		 1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
05dbe005
JP		 1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1881 1000 :
1882 (tp->link_config.active_speed == SPEED_100 ?
1883 100 : 10)),
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1885 "full" : "half"));
1886
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1889 "on" : "off",
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1891 "on" : "off");
47007831
MC		 1892
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1896
95e2869a
MC		 1897 tg3_ump_link_report(tp);
1898 }
84421b99
NS		 1899
1900 tp->link_up = netif_carrier_ok(tp->dev);
95e2869a
MC		 1901}
1902
fdad8de4
NS		 1903static u32 tg3_decode_flowctrl_1000T(u32 adv)
1904{
1905 u32 flowctrl = 0;
1906
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1913
1914 return flowctrl;
1915}
1916
95e2869a
MC		 1917static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1918{
1919 u16 miireg;
1920
e18ce346 1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
95e2869a 1922 miireg = ADVERTISE_1000XPAUSE;
e18ce346 1923 else if (flow_ctrl & FLOW_CTRL_TX)
95e2869a 1924 miireg = ADVERTISE_1000XPSE_ASYM;
e18ce346 1925 else if (flow_ctrl & FLOW_CTRL_RX)
95e2869a
MC		 1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1927 else
1928 miireg = 0;
1929
1930 return miireg;
1931}
1932
fdad8de4
NS		 1933static u32 tg3_decode_flowctrl_1000X(u32 adv)
1934{
1935 u32 flowctrl = 0;
1936
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1943
1944 return flowctrl;
1945}
1946
95e2869a
MC		 1947static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1948{
1949 u8 cap = 0;
1950
f3791cdf
MC		 1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1955 cap = FLOW_CTRL_RX;
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
e18ce346 1957 cap = FLOW_CTRL_TX;
95e2869a
MC		 1958 }
1959
1960 return cap;
1961}
1962
f51f3562 1963static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
95e2869a 1964{
b02fd9e3 1965 u8 autoneg;
f51f3562 1966 u8 flowctrl = 0;
95e2869a
MC		 1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1969
63c3a66f 1970 if (tg3_flag(tp, USE_PHYLIB))
ead2402c 1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
b02fd9e3
MC		 1972 else
1973 autoneg = tp->link_config.autoneg;
1974
63c3a66f 1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
f07e9af3 1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
f51f3562 1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
95e2869a 1978 else
bc02ff95 1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
f51f3562
MC		 1980 } else
1981 flowctrl = tp->link_config.flowctrl;
95e2869a 1982
f51f3562 1983 tp->link_config.active_flowctrl = flowctrl;
95e2869a 1984
e18ce346 1985 if (flowctrl & FLOW_CTRL_RX)
95e2869a
MC		 1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1987 else
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1989
f51f3562 1990 if (old_rx_mode != tp->rx_mode)
95e2869a 1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
95e2869a 1992
e18ce346 1993 if (flowctrl & FLOW_CTRL_TX)
95e2869a
MC		 1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1995 else
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1997
f51f3562 1998 if (old_tx_mode != tp->tx_mode)
95e2869a 1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
95e2869a
MC		 2000}
2001
b02fd9e3
MC		 2002static void tg3_adjust_link(struct net_device *dev)
2003{
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
ead2402c 2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2008
24bb4fb6 2009 spin_lock_bh(&tp->lock);
b02fd9e3
MC		 2010
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2013
2014 oldflowctrl = tp->link_config.active_flowctrl;
2015
2016 if (phydev->link) {
2017 lcl_adv = 0;
2018 rmt_adv = 0;
2019
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
c3df0748 2022 else if (phydev->speed == SPEED_1000 ||
4153577a 2023 tg3_asic_rev(tp) != ASIC_REV_5785)
b02fd9e3 2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
c3df0748
MC		 2025 else
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
b02fd9e3
MC		 2027
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2030 else {
f88788f0 2031 lcl_adv = mii_advertise_flowctrl(
b02fd9e3
MC		 2032 tp->link_config.flowctrl);
2033
2034 if (phydev->pause)
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2038 }
2039
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2041 } else
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2043
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2047 udelay(40);
2048 }
2049
4153577a 2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
fcb389df
MC		 2051 if (phydev->speed == SPEED_10)
2052 tw32(MAC_MI_STAT,
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2055 else
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2057 }
2058
b02fd9e3
MC		 2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2064 else
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2069
34655ad6 2070 if (phydev->link != tp->old_link ||
b02fd9e3
MC		 2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
c6cdf436 2074 linkmesg = 1;
b02fd9e3 2075
34655ad6 2076 tp->old_link = phydev->link;
b02fd9e3
MC		 2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2079
24bb4fb6 2080 spin_unlock_bh(&tp->lock);
b02fd9e3
MC		 2081
2082 if (linkmesg)
2083 tg3_link_report(tp);
2084}
2085
2086static int tg3_phy_init(struct tg3 *tp)
2087{
2088 struct phy_device *phydev;
2089
f07e9af3 2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
b02fd9e3
MC		 2091 return 0;
2092
2093 /* Bring the PHY back to a known state. */
2094 tg3_bmcr_reset(tp);
2095
ead2402c 2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3
MC		 2097
2098 /* Attach the MAC to the PHY. */
f9a8f83b
FF		 2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
b02fd9e3 2101 if (IS_ERR(phydev)) {
ab96b241 2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
b02fd9e3
MC		 2103 return PTR_ERR(phydev);
2104 }
2105
b02fd9e3 2106 /* Mask with MAC supported features. */
9c61d6bc
MC		 2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
f07e9af3 2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
321d32a0
MC		 2111 phydev->supported &= (PHY_GBIT_FEATURES |
2112 SUPPORTED_Pause |
2113 SUPPORTED_Asym_Pause);
2114 break;
2115 }
2116 /* fallthru */
9c61d6bc
MC		 2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2119 SUPPORTED_Pause |
2120 SUPPORTED_Asym_Pause);
2121 break;
2122 default:
ead2402c 2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
9c61d6bc
MC		 2124 return -EINVAL;
2125 }
2126
f07e9af3 2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2128
2129 phydev->advertising = phydev->supported;
2130
b02fd9e3
MC		 2131 return 0;
2132}
2133
2134static void tg3_phy_start(struct tg3 *tp)
2135{
2136 struct phy_device *phydev;
2137
f07e9af3 2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2139 return;
2140
ead2402c 2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 2142
80096068
MC		 2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
c6700ce2
MC		 2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
b02fd9e3
MC		 2149 }
2150
2151 phy_start(phydev);
2152
2153 phy_start_aneg(phydev);
2154}
2155
2156static void tg3_phy_stop(struct tg3 *tp)
2157{
f07e9af3 2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3
MC		 2159 return;
2160
ead2402c 2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 2162}
2163
2164static void tg3_phy_fini(struct tg3 *tp)
2165{
f07e9af3 2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
ead2402c 2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
f07e9af3 2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
b02fd9e3
MC		 2169 }
2170}
2171
941ec90f
MC		 2172static int tg3_phy_set_extloopbk(struct tg3 *tp)
2173{
2174 int err;
2175 u32 val;
2176
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2178 return 0;
2179
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2185 0x4c20);
2186 goto done;
2187 }
2188
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2191 if (err)
2192 return err;
2193
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2197
2198done:
2199 return err;
2200}
2201
7f97a4bd
MC		 2202static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2203{
2204 u32 phytest;
2205
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2207 u32 phy;
2208
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2212 if (enable)
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2214 else
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2217 }
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2219 }
2220}
2221
6833c043
MC		 2222static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2223{
2224 u32 reg;
2225
63c3a66f
JP		 2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
6833c043
MC		 2229 return;
2230
f07e9af3 2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7f97a4bd
MC		 2232 tg3_phy_fet_toggle_apd(tp, enable);
2233 return;
2234 }
2235
3ab71071 2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
6833c043
MC		 2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
4153577a 2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
6833c043
MC		 2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2242
3ab71071 2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
6833c043
MC		 2244
2245
3ab71071 2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
6833c043
MC		 2247 if (enable)
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2249
3ab71071 2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
6833c043
MC		 2251}
2252
953c96e0 2253static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
9ef8ca99
MC		 2254{
2255 u32 phy;
2256
63c3a66f 2257 if (!tg3_flag(tp, 5705_PLUS) ||
f07e9af3 2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9ef8ca99
MC		 2259 return;
2260
f07e9af3 2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
9ef8ca99
MC		 2262 u32 ephy;
2263
535ef6e1
MC		 2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2266
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
9ef8ca99 2270 if (enable)
535ef6e1 2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
9ef8ca99 2272 else
535ef6e1
MC		 2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
9ef8ca99 2275 }
535ef6e1 2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
9ef8ca99
MC		 2277 }
2278 } else {
15ee95c3
MC		 2279 int ret;
2280
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2283 if (!ret) {
9ef8ca99
MC		 2284 if (enable)
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2286 else
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
b4bd2929
MC		 2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
9ef8ca99
MC		 2290 }
2291 }
2292}
2293
1da177e4
LT		 2294static void tg3_phy_set_wirespeed(struct tg3 *tp)
2295{
15ee95c3 2296 int ret;
1da177e4
LT		 2297 u32 val;
2298
f07e9af3 2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1da177e4
LT		 2300 return;
2301
15ee95c3
MC		 2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2303 if (!ret)
b4bd2929
MC		 2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1da177e4
LT		 2306}
2307
b2a5c19c
MC		 2308static void tg3_phy_apply_otp(struct tg3 *tp)
2309{
2310 u32 otp, phy;
2311
2312 if (!tp->phy_otp)
2313 return;
2314
2315 otp = tp->phy_otp;
2316
daf3ec68 2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
1d36ba45 2318 return;
b2a5c19c
MC		 2319
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2323
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2327
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2331
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2334
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2337
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2341
daf3ec68 2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
b2a5c19c
MC		 2343}
2344
400dfbaa
NS		 2345static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2346{
2347 u32 val;
2348 struct ethtool_eee *dest = &tp->eee;
2349
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2351 return;
2352
2353 if (eee)
2354 dest = eee;
2355
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2357 return;
2358
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2363 } else
2364 dest->eee_active = 0;
2365
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2368 return;
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2370
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2373 return;
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2376
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2380
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2383}
2384
953c96e0 2385static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
52b02d04
MC		 2386{
2387 u32 val;
2388
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2390 return;
2391
2392 tp->setlpicnt = 0;
2393
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
953c96e0 2395 current_link_up &&
a6b68dab
MC		 2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
52b02d04
MC		 2399 u32 eeectl;
2400
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2403 else
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2405
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2407
400dfbaa
NS		 2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
52b02d04
MC		 2410 tp->setlpicnt = 2;
2411 }
2412
2413 if (!tp->setlpicnt) {
953c96e0 2414 if (current_link_up &&
daf3ec68 2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94 2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
daf3ec68 2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
b715ce94
MC		 2418 }
2419
52b02d04
MC		 2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2422 }
2423}
2424
b0c5943f
MC		 2425static void tg3_phy_eee_enable(struct tg3 *tp)
2426{
2427 u32 val;
2428
2429 if (tp->link_config.active_speed == SPEED_1000 &&
4153577a
JP		 2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
55086ad9 2432 tg3_flag(tp, 57765_CLASS)) &&
daf3ec68 2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
b715ce94
MC		 2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
daf3ec68 2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
b0c5943f
MC		 2438 }
2439
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2442}
2443
1da177e4
LT		 2444static int tg3_wait_macro_done(struct tg3 *tp)
2445{
2446 int limit = 100;
2447
2448 while (limit--) {
2449 u32 tmp32;
2450
f08aa1a8 2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1da177e4
LT		 2452 if ((tmp32 & 0x1000) == 0)
2453 break;
2454 }
2455 }
d4675b52 2456 if (limit < 0)
1da177e4
LT		 2457 return -EBUSY;
2458
2459 return 0;
2460}
2461
2462static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2463{
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2469 };
2470 int chan;
2471
2472 for (chan = 0; chan < 4; chan++) {
2473 int i;
2474
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
f08aa1a8 2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2478
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2481 test_pat[chan][i]);
2482
f08aa1a8 2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2484 if (tg3_wait_macro_done(tp)) {
2485 *resetp = 1;
2486 return -EBUSY;
2487 }
2488
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
f08aa1a8 2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1da177e4
LT		 2492 if (tg3_wait_macro_done(tp)) {
2493 *resetp = 1;
2494 return -EBUSY;
2495 }
2496
f08aa1a8 2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1da177e4
LT		 2498 if (tg3_wait_macro_done(tp)) {
2499 *resetp = 1;
2500 return -EBUSY;
2501 }
2502
2503 for (i = 0; i < 6; i += 2) {
2504 u32 low, high;
2505
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2509 *resetp = 1;
2510 return -EBUSY;
2511 }
2512 low &= 0x7fff;
2513 high &= 0x000f;
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2519
2520 return -EBUSY;
2521 }
2522 }
2523 }
2524
2525 return 0;
2526}
2527
2528static int tg3_phy_reset_chanpat(struct tg3 *tp)
2529{
2530 int chan;
2531
2532 for (chan = 0; chan < 4; chan++) {
2533 int i;
2534
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
f08aa1a8 2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1da177e4
LT		 2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
f08aa1a8 2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1da177e4
LT		 2541 if (tg3_wait_macro_done(tp))
2542 return -EBUSY;
2543 }
2544
2545 return 0;
2546}
2547
2548static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2549{
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2552
2553 retries = 10;
2554 do_phy_reset = 1;
2555 do {
2556 if (do_phy_reset) {
2557 err = tg3_bmcr_reset(tp);
2558 if (err)
2559 return err;
2560 do_phy_reset = 0;
2561 }
2562
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2565 continue;
2566
2567 reg32 |= 0x3000;
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2569
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
221c5637 2572 BMCR_FULLDPLX | BMCR_SPEED1000);
1da177e4
LT		 2573
2574 /* Set to master mode. */
221c5637 2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
1da177e4
LT		 2576 continue;
2577
221c5637
MC		 2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
1da177e4 2580
daf3ec68 2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
1d36ba45
MC		 2582 if (err)
2583 return err;
1da177e4
LT		 2584
2585 /* Block the PHY control access. */
6ee7c0a0 2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
1da177e4
LT		 2587
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2589 if (!err)
2590 break;
2591 } while (--retries);
2592
2593 err = tg3_phy_reset_chanpat(tp);
2594 if (err)
2595 return err;
2596
6ee7c0a0 2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
1da177e4
LT		 2598
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
f08aa1a8 2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1da177e4 2601
daf3ec68 2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2603
221c5637 2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
1da177e4 2605
c6e27f2f
DC		 2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2607 if (err)
2608 return err;
1da177e4 2609
c6e27f2f
DC		 2610 reg32 &= ~0x3000;
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2612
2613 return 0;
1da177e4
LT		 2614}
2615
f4a46d1f
NNS		 2616static void tg3_carrier_off(struct tg3 *tp)
2617{
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2620}
2621
ce20f161
NS		 2622static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2623{
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2627}
2628
1da177e4
LT		 2629/* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2631 */
2632static int tg3_phy_reset(struct tg3 *tp)
2633{
f833c4c1 2634 u32 val, cpmuctrl;
1da177e4
LT		 2635 int err;
2636
4153577a 2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2640 udelay(40);
2641 }
f833c4c1
MC		 2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
1da177e4
LT		 2644 if (err != 0)
2645 return -EBUSY;
2646
f4a46d1f 2647 if (netif_running(tp->dev) && tp->link_up) {
84421b99 2648 netif_carrier_off(tp->dev);
c8e1e82b
MC		 2649 tg3_link_report(tp);
2650 }
2651
4153577a
JP		 2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 2655 err = tg3_phy_reset_5703_4_5(tp);
2656 if (err)
2657 return err;
2658 goto out;
2659 }
2660
b2a5c19c 2661 cpmuctrl = 0;
4153577a
JP		 2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2666 tw32(TG3_CPMU_CTRL,
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2668 }
2669
1da177e4
LT		 2670 err = tg3_bmcr_reset(tp);
2671 if (err)
2672 return err;
2673
b2a5c19c 2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
f833c4c1
MC		 2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
b2a5c19c
MC		 2677
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2679 }
2680
4153577a
JP		 2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2687 udelay(40);
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2689 }
2690 }
2691
63c3a66f 2692 if (tg3_flag(tp, 5717_PLUS) &&
f07e9af3 2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
ecf1410b
MC		 2694 return 0;
2695
b2a5c19c
MC		 2696 tg3_phy_apply_otp(tp);
2697
f07e9af3 2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
6833c043
MC		 2699 tg3_phy_toggle_apd(tp, true);
2700 else
2701 tg3_phy_toggle_apd(tp, false);
2702
1da177e4 2703out:
1d36ba45 2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
daf3ec68 2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
6ee7c0a0
MC		 2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
daf3ec68 2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
1da177e4 2709 }
1d36ba45 2710
f07e9af3 2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
f08aa1a8
MC		 2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1da177e4 2714 }
1d36ba45 2715
f07e9af3 2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
daf3ec68 2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
daf3ec68 2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2722 }
f07e9af3 2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
daf3ec68 2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
1d36ba45
MC		 2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2730 } else
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2732
daf3ec68 2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
1d36ba45 2734 }
c424cb24 2735 }
1d36ba45 2736
1da177e4
LT		 2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
79eb6904 2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4 2740 /* Cannot do read-modify-write on 5401 */
b4bd2929 2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
63c3a66f 2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
1da177e4 2743 /* Set bit 14 with read-modify-write to preserve other bits */
15ee95c3
MC		 2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2746 if (!err)
b4bd2929
MC		 2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
1da177e4
LT		 2749 }
2750
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2753 */
63c3a66f 2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
f833c4c1 2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
c6cdf436 2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
f833c4c1 2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1da177e4
LT		 2758 }
2759
4153577a 2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
715116a1 2761 /* adjust output voltage */
535ef6e1 2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
715116a1
MC		 2763 }
2764
4153577a 2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
c65a17f4
MC		 2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2767
953c96e0 2768 tg3_phy_toggle_automdix(tp, true);
1da177e4
LT		 2769 tg3_phy_set_wirespeed(tp);
2770 return 0;
2771}
2772
3a1e19d3
MC		 2773#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2782
2783#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2788
2789static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2790{
2791 u32 status, shift;
2792
4153577a
JP		 2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2796 else
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2798
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2802
4153577a
JP		 2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
3a1e19d3
MC		 2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2806 else
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2808
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2810}
2811
520b2756
MC		 2812static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2813{
2814 if (!tg3_flag(tp, IS_NIC))
2815 return 0;
2816
4153577a
JP		 2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
3a1e19d3
MC		 2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2821 return -EIO;
520b2756 2822
3a1e19d3
MC		 2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2824
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2829 } else {
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2832 }
6f5c8f83 2833
520b2756
MC		 2834 return 0;
2835}
2836
2837static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2838{
2839 u32 grc_local_ctrl;
2840
2841 if (!tg3_flag(tp, IS_NIC) ||
4153577a
JP		 2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
520b2756
MC		 2844 return;
2845
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2847
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2851
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2853 grc_local_ctrl,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2855
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2859}
2860
2861static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2862{
2863 if (!tg3_flag(tp, IS_NIC))
2864 return;
2865
4153577a
JP		 2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
520b2756
MC		 2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2883 tp->grc_local_ctrl;
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2886
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2890
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2894 } else {
2895 u32 no_gpio2;
2896 u32 grc_local_ctrl = 0;
2897
2898 /* Workaround to prevent overdrawing Amps. */
4153577a 2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
520b2756
MC		 2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2902 grc_local_ctrl,
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2904 }
2905
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2909
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2915 if (no_gpio2) {
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2918 }
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2922
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2924
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2928
2929 if (!no_gpio2) {
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2934 }
2935 }
3a1e19d3
MC		 2936}
2937
cd0d7228 2938static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
3a1e19d3
MC		 2939{
2940 u32 msg = 0;
2941
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2944 return;
2945
cd0d7228 2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
3a1e19d3
MC		 2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2948
2949 msg = tg3_set_function_status(tp, msg);
2950
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2952 goto done;
6f5c8f83 2953
3a1e19d3
MC		 2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2956 else
2957 tg3_pwrsrc_die_with_vmain(tp);
2958
2959done:
6f5c8f83 2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
520b2756
MC		 2961}
2962
cd0d7228 2963static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
1da177e4 2964{
683644b7 2965 bool need_vaux = false;
1da177e4 2966
334355aa 2967 /* The GPIOs do something completely different on 57765. */
55086ad9 2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
1da177e4
LT		 2969 return;
2970
4153577a
JP		 2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
cd0d7228
MC		 2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
3a1e19d3
MC		 2976 return;
2977 }
2978
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
8c2dc7e1
MC		 2980 struct net_device *dev_peer;
2981
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
683644b7 2983
bc1c7567 2984 /* remove_one() may have been run on the peer. */
683644b7
MC		 2985 if (dev_peer) {
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2987
63c3a66f 2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
683644b7
MC		 2989 return;
2990
cd0d7228 2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
63c3a66f 2992 tg3_flag(tp_peer, ENABLE_ASF))
683644b7
MC		 2993 need_vaux = true;
2994 }
1da177e4
LT		 2995 }
2996
cd0d7228
MC		 2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
683644b7
MC		 2999 need_vaux = true;
3000
520b2756
MC		 3001 if (need_vaux)
3002 tg3_pwrsrc_switch_to_vaux(tp);
3003 else
3004 tg3_pwrsrc_die_with_vmain(tp);
1da177e4
LT		 3005}
3006
e8f3f6ca
MC		 3007static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3008{
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3010 return 1;
79eb6904 3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
e8f3f6ca
MC		 3012 if (speed != SPEED_10)
3013 return 1;
3014 } else if (speed == SPEED_10)
3015 return 1;
3016
3017 return 0;
3018}
3019
44f3b503
NS		 3020static bool tg3_phy_power_bug(struct tg3 *tp)
3021{
3022 switch (tg3_asic_rev(tp)) {
3023 case ASIC_REV_5700:
3024 case ASIC_REV_5704:
3025 return true;
3026 case ASIC_REV_5780:
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3028 return true;
3029 return false;
3030 case ASIC_REV_5717:
3031 if (!tp->pci_fn)
3032 return true;
3033 return false;
3034 case ASIC_REV_5719:
3035 case ASIC_REV_5720:
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3037 !tp->pci_fn)
3038 return true;
3039 return false;
3040 }
3041
3042 return false;
3043}
3044
989038e2
NS		 3045static bool tg3_phy_led_bug(struct tg3 *tp)
3046{
3047 switch (tg3_asic_rev(tp)) {
3048 case ASIC_REV_5719:
300cf9b9 3049 case ASIC_REV_5720:
989038e2
NS		 3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3051 !tp->pci_fn)
3052 return true;
3053 return false;
3054 }
3055
3056 return false;
3057}
3058
0a459aac 3059static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
15c3b696 3060{
ce057f01
MC		 3061 u32 val;
3062
942d1af0
NS		 3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3064 return;
3065
f07e9af3 3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a 3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
5129724a
MC		 3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3070
3071 sg_dig_ctrl |=
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3075 }
3f7045c1 3076 return;
5129724a 3077 }
3f7045c1 3078
4153577a 3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
60189ddf
MC		 3080 tg3_bmcr_reset(tp);
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3083 udelay(40);
3084 return;
f07e9af3 3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
0e5f784c
MC		 3086 u32 phytest;
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3088 u32 phy;
3089
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3093
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3098 tg3_writephy(tp,
3099 MII_TG3_FET_SHDW_AUXMODE4,
3100 phy);
3101 }
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3103 }
3104 return;
0a459aac 3105 } else if (do_low_power) {
989038e2
NS		 3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
0a459aac 3109
b4bd2929
MC		 3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
715116a1 3114 }
3f7045c1 3115
15c3b696
MC		 3116 /* The PHY should not be powered down on some chips because
3117 * of bugs.
3118 */
44f3b503 3119 if (tg3_phy_power_bug(tp))
15c3b696 3120 return;
ce057f01 3121
4153577a
JP		 3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
ce057f01
MC		 3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3128 }
3129
15c3b696
MC		 3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3131}
3132
ffbcfed4
MC		 3133/* tp->lock is held. */
3134static int tg3_nvram_lock(struct tg3 *tp)
3135{
63c3a66f 3136 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3137 int i;
3138
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3143 break;
3144 udelay(20);
3145 }
3146 if (i == 8000) {
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3148 return -ENODEV;
3149 }
3150 }
3151 tp->nvram_lock_cnt++;
3152 }
3153 return 0;
3154}
3155
3156/* tp->lock is held. */
3157static void tg3_nvram_unlock(struct tg3 *tp)
3158{
63c3a66f 3159 if (tg3_flag(tp, NVRAM)) {
ffbcfed4
MC		 3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3164 }
3165}
3166
3167/* tp->lock is held. */
3168static void tg3_enable_nvram_access(struct tg3 *tp)
3169{
63c3a66f 3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3172
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3174 }
3175}
3176
3177/* tp->lock is held. */
3178static void tg3_disable_nvram_access(struct tg3 *tp)
3179{
63c3a66f 3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
ffbcfed4
MC		 3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3182
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3184 }
3185}
3186
3187static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3189{
3190 u32 tmp;
3191 int i;
3192
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3194 return -EINVAL;
3195
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3198 EEPROM_ADDR_READ);
3199 tw32(GRC_EEPROM_ADDR,
3200 tmp |
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3205
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3208
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3210 break;
3211 msleep(1);
3212 }
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3214 return -EBUSY;
3215
62cedd11
MC		 3216 tmp = tr32(GRC_EEPROM_DATA);
3217
3218 /*
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3221 */
3222 *val = swab32(tmp);
3223
ffbcfed4
MC		 3224 return 0;
3225}
3226
3227#define NVRAM_CMD_TIMEOUT 10000
3228
3229static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3230{
3231 int i;
3232
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3235 udelay(10);
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3237 udelay(10);
3238 break;
3239 }
3240 }
3241
3242 if (i == NVRAM_CMD_TIMEOUT)
3243 return -EBUSY;
3244
3245 return 0;
3246}
3247
3248static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3249{
63c3a66f
JP		 3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3255
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3259
3260 return addr;
3261}
3262
3263static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3264{
63c3a66f
JP		 3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
ffbcfed4
MC		 3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3270
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3274
3275 return addr;
3276}
3277
e4f34110
MC		 3278/* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3283 */
ffbcfed4
MC		 3284static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3285{
3286 int ret;
3287
63c3a66f 3288 if (!tg3_flag(tp, NVRAM))
ffbcfed4
MC		 3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3290
3291 offset = tg3_nvram_phys_addr(tp, offset);
3292
3293 if (offset > NVRAM_ADDR_MSK)
3294 return -EINVAL;
3295
3296 ret = tg3_nvram_lock(tp);
3297 if (ret)
3298 return ret;
3299
3300 tg3_enable_nvram_access(tp);
3301
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3305
3306 if (ret == 0)
e4f34110 3307 *val = tr32(NVRAM_RDDATA);
ffbcfed4
MC		 3308
3309 tg3_disable_nvram_access(tp);
3310
3311 tg3_nvram_unlock(tp);
3312
3313 return ret;
3314}
3315
a9dc529d
MC		 3316/* Ensures NVRAM data is in bytestream format. */
3317static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
ffbcfed4
MC		 3318{
3319 u32 v;
a9dc529d 3320 int res = tg3_nvram_read(tp, offset, &v);
ffbcfed4 3321 if (!res)
a9dc529d 3322 *val = cpu_to_be32(v);
ffbcfed4
MC		 3323 return res;
3324}
3325
dbe9b92a
MC		 3326static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3328{
3329 int i, j, rc = 0;
3330 u32 val;
3331
3332 for (i = 0; i < len; i += 4) {
3333 u32 addr;
3334 __be32 data;
3335
3336 addr = offset + i;
3337
3338 memcpy(&data, buf + i, 4);
3339
3340 /*
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3345 */
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3347
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3350
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3352 EEPROM_ADDR_READ);
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3356 EEPROM_ADDR_START |
3357 EEPROM_ADDR_WRITE);
3358
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3361
3362 if (val & EEPROM_ADDR_COMPLETE)
3363 break;
3364 msleep(1);
3365 }
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3367 rc = -EBUSY;
3368 break;
3369 }
3370 }
3371
3372 return rc;
3373}
3374
3375/* offset and length are dword aligned */
3376static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3377 u8 *buf)
3378{
3379 int ret = 0;
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3382 u32 nvram_cmd;
3383 u8 *tmp;
3384
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3386 if (tmp == NULL)
3387 return -ENOMEM;
3388
3389 while (len) {
3390 int j;
3391 u32 phy_addr, page_off, size;
3392
3393 phy_addr = offset & ~pagemask;
3394
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3398 if (ret)
3399 break;
3400 }
3401 if (ret)
3402 break;
3403
3404 page_off = offset & pagemask;
3405 size = pagesize;
3406 if (len < size)
3407 size = len;
3408
3409 len -= size;
3410
3411 memcpy(tmp + page_off, buf, size);
3412
3413 offset = offset + (pagesize - page_off);
3414
3415 tg3_enable_nvram_access(tp);
3416
3417 /*
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3420 */
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3422
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3424 break;
3425
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3428
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3431
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3433 break;
3434
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3437
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3439 break;
3440
3441 for (j = 0; j < pagesize; j += 4) {
3442 __be32 data;
3443
3444 data = *((__be32 *) (tmp + j));
3445
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3447
3448 tw32(NVRAM_ADDR, phy_addr + j);
3449
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3451 NVRAM_CMD_WR;
3452
3453 if (j == 0)
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3457
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3459 if (ret)
3460 break;
3461 }
3462 if (ret)
3463 break;
3464 }
3465
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3468
3469 kfree(tmp);
3470
3471 return ret;
3472}
3473
3474/* offset and length are dword aligned */
3475static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3476 u8 *buf)
3477{
3478 int i, ret = 0;
3479
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3482 __be32 data;
3483
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3486
3487 page_off = offset % tp->nvram_pagesize;
3488
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3490
dbe9b92a
MC		 3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3492
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3497
3498 if (i == (len - 4))
3499 nvram_cmd |= NVRAM_CMD_LAST;
3500
42278224
MC		 3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3505
4153577a 3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
dbe9b92a
MC		 3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3510 u32 cmd;
3511
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3514 if (ret)
3515 break;
3516 }
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3520 }
3521
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3523 if (ret)
3524 break;
3525 }
3526 return ret;
3527}
3528
3529/* offset and length are dword aligned */
3530static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3531{
3532 int ret;
3533
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3537 udelay(40);
3538 }
3539
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3542 } else {
3543 u32 grc_mode;
3544
3545 ret = tg3_nvram_lock(tp);
3546 if (ret)
3547 return ret;
3548
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3552
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3555
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3558 buf);
3559 } else {
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3561 buf);
3562 }
3563
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3566
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3569 }
3570
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3573 udelay(40);
3574 }
3575
3576 return ret;
3577}
3578
997b4f13
MC		 3579#define RX_CPU_SCRATCH_BASE 0x30000
3580#define RX_CPU_SCRATCH_SIZE 0x04000
3581#define TX_CPU_SCRATCH_BASE 0x34000
3582#define TX_CPU_SCRATCH_SIZE 0x04000
3583
3584/* tp->lock is held. */
837c45bb 3585static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
997b4f13
MC		 3586{
3587 int i;
837c45bb 3588 const int iters = 10000;
997b4f13 3589
837c45bb
NS		 3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3594 break;
6d446ec3
GS		 3595 if (pci_channel_offline(tp->pdev))
3596 return -EBUSY;
837c45bb
NS		 3597 }
3598
3599 return (i == iters) ? -EBUSY : 0;
3600}
3601
3602/* tp->lock is held. */
3603static int tg3_rxcpu_pause(struct tg3 *tp)
3604{
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3606
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3609 udelay(10);
3610
3611 return rc;
3612}
3613
3614/* tp->lock is held. */
3615static int tg3_txcpu_pause(struct tg3 *tp)
3616{
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3618}
3619
3620/* tp->lock is held. */
3621static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3622{
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3625}
3626
3627/* tp->lock is held. */
3628static void tg3_rxcpu_resume(struct tg3 *tp)
3629{
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3631}
3632
3633/* tp->lock is held. */
3634static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3635{
3636 int rc;
3637
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
997b4f13 3639
4153577a 3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
997b4f13
MC		 3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3642
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3644 return 0;
3645 }
837c45bb
NS		 3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
997b4f13 3648 } else {
7e6c63f0
HM		 3649 /*
3650 * There is only an Rx CPU for the 5750 derivative in the
3651 * BCM4785.
3652 */
3653 if (tg3_flag(tp, IS_SSB_CORE))
3654 return 0;
3655
837c45bb 3656 rc = tg3_txcpu_pause(tp);
997b4f13
MC		 3657 }
3658
837c45bb 3659 if (rc) {
997b4f13 3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
837c45bb 3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
997b4f13
MC		 3662 return -ENODEV;
3663 }
3664
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3668 return 0;
3669}
3670
31f11a95
NS		 3671static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3673{
3674 int fw_len;
3675
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3681 *
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3689 */
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3692 else
3693 fw_len = tp->fw->size;
3694
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3696}
3697
997b4f13
MC		 3698/* tp->lock is held. */
3699static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
77997ea3 3701 const struct tg3_firmware_hdr *fw_hdr)
997b4f13 3702{
c4dab506 3703 int err, i;
997b4f13 3704 void (*write_op)(struct tg3 *, u32, u32);
31f11a95 3705 int total_len = tp->fw->size;
997b4f13
MC		 3706
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3708 netdev_err(tp->dev,
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3710 __func__);
3711 return -EINVAL;
3712 }
3713
c4dab506 3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
997b4f13
MC		 3715 write_op = tg3_write_mem;
3716 else
3717 write_op = tg3_write_indirect_reg32;
3718
c4dab506
NS		 3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3722 */
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3725 if (!lock_err)
3726 tg3_nvram_unlock(tp);
3727 if (err)
3728 goto out;
997b4f13 3729
c4dab506
NS		 3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3735 } else {
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3738 */
3739 total_len -= TG3_FW_HDR_LEN;
3740 fw_hdr++;
3741 }
77997ea3 3742
31f11a95
NS		 3743 do {
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3748 (i * sizeof(u32)),
3749 be32_to_cpu(fw_data[i]));
3750
3751 total_len -= be32_to_cpu(fw_hdr->len);
3752
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
997b4f13
MC		 3757
3758 err = 0;
3759
3760out:
3761 return err;
3762}
3763
f4bffb28
NS		 3764/* tp->lock is held. */
3765static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3766{
3767 int i;
3768 const int iters = 5;
3769
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3772
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3775 break;
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3779 udelay(1000);
3780 }
3781
3782 return (i == iters) ? -EBUSY : 0;
3783}
3784
997b4f13
MC		 3785/* tp->lock is held. */
3786static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3787{
77997ea3 3788 const struct tg3_firmware_hdr *fw_hdr;
f4bffb28 3789 int err;
997b4f13 3790
77997ea3 3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3792
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3798
997b4f13
MC		 3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
77997ea3 3801 fw_hdr);
997b4f13
MC		 3802 if (err)
3803 return err;
3804
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
77997ea3 3807 fw_hdr);
997b4f13
MC		 3808 if (err)
3809 return err;
3810
3811 /* Now startup only the RX cpu. */
77997ea3
NS		 3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3814 if (err) {
997b4f13
MC		 3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
77997ea3
NS		 3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3819 return -ENODEV;
3820 }
837c45bb
NS		 3821
3822 tg3_rxcpu_resume(tp);
997b4f13
MC		 3823
3824 return 0;
3825}
3826
c4dab506
NS		 3827static int tg3_validate_rxcpu_state(struct tg3 *tp)
3828{
3829 const int iters = 1000;
3830 int i;
3831 u32 val;
3832
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3835 */
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3838 break;
3839
3840 udelay(10);
3841 }
3842
3843 if (i == iters) {
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3845 return -EBUSY;
3846 }
3847
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3849 if (val & 0xff) {
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3852 return -EEXIST;
3853 }
3854
3855 return 0;
3856}
3857
3858/* tp->lock is held. */
3859static void tg3_load_57766_firmware(struct tg3 *tp)
3860{
3861 struct tg3_firmware_hdr *fw_hdr;
3862
3863 if (!tg3_flag(tp, NO_NVRAM))
3864 return;
3865
3866 if (tg3_validate_rxcpu_state(tp))
3867 return;
3868
3869 if (!tp->fw)
3870 return;
3871
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3875 *
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3879 *
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3884 */
3885
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3888 return;
3889
3890 if (tg3_rxcpu_pause(tp))
3891 return;
3892
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3895
3896 tg3_rxcpu_resume(tp);
3897}
3898
997b4f13
MC		 3899/* tp->lock is held. */
3900static int tg3_load_tso_firmware(struct tg3 *tp)
3901{
77997ea3 3902 const struct tg3_firmware_hdr *fw_hdr;
997b4f13 3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
f4bffb28 3904 int err;
997b4f13 3905
1caf13eb 3906 if (!tg3_flag(tp, FW_TSO))
997b4f13
MC		 3907 return 0;
3908
77997ea3 3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
997b4f13
MC		 3910
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3916
997b4f13 3917 cpu_scratch_size = tp->fw_len;
997b4f13 3918
4153577a 3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
997b4f13
MC		 3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3922 } else {
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3926 }
3927
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
77997ea3 3930 fw_hdr);
997b4f13
MC		 3931 if (err)
3932 return err;
3933
3934 /* Now startup the cpu. */
77997ea3
NS		 3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
f4bffb28 3937 if (err) {
997b4f13
MC		 3938 netdev_err(tp->dev,
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
77997ea3
NS		 3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
997b4f13
MC		 3942 return -ENODEV;
3943 }
837c45bb
NS		 3944
3945 tg3_resume_cpu(tp, cpu_base);
997b4f13
MC		 3946 return 0;
3947}
3948
f022ae62
MC		 3949/* tp->lock is held. */
3950static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3951{
3952 u32 addr_high, addr_low;
3953
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3957
3958 if (index < 4) {
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 } else {
3962 index -= 4;
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3965 }
3966}
997b4f13 3967
3f007891 3968/* tp->lock is held. */
953c96e0 3969static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3f007891 3970{
f022ae62 3971 u32 addr_high;
3f007891
MC		 3972 int i;
3973
3f007891
MC		 3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3976 continue;
f022ae62 3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3978 }
3979
4153577a
JP		 3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
f022ae62
MC		 3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3f007891
MC		 3984 }
3985
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3994}
3995
c866b7ea 3996static void tg3_enable_register_access(struct tg3 *tp)
1da177e4 3997{
c866b7ea
RW		 3998 /*
3999 * Make sure register accesses (indirect or otherwise) will function
4000 * correctly.
1da177e4
LT		 4001 */
4002 pci_write_config_dword(tp->pdev,
c866b7ea
RW		 4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4004}
1da177e4 4005
c866b7ea
RW		 4006static int tg3_power_up(struct tg3 *tp)
4007{
bed9829f 4008 int err;
8c6bda1a 4009
bed9829f 4010 tg3_enable_register_access(tp);
1da177e4 4011
bed9829f
MC		 4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4013 if (!err) {
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4016 } else {
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4018 }
1da177e4 4019
bed9829f 4020 return err;
c866b7ea 4021}
1da177e4 4022
953c96e0 4023static int tg3_setup_phy(struct tg3 *, bool);
4b409522 4024
c866b7ea
RW		 4025static int tg3_power_down_prepare(struct tg3 *tp)
4026{
4027 u32 misc_host_ctrl;
4028 bool device_should_wake, do_low_power;
4029
4030 tg3_enable_register_access(tp);
5e7dfd0f
MC		 4031
4032 /* Restore the CLKREQ setting. */
0f49bfbd
JL		 4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 4036
1da177e4
LT		 4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4040
c866b7ea 4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
63c3a66f 4042 tg3_flag(tp, WOL_ENABLE);
05ac4cb7 4043
63c3a66f 4044 if (tg3_flag(tp, USE_PHYLIB)) {
0a459aac 4045 do_low_power = false;
f07e9af3 4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
80096068 4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
b02fd9e3 4048 struct phy_device *phydev;
0a459aac 4049 u32 phyid, advertising;
b02fd9e3 4050
ead2402c 4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
b02fd9e3 4052
80096068 4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
b02fd9e3 4054
c6700ce2
MC		 4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
b02fd9e3
MC		 4059
4060 advertising = ADVERTISED_TP |
4061 ADVERTISED_Pause |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4064
63c3a66f
JP		 4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
b02fd9e3
MC		 4067 advertising |=
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4071 else
4072 advertising |= ADVERTISED_10baseT_Full;
4073 }
4074
4075 phydev->advertising = advertising;
4076
4077 phy_start_aneg(phydev);
0a459aac
MC		 4078
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
6a443a0f
MC		 4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
0a459aac
MC		 4085 do_low_power = true;
4086 }
b02fd9e3 4087 }
dd477003 4088 } else {
2023276e 4089 do_low_power = true;
0a459aac 4090
c6700ce2 4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
80096068 4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
1da177e4 4093
2855b9fe 4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
953c96e0 4095 tg3_setup_phy(tp, false);
1da177e4
LT		 4096 }
4097
4153577a 4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 4099 u32 val;
4100
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
63c3a66f 4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
6921d201
MC		 4104 int i;
4105 u32 val;
4106
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4110 break;
4111 msleep(1);
4112 }
4113 }
63c3a66f 4114 if (tg3_flag(tp, WOL_CAP))
a85feb8c
GZ		 4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4117 WOL_DRV_WOL |
4118 WOL_SET_MAGIC_PKT);
6921d201 4119
05ac4cb7 4120 if (device_should_wake) {
1da177e4
LT		 4121 u32 mac_mode;
4122
f07e9af3 4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
b4bd2929
MC		 4124 if (do_low_power &&
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
dd477003
MC		 4131 udelay(40);
4132 }
1da177e4 4133
f07e9af3 4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3f7045c1 4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
942d1af0
NS		 4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4140 else
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4142 } else
3f7045c1 4143 mac_mode = MAC_MODE_PORT_MODE_MII;
1da177e4 4144
e8f3f6ca 4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153577a 4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
63c3a66f 4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
e8f3f6ca
MC		 4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4151 else
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4153 }
1da177e4
LT		 4154 } else {
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4156 }
4157
63c3a66f 4158 if (!tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4160
05ac4cb7 4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
63c3a66f
JP		 4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
05ac4cb7 4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
1da177e4 4165
63c3a66f 4166 if (tg3_flag(tp, ENABLE_APE))
d2394e6b
MC		 4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
3bda1258 4170
1da177e4
LT		 4171 tw32_f(MAC_MODE, mac_mode);
4172 udelay(100);
4173
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4175 udelay(10);
4176 }
4177
63c3a66f 4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4153577a
JP		 4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 4181 u32 base_val;
4182
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4186
b401e9e2
MC		 4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
63c3a66f
JP		 4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4153577a 4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4cf78e4f 4192 /* do nothing */
63c3a66f 4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
1da177e4
LT		 4194 u32 newbits1, newbits2;
4195
4153577a
JP		 4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4200 CLOCK_CTRL_ALTCLK);
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
63c3a66f 4202 } else if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4205 } else {
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4208 }
4209
b401e9e2
MC		 4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4211 40);
1da177e4 4212
b401e9e2
MC		 4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4214 40);
1da177e4 4215
63c3a66f 4216 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 4217 u32 newbits3;
4218
4153577a
JP		 4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4224 } else {
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4226 }
4227
b401e9e2
MC		 4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
1da177e4
LT		 4230 }
4231 }
4232
63c3a66f 4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
0a459aac 4234 tg3_power_down_phy(tp, do_low_power);
6921d201 4235
cd0d7228 4236 tg3_frob_aux_power(tp, true);
1da177e4
LT		 4237
4238 /* Workaround for unstable PLL clock */
7e6c63f0 4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4153577a
JP		 4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
1da177e4
LT		 4242 u32 val = tr32(0x7d00);
4243
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4245 tw32(0x7d00, val);
63c3a66f 4246 if (!tg3_flag(tp, ENABLE_ASF)) {
ec41c7df
MC		 4247 int err;
4248
4249 err = tg3_nvram_lock(tp);
1da177e4 4250 tg3_halt_cpu(tp, RX_CPU_BASE);
ec41c7df
MC		 4251 if (!err)
4252 tg3_nvram_unlock(tp);
6921d201 4253 }
1da177e4
LT		 4254 }
4255
bbadf503
MC		 4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4257
2e460fc0
NS		 4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4259
c866b7ea
RW		 4260 return 0;
4261}
12dac075 4262
c866b7ea
RW		 4263static void tg3_power_down(struct tg3 *tp)
4264{
63c3a66f 4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
c866b7ea 4266 pci_set_power_state(tp->pdev, PCI_D3hot);
1da177e4
LT		 4267}
4268
1da177e4
LT		 4269static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4270{
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4273 *speed = SPEED_10;
4274 *duplex = DUPLEX_HALF;
4275 break;
4276
4277 case MII_TG3_AUX_STAT_10FULL:
4278 *speed = SPEED_10;
4279 *duplex = DUPLEX_FULL;
4280 break;
4281
4282 case MII_TG3_AUX_STAT_100HALF:
4283 *speed = SPEED_100;
4284 *duplex = DUPLEX_HALF;
4285 break;
4286
4287 case MII_TG3_AUX_STAT_100FULL:
4288 *speed = SPEED_100;
4289 *duplex = DUPLEX_FULL;
4290 break;
4291
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4295 break;
4296
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4300 break;
4301
4302 default:
f07e9af3 4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
715116a1
MC		 4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4305 SPEED_10;
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4307 DUPLEX_HALF;
4308 break;
4309 }
e740522e
MC		 4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
1da177e4 4312 break;
855e1111 4313 }
1da177e4
LT		 4314}
4315
42b64a45 4316static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
1da177e4 4317{
42b64a45
MC		 4318 int err = 0;
4319 u32 val, new_adv;
1da177e4 4320
42b64a45 4321 new_adv = ADVERTISE_CSMA;
202ff1c2 4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
f88788f0 4323 new_adv |= mii_advertise_flowctrl(flowctrl);
1da177e4 4324
42b64a45
MC		 4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4326 if (err)
4327 goto done;
ba4d07a8 4328
4f272096
MC		 4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
ba4d07a8 4331
4153577a
JP		 4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4f272096 4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
ba4d07a8 4335
4f272096
MC		 4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4337 if (err)
4338 goto done;
4339 }
1da177e4 4340
42b64a45
MC		 4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4342 goto done;
52b02d04 4343
42b64a45
MC		 4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
52b02d04 4346
daf3ec68 4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
42b64a45
MC		 4348 if (!err) {
4349 u32 err2;
52b02d04 4350
b715ce94
MC		 4351 val = 0;
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
9e2ecbeb
NS		 4358
4359 if (!tp->eee.eee_enabled) {
4360 val = 0;
4361 tp->eee.advertised = 0;
4362 } else {
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4366 }
4367
b715ce94
MC		 4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4369 if (err)
4370 val = 0;
4371
4153577a 4372 switch (tg3_asic_rev(tp)) {
21a00ab2
MC		 4373 case ASIC_REV_5717:
4374 case ASIC_REV_57765:
55086ad9 4375 case ASIC_REV_57766:
21a00ab2 4376 case ASIC_REV_5719:
b715ce94
MC		 4377 /* If we advertised any eee advertisements above... */
4378 if (val)
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
21a00ab2 4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
be671947
MC		 4383 /* Fall through */
4384 case ASIC_REV_5720:
c65a17f4 4385 case ASIC_REV_5762:
be671947
MC		 4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
21a00ab2 4389 }
52b02d04 4390
daf3ec68 4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
42b64a45
MC		 4392 if (!err)
4393 err = err2;
4394 }
4395
4396done:
4397 return err;
4398}
4399
4400static void tg3_phy_copper_begin(struct tg3 *tp)
4401{
d13ba512
MC		 4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4404 u32 adv, fc;
4405
942d1af0
NS		 4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
d13ba512
MC		 4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
7c786065
NS		 4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4418 }
d13ba512
MC		 4419
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
42b64a45 4421 } else {
d13ba512
MC		 4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4426
4427 fc = tp->link_config.flowctrl;
52b02d04 4428 }
52b02d04 4429
d13ba512 4430 tg3_phy_autoneg_cfg(tp, adv, fc);
52b02d04 4431
942d1af0
NS		 4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4437 */
4438 return;
4439 }
4440
d13ba512
MC		 4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4443 } else {
4444 int i;
1da177e4
LT		 4445 u32 bmcr, orig_bmcr;
4446
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4449
7c6cdead
NS		 4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4453 * enabled.
4454 */
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4456 }
4457
1da177e4
LT		 4458 bmcr = 0;
4459 switch (tp->link_config.speed) {
4460 default:
4461 case SPEED_10:
4462 break;
4463
4464 case SPEED_100:
4465 bmcr |= BMCR_SPEED100;
4466 break;
4467
4468 case SPEED_1000:
221c5637 4469 bmcr |= BMCR_SPEED1000;
1da177e4 4470 break;
855e1111 4471 }
1da177e4
LT		 4472
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4475
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4480 u32 tmp;
4481
4482 udelay(10);
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4485 continue;
4486 if (!(tmp & BMSR_LSTATUS)) {
4487 udelay(40);
4488 break;
4489 }
4490 }
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4492 udelay(40);
4493 }
1da177e4
LT		 4494 }
4495}
4496
fdad8de4
NS		 4497static int tg3_phy_pull_config(struct tg3 *tp)
4498{
4499 int err;
4500 u32 val;
4501
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4503 if (err)
4504 goto done;
4505
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4510
4511 err = -EIO;
4512
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4514 case 0:
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4516 goto done;
4517
4518 tp->link_config.speed = SPEED_10;
4519 break;
4520 case BMCR_SPEED100:
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4522 goto done;
4523
4524 tp->link_config.speed = SPEED_100;
4525 break;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4529 break;
4530 }
4531 /* Fall through */
4532 default:
4533 goto done;
4534 }
4535
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4538 else
4539 tp->link_config.duplex = DUPLEX_HALF;
4540
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4542
4543 err = 0;
4544 goto done;
4545 }
4546
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4550
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4552 u32 adv;
4553
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4555 if (err)
4556 goto done;
4557
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4560
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4562 } else {
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4564 }
4565
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4567 u32 adv;
4568
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4571 if (err)
4572 goto done;
4573
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4575 } else {
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4577 if (err)
4578 goto done;
4579
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4582
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4585 }
4586
4587 tp->link_config.advertising |= adv;
4588 }
4589
4590done:
4591 return err;
4592}
4593
1da177e4
LT		 4594static int tg3_init_5401phy_dsp(struct tg3 *tp)
4595{
4596 int err;
4597
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
b4bd2929 4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
1da177e4 4601
6ee7c0a0
MC		 4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
1da177e4
LT		 4607
4608 udelay(40);
4609
4610 return err;
4611}
4612
ed1ff5c3
NS		 4613static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4614{
5b6c273a 4615 struct ethtool_eee eee;
ed1ff5c3
NS		 4616
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4618 return true;
4619
5b6c273a 4620 tg3_eee_pull_config(tp, &eee);
ed1ff5c3 4621
5b6c273a
NS		 4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4626 return false;
4627 } else {
4628 /* EEE is disabled but we're advertising */
4629 if (eee.advertised)
4630 return false;
4631 }
ed1ff5c3
NS		 4632
4633 return true;
4634}
4635
e2bf73e7 4636static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
1da177e4 4637{
e2bf73e7 4638 u32 advmsk, tgtadv, advertising;
3600d918 4639
e2bf73e7
MC		 4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
1da177e4 4642
e2bf73e7
MC		 4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
f88788f0 4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
e2bf73e7
MC		 4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4647 }
1da177e4 4648
e2bf73e7
MC		 4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4650 return false;
4651
4652 if ((*lcladv & advmsk) != tgtadv)
4653 return false;
b99d2a57 4654
f07e9af3 4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1da177e4
LT		 4656 u32 tg3_ctrl;
4657
e2bf73e7 4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3600d918 4659
221c5637 4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
e2bf73e7 4661 return false;
1da177e4 4662
3198e07f 4663 if (tgtadv &&
4153577a
JP		 4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
3198e07f
MC		 4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4669 } else {
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4671 }
4672
e2bf73e7
MC		 4673 if (tg3_ctrl != tgtadv)
4674 return false;
ef167e27
MC		 4675 }
4676
e2bf73e7 4677 return true;
ef167e27
MC		 4678}
4679
859edb26
MC		 4680static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4681{
4682 u32 lpeth = 0;
4683
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4685 u32 val;
4686
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4688 return false;
4689
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4691 }
4692
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4694 return false;
4695
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4698
4699 return true;
4700}
4701
953c96e0 4702static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
f4a46d1f
NNS		 4703{
4704 if (curr_link_up != tp->link_up) {
4705 if (curr_link_up) {
84421b99 4706 netif_carrier_on(tp->dev);
f4a46d1f 4707 } else {
84421b99 4708 netif_carrier_off(tp->dev);
f4a46d1f
NNS		 4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4711 }
4712
4713 tg3_link_report(tp);
4714 return true;
4715 }
4716
4717 return false;
4718}
4719
3310e248
MC		 4720static void tg3_clear_mac_status(struct tg3 *tp)
4721{
4722 tw32(MAC_EVENT, 0);
4723
4724 tw32_f(MAC_STATUS,
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4729 udelay(40);
4730}
4731
9e2ecbeb
NS		 4732static void tg3_setup_eee(struct tg3 *tp)
4733{
4734 u32 val;
4735
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4740
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4742
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4745
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4750
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4753
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4756
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4758
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4762
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4766}
4767
953c96e0 4768static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
1da177e4 4769{
953c96e0 4770 bool current_link_up;
f833c4c1 4771 u32 bmsr, val;
ef167e27 4772 u32 lcl_adv, rmt_adv;
1da177e4
LT		 4773 u16 current_speed;
4774 u8 current_duplex;
4775 int i, err;
4776
3310e248 4777 tg3_clear_mac_status(tp);
1da177e4 4778
8ef21428
MC		 4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4780 tw32_f(MAC_MI_MODE,
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4782 udelay(80);
4783 }
1da177e4 4784
b4bd2929 4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1da177e4
LT		 4786
4787 /* Some third-party PHYs need to be reset on link going
4788 * down.
4789 */
4153577a
JP		 4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
f4a46d1f 4793 tp->link_up) {
1da177e4
LT		 4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
953c96e0 4797 force_reset = true;
1da177e4
LT		 4798 }
4799 if (force_reset)
4800 tg3_phy_reset(tp);
4801
79eb6904 4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
63c3a66f 4805 !tg3_flag(tp, INIT_COMPLETE))
1da177e4
LT		 4806 bmsr = 0;
4807
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4810 if (err)
4811 return err;
4812
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4815 udelay(10);
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4818 udelay(40);
4819 break;
4820 }
4821 }
4822
79eb6904
MC		 4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
1da177e4
LT		 4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4828 if (!err)
4829 err = tg3_init_5401phy_dsp(tp);
4830 if (err)
4831 return err;
4832 }
4833 }
4153577a
JP		 4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
1da177e4
LT		 4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
f08aa1a8
MC		 4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1da177e4
LT		 4841 }
4842
4843 /* Clear pending interrupts... */
f833c4c1
MC		 4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
1da177e4 4846
f07e9af3 4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1da177e4 4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
f07e9af3 4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1da177e4
LT		 4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4851
4153577a
JP		 4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4857 else
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4859 }
4860
953c96e0 4861 current_link_up = false;
e740522e
MC		 4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
e348c5e7 4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
859edb26 4865 tp->link_config.rmt_adv = 0;
1da177e4 4866
f07e9af3 4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
15ee95c3
MC		 4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4870 &val);
4871 if (!err && !(val & (1 << 10))) {
b4bd2929
MC		 4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4874 val | (1 << 10));
1da177e4
LT		 4875 goto relink;
4876 }
4877 }
4878
4879 bmsr = 0;
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4884 break;
4885 udelay(40);
4886 }
4887
4888 if (bmsr & BMSR_LSTATUS) {
4889 u32 aux_stat, bmcr;
4890
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4893 udelay(10);
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4895 aux_stat)
4896 break;
4897 }
4898
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4900 &current_speed,
4901 &current_duplex);
4902
4903 bmcr = 0;
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4907 continue;
4908 if (bmcr && bmcr != 0x7fff)
4909 break;
4910 udelay(10);
4911 }
4912
ef167e27
MC		 4913 lcl_adv = 0;
4914 rmt_adv = 0;
1da177e4 4915
ef167e27
MC		 4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4918
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
ed1ff5c3
NS		 4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4921
ef167e27 4922 if ((bmcr & BMCR_ANENABLE) &&
ed1ff5c3 4923 eee_config_ok &&
e2bf73e7 4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
859edb26 4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
953c96e0 4926 current_link_up = true;
ed1ff5c3
NS		 4927
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4931 */
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
5b6c273a
NS		 4934 !force_reset) {
4935 tg3_setup_eee(tp);
ed1ff5c3 4936 tg3_phy_reset(tp);
5b6c273a 4937 }
1da177e4
LT		 4938 } else {
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
f0fcd7a9 4941 tp->link_config.duplex == current_duplex) {
953c96e0 4942 current_link_up = true;
1da177e4
LT		 4943 }
4944 }
4945
953c96e0 4946 if (current_link_up &&
e348c5e7
MC		 4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4948 u32 reg, bit;
4949
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4953 } else {
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4956 }
4957
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4960
ef167e27 4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
e348c5e7 4962 }
1da177e4
LT		 4963 }
4964
1da177e4 4965relink:
953c96e0 4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
1da177e4
LT		 4967 tg3_phy_copper_begin(tp);
4968
7e6c63f0 4969 if (tg3_flag(tp, ROBOSWITCH)) {
953c96e0 4970 current_link_up = true;
7e6c63f0
HM		 4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4976 }
4977
f833c4c1 4978 tg3_readphy(tp, MII_BMSR, &bmsr);
06c03c02
MB		 4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
953c96e0 4981 current_link_up = true;
1da177e4
LT		 4982 }
4983
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
953c96e0 4985 if (current_link_up) {
1da177e4
LT		 4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4989 else
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
f07e9af3 4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7f97a4bd
MC		 4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4993 else
1da177e4
LT		 4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4995
7e6c63f0
HM		 4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4998 */
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5002
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5011
5012 tw32(MAC_LED_CTRL, led_ctrl);
5013 udelay(40);
5014 }
5015
1da177e4
LT		 5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5019
4153577a 5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
953c96e0 5021 if (current_link_up &&
e8f3f6ca 5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1da177e4 5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
e8f3f6ca
MC		 5024 else
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1da177e4
LT		 5026 }
5027
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5030 */
79eb6904 5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4153577a 5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
1da177e4
LT		 5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5035 udelay(80);
5036 }
5037
5038 tw32_f(MAC_MODE, tp->mac_mode);
5039 udelay(40);
5040
52b02d04
MC		 5041 tg3_phy_eee_adjust(tp, current_link_up);
5042
63c3a66f 5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5046 } else {
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5048 }
5049 udelay(40);
5050
4153577a 5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
953c96e0 5052 current_link_up &&
1da177e4 5053 tp->link_config.active_speed == SPEED_1000 &&
63c3a66f 5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1da177e4
LT		 5055 udelay(120);
5056 tw32_f(MAC_STATUS,
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5059 udelay(40);
5060 tg3_write_mem(tp,
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5063 }
5064
5e7dfd0f 5065 /* Prevent send BD corruption. */
63c3a66f 5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5e7dfd0f
MC		 5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
0f49bfbd
JL		 5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f 5071 else
0f49bfbd
JL		 5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5e7dfd0f
MC		 5074 }
5075
f4a46d1f 5076 tg3_test_and_report_link_chg(tp, current_link_up);
1da177e4
LT		 5077
5078 return 0;
5079}
5080
5081struct tg3_fiber_aneginfo {
5082 int state;
5083#define ANEG_STATE_UNKNOWN 0
5084#define ANEG_STATE_AN_ENABLE 1
5085#define ANEG_STATE_RESTART_INIT 2
5086#define ANEG_STATE_RESTART 3
5087#define ANEG_STATE_DISABLE_LINK_OK 4
5088#define ANEG_STATE_ABILITY_DETECT_INIT 5
5089#define ANEG_STATE_ABILITY_DETECT 6
5090#define ANEG_STATE_ACK_DETECT_INIT 7
5091#define ANEG_STATE_ACK_DETECT 8
5092#define ANEG_STATE_COMPLETE_ACK_INIT 9
5093#define ANEG_STATE_COMPLETE_ACK 10
5094#define ANEG_STATE_IDLE_DETECT_INIT 11
5095#define ANEG_STATE_IDLE_DETECT 12
5096#define ANEG_STATE_LINK_OK 13
5097#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098#define ANEG_STATE_NEXT_PAGE_WAIT 15
5099
5100 u32 flags;
5101#define MR_AN_ENABLE 0x00000001
5102#define MR_RESTART_AN 0x00000002
5103#define MR_AN_COMPLETE 0x00000004
5104#define MR_PAGE_RX 0x00000008
5105#define MR_NP_LOADED 0x00000010
5106#define MR_TOGGLE_TX 0x00000020
5107#define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108#define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109#define MR_LP_ADV_SYM_PAUSE 0x00000100
5110#define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113#define MR_LP_ADV_NEXT_PAGE 0x00001000
5114#define MR_TOGGLE_RX 0x00002000
5115#define MR_NP_RX 0x00004000
5116
5117#define MR_LINK_OK 0x80000000
5118
5119 unsigned long link_time, cur_time;
5120
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5123
5124 char ability_match, idle_match, ack_match;
5125
5126 u32 txconfig, rxconfig;
5127#define ANEG_CFG_NP 0x00000080
5128#define ANEG_CFG_ACK 0x00000040
5129#define ANEG_CFG_RF2 0x00000020
5130#define ANEG_CFG_RF1 0x00000010
5131#define ANEG_CFG_PS2 0x00000001
5132#define ANEG_CFG_PS1 0x00008000
5133#define ANEG_CFG_HD 0x00004000
5134#define ANEG_CFG_FD 0x00002000
5135#define ANEG_CFG_INVAL 0x00001f06
5136
5137};
5138#define ANEG_OK 0
5139#define ANEG_DONE 1
5140#define ANEG_TIMER_ENAB 2
5141#define ANEG_FAILED -1
5142
5143#define ANEG_STATE_SETTLE_TIME 10000
5144
5145static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5147{
5be73b47 5148 u16 flowctrl;
1da177e4
LT		 5149 unsigned long delta;
5150 u32 rx_cfg_reg;
5151 int ret;
5152
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5154 ap->rxconfig = 0;
5155 ap->link_time = 0;
5156 ap->cur_time = 0;
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5160 ap->idle_match = 0;
5161 ap->ack_match = 0;
5162 }
5163 ap->cur_time++;
5164
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5167
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5172 } else {
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5176 }
5177 }
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5179 ap->ack_match = 1;
5180 else
5181 ap->ack_match = 0;
5182
5183 ap->idle_match = 0;
5184 } else {
5185 ap->idle_match = 1;
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5189 ap->ack_match = 0;
5190
5191 rx_cfg_reg = 0;
5192 }
5193
5194 ap->rxconfig = rx_cfg_reg;
5195 ret = ANEG_OK;
5196
33f401ae 5197 switch (ap->state) {
1da177e4
LT		 5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5201
5202 /* fallthru */
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5206 ap->link_time = 0;
5207 ap->cur_time = 0;
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5211 ap->idle_match = 0;
5212 ap->ack_match = 0;
5213
5214 ap->state = ANEG_STATE_RESTART_INIT;
5215 } else {
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5217 }
5218 break;
5219
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5223 ap->txconfig = 0;
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5227 udelay(40);
5228
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5231
5232 /* fallthru */
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
859a5887 5235 if (delta > ANEG_STATE_SETTLE_TIME)
1da177e4 5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
859a5887 5237 else
1da177e4 5238 ret = ANEG_TIMER_ENAB;
1da177e4
LT		 5239 break;
5240
5241 case ANEG_STATE_DISABLE_LINK_OK:
5242 ret = ANEG_DONE;
5243 break;
5244
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5be73b47
MC		 5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
1da177e4
LT		 5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5256 udelay(40);
5257
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5259 break;
5260
5261 case ANEG_STATE_ABILITY_DETECT:
859a5887 5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
1da177e4 5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
1da177e4
LT		 5264 break;
5265
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5271 udelay(40);
5272
5273 ap->state = ANEG_STATE_ACK_DETECT;
5274
5275 /* fallthru */
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5281 } else {
5282 ap->state = ANEG_STATE_AN_ENABLE;
5283 }
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5287 }
5288 break;
5289
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5292 ret = ANEG_FAILED;
5293 break;
5294 }
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5302 MR_TOGGLE_RX |
5303 MR_NP_RX);
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5318
5319 ap->link_time = ap->cur_time;
5320
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5327
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5330 break;
5331
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5336 break;
5337 }
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5342 } else {
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5346 } else {
5347 ret = ANEG_FAILED;
5348 }
5349 }
5350 }
5351 break;
5352
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5357 udelay(40);
5358
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5361 break;
5362
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5367 break;
5368 }
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5373 }
5374 break;
5375
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5378 ret = ANEG_DONE;
5379 break;
5380
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5383 break;
5384
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5387 break;
5388
5389 default:
5390 ret = ANEG_FAILED;
5391 break;
855e1111 5392 }
1da177e4
LT		 5393
5394 return ret;
5395}
5396
5be73b47 5397static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1da177e4
LT		 5398{
5399 int res = 0;
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5402 unsigned int tick;
5403 u32 tmp;
5404
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5406
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5409 udelay(40);
5410
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5412 udelay(40);
5413
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5418 tick = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5422 break;
5423
5424 udelay(1);
5425 }
5426
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5429 udelay(40);
5430
5be73b47
MC		 5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
1da177e4
LT		 5433
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5437 res = 1;
5438
5439 return res;
5440}
5441
5442static void tg3_init_bcm8002(struct tg3 *tp)
5443{
5444 u32 mac_status = tr32(MAC_STATUS);
5445 int i;
5446
5447 /* Reset when initting first time or we have a link. */
63c3a66f 5448 if (tg3_flag(tp, INIT_COMPLETE) &&
1da177e4
LT		 5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5450 return;
5451
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5454
5455 /* SW reset */
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5457
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5461 udelay(10);
5462
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5465
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5468
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5471
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5474 udelay(40);
5475 tg3_writephy(tp, 0x13, 0x0000);
5476
5477 tg3_writephy(tp, 0x11, 0x0a50);
5478 udelay(40);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5480
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5484 udelay(10);
5485
5486 /* Deselect the channel register so we can read the PHYID
5487 * later.
5488 */
5489 tg3_writephy(tp, 0x10, 0x8011);
5490}
5491
953c96e0 5492static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1da177e4 5493{
82cd3d11 5494 u16 flowctrl;
953c96e0 5495 bool current_link_up;
1da177e4
LT		 5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
1da177e4
LT		 5499
5500 serdes_cfg = 0;
5501 expected_sg_dig_ctrl = 0;
5502 workaround = 0;
5503 port_a = 1;
953c96e0 5504 current_link_up = false;
1da177e4 5505
4153577a
JP		 5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
1da177e4
LT		 5508 workaround = 1;
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5510 port_a = 0;
5511
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5515 }
5516
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5518
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
c98f6e3b 5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1da177e4
LT		 5521 if (workaround) {
5522 u32 val = serdes_cfg;
5523
5524 if (port_a)
5525 val |= 0xc010000;
5526 else
5527 val |= 0x4010000;
5528 tw32_f(MAC_SERDES_CFG, val);
5529 }
c98f6e3b
MC		 5530
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5532 }
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5535 current_link_up = true;
1da177e4
LT		 5536 }
5537 goto out;
5538 }
5539
5540 /* Want auto-negotiation. */
c98f6e3b 5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1da177e4 5542
82cd3d11
MC		 5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1da177e4
LT		 5548
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
f07e9af3 5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3d3ebe74
MC		 5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
953c96e0 5556 current_link_up = true;
3d3ebe74
MC		 5557 goto out;
5558 }
5559restart_autoneg:
1da177e4
LT		 5560 if (workaround)
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
c98f6e3b 5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1da177e4
LT		 5563 udelay(5);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5565
3d3ebe74 5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
3d3ebe74 5570 sg_dig_status = tr32(SG_DIG_STATUS);
1da177e4
LT		 5571 mac_status = tr32(MAC_STATUS);
5572
c98f6e3b 5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1da177e4 5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
82cd3d11
MC		 5575 u32 local_adv = 0, remote_adv = 0;
5576
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
1da177e4 5581
c98f6e3b 5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
82cd3d11 5583 remote_adv |= LPA_1000XPAUSE;
c98f6e3b 5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
82cd3d11 5585 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5586
859edb26
MC		 5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5589
1da177e4 5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
953c96e0 5591 current_link_up = true;
3d3ebe74 5592 tp->serdes_counter = 0;
f07e9af3 5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c98f6e3b 5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3d3ebe74
MC		 5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
1da177e4
LT		 5597 else {
5598 if (workaround) {
5599 u32 val = serdes_cfg;
5600
5601 if (port_a)
5602 val |= 0xc010000;
5603 else
5604 val |= 0x4010000;
5605
5606 tw32_f(MAC_SERDES_CFG, val);
5607 }
5608
c98f6e3b 5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1da177e4
LT		 5610 udelay(40);
5611
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
953c96e0 5619 current_link_up = true;
f07e9af3
MC		 5620 tp->phy_flags |=
5621 TG3_PHYFLG_PARALLEL_DETECT;
3d3ebe74
MC		 5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5624 } else
5625 goto restart_autoneg;
1da177e4
LT		 5626 }
5627 }
3d3ebe74
MC		 5628 } else {
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
f07e9af3 5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1da177e4
LT		 5631 }
5632
5633out:
5634 return current_link_up;
5635}
5636
953c96e0 5637static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1da177e4 5638{
953c96e0 5639 bool current_link_up = false;
1da177e4 5640
5cf64b8a 5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1da177e4 5642 goto out;
1da177e4
LT		 5643
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5be73b47 5645 u32 txflags, rxflags;
1da177e4 5646 int i;
6aa20a22 5647
5be73b47
MC		 5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
1da177e4 5650
5be73b47
MC		 5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5655
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
1da177e4 5660
859edb26
MC		 5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5663
1da177e4
LT		 5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5665
953c96e0 5666 current_link_up = true;
1da177e4
LT		 5667 }
5668 for (i = 0; i < 30; i++) {
5669 udelay(20);
5670 tw32_f(MAC_STATUS,
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5673 udelay(40);
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5677 break;
5678 }
5679
5680 mac_status = tr32(MAC_STATUS);
953c96e0 5681 if (!current_link_up &&
1da177e4
LT		 5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
953c96e0 5684 current_link_up = true;
1da177e4 5685 } else {
5be73b47
MC		 5686 tg3_setup_flow_control(tp, 0, 0);
5687
1da177e4 5688 /* Forcing 1000FD link up. */
953c96e0 5689 current_link_up = true;
1da177e4
LT		 5690
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5692 udelay(40);
e8f3f6ca
MC		 5693
5694 tw32_f(MAC_MODE, tp->mac_mode);
5695 udelay(40);
1da177e4
LT		 5696 }
5697
5698out:
5699 return current_link_up;
5700}
5701
953c96e0 5702static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
1da177e4
LT		 5703{
5704 u32 orig_pause_cfg;
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5707 u32 mac_status;
953c96e0 5708 bool current_link_up;
1da177e4
LT		 5709 int i;
5710
8d018621 5711 orig_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5714
63c3a66f 5715 if (!tg3_flag(tp, HW_AUTONEG) &&
f4a46d1f 5716 tp->link_up &&
63c3a66f 5717 tg3_flag(tp, INIT_COMPLETE)) {
1da177e4
LT		 5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5727 return 0;
5728 }
5729 }
5730
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5732
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5736 udelay(40);
5737
79eb6904 5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
1da177e4
LT		 5739 tg3_init_bcm8002(tp);
5740
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5743 udelay(40);
5744
953c96e0 5745 current_link_up = false;
859edb26 5746 tp->link_config.rmt_adv = 0;
1da177e4
LT		 5747 mac_status = tr32(MAC_STATUS);
5748
63c3a66f 5749 if (tg3_flag(tp, HW_AUTONEG))
1da177e4
LT		 5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5751 else
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5753
898a56f8 5754 tp->napi[0].hw_status->status =
1da177e4 5755 (SD_STATUS_UPDATED |
898a56f8 5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
1da177e4
LT		 5757
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5761 udelay(5);
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3d3ebe74
MC		 5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
1da177e4
LT		 5765 break;
5766 }
5767
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
953c96e0 5770 current_link_up = false;
3d3ebe74
MC		 5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
1da177e4
LT		 5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5775 udelay(1);
5776 tw32_f(MAC_MODE, tp->mac_mode);
5777 }
5778 }
5779
953c96e0 5780 if (current_link_up) {
1da177e4
LT		 5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5786 } else {
e740522e
MC		 5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5792 }
5793
f4a46d1f 5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
8d018621 5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
1da177e4
LT		 5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5800 }
5801
5802 return 0;
5803}
5804
953c96e0 5805static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
747e8f8b 5806{
953c96e0 5807 int err = 0;
747e8f8b 5808 u32 bmsr, bmcr;
85730a63
MC		 5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
953c96e0 5811 bool current_link_up = false;
85730a63
MC		 5812 u32 local_adv, remote_adv, sgsr;
5813
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5818
5819 if (force_reset)
5820 tg3_phy_reset(tp);
5821
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5823
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5826 } else {
953c96e0 5827 current_link_up = true;
85730a63
MC		 5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5834 } else {
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5837 }
5838
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5841 else
5842 current_duplex = DUPLEX_HALF;
5843 }
5844
5845 tw32_f(MAC_MODE, tp->mac_mode);
5846 udelay(40);
5847
5848 tg3_clear_mac_status(tp);
5849
5850 goto fiber_setup_done;
5851 }
747e8f8b
MC		 5852
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5855 udelay(40);
5856
3310e248 5857 tg3_clear_mac_status(tp);
747e8f8b
MC		 5858
5859 if (force_reset)
5860 tg3_phy_reset(tp);
5861
859edb26 5862 tp->link_config.rmt_adv = 0;
747e8f8b
MC		 5863
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5869 else
5870 bmsr &= ~BMSR_LSTATUS;
5871 }
747e8f8b
MC		 5872
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5874
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
f07e9af3 5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
28011cf1 5879 u32 adv, newadv;
747e8f8b
MC		 5880
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
28011cf1
MC		 5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5885 ADVERTISE_SLCT);
747e8f8b 5886
28011cf1 5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
37f07023 5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
747e8f8b 5889
28011cf1
MC		 5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
747e8f8b
MC		 5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5894
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3d3ebe74 5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
f07e9af3 5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5898
5899 return err;
5900 }
5901 } else {
5902 u32 new_bmcr;
5903
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5906
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5909
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5913 */
5914 new_bmcr |= BMCR_SPEED1000;
5915
5916 /* Force a linkdown */
f4a46d1f 5917 if (tp->link_up) {
747e8f8b
MC		 5918 u32 adv;
5919
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5923 ADVERTISE_SLCT);
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5926 BMCR_ANRESTART |
5927 BMCR_ANENABLE);
5928 udelay(10);
f4a46d1f 5929 tg3_carrier_off(tp);
747e8f8b
MC		 5930 }
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5932 bmcr = new_bmcr;
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4153577a 5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5938 else
5939 bmsr &= ~BMSR_LSTATUS;
5940 }
f07e9af3 5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 5942 }
5943 }
5944
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
953c96e0 5947 current_link_up = true;
747e8f8b
MC		 5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5950 else
5951 current_duplex = DUPLEX_HALF;
5952
ef167e27
MC		 5953 local_adv = 0;
5954 remote_adv = 0;
5955
747e8f8b 5956 if (bmcr & BMCR_ANENABLE) {
ef167e27 5957 u32 common;
747e8f8b
MC		 5958
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5966 else
5967 current_duplex = DUPLEX_HALF;
859edb26
MC		 5968
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
63c3a66f 5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
57d8b880 5972 /* Link is up via parallel detect */
859a5887 5973 } else {
953c96e0 5974 current_link_up = false;
859a5887 5975 }
747e8f8b
MC		 5976 }
5977 }
5978
85730a63 5979fiber_setup_done:
953c96e0 5980 if (current_link_up && current_duplex == DUPLEX_FULL)
ef167e27
MC		 5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5982
747e8f8b
MC		 5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5986
5987 tw32_f(MAC_MODE, tp->mac_mode);
5988 udelay(40);
5989
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5991
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5994
f4a46d1f 5995 tg3_test_and_report_link_chg(tp, current_link_up);
747e8f8b
MC		 5996 return err;
5997}
5998
5999static void tg3_serdes_parallel_detect(struct tg3 *tp)
6000{
3d3ebe74 6001 if (tp->serdes_counter) {
747e8f8b 6002 /* Give autoneg time to complete. */
3d3ebe74 6003 tp->serdes_counter--;
747e8f8b
MC		 6004 return;
6005 }
c6cdf436 6006
f4a46d1f 6007 if (!tp->link_up &&
747e8f8b
MC		 6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6009 u32 bmcr;
6010
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6013 u32 phy1, phy2;
6014
6015 /* Select shadow register 0x1f */
f08aa1a8
MC		 6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
747e8f8b
MC		 6018
6019 /* Select expansion interrupt status register */
f08aa1a8
MC		 6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6024
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6028 * detection.
6029 */
6030
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
f07e9af3 6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6035 }
6036 }
f4a46d1f 6037 } else if (tp->link_up &&
859a5887 6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
f07e9af3 6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
747e8f8b
MC		 6040 u32 phy2;
6041
6042 /* Select expansion interrupt status register */
f08aa1a8
MC		 6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
747e8f8b
MC		 6046 if (phy2 & 0x20) {
6047 u32 bmcr;
6048
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6052
f07e9af3 6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
747e8f8b
MC		 6054
6055 }
6056 }
6057}
6058
953c96e0 6059static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
1da177e4 6060{
f2096f94 6061 u32 val;
1da177e4
LT		 6062 int err;
6063
f07e9af3 6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4 6065 err = tg3_setup_fiber_phy(tp, force_reset);
f07e9af3 6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
747e8f8b 6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
859a5887 6068 else
1da177e4 6069 err = tg3_setup_copper_phy(tp, force_reset);
1da177e4 6070
4153577a 6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
f2096f94 6072 u32 scale;
aa6c91fe
MC		 6073
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6076 scale = 65;
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6078 scale = 6;
6079 else
6080 scale = 12;
6081
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6085 }
6086
f2096f94
MC		 6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
4153577a
JP		 6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6094
1da177e4
LT		 6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
f2096f94
MC		 6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6099 else
f2096f94
MC		 6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1da177e4 6102
63c3a66f 6103 if (!tg3_flag(tp, 5705_PLUS)) {
f4a46d1f 6104 if (tp->link_up) {
1da177e4 6105 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 6106 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 6107 } else {
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6109 }
6110 }
6111
63c3a66f 6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
f2096f94 6113 val = tr32(PCIE_PWR_MGMT_THRESH);
f4a46d1f 6114 if (!tp->link_up)
8ed5d97e
MC		 6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6116 tp->pwrmgmt_thresh;
6117 else
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6120 }
6121
1da177e4
LT		 6122 return err;
6123}
6124
7d41e49a
MC		 6125/* tp->lock must be held */
6126static u64 tg3_refclk_read(struct tg3 *tp)
6127{
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6130}
6131
be947307
MC		 6132/* tp->lock must be held */
6133static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6134{
92e6457d
NS		 6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6136
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
be947307
MC		 6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
92e6457d 6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
be947307
MC		 6141}
6142
7d41e49a
MC		 6143static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144static inline void tg3_full_unlock(struct tg3 *tp);
6145static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6146{
6147 struct tg3 *tp = netdev_priv(dev);
6148
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
f233a976
FL		 6151 SOF_TIMESTAMPING_SOFTWARE;
6152
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
32e19272 6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
f233a976
FL		 6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6157 }
7d41e49a
MC		 6158
6159 if (tp->ptp_clock)
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6161 else
6162 info->phc_index = -1;
6163
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6165
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6170 return 0;
6171}
6172
6173static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6174{
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6177 u32 correction = 0;
6178
6179 if (ppb < 0) {
6180 neg_adj = true;
6181 ppb = -ppb;
6182 }
6183
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6188 *
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6191 */
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6194
6195 tg3_full_lock(tp, 0);
6196
6197 if (correction)
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6201 else
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6203
6204 tg3_full_unlock(tp);
6205
6206 return 0;
6207}
6208
6209static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6210{
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6212
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6216
6217 return 0;
6218}
6219
6220static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6221{
6222 u64 ns;
6223 u32 remainder;
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6230
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6233
6234 return 0;
6235}
6236
6237static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6239{
6240 u64 ns;
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6242
6243 ns = timespec_to_ns(ts);
6244
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6247 tp->ptp_adjust = 0;
6248 tg3_full_unlock(tp);
6249
6250 return 0;
6251}
6252
6253static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6255{
92e6457d
NS		 6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6257 u32 clock_ctl;
6258 int rval = 0;
6259
6260 switch (rq->type) {
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6263 return -EINVAL;
6264
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6268
6269 if (on) {
6270 u64 nsec;
6271
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6274
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6278 rval = -EINVAL;
6279 goto err_out;
6280 }
6281
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6285 rval = -EINVAL;
6286 goto err_out;
6287 }
6288
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6293
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6296 } else {
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6299 }
6300
6301err_out:
6302 tg3_full_unlock(tp);
6303 return rval;
6304
6305 default:
6306 break;
6307 }
6308
7d41e49a
MC		 6309 return -EOPNOTSUPP;
6310}
6311
6312static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6316 .n_alarm = 0,
6317 .n_ext_ts = 0,
92e6457d 6318 .n_per_out = 1,
4986b4f0 6319 .n_pins = 0,
7d41e49a
MC		 6320 .pps = 0,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6326};
6327
fb4ce8ad
MC		 6328static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6330{
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6333 tp->ptp_adjust);
6334}
6335
be947307
MC		 6336/* tp->lock must be held */
6337static void tg3_ptp_init(struct tg3 *tp)
6338{
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6340 return;
6341
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6344 tp->ptp_adjust = 0;
7d41e49a 6345 tp->ptp_info = tg3_ptp_caps;
be947307
MC		 6346}
6347
6348/* tp->lock must be held */
6349static void tg3_ptp_resume(struct tg3 *tp)
6350{
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6352 return;
6353
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6355 tp->ptp_adjust = 0;
6356}
6357
6358static void tg3_ptp_fini(struct tg3 *tp)
6359{
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6361 return;
6362
7d41e49a 6363 ptp_clock_unregister(tp->ptp_clock);
be947307
MC		 6364 tp->ptp_clock = NULL;
6365 tp->ptp_adjust = 0;
6366}
6367
66cfd1bd
MC		 6368static inline int tg3_irq_sync(struct tg3 *tp)
6369{
6370 return tp->irq_sync;
6371}
6372
97bd8e49
MC		 6373static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6374{
6375 int i;
6376
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6380}
6381
6382static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6383{
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6403
63c3a66f 6404 if (tg3_flag(tp, SUPPORT_MSIX))
97bd8e49
MC		 6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6406
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6415
63c3a66f 6416 if (!tg3_flag(tp, 5705_PLUS)) {
97bd8e49
MC		 6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6420 }
6421
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6427
63c3a66f 6428 if (tg3_flag(tp, NVRAM))
97bd8e49
MC		 6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6430}
6431
6432static void tg3_dump_state(struct tg3 *tp)
6433{
6434 int i;
6435 u32 *regs;
6436
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
b2adaca9 6438 if (!regs)
97bd8e49 6439 return;
97bd8e49 6440
63c3a66f 6441 if (tg3_flag(tp, PCI_EXPRESS)) {
97bd8e49
MC		 6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6445 } else
6446 tg3_dump_legacy_regs(tp, regs);
6447
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6451 continue;
6452
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6454 i * 4,
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6456 }
6457
6458 kfree(regs);
6459
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6462
6463 /* SW status block */
6464 netdev_err(tp->dev,
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6466 i,
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6474
6475 netdev_err(tp->dev,
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6477 i,
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6480 tnapi->rx_rcb_ptr,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6485 }
6486}
6487
df3e6548
MC		 6488/* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6492 * in the workqueue.
6493 */
6494static void tg3_tx_recover(struct tg3 *tp)
6495{
63c3a66f 6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
df3e6548
MC		 6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6498
5129c3a3
MC		 6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
df3e6548 6504
63c3a66f 6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
df3e6548
MC		 6506}
6507
f3f3f27e 6508static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
1b2a7205 6509{
f65aac16
MC		 6510 /* Tell compiler to fetch tx indices from memory. */
6511 barrier();
f3f3f27e
MC		 6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
1b2a7205
MC		 6514}
6515
1da177e4
LT		 6516/* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6519 */
17375d25 6520static void tg3_tx(struct tg3_napi *tnapi)
1da177e4 6521{
17375d25 6522 struct tg3 *tp = tnapi->tp;
898a56f8 6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
f3f3f27e 6524 u32 sw_idx = tnapi->tx_cons;
fe5f5787
MC		 6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
298376d3 6527 unsigned int pkts_compl = 0, bytes_compl = 0;
fe5f5787 6528
63c3a66f 6529 if (tg3_flag(tp, ENABLE_TSS))
fe5f5787
MC		 6530 index--;
6531
6532 txq = netdev_get_tx_queue(tp->dev, index);
1da177e4
LT		 6533
6534 while (sw_idx != hw_idx) {
df8944cf 6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
1da177e4 6536 struct sk_buff *skb = ri->skb;
df3e6548
MC		 6537 int i, tx_bug = 0;
6538
6539 if (unlikely(skb == NULL)) {
6540 tg3_tx_recover(tp);
6541 return;
6542 }
1da177e4 6543
fb4ce8ad
MC		 6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6548
6549 tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
6550
6551 skb_tstamp_tx(skb, &timestamp);
6552 }
6553
f4188d8a 6554 pci_unmap_single(tp->pdev,
4e5e4f0d 6555 dma_unmap_addr(ri, mapping),
f4188d8a
AD		 6556 skb_headlen(skb),
6557 PCI_DMA_TODEVICE);
1da177e4
LT		 6558
6559 ri->skb = NULL;
6560
e01ee14d
MC		 6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6565 }
6566
1da177e4
LT		 6567 sw_idx = NEXT_TX(sw_idx);
6568
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
f3f3f27e 6570 ri = &tnapi->tx_buffers[sw_idx];
df3e6548
MC		 6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6572 tx_bug = 1;
f4188d8a
AD		 6573
6574 pci_unmap_page(tp->pdev,
4e5e4f0d 6575 dma_unmap_addr(ri, mapping),
9e903e08 6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
f4188d8a 6577 PCI_DMA_TODEVICE);
e01ee14d
MC		 6578
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6583 }
6584
1da177e4
LT		 6585 sw_idx = NEXT_TX(sw_idx);
6586 }
6587
298376d3
TH		 6588 pkts_compl++;
6589 bytes_compl += skb->len;
6590
497a27b9 6591 dev_kfree_skb_any(skb);
df3e6548
MC		 6592
6593 if (unlikely(tx_bug)) {
6594 tg3_tx_recover(tp);
6595 return;
6596 }
1da177e4
LT		 6597 }
6598
5cb917bc 6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
298376d3 6600
f3f3f27e 6601 tnapi->tx_cons = sw_idx;
1da177e4 6602
1b2a7205
MC		 6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6607 */
6608 smp_mb();
6609
fe5f5787 6610 if (unlikely(netif_tx_queue_stopped(txq) &&
f3f3f27e 6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
fe5f5787
MC		 6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
f3f3f27e 6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
fe5f5787
MC		 6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
51b91468 6617 }
1da177e4
LT		 6618}
6619
8d4057a9
ED		 6620static void tg3_frag_free(bool is_frag, void *data)
6621{
6622 if (is_frag)
6623 put_page(virt_to_head_page(data));
6624 else
6625 kfree(data);
6626}
6627
9205fd9c 6628static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
2b2cdb65 6629{
8d4057a9
ED		 6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6632
9205fd9c 6633 if (!ri->data)
2b2cdb65
MC		 6634 return;
6635
4e5e4f0d 6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
2b2cdb65 6637 map_sz, PCI_DMA_FROMDEVICE);
a1e8b307 6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
9205fd9c 6639 ri->data = NULL;
2b2cdb65
MC		 6640}
6641
8d4057a9 6642
1da177e4
LT		 6643/* Returns size of skb allocated or < 0 on error.
6644 *
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6647 *
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6653 */
9205fd9c 6654static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
8d4057a9
ED		 6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
1da177e4
LT		 6657{
6658 struct tg3_rx_buffer_desc *desc;
f94e290e 6659 struct ring_info *map;
9205fd9c 6660 u8 *data;
1da177e4 6661 dma_addr_t mapping;
9205fd9c 6662 int skb_size, data_size, dest_idx;
1da177e4 6663
1da177e4
LT		 6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
2c49a44d 6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
21f581a5
MC		 6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
9205fd9c 6669 data_size = tp->rx_pkt_map_sz;
1da177e4
LT		 6670 break;
6671
6672 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
79ed5ac7 6674 desc = &tpr->rx_jmb[dest_idx].std;
21f581a5 6675 map = &tpr->rx_jmb_buffers[dest_idx];
9205fd9c 6676 data_size = TG3_RX_JMB_MAP_SZ;
1da177e4
LT		 6677 break;
6678
6679 default:
6680 return -EINVAL;
855e1111 6681 }
1da177e4
LT		 6682
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6685 *
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6688 */
9205fd9c
ED		 6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
a1e8b307
ED		 6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
8d4057a9
ED		 6694 } else {
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6696 *frag_size = 0;
6697 }
9205fd9c 6698 if (!data)
1da177e4
LT		 6699 return -ENOMEM;
6700
9205fd9c
ED		 6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6703 data_size,
1da177e4 6704 PCI_DMA_FROMDEVICE);
8d4057a9 6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
a1e8b307 6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
a21771dd
MC		 6707 return -EIO;
6708 }
1da177e4 6709
9205fd9c 6710 map->data = data;
4e5e4f0d 6711 dma_unmap_addr_set(map, mapping, mapping);
1da177e4 6712
1da177e4
LT		 6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6715
9205fd9c 6716 return data_size;
1da177e4
LT		 6717}
6718
6719/* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
9205fd9c 6721 * tg3_alloc_rx_data for full details.
1da177e4 6722 */
a3896167
MC		 6723static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
1da177e4 6727{
17375d25 6728 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
8fea32b9 6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
c6cdf436 6732 int dest_idx;
1da177e4
LT		 6733
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
2c49a44d 6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
a3896167
MC		 6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
1da177e4
LT		 6741 break;
6742
6743 case RXD_OPAQUE_RING_JUMBO:
2c49a44d 6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
a3896167
MC		 6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
1da177e4
LT		 6749 break;
6750
6751 default:
6752 return;
855e1111 6753 }
1da177e4 6754
9205fd9c 6755 dest_map->data = src_map->data;
4e5e4f0d
FT		 6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
1da177e4
LT		 6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
e92967bf
MC		 6760
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6763 */
6764 smp_wmb();
6765
9205fd9c 6766 src_map->data = NULL;
1da177e4
LT		 6767}
6768
1da177e4
LT		 6769/* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6772 *
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6778 *
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6785 *
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6792 */
17375d25 6793static int tg3_rx(struct tg3_napi *tnapi, int budget)
1da177e4 6794{
17375d25 6795 struct tg3 *tp = tnapi->tp;
f92905de 6796 u32 work_mask, rx_std_posted = 0;
4361935a 6797 u32 std_prod_idx, jmb_prod_idx;
72334482 6798 u32 sw_idx = tnapi->rx_rcb_ptr;
483ba50b 6799 u16 hw_idx;
1da177e4 6800 int received;
8fea32b9 6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
1da177e4 6802
8d9d7cfc 6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
1da177e4
LT		 6804 /*
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6807 */
6808 rmb();
1da177e4
LT		 6809 work_mask = 0;
6810 received = 0;
4361935a
MC		 6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
1da177e4 6813 while (sw_idx != hw_idx && budget > 0) {
afc081f8 6814 struct ring_info *ri;
72334482 6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
1da177e4
LT		 6816 unsigned int len;
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
9205fd9c 6820 u8 *data;
fb4ce8ad 6821 u64 tstamp = 0;
1da177e4
LT		 6822
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
8fea32b9 6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4e5e4f0d 6827 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6828 data = ri->data;
4361935a 6829 post_ptr = &std_prod_idx;
f92905de 6830 rx_std_posted++;
1da177e4 6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
8fea32b9 6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4e5e4f0d 6833 dma_addr = dma_unmap_addr(ri, mapping);
9205fd9c 6834 data = ri->data;
4361935a 6835 post_ptr = &jmb_prod_idx;
21f581a5 6836 } else
1da177e4 6837 goto next_pkt_nopost;
1da177e4
LT		 6838
6839 work_mask |= opaque_key;
6840
d7b95315 6841 if (desc->err_vlan & RXD_ERR_MASK) {
1da177e4 6842 drop_it:
a3896167 6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6844 desc_idx, *post_ptr);
6845 drop_it_no_recycle:
6846 /* Other statistics kept track of by card. */
b0057c51 6847 tp->rx_dropped++;
1da177e4
LT		 6848 goto next_pkt;
6849 }
6850
9205fd9c 6851 prefetch(data + TG3_RX_OFFSET(tp));
ad829268
MC		 6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6853 ETH_FCS_LEN;
1da177e4 6854
fb4ce8ad
MC		 6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6861 }
6862
d2757fc4 6863 if (len > TG3_RX_COPY_THRESH(tp)) {
1da177e4 6864 int skb_size;
8d4057a9 6865 unsigned int frag_size;
1da177e4 6866
9205fd9c 6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
8d4057a9 6868 *post_ptr, &frag_size);
1da177e4
LT		 6869 if (skb_size < 0)
6870 goto drop_it;
6871
287be12e 6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
1da177e4
LT		 6873 PCI_DMA_FROMDEVICE);
6874
9205fd9c 6875 /* Ensure that the update to the data happens
61e800cf
MC		 6876 * after the usage of the old DMA mapping.
6877 */
6878 smp_wmb();
6879
9205fd9c 6880 ri->data = NULL;
61e800cf 6881
85aec73d
IV		 6882 skb = build_skb(data, frag_size);
6883 if (!skb) {
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6886 }
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
1da177e4 6888 } else {
a3896167 6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
1da177e4
LT		 6890 desc_idx, *post_ptr);
6891
9205fd9c
ED		 6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6894 if (skb == NULL)
1da177e4
LT		 6895 goto drop_it_no_recycle;
6896
9205fd9c 6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
1da177e4 6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
9205fd9c
ED		 6899 memcpy(skb->data,
6900 data + TG3_RX_OFFSET(tp),
6901 len);
1da177e4 6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
1da177e4
LT		 6903 }
6904
9205fd9c 6905 skb_put(skb, len);
fb4ce8ad
MC		 6906 if (tstamp)
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6909
dc668910 6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
1da177e4
LT		 6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6915 else
bc8acf2c 6916 skb_checksum_none_assert(skb);
1da177e4
LT		 6917
6918 skb->protocol = eth_type_trans(skb, tp->dev);
f7b493e0
MC		 6919
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q)) {
497a27b9 6922 dev_kfree_skb_any(skb);
b0057c51 6923 goto drop_it_no_recycle;
f7b493e0
MC		 6924 }
6925
9dc7a113 6926 if (desc->type_flags & RXD_FLAG_VLAN &&
bf933c80 6927 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
86a9bad3 6928 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
bf933c80 6929 desc->err_vlan & RXD_VLAN_MASK);
9dc7a113 6930
bf933c80 6931 napi_gro_receive(&tnapi->napi, skb);
1da177e4 6932
1da177e4
LT		 6933 received++;
6934 budget--;
6935
6936next_pkt:
6937 (*post_ptr)++;
f92905de
MC		 6938
6939 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
2c49a44d
MC		 6940 tpr->rx_std_prod_idx = std_prod_idx &
6941 tp->rx_std_ring_mask;
86cfe4ff
MC		 6942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6943 tpr->rx_std_prod_idx);
f92905de
MC		 6944 work_mask &= ~RXD_OPAQUE_RING_STD;
6945 rx_std_posted = 0;
6946 }
1da177e4 6947next_pkt_nopost:
483ba50b 6948 sw_idx++;
7cb32cf2 6949 sw_idx &= tp->rx_ret_ring_mask;
52f6d697
MC		 6950
6951 /* Refresh hw_idx to see if there is new work */
6952 if (sw_idx == hw_idx) {
8d9d7cfc 6953 hw_idx = *(tnapi->rx_rcb_prod_idx);
52f6d697
MC		 6954 rmb();
6955 }
1da177e4
LT		 6956 }
6957
6958 /* ACK the status ring. */
72334482
MC		 6959 tnapi->rx_rcb_ptr = sw_idx;
6960 tw32_rx_mbox(tnapi->consmbox, sw_idx);
1da177e4
LT		 6961
6962 /* Refill RX ring(s). */
63c3a66f 6963 if (!tg3_flag(tp, ENABLE_RSS)) {
6541b806
MC		 6964 /* Sync BD data before updating mailbox */
6965 wmb();
6966
b196c7e4 6967 if (work_mask & RXD_OPAQUE_RING_STD) {
2c49a44d
MC		 6968 tpr->rx_std_prod_idx = std_prod_idx &
6969 tp->rx_std_ring_mask;
b196c7e4
MC		 6970 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6971 tpr->rx_std_prod_idx);
6972 }
6973 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2c49a44d
MC		 6974 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6975 tp->rx_jmb_ring_mask;
b196c7e4
MC		 6976 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6977 tpr->rx_jmb_prod_idx);
6978 }
6979 mmiowb();
6980 } else if (work_mask) {
6981 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6982 * updated before the producer indices can be updated.
6983 */
6984 smp_wmb();
6985
2c49a44d
MC		 6986 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6987 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
b196c7e4 6988
7ae52890
MC		 6989 if (tnapi != &tp->napi[1]) {
6990 tp->rx_refill = true;
e4af1af9 6991 napi_schedule(&tp->napi[1].napi);
7ae52890 6992 }
1da177e4 6993 }
1da177e4
LT		 6994
6995 return received;
6996}
6997
35f2d7d0 6998static void tg3_poll_link(struct tg3 *tp)
1da177e4 6999{
1da177e4 7000 /* handle link change and other phy events */
63c3a66f 7001 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
35f2d7d0
MC		 7002 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7003
1da177e4
LT		 7004 if (sblk->status & SD_STATUS_LINK_CHG) {
7005 sblk->status = SD_STATUS_UPDATED |
35f2d7d0 7006 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 7007 spin_lock(&tp->lock);
63c3a66f 7008 if (tg3_flag(tp, USE_PHYLIB)) {
dd477003
MC		 7009 tw32_f(MAC_STATUS,
7010 (MAC_STATUS_SYNC_CHANGED |
7011 MAC_STATUS_CFG_CHANGED |
7012 MAC_STATUS_MI_COMPLETION |
7013 MAC_STATUS_LNKSTATE_CHANGED));
7014 udelay(40);
7015 } else
953c96e0 7016 tg3_setup_phy(tp, false);
f47c11ee 7017 spin_unlock(&tp->lock);
1da177e4
LT		 7018 }
7019 }
35f2d7d0
MC		 7020}
7021
f89f38b8
MC		 7022static int tg3_rx_prodring_xfer(struct tg3 *tp,
7023 struct tg3_rx_prodring_set *dpr,
7024 struct tg3_rx_prodring_set *spr)
b196c7e4
MC		 7025{
7026 u32 si, di, cpycnt, src_prod_idx;
f89f38b8 7027 int i, err = 0;
b196c7e4
MC		 7028
7029 while (1) {
7030 src_prod_idx = spr->rx_std_prod_idx;
7031
7032 /* Make sure updates to the rx_std_buffers[] entries and the
7033 * standard producer index are seen in the correct order.
7034 */
7035 smp_rmb();
7036
7037 if (spr->rx_std_cons_idx == src_prod_idx)
7038 break;
7039
7040 if (spr->rx_std_cons_idx < src_prod_idx)
7041 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7042 else
2c49a44d
MC		 7043 cpycnt = tp->rx_std_ring_mask + 1 -
7044 spr->rx_std_cons_idx;
b196c7e4 7045
2c49a44d
MC		 7046 cpycnt = min(cpycnt,
7047 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
b196c7e4
MC		 7048
7049 si = spr->rx_std_cons_idx;
7050 di = dpr->rx_std_prod_idx;
7051
e92967bf 7052 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7053 if (dpr->rx_std_buffers[i].data) {
e92967bf 7054 cpycnt = i - di;
f89f38b8 7055 err = -ENOSPC;
e92967bf
MC		 7056 break;
7057 }
7058 }
7059
7060 if (!cpycnt)
7061 break;
7062
7063 /* Ensure that updates to the rx_std_buffers ring and the
7064 * shadowed hardware producer ring from tg3_recycle_skb() are
7065 * ordered correctly WRT the skb check above.
7066 */
7067 smp_rmb();
7068
b196c7e4
MC		 7069 memcpy(&dpr->rx_std_buffers[di],
7070 &spr->rx_std_buffers[si],
7071 cpycnt * sizeof(struct ring_info));
7072
7073 for (i = 0; i < cpycnt; i++, di++, si++) {
7074 struct tg3_rx_buffer_desc *sbd, *dbd;
7075 sbd = &spr->rx_std[si];
7076 dbd = &dpr->rx_std[di];
7077 dbd->addr_hi = sbd->addr_hi;
7078 dbd->addr_lo = sbd->addr_lo;
7079 }
7080
2c49a44d
MC		 7081 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7082 tp->rx_std_ring_mask;
7083 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7084 tp->rx_std_ring_mask;
b196c7e4
MC		 7085 }
7086
7087 while (1) {
7088 src_prod_idx = spr->rx_jmb_prod_idx;
7089
7090 /* Make sure updates to the rx_jmb_buffers[] entries and
7091 * the jumbo producer index are seen in the correct order.
7092 */
7093 smp_rmb();
7094
7095 if (spr->rx_jmb_cons_idx == src_prod_idx)
7096 break;
7097
7098 if (spr->rx_jmb_cons_idx < src_prod_idx)
7099 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7100 else
2c49a44d
MC		 7101 cpycnt = tp->rx_jmb_ring_mask + 1 -
7102 spr->rx_jmb_cons_idx;
b196c7e4
MC		 7103
7104 cpycnt = min(cpycnt,
2c49a44d 7105 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7106
7107 si = spr->rx_jmb_cons_idx;
7108 di = dpr->rx_jmb_prod_idx;
7109
e92967bf 7110 for (i = di; i < di + cpycnt; i++) {
9205fd9c 7111 if (dpr->rx_jmb_buffers[i].data) {
e92967bf 7112 cpycnt = i - di;
f89f38b8 7113 err = -ENOSPC;
e92967bf
MC		 7114 break;
7115 }
7116 }
7117
7118 if (!cpycnt)
7119 break;
7120
7121 /* Ensure that updates to the rx_jmb_buffers ring and the
7122 * shadowed hardware producer ring from tg3_recycle_skb() are
7123 * ordered correctly WRT the skb check above.
7124 */
7125 smp_rmb();
7126
b196c7e4
MC		 7127 memcpy(&dpr->rx_jmb_buffers[di],
7128 &spr->rx_jmb_buffers[si],
7129 cpycnt * sizeof(struct ring_info));
7130
7131 for (i = 0; i < cpycnt; i++, di++, si++) {
7132 struct tg3_rx_buffer_desc *sbd, *dbd;
7133 sbd = &spr->rx_jmb[si].std;
7134 dbd = &dpr->rx_jmb[di].std;
7135 dbd->addr_hi = sbd->addr_hi;
7136 dbd->addr_lo = sbd->addr_lo;
7137 }
7138
2c49a44d
MC		 7139 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7140 tp->rx_jmb_ring_mask;
7141 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7142 tp->rx_jmb_ring_mask;
b196c7e4 7143 }
f89f38b8
MC		 7144
7145 return err;
b196c7e4
MC		 7146}
7147
35f2d7d0
MC		 7148static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7149{
7150 struct tg3 *tp = tnapi->tp;
1da177e4
LT		 7151
7152 /* run TX completion thread */
f3f3f27e 7153 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
17375d25 7154 tg3_tx(tnapi);
63c3a66f 7155 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
4fd7ab59 7156 return work_done;
1da177e4
LT		 7157 }
7158
f891ea16
MC		 7159 if (!tnapi->rx_rcb_prod_idx)
7160 return work_done;
7161
1da177e4
LT		 7162 /* run RX thread, within the bounds set by NAPI.
7163 * All RX "locking" is done by ensuring outside
bea3348e 7164 * code synchronizes with tg3->napi.poll()
1da177e4 7165 */
8d9d7cfc 7166 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
17375d25 7167 work_done += tg3_rx(tnapi, budget - work_done);
1da177e4 7168
63c3a66f 7169 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
8fea32b9 7170 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
f89f38b8 7171 int i, err = 0;
e4af1af9
MC		 7172 u32 std_prod_idx = dpr->rx_std_prod_idx;
7173 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
b196c7e4 7174
7ae52890 7175 tp->rx_refill = false;
9102426a 7176 for (i = 1; i <= tp->rxq_cnt; i++)
f89f38b8 7177 err |= tg3_rx_prodring_xfer(tp, dpr,
8fea32b9 7178 &tp->napi[i].prodring);
b196c7e4
MC		 7179
7180 wmb();
7181
e4af1af9
MC		 7182 if (std_prod_idx != dpr->rx_std_prod_idx)
7183 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7184 dpr->rx_std_prod_idx);
b196c7e4 7185
e4af1af9
MC		 7186 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7187 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7188 dpr->rx_jmb_prod_idx);
b196c7e4
MC		 7189
7190 mmiowb();
f89f38b8
MC		 7191
7192 if (err)
7193 tw32_f(HOSTCC_MODE, tp->coal_now);
b196c7e4
MC		 7194 }
7195
6f535763
DM		 7196 return work_done;
7197}
7198
db219973
MC		 7199static inline void tg3_reset_task_schedule(struct tg3 *tp)
7200{
7201 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7202 schedule_work(&tp->reset_task);
7203}
7204
7205static inline void tg3_reset_task_cancel(struct tg3 *tp)
7206{
7207 cancel_work_sync(&tp->reset_task);
7208 tg3_flag_clear(tp, RESET_TASK_PENDING);
c7101359 7209 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
db219973
MC		 7210}
7211
35f2d7d0
MC		 7212static int tg3_poll_msix(struct napi_struct *napi, int budget)
7213{
7214 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7215 struct tg3 *tp = tnapi->tp;
7216 int work_done = 0;
7217 struct tg3_hw_status *sblk = tnapi->hw_status;
7218
7219 while (1) {
7220 work_done = tg3_poll_work(tnapi, work_done, budget);
7221
63c3a66f 7222 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
35f2d7d0
MC		 7223 goto tx_recovery;
7224
7225 if (unlikely(work_done >= budget))
7226 break;
7227
c6cdf436 7228 /* tp->last_tag is used in tg3_int_reenable() below
35f2d7d0
MC		 7229 * to tell the hw how much work has been processed,
7230 * so we must read it before checking for more work.
7231 */
7232 tnapi->last_tag = sblk->status_tag;
7233 tnapi->last_irq_tag = tnapi->last_tag;
7234 rmb();
7235
7236 /* check for RX/TX work to do */
6d40db7b
MC		 7237 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7238 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7ae52890
MC		 7239
7240 /* This test here is not race free, but will reduce
7241 * the number of interrupts by looping again.
7242 */
7243 if (tnapi == &tp->napi[1] && tp->rx_refill)
7244 continue;
7245
35f2d7d0
MC		 7246 napi_complete(napi);
7247 /* Reenable interrupts. */
7248 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7ae52890
MC		 7249
7250 /* This test here is synchronized by napi_schedule()
7251 * and napi_complete() to close the race condition.
7252 */
7253 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7254 tw32(HOSTCC_MODE, tp->coalesce_mode |
7255 HOSTCC_MODE_ENABLE |
7256 tnapi->coal_now);
7257 }
35f2d7d0
MC		 7258 mmiowb();
7259 break;
7260 }
7261 }
7262
7263 return work_done;
7264
7265tx_recovery:
7266 /* work_done is guaranteed to be less than budget. */
7267 napi_complete(napi);
db219973 7268 tg3_reset_task_schedule(tp);
35f2d7d0
MC		 7269 return work_done;
7270}
7271
e64de4e6
MC		 7272static void tg3_process_error(struct tg3 *tp)
7273{
7274 u32 val;
7275 bool real_error = false;
7276
63c3a66f 7277 if (tg3_flag(tp, ERROR_PROCESSED))
e64de4e6
MC		 7278 return;
7279
7280 /* Check Flow Attention register */
7281 val = tr32(HOSTCC_FLOW_ATTN);
7282 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7283 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7284 real_error = true;
7285 }
7286
7287 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7288 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7289 real_error = true;
7290 }
7291
7292 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7293 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7294 real_error = true;
7295 }
7296
7297 if (!real_error)
7298 return;
7299
7300 tg3_dump_state(tp);
7301
63c3a66f 7302 tg3_flag_set(tp, ERROR_PROCESSED);
db219973 7303 tg3_reset_task_schedule(tp);
e64de4e6
MC		 7304}
7305
6f535763
DM		 7306static int tg3_poll(struct napi_struct *napi, int budget)
7307{
8ef0442f
MC		 7308 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7309 struct tg3 *tp = tnapi->tp;
6f535763 7310 int work_done = 0;
898a56f8 7311 struct tg3_hw_status *sblk = tnapi->hw_status;
6f535763
DM		 7312
7313 while (1) {
e64de4e6
MC		 7314 if (sblk->status & SD_STATUS_ERROR)
7315 tg3_process_error(tp);
7316
35f2d7d0
MC		 7317 tg3_poll_link(tp);
7318
17375d25 7319 work_done = tg3_poll_work(tnapi, work_done, budget);
6f535763 7320
63c3a66f 7321 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6f535763
DM		 7322 goto tx_recovery;
7323
7324 if (unlikely(work_done >= budget))
7325 break;
7326
63c3a66f 7327 if (tg3_flag(tp, TAGGED_STATUS)) {
17375d25 7328 /* tp->last_tag is used in tg3_int_reenable() below
4fd7ab59
MC		 7329 * to tell the hw how much work has been processed,
7330 * so we must read it before checking for more work.
7331 */
898a56f8
MC		 7332 tnapi->last_tag = sblk->status_tag;
7333 tnapi->last_irq_tag = tnapi->last_tag;
4fd7ab59
MC		 7334 rmb();
7335 } else
7336 sblk->status &= ~SD_STATUS_UPDATED;
6f535763 7337
17375d25 7338 if (likely(!tg3_has_work(tnapi))) {
288379f0 7339 napi_complete(napi);
17375d25 7340 tg3_int_reenable(tnapi);
6f535763
DM		 7341 break;
7342 }
1da177e4
LT		 7343 }
7344
bea3348e 7345 return work_done;
6f535763
DM		 7346
7347tx_recovery:
4fd7ab59 7348 /* work_done is guaranteed to be less than budget. */
288379f0 7349 napi_complete(napi);
db219973 7350 tg3_reset_task_schedule(tp);
4fd7ab59 7351 return work_done;
1da177e4
LT		 7352}
7353
66cfd1bd
MC		 7354static void tg3_napi_disable(struct tg3 *tp)
7355{
7356 int i;
7357
7358 for (i = tp->irq_cnt - 1; i >= 0; i--)
7359 napi_disable(&tp->napi[i].napi);
7360}
7361
7362static void tg3_napi_enable(struct tg3 *tp)
7363{
7364 int i;
7365
7366 for (i = 0; i < tp->irq_cnt; i++)
7367 napi_enable(&tp->napi[i].napi);
7368}
7369
7370static void tg3_napi_init(struct tg3 *tp)
7371{
7372 int i;
7373
7374 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7375 for (i = 1; i < tp->irq_cnt; i++)
7376 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7377}
7378
7379static void tg3_napi_fini(struct tg3 *tp)
7380{
7381 int i;
7382
7383 for (i = 0; i < tp->irq_cnt; i++)
7384 netif_napi_del(&tp->napi[i].napi);
7385}
7386
7387static inline void tg3_netif_stop(struct tg3 *tp)
7388{
7389 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7390 tg3_napi_disable(tp);
f4a46d1f 7391 netif_carrier_off(tp->dev);
66cfd1bd
MC		 7392 netif_tx_disable(tp->dev);
7393}
7394
35763066 7395/* tp->lock must be held */
66cfd1bd
MC		 7396static inline void tg3_netif_start(struct tg3 *tp)
7397{
be947307
MC		 7398 tg3_ptp_resume(tp);
7399
66cfd1bd
MC		 7400 /* NOTE: unconditional netif_tx_wake_all_queues is only
7401 * appropriate so long as all callers are assured to
7402 * have free tx slots (such as after tg3_init_hw)
7403 */
7404 netif_tx_wake_all_queues(tp->dev);
7405
f4a46d1f
NNS		 7406 if (tp->link_up)
7407 netif_carrier_on(tp->dev);
7408
66cfd1bd
MC		 7409 tg3_napi_enable(tp);
7410 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7411 tg3_enable_ints(tp);
7412}
7413
f47c11ee
DM		 7414static void tg3_irq_quiesce(struct tg3 *tp)
7415{
4f125f42
MC		 7416 int i;
7417
f47c11ee
DM		 7418 BUG_ON(tp->irq_sync);
7419
7420 tp->irq_sync = 1;
7421 smp_mb();
7422
4f125f42
MC		 7423 for (i = 0; i < tp->irq_cnt; i++)
7424 synchronize_irq(tp->napi[i].irq_vec);
f47c11ee
DM		 7425}
7426
f47c11ee
DM		 7427/* Fully shutdown all tg3 driver activity elsewhere in the system.
7428 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7429 * with as well. Most of the time, this is not necessary except when
7430 * shutting down the device.
7431 */
7432static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7433{
46966545 7434 spin_lock_bh(&tp->lock);
f47c11ee
DM		 7435 if (irq_sync)
7436 tg3_irq_quiesce(tp);
f47c11ee
DM		 7437}
7438
7439static inline void tg3_full_unlock(struct tg3 *tp)
7440{
f47c11ee
DM		 7441 spin_unlock_bh(&tp->lock);
7442}
7443
fcfa0a32
MC		 7444/* One-shot MSI handler - Chip automatically disables interrupt
7445 * after sending MSI so driver doesn't have to do it.
7446 */
7d12e780 7447static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
fcfa0a32 7448{
09943a18
MC		 7449 struct tg3_napi *tnapi = dev_id;
7450 struct tg3 *tp = tnapi->tp;
fcfa0a32 7451
898a56f8 7452 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7453 if (tnapi->rx_rcb)
7454 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
fcfa0a32
MC		 7455
7456 if (likely(!tg3_irq_sync(tp)))
09943a18 7457 napi_schedule(&tnapi->napi);
fcfa0a32
MC		 7458
7459 return IRQ_HANDLED;
7460}
7461
88b06bc2
MC		 7462/* MSI ISR - No need to check for interrupt sharing and no need to
7463 * flush status block and interrupt mailbox. PCI ordering rules
7464 * guarantee that MSI will arrive after the status block.
7465 */
7d12e780 7466static irqreturn_t tg3_msi(int irq, void *dev_id)
88b06bc2 7467{
09943a18
MC		 7468 struct tg3_napi *tnapi = dev_id;
7469 struct tg3 *tp = tnapi->tp;
88b06bc2 7470
898a56f8 7471 prefetch(tnapi->hw_status);
0c1d0e2b
MC		 7472 if (tnapi->rx_rcb)
7473 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
88b06bc2 7474 /*
fac9b83e 7475 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 7476 * chip-internal interrupt pending events.
fac9b83e 7477 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 7478 * NIC to stop sending us irqs, engaging "in-intr-handler"
7479 * event coalescing.
7480 */
5b39de91 7481 tw32_mailbox(tnapi->int_mbox, 0x00000001);
61487480 7482 if (likely(!tg3_irq_sync(tp)))
09943a18 7483 napi_schedule(&tnapi->napi);
61487480 7484
88b06bc2
MC		 7485 return IRQ_RETVAL(1);
7486}
7487
7d12e780 7488static irqreturn_t tg3_interrupt(int irq, void *dev_id)
1da177e4 7489{
09943a18
MC		 7490 struct tg3_napi *tnapi = dev_id;
7491 struct tg3 *tp = tnapi->tp;
898a56f8 7492 struct tg3_hw_status *sblk = tnapi->hw_status;
1da177e4
LT		 7493 unsigned int handled = 1;
7494
1da177e4
LT		 7495 /* In INTx mode, it is possible for the interrupt to arrive at
7496 * the CPU before the status block posted prior to the interrupt.
7497 * Reading the PCI State register will confirm whether the
7498 * interrupt is ours and will flush the status block.
7499 */
d18edcb2 7500 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
63c3a66f 7501 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7502 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7503 handled = 0;
f47c11ee 7504 goto out;
fac9b83e 7505 }
d18edcb2
MC		 7506 }
7507
7508 /*
7509 * Writing any value to intr-mbox-0 clears PCI INTA# and
7510 * chip-internal interrupt pending events.
7511 * Writing non-zero to intr-mbox-0 additional tells the
7512 * NIC to stop sending us irqs, engaging "in-intr-handler"
7513 * event coalescing.
c04cb347
MC		 7514 *
7515 * Flush the mailbox to de-assert the IRQ immediately to prevent
7516 * spurious interrupts. The flush impacts performance but
7517 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7518 */
c04cb347 7519 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
d18edcb2
MC		 7520 if (tg3_irq_sync(tp))
7521 goto out;
7522 sblk->status &= ~SD_STATUS_UPDATED;
17375d25 7523 if (likely(tg3_has_work(tnapi))) {
72334482 7524 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
09943a18 7525 napi_schedule(&tnapi->napi);
d18edcb2
MC		 7526 } else {
7527 /* No work, shared interrupt perhaps? re-enable
7528 * interrupts, and flush that PCI write
7529 */
7530 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7531 0x00000000);
fac9b83e 7532 }
f47c11ee 7533out:
fac9b83e
DM		 7534 return IRQ_RETVAL(handled);
7535}
7536
7d12e780 7537static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
fac9b83e 7538{
09943a18
MC		 7539 struct tg3_napi *tnapi = dev_id;
7540 struct tg3 *tp = tnapi->tp;
898a56f8 7541 struct tg3_hw_status *sblk = tnapi->hw_status;
fac9b83e
DM		 7542 unsigned int handled = 1;
7543
fac9b83e
DM		 7544 /* In INTx mode, it is possible for the interrupt to arrive at
7545 * the CPU before the status block posted prior to the interrupt.
7546 * Reading the PCI State register will confirm whether the
7547 * interrupt is ours and will flush the status block.
7548 */
898a56f8 7549 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
63c3a66f 7550 if (tg3_flag(tp, CHIP_RESETTING) ||
d18edcb2
MC		 7551 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7552 handled = 0;
f47c11ee 7553 goto out;
1da177e4 7554 }
d18edcb2
MC		 7555 }
7556
7557 /*
7558 * writing any value to intr-mbox-0 clears PCI INTA# and
7559 * chip-internal interrupt pending events.
7560 * writing non-zero to intr-mbox-0 additional tells the
7561 * NIC to stop sending us irqs, engaging "in-intr-handler"
7562 * event coalescing.
c04cb347
MC		 7563 *
7564 * Flush the mailbox to de-assert the IRQ immediately to prevent
7565 * spurious interrupts. The flush impacts performance but
7566 * excessive spurious interrupts can be worse in some cases.
d18edcb2 7567 */
c04cb347 7568 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
624f8e50
MC		 7569
7570 /*
7571 * In a shared interrupt configuration, sometimes other devices'
7572 * interrupts will scream. We record the current status tag here
7573 * so that the above check can report that the screaming interrupts
7574 * are unhandled. Eventually they will be silenced.
7575 */
898a56f8 7576 tnapi->last_irq_tag = sblk->status_tag;
624f8e50 7577
d18edcb2
MC		 7578 if (tg3_irq_sync(tp))
7579 goto out;
624f8e50 7580
72334482 7581 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
624f8e50 7582
09943a18 7583 napi_schedule(&tnapi->napi);
624f8e50 7584
f47c11ee 7585out:
1da177e4
LT		 7586 return IRQ_RETVAL(handled);
7587}
7588
7938109f 7589/* ISR for interrupt test */
7d12e780 7590static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7938109f 7591{
09943a18
MC		 7592 struct tg3_napi *tnapi = dev_id;
7593 struct tg3 *tp = tnapi->tp;
898a56f8 7594 struct tg3_hw_status *sblk = tnapi->hw_status;
7938109f 7595
f9804ddb
MC		 7596 if ((sblk->status & SD_STATUS_UPDATED) ||
7597 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
b16250e3 7598 tg3_disable_ints(tp);
7938109f
MC		 7599 return IRQ_RETVAL(1);
7600 }
7601 return IRQ_RETVAL(0);
7602}
7603
1da177e4
LT		 7604#ifdef CONFIG_NET_POLL_CONTROLLER
7605static void tg3_poll_controller(struct net_device *dev)
7606{
4f125f42 7607 int i;
88b06bc2
MC		 7608 struct tg3 *tp = netdev_priv(dev);
7609
9c13cb8b
NNS		 7610 if (tg3_irq_sync(tp))
7611 return;
7612
4f125f42 7613 for (i = 0; i < tp->irq_cnt; i++)
fe234f0e 7614 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
1da177e4
LT		 7615}
7616#endif
7617
1da177e4
LT		 7618static void tg3_tx_timeout(struct net_device *dev)
7619{
7620 struct tg3 *tp = netdev_priv(dev);
7621
b0408751 7622 if (netif_msg_tx_err(tp)) {
05dbe005 7623 netdev_err(dev, "transmit timed out, resetting\n");
97bd8e49 7624 tg3_dump_state(tp);
b0408751 7625 }
1da177e4 7626
db219973 7627 tg3_reset_task_schedule(tp);
1da177e4
LT		 7628}
7629
c58ec932
MC		 7630/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7631static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7632{
7633 u32 base = (u32) mapping & 0xffffffff;
7634
37567910 7635 return base + len + 8 < base;
c58ec932
MC		 7636}
7637
0f0d1510
MC		 7638/* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7639 * of any 4GB boundaries: 4G, 8G, etc
7640 */
7641static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7642 u32 len, u32 mss)
7643{
7644 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7645 u32 base = (u32) mapping & 0xffffffff;
7646
7647 return ((base + len + (mss & 0x3fff)) < base);
7648 }
7649 return 0;
7650}
7651
72f2afb8
MC		 7652/* Test for DMA addresses > 40-bit */
7653static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7654 int len)
7655{
7656#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
63c3a66f 7657 if (tg3_flag(tp, 40BIT_DMA_BUG))
807540ba 7658 return ((u64) mapping + len) > DMA_BIT_MASK(40);
72f2afb8
MC		 7659 return 0;
7660#else
7661 return 0;
7662#endif
7663}
7664
d1a3b737 7665static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
92cd3a17
MC		 7666 dma_addr_t mapping, u32 len, u32 flags,
7667 u32 mss, u32 vlan)
2ffcc981 7668{
92cd3a17
MC		 7669 txbd->addr_hi = ((u64) mapping >> 32);
7670 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7671 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7672 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
2ffcc981 7673}
1da177e4 7674
84b67b27 7675static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
d1a3b737
MC		 7676 dma_addr_t map, u32 len, u32 flags,
7677 u32 mss, u32 vlan)
7678{
7679 struct tg3 *tp = tnapi->tp;
7680 bool hwbug = false;
7681
7682 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
3db1cd5c 7683 hwbug = true;
d1a3b737
MC		 7684
7685 if (tg3_4g_overflow_test(map, len))
3db1cd5c 7686 hwbug = true;
d1a3b737 7687
0f0d1510
MC		 7688 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7689 hwbug = true;
7690
d1a3b737 7691 if (tg3_40bit_overflow_test(tp, map, len))
3db1cd5c 7692 hwbug = true;
d1a3b737 7693
a4cb428d 7694 if (tp->dma_limit) {
b9e45482 7695 u32 prvidx = *entry;
e31aa987 7696 u32 tmp_flag = flags & ~TXD_FLAG_END;
a4cb428d
MC		 7697 while (len > tp->dma_limit && *budget) {
7698 u32 frag_len = tp->dma_limit;
7699 len -= tp->dma_limit;
e31aa987 7700
b9e45482
MC		 7701 /* Avoid the 8byte DMA problem */
7702 if (len <= 8) {
a4cb428d
MC		 7703 len += tp->dma_limit / 2;
7704 frag_len = tp->dma_limit / 2;
e31aa987
MC		 7705 }
7706
b9e45482
MC		 7707 tnapi->tx_buffers[*entry].fragmented = true;
7708
7709 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7710 frag_len, tmp_flag, mss, vlan);
7711 *budget -= 1;
7712 prvidx = *entry;
7713 *entry = NEXT_TX(*entry);
7714
e31aa987
MC		 7715 map += frag_len;
7716 }
7717
7718 if (len) {
7719 if (*budget) {
7720 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7721 len, flags, mss, vlan);
b9e45482 7722 *budget -= 1;
e31aa987
MC		 7723 *entry = NEXT_TX(*entry);
7724 } else {
3db1cd5c 7725 hwbug = true;
b9e45482 7726 tnapi->tx_buffers[prvidx].fragmented = false;
e31aa987
MC		 7727 }
7728 }
7729 } else {
84b67b27
MC		 7730 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7731 len, flags, mss, vlan);
e31aa987
MC		 7732 *entry = NEXT_TX(*entry);
7733 }
d1a3b737
MC		 7734
7735 return hwbug;
7736}
7737
0d681b27 7738static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
432aa7ed
MC		 7739{
7740 int i;
0d681b27 7741 struct sk_buff *skb;
df8944cf 7742 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
432aa7ed 7743
0d681b27
MC		 7744 skb = txb->skb;
7745 txb->skb = NULL;
7746
432aa7ed
MC		 7747 pci_unmap_single(tnapi->tp->pdev,
7748 dma_unmap_addr(txb, mapping),
7749 skb_headlen(skb),
7750 PCI_DMA_TODEVICE);
e01ee14d
MC		 7751
7752 while (txb->fragmented) {
7753 txb->fragmented = false;
7754 entry = NEXT_TX(entry);
7755 txb = &tnapi->tx_buffers[entry];
7756 }
7757
ba1142e4 7758 for (i = 0; i <= last; i++) {
9e903e08 7759 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
432aa7ed
MC		 7760
7761 entry = NEXT_TX(entry);
7762 txb = &tnapi->tx_buffers[entry];
7763
7764 pci_unmap_page(tnapi->tp->pdev,
7765 dma_unmap_addr(txb, mapping),
9e903e08 7766 skb_frag_size(frag), PCI_DMA_TODEVICE);
e01ee14d
MC		 7767
7768 while (txb->fragmented) {
7769 txb->fragmented = false;
7770 entry = NEXT_TX(entry);
7771 txb = &tnapi->tx_buffers[entry];
7772 }
432aa7ed
MC		 7773 }
7774}
7775
72f2afb8 7776/* Workaround 4GB and 40-bit hardware DMA bugs. */
24f4efd4 7777static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
f7ff1987 7778 struct sk_buff **pskb,
84b67b27 7779 u32 *entry, u32 *budget,
92cd3a17 7780 u32 base_flags, u32 mss, u32 vlan)
1da177e4 7781{
24f4efd4 7782 struct tg3 *tp = tnapi->tp;
f7ff1987 7783 struct sk_buff *new_skb, *skb = *pskb;
c58ec932 7784 dma_addr_t new_addr = 0;
432aa7ed 7785 int ret = 0;
1da177e4 7786
4153577a 7787 if (tg3_asic_rev(tp) != ASIC_REV_5701)
41588ba1
MC		 7788 new_skb = skb_copy(skb, GFP_ATOMIC);
7789 else {
7790 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7791
7792 new_skb = skb_copy_expand(skb,
7793 skb_headroom(skb) + more_headroom,
7794 skb_tailroom(skb), GFP_ATOMIC);
7795 }
7796
1da177e4 7797 if (!new_skb) {
c58ec932
MC		 7798 ret = -1;
7799 } else {
7800 /* New SKB is guaranteed to be linear. */
f4188d8a
AD		 7801 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7802 PCI_DMA_TODEVICE);
7803 /* Make sure the mapping succeeded */
7804 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
497a27b9 7805 dev_kfree_skb_any(new_skb);
c58ec932 7806 ret = -1;
c58ec932 7807 } else {
b9e45482
MC		 7808 u32 save_entry = *entry;
7809
92cd3a17
MC		 7810 base_flags |= TXD_FLAG_END;
7811
84b67b27
MC		 7812 tnapi->tx_buffers[*entry].skb = new_skb;
7813 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
432aa7ed
MC		 7814 mapping, new_addr);
7815
84b67b27 7816 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
d1a3b737
MC		 7817 new_skb->len, base_flags,
7818 mss, vlan)) {
ba1142e4 7819 tg3_tx_skb_unmap(tnapi, save_entry, -1);
497a27b9 7820 dev_kfree_skb_any(new_skb);
d1a3b737
MC		 7821 ret = -1;
7822 }
f4188d8a 7823 }
1da177e4
LT		 7824 }
7825
497a27b9 7826 dev_kfree_skb_any(skb);
f7ff1987 7827 *pskb = new_skb;
c58ec932 7828 return ret;
1da177e4
LT		 7829}
7830
2ffcc981 7831static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
52c0fd83
MC		 7832
7833/* Use GSO to workaround a rare TSO bug that may be triggered when the
7834 * TSO header is greater than 80 bytes.
7835 */
7836static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7837{
7838 struct sk_buff *segs, *nskb;
f3f3f27e 7839 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
52c0fd83
MC		 7840
7841 /* Estimate the number of fragments in the worst case */
f3f3f27e 7842 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
52c0fd83 7843 netif_stop_queue(tp->dev);
f65aac16
MC		 7844
7845 /* netif_tx_stop_queue() must be done before checking
7846 * checking tx index in tg3_tx_avail() below, because in
7847 * tg3_tx(), we update tx index before checking for
7848 * netif_tx_queue_stopped().
7849 */
7850 smp_mb();
f3f3f27e 7851 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7f62ad5d
MC		 7852 return NETDEV_TX_BUSY;
7853
7854 netif_wake_queue(tp->dev);
52c0fd83
MC		 7855 }
7856
7857 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
801678c5 7858 if (IS_ERR(segs))
52c0fd83
MC		 7859 goto tg3_tso_bug_end;
7860
7861 do {
7862 nskb = segs;
7863 segs = segs->next;
7864 nskb->next = NULL;
2ffcc981 7865 tg3_start_xmit(nskb, tp->dev);
52c0fd83
MC		 7866 } while (segs);
7867
7868tg3_tso_bug_end:
497a27b9 7869 dev_kfree_skb_any(skb);
52c0fd83
MC		 7870
7871 return NETDEV_TX_OK;
7872}
52c0fd83 7873
d71c0dc4 7874/* hard_start_xmit for all devices */
2ffcc981 7875static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 7876{
7877 struct tg3 *tp = netdev_priv(dev);
92cd3a17 7878 u32 len, entry, base_flags, mss, vlan = 0;
84b67b27 7879 u32 budget;
432aa7ed 7880 int i = -1, would_hit_hwbug;
90079ce8 7881 dma_addr_t mapping;
24f4efd4
MC		 7882 struct tg3_napi *tnapi;
7883 struct netdev_queue *txq;
432aa7ed 7884 unsigned int last;
d3f6f3a1
MC		 7885 struct iphdr *iph = NULL;
7886 struct tcphdr *tcph = NULL;
7887 __sum16 tcp_csum = 0, ip_csum = 0;
7888 __be16 ip_tot_len = 0;
f4188d8a 7889
24f4efd4
MC		 7890 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7891 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
63c3a66f 7892 if (tg3_flag(tp, ENABLE_TSS))
24f4efd4 7893 tnapi++;
1da177e4 7894
84b67b27
MC		 7895 budget = tg3_tx_avail(tnapi);
7896
00b70504 7897 /* We are running in BH disabled context with netif_tx_lock
bea3348e 7898 * and TX reclaim runs via tp->napi.poll inside of a software
f47c11ee
DM		 7899 * interrupt. Furthermore, IRQ processing runs lockless so we have
7900 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 7901 */
84b67b27 7902 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
24f4efd4
MC		 7903 if (!netif_tx_queue_stopped(txq)) {
7904 netif_tx_stop_queue(txq);
1f064a87
SH		 7905
7906 /* This is a hard error, log it. */
5129c3a3
MC		 7907 netdev_err(dev,
7908 "BUG! Tx Ring full when queue awake!\n");
1f064a87 7909 }
1da177e4
LT		 7910 return NETDEV_TX_BUSY;
7911 }
7912
f3f3f27e 7913 entry = tnapi->tx_prod;
1da177e4 7914 base_flags = 0;
84fa7933 7915 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 7916 base_flags |= TXD_FLAG_TCPUDP_CSUM;
24f4efd4 7917
be98da6a
MC		 7918 mss = skb_shinfo(skb)->gso_size;
7919 if (mss) {
34195c3d 7920 u32 tcp_opt_len, hdr_len;
1da177e4 7921
105dcb59 7922 if (skb_cow_head(skb, 0))
48855432 7923 goto drop;
1da177e4 7924
34195c3d 7925 iph = ip_hdr(skb);
ab6a5bb6 7926 tcp_opt_len = tcp_optlen(skb);
1da177e4 7927
a5a11955 7928 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
34195c3d 7929
a5a11955 7930 if (!skb_is_gso_v6(skb)) {
d71c0dc4
MC		 7931 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7932 tg3_flag(tp, TSO_BUG))
7933 return tg3_tso_bug(tp, skb);
7934
d3f6f3a1
MC		 7935 ip_csum = iph->check;
7936 ip_tot_len = iph->tot_len;
34195c3d
MC		 7937 iph->check = 0;
7938 iph->tot_len = htons(mss + hdr_len);
7939 }
7940
1da177e4
LT		 7941 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7942 TXD_FLAG_CPU_POST_DMA);
7943
d3f6f3a1
MC		 7944 tcph = tcp_hdr(skb);
7945 tcp_csum = tcph->check;
7946
63c3a66f
JP		 7947 if (tg3_flag(tp, HW_TSO_1) ||
7948 tg3_flag(tp, HW_TSO_2) ||
7949 tg3_flag(tp, HW_TSO_3)) {
d3f6f3a1 7950 tcph->check = 0;
1da177e4 7951 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
d3f6f3a1
MC		 7952 } else {
7953 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7954 0, IPPROTO_TCP, 0);
7955 }
1da177e4 7956
63c3a66f 7957 if (tg3_flag(tp, HW_TSO_3)) {
615774fe
MC		 7958 mss |= (hdr_len & 0xc) << 12;
7959 if (hdr_len & 0x10)
7960 base_flags |= 0x00000010;
7961 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 7962 } else if (tg3_flag(tp, HW_TSO_2))
92c6b8d1 7963 mss |= hdr_len << 9;
63c3a66f 7964 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 7965 tg3_asic_rev(tp) == ASIC_REV_5705) {
eddc9ec5 7966 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7967 int tsflags;
7968
eddc9ec5 7969 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7970 mss |= (tsflags << 11);
7971 }
7972 } else {
eddc9ec5 7973 if (tcp_opt_len || iph->ihl > 5) {
1da177e4
LT		 7974 int tsflags;
7975
eddc9ec5 7976 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
1da177e4
LT		 7977 base_flags |= tsflags << 12;
7978 }
7979 }
7980 }
bf933c80 7981
93a700a9
MC		 7982 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7983 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7984 base_flags |= TXD_FLAG_JMB_PKT;
7985
92cd3a17
MC		 7986 if (vlan_tx_tag_present(skb)) {
7987 base_flags |= TXD_FLAG_VLAN;
7988 vlan = vlan_tx_tag_get(skb);
7989 }
1da177e4 7990
fb4ce8ad
MC		 7991 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7992 tg3_flag(tp, TX_TSTAMP_EN)) {
7993 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7994 base_flags |= TXD_FLAG_HWTSTAMP;
7995 }
7996
f4188d8a
AD		 7997 len = skb_headlen(skb);
7998
7999 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
48855432
ED		 8000 if (pci_dma_mapping_error(tp->pdev, mapping))
8001 goto drop;
8002
90079ce8 8003
f3f3f27e 8004 tnapi->tx_buffers[entry].skb = skb;
4e5e4f0d 8005 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
1da177e4
LT		 8006
8007 would_hit_hwbug = 0;
8008
63c3a66f 8009 if (tg3_flag(tp, 5701_DMA_BUG))
c58ec932 8010 would_hit_hwbug = 1;
1da177e4 8011
84b67b27 8012 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
d1a3b737 8013 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
ba1142e4 8014 mss, vlan)) {
d1a3b737 8015 would_hit_hwbug = 1;
ba1142e4 8016 } else if (skb_shinfo(skb)->nr_frags > 0) {
92cd3a17
MC		 8017 u32 tmp_mss = mss;
8018
8019 if (!tg3_flag(tp, HW_TSO_1) &&
8020 !tg3_flag(tp, HW_TSO_2) &&
8021 !tg3_flag(tp, HW_TSO_3))
8022 tmp_mss = 0;
8023
c5665a53
MC		 8024 /* Now loop through additional data
8025 * fragments, and queue them.
8026 */
1da177e4
LT		 8027 last = skb_shinfo(skb)->nr_frags - 1;
8028 for (i = 0; i <= last; i++) {
8029 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8030
9e903e08 8031 len = skb_frag_size(frag);
dc234d0b 8032 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
5d6bcdfe 8033 len, DMA_TO_DEVICE);
1da177e4 8034
f3f3f27e 8035 tnapi->tx_buffers[entry].skb = NULL;
4e5e4f0d 8036 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
f4188d8a 8037 mapping);
5d6bcdfe 8038 if (dma_mapping_error(&tp->pdev->dev, mapping))
f4188d8a 8039 goto dma_error;
1da177e4 8040
b9e45482
MC		 8041 if (!budget ||
8042 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
84b67b27
MC		 8043 len, base_flags |
8044 ((i == last) ? TXD_FLAG_END : 0),
b9e45482 8045 tmp_mss, vlan)) {
72f2afb8 8046 would_hit_hwbug = 1;
b9e45482
MC		 8047 break;
8048 }
1da177e4
LT		 8049 }
8050 }
8051
8052 if (would_hit_hwbug) {
0d681b27 8053 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
1da177e4 8054
d3f6f3a1
MC		 8055 if (mss) {
8056 /* If it's a TSO packet, do GSO instead of
8057 * allocating and copying to a large linear SKB
8058 */
8059 if (ip_tot_len) {
8060 iph->check = ip_csum;
8061 iph->tot_len = ip_tot_len;
8062 }
8063 tcph->check = tcp_csum;
8064 return tg3_tso_bug(tp, skb);
8065 }
8066
1da177e4
LT		 8067 /* If the workaround fails due to memory/mapping
8068 * failure, silently drop this packet.
8069 */
84b67b27
MC		 8070 entry = tnapi->tx_prod;
8071 budget = tg3_tx_avail(tnapi);
f7ff1987 8072 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
84b67b27 8073 base_flags, mss, vlan))
48855432 8074 goto drop_nofree;
1da177e4
LT		 8075 }
8076
d515b450 8077 skb_tx_timestamp(skb);
5cb917bc 8078 netdev_tx_sent_queue(txq, skb->len);
d515b450 8079
6541b806
MC		 8080 /* Sync BD data before updating mailbox */
8081 wmb();
8082
1da177e4 8083 /* Packets are ready, update Tx producer idx local and on card. */
24f4efd4 8084 tw32_tx_mbox(tnapi->prodmbox, entry);
1da177e4 8085
f3f3f27e
MC		 8086 tnapi->tx_prod = entry;
8087 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
24f4efd4 8088 netif_tx_stop_queue(txq);
f65aac16
MC		 8089
8090 /* netif_tx_stop_queue() must be done before checking
8091 * checking tx index in tg3_tx_avail() below, because in
8092 * tg3_tx(), we update tx index before checking for
8093 * netif_tx_queue_stopped().
8094 */
8095 smp_mb();
f3f3f27e 8096 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
24f4efd4 8097 netif_tx_wake_queue(txq);
51b91468 8098 }
1da177e4 8099
cdd0db05 8100 mmiowb();
1da177e4 8101 return NETDEV_TX_OK;
f4188d8a
AD		 8102
8103dma_error:
ba1142e4 8104 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
432aa7ed 8105 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
48855432 8106drop:
497a27b9 8107 dev_kfree_skb_any(skb);
48855432
ED		 8108drop_nofree:
8109 tp->tx_dropped++;
f4188d8a 8110 return NETDEV_TX_OK;
1da177e4
LT		 8111}
8112
6e01b20b
MC		 8113static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8114{
8115 if (enable) {
8116 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8117 MAC_MODE_PORT_MODE_MASK);
8118
8119 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8120
8121 if (!tg3_flag(tp, 5705_PLUS))
8122 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8123
8124 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8125 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8126 else
8127 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8128 } else {
8129 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8130
8131 if (tg3_flag(tp, 5705_PLUS) ||
8132 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
4153577a 8133 tg3_asic_rev(tp) == ASIC_REV_5700)
6e01b20b
MC		 8134 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8135 }
8136
8137 tw32(MAC_MODE, tp->mac_mode);
8138 udelay(40);
8139}
8140
941ec90f 8141static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
5e5a7f37 8142{
941ec90f 8143 u32 val, bmcr, mac_mode, ptest = 0;
5e5a7f37
MC		 8144
8145 tg3_phy_toggle_apd(tp, false);
953c96e0 8146 tg3_phy_toggle_automdix(tp, false);
5e5a7f37 8147
941ec90f
MC		 8148 if (extlpbk && tg3_phy_set_extloopbk(tp))
8149 return -EIO;
8150
8151 bmcr = BMCR_FULLDPLX;
5e5a7f37
MC		 8152 switch (speed) {
8153 case SPEED_10:
8154 break;
8155 case SPEED_100:
8156 bmcr |= BMCR_SPEED100;
8157 break;
8158 case SPEED_1000:
8159 default:
8160 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8161 speed = SPEED_100;
8162 bmcr |= BMCR_SPEED100;
8163 } else {
8164 speed = SPEED_1000;
8165 bmcr |= BMCR_SPEED1000;
8166 }
8167 }
8168
941ec90f
MC		 8169 if (extlpbk) {
8170 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8171 tg3_readphy(tp, MII_CTRL1000, &val);
8172 val |= CTL1000_AS_MASTER |
8173 CTL1000_ENABLE_MASTER;
8174 tg3_writephy(tp, MII_CTRL1000, val);
8175 } else {
8176 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8177 MII_TG3_FET_PTEST_TRIM_2;
8178 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8179 }
8180 } else
8181 bmcr |= BMCR_LOOPBACK;
8182
5e5a7f37
MC		 8183 tg3_writephy(tp, MII_BMCR, bmcr);
8184
8185 /* The write needs to be flushed for the FETs */
8186 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8187 tg3_readphy(tp, MII_BMCR, &bmcr);
8188
8189 udelay(40);
8190
8191 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a 8192 tg3_asic_rev(tp) == ASIC_REV_5785) {
941ec90f 8193 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
5e5a7f37
MC		 8194 MII_TG3_FET_PTEST_FRC_TX_LINK |
8195 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8196
8197 /* The write needs to be flushed for the AC131 */
8198 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8199 }
8200
8201 /* Reset to prevent losing 1st rx packet intermittently */
8202 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8203 tg3_flag(tp, 5780_CLASS)) {
8204 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8205 udelay(10);
8206 tw32_f(MAC_RX_MODE, tp->rx_mode);
8207 }
8208
8209 mac_mode = tp->mac_mode &
8210 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8211 if (speed == SPEED_1000)
8212 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8213 else
8214 mac_mode |= MAC_MODE_PORT_MODE_MII;
8215
4153577a 8216 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5e5a7f37
MC		 8217 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8218
8219 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8220 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8221 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8222 mac_mode |= MAC_MODE_LINK_POLARITY;
8223
8224 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8225 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8226 }
8227
8228 tw32(MAC_MODE, mac_mode);
8229 udelay(40);
941ec90f
MC		 8230
8231 return 0;
5e5a7f37
MC		 8232}
8233
c8f44aff 8234static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
06c03c02
MB		 8235{
8236 struct tg3 *tp = netdev_priv(dev);
8237
8238 if (features & NETIF_F_LOOPBACK) {
8239 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8240 return;
8241
06c03c02 8242 spin_lock_bh(&tp->lock);
6e01b20b 8243 tg3_mac_loopback(tp, true);
06c03c02
MB		 8244 netif_carrier_on(tp->dev);
8245 spin_unlock_bh(&tp->lock);
8246 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8247 } else {
8248 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8249 return;
8250
06c03c02 8251 spin_lock_bh(&tp->lock);
6e01b20b 8252 tg3_mac_loopback(tp, false);
06c03c02 8253 /* Force link status check */
953c96e0 8254 tg3_setup_phy(tp, true);
06c03c02
MB		 8255 spin_unlock_bh(&tp->lock);
8256 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8257 }
8258}
8259
c8f44aff
MM		 8260static netdev_features_t tg3_fix_features(struct net_device *dev,
8261 netdev_features_t features)
dc668910
MM		 8262{
8263 struct tg3 *tp = netdev_priv(dev);
8264
63c3a66f 8265 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
dc668910
MM		 8266 features &= ~NETIF_F_ALL_TSO;
8267
8268 return features;
8269}
8270
c8f44aff 8271static int tg3_set_features(struct net_device *dev, netdev_features_t features)
06c03c02 8272{
c8f44aff 8273 netdev_features_t changed = dev->features ^ features;
06c03c02
MB		 8274
8275 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8276 tg3_set_loopback(dev, features);
8277
8278 return 0;
8279}
8280
21f581a5
MC		 8281static void tg3_rx_prodring_free(struct tg3 *tp,
8282 struct tg3_rx_prodring_set *tpr)
1da177e4 8283{
1da177e4
LT		 8284 int i;
8285
8fea32b9 8286 if (tpr != &tp->napi[0].prodring) {
b196c7e4 8287 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
2c49a44d 8288 i = (i + 1) & tp->rx_std_ring_mask)
9205fd9c 8289 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
b196c7e4
MC		 8290 tp->rx_pkt_map_sz);
8291
63c3a66f 8292 if (tg3_flag(tp, JUMBO_CAPABLE)) {
b196c7e4
MC		 8293 for (i = tpr->rx_jmb_cons_idx;
8294 i != tpr->rx_jmb_prod_idx;
2c49a44d 8295 i = (i + 1) & tp->rx_jmb_ring_mask) {
9205fd9c 8296 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
b196c7e4
MC		 8297 TG3_RX_JMB_MAP_SZ);
8298 }
8299 }
8300
2b2cdb65 8301 return;
b196c7e4 8302 }
1da177e4 8303
2c49a44d 8304 for (i = 0; i <= tp->rx_std_ring_mask; i++)
9205fd9c 8305 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
2b2cdb65 8306 tp->rx_pkt_map_sz);
1da177e4 8307
63c3a66f 8308 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8309 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
9205fd9c 8310 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
2b2cdb65 8311 TG3_RX_JMB_MAP_SZ);
1da177e4
LT		 8312 }
8313}
8314
c6cdf436 8315/* Initialize rx rings for packet processing.
1da177e4
LT		 8316 *
8317 * The chip has been shut down and the driver detached from
8318 * the networking, so no interrupts or new tx packets will
8319 * end up in the driver. tp->{tx,}lock are held and thus
8320 * we may not sleep.
8321 */
21f581a5
MC		 8322static int tg3_rx_prodring_alloc(struct tg3 *tp,
8323 struct tg3_rx_prodring_set *tpr)
1da177e4 8324{
287be12e 8325 u32 i, rx_pkt_dma_sz;
1da177e4 8326
b196c7e4
MC		 8327 tpr->rx_std_cons_idx = 0;
8328 tpr->rx_std_prod_idx = 0;
8329 tpr->rx_jmb_cons_idx = 0;
8330 tpr->rx_jmb_prod_idx = 0;
8331
8fea32b9 8332 if (tpr != &tp->napi[0].prodring) {
2c49a44d
MC		 8333 memset(&tpr->rx_std_buffers[0], 0,
8334 TG3_RX_STD_BUFF_RING_SIZE(tp));
48035728 8335 if (tpr->rx_jmb_buffers)
2b2cdb65 8336 memset(&tpr->rx_jmb_buffers[0], 0,
2c49a44d 8337 TG3_RX_JMB_BUFF_RING_SIZE(tp));
2b2cdb65
MC		 8338 goto done;
8339 }
8340
1da177e4 8341 /* Zero out all descriptors. */
2c49a44d 8342 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
1da177e4 8343
287be12e 8344 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
63c3a66f 8345 if (tg3_flag(tp, 5780_CLASS) &&
287be12e
MC		 8346 tp->dev->mtu > ETH_DATA_LEN)
8347 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8348 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7e72aad4 8349
1da177e4
LT		 8350 /* Initialize invariants of the rings, we only set this
8351 * stuff once. This works because the card does not
8352 * write into the rx buffer posting rings.
8353 */
2c49a44d 8354 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
1da177e4
LT		 8355 struct tg3_rx_buffer_desc *rxd;
8356
21f581a5 8357 rxd = &tpr->rx_std[i];
287be12e 8358 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
1da177e4
LT		 8359 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8360 rxd->opaque = (RXD_OPAQUE_RING_STD |
8361 (i << RXD_OPAQUE_INDEX_SHIFT));
8362 }
8363
1da177e4
LT		 8364 /* Now allocate fresh SKBs for each rx ring. */
8365 for (i = 0; i < tp->rx_pending; i++) {
8d4057a9
ED		 8366 unsigned int frag_size;
8367
8368 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8369 &frag_size) < 0) {
5129c3a3
MC		 8370 netdev_warn(tp->dev,
8371 "Using a smaller RX standard ring. Only "
8372 "%d out of %d buffers were allocated "
8373 "successfully\n", i, tp->rx_pending);
32d8c572 8374 if (i == 0)
cf7a7298 8375 goto initfail;
32d8c572 8376 tp->rx_pending = i;
1da177e4 8377 break;
32d8c572 8378 }
1da177e4
LT		 8379 }
8380
63c3a66f 8381 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
cf7a7298
MC		 8382 goto done;
8383
2c49a44d 8384 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
cf7a7298 8385
63c3a66f 8386 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
0d86df80 8387 goto done;
cf7a7298 8388
2c49a44d 8389 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
0d86df80
MC		 8390 struct tg3_rx_buffer_desc *rxd;
8391
8392 rxd = &tpr->rx_jmb[i].std;
8393 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8394 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8395 RXD_FLAG_JUMBO;
8396 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8397 (i << RXD_OPAQUE_INDEX_SHIFT));
8398 }
8399
8400 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8d4057a9
ED		 8401 unsigned int frag_size;
8402
8403 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8404 &frag_size) < 0) {
5129c3a3
MC		 8405 netdev_warn(tp->dev,
8406 "Using a smaller RX jumbo ring. Only %d "
8407 "out of %d buffers were allocated "
8408 "successfully\n", i, tp->rx_jumbo_pending);
0d86df80
MC		 8409 if (i == 0)
8410 goto initfail;
8411 tp->rx_jumbo_pending = i;
8412 break;
1da177e4
LT		 8413 }
8414 }
cf7a7298
MC		 8415
8416done:
32d8c572 8417 return 0;
cf7a7298
MC		 8418
8419initfail:
21f581a5 8420 tg3_rx_prodring_free(tp, tpr);
cf7a7298 8421 return -ENOMEM;
1da177e4
LT		 8422}
8423
21f581a5
MC		 8424static void tg3_rx_prodring_fini(struct tg3 *tp,
8425 struct tg3_rx_prodring_set *tpr)
1da177e4 8426{
21f581a5
MC		 8427 kfree(tpr->rx_std_buffers);
8428 tpr->rx_std_buffers = NULL;
8429 kfree(tpr->rx_jmb_buffers);
8430 tpr->rx_jmb_buffers = NULL;
8431 if (tpr->rx_std) {
4bae65c8
MC		 8432 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8433 tpr->rx_std, tpr->rx_std_mapping);
21f581a5 8434 tpr->rx_std = NULL;
1da177e4 8435 }
21f581a5 8436 if (tpr->rx_jmb) {
4bae65c8
MC		 8437 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8438 tpr->rx_jmb, tpr->rx_jmb_mapping);
21f581a5 8439 tpr->rx_jmb = NULL;
1da177e4 8440 }
cf7a7298
MC		 8441}
8442
21f581a5
MC		 8443static int tg3_rx_prodring_init(struct tg3 *tp,
8444 struct tg3_rx_prodring_set *tpr)
cf7a7298 8445{
2c49a44d
MC		 8446 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8447 GFP_KERNEL);
21f581a5 8448 if (!tpr->rx_std_buffers)
cf7a7298
MC		 8449 return -ENOMEM;
8450
4bae65c8
MC		 8451 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8452 TG3_RX_STD_RING_BYTES(tp),
8453 &tpr->rx_std_mapping,
8454 GFP_KERNEL);
21f581a5 8455 if (!tpr->rx_std)
cf7a7298
MC		 8456 goto err_out;
8457
63c3a66f 8458 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
2c49a44d 8459 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
21f581a5
MC		 8460 GFP_KERNEL);
8461 if (!tpr->rx_jmb_buffers)
cf7a7298
MC		 8462 goto err_out;
8463
4bae65c8
MC		 8464 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8465 TG3_RX_JMB_RING_BYTES(tp),
8466 &tpr->rx_jmb_mapping,
8467 GFP_KERNEL);
21f581a5 8468 if (!tpr->rx_jmb)
cf7a7298
MC		 8469 goto err_out;
8470 }
8471
8472 return 0;
8473
8474err_out:
21f581a5 8475 tg3_rx_prodring_fini(tp, tpr);
cf7a7298
MC		 8476 return -ENOMEM;
8477}
8478
8479/* Free up pending packets in all rx/tx rings.
8480 *
8481 * The chip has been shut down and the driver detached from
8482 * the networking, so no interrupts or new tx packets will
8483 * end up in the driver. tp->{tx,}lock is not held and we are not
8484 * in an interrupt context and thus may sleep.
8485 */
8486static void tg3_free_rings(struct tg3 *tp)
8487{
f77a6a8e 8488 int i, j;
cf7a7298 8489
f77a6a8e
MC		 8490 for (j = 0; j < tp->irq_cnt; j++) {
8491 struct tg3_napi *tnapi = &tp->napi[j];
cf7a7298 8492
8fea32b9 8493 tg3_rx_prodring_free(tp, &tnapi->prodring);
b28f6428 8494
0c1d0e2b
MC		 8495 if (!tnapi->tx_buffers)
8496 continue;
8497
0d681b27
MC		 8498 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8499 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
cf7a7298 8500
0d681b27 8501 if (!skb)
f77a6a8e 8502 continue;
cf7a7298 8503
ba1142e4
MC		 8504 tg3_tx_skb_unmap(tnapi, i,
8505 skb_shinfo(skb)->nr_frags - 1);
f77a6a8e
MC		 8506
8507 dev_kfree_skb_any(skb);
8508 }
5cb917bc 8509 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
2b2cdb65 8510 }
cf7a7298
MC		 8511}
8512
8513/* Initialize tx/rx rings for packet processing.
8514 *
8515 * The chip has been shut down and the driver detached from
8516 * the networking, so no interrupts or new tx packets will
8517 * end up in the driver. tp->{tx,}lock are held and thus
8518 * we may not sleep.
8519 */
8520static int tg3_init_rings(struct tg3 *tp)
8521{
f77a6a8e 8522 int i;
72334482 8523
cf7a7298
MC		 8524 /* Free up all the SKBs. */
8525 tg3_free_rings(tp);
8526
f77a6a8e
MC		 8527 for (i = 0; i < tp->irq_cnt; i++) {
8528 struct tg3_napi *tnapi = &tp->napi[i];
8529
8530 tnapi->last_tag = 0;
8531 tnapi->last_irq_tag = 0;
8532 tnapi->hw_status->status = 0;
8533 tnapi->hw_status->status_tag = 0;
8534 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
cf7a7298 8535
f77a6a8e
MC		 8536 tnapi->tx_prod = 0;
8537 tnapi->tx_cons = 0;
0c1d0e2b
MC		 8538 if (tnapi->tx_ring)
8539 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
f77a6a8e
MC		 8540
8541 tnapi->rx_rcb_ptr = 0;
0c1d0e2b
MC		 8542 if (tnapi->rx_rcb)
8543 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
2b2cdb65 8544
8fea32b9 8545 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
e4af1af9 8546 tg3_free_rings(tp);
2b2cdb65 8547 return -ENOMEM;
e4af1af9 8548 }
f77a6a8e 8549 }
72334482 8550
2b2cdb65 8551 return 0;
cf7a7298
MC		 8552}
8553
49a359e3 8554static void tg3_mem_tx_release(struct tg3 *tp)
cf7a7298 8555{
f77a6a8e 8556 int i;
898a56f8 8557
49a359e3 8558 for (i = 0; i < tp->irq_max; i++) {
f77a6a8e
MC		 8559 struct tg3_napi *tnapi = &tp->napi[i];
8560
8561 if (tnapi->tx_ring) {
4bae65c8 8562 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
f77a6a8e
MC		 8563 tnapi->tx_ring, tnapi->tx_desc_mapping);
8564 tnapi->tx_ring = NULL;
8565 }
8566
8567 kfree(tnapi->tx_buffers);
8568 tnapi->tx_buffers = NULL;
49a359e3
MC		 8569 }
8570}
f77a6a8e 8571
49a359e3
MC		 8572static int tg3_mem_tx_acquire(struct tg3 *tp)
8573{
8574 int i;
8575 struct tg3_napi *tnapi = &tp->napi[0];
8576
8577 /* If multivector TSS is enabled, vector 0 does not handle
8578 * tx interrupts. Don't allocate any resources for it.
8579 */
8580 if (tg3_flag(tp, ENABLE_TSS))
8581 tnapi++;
8582
8583 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8584 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8585 TG3_TX_RING_SIZE, GFP_KERNEL);
8586 if (!tnapi->tx_buffers)
8587 goto err_out;
8588
8589 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8590 TG3_TX_RING_BYTES,
8591 &tnapi->tx_desc_mapping,
8592 GFP_KERNEL);
8593 if (!tnapi->tx_ring)
8594 goto err_out;
8595 }
8596
8597 return 0;
8598
8599err_out:
8600 tg3_mem_tx_release(tp);
8601 return -ENOMEM;
8602}
8603
8604static void tg3_mem_rx_release(struct tg3 *tp)
8605{
8606 int i;
8607
8608 for (i = 0; i < tp->irq_max; i++) {
8609 struct tg3_napi *tnapi = &tp->napi[i];
f77a6a8e 8610
8fea32b9
MC		 8611 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8612
49a359e3
MC		 8613 if (!tnapi->rx_rcb)
8614 continue;
8615
8616 dma_free_coherent(&tp->pdev->dev,
8617 TG3_RX_RCB_RING_BYTES(tp),
8618 tnapi->rx_rcb,
8619 tnapi->rx_rcb_mapping);
8620 tnapi->rx_rcb = NULL;
8621 }
8622}
8623
8624static int tg3_mem_rx_acquire(struct tg3 *tp)
8625{
8626 unsigned int i, limit;
8627
8628 limit = tp->rxq_cnt;
8629
8630 /* If RSS is enabled, we need a (dummy) producer ring
8631 * set on vector zero. This is the true hw prodring.
8632 */
8633 if (tg3_flag(tp, ENABLE_RSS))
8634 limit++;
8635
8636 for (i = 0; i < limit; i++) {
8637 struct tg3_napi *tnapi = &tp->napi[i];
8638
8639 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8640 goto err_out;
8641
8642 /* If multivector RSS is enabled, vector 0
8643 * does not handle rx or tx interrupts.
8644 * Don't allocate any resources for it.
8645 */
8646 if (!i && tg3_flag(tp, ENABLE_RSS))
8647 continue;
8648
ede23fa8
JP		 8649 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8650 TG3_RX_RCB_RING_BYTES(tp),
8651 &tnapi->rx_rcb_mapping,
8652 GFP_KERNEL);
49a359e3
MC		 8653 if (!tnapi->rx_rcb)
8654 goto err_out;
49a359e3
MC		 8655 }
8656
8657 return 0;
8658
8659err_out:
8660 tg3_mem_rx_release(tp);
8661 return -ENOMEM;
8662}
8663
8664/*
8665 * Must not be invoked with interrupt sources disabled and
8666 * the hardware shutdown down.
8667 */
8668static void tg3_free_consistent(struct tg3 *tp)
8669{
8670 int i;
8671
8672 for (i = 0; i < tp->irq_cnt; i++) {
8673 struct tg3_napi *tnapi = &tp->napi[i];
8674
f77a6a8e 8675 if (tnapi->hw_status) {
4bae65c8
MC		 8676 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8677 tnapi->hw_status,
8678 tnapi->status_mapping);
f77a6a8e
MC		 8679 tnapi->hw_status = NULL;
8680 }
1da177e4 8681 }
f77a6a8e 8682
49a359e3
MC		 8683 tg3_mem_rx_release(tp);
8684 tg3_mem_tx_release(tp);
8685
1da177e4 8686 if (tp->hw_stats) {
4bae65c8
MC		 8687 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8688 tp->hw_stats, tp->stats_mapping);
1da177e4
LT		 8689 tp->hw_stats = NULL;
8690 }
8691}
8692
8693/*
8694 * Must not be invoked with interrupt sources disabled and
8695 * the hardware shutdown down. Can sleep.
8696 */
8697static int tg3_alloc_consistent(struct tg3 *tp)
8698{
f77a6a8e 8699 int i;
898a56f8 8700
ede23fa8
JP		 8701 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8702 sizeof(struct tg3_hw_stats),
8703 &tp->stats_mapping, GFP_KERNEL);
f77a6a8e 8704 if (!tp->hw_stats)
1da177e4
LT		 8705 goto err_out;
8706
f77a6a8e
MC		 8707 for (i = 0; i < tp->irq_cnt; i++) {
8708 struct tg3_napi *tnapi = &tp->napi[i];
8d9d7cfc 8709 struct tg3_hw_status *sblk;
1da177e4 8710
ede23fa8
JP		 8711 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8712 TG3_HW_STATUS_SIZE,
8713 &tnapi->status_mapping,
8714 GFP_KERNEL);
f77a6a8e
MC		 8715 if (!tnapi->hw_status)
8716 goto err_out;
898a56f8 8717
8d9d7cfc
MC		 8718 sblk = tnapi->hw_status;
8719
49a359e3 8720 if (tg3_flag(tp, ENABLE_RSS)) {
86449944 8721 u16 *prodptr = NULL;
8fea32b9 8722
49a359e3
MC		 8723 /*
8724 * When RSS is enabled, the status block format changes
8725 * slightly. The "rx_jumbo_consumer", "reserved",
8726 * and "rx_mini_consumer" members get mapped to the
8727 * other three rx return ring producer indexes.
8728 */
8729 switch (i) {
8730 case 1:
8731 prodptr = &sblk->idx[0].rx_producer;
8732 break;
8733 case 2:
8734 prodptr = &sblk->rx_jumbo_consumer;
8735 break;
8736 case 3:
8737 prodptr = &sblk->reserved;
8738 break;
8739 case 4:
8740 prodptr = &sblk->rx_mini_consumer;
f891ea16
MC		 8741 break;
8742 }
49a359e3
MC		 8743 tnapi->rx_rcb_prod_idx = prodptr;
8744 } else {
8d9d7cfc 8745 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8d9d7cfc 8746 }
f77a6a8e 8747 }
1da177e4 8748
49a359e3
MC		 8749 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8750 goto err_out;
8751
1da177e4
LT		 8752 return 0;
8753
8754err_out:
8755 tg3_free_consistent(tp);
8756 return -ENOMEM;
8757}
8758
8759#define MAX_WAIT_CNT 1000
8760
8761/* To stop a block, clear the enable bit and poll till it
8762 * clears. tp->lock is held.
8763 */
953c96e0 8764static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
1da177e4
LT		 8765{
8766 unsigned int i;
8767 u32 val;
8768
63c3a66f 8769 if (tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 8770 switch (ofs) {
8771 case RCVLSC_MODE:
8772 case DMAC_MODE:
8773 case MBFREE_MODE:
8774 case BUFMGR_MODE:
8775 case MEMARB_MODE:
8776 /* We can't enable/disable these bits of the
8777 * 5705/5750, just say success.
8778 */
8779 return 0;
8780
8781 default:
8782 break;
855e1111 8783 }
1da177e4
LT		 8784 }
8785
8786 val = tr32(ofs);
8787 val &= ~enable_bit;
8788 tw32_f(ofs, val);
8789
8790 for (i = 0; i < MAX_WAIT_CNT; i++) {
6d446ec3
GS		 8791 if (pci_channel_offline(tp->pdev)) {
8792 dev_err(&tp->pdev->dev,
8793 "tg3_stop_block device offline, "
8794 "ofs=%lx enable_bit=%x\n",
8795 ofs, enable_bit);
8796 return -ENODEV;
8797 }
8798
1da177e4
LT		 8799 udelay(100);
8800 val = tr32(ofs);
8801 if ((val & enable_bit) == 0)
8802 break;
8803 }
8804
b3b7d6be 8805 if (i == MAX_WAIT_CNT && !silent) {
2445e461
MC		 8806 dev_err(&tp->pdev->dev,
8807 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8808 ofs, enable_bit);
1da177e4
LT		 8809 return -ENODEV;
8810 }
8811
8812 return 0;
8813}
8814
8815/* tp->lock is held. */
953c96e0 8816static int tg3_abort_hw(struct tg3 *tp, bool silent)
1da177e4
LT		 8817{
8818 int i, err;
8819
8820 tg3_disable_ints(tp);
8821
6d446ec3
GS		 8822 if (pci_channel_offline(tp->pdev)) {
8823 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8824 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8825 err = -ENODEV;
8826 goto err_no_dev;
8827 }
8828
1da177e4
LT		 8829 tp->rx_mode &= ~RX_MODE_ENABLE;
8830 tw32_f(MAC_RX_MODE, tp->rx_mode);
8831 udelay(10);
8832
b3b7d6be
DM		 8833 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8834 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8835 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8836 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8837 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8838 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8839
8840 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8841 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8842 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8843 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8844 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8845 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8846 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 8847
8848 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8849 tw32_f(MAC_MODE, tp->mac_mode);
8850 udelay(40);
8851
8852 tp->tx_mode &= ~TX_MODE_ENABLE;
8853 tw32_f(MAC_TX_MODE, tp->tx_mode);
8854
8855 for (i = 0; i < MAX_WAIT_CNT; i++) {
8856 udelay(100);
8857 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8858 break;
8859 }
8860 if (i >= MAX_WAIT_CNT) {
ab96b241
MC		 8861 dev_err(&tp->pdev->dev,
8862 "%s timed out, TX_MODE_ENABLE will not clear "
8863 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
e6de8ad1 8864 err |= -ENODEV;
1da177e4
LT		 8865 }
8866
e6de8ad1 8867 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 8868 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8869 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 8870
8871 tw32(FTQ_RESET, 0xffffffff);
8872 tw32(FTQ_RESET, 0x00000000);
8873
b3b7d6be
DM		 8874 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8875 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4 8876
6d446ec3 8877err_no_dev:
f77a6a8e
MC		 8878 for (i = 0; i < tp->irq_cnt; i++) {
8879 struct tg3_napi *tnapi = &tp->napi[i];
8880 if (tnapi->hw_status)
8881 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8882 }
1da177e4 8883
1da177e4
LT		 8884 return err;
8885}
8886
ee6a99b5
MC		 8887/* Save PCI command register before chip reset */
8888static void tg3_save_pci_state(struct tg3 *tp)
8889{
8a6eac90 8890 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
ee6a99b5
MC		 8891}
8892
8893/* Restore PCI state after chip reset */
8894static void tg3_restore_pci_state(struct tg3 *tp)
8895{
8896 u32 val;
8897
8898 /* Re-enable indirect register accesses. */
8899 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8900 tp->misc_host_ctrl);
8901
8902 /* Set MAX PCI retry to zero. */
8903 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4153577a 8904 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 8905 tg3_flag(tp, PCIX_MODE))
ee6a99b5 8906 val |= PCISTATE_RETRY_SAME_DMA;
0d3031d9 8907 /* Allow reads and writes to the APE register and memory space. */
63c3a66f 8908 if (tg3_flag(tp, ENABLE_APE))
0d3031d9 8909 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 8910 PCISTATE_ALLOW_APE_SHMEM_WR |
8911 PCISTATE_ALLOW_APE_PSPACE_WR;
ee6a99b5
MC		 8912 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8913
8a6eac90 8914 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
ee6a99b5 8915
2c55a3d0
MC		 8916 if (!tg3_flag(tp, PCI_EXPRESS)) {
8917 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8918 tp->pci_cacheline_sz);
8919 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8920 tp->pci_lat_timer);
114342f2 8921 }
5f5c51e3 8922
ee6a99b5 8923 /* Make sure PCI-X relaxed ordering bit is clear. */
63c3a66f 8924 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 8925 u16 pcix_cmd;
8926
8927 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8928 &pcix_cmd);
8929 pcix_cmd &= ~PCI_X_CMD_ERO;
8930 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8931 pcix_cmd);
8932 }
ee6a99b5 8933
63c3a66f 8934 if (tg3_flag(tp, 5780_CLASS)) {
ee6a99b5
MC		 8935
8936 /* Chip reset on 5780 will reset MSI enable bit,
8937 * so need to restore it.
8938 */
63c3a66f 8939 if (tg3_flag(tp, USING_MSI)) {
ee6a99b5
MC		 8940 u16 ctrl;
8941
8942 pci_read_config_word(tp->pdev,
8943 tp->msi_cap + PCI_MSI_FLAGS,
8944 &ctrl);
8945 pci_write_config_word(tp->pdev,
8946 tp->msi_cap + PCI_MSI_FLAGS,
8947 ctrl | PCI_MSI_FLAGS_ENABLE);
8948 val = tr32(MSGINT_MODE);
8949 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8950 }
8951 }
8952}
8953
f82995b6
NS		 8954static void tg3_override_clk(struct tg3 *tp)
8955{
8956 u32 val;
8957
8958 switch (tg3_asic_rev(tp)) {
8959 case ASIC_REV_5717:
8960 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8961 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8962 TG3_CPMU_MAC_ORIDE_ENABLE);
8963 break;
8964
8965 case ASIC_REV_5719:
8966 case ASIC_REV_5720:
8967 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8968 break;
8969
8970 default:
8971 return;
8972 }
8973}
8974
8975static void tg3_restore_clk(struct tg3 *tp)
8976{
8977 u32 val;
8978
8979 switch (tg3_asic_rev(tp)) {
8980 case ASIC_REV_5717:
8981 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8982 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
8983 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
8984 break;
8985
8986 case ASIC_REV_5719:
8987 case ASIC_REV_5720:
8988 val = tr32(TG3_CPMU_CLCK_ORIDE);
8989 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8990 break;
8991
8992 default:
8993 return;
8994 }
8995}
8996
1da177e4
LT		 8997/* tp->lock is held. */
8998static int tg3_chip_reset(struct tg3 *tp)
8999{
9000 u32 val;
1ee582d8 9001 void (*write_op)(struct tg3 *, u32, u32);
4f125f42 9002 int i, err;
1da177e4 9003
8496e85c
RW		 9004 if (!pci_device_is_present(tp->pdev))
9005 return -ENODEV;
9006
f49639e6
DM		 9007 tg3_nvram_lock(tp);
9008
77b483f1
MC		 9009 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9010
f49639e6
DM		 9011 /* No matching tg3_nvram_unlock() after this because
9012 * chip reset below will undo the nvram lock.
9013 */
9014 tp->nvram_lock_cnt = 0;
1da177e4 9015
ee6a99b5
MC		 9016 /* GRC_MISC_CFG core clock reset will clear the memory
9017 * enable bit in PCI register 4 and the MSI enable bit
9018 * on some chips, so we save relevant registers here.
9019 */
9020 tg3_save_pci_state(tp);
9021
4153577a 9022 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
63c3a66f 9023 tg3_flag(tp, 5755_PLUS))
d9ab5ad1
MC		 9024 tw32(GRC_FASTBOOT_PC, 0);
9025
1da177e4
LT		 9026 /*
9027 * We must avoid the readl() that normally takes place.
9028 * It locks machines, causes machine checks, and other
9029 * fun things. So, temporarily disable the 5701
9030 * hardware workaround, while we do the reset.
9031 */
1ee582d8
MC		 9032 write_op = tp->write32;
9033 if (write_op == tg3_write_flush_reg32)
9034 tp->write32 = tg3_write32;
1da177e4 9035
d18edcb2
MC		 9036 /* Prevent the irq handler from reading or writing PCI registers
9037 * during chip reset when the memory enable bit in the PCI command
9038 * register may be cleared. The chip does not generate interrupt
9039 * at this time, but the irq handler may still be called due to irq
9040 * sharing or irqpoll.
9041 */
63c3a66f 9042 tg3_flag_set(tp, CHIP_RESETTING);
f77a6a8e
MC		 9043 for (i = 0; i < tp->irq_cnt; i++) {
9044 struct tg3_napi *tnapi = &tp->napi[i];
9045 if (tnapi->hw_status) {
9046 tnapi->hw_status->status = 0;
9047 tnapi->hw_status->status_tag = 0;
9048 }
9049 tnapi->last_tag = 0;
9050 tnapi->last_irq_tag = 0;
b8fa2f3a 9051 }
d18edcb2 9052 smp_mb();
4f125f42
MC		 9053
9054 for (i = 0; i < tp->irq_cnt; i++)
9055 synchronize_irq(tp->napi[i].irq_vec);
d18edcb2 9056
4153577a 9057 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
255ca311
MC		 9058 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9059 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9060 }
9061
1da177e4
LT		 9062 /* do the reset */
9063 val = GRC_MISC_CFG_CORECLK_RESET;
9064
63c3a66f 9065 if (tg3_flag(tp, PCI_EXPRESS)) {
88075d91 9066 /* Force PCIe 1.0a mode */
4153577a 9067 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9068 !tg3_flag(tp, 57765_PLUS) &&
88075d91
MC		 9069 tr32(TG3_PCIE_PHY_TSTCTL) ==
9070 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9071 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9072
4153577a 9073 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
1da177e4
LT		 9074 tw32(GRC_MISC_CFG, (1 << 29));
9075 val |= (1 << 29);
9076 }
9077 }
9078
4153577a 9079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 9080 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9081 tw32(GRC_VCPU_EXT_CTRL,
9082 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9083 }
9084
f82995b6
NS		 9085 /* Set the clock to the highest frequency to avoid timeouts. With link
9086 * aware mode, the clock speed could be slow and bootcode does not
9087 * complete within the expected time. Override the clock to allow the
9088 * bootcode to finish sooner and then restore it.
9089 */
9090 tg3_override_clk(tp);
9091
f37500d3 9092 /* Manage gphy power for all CPMU absent PCIe devices. */
63c3a66f 9093 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
1da177e4 9094 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
f37500d3 9095
1da177e4
LT		 9096 tw32(GRC_MISC_CFG, val);
9097
1ee582d8
MC		 9098 /* restore 5701 hardware bug workaround write method */
9099 tp->write32 = write_op;
1da177e4
LT		 9100
9101 /* Unfortunately, we have to delay before the PCI read back.
9102 * Some 575X chips even will not respond to a PCI cfg access
9103 * when the reset command is given to the chip.
9104 *
9105 * How do these hardware designers expect things to work
9106 * properly if the PCI write is posted for a long period
9107 * of time? It is always necessary to have some method by
9108 * which a register read back can occur to push the write
9109 * out which does the reset.
9110 *
9111 * For most tg3 variants the trick below was working.
9112 * Ho hum...
9113 */
9114 udelay(120);
9115
9116 /* Flush PCI posted writes. The normal MMIO registers
9117 * are inaccessible at this time so this is the only
9118 * way to make this reliably (actually, this is no longer
9119 * the case, see above). I tried to use indirect
9120 * register read/write but this upset some 5701 variants.
9121 */
9122 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9123
9124 udelay(120);
9125
0f49bfbd 9126 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
e7126997
MC		 9127 u16 val16;
9128
4153577a 9129 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
86449944 9130 int j;
1da177e4
LT		 9131 u32 cfg_val;
9132
9133 /* Wait for link training to complete. */
86449944 9134 for (j = 0; j < 5000; j++)
1da177e4
LT		 9135 udelay(100);
9136
9137 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9138 pci_write_config_dword(tp->pdev, 0xc4,
9139 cfg_val | (1 << 15));
9140 }
5e7dfd0f 9141
e7126997 9142 /* Clear the "no snoop" and "relaxed ordering" bits. */
0f49bfbd 9143 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
e7126997
MC		 9144 /*
9145 * Older PCIe devices only support the 128 byte
9146 * MPS setting. Enforce the restriction.
5e7dfd0f 9147 */
63c3a66f 9148 if (!tg3_flag(tp, CPMU_PRESENT))
0f49bfbd
JL		 9149 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9150 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
5e7dfd0f 9151
5e7dfd0f 9152 /* Clear error status */
0f49bfbd 9153 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
5e7dfd0f
MC		 9154 PCI_EXP_DEVSTA_CED |
9155 PCI_EXP_DEVSTA_NFED |
9156 PCI_EXP_DEVSTA_FED |
9157 PCI_EXP_DEVSTA_URD);
1da177e4
LT		 9158 }
9159
ee6a99b5 9160 tg3_restore_pci_state(tp);
1da177e4 9161
63c3a66f
JP		 9162 tg3_flag_clear(tp, CHIP_RESETTING);
9163 tg3_flag_clear(tp, ERROR_PROCESSED);
d18edcb2 9164
ee6a99b5 9165 val = 0;
63c3a66f 9166 if (tg3_flag(tp, 5780_CLASS))
4cf78e4f 9167 val = tr32(MEMARB_MODE);
ee6a99b5 9168 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
1da177e4 9169
4153577a 9170 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
1da177e4
LT		 9171 tg3_stop_fw(tp);
9172 tw32(0x5000, 0x400);
9173 }
9174
7e6c63f0
HM		 9175 if (tg3_flag(tp, IS_SSB_CORE)) {
9176 /*
9177 * BCM4785: In order to avoid repercussions from using
9178 * potentially defective internal ROM, stop the Rx RISC CPU,
9179 * which is not required.
9180 */
9181 tg3_stop_fw(tp);
9182 tg3_halt_cpu(tp, RX_CPU_BASE);
9183 }
9184
fb03a43f
NS		 9185 err = tg3_poll_fw(tp);
9186 if (err)
9187 return err;
9188
1da177e4
LT		 9189 tw32(GRC_MODE, tp->grc_mode);
9190
4153577a 9191 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
ab0049b4 9192 val = tr32(0xc4);
1da177e4
LT		 9193
9194 tw32(0xc4, val | (1 << 15));
9195 }
9196
9197 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4153577a 9198 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4 9199 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4153577a 9200 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
1da177e4
LT		 9201 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9202 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9203 }
9204
f07e9af3 9205 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9e975cc2 9206 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
d2394e6b 9207 val = tp->mac_mode;
f07e9af3 9208 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9e975cc2 9209 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
d2394e6b 9210 val = tp->mac_mode;
1da177e4 9211 } else
d2394e6b
MC		 9212 val = 0;
9213
9214 tw32_f(MAC_MODE, val);
1da177e4
LT		 9215 udelay(40);
9216
77b483f1
MC		 9217 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9218
0a9140cf
MC		 9219 tg3_mdio_start(tp);
9220
63c3a66f 9221 if (tg3_flag(tp, PCI_EXPRESS) &&
4153577a
JP		 9222 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9223 tg3_asic_rev(tp) != ASIC_REV_5785 &&
63c3a66f 9224 !tg3_flag(tp, 57765_PLUS)) {
ab0049b4 9225 val = tr32(0x7c00);
1da177e4
LT		 9226
9227 tw32(0x7c00, val | (1 << 25));
9228 }
9229
f82995b6 9230 tg3_restore_clk(tp);
d78b59f5 9231
1da177e4 9232 /* Reprobe ASF enable state. */
63c3a66f 9233 tg3_flag_clear(tp, ENABLE_ASF);
942d1af0
NS		 9234 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9235 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9236
63c3a66f 9237 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
1da177e4
LT		 9238 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9239 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9240 u32 nic_cfg;
9241
9242 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9243 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f 9244 tg3_flag_set(tp, ENABLE_ASF);
4ba526ce 9245 tp->last_event_jiffies = jiffies;
63c3a66f
JP		 9246 if (tg3_flag(tp, 5750_PLUS))
9247 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
942d1af0
NS		 9248
9249 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9250 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9251 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9252 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9253 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
1da177e4
LT		 9254 }
9255 }
9256
9257 return 0;
9258}
9259
65ec698d
MC		 9260static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9261static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
e565eec3 9262static void __tg3_set_rx_mode(struct net_device *);
92feeabf 9263
1da177e4 9264/* tp->lock is held. */
953c96e0 9265static int tg3_halt(struct tg3 *tp, int kind, bool silent)
1da177e4
LT		 9266{
9267 int err;
9268
9269 tg3_stop_fw(tp);
9270
944d980e 9271 tg3_write_sig_pre_reset(tp, kind);
1da177e4 9272
b3b7d6be 9273 tg3_abort_hw(tp, silent);
1da177e4
LT		 9274 err = tg3_chip_reset(tp);
9275
953c96e0 9276 __tg3_set_mac_addr(tp, false);
daba2a63 9277
944d980e
MC		 9278 tg3_write_sig_legacy(tp, kind);
9279 tg3_write_sig_post_reset(tp, kind);
1da177e4 9280
92feeabf
MC		 9281 if (tp->hw_stats) {
9282 /* Save the stats across chip resets... */
b4017c53 9283 tg3_get_nstats(tp, &tp->net_stats_prev);
92feeabf
MC		 9284 tg3_get_estats(tp, &tp->estats_prev);
9285
9286 /* And make sure the next sample is new data */
9287 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9288 }
9289
4bc814ab 9290 return err;
1da177e4
LT		 9291}
9292
1da177e4
LT		 9293static int tg3_set_mac_addr(struct net_device *dev, void *p)
9294{
9295 struct tg3 *tp = netdev_priv(dev);
9296 struct sockaddr *addr = p;
953c96e0
JP		 9297 int err = 0;
9298 bool skip_mac_1 = false;
1da177e4 9299
f9804ddb 9300 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 9301 return -EADDRNOTAVAIL;
f9804ddb 9302
1da177e4
LT		 9303 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9304
e75f7c90
MC		 9305 if (!netif_running(dev))
9306 return 0;
9307
63c3a66f 9308 if (tg3_flag(tp, ENABLE_ASF)) {
986e0aeb 9309 u32 addr0_high, addr0_low, addr1_high, addr1_low;
58712ef9 9310
986e0aeb
MC		 9311 addr0_high = tr32(MAC_ADDR_0_HIGH);
9312 addr0_low = tr32(MAC_ADDR_0_LOW);
9313 addr1_high = tr32(MAC_ADDR_1_HIGH);
9314 addr1_low = tr32(MAC_ADDR_1_LOW);
9315
9316 /* Skip MAC addr 1 if ASF is using it. */
9317 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9318 !(addr1_high == 0 && addr1_low == 0))
953c96e0 9319 skip_mac_1 = true;
58712ef9 9320 }
986e0aeb
MC		 9321 spin_lock_bh(&tp->lock);
9322 __tg3_set_mac_addr(tp, skip_mac_1);
e565eec3 9323 __tg3_set_rx_mode(dev);
986e0aeb 9324 spin_unlock_bh(&tp->lock);
1da177e4 9325
b9ec6c1b 9326 return err;
1da177e4
LT		 9327}
9328
9329/* tp->lock is held. */
9330static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9331 dma_addr_t mapping, u32 maxlen_flags,
9332 u32 nic_addr)
9333{
9334 tg3_write_mem(tp,
9335 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9336 ((u64) mapping >> 32));
9337 tg3_write_mem(tp,
9338 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9339 ((u64) mapping & 0xffffffff));
9340 tg3_write_mem(tp,
9341 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9342 maxlen_flags);
9343
63c3a66f 9344 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 9345 tg3_write_mem(tp,
9346 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9347 nic_addr);
9348}
9349
a489b6d9
MC		 9350
9351static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d 9352{
a489b6d9 9353 int i = 0;
b6080e12 9354
63c3a66f 9355 if (!tg3_flag(tp, ENABLE_TSS)) {
b6080e12
MC		 9356 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9357 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9358 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
b6080e12
MC		 9359 } else {
9360 tw32(HOSTCC_TXCOL_TICKS, 0);
9361 tw32(HOSTCC_TXMAX_FRAMES, 0);
9362 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
a489b6d9
MC		 9363
9364 for (; i < tp->txq_cnt; i++) {
9365 u32 reg;
9366
9367 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9368 tw32(reg, ec->tx_coalesce_usecs);
9369 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9370 tw32(reg, ec->tx_max_coalesced_frames);
9371 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9372 tw32(reg, ec->tx_max_coalesced_frames_irq);
9373 }
19cfaecc 9374 }
b6080e12 9375
a489b6d9
MC		 9376 for (; i < tp->irq_max - 1; i++) {
9377 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9378 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9379 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9380 }
9381}
9382
9383static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9384{
9385 int i = 0;
9386 u32 limit = tp->rxq_cnt;
9387
63c3a66f 9388 if (!tg3_flag(tp, ENABLE_RSS)) {
19cfaecc
MC		 9389 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9390 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9391 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
a489b6d9 9392 limit--;
19cfaecc 9393 } else {
b6080e12
MC		 9394 tw32(HOSTCC_RXCOL_TICKS, 0);
9395 tw32(HOSTCC_RXMAX_FRAMES, 0);
9396 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
15f9850d 9397 }
b6080e12 9398
a489b6d9 9399 for (; i < limit; i++) {
b6080e12
MC		 9400 u32 reg;
9401
9402 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9403 tw32(reg, ec->rx_coalesce_usecs);
b6080e12
MC		 9404 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9405 tw32(reg, ec->rx_max_coalesced_frames);
b6080e12
MC		 9406 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9407 tw32(reg, ec->rx_max_coalesced_frames_irq);
b6080e12
MC		 9408 }
9409
9410 for (; i < tp->irq_max - 1; i++) {
9411 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
b6080e12 9412 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
b6080e12 9413 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
a489b6d9
MC		 9414 }
9415}
19cfaecc 9416
a489b6d9
MC		 9417static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9418{
9419 tg3_coal_tx_init(tp, ec);
9420 tg3_coal_rx_init(tp, ec);
9421
9422 if (!tg3_flag(tp, 5705_PLUS)) {
9423 u32 val = ec->stats_block_coalesce_usecs;
9424
9425 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9426 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9427
f4a46d1f 9428 if (!tp->link_up)
a489b6d9
MC		 9429 val = 0;
9430
9431 tw32(HOSTCC_STAT_COAL_TICKS, val);
b6080e12 9432 }
15f9850d 9433}
1da177e4 9434
328947ff
NS		 9435/* tp->lock is held. */
9436static void tg3_tx_rcbs_disable(struct tg3 *tp)
9437{
9438 u32 txrcb, limit;
9439
9440 /* Disable all transmit rings but the first. */
9441 if (!tg3_flag(tp, 5705_PLUS))
9442 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9443 else if (tg3_flag(tp, 5717_PLUS))
9444 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9445 else if (tg3_flag(tp, 57765_CLASS) ||
9446 tg3_asic_rev(tp) == ASIC_REV_5762)
9447 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9448 else
9449 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9450
9451 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9452 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9453 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9454 BDINFO_FLAGS_DISABLED);
9455}
9456
32ba19ef
NS		 9457/* tp->lock is held. */
9458static void tg3_tx_rcbs_init(struct tg3 *tp)
9459{
9460 int i = 0;
9461 u32 txrcb = NIC_SRAM_SEND_RCB;
9462
9463 if (tg3_flag(tp, ENABLE_TSS))
9464 i++;
9465
9466 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9467 struct tg3_napi *tnapi = &tp->napi[i];
9468
9469 if (!tnapi->tx_ring)
9470 continue;
9471
9472 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9473 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9474 NIC_SRAM_TX_BUFFER_DESC);
9475 }
9476}
9477
328947ff
NS		 9478/* tp->lock is held. */
9479static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9480{
9481 u32 rxrcb, limit;
9482
9483 /* Disable all receive return rings but the first. */
9484 if (tg3_flag(tp, 5717_PLUS))
9485 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9486 else if (!tg3_flag(tp, 5705_PLUS))
9487 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9488 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9489 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9490 tg3_flag(tp, 57765_CLASS))
9491 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9492 else
9493 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9494
9495 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9496 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9497 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9498 BDINFO_FLAGS_DISABLED);
9499}
9500
32ba19ef
NS		 9501/* tp->lock is held. */
9502static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9503{
9504 int i = 0;
9505 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9506
9507 if (tg3_flag(tp, ENABLE_RSS))
9508 i++;
9509
9510 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9511 struct tg3_napi *tnapi = &tp->napi[i];
9512
9513 if (!tnapi->rx_rcb)
9514 continue;
9515
9516 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9517 (tp->rx_ret_ring_mask + 1) <<
9518 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9519 }
9520}
9521
2d31ecaf
MC		 9522/* tp->lock is held. */
9523static void tg3_rings_reset(struct tg3 *tp)
9524{
9525 int i;
328947ff 9526 u32 stblk;
2d31ecaf
MC		 9527 struct tg3_napi *tnapi = &tp->napi[0];
9528
328947ff 9529 tg3_tx_rcbs_disable(tp);
2d31ecaf 9530
328947ff 9531 tg3_rx_ret_rcbs_disable(tp);
2d31ecaf
MC		 9532
9533 /* Disable interrupts */
9534 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
0e6cf6a9
MC		 9535 tp->napi[0].chk_msi_cnt = 0;
9536 tp->napi[0].last_rx_cons = 0;
9537 tp->napi[0].last_tx_cons = 0;
2d31ecaf
MC		 9538
9539 /* Zero mailbox registers. */
63c3a66f 9540 if (tg3_flag(tp, SUPPORT_MSIX)) {
6fd45cb8 9541 for (i = 1; i < tp->irq_max; i++) {
f77a6a8e
MC		 9542 tp->napi[i].tx_prod = 0;
9543 tp->napi[i].tx_cons = 0;
63c3a66f 9544 if (tg3_flag(tp, ENABLE_TSS))
c2353a32 9545 tw32_mailbox(tp->napi[i].prodmbox, 0);
f77a6a8e
MC		 9546 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9547 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7f230735 9548 tp->napi[i].chk_msi_cnt = 0;
0e6cf6a9
MC		 9549 tp->napi[i].last_rx_cons = 0;
9550 tp->napi[i].last_tx_cons = 0;
f77a6a8e 9551 }
63c3a66f 9552 if (!tg3_flag(tp, ENABLE_TSS))
c2353a32 9553 tw32_mailbox(tp->napi[0].prodmbox, 0);
f77a6a8e
MC		 9554 } else {
9555 tp->napi[0].tx_prod = 0;
9556 tp->napi[0].tx_cons = 0;
9557 tw32_mailbox(tp->napi[0].prodmbox, 0);
9558 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9559 }
2d31ecaf
MC		 9560
9561 /* Make sure the NIC-based send BD rings are disabled. */
63c3a66f 9562 if (!tg3_flag(tp, 5705_PLUS)) {
2d31ecaf
MC		 9563 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9564 for (i = 0; i < 16; i++)
9565 tw32_tx_mbox(mbox + i * 8, 0);
9566 }
9567
2d31ecaf
MC		 9568 /* Clear status block in ram. */
9569 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9570
9571 /* Set status block DMA address */
9572 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9573 ((u64) tnapi->status_mapping >> 32));
9574 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9575 ((u64) tnapi->status_mapping & 0xffffffff));
9576
f77a6a8e 9577 stblk = HOSTCC_STATBLCK_RING1;
2d31ecaf 9578
f77a6a8e
MC		 9579 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9580 u64 mapping = (u64)tnapi->status_mapping;
9581 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9582 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
32ba19ef 9583 stblk += 8;
f77a6a8e
MC		 9584
9585 /* Clear status block in ram. */
9586 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
f77a6a8e 9587 }
32ba19ef
NS		 9588
9589 tg3_tx_rcbs_init(tp);
9590 tg3_rx_ret_rcbs_init(tp);
2d31ecaf
MC		 9591}
9592
eb07a940
MC		 9593static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9594{
9595 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9596
63c3a66f
JP		 9597 if (!tg3_flag(tp, 5750_PLUS) ||
9598 tg3_flag(tp, 5780_CLASS) ||
4153577a
JP		 9599 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9600 tg3_asic_rev(tp) == ASIC_REV_5752 ||
513aa6ea 9601 tg3_flag(tp, 57765_PLUS))
eb07a940 9602 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
4153577a
JP		 9603 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9604 tg3_asic_rev(tp) == ASIC_REV_5787)
eb07a940
MC		 9605 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9606 else
9607 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9608
9609 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9610 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9611
9612 val = min(nic_rep_thresh, host_rep_thresh);
9613 tw32(RCVBDI_STD_THRESH, val);
9614
63c3a66f 9615 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9616 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9617
63c3a66f 9618 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
eb07a940
MC		 9619 return;
9620
513aa6ea 9621 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
eb07a940
MC		 9622
9623 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9624
9625 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9626 tw32(RCVBDI_JUMBO_THRESH, val);
9627
63c3a66f 9628 if (tg3_flag(tp, 57765_PLUS))
eb07a940
MC		 9629 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9630}
9631
ccd5ba9d
MC		 9632static inline u32 calc_crc(unsigned char *buf, int len)
9633{
9634 u32 reg;
9635 u32 tmp;
9636 int j, k;
9637
9638 reg = 0xffffffff;
9639
9640 for (j = 0; j < len; j++) {
9641 reg ^= buf[j];
9642
9643 for (k = 0; k < 8; k++) {
9644 tmp = reg & 0x01;
9645
9646 reg >>= 1;
9647
9648 if (tmp)
9649 reg ^= 0xedb88320;
9650 }
9651 }
9652
9653 return ~reg;
9654}
9655
9656static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9657{
9658 /* accept or reject all multicast frames */
9659 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9660 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9661 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9662 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9663}
9664
9665static void __tg3_set_rx_mode(struct net_device *dev)
9666{
9667 struct tg3 *tp = netdev_priv(dev);
9668 u32 rx_mode;
9669
9670 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9671 RX_MODE_KEEP_VLAN_TAG);
9672
9673#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9674 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9675 * flag clear.
9676 */
9677 if (!tg3_flag(tp, ENABLE_ASF))
9678 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9679#endif
9680
9681 if (dev->flags & IFF_PROMISC) {
9682 /* Promiscuous mode. */
9683 rx_mode |= RX_MODE_PROMISC;
9684 } else if (dev->flags & IFF_ALLMULTI) {
9685 /* Accept all multicast. */
9686 tg3_set_multi(tp, 1);
9687 } else if (netdev_mc_empty(dev)) {
9688 /* Reject all multicast. */
9689 tg3_set_multi(tp, 0);
9690 } else {
9691 /* Accept one or more multicast(s). */
9692 struct netdev_hw_addr *ha;
9693 u32 mc_filter[4] = { 0, };
9694 u32 regidx;
9695 u32 bit;
9696 u32 crc;
9697
9698 netdev_for_each_mc_addr(ha, dev) {
9699 crc = calc_crc(ha->addr, ETH_ALEN);
9700 bit = ~crc & 0x7f;
9701 regidx = (bit & 0x60) >> 5;
9702 bit &= 0x1f;
9703 mc_filter[regidx] |= (1 << bit);
9704 }
9705
9706 tw32(MAC_HASH_REG_0, mc_filter[0]);
9707 tw32(MAC_HASH_REG_1, mc_filter[1]);
9708 tw32(MAC_HASH_REG_2, mc_filter[2]);
9709 tw32(MAC_HASH_REG_3, mc_filter[3]);
9710 }
9711
e565eec3
MC		 9712 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9713 rx_mode |= RX_MODE_PROMISC;
9714 } else if (!(dev->flags & IFF_PROMISC)) {
9715 /* Add all entries into to the mac addr filter list */
9716 int i = 0;
9717 struct netdev_hw_addr *ha;
9718
9719 netdev_for_each_uc_addr(ha, dev) {
9720 __tg3_set_one_mac_addr(tp, ha->addr,
9721 i + TG3_UCAST_ADDR_IDX(tp));
9722 i++;
9723 }
9724 }
9725
ccd5ba9d
MC		 9726 if (rx_mode != tp->rx_mode) {
9727 tp->rx_mode = rx_mode;
9728 tw32_f(MAC_RX_MODE, rx_mode);
9729 udelay(10);
9730 }
9731}
9732
9102426a 9733static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
90415477
MC		 9734{
9735 int i;
9736
9737 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9102426a 9738 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
90415477
MC		 9739}
9740
9741static void tg3_rss_check_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9742{
9743 int i;
9744
9745 if (!tg3_flag(tp, SUPPORT_MSIX))
9746 return;
9747
0b3ba055 9748 if (tp->rxq_cnt == 1) {
bcebcc46 9749 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
90415477
MC		 9750 return;
9751 }
9752
9753 /* Validate table against current IRQ count */
9754 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
0b3ba055 9755 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
90415477
MC		 9756 break;
9757 }
9758
9759 if (i != TG3_RSS_INDIR_TBL_SIZE)
9102426a 9760 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
bcebcc46
MC		 9761}
9762
90415477 9763static void tg3_rss_write_indir_tbl(struct tg3 *tp)
bcebcc46
MC		 9764{
9765 int i = 0;
9766 u32 reg = MAC_RSS_INDIR_TBL_0;
9767
9768 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9769 u32 val = tp->rss_ind_tbl[i];
9770 i++;
9771 for (; i % 8; i++) {
9772 val <<= 4;
9773 val |= tp->rss_ind_tbl[i];
9774 }
9775 tw32(reg, val);
9776 reg += 4;
9777 }
9778}
9779
9bc297ea
NS		 9780static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9781{
9782 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9783 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9784 else
9785 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9786}
9787
1da177e4 9788/* tp->lock is held. */
953c96e0 9789static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
1da177e4
LT		 9790{
9791 u32 val, rdmac_mode;
9792 int i, err, limit;
8fea32b9 9793 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
1da177e4
LT		 9794
9795 tg3_disable_ints(tp);
9796
9797 tg3_stop_fw(tp);
9798
9799 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9800
63c3a66f 9801 if (tg3_flag(tp, INIT_COMPLETE))
e6de8ad1 9802 tg3_abort_hw(tp, 1);
1da177e4 9803
fdad8de4
NS		 9804 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9805 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9806 tg3_phy_pull_config(tp);
400dfbaa 9807 tg3_eee_pull_config(tp, NULL);
fdad8de4
NS		 9808 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9809 }
9810
400dfbaa
NS		 9811 /* Enable MAC control of LPI */
9812 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9813 tg3_setup_eee(tp);
9814
603f1173 9815 if (reset_phy)
d4d2c558
MC		 9816 tg3_phy_reset(tp);
9817
1da177e4
LT		 9818 err = tg3_chip_reset(tp);
9819 if (err)
9820 return err;
9821
9822 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9823
4153577a 9824 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
d30cdd28
MC		 9825 val = tr32(TG3_CPMU_CTRL);
9826 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9827 tw32(TG3_CPMU_CTRL, val);
9acb961e
MC		 9828
9829 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9830 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9831 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9832 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9833
9834 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9835 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9836 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9837 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9838
9839 val = tr32(TG3_CPMU_HST_ACC);
9840 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9841 val |= CPMU_HST_ACC_MACCLK_6_25;
9842 tw32(TG3_CPMU_HST_ACC, val);
d30cdd28
MC		 9843 }
9844
4153577a 9845 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
33466d93
MC		 9846 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9847 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9848 PCIE_PWR_MGMT_L1_THRESH_4MS;
9849 tw32(PCIE_PWR_MGMT_THRESH, val);
521e6b90
MC		 9850
9851 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9852 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9853
9854 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
33466d93 9855
f40386c8
MC		 9856 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9857 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
255ca311
MC		 9858 }
9859
63c3a66f 9860 if (tg3_flag(tp, L1PLLPD_EN)) {
614b0590
MC		 9861 u32 grc_mode = tr32(GRC_MODE);
9862
9863 /* Access the lower 1K of PL PCIE block registers. */
9864 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9865 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9866
9867 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9868 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9869 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9870
9871 tw32(GRC_MODE, grc_mode);
9872 }
9873
55086ad9 9874 if (tg3_flag(tp, 57765_CLASS)) {
4153577a 9875 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
5093eedc 9876 u32 grc_mode = tr32(GRC_MODE);
cea46462 9877
5093eedc
MC		 9878 /* Access the lower 1K of PL PCIE block registers. */
9879 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9880 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
cea46462 9881
5093eedc
MC		 9882 val = tr32(TG3_PCIE_TLDLPL_PORT +
9883 TG3_PCIE_PL_LO_PHYCTL5);
9884 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9885 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
cea46462 9886
5093eedc
MC		 9887 tw32(GRC_MODE, grc_mode);
9888 }
a977dbe8 9889
4153577a 9890 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
d3f677af
MC		 9891 u32 grc_mode;
9892
9893 /* Fix transmit hangs */
9894 val = tr32(TG3_CPMU_PADRNG_CTL);
9895 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9896 tw32(TG3_CPMU_PADRNG_CTL, val);
9897
9898 grc_mode = tr32(GRC_MODE);
1ff30a59
MC		 9899
9900 /* Access the lower 1K of DL PCIE block registers. */
9901 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9902 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9903
9904 val = tr32(TG3_PCIE_TLDLPL_PORT +
9905 TG3_PCIE_DL_LO_FTSMAX);
9906 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9907 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9908 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9909
9910 tw32(GRC_MODE, grc_mode);
9911 }
9912
a977dbe8
MC		 9913 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9914 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9915 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9916 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
cea46462
MC		 9917 }
9918
1da177e4
LT		 9919 /* This works around an issue with Athlon chipsets on
9920 * B3 tigon3 silicon. This bit has no effect on any
9921 * other revision. But do not set this on PCI Express
795d01c5 9922 * chips and don't even touch the clocks if the CPMU is present.
1da177e4 9923 */
63c3a66f
JP		 9924 if (!tg3_flag(tp, CPMU_PRESENT)) {
9925 if (!tg3_flag(tp, PCI_EXPRESS))
795d01c5
MC		 9926 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9927 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9928 }
1da177e4 9929
4153577a 9930 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
63c3a66f 9931 tg3_flag(tp, PCIX_MODE)) {
1da177e4
LT		 9932 val = tr32(TG3PCI_PCISTATE);
9933 val |= PCISTATE_RETRY_SAME_DMA;
9934 tw32(TG3PCI_PCISTATE, val);
9935 }
9936
63c3a66f 9937 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 9938 /* Allow reads and writes to the
9939 * APE register and memory space.
9940 */
9941 val = tr32(TG3PCI_PCISTATE);
9942 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 9943 PCISTATE_ALLOW_APE_SHMEM_WR |
9944 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 9945 tw32(TG3PCI_PCISTATE, val);
9946 }
9947
4153577a 9948 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
1da177e4
LT		 9949 /* Enable some hw fixes. */
9950 val = tr32(TG3PCI_MSI_DATA);
9951 val |= (1 << 26) | (1 << 28) | (1 << 29);
9952 tw32(TG3PCI_MSI_DATA, val);
9953 }
9954
9955 /* Descriptor ring init may make accesses to the
9956 * NIC SRAM area to setup the TX descriptors, so we
9957 * can only do this after the hardware has been
9958 * successfully reset.
9959 */
32d8c572
MC		 9960 err = tg3_init_rings(tp);
9961 if (err)
9962 return err;
1da177e4 9963
63c3a66f 9964 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 9965 val = tr32(TG3PCI_DMA_RW_CTRL) &
9966 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
4153577a 9967 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
1a319025 9968 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
55086ad9 9969 if (!tg3_flag(tp, 57765_CLASS) &&
4153577a
JP		 9970 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9971 tg3_asic_rev(tp) != ASIC_REV_5762)
0aebff48 9972 val |= DMA_RWCTRL_TAGGED_STAT_WA;
cbf9ca6c 9973 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
4153577a
JP		 9974 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9975 tg3_asic_rev(tp) != ASIC_REV_5761) {
d30cdd28
MC		 9976 /* This value is determined during the probe time DMA
9977 * engine test, tg3_test_dma.
9978 */
9979 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9980 }
1da177e4
LT		 9981
9982 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9983 GRC_MODE_4X_NIC_SEND_RINGS |
9984 GRC_MODE_NO_TX_PHDR_CSUM |
9985 GRC_MODE_NO_RX_PHDR_CSUM);
9986 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
d2d746f8
MC		 9987
9988 /* Pseudo-header checksum is done by hardware logic and not
9989 * the offload processers, so make the chip do the pseudo-
9990 * header checksums on receive. For transmit it is more
9991 * convenient to do the pseudo-header checksum in software
9992 * as Linux does that on transmit for us in all cases.
9993 */
9994 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1da177e4 9995
fb4ce8ad
MC		 9996 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9997 if (tp->rxptpctl)
9998 tw32(TG3_RX_PTP_CTL,
9999 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10000
10001 if (tg3_flag(tp, PTP_CAPABLE))
10002 val |= GRC_MODE_TIME_SYNC_ENABLE;
10003
10004 tw32(GRC_MODE, tp->grc_mode | val);
1da177e4
LT		 10005
10006 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10007 val = tr32(GRC_MISC_CFG);
10008 val &= ~0xff;
10009 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10010 tw32(GRC_MISC_CFG, val);
10011
10012 /* Initialize MBUF/DESC pool. */
63c3a66f 10013 if (tg3_flag(tp, 5750_PLUS)) {
1da177e4 10014 /* Do nothing. */
4153577a 10015 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
1da177e4 10016 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
4153577a 10017 if (tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 10018 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10019 else
10020 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10021 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10022 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
63c3a66f 10023 } else if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10024 int fw_len;
10025
077f849d 10026 fw_len = tp->fw_len;
1da177e4
LT		 10027 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10028 tw32(BUFMGR_MB_POOL_ADDR,
10029 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10030 tw32(BUFMGR_MB_POOL_SIZE,
10031 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10032 }
1da177e4 10033
0f893dc6 10034 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 10035 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10036 tp->bufmgr_config.mbuf_read_dma_low_water);
10037 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10038 tp->bufmgr_config.mbuf_mac_rx_low_water);
10039 tw32(BUFMGR_MB_HIGH_WATER,
10040 tp->bufmgr_config.mbuf_high_water);
10041 } else {
10042 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10043 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10044 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10045 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10046 tw32(BUFMGR_MB_HIGH_WATER,
10047 tp->bufmgr_config.mbuf_high_water_jumbo);
10048 }
10049 tw32(BUFMGR_DMA_LOW_WATER,
10050 tp->bufmgr_config.dma_low_water);
10051 tw32(BUFMGR_DMA_HIGH_WATER,
10052 tp->bufmgr_config.dma_high_water);
10053
d309a46e 10054 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
4153577a 10055 if (tg3_asic_rev(tp) == ASIC_REV_5719)
d309a46e 10056 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
4153577a 10057 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 10058 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 10059 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10060 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
4d958473 10061 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
d309a46e 10062 tw32(BUFMGR_MODE, val);
1da177e4
LT		 10063 for (i = 0; i < 2000; i++) {
10064 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10065 break;
10066 udelay(10);
10067 }
10068 if (i >= 2000) {
05dbe005 10069 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
1da177e4
LT		 10070 return -ENODEV;
10071 }
10072
4153577a 10073 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
eb07a940 10074 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
b5d3772c 10075
eb07a940 10076 tg3_setup_rxbd_thresholds(tp);
1da177e4
LT		 10077
10078 /* Initialize TG3_BDINFO's at:
10079 * RCVDBDI_STD_BD: standard eth size rx ring
10080 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10081 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10082 *
10083 * like so:
10084 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10085 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10086 * ring attribute flags
10087 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10088 *
10089 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10090 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10091 *
10092 * The size of each ring is fixed in the firmware, but the location is
10093 * configurable.
10094 */
10095 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10096 ((u64) tpr->rx_std_mapping >> 32));
1da177e4 10097 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10098 ((u64) tpr->rx_std_mapping & 0xffffffff));
63c3a66f 10099 if (!tg3_flag(tp, 5717_PLUS))
87668d35
MC		 10100 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10101 NIC_SRAM_RX_BUFFER_DESC);
1da177e4 10102
fdb72b38 10103 /* Disable the mini ring */
63c3a66f 10104 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10105 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10106 BDINFO_FLAGS_DISABLED);
10107
fdb72b38
MC		 10108 /* Program the jumbo buffer descriptor ring control
10109 * blocks on those devices that have them.
10110 */
4153577a 10111 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
63c3a66f 10112 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
1da177e4 10113
63c3a66f 10114 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
1da177e4 10115 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
21f581a5 10116 ((u64) tpr->rx_jmb_mapping >> 32));
1da177e4 10117 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
21f581a5 10118 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
de9f5230
MC		 10119 val = TG3_RX_JMB_RING_SIZE(tp) <<
10120 BDINFO_FLAGS_MAXLEN_SHIFT;
1da177e4 10121 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
de9f5230 10122 val | BDINFO_FLAGS_USE_EXT_RECV);
63c3a66f 10123 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
c65a17f4 10124 tg3_flag(tp, 57765_CLASS) ||
4153577a 10125 tg3_asic_rev(tp) == ASIC_REV_5762)
87668d35
MC		 10126 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10127 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
1da177e4
LT		 10128 } else {
10129 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10130 BDINFO_FLAGS_DISABLED);
10131 }
10132
63c3a66f 10133 if (tg3_flag(tp, 57765_PLUS)) {
fa6b2aae 10134 val = TG3_RX_STD_RING_SIZE(tp);
7cb32cf2
MC		 10135 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10136 val |= (TG3_RX_STD_DMA_SZ << 2);
10137 } else
04380d40 10138 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38 10139 } else
de9f5230 10140 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
fdb72b38
MC		 10141
10142 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
1da177e4 10143
411da640 10144 tpr->rx_std_prod_idx = tp->rx_pending;
66711e66 10145 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
1da177e4 10146
63c3a66f
JP		 10147 tpr->rx_jmb_prod_idx =
10148 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
66711e66 10149 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
1da177e4 10150
2d31ecaf
MC		 10151 tg3_rings_reset(tp);
10152
1da177e4 10153 /* Initialize MAC address and backoff seed. */
953c96e0 10154 __tg3_set_mac_addr(tp, false);
1da177e4
LT		 10155
10156 /* MTU + ethernet header + FCS + optional VLAN tag */
f7b493e0
MC		 10157 tw32(MAC_RX_MTU_SIZE,
10158 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
1da177e4
LT		 10159
10160 /* The slot time is changed by tg3_setup_phy if we
10161 * run at gigabit with half duplex.
10162 */
f2096f94
MC		 10163 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10164 (6 << TX_LENGTHS_IPG_SHIFT) |
10165 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10166
4153577a
JP		 10167 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10168 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10169 val |= tr32(MAC_TX_LENGTHS) &
10170 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10171 TX_LENGTHS_CNT_DWN_VAL_MSK);
10172
10173 tw32(MAC_TX_LENGTHS, val);
1da177e4
LT		 10174
10175 /* Receive rules. */
10176 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10177 tw32(RCVLPC_CONFIG, 0x0181);
10178
10179 /* Calculate RDMAC_MODE setting early, we need it to determine
10180 * the RCVLPC_STATE_ENABLE mask.
10181 */
10182 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10183 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10184 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10185 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10186 RDMAC_MODE_LNGREAD_ENAB);
85e94ced 10187
4153577a 10188 if (tg3_asic_rev(tp) == ASIC_REV_5717)
0339e4e3
MC		 10189 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10190
4153577a
JP		 10191 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10192 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10193 tg3_asic_rev(tp) == ASIC_REV_57780)
d30cdd28
MC		 10194 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10195 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10196 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10197
4153577a
JP		 10198 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10199 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10200 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a 10201 tg3_asic_rev(tp) == ASIC_REV_5705) {
1da177e4
LT		 10202 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10203 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10204 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10205 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10206 }
10207 }
10208
63c3a66f 10209 if (tg3_flag(tp, PCI_EXPRESS))
85e94ced
MC		 10210 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10211
4153577a 10212 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
d3f677af
MC		 10213 tp->dma_limit = 0;
10214 if (tp->dev->mtu <= ETH_DATA_LEN) {
10215 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10216 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10217 }
10218 }
10219
63c3a66f
JP		 10220 if (tg3_flag(tp, HW_TSO_1) ||
10221 tg3_flag(tp, HW_TSO_2) ||
10222 tg3_flag(tp, HW_TSO_3))
027455ad
MC		 10223 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10224
108a6c16 10225 if (tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 10226 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10227 tg3_asic_rev(tp) == ASIC_REV_57780)
027455ad 10228 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
1da177e4 10229
4153577a
JP		 10230 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10231 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 10232 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10233
4153577a
JP		 10234 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10235 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10236 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10237 tg3_asic_rev(tp) == ASIC_REV_57780 ||
63c3a66f 10238 tg3_flag(tp, 57765_PLUS)) {
c65a17f4
MC		 10239 u32 tgtreg;
10240
4153577a 10241 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10242 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10243 else
10244 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10245
10246 val = tr32(tgtreg);
4153577a
JP		 10247 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10248 tg3_asic_rev(tp) == ASIC_REV_5762) {
b4495ed8
MC		 10249 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10250 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10251 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10252 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10253 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10254 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
b75cc0e4 10255 }
c65a17f4 10256 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
41a8a7ee
MC		 10257 }
10258
4153577a
JP		 10259 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10260 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10261 tg3_asic_rev(tp) == ASIC_REV_5762) {
c65a17f4
MC		 10262 u32 tgtreg;
10263
4153577a 10264 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c65a17f4
MC		 10265 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10266 else
10267 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10268
10269 val = tr32(tgtreg);
10270 tw32(tgtreg, val |
d309a46e
MC		 10271 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10272 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10273 }
10274
1da177e4 10275 /* Receive/send statistics. */
63c3a66f 10276 if (tg3_flag(tp, 5750_PLUS)) {
1661394e
MC		 10277 val = tr32(RCVLPC_STATS_ENABLE);
10278 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10279 tw32(RCVLPC_STATS_ENABLE, val);
10280 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
63c3a66f 10281 tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10282 val = tr32(RCVLPC_STATS_ENABLE);
10283 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10284 tw32(RCVLPC_STATS_ENABLE, val);
10285 } else {
10286 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10287 }
10288 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10289 tw32(SNDDATAI_STATSENAB, 0xffffff);
10290 tw32(SNDDATAI_STATSCTRL,
10291 (SNDDATAI_SCTRL_ENABLE |
10292 SNDDATAI_SCTRL_FASTUPD));
10293
10294 /* Setup host coalescing engine. */
10295 tw32(HOSTCC_MODE, 0);
10296 for (i = 0; i < 2000; i++) {
10297 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10298 break;
10299 udelay(10);
10300 }
10301
d244c892 10302 __tg3_set_coalesce(tp, &tp->coal);
1da177e4 10303
63c3a66f 10304 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10305 /* Status/statistics block address. See tg3_timer,
10306 * the tg3_periodic_fetch_stats call there, and
10307 * tg3_get_stats to see how this works for 5705/5750 chips.
10308 */
1da177e4
LT		 10309 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10310 ((u64) tp->stats_mapping >> 32));
10311 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10312 ((u64) tp->stats_mapping & 0xffffffff));
10313 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
2d31ecaf 10314
1da177e4 10315 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
2d31ecaf
MC		 10316
10317 /* Clear statistics and status block memory areas */
10318 for (i = NIC_SRAM_STATS_BLK;
10319 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10320 i += sizeof(u32)) {
10321 tg3_write_mem(tp, i, 0);
10322 udelay(40);
10323 }
1da177e4
LT		 10324 }
10325
10326 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10327
10328 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10329 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
63c3a66f 10330 if (!tg3_flag(tp, 5705_PLUS))
1da177e4
LT		 10331 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10332
f07e9af3
MC		 10333 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10334 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
c94e3941
MC		 10335 /* reset to prevent losing 1st rx packet intermittently */
10336 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10337 udelay(10);
10338 }
10339
3bda1258 10340 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9e975cc2
MC		 10341 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10342 MAC_MODE_FHDE_ENABLE;
10343 if (tg3_flag(tp, ENABLE_APE))
10344 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
63c3a66f 10345 if (!tg3_flag(tp, 5705_PLUS) &&
f07e9af3 10346 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a 10347 tg3_asic_rev(tp) != ASIC_REV_5700)
e8f3f6ca 10348 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1da177e4
LT		 10349 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10350 udelay(40);
10351
314fba34 10352 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
63c3a66f 10353 * If TG3_FLAG_IS_NIC is zero, we should read the
314fba34
MC		 10354 * register to preserve the GPIO settings for LOMs. The GPIOs,
10355 * whether used as inputs or outputs, are set by boot code after
10356 * reset.
10357 */
63c3a66f 10358 if (!tg3_flag(tp, IS_NIC)) {
314fba34
MC		 10359 u32 gpio_mask;
10360
9d26e213
MC		 10361 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10362 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10363 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc 10364
4153577a 10365 if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc
MC		 10366 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10367 GRC_LCLCTRL_GPIO_OUTPUT3;
10368
4153577a 10369 if (tg3_asic_rev(tp) == ASIC_REV_5755)
af36e6b6
MC		 10370 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10371
aaf84465 10372 tp->grc_local_ctrl &= ~gpio_mask;
314fba34
MC		 10373 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10374
10375 /* GPIO1 must be driven high for eeprom write protect */
63c3a66f 10376 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9d26e213
MC		 10377 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10378 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 10379 }
1da177e4
LT		 10380 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10381 udelay(100);
10382
c3b5003b 10383 if (tg3_flag(tp, USING_MSIX)) {
baf8a94a 10384 val = tr32(MSGINT_MODE);
c3b5003b
MC		 10385 val |= MSGINT_MODE_ENABLE;
10386 if (tp->irq_cnt > 1)
10387 val |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 10388 if (!tg3_flag(tp, 1SHOT_MSI))
10389 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
baf8a94a
MC		 10390 tw32(MSGINT_MODE, val);
10391 }
10392
63c3a66f 10393 if (!tg3_flag(tp, 5705_PLUS)) {
1da177e4
LT		 10394 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10395 udelay(40);
10396 }
10397
10398 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10399 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10400 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10401 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10402 WDMAC_MODE_LNGREAD_ENAB);
10403
4153577a
JP		 10404 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10405 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
63c3a66f 10406 if (tg3_flag(tp, TSO_CAPABLE) &&
4153577a
JP		 10407 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10408 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
1da177e4
LT		 10409 /* nothing */
10410 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
63c3a66f 10411 !tg3_flag(tp, IS_5788)) {
1da177e4
LT		 10412 val |= WDMAC_MODE_RX_ACCEL;
10413 }
10414 }
10415
d9ab5ad1 10416 /* Enable host coalescing bug fix */
63c3a66f 10417 if (tg3_flag(tp, 5755_PLUS))
f51f3562 10418 val |= WDMAC_MODE_STATUS_TAG_FIX;
d9ab5ad1 10419
4153577a 10420 if (tg3_asic_rev(tp) == ASIC_REV_5785)
788a035e
MC		 10421 val |= WDMAC_MODE_BURST_ALL_DATA;
10422
1da177e4
LT		 10423 tw32_f(WDMAC_MODE, val);
10424 udelay(40);
10425
63c3a66f 10426 if (tg3_flag(tp, PCIX_MODE)) {
9974a356
MC		 10427 u16 pcix_cmd;
10428
10429 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10430 &pcix_cmd);
4153577a 10431 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
9974a356
MC		 10432 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10433 pcix_cmd |= PCI_X_CMD_READ_2K;
4153577a 10434 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
9974a356
MC		 10435 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10436 pcix_cmd |= PCI_X_CMD_READ_2K;
1da177e4 10437 }
9974a356
MC		 10438 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10439 pcix_cmd);
1da177e4
LT		 10440 }
10441
10442 tw32_f(RDMAC_MODE, rdmac_mode);
10443 udelay(40);
10444
9bc297ea
NS		 10445 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10446 tg3_asic_rev(tp) == ASIC_REV_5720) {
091f0ea3
MC		 10447 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10448 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10449 break;
10450 }
10451 if (i < TG3_NUM_RDMA_CHANNELS) {
10452 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10453 val |= tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10454 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10455 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
091f0ea3
MC		 10456 }
10457 }
10458
1da177e4 10459 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
63c3a66f 10460 if (!tg3_flag(tp, 5705_PLUS))
1da177e4 10461 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9936bcf6 10462
4153577a 10463 if (tg3_asic_rev(tp) == ASIC_REV_5761)
9936bcf6
MC		 10464 tw32(SNDDATAC_MODE,
10465 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10466 else
10467 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10468
1da177e4
LT		 10469 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10470 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7cb32cf2 10471 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
63c3a66f 10472 if (tg3_flag(tp, LRG_PROD_RING_CAP))
7cb32cf2
MC		 10473 val |= RCVDBDI_MODE_LRG_RING_SZ;
10474 tw32(RCVDBDI_MODE, val);
1da177e4 10475 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
63c3a66f
JP		 10476 if (tg3_flag(tp, HW_TSO_1) ||
10477 tg3_flag(tp, HW_TSO_2) ||
10478 tg3_flag(tp, HW_TSO_3))
1da177e4 10479 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
baf8a94a 10480 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
63c3a66f 10481 if (tg3_flag(tp, ENABLE_TSS))
baf8a94a
MC		 10482 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10483 tw32(SNDBDI_MODE, val);
1da177e4
LT		 10484 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10485
4153577a 10486 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
1da177e4
LT		 10487 err = tg3_load_5701_a0_firmware_fix(tp);
10488 if (err)
10489 return err;
10490 }
10491
c4dab506
NS		 10492 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10493 /* Ignore any errors for the firmware download. If download
10494 * fails, the device will operate with EEE disabled
10495 */
10496 tg3_load_57766_firmware(tp);
10497 }
10498
63c3a66f 10499 if (tg3_flag(tp, TSO_CAPABLE)) {
1da177e4
LT		 10500 err = tg3_load_tso_firmware(tp);
10501 if (err)
10502 return err;
10503 }
1da177e4
LT		 10504
10505 tp->tx_mode = TX_MODE_ENABLE;
f2096f94 10506
63c3a66f 10507 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 10508 tg3_asic_rev(tp) == ASIC_REV_5906)
b1d05210 10509 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
f2096f94 10510
4153577a
JP		 10511 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10512 tg3_asic_rev(tp) == ASIC_REV_5762) {
f2096f94
MC		 10513 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10514 tp->tx_mode &= ~val;
10515 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10516 }
10517
1da177e4
LT		 10518 tw32_f(MAC_TX_MODE, tp->tx_mode);
10519 udelay(100);
10520
63c3a66f 10521 if (tg3_flag(tp, ENABLE_RSS)) {
bcebcc46 10522 tg3_rss_write_indir_tbl(tp);
baf8a94a
MC		 10523
10524 /* Setup the "secret" hash key. */
10525 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10526 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10527 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10528 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10529 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10530 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10531 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10532 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10533 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10534 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10535 }
10536
1da177e4 10537 tp->rx_mode = RX_MODE_ENABLE;
63c3a66f 10538 if (tg3_flag(tp, 5755_PLUS))
af36e6b6
MC		 10539 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10540
378b72c8
NS		 10541 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10542 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10543
63c3a66f 10544 if (tg3_flag(tp, ENABLE_RSS))
baf8a94a
MC		 10545 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10546 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10547 RX_MODE_RSS_IPV6_HASH_EN |
10548 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10549 RX_MODE_RSS_IPV4_HASH_EN |
10550 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10551
1da177e4
LT		 10552 tw32_f(MAC_RX_MODE, tp->rx_mode);
10553 udelay(10);
10554
1da177e4
LT		 10555 tw32(MAC_LED_CTRL, tp->led_ctrl);
10556
10557 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
f07e9af3 10558 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
1da177e4
LT		 10559 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10560 udelay(10);
10561 }
10562 tw32_f(MAC_RX_MODE, tp->rx_mode);
10563 udelay(10);
10564
f07e9af3 10565 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
4153577a
JP		 10566 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10567 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
1da177e4
LT		 10568 /* Set drive transmission level to 1.2V */
10569 /* only if the signal pre-emphasis bit is not set */
10570 val = tr32(MAC_SERDES_CFG);
10571 val &= 0xfffff000;
10572 val |= 0x880;
10573 tw32(MAC_SERDES_CFG, val);
10574 }
4153577a 10575 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
1da177e4
LT		 10576 tw32(MAC_SERDES_CFG, 0x616000);
10577 }
10578
10579 /* Prevent chip from dropping frames when flow control
10580 * is enabled.
10581 */
55086ad9 10582 if (tg3_flag(tp, 57765_CLASS))
666bc831
MC		 10583 val = 1;
10584 else
10585 val = 2;
10586 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
1da177e4 10587
4153577a 10588 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
f07e9af3 10589 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
1da177e4 10590 /* Use hardware link auto-negotiation */
63c3a66f 10591 tg3_flag_set(tp, HW_AUTONEG);
1da177e4
LT		 10592 }
10593
f07e9af3 10594 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
4153577a 10595 tg3_asic_rev(tp) == ASIC_REV_5714) {
d4d2c558
MC		 10596 u32 tmp;
10597
10598 tmp = tr32(SERDES_RX_CTRL);
10599 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10600 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10601 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10602 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10603 }
10604
63c3a66f 10605 if (!tg3_flag(tp, USE_PHYLIB)) {
c6700ce2 10606 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
80096068 10607 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1da177e4 10608
953c96e0 10609 err = tg3_setup_phy(tp, false);
dd477003
MC		 10610 if (err)
10611 return err;
1da177e4 10612
f07e9af3
MC		 10613 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10614 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
dd477003
MC		 10615 u32 tmp;
10616
10617 /* Clear CRC stats. */
10618 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10619 tg3_writephy(tp, MII_TG3_TEST1,
10620 tmp | MII_TG3_TEST1_CRC_EN);
f08aa1a8 10621 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
dd477003 10622 }
1da177e4
LT		 10623 }
10624 }
10625
10626 __tg3_set_rx_mode(tp->dev);
10627
10628 /* Initialize receive rules. */
10629 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10630 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10631 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10632 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10633
63c3a66f 10634 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
1da177e4
LT		 10635 limit = 8;
10636 else
10637 limit = 16;
63c3a66f 10638 if (tg3_flag(tp, ENABLE_ASF))
1da177e4
LT		 10639 limit -= 4;
10640 switch (limit) {
10641 case 16:
10642 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10643 case 15:
10644 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10645 case 14:
10646 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10647 case 13:
10648 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10649 case 12:
10650 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10651 case 11:
10652 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10653 case 10:
10654 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10655 case 9:
10656 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10657 case 8:
10658 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10659 case 7:
10660 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10661 case 6:
10662 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10663 case 5:
10664 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10665 case 4:
10666 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10667 case 3:
10668 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10669 case 2:
10670 case 1:
10671
10672 default:
10673 break;
855e1111 10674 }
1da177e4 10675
63c3a66f 10676 if (tg3_flag(tp, ENABLE_APE))
9ce768ea
MC		 10677 /* Write our heartbeat update interval to APE. */
10678 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10679 APE_HOST_HEARTBEAT_INT_DISABLE);
0d3031d9 10680
1da177e4
LT		 10681 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10682
1da177e4
LT		 10683 return 0;
10684}
10685
10686/* Called at device open time to get the chip ready for
10687 * packet processing. Invoked with tp->lock held.
10688 */
953c96e0 10689static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
1da177e4 10690{
df465abf
NS		 10691 /* Chip may have been just powered on. If so, the boot code may still
10692 * be running initialization. Wait for it to finish to avoid races in
10693 * accessing the hardware.
10694 */
10695 tg3_enable_register_access(tp);
10696 tg3_poll_fw(tp);
10697
1da177e4
LT		 10698 tg3_switch_clocks(tp);
10699
10700 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10701
2f751b67 10702 return tg3_reset_hw(tp, reset_phy);
1da177e4
LT		 10703}
10704
aed93e0b
MC		 10705static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10706{
10707 int i;
10708
10709 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10710 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10711
10712 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10713 off += len;
10714
10715 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10716 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10717 memset(ocir, 0, TG3_OCIR_LEN);
10718 }
10719}
10720
10721/* sysfs attributes for hwmon */
10722static ssize_t tg3_show_temp(struct device *dev,
10723 struct device_attribute *devattr, char *buf)
10724{
aed93e0b 10725 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
a2f4dfba 10726 struct tg3 *tp = dev_get_drvdata(dev);
aed93e0b
MC		 10727 u32 temperature;
10728
10729 spin_lock_bh(&tp->lock);
10730 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10731 sizeof(temperature));
10732 spin_unlock_bh(&tp->lock);
10733 return sprintf(buf, "%u\n", temperature);
10734}
10735
10736
10737static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10738 TG3_TEMP_SENSOR_OFFSET);
10739static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10740 TG3_TEMP_CAUTION_OFFSET);
10741static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10742 TG3_TEMP_MAX_OFFSET);
10743
a2f4dfba 10744static struct attribute *tg3_attrs[] = {
aed93e0b
MC		 10745 &sensor_dev_attr_temp1_input.dev_attr.attr,
10746 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10747 &sensor_dev_attr_temp1_max.dev_attr.attr,
10748 NULL
10749};
a2f4dfba 10750ATTRIBUTE_GROUPS(tg3);
aed93e0b 10751
aed93e0b
MC		 10752static void tg3_hwmon_close(struct tg3 *tp)
10753{
aed93e0b
MC		 10754 if (tp->hwmon_dev) {
10755 hwmon_device_unregister(tp->hwmon_dev);
10756 tp->hwmon_dev = NULL;
aed93e0b 10757 }
aed93e0b
MC		 10758}
10759
10760static void tg3_hwmon_open(struct tg3 *tp)
10761{
a2f4dfba 10762 int i;
aed93e0b
MC		 10763 u32 size = 0;
10764 struct pci_dev *pdev = tp->pdev;
10765 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10766
10767 tg3_sd_scan_scratchpad(tp, ocirs);
10768
10769 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10770 if (!ocirs[i].src_data_length)
10771 continue;
10772
10773 size += ocirs[i].src_hdr_length;
10774 size += ocirs[i].src_data_length;
10775 }
10776
10777 if (!size)
10778 return;
10779
a2f4dfba
GR		 10780 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10781 tp, tg3_groups);
aed93e0b
MC		 10782 if (IS_ERR(tp->hwmon_dev)) {
10783 tp->hwmon_dev = NULL;
10784 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
aed93e0b 10785 }
aed93e0b
MC		 10786}
10787
10788
1da177e4
LT		 10789#define TG3_STAT_ADD32(PSTAT, REG) \
10790do { u32 __val = tr32(REG); \
10791 (PSTAT)->low += __val; \
10792 if ((PSTAT)->low < __val) \
10793 (PSTAT)->high += 1; \
10794} while (0)
10795
10796static void tg3_periodic_fetch_stats(struct tg3 *tp)
10797{
10798 struct tg3_hw_stats *sp = tp->hw_stats;
10799
f4a46d1f 10800 if (!tp->link_up)
1da177e4
LT		 10801 return;
10802
10803 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10804 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10805 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10806 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10807 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10808 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10809 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10810 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10811 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10812 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10813 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10814 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10815 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9bc297ea 10816 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
091f0ea3
MC		 10817 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10818 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10819 u32 val;
10820
10821 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9bc297ea 10822 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
091f0ea3 10823 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9bc297ea 10824 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
091f0ea3 10825 }
1da177e4
LT		 10826
10827 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10828 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10829 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10830 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10831 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10832 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10833 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10834 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10835 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10836 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10837 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10838 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10839 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10840 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
463d305b
MC		 10841
10842 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
4153577a 10843 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
94962f7f 10844 tg3_asic_rev(tp) != ASIC_REV_5762 &&
4153577a
JP		 10845 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10846 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
4d958473
MC		 10847 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10848 } else {
10849 u32 val = tr32(HOSTCC_FLOW_ATTN);
10850 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10851 if (val) {
10852 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10853 sp->rx_discards.low += val;
10854 if (sp->rx_discards.low < val)
10855 sp->rx_discards.high += 1;
10856 }
10857 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10858 }
463d305b 10859 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
1da177e4
LT		 10860}
10861
0e6cf6a9
MC		 10862static void tg3_chk_missed_msi(struct tg3 *tp)
10863{
10864 u32 i;
10865
10866 for (i = 0; i < tp->irq_cnt; i++) {
10867 struct tg3_napi *tnapi = &tp->napi[i];
10868
10869 if (tg3_has_work(tnapi)) {
10870 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10871 tnapi->last_tx_cons == tnapi->tx_cons) {
10872 if (tnapi->chk_msi_cnt < 1) {
10873 tnapi->chk_msi_cnt++;
10874 return;
10875 }
7f230735 10876 tg3_msi(0, tnapi);
0e6cf6a9
MC		 10877 }
10878 }
10879 tnapi->chk_msi_cnt = 0;
10880 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10881 tnapi->last_tx_cons = tnapi->tx_cons;
10882 }
10883}
10884
1da177e4
LT		 10885static void tg3_timer(unsigned long __opaque)
10886{
10887 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 10888
5b190624 10889 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
f475f163
MC		 10890 goto restart_timer;
10891
f47c11ee 10892 spin_lock(&tp->lock);
1da177e4 10893
4153577a 10894 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
55086ad9 10895 tg3_flag(tp, 57765_CLASS))
0e6cf6a9
MC		 10896 tg3_chk_missed_msi(tp);
10897
7e6c63f0
HM		 10898 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10899 /* BCM4785: Flush posted writes from GbE to host memory. */
10900 tr32(HOSTCC_MODE);
10901 }
10902
63c3a66f 10903 if (!tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 10904 /* All of this garbage is because when using non-tagged
10905 * IRQ status the mailbox/status_block protocol the chip
10906 * uses with the cpu is race prone.
10907 */
898a56f8 10908 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
fac9b83e
DM		 10909 tw32(GRC_LOCAL_CTRL,
10910 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10911 } else {
10912 tw32(HOSTCC_MODE, tp->coalesce_mode |
fd2ce37f 10913 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
fac9b83e 10914 }
1da177e4 10915
fac9b83e 10916 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
f47c11ee 10917 spin_unlock(&tp->lock);
db219973 10918 tg3_reset_task_schedule(tp);
5b190624 10919 goto restart_timer;
fac9b83e 10920 }
1da177e4
LT		 10921 }
10922
1da177e4
LT		 10923 /* This part only runs once per second. */
10924 if (!--tp->timer_counter) {
63c3a66f 10925 if (tg3_flag(tp, 5705_PLUS))
fac9b83e
DM		 10926 tg3_periodic_fetch_stats(tp);
10927
b0c5943f
MC		 10928 if (tp->setlpicnt && !--tp->setlpicnt)
10929 tg3_phy_eee_enable(tp);
52b02d04 10930
63c3a66f 10931 if (tg3_flag(tp, USE_LINKCHG_REG)) {
1da177e4
LT		 10932 u32 mac_stat;
10933 int phy_event;
10934
10935 mac_stat = tr32(MAC_STATUS);
10936
10937 phy_event = 0;
f07e9af3 10938 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
1da177e4
LT		 10939 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10940 phy_event = 1;
10941 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10942 phy_event = 1;
10943
10944 if (phy_event)
953c96e0 10945 tg3_setup_phy(tp, false);
63c3a66f 10946 } else if (tg3_flag(tp, POLL_SERDES)) {
1da177e4
LT		 10947 u32 mac_stat = tr32(MAC_STATUS);
10948 int need_setup = 0;
10949
f4a46d1f 10950 if (tp->link_up &&
1da177e4
LT		 10951 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10952 need_setup = 1;
10953 }
f4a46d1f 10954 if (!tp->link_up &&
1da177e4
LT		 10955 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10956 MAC_STATUS_SIGNAL_DET))) {
10957 need_setup = 1;
10958 }
10959 if (need_setup) {
3d3ebe74
MC		 10960 if (!tp->serdes_counter) {
10961 tw32_f(MAC_MODE,
10962 (tp->mac_mode &
10963 ~MAC_MODE_PORT_MODE_MASK));
10964 udelay(40);
10965 tw32_f(MAC_MODE, tp->mac_mode);
10966 udelay(40);
10967 }
953c96e0 10968 tg3_setup_phy(tp, false);
1da177e4 10969 }
f07e9af3 10970 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
63c3a66f 10971 tg3_flag(tp, 5780_CLASS)) {
747e8f8b 10972 tg3_serdes_parallel_detect(tp);
1743b83c
NS		 10973 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10974 u32 cpmu = tr32(TG3_CPMU_STATUS);
10975 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10976 TG3_CPMU_STATUS_LINK_MASK);
10977
10978 if (link_up != tp->link_up)
10979 tg3_setup_phy(tp, false);
57d8b880 10980 }
1da177e4
LT		 10981
10982 tp->timer_counter = tp->timer_multiplier;
10983 }
10984
130b8e4d
MC		 10985 /* Heartbeat is only sent once every 2 seconds.
10986 *
10987 * The heartbeat is to tell the ASF firmware that the host
10988 * driver is still alive. In the event that the OS crashes,
10989 * ASF needs to reset the hardware to free up the FIFO space
10990 * that may be filled with rx packets destined for the host.
10991 * If the FIFO is full, ASF will no longer function properly.
10992 *
10993 * Unintended resets have been reported on real time kernels
10994 * where the timer doesn't run on time. Netpoll will also have
10995 * same problem.
10996 *
10997 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10998 * to check the ring condition when the heartbeat is expiring
10999 * before doing the reset. This will prevent most unintended
11000 * resets.
11001 */
1da177e4 11002 if (!--tp->asf_counter) {
63c3a66f 11003 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7c5026aa
MC		 11004 tg3_wait_for_event_ack(tp);
11005
bbadf503 11006 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
130b8e4d 11007 FWCMD_NICDRV_ALIVE3);
bbadf503 11008 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
c6cdf436
MC		 11009 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11010 TG3_FW_UPDATE_TIMEOUT_SEC);
4ba526ce
MC		 11011
11012 tg3_generate_fw_event(tp);
1da177e4
LT		 11013 }
11014 tp->asf_counter = tp->asf_multiplier;
11015 }
11016
f47c11ee 11017 spin_unlock(&tp->lock);
1da177e4 11018
f475f163 11019restart_timer:
1da177e4
LT		 11020 tp->timer.expires = jiffies + tp->timer_offset;
11021 add_timer(&tp->timer);
11022}
11023
229b1ad1 11024static void tg3_timer_init(struct tg3 *tp)
21f7638e
MC		 11025{
11026 if (tg3_flag(tp, TAGGED_STATUS) &&
4153577a 11027 tg3_asic_rev(tp) != ASIC_REV_5717 &&
21f7638e
MC		 11028 !tg3_flag(tp, 57765_CLASS))
11029 tp->timer_offset = HZ;
11030 else
11031 tp->timer_offset = HZ / 10;
11032
11033 BUG_ON(tp->timer_offset > HZ);
11034
11035 tp->timer_multiplier = (HZ / tp->timer_offset);
11036 tp->asf_multiplier = (HZ / tp->timer_offset) *
11037 TG3_FW_UPDATE_FREQ_SEC;
11038
11039 init_timer(&tp->timer);
11040 tp->timer.data = (unsigned long) tp;
11041 tp->timer.function = tg3_timer;
11042}
11043
11044static void tg3_timer_start(struct tg3 *tp)
11045{
11046 tp->asf_counter = tp->asf_multiplier;
11047 tp->timer_counter = tp->timer_multiplier;
11048
11049 tp->timer.expires = jiffies + tp->timer_offset;
11050 add_timer(&tp->timer);
11051}
11052
11053static void tg3_timer_stop(struct tg3 *tp)
11054{
11055 del_timer_sync(&tp->timer);
11056}
11057
11058/* Restart hardware after configuration changes, self-test, etc.
11059 * Invoked with tp->lock held.
11060 */
953c96e0 11061static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
21f7638e
MC		 11062 __releases(tp->lock)
11063 __acquires(tp->lock)
11064{
11065 int err;
11066
11067 err = tg3_init_hw(tp, reset_phy);
11068 if (err) {
11069 netdev_err(tp->dev,
11070 "Failed to re-initialize device, aborting\n");
11071 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11072 tg3_full_unlock(tp);
11073 tg3_timer_stop(tp);
11074 tp->irq_sync = 0;
11075 tg3_napi_enable(tp);
11076 dev_close(tp->dev);
11077 tg3_full_lock(tp, 0);
11078 }
11079 return err;
11080}
11081
11082static void tg3_reset_task(struct work_struct *work)
11083{
11084 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11085 int err;
11086
11087 tg3_full_lock(tp, 0);
11088
11089 if (!netif_running(tp->dev)) {
11090 tg3_flag_clear(tp, RESET_TASK_PENDING);
11091 tg3_full_unlock(tp);
11092 return;
11093 }
11094
11095 tg3_full_unlock(tp);
11096
11097 tg3_phy_stop(tp);
11098
11099 tg3_netif_stop(tp);
11100
11101 tg3_full_lock(tp, 1);
11102
11103 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11104 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11105 tp->write32_rx_mbox = tg3_write_flush_reg32;
11106 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11107 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11108 }
11109
11110 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
953c96e0 11111 err = tg3_init_hw(tp, true);
21f7638e
MC		 11112 if (err)
11113 goto out;
11114
11115 tg3_netif_start(tp);
11116
11117out:
11118 tg3_full_unlock(tp);
11119
11120 if (!err)
11121 tg3_phy_start(tp);
11122
11123 tg3_flag_clear(tp, RESET_TASK_PENDING);
11124}
11125
4f125f42 11126static int tg3_request_irq(struct tg3 *tp, int irq_num)
fcfa0a32 11127{
7d12e780 11128 irq_handler_t fn;
fcfa0a32 11129 unsigned long flags;
4f125f42
MC		 11130 char *name;
11131 struct tg3_napi *tnapi = &tp->napi[irq_num];
11132
11133 if (tp->irq_cnt == 1)
11134 name = tp->dev->name;
11135 else {
11136 name = &tnapi->irq_lbl[0];
21e315e1
NS		 11137 if (tnapi->tx_buffers && tnapi->rx_rcb)
11138 snprintf(name, IFNAMSIZ,
11139 "%s-txrx-%d", tp->dev->name, irq_num);
11140 else if (tnapi->tx_buffers)
11141 snprintf(name, IFNAMSIZ,
11142 "%s-tx-%d", tp->dev->name, irq_num);
11143 else if (tnapi->rx_rcb)
11144 snprintf(name, IFNAMSIZ,
11145 "%s-rx-%d", tp->dev->name, irq_num);
11146 else
11147 snprintf(name, IFNAMSIZ,
11148 "%s-%d", tp->dev->name, irq_num);
4f125f42
MC		 11149 name[IFNAMSIZ-1] = 0;
11150 }
fcfa0a32 11151
63c3a66f 11152 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
fcfa0a32 11153 fn = tg3_msi;
63c3a66f 11154 if (tg3_flag(tp, 1SHOT_MSI))
fcfa0a32 11155 fn = tg3_msi_1shot;
ab392d2d 11156 flags = 0;
fcfa0a32
MC		 11157 } else {
11158 fn = tg3_interrupt;
63c3a66f 11159 if (tg3_flag(tp, TAGGED_STATUS))
fcfa0a32 11160 fn = tg3_interrupt_tagged;
ab392d2d 11161 flags = IRQF_SHARED;
fcfa0a32 11162 }
4f125f42
MC		 11163
11164 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
fcfa0a32
MC		 11165}
11166
7938109f
MC		 11167static int tg3_test_interrupt(struct tg3 *tp)
11168{
09943a18 11169 struct tg3_napi *tnapi = &tp->napi[0];
7938109f 11170 struct net_device *dev = tp->dev;
b16250e3 11171 int err, i, intr_ok = 0;
f6eb9b1f 11172 u32 val;
7938109f 11173
d4bc3927
MC		 11174 if (!netif_running(dev))
11175 return -ENODEV;
11176
7938109f
MC		 11177 tg3_disable_ints(tp);
11178
4f125f42 11179 free_irq(tnapi->irq_vec, tnapi);
7938109f 11180
f6eb9b1f
MC		 11181 /*
11182 * Turn off MSI one shot mode. Otherwise this test has no
11183 * observable way to know whether the interrupt was delivered.
11184 */
3aa1cdf8 11185 if (tg3_flag(tp, 57765_PLUS)) {
f6eb9b1f
MC		 11186 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11187 tw32(MSGINT_MODE, val);
11188 }
11189
4f125f42 11190 err = request_irq(tnapi->irq_vec, tg3_test_isr,
f274fd9a 11191 IRQF_SHARED, dev->name, tnapi);
7938109f
MC		 11192 if (err)
11193 return err;
11194
898a56f8 11195 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7938109f
MC		 11196 tg3_enable_ints(tp);
11197
11198 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 11199 tnapi->coal_now);
7938109f
MC		 11200
11201 for (i = 0; i < 5; i++) {
b16250e3
MC		 11202 u32 int_mbox, misc_host_ctrl;
11203
898a56f8 11204 int_mbox = tr32_mailbox(tnapi->int_mbox);
b16250e3
MC		 11205 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11206
11207 if ((int_mbox != 0) ||
11208 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11209 intr_ok = 1;
7938109f 11210 break;
b16250e3
MC		 11211 }
11212
3aa1cdf8
MC		 11213 if (tg3_flag(tp, 57765_PLUS) &&
11214 tnapi->hw_status->status_tag != tnapi->last_tag)
11215 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11216
7938109f
MC		 11217 msleep(10);
11218 }
11219
11220 tg3_disable_ints(tp);
11221
4f125f42 11222 free_irq(tnapi->irq_vec, tnapi);
6aa20a22 11223
4f125f42 11224 err = tg3_request_irq(tp, 0);
7938109f
MC		 11225
11226 if (err)
11227 return err;
11228
f6eb9b1f
MC		 11229 if (intr_ok) {
11230 /* Reenable MSI one shot mode. */
5b39de91 11231 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
f6eb9b1f
MC		 11232 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11233 tw32(MSGINT_MODE, val);
11234 }
7938109f 11235 return 0;
f6eb9b1f 11236 }
7938109f
MC		 11237
11238 return -EIO;
11239}
11240
11241/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11242 * successfully restored
11243 */
11244static int tg3_test_msi(struct tg3 *tp)
11245{
7938109f
MC		 11246 int err;
11247 u16 pci_cmd;
11248
63c3a66f 11249 if (!tg3_flag(tp, USING_MSI))
7938109f
MC		 11250 return 0;
11251
11252 /* Turn off SERR reporting in case MSI terminates with Master
11253 * Abort.
11254 */
11255 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11256 pci_write_config_word(tp->pdev, PCI_COMMAND,
11257 pci_cmd & ~PCI_COMMAND_SERR);
11258
11259 err = tg3_test_interrupt(tp);
11260
11261 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11262
11263 if (!err)
11264 return 0;
11265
11266 /* other failures */
11267 if (err != -EIO)
11268 return err;
11269
11270 /* MSI test failed, go back to INTx mode */
5129c3a3
MC		 11271 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11272 "to INTx mode. Please report this failure to the PCI "
11273 "maintainer and include system chipset information\n");
7938109f 11274
4f125f42 11275 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
09943a18 11276
7938109f
MC		 11277 pci_disable_msi(tp->pdev);
11278
63c3a66f 11279 tg3_flag_clear(tp, USING_MSI);
dc8bf1b1 11280 tp->napi[0].irq_vec = tp->pdev->irq;
7938109f 11281
4f125f42 11282 err = tg3_request_irq(tp, 0);
7938109f
MC		 11283 if (err)
11284 return err;
11285
11286 /* Need to reset the chip because the MSI cycle may have terminated
11287 * with Master Abort.
11288 */
f47c11ee 11289 tg3_full_lock(tp, 1);
7938109f 11290
944d980e 11291 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 11292 err = tg3_init_hw(tp, true);
7938109f 11293
f47c11ee 11294 tg3_full_unlock(tp);
7938109f
MC		 11295
11296 if (err)
4f125f42 11297 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
7938109f
MC		 11298
11299 return err;
11300}
11301
9e9fd12d
MC		 11302static int tg3_request_firmware(struct tg3 *tp)
11303{
77997ea3 11304 const struct tg3_firmware_hdr *fw_hdr;
9e9fd12d
MC		 11305
11306 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
05dbe005
JP		 11307 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11308 tp->fw_needed);
9e9fd12d
MC		 11309 return -ENOENT;
11310 }
11311
77997ea3 11312 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
9e9fd12d
MC		 11313
11314 /* Firmware blob starts with version numbers, followed by
11315 * start address and _full_ length including BSS sections
11316 * (which must be longer than the actual data, of course
11317 */
11318
77997ea3
NS		 11319 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11320 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
05dbe005
JP		 11321 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11322 tp->fw_len, tp->fw_needed);
9e9fd12d
MC		 11323 release_firmware(tp->fw);
11324 tp->fw = NULL;
11325 return -EINVAL;
11326 }
11327
11328 /* We no longer need firmware; we have it. */
11329 tp->fw_needed = NULL;
11330 return 0;
11331}
11332
9102426a 11333static u32 tg3_irq_count(struct tg3 *tp)
679563f4 11334{
9102426a 11335 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
679563f4 11336
9102426a 11337 if (irq_cnt > 1) {
c3b5003b
MC		 11338 /* We want as many rx rings enabled as there are cpus.
11339 * In multiqueue MSI-X mode, the first MSI-X vector
11340 * only deals with link interrupts, etc, so we add
11341 * one to the number of vectors we are requesting.
11342 */
9102426a 11343 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
c3b5003b 11344 }
679563f4 11345
9102426a
MC		 11346 return irq_cnt;
11347}
11348
11349static bool tg3_enable_msix(struct tg3 *tp)
11350{
11351 int i, rc;
86449944 11352 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
9102426a 11353
0968169c
MC		 11354 tp->txq_cnt = tp->txq_req;
11355 tp->rxq_cnt = tp->rxq_req;
11356 if (!tp->rxq_cnt)
11357 tp->rxq_cnt = netif_get_num_default_rss_queues();
9102426a
MC		 11358 if (tp->rxq_cnt > tp->rxq_max)
11359 tp->rxq_cnt = tp->rxq_max;
cf6d6ea6
MC		 11360
11361 /* Disable multiple TX rings by default. Simple round-robin hardware
11362 * scheduling of the TX rings can cause starvation of rings with
11363 * small packets when other rings have TSO or jumbo packets.
11364 */
11365 if (!tp->txq_req)
11366 tp->txq_cnt = 1;
9102426a
MC		 11367
11368 tp->irq_cnt = tg3_irq_count(tp);
11369
679563f4
MC		 11370 for (i = 0; i < tp->irq_max; i++) {
11371 msix_ent[i].entry = i;
11372 msix_ent[i].vector = 0;
11373 }
11374
6f1f411a 11375 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
2430b031
MC		 11376 if (rc < 0) {
11377 return false;
6f1f411a 11378 } else if (rc < tp->irq_cnt) {
05dbe005
JP		 11379 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11380 tp->irq_cnt, rc);
679563f4 11381 tp->irq_cnt = rc;
49a359e3 11382 tp->rxq_cnt = max(rc - 1, 1);
9102426a
MC		 11383 if (tp->txq_cnt)
11384 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
679563f4
MC		 11385 }
11386
11387 for (i = 0; i < tp->irq_max; i++)
11388 tp->napi[i].irq_vec = msix_ent[i].vector;
11389
49a359e3 11390 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
2ddaad39
BH		 11391 pci_disable_msix(tp->pdev);
11392 return false;
11393 }
b92b9040 11394
9102426a
MC		 11395 if (tp->irq_cnt == 1)
11396 return true;
d78b59f5 11397
9102426a
MC		 11398 tg3_flag_set(tp, ENABLE_RSS);
11399
11400 if (tp->txq_cnt > 1)
11401 tg3_flag_set(tp, ENABLE_TSS);
11402
11403 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
2430b031 11404
679563f4
MC		 11405 return true;
11406}
11407
07b0173c
MC		 11408static void tg3_ints_init(struct tg3 *tp)
11409{
63c3a66f
JP		 11410 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11411 !tg3_flag(tp, TAGGED_STATUS)) {
07b0173c
MC		 11412 /* All MSI supporting chips should support tagged
11413 * status. Assert that this is the case.
11414 */
5129c3a3
MC		 11415 netdev_warn(tp->dev,
11416 "MSI without TAGGED_STATUS? Not using MSI\n");
679563f4 11417 goto defcfg;
07b0173c 11418 }
4f125f42 11419
63c3a66f
JP		 11420 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11421 tg3_flag_set(tp, USING_MSIX);
11422 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11423 tg3_flag_set(tp, USING_MSI);
679563f4 11424
63c3a66f 11425 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
679563f4 11426 u32 msi_mode = tr32(MSGINT_MODE);
63c3a66f 11427 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
baf8a94a 11428 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
5b39de91
MC		 11429 if (!tg3_flag(tp, 1SHOT_MSI))
11430 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
679563f4
MC		 11431 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11432 }
11433defcfg:
63c3a66f 11434 if (!tg3_flag(tp, USING_MSIX)) {
679563f4
MC		 11435 tp->irq_cnt = 1;
11436 tp->napi[0].irq_vec = tp->pdev->irq;
49a359e3
MC		 11437 }
11438
11439 if (tp->irq_cnt == 1) {
11440 tp->txq_cnt = 1;
11441 tp->rxq_cnt = 1;
2ddaad39 11442 netif_set_real_num_tx_queues(tp->dev, 1);
85407885 11443 netif_set_real_num_rx_queues(tp->dev, 1);
679563f4 11444 }
07b0173c
MC		 11445}
11446
11447static void tg3_ints_fini(struct tg3 *tp)
11448{
63c3a66f 11449 if (tg3_flag(tp, USING_MSIX))
679563f4 11450 pci_disable_msix(tp->pdev);
63c3a66f 11451 else if (tg3_flag(tp, USING_MSI))
679563f4 11452 pci_disable_msi(tp->pdev);
63c3a66f
JP		 11453 tg3_flag_clear(tp, USING_MSI);
11454 tg3_flag_clear(tp, USING_MSIX);
11455 tg3_flag_clear(tp, ENABLE_RSS);
11456 tg3_flag_clear(tp, ENABLE_TSS);
07b0173c
MC		 11457}
11458
be947307
MC		 11459static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11460 bool init)
1da177e4 11461{
d8f4cd38 11462 struct net_device *dev = tp->dev;
4f125f42 11463 int i, err;
1da177e4 11464
679563f4
MC		 11465 /*
11466 * Setup interrupts first so we know how
11467 * many NAPI resources to allocate
11468 */
11469 tg3_ints_init(tp);
11470
90415477 11471 tg3_rss_check_indir_tbl(tp);
bcebcc46 11472
1da177e4
LT		 11473 /* The placement of this call is tied
11474 * to the setup and use of Host TX descriptors.
11475 */
11476 err = tg3_alloc_consistent(tp);
11477 if (err)
4a5f46f2 11478 goto out_ints_fini;
88b06bc2 11479
66cfd1bd
MC		 11480 tg3_napi_init(tp);
11481
fed97810 11482 tg3_napi_enable(tp);
1da177e4 11483
4f125f42
MC		 11484 for (i = 0; i < tp->irq_cnt; i++) {
11485 struct tg3_napi *tnapi = &tp->napi[i];
11486 err = tg3_request_irq(tp, i);
11487 if (err) {
5bc09186
MC		 11488 for (i--; i >= 0; i--) {
11489 tnapi = &tp->napi[i];
4f125f42 11490 free_irq(tnapi->irq_vec, tnapi);
5bc09186 11491 }
4a5f46f2 11492 goto out_napi_fini;
4f125f42
MC		 11493 }
11494 }
1da177e4 11495
f47c11ee 11496 tg3_full_lock(tp, 0);
1da177e4 11497
2e460fc0
NS		 11498 if (init)
11499 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11500
d8f4cd38 11501 err = tg3_init_hw(tp, reset_phy);
1da177e4 11502 if (err) {
944d980e 11503 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11504 tg3_free_rings(tp);
1da177e4
LT		 11505 }
11506
f47c11ee 11507 tg3_full_unlock(tp);
1da177e4 11508
07b0173c 11509 if (err)
4a5f46f2 11510 goto out_free_irq;
1da177e4 11511
d8f4cd38 11512 if (test_irq && tg3_flag(tp, USING_MSI)) {
7938109f 11513 err = tg3_test_msi(tp);
fac9b83e 11514
7938109f 11515 if (err) {
f47c11ee 11516 tg3_full_lock(tp, 0);
944d980e 11517 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f 11518 tg3_free_rings(tp);
f47c11ee 11519 tg3_full_unlock(tp);
7938109f 11520
4a5f46f2 11521 goto out_napi_fini;
7938109f 11522 }
fcfa0a32 11523
63c3a66f 11524 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
f6eb9b1f 11525 u32 val = tr32(PCIE_TRANSACTION_CFG);
fcfa0a32 11526
f6eb9b1f
MC		 11527 tw32(PCIE_TRANSACTION_CFG,
11528 val | PCIE_TRANS_CFG_1SHOT_MSI);
fcfa0a32 11529 }
7938109f
MC		 11530 }
11531
b02fd9e3
MC		 11532 tg3_phy_start(tp);
11533
aed93e0b
MC		 11534 tg3_hwmon_open(tp);
11535
f47c11ee 11536 tg3_full_lock(tp, 0);
1da177e4 11537
21f7638e 11538 tg3_timer_start(tp);
63c3a66f 11539 tg3_flag_set(tp, INIT_COMPLETE);
1da177e4
LT		 11540 tg3_enable_ints(tp);
11541
be947307
MC		 11542 if (init)
11543 tg3_ptp_init(tp);
11544 else
11545 tg3_ptp_resume(tp);
11546
11547
f47c11ee 11548 tg3_full_unlock(tp);
1da177e4 11549
fe5f5787 11550 netif_tx_start_all_queues(dev);
1da177e4 11551
06c03c02
MB		 11552 /*
11553 * Reset loopback feature if it was turned on while the device was down
11554 * make sure that it's installed properly now.
11555 */
11556 if (dev->features & NETIF_F_LOOPBACK)
11557 tg3_set_loopback(dev, dev->features);
11558
1da177e4 11559 return 0;
07b0173c 11560
4a5f46f2 11561out_free_irq:
4f125f42
MC		 11562 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11563 struct tg3_napi *tnapi = &tp->napi[i];
11564 free_irq(tnapi->irq_vec, tnapi);
11565 }
07b0173c 11566
4a5f46f2 11567out_napi_fini:
fed97810 11568 tg3_napi_disable(tp);
66cfd1bd 11569 tg3_napi_fini(tp);
07b0173c 11570 tg3_free_consistent(tp);
679563f4 11571
4a5f46f2 11572out_ints_fini:
679563f4 11573 tg3_ints_fini(tp);
d8f4cd38 11574
07b0173c 11575 return err;
1da177e4
LT		 11576}
11577
65138594 11578static void tg3_stop(struct tg3 *tp)
1da177e4 11579{
4f125f42 11580 int i;
1da177e4 11581
db219973 11582 tg3_reset_task_cancel(tp);
bd473da3 11583 tg3_netif_stop(tp);
1da177e4 11584
21f7638e 11585 tg3_timer_stop(tp);
1da177e4 11586
aed93e0b
MC		 11587 tg3_hwmon_close(tp);
11588
24bb4fb6
MC		 11589 tg3_phy_stop(tp);
11590
f47c11ee 11591 tg3_full_lock(tp, 1);
1da177e4
LT		 11592
11593 tg3_disable_ints(tp);
11594
944d980e 11595 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4 11596 tg3_free_rings(tp);
63c3a66f 11597 tg3_flag_clear(tp, INIT_COMPLETE);
1da177e4 11598
f47c11ee 11599 tg3_full_unlock(tp);
1da177e4 11600
4f125f42
MC		 11601 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11602 struct tg3_napi *tnapi = &tp->napi[i];
11603 free_irq(tnapi->irq_vec, tnapi);
11604 }
07b0173c
MC		 11605
11606 tg3_ints_fini(tp);
1da177e4 11607
66cfd1bd
MC		 11608 tg3_napi_fini(tp);
11609
1da177e4 11610 tg3_free_consistent(tp);
65138594
MC		 11611}
11612
d8f4cd38
MC		 11613static int tg3_open(struct net_device *dev)
11614{
11615 struct tg3 *tp = netdev_priv(dev);
11616 int err;
11617
11618 if (tp->fw_needed) {
11619 err = tg3_request_firmware(tp);
c4dab506
NS		 11620 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11621 if (err) {
11622 netdev_warn(tp->dev, "EEE capability disabled\n");
11623 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11624 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11625 netdev_warn(tp->dev, "EEE capability restored\n");
11626 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11627 }
11628 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
d8f4cd38
MC		 11629 if (err)
11630 return err;
11631 } else if (err) {
11632 netdev_warn(tp->dev, "TSO capability disabled\n");
11633 tg3_flag_clear(tp, TSO_CAPABLE);
11634 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11635 netdev_notice(tp->dev, "TSO capability restored\n");
11636 tg3_flag_set(tp, TSO_CAPABLE);
11637 }
11638 }
11639
f4a46d1f 11640 tg3_carrier_off(tp);
d8f4cd38
MC		 11641
11642 err = tg3_power_up(tp);
11643 if (err)
11644 return err;
11645
11646 tg3_full_lock(tp, 0);
11647
11648 tg3_disable_ints(tp);
11649 tg3_flag_clear(tp, INIT_COMPLETE);
11650
11651 tg3_full_unlock(tp);
11652
942d1af0
NS		 11653 err = tg3_start(tp,
11654 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11655 true, true);
d8f4cd38
MC		 11656 if (err) {
11657 tg3_frob_aux_power(tp, false);
11658 pci_set_power_state(tp->pdev, PCI_D3hot);
11659 }
be947307 11660
7d41e49a
MC		 11661 if (tg3_flag(tp, PTP_CAPABLE)) {
11662 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11663 &tp->pdev->dev);
11664 if (IS_ERR(tp->ptp_clock))
11665 tp->ptp_clock = NULL;
11666 }
11667
07b0173c 11668 return err;
1da177e4
LT		 11669}
11670
1da177e4
LT		 11671static int tg3_close(struct net_device *dev)
11672{
11673 struct tg3 *tp = netdev_priv(dev);
11674
be947307
MC		 11675 tg3_ptp_fini(tp);
11676
65138594 11677 tg3_stop(tp);
1da177e4 11678
92feeabf
MC		 11679 /* Clear stats across close / open calls */
11680 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11681 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
1da177e4 11682
8496e85c
RW		 11683 if (pci_device_is_present(tp->pdev)) {
11684 tg3_power_down_prepare(tp);
bc1c7567 11685
8496e85c
RW		 11686 tg3_carrier_off(tp);
11687 }
1da177e4
LT		 11688 return 0;
11689}
11690
511d2224 11691static inline u64 get_stat64(tg3_stat64_t *val)
816f8b86
SB		 11692{
11693 return ((u64)val->high << 32) | ((u64)val->low);
11694}
11695
65ec698d 11696static u64 tg3_calc_crc_errors(struct tg3 *tp)
1da177e4
LT		 11697{
11698 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11699
f07e9af3 11700 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
4153577a
JP		 11701 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11702 tg3_asic_rev(tp) == ASIC_REV_5701)) {
1da177e4
LT		 11703 u32 val;
11704
569a5df8
MC		 11705 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11706 tg3_writephy(tp, MII_TG3_TEST1,
11707 val | MII_TG3_TEST1_CRC_EN);
f08aa1a8 11708 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
1da177e4
LT		 11709 } else
11710 val = 0;
1da177e4
LT		 11711
11712 tp->phy_crc_errors += val;
11713
11714 return tp->phy_crc_errors;
11715 }
11716
11717 return get_stat64(&hw_stats->rx_fcs_errors);
11718}
11719
11720#define ESTAT_ADD(member) \
11721 estats->member = old_estats->member + \
511d2224 11722 get_stat64(&hw_stats->member)
1da177e4 11723
65ec698d 11724static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
1da177e4 11725{
1da177e4
LT		 11726 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11727 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11728
1da177e4
LT		 11729 ESTAT_ADD(rx_octets);
11730 ESTAT_ADD(rx_fragments);
11731 ESTAT_ADD(rx_ucast_packets);
11732 ESTAT_ADD(rx_mcast_packets);
11733 ESTAT_ADD(rx_bcast_packets);
11734 ESTAT_ADD(rx_fcs_errors);
11735 ESTAT_ADD(rx_align_errors);
11736 ESTAT_ADD(rx_xon_pause_rcvd);
11737 ESTAT_ADD(rx_xoff_pause_rcvd);
11738 ESTAT_ADD(rx_mac_ctrl_rcvd);
11739 ESTAT_ADD(rx_xoff_entered);
11740 ESTAT_ADD(rx_frame_too_long_errors);
11741 ESTAT_ADD(rx_jabbers);
11742 ESTAT_ADD(rx_undersize_packets);
11743 ESTAT_ADD(rx_in_length_errors);
11744 ESTAT_ADD(rx_out_length_errors);
11745 ESTAT_ADD(rx_64_or_less_octet_packets);
11746 ESTAT_ADD(rx_65_to_127_octet_packets);
11747 ESTAT_ADD(rx_128_to_255_octet_packets);
11748 ESTAT_ADD(rx_256_to_511_octet_packets);
11749 ESTAT_ADD(rx_512_to_1023_octet_packets);
11750 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11751 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11752 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11753 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11754 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11755
11756 ESTAT_ADD(tx_octets);
11757 ESTAT_ADD(tx_collisions);
11758 ESTAT_ADD(tx_xon_sent);
11759 ESTAT_ADD(tx_xoff_sent);
11760 ESTAT_ADD(tx_flow_control);
11761 ESTAT_ADD(tx_mac_errors);
11762 ESTAT_ADD(tx_single_collisions);
11763 ESTAT_ADD(tx_mult_collisions);
11764 ESTAT_ADD(tx_deferred);
11765 ESTAT_ADD(tx_excessive_collisions);
11766 ESTAT_ADD(tx_late_collisions);
11767 ESTAT_ADD(tx_collide_2times);
11768 ESTAT_ADD(tx_collide_3times);
11769 ESTAT_ADD(tx_collide_4times);
11770 ESTAT_ADD(tx_collide_5times);
11771 ESTAT_ADD(tx_collide_6times);
11772 ESTAT_ADD(tx_collide_7times);
11773 ESTAT_ADD(tx_collide_8times);
11774 ESTAT_ADD(tx_collide_9times);
11775 ESTAT_ADD(tx_collide_10times);
11776 ESTAT_ADD(tx_collide_11times);
11777 ESTAT_ADD(tx_collide_12times);
11778 ESTAT_ADD(tx_collide_13times);
11779 ESTAT_ADD(tx_collide_14times);
11780 ESTAT_ADD(tx_collide_15times);
11781 ESTAT_ADD(tx_ucast_packets);
11782 ESTAT_ADD(tx_mcast_packets);
11783 ESTAT_ADD(tx_bcast_packets);
11784 ESTAT_ADD(tx_carrier_sense_errors);
11785 ESTAT_ADD(tx_discards);
11786 ESTAT_ADD(tx_errors);
11787
11788 ESTAT_ADD(dma_writeq_full);
11789 ESTAT_ADD(dma_write_prioq_full);
11790 ESTAT_ADD(rxbds_empty);
11791 ESTAT_ADD(rx_discards);
11792 ESTAT_ADD(rx_errors);
11793 ESTAT_ADD(rx_threshold_hit);
11794
11795 ESTAT_ADD(dma_readq_full);
11796 ESTAT_ADD(dma_read_prioq_full);
11797 ESTAT_ADD(tx_comp_queue_full);
11798
11799 ESTAT_ADD(ring_set_send_prod_index);
11800 ESTAT_ADD(ring_status_update);
11801 ESTAT_ADD(nic_irqs);
11802 ESTAT_ADD(nic_avoided_irqs);
11803 ESTAT_ADD(nic_tx_threshold_hit);
11804
4452d099 11805 ESTAT_ADD(mbuf_lwm_thresh_hit);
1da177e4
LT		 11806}
11807
65ec698d 11808static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
1da177e4 11809{
511d2224 11810 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
1da177e4
LT		 11811 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11812
1da177e4
LT		 11813 stats->rx_packets = old_stats->rx_packets +
11814 get_stat64(&hw_stats->rx_ucast_packets) +
11815 get_stat64(&hw_stats->rx_mcast_packets) +
11816 get_stat64(&hw_stats->rx_bcast_packets);
6aa20a22 11817
1da177e4
LT		 11818 stats->tx_packets = old_stats->tx_packets +
11819 get_stat64(&hw_stats->tx_ucast_packets) +
11820 get_stat64(&hw_stats->tx_mcast_packets) +
11821 get_stat64(&hw_stats->tx_bcast_packets);
11822
11823 stats->rx_bytes = old_stats->rx_bytes +
11824 get_stat64(&hw_stats->rx_octets);
11825 stats->tx_bytes = old_stats->tx_bytes +
11826 get_stat64(&hw_stats->tx_octets);
11827
11828 stats->rx_errors = old_stats->rx_errors +
4f63b877 11829 get_stat64(&hw_stats->rx_errors);
1da177e4
LT		 11830 stats->tx_errors = old_stats->tx_errors +
11831 get_stat64(&hw_stats->tx_errors) +
11832 get_stat64(&hw_stats->tx_mac_errors) +
11833 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11834 get_stat64(&hw_stats->tx_discards);
11835
11836 stats->multicast = old_stats->multicast +
11837 get_stat64(&hw_stats->rx_mcast_packets);
11838 stats->collisions = old_stats->collisions +
11839 get_stat64(&hw_stats->tx_collisions);
11840
11841 stats->rx_length_errors = old_stats->rx_length_errors +
11842 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11843 get_stat64(&hw_stats->rx_undersize_packets);
11844
1da177e4
LT		 11845 stats->rx_frame_errors = old_stats->rx_frame_errors +
11846 get_stat64(&hw_stats->rx_align_errors);
11847 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11848 get_stat64(&hw_stats->tx_discards);
11849 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11850 get_stat64(&hw_stats->tx_carrier_sense_errors);
11851
11852 stats->rx_crc_errors = old_stats->rx_crc_errors +
65ec698d 11853 tg3_calc_crc_errors(tp);
1da177e4 11854
4f63b877
JL		 11855 stats->rx_missed_errors = old_stats->rx_missed_errors +
11856 get_stat64(&hw_stats->rx_discards);
11857
b0057c51 11858 stats->rx_dropped = tp->rx_dropped;
48855432 11859 stats->tx_dropped = tp->tx_dropped;
1da177e4
LT		 11860}
11861
1da177e4
LT		 11862static int tg3_get_regs_len(struct net_device *dev)
11863{
97bd8e49 11864 return TG3_REG_BLK_SIZE;
1da177e4
LT		 11865}
11866
11867static void tg3_get_regs(struct net_device *dev,
11868 struct ethtool_regs *regs, void *_p)
11869{
1da177e4 11870 struct tg3 *tp = netdev_priv(dev);
1da177e4
LT		 11871
11872 regs->version = 0;
11873
97bd8e49 11874 memset(_p, 0, TG3_REG_BLK_SIZE);
1da177e4 11875
80096068 11876 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
bc1c7567
MC		 11877 return;
11878
f47c11ee 11879 tg3_full_lock(tp, 0);
1da177e4 11880
97bd8e49 11881 tg3_dump_legacy_regs(tp, (u32 *)_p);
1da177e4 11882
f47c11ee 11883 tg3_full_unlock(tp);
1da177e4
LT		 11884}
11885
11886static int tg3_get_eeprom_len(struct net_device *dev)
11887{
11888 struct tg3 *tp = netdev_priv(dev);
11889
11890 return tp->nvram_size;
11891}
11892
1da177e4
LT		 11893static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11894{
11895 struct tg3 *tp = netdev_priv(dev);
11896 int ret;
11897 u8 *pd;
b9fc7dc5 11898 u32 i, offset, len, b_offset, b_count;
a9dc529d 11899 __be32 val;
1da177e4 11900
63c3a66f 11901 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 11902 return -EINVAL;
11903
1da177e4
LT		 11904 offset = eeprom->offset;
11905 len = eeprom->len;
11906 eeprom->len = 0;
11907
11908 eeprom->magic = TG3_EEPROM_MAGIC;
11909
11910 if (offset & 3) {
11911 /* adjustments to start on required 4 byte boundary */
11912 b_offset = offset & 3;
11913 b_count = 4 - b_offset;
11914 if (b_count > len) {
11915 /* i.e. offset=1 len=2 */
11916 b_count = len;
11917 }
a9dc529d 11918 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
1da177e4
LT		 11919 if (ret)
11920 return ret;
be98da6a 11921 memcpy(data, ((char *)&val) + b_offset, b_count);
1da177e4
LT		 11922 len -= b_count;
11923 offset += b_count;
c6cdf436 11924 eeprom->len += b_count;
1da177e4
LT		 11925 }
11926
25985edc 11927 /* read bytes up to the last 4 byte boundary */
1da177e4
LT		 11928 pd = &data[eeprom->len];
11929 for (i = 0; i < (len - (len & 3)); i += 4) {
a9dc529d 11930 ret = tg3_nvram_read_be32(tp, offset + i, &val);
1da177e4
LT		 11931 if (ret) {
11932 eeprom->len += i;
11933 return ret;
11934 }
1da177e4
LT		 11935 memcpy(pd + i, &val, 4);
11936 }
11937 eeprom->len += i;
11938
11939 if (len & 3) {
11940 /* read last bytes not ending on 4 byte boundary */
11941 pd = &data[eeprom->len];
11942 b_count = len & 3;
11943 b_offset = offset + len - b_count;
a9dc529d 11944 ret = tg3_nvram_read_be32(tp, b_offset, &val);
1da177e4
LT		 11945 if (ret)
11946 return ret;
b9fc7dc5 11947 memcpy(pd, &val, b_count);
1da177e4
LT		 11948 eeprom->len += b_count;
11949 }
11950 return 0;
11951}
11952
1da177e4
LT		 11953static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11954{
11955 struct tg3 *tp = netdev_priv(dev);
11956 int ret;
b9fc7dc5 11957 u32 offset, len, b_offset, odd_len;
1da177e4 11958 u8 *buf;
a9dc529d 11959 __be32 start, end;
1da177e4 11960
63c3a66f 11961 if (tg3_flag(tp, NO_NVRAM) ||
df259d8c 11962 eeprom->magic != TG3_EEPROM_MAGIC)
1da177e4
LT		 11963 return -EINVAL;
11964
11965 offset = eeprom->offset;
11966 len = eeprom->len;
11967
11968 if ((b_offset = (offset & 3))) {
11969 /* adjustments to start on required 4 byte boundary */
a9dc529d 11970 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
1da177e4
LT		 11971 if (ret)
11972 return ret;
1da177e4
LT		 11973 len += b_offset;
11974 offset &= ~3;
1c8594b4
MC		 11975 if (len < 4)
11976 len = 4;
1da177e4
LT		 11977 }
11978
11979 odd_len = 0;
1c8594b4 11980 if (len & 3) {
1da177e4
LT		 11981 /* adjustments to end on required 4 byte boundary */
11982 odd_len = 1;
11983 len = (len + 3) & ~3;
a9dc529d 11984 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
1da177e4
LT		 11985 if (ret)
11986 return ret;
1da177e4
LT		 11987 }
11988
11989 buf = data;
11990 if (b_offset || odd_len) {
11991 buf = kmalloc(len, GFP_KERNEL);
ab0049b4 11992 if (!buf)
1da177e4
LT		 11993 return -ENOMEM;
11994 if (b_offset)
11995 memcpy(buf, &start, 4);
11996 if (odd_len)
11997 memcpy(buf+len-4, &end, 4);
11998 memcpy(buf + b_offset, data, eeprom->len);
11999 }
12000
12001 ret = tg3_nvram_write_block(tp, offset, len, buf);
12002
12003 if (buf != data)
12004 kfree(buf);
12005
12006 return ret;
12007}
12008
12009static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12010{
b02fd9e3
MC		 12011 struct tg3 *tp = netdev_priv(dev);
12012
63c3a66f 12013 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12014 struct phy_device *phydev;
f07e9af3 12015 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12016 return -EAGAIN;
ead2402c 12017 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12018 return phy_ethtool_gset(phydev, cmd);
b02fd9e3 12019 }
6aa20a22 12020
1da177e4
LT		 12021 cmd->supported = (SUPPORTED_Autoneg);
12022
f07e9af3 12023 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
1da177e4
LT		 12024 cmd->supported |= (SUPPORTED_1000baseT_Half |
12025 SUPPORTED_1000baseT_Full);
12026
f07e9af3 12027 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
1da177e4
LT		 12028 cmd->supported |= (SUPPORTED_100baseT_Half |
12029 SUPPORTED_100baseT_Full |
12030 SUPPORTED_10baseT_Half |
12031 SUPPORTED_10baseT_Full |
3bebab59 12032 SUPPORTED_TP);
ef348144
KK		 12033 cmd->port = PORT_TP;
12034 } else {
1da177e4 12035 cmd->supported |= SUPPORTED_FIBRE;
ef348144
KK		 12036 cmd->port = PORT_FIBRE;
12037 }
6aa20a22 12038
1da177e4 12039 cmd->advertising = tp->link_config.advertising;
5bb09778
MC		 12040 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12041 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12042 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12043 cmd->advertising |= ADVERTISED_Pause;
12044 } else {
12045 cmd->advertising |= ADVERTISED_Pause |
12046 ADVERTISED_Asym_Pause;
12047 }
12048 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12049 cmd->advertising |= ADVERTISED_Asym_Pause;
12050 }
12051 }
f4a46d1f 12052 if (netif_running(dev) && tp->link_up) {
70739497 12053 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
1da177e4 12054 cmd->duplex = tp->link_config.active_duplex;
859edb26 12055 cmd->lp_advertising = tp->link_config.rmt_adv;
e348c5e7
MC		 12056 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12057 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12058 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12059 else
12060 cmd->eth_tp_mdix = ETH_TP_MDI;
12061 }
64c22182 12062 } else {
e740522e
MC		 12063 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12064 cmd->duplex = DUPLEX_UNKNOWN;
e348c5e7 12065 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
1da177e4 12066 }
882e9793 12067 cmd->phy_address = tp->phy_addr;
7e5856bd 12068 cmd->transceiver = XCVR_INTERNAL;
1da177e4
LT		 12069 cmd->autoneg = tp->link_config.autoneg;
12070 cmd->maxtxpkt = 0;
12071 cmd->maxrxpkt = 0;
12072 return 0;
12073}
6aa20a22 12074
1da177e4
LT		 12075static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12076{
12077 struct tg3 *tp = netdev_priv(dev);
25db0338 12078 u32 speed = ethtool_cmd_speed(cmd);
6aa20a22 12079
63c3a66f 12080 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 12081 struct phy_device *phydev;
f07e9af3 12082 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12083 return -EAGAIN;
ead2402c 12084 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
3f0e3ad7 12085 return phy_ethtool_sset(phydev, cmd);
b02fd9e3
MC		 12086 }
12087
7e5856bd
MC		 12088 if (cmd->autoneg != AUTONEG_ENABLE &&
12089 cmd->autoneg != AUTONEG_DISABLE)
37ff238d 12090 return -EINVAL;
7e5856bd
MC		 12091
12092 if (cmd->autoneg == AUTONEG_DISABLE &&
12093 cmd->duplex != DUPLEX_FULL &&
12094 cmd->duplex != DUPLEX_HALF)
37ff238d 12095 return -EINVAL;
1da177e4 12096
7e5856bd
MC		 12097 if (cmd->autoneg == AUTONEG_ENABLE) {
12098 u32 mask = ADVERTISED_Autoneg |
12099 ADVERTISED_Pause |
12100 ADVERTISED_Asym_Pause;
12101
f07e9af3 12102 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
7e5856bd
MC		 12103 mask |= ADVERTISED_1000baseT_Half |
12104 ADVERTISED_1000baseT_Full;
12105
f07e9af3 12106 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
7e5856bd
MC		 12107 mask |= ADVERTISED_100baseT_Half |
12108 ADVERTISED_100baseT_Full |
12109 ADVERTISED_10baseT_Half |
12110 ADVERTISED_10baseT_Full |
12111 ADVERTISED_TP;
12112 else
12113 mask |= ADVERTISED_FIBRE;
12114
12115 if (cmd->advertising & ~mask)
12116 return -EINVAL;
12117
12118 mask &= (ADVERTISED_1000baseT_Half |
12119 ADVERTISED_1000baseT_Full |
12120 ADVERTISED_100baseT_Half |
12121 ADVERTISED_100baseT_Full |
12122 ADVERTISED_10baseT_Half |
12123 ADVERTISED_10baseT_Full);
12124
12125 cmd->advertising &= mask;
12126 } else {
f07e9af3 12127 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
25db0338 12128 if (speed != SPEED_1000)
7e5856bd
MC		 12129 return -EINVAL;
12130
12131 if (cmd->duplex != DUPLEX_FULL)
12132 return -EINVAL;
12133 } else {
25db0338
DD		 12134 if (speed != SPEED_100 &&
12135 speed != SPEED_10)
7e5856bd
MC		 12136 return -EINVAL;
12137 }
12138 }
12139
f47c11ee 12140 tg3_full_lock(tp, 0);
1da177e4
LT		 12141
12142 tp->link_config.autoneg = cmd->autoneg;
12143 if (cmd->autoneg == AUTONEG_ENABLE) {
405d8e5c
AG		 12144 tp->link_config.advertising = (cmd->advertising |
12145 ADVERTISED_Autoneg);
e740522e
MC		 12146 tp->link_config.speed = SPEED_UNKNOWN;
12147 tp->link_config.duplex = DUPLEX_UNKNOWN;
1da177e4
LT		 12148 } else {
12149 tp->link_config.advertising = 0;
25db0338 12150 tp->link_config.speed = speed;
1da177e4 12151 tp->link_config.duplex = cmd->duplex;
b02fd9e3 12152 }
6aa20a22 12153
fdad8de4
NS		 12154 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12155
ce20f161
NS		 12156 tg3_warn_mgmt_link_flap(tp);
12157
1da177e4 12158 if (netif_running(dev))
953c96e0 12159 tg3_setup_phy(tp, true);
1da177e4 12160
f47c11ee 12161 tg3_full_unlock(tp);
6aa20a22 12162
1da177e4
LT		 12163 return 0;
12164}
6aa20a22 12165
1da177e4
LT		 12166static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12167{
12168 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12169
68aad78c
RJ		 12170 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12171 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12172 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12173 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
1da177e4 12174}
6aa20a22 12175
1da177e4
LT		 12176static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12177{
12178 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12179
63c3a66f 12180 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
a85feb8c
GZ		 12181 wol->supported = WAKE_MAGIC;
12182 else
12183 wol->supported = 0;
1da177e4 12184 wol->wolopts = 0;
63c3a66f 12185 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
1da177e4
LT		 12186 wol->wolopts = WAKE_MAGIC;
12187 memset(&wol->sopass, 0, sizeof(wol->sopass));
12188}
6aa20a22 12189
1da177e4
LT		 12190static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12191{
12192 struct tg3 *tp = netdev_priv(dev);
12dac075 12193 struct device *dp = &tp->pdev->dev;
6aa20a22 12194
1da177e4
LT		 12195 if (wol->wolopts & ~WAKE_MAGIC)
12196 return -EINVAL;
12197 if ((wol->wolopts & WAKE_MAGIC) &&
63c3a66f 12198 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
1da177e4 12199 return -EINVAL;
6aa20a22 12200
f2dc0d18
RW		 12201 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12202
f2dc0d18 12203 if (device_may_wakeup(dp))
63c3a66f 12204 tg3_flag_set(tp, WOL_ENABLE);
f2dc0d18 12205 else
63c3a66f 12206 tg3_flag_clear(tp, WOL_ENABLE);
6aa20a22 12207
1da177e4
LT		 12208 return 0;
12209}
6aa20a22 12210
1da177e4
LT		 12211static u32 tg3_get_msglevel(struct net_device *dev)
12212{
12213 struct tg3 *tp = netdev_priv(dev);
12214 return tp->msg_enable;
12215}
6aa20a22 12216
1da177e4
LT		 12217static void tg3_set_msglevel(struct net_device *dev, u32 value)
12218{
12219 struct tg3 *tp = netdev_priv(dev);
12220 tp->msg_enable = value;
12221}
6aa20a22 12222
1da177e4
LT		 12223static int tg3_nway_reset(struct net_device *dev)
12224{
12225 struct tg3 *tp = netdev_priv(dev);
1da177e4 12226 int r;
6aa20a22 12227
1da177e4
LT		 12228 if (!netif_running(dev))
12229 return -EAGAIN;
12230
f07e9af3 12231 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
c94e3941
MC		 12232 return -EINVAL;
12233
ce20f161
NS		 12234 tg3_warn_mgmt_link_flap(tp);
12235
63c3a66f 12236 if (tg3_flag(tp, USE_PHYLIB)) {
f07e9af3 12237 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 12238 return -EAGAIN;
ead2402c 12239 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
b02fd9e3
MC		 12240 } else {
12241 u32 bmcr;
12242
12243 spin_lock_bh(&tp->lock);
12244 r = -EINVAL;
12245 tg3_readphy(tp, MII_BMCR, &bmcr);
12246 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12247 ((bmcr & BMCR_ANENABLE) ||
f07e9af3 12248 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
b02fd9e3
MC		 12249 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12250 BMCR_ANENABLE);
12251 r = 0;
12252 }
12253 spin_unlock_bh(&tp->lock);
1da177e4 12254 }
6aa20a22 12255
1da177e4
LT		 12256 return r;
12257}
6aa20a22 12258
1da177e4
LT		 12259static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12260{
12261 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12262
2c49a44d 12263 ering->rx_max_pending = tp->rx_std_ring_mask;
63c3a66f 12264 if (tg3_flag(tp, JUMBO_RING_ENABLE))
2c49a44d 12265 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
4f81c32b
MC		 12266 else
12267 ering->rx_jumbo_max_pending = 0;
12268
12269 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
1da177e4
LT		 12270
12271 ering->rx_pending = tp->rx_pending;
63c3a66f 12272 if (tg3_flag(tp, JUMBO_RING_ENABLE))
4f81c32b
MC		 12273 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12274 else
12275 ering->rx_jumbo_pending = 0;
12276
f3f3f27e 12277 ering->tx_pending = tp->napi[0].tx_pending;
1da177e4 12278}
6aa20a22 12279
1da177e4
LT		 12280static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12281{
12282 struct tg3 *tp = netdev_priv(dev);
646c9edd 12283 int i, irq_sync = 0, err = 0;
6aa20a22 12284
2c49a44d
MC		 12285 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12286 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
bc3a9254
MC		 12287 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12288 (ering->tx_pending <= MAX_SKB_FRAGS) ||
63c3a66f 12289 (tg3_flag(tp, TSO_BUG) &&
bc3a9254 12290 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
1da177e4 12291 return -EINVAL;
6aa20a22 12292
bbe832c0 12293 if (netif_running(dev)) {
b02fd9e3 12294 tg3_phy_stop(tp);
1da177e4 12295 tg3_netif_stop(tp);
bbe832c0
MC		 12296 irq_sync = 1;
12297 }
1da177e4 12298
bbe832c0 12299 tg3_full_lock(tp, irq_sync);
6aa20a22 12300
1da177e4
LT		 12301 tp->rx_pending = ering->rx_pending;
12302
63c3a66f 12303 if (tg3_flag(tp, MAX_RXPEND_64) &&
1da177e4
LT		 12304 tp->rx_pending > 63)
12305 tp->rx_pending = 63;
ba67b510
IV		 12306
12307 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12308 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
646c9edd 12309
6fd45cb8 12310 for (i = 0; i < tp->irq_max; i++)
646c9edd 12311 tp->napi[i].tx_pending = ering->tx_pending;
1da177e4
LT		 12312
12313 if (netif_running(dev)) {
944d980e 12314 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12315 err = tg3_restart_hw(tp, false);
b9ec6c1b
MC		 12316 if (!err)
12317 tg3_netif_start(tp);
1da177e4
LT		 12318 }
12319
f47c11ee 12320 tg3_full_unlock(tp);
6aa20a22 12321
b02fd9e3
MC		 12322 if (irq_sync && !err)
12323 tg3_phy_start(tp);
12324
b9ec6c1b 12325 return err;
1da177e4 12326}
6aa20a22 12327
1da177e4
LT		 12328static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12329{
12330 struct tg3 *tp = netdev_priv(dev);
6aa20a22 12331
63c3a66f 12332 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
8d018621 12333
4a2db503 12334 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
8d018621
MC		 12335 epause->rx_pause = 1;
12336 else
12337 epause->rx_pause = 0;
12338
4a2db503 12339 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
8d018621
MC		 12340 epause->tx_pause = 1;
12341 else
12342 epause->tx_pause = 0;
1da177e4 12343}
6aa20a22 12344
1da177e4
LT		 12345static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12346{
12347 struct tg3 *tp = netdev_priv(dev);
b02fd9e3 12348 int err = 0;
6aa20a22 12349
ce20f161
NS		 12350 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12351 tg3_warn_mgmt_link_flap(tp);
12352
63c3a66f 12353 if (tg3_flag(tp, USE_PHYLIB)) {
2712168f
MC		 12354 u32 newadv;
12355 struct phy_device *phydev;
1da177e4 12356
ead2402c 12357 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
f47c11ee 12358
2712168f
MC		 12359 if (!(phydev->supported & SUPPORTED_Pause) ||
12360 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
2259dca3 12361 (epause->rx_pause != epause->tx_pause)))
2712168f 12362 return -EINVAL;
1da177e4 12363
2712168f
MC		 12364 tp->link_config.flowctrl = 0;
12365 if (epause->rx_pause) {
12366 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12367
12368 if (epause->tx_pause) {
12369 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12370 newadv = ADVERTISED_Pause;
b02fd9e3 12371 } else
2712168f
MC		 12372 newadv = ADVERTISED_Pause |
12373 ADVERTISED_Asym_Pause;
12374 } else if (epause->tx_pause) {
12375 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12376 newadv = ADVERTISED_Asym_Pause;
12377 } else
12378 newadv = 0;
12379
12380 if (epause->autoneg)
63c3a66f 12381 tg3_flag_set(tp, PAUSE_AUTONEG);
2712168f 12382 else
63c3a66f 12383 tg3_flag_clear(tp, PAUSE_AUTONEG);
2712168f 12384
f07e9af3 12385 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2712168f
MC		 12386 u32 oldadv = phydev->advertising &
12387 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12388 if (oldadv != newadv) {
12389 phydev->advertising &=
12390 ~(ADVERTISED_Pause |
12391 ADVERTISED_Asym_Pause);
12392 phydev->advertising |= newadv;
12393 if (phydev->autoneg) {
12394 /*
12395 * Always renegotiate the link to
12396 * inform our link partner of our
12397 * flow control settings, even if the
12398 * flow control is forced. Let
12399 * tg3_adjust_link() do the final
12400 * flow control setup.
12401 */
12402 return phy_start_aneg(phydev);
b02fd9e3 12403 }
b02fd9e3 12404 }
b02fd9e3 12405
2712168f 12406 if (!epause->autoneg)
b02fd9e3 12407 tg3_setup_flow_control(tp, 0, 0);
2712168f 12408 } else {
c6700ce2 12409 tp->link_config.advertising &=
2712168f
MC		 12410 ~(ADVERTISED_Pause |
12411 ADVERTISED_Asym_Pause);
c6700ce2 12412 tp->link_config.advertising |= newadv;
b02fd9e3
MC		 12413 }
12414 } else {
12415 int irq_sync = 0;
12416
12417 if (netif_running(dev)) {
12418 tg3_netif_stop(tp);
12419 irq_sync = 1;
12420 }
12421
12422 tg3_full_lock(tp, irq_sync);
12423
12424 if (epause->autoneg)
63c3a66f 12425 tg3_flag_set(tp, PAUSE_AUTONEG);
b02fd9e3 12426 else
63c3a66f 12427 tg3_flag_clear(tp, PAUSE_AUTONEG);
b02fd9e3 12428 if (epause->rx_pause)
e18ce346 12429 tp->link_config.flowctrl |= FLOW_CTRL_RX;
b02fd9e3 12430 else
e18ce346 12431 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
b02fd9e3 12432 if (epause->tx_pause)
e18ce346 12433 tp->link_config.flowctrl |= FLOW_CTRL_TX;
b02fd9e3 12434 else
e18ce346 12435 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
b02fd9e3
MC		 12436
12437 if (netif_running(dev)) {
12438 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
953c96e0 12439 err = tg3_restart_hw(tp, false);
b02fd9e3
MC		 12440 if (!err)
12441 tg3_netif_start(tp);
12442 }
12443
12444 tg3_full_unlock(tp);
12445 }
6aa20a22 12446
fdad8de4
NS		 12447 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12448
b9ec6c1b 12449 return err;
1da177e4 12450}
6aa20a22 12451
de6f31eb 12452static int tg3_get_sset_count(struct net_device *dev, int sset)
1da177e4 12453{
b9f2c044
JG		 12454 switch (sset) {
12455 case ETH_SS_TEST:
12456 return TG3_NUM_TEST;
12457 case ETH_SS_STATS:
12458 return TG3_NUM_STATS;
12459 default:
12460 return -EOPNOTSUPP;
12461 }
4cafd3f5
MC		 12462}
12463
90415477
MC		 12464static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12465 u32 *rules __always_unused)
12466{
12467 struct tg3 *tp = netdev_priv(dev);
12468
12469 if (!tg3_flag(tp, SUPPORT_MSIX))
12470 return -EOPNOTSUPP;
12471
12472 switch (info->cmd) {
12473 case ETHTOOL_GRXRINGS:
12474 if (netif_running(tp->dev))
9102426a 12475 info->data = tp->rxq_cnt;
90415477
MC		 12476 else {
12477 info->data = num_online_cpus();
9102426a
MC		 12478 if (info->data > TG3_RSS_MAX_NUM_QS)
12479 info->data = TG3_RSS_MAX_NUM_QS;
90415477
MC		 12480 }
12481
12482 /* The first interrupt vector only
12483 * handles link interrupts.
12484 */
12485 info->data -= 1;
12486 return 0;
12487
12488 default:
12489 return -EOPNOTSUPP;
12490 }
12491}
12492
12493static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12494{
12495 u32 size = 0;
12496 struct tg3 *tp = netdev_priv(dev);
12497
12498 if (tg3_flag(tp, SUPPORT_MSIX))
12499 size = TG3_RSS_INDIR_TBL_SIZE;
12500
12501 return size;
12502}
12503
12504static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12505{
12506 struct tg3 *tp = netdev_priv(dev);
12507 int i;
12508
12509 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12510 indir[i] = tp->rss_ind_tbl[i];
12511
12512 return 0;
12513}
12514
12515static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12516{
12517 struct tg3 *tp = netdev_priv(dev);
12518 size_t i;
12519
12520 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12521 tp->rss_ind_tbl[i] = indir[i];
12522
12523 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12524 return 0;
12525
12526 /* It is legal to write the indirection
12527 * table while the device is running.
12528 */
12529 tg3_full_lock(tp, 0);
12530 tg3_rss_write_indir_tbl(tp);
12531 tg3_full_unlock(tp);
12532
12533 return 0;
12534}
12535
0968169c
MC		 12536static void tg3_get_channels(struct net_device *dev,
12537 struct ethtool_channels *channel)
12538{
12539 struct tg3 *tp = netdev_priv(dev);
12540 u32 deflt_qs = netif_get_num_default_rss_queues();
12541
12542 channel->max_rx = tp->rxq_max;
12543 channel->max_tx = tp->txq_max;
12544
12545 if (netif_running(dev)) {
12546 channel->rx_count = tp->rxq_cnt;
12547 channel->tx_count = tp->txq_cnt;
12548 } else {
12549 if (tp->rxq_req)
12550 channel->rx_count = tp->rxq_req;
12551 else
12552 channel->rx_count = min(deflt_qs, tp->rxq_max);
12553
12554 if (tp->txq_req)
12555 channel->tx_count = tp->txq_req;
12556 else
12557 channel->tx_count = min(deflt_qs, tp->txq_max);
12558 }
12559}
12560
12561static int tg3_set_channels(struct net_device *dev,
12562 struct ethtool_channels *channel)
12563{
12564 struct tg3 *tp = netdev_priv(dev);
12565
12566 if (!tg3_flag(tp, SUPPORT_MSIX))
12567 return -EOPNOTSUPP;
12568
12569 if (channel->rx_count > tp->rxq_max ||
12570 channel->tx_count > tp->txq_max)
12571 return -EINVAL;
12572
12573 tp->rxq_req = channel->rx_count;
12574 tp->txq_req = channel->tx_count;
12575
12576 if (!netif_running(dev))
12577 return 0;
12578
12579 tg3_stop(tp);
12580
f4a46d1f 12581 tg3_carrier_off(tp);
0968169c 12582
be947307 12583 tg3_start(tp, true, false, false);
0968169c
MC		 12584
12585 return 0;
12586}
12587
de6f31eb 12588static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1da177e4
LT		 12589{
12590 switch (stringset) {
12591 case ETH_SS_STATS:
12592 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
12593 break;
4cafd3f5
MC		 12594 case ETH_SS_TEST:
12595 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
12596 break;
1da177e4
LT		 12597 default:
12598 WARN_ON(1); /* we need a WARN() */
12599 break;
12600 }
12601}
12602
81b8709c 12603static int tg3_set_phys_id(struct net_device *dev,
12604 enum ethtool_phys_id_state state)
4009a93d
MC		 12605{
12606 struct tg3 *tp = netdev_priv(dev);
4009a93d
MC		 12607
12608 if (!netif_running(tp->dev))
12609 return -EAGAIN;
12610
81b8709c 12611 switch (state) {
12612 case ETHTOOL_ID_ACTIVE:
fce55922 12613 return 1; /* cycle on/off once per second */
4009a93d 12614
81b8709c 12615 case ETHTOOL_ID_ON:
12616 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12617 LED_CTRL_1000MBPS_ON |
12618 LED_CTRL_100MBPS_ON |
12619 LED_CTRL_10MBPS_ON |
12620 LED_CTRL_TRAFFIC_OVERRIDE |
12621 LED_CTRL_TRAFFIC_BLINK |
12622 LED_CTRL_TRAFFIC_LED);
12623 break;
6aa20a22 12624
81b8709c 12625 case ETHTOOL_ID_OFF:
12626 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12627 LED_CTRL_TRAFFIC_OVERRIDE);
12628 break;
4009a93d 12629
81b8709c 12630 case ETHTOOL_ID_INACTIVE:
12631 tw32(MAC_LED_CTRL, tp->led_ctrl);
12632 break;
4009a93d 12633 }
81b8709c 12634
4009a93d
MC		 12635 return 0;
12636}
12637
de6f31eb 12638static void tg3_get_ethtool_stats(struct net_device *dev,
1da177e4
LT		 12639 struct ethtool_stats *estats, u64 *tmp_stats)
12640{
12641 struct tg3 *tp = netdev_priv(dev);
0e6c9da3 12642
b546e46f
MC		 12643 if (tp->hw_stats)
12644 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12645 else
12646 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
1da177e4
LT		 12647}
12648
535a490e 12649static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
c3e94500
MC		 12650{
12651 int i;
12652 __be32 *buf;
12653 u32 offset = 0, len = 0;
12654 u32 magic, val;
12655
63c3a66f 12656 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
c3e94500
MC		 12657 return NULL;
12658
12659 if (magic == TG3_EEPROM_MAGIC) {
12660 for (offset = TG3_NVM_DIR_START;
12661 offset < TG3_NVM_DIR_END;
12662 offset += TG3_NVM_DIRENT_SIZE) {
12663 if (tg3_nvram_read(tp, offset, &val))
12664 return NULL;
12665
12666 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12667 TG3_NVM_DIRTYPE_EXTVPD)
12668 break;
12669 }
12670
12671 if (offset != TG3_NVM_DIR_END) {
12672 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12673 if (tg3_nvram_read(tp, offset + 4, &offset))
12674 return NULL;
12675
12676 offset = tg3_nvram_logical_addr(tp, offset);
12677 }
12678 }
12679
12680 if (!offset || !len) {
12681 offset = TG3_NVM_VPD_OFF;
12682 len = TG3_NVM_VPD_LEN;
12683 }
12684
12685 buf = kmalloc(len, GFP_KERNEL);
12686 if (buf == NULL)
12687 return NULL;
12688
12689 if (magic == TG3_EEPROM_MAGIC) {
12690 for (i = 0; i < len; i += 4) {
12691 /* The data is in little-endian format in NVRAM.
12692 * Use the big-endian read routines to preserve
12693 * the byte order as it exists in NVRAM.
12694 */
12695 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12696 goto error;
12697 }
12698 } else {
12699 u8 *ptr;
12700 ssize_t cnt;
12701 unsigned int pos = 0;
12702
12703 ptr = (u8 *)&buf[0];
12704 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12705 cnt = pci_read_vpd(tp->pdev, pos,
12706 len - pos, ptr);
12707 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12708 cnt = 0;
12709 else if (cnt < 0)
12710 goto error;
12711 }
12712 if (pos != len)
12713 goto error;
12714 }
12715
535a490e
MC		 12716 *vpdlen = len;
12717
c3e94500
MC		 12718 return buf;
12719
12720error:
12721 kfree(buf);
12722 return NULL;
12723}
12724
566f86ad 12725#define NVRAM_TEST_SIZE 0x100
a5767dec
MC		 12726#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12727#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12728#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
727a6d9f
MC		 12729#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12730#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
bda18faf 12731#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
b16250e3
MC		 12732#define NVRAM_SELFBOOT_HW_SIZE 0x20
12733#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
566f86ad
MC		 12734
12735static int tg3_test_nvram(struct tg3 *tp)
12736{
535a490e 12737 u32 csum, magic, len;
a9dc529d 12738 __be32 *buf;
ab0049b4 12739 int i, j, k, err = 0, size;
566f86ad 12740
63c3a66f 12741 if (tg3_flag(tp, NO_NVRAM))
df259d8c
MC		 12742 return 0;
12743
e4f34110 12744 if (tg3_nvram_read(tp, 0, &magic) != 0)
1b27777a
MC		 12745 return -EIO;
12746
1b27777a
MC		 12747 if (magic == TG3_EEPROM_MAGIC)
12748 size = NVRAM_TEST_SIZE;
b16250e3 12749 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
a5767dec
MC		 12750 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12751 TG3_EEPROM_SB_FORMAT_1) {
12752 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12753 case TG3_EEPROM_SB_REVISION_0:
12754 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12755 break;
12756 case TG3_EEPROM_SB_REVISION_2:
12757 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12758 break;
12759 case TG3_EEPROM_SB_REVISION_3:
12760 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12761 break;
727a6d9f
MC		 12762 case TG3_EEPROM_SB_REVISION_4:
12763 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12764 break;
12765 case TG3_EEPROM_SB_REVISION_5:
12766 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12767 break;
12768 case TG3_EEPROM_SB_REVISION_6:
12769 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12770 break;
a5767dec 12771 default:
727a6d9f 12772 return -EIO;
a5767dec
MC		 12773 }
12774 } else
1b27777a 12775 return 0;
b16250e3
MC		 12776 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12777 size = NVRAM_SELFBOOT_HW_SIZE;
12778 else
1b27777a
MC		 12779 return -EIO;
12780
12781 buf = kmalloc(size, GFP_KERNEL);
566f86ad
MC		 12782 if (buf == NULL)
12783 return -ENOMEM;
12784
1b27777a
MC		 12785 err = -EIO;
12786 for (i = 0, j = 0; i < size; i += 4, j++) {
a9dc529d
MC		 12787 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12788 if (err)
566f86ad 12789 break;
566f86ad 12790 }
1b27777a 12791 if (i < size)
566f86ad
MC		 12792 goto out;
12793
1b27777a 12794 /* Selfboot format */
a9dc529d 12795 magic = be32_to_cpu(buf[0]);
b9fc7dc5 12796 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
b16250e3 12797 TG3_EEPROM_MAGIC_FW) {
1b27777a
MC		 12798 u8 *buf8 = (u8 *) buf, csum8 = 0;
12799
b9fc7dc5 12800 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
a5767dec
MC		 12801 TG3_EEPROM_SB_REVISION_2) {
12802 /* For rev 2, the csum doesn't include the MBA. */
12803 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12804 csum8 += buf8[i];
12805 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12806 csum8 += buf8[i];
12807 } else {
12808 for (i = 0; i < size; i++)
12809 csum8 += buf8[i];
12810 }
1b27777a 12811
ad96b485
AB		 12812 if (csum8 == 0) {
12813 err = 0;
12814 goto out;
12815 }
12816
12817 err = -EIO;
12818 goto out;
1b27777a 12819 }
566f86ad 12820
b9fc7dc5 12821 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
b16250e3
MC		 12822 TG3_EEPROM_MAGIC_HW) {
12823 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
a9dc529d 12824 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
b16250e3 12825 u8 *buf8 = (u8 *) buf;
b16250e3
MC		 12826
12827 /* Separate the parity bits and the data bytes. */
12828 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12829 if ((i == 0) || (i == 8)) {
12830 int l;
12831 u8 msk;
12832
12833 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12834 parity[k++] = buf8[i] & msk;
12835 i++;
859a5887 12836 } else if (i == 16) {
b16250e3
MC		 12837 int l;
12838 u8 msk;
12839
12840 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12841 parity[k++] = buf8[i] & msk;
12842 i++;
12843
12844 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12845 parity[k++] = buf8[i] & msk;
12846 i++;
12847 }
12848 data[j++] = buf8[i];
12849 }
12850
12851 err = -EIO;
12852 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12853 u8 hw8 = hweight8(data[i]);
12854
12855 if ((hw8 & 0x1) && parity[i])
12856 goto out;
12857 else if (!(hw8 & 0x1) && !parity[i])
12858 goto out;
12859 }
12860 err = 0;
12861 goto out;
12862 }
12863
01c3a392
MC		 12864 err = -EIO;
12865
566f86ad
MC		 12866 /* Bootstrap checksum at offset 0x10 */
12867 csum = calc_crc((unsigned char *) buf, 0x10);
01c3a392 12868 if (csum != le32_to_cpu(buf[0x10/4]))
566f86ad
MC		 12869 goto out;
12870
12871 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12872 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
01c3a392 12873 if (csum != le32_to_cpu(buf[0xfc/4]))
a9dc529d 12874 goto out;
566f86ad 12875
c3e94500
MC		 12876 kfree(buf);
12877
535a490e 12878 buf = tg3_vpd_readblock(tp, &len);
c3e94500
MC		 12879 if (!buf)
12880 return -ENOMEM;
d4894f3e 12881
535a490e 12882 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
d4894f3e
MC		 12883 if (i > 0) {
12884 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12885 if (j < 0)
12886 goto out;
12887
535a490e 12888 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
d4894f3e
MC		 12889 goto out;
12890
12891 i += PCI_VPD_LRDT_TAG_SIZE;
12892 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12893 PCI_VPD_RO_KEYWORD_CHKSUM);
12894 if (j > 0) {
12895 u8 csum8 = 0;
12896
12897 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12898
12899 for (i = 0; i <= j; i++)
12900 csum8 += ((u8 *)buf)[i];
12901
12902 if (csum8)
12903 goto out;
12904 }
12905 }
12906
566f86ad
MC		 12907 err = 0;
12908
12909out:
12910 kfree(buf);
12911 return err;
12912}
12913
ca43007a
MC		 12914#define TG3_SERDES_TIMEOUT_SEC 2
12915#define TG3_COPPER_TIMEOUT_SEC 6
12916
12917static int tg3_test_link(struct tg3 *tp)
12918{
12919 int i, max;
12920
12921 if (!netif_running(tp->dev))
12922 return -ENODEV;
12923
f07e9af3 12924 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
ca43007a
MC		 12925 max = TG3_SERDES_TIMEOUT_SEC;
12926 else
12927 max = TG3_COPPER_TIMEOUT_SEC;
12928
12929 for (i = 0; i < max; i++) {
f4a46d1f 12930 if (tp->link_up)
ca43007a
MC		 12931 return 0;
12932
12933 if (msleep_interruptible(1000))
12934 break;
12935 }
12936
12937 return -EIO;
12938}
12939
a71116d1 12940/* Only test the commonly used registers */
30ca3e37 12941static int tg3_test_registers(struct tg3 *tp)
a71116d1 12942{
b16250e3 12943 int i, is_5705, is_5750;
a71116d1
MC		 12944 u32 offset, read_mask, write_mask, val, save_val, read_val;
12945 static struct {
12946 u16 offset;
12947 u16 flags;
12948#define TG3_FL_5705 0x1
12949#define TG3_FL_NOT_5705 0x2
12950#define TG3_FL_NOT_5788 0x4
b16250e3 12951#define TG3_FL_NOT_5750 0x8
a71116d1
MC		 12952 u32 read_mask;
12953 u32 write_mask;
12954 } reg_tbl[] = {
12955 /* MAC Control Registers */
12956 { MAC_MODE, TG3_FL_NOT_5705,
12957 0x00000000, 0x00ef6f8c },
12958 { MAC_MODE, TG3_FL_5705,
12959 0x00000000, 0x01ef6b8c },
12960 { MAC_STATUS, TG3_FL_NOT_5705,
12961 0x03800107, 0x00000000 },
12962 { MAC_STATUS, TG3_FL_5705,
12963 0x03800100, 0x00000000 },
12964 { MAC_ADDR_0_HIGH, 0x0000,
12965 0x00000000, 0x0000ffff },
12966 { MAC_ADDR_0_LOW, 0x0000,
c6cdf436 12967 0x00000000, 0xffffffff },
a71116d1
MC		 12968 { MAC_RX_MTU_SIZE, 0x0000,
12969 0x00000000, 0x0000ffff },
12970 { MAC_TX_MODE, 0x0000,
12971 0x00000000, 0x00000070 },
12972 { MAC_TX_LENGTHS, 0x0000,
12973 0x00000000, 0x00003fff },
12974 { MAC_RX_MODE, TG3_FL_NOT_5705,
12975 0x00000000, 0x000007fc },
12976 { MAC_RX_MODE, TG3_FL_5705,
12977 0x00000000, 0x000007dc },
12978 { MAC_HASH_REG_0, 0x0000,
12979 0x00000000, 0xffffffff },
12980 { MAC_HASH_REG_1, 0x0000,
12981 0x00000000, 0xffffffff },
12982 { MAC_HASH_REG_2, 0x0000,
12983 0x00000000, 0xffffffff },
12984 { MAC_HASH_REG_3, 0x0000,
12985 0x00000000, 0xffffffff },
12986
12987 /* Receive Data and Receive BD Initiator Control Registers. */
12988 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12989 0x00000000, 0xffffffff },
12990 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12991 0x00000000, 0xffffffff },
12992 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12993 0x00000000, 0x00000003 },
12994 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12995 0x00000000, 0xffffffff },
12996 { RCVDBDI_STD_BD+0, 0x0000,
12997 0x00000000, 0xffffffff },
12998 { RCVDBDI_STD_BD+4, 0x0000,
12999 0x00000000, 0xffffffff },
13000 { RCVDBDI_STD_BD+8, 0x0000,
13001 0x00000000, 0xffff0002 },
13002 { RCVDBDI_STD_BD+0xc, 0x0000,
13003 0x00000000, 0xffffffff },
6aa20a22 13004
a71116d1
MC		 13005 /* Receive BD Initiator Control Registers. */
13006 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13007 0x00000000, 0xffffffff },
13008 { RCVBDI_STD_THRESH, TG3_FL_5705,
13009 0x00000000, 0x000003ff },
13010 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13011 0x00000000, 0xffffffff },
6aa20a22 13012
a71116d1
MC		 13013 /* Host Coalescing Control Registers. */
13014 { HOSTCC_MODE, TG3_FL_NOT_5705,
13015 0x00000000, 0x00000004 },
13016 { HOSTCC_MODE, TG3_FL_5705,
13017 0x00000000, 0x000000f6 },
13018 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13019 0x00000000, 0xffffffff },
13020 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13021 0x00000000, 0x000003ff },
13022 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13023 0x00000000, 0xffffffff },
13024 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13025 0x00000000, 0x000003ff },
13026 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13027 0x00000000, 0xffffffff },
13028 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13029 0x00000000, 0x000000ff },
13030 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13031 0x00000000, 0xffffffff },
13032 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13033 0x00000000, 0x000000ff },
13034 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13035 0x00000000, 0xffffffff },
13036 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13037 0x00000000, 0xffffffff },
13038 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13039 0x00000000, 0xffffffff },
13040 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13041 0x00000000, 0x000000ff },
13042 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13043 0x00000000, 0xffffffff },
13044 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13045 0x00000000, 0x000000ff },
13046 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13047 0x00000000, 0xffffffff },
13048 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13049 0x00000000, 0xffffffff },
13050 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13051 0x00000000, 0xffffffff },
13052 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13053 0x00000000, 0xffffffff },
13054 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13055 0x00000000, 0xffffffff },
13056 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13057 0xffffffff, 0x00000000 },
13058 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13059 0xffffffff, 0x00000000 },
13060
13061 /* Buffer Manager Control Registers. */
b16250e3 13062 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
a71116d1 13063 0x00000000, 0x007fff80 },
b16250e3 13064 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
a71116d1
MC		 13065 0x00000000, 0x007fffff },
13066 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13067 0x00000000, 0x0000003f },
13068 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13069 0x00000000, 0x000001ff },
13070 { BUFMGR_MB_HIGH_WATER, 0x0000,
13071 0x00000000, 0x000001ff },
13072 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13073 0xffffffff, 0x00000000 },
13074 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13075 0xffffffff, 0x00000000 },
6aa20a22 13076
a71116d1
MC		 13077 /* Mailbox Registers */
13078 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13079 0x00000000, 0x000001ff },
13080 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13081 0x00000000, 0x000001ff },
13082 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13083 0x00000000, 0x000007ff },
13084 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13085 0x00000000, 0x000001ff },
13086
13087 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13088 };
13089
b16250e3 13090 is_5705 = is_5750 = 0;
63c3a66f 13091 if (tg3_flag(tp, 5705_PLUS)) {
a71116d1 13092 is_5705 = 1;
63c3a66f 13093 if (tg3_flag(tp, 5750_PLUS))
b16250e3
MC		 13094 is_5750 = 1;
13095 }
a71116d1
MC		 13096
13097 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13098 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13099 continue;
13100
13101 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13102 continue;
13103
63c3a66f 13104 if (tg3_flag(tp, IS_5788) &&
a71116d1
MC		 13105 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13106 continue;
13107
b16250e3
MC		 13108 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13109 continue;
13110
a71116d1
MC		 13111 offset = (u32) reg_tbl[i].offset;
13112 read_mask = reg_tbl[i].read_mask;
13113 write_mask = reg_tbl[i].write_mask;
13114
13115 /* Save the original register content */
13116 save_val = tr32(offset);
13117
13118 /* Determine the read-only value. */
13119 read_val = save_val & read_mask;
13120
13121 /* Write zero to the register, then make sure the read-only bits
13122 * are not changed and the read/write bits are all zeros.
13123 */
13124 tw32(offset, 0);
13125
13126 val = tr32(offset);
13127
13128 /* Test the read-only and read/write bits. */
13129 if (((val & read_mask) != read_val) || (val & write_mask))
13130 goto out;
13131
13132 /* Write ones to all the bits defined by RdMask and WrMask, then
13133 * make sure the read-only bits are not changed and the
13134 * read/write bits are all ones.
13135 */
13136 tw32(offset, read_mask | write_mask);
13137
13138 val = tr32(offset);
13139
13140 /* Test the read-only bits. */
13141 if ((val & read_mask) != read_val)
13142 goto out;
13143
13144 /* Test the read/write bits. */
13145 if ((val & write_mask) != write_mask)
13146 goto out;
13147
13148 tw32(offset, save_val);
13149 }
13150
13151 return 0;
13152
13153out:
9f88f29f 13154 if (netif_msg_hw(tp))
2445e461
MC		 13155 netdev_err(tp->dev,
13156 "Register test failed at offset %x\n", offset);
a71116d1
MC		 13157 tw32(offset, save_val);
13158 return -EIO;
13159}
13160
7942e1db
MC		 13161static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13162{
f71e1309 13163 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7942e1db
MC		 13164 int i;
13165 u32 j;
13166
e9edda69 13167 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
7942e1db
MC		 13168 for (j = 0; j < len; j += 4) {
13169 u32 val;
13170
13171 tg3_write_mem(tp, offset + j, test_pattern[i]);
13172 tg3_read_mem(tp, offset + j, &val);
13173 if (val != test_pattern[i])
13174 return -EIO;
13175 }
13176 }
13177 return 0;
13178}
13179
13180static int tg3_test_memory(struct tg3 *tp)
13181{
13182 static struct mem_entry {
13183 u32 offset;
13184 u32 len;
13185 } mem_tbl_570x[] = {
38690194 13186 { 0x00000000, 0x00b50},
7942e1db
MC		 13187 { 0x00002000, 0x1c000},
13188 { 0xffffffff, 0x00000}
13189 }, mem_tbl_5705[] = {
13190 { 0x00000100, 0x0000c},
13191 { 0x00000200, 0x00008},
7942e1db
MC		 13192 { 0x00004000, 0x00800},
13193 { 0x00006000, 0x01000},
13194 { 0x00008000, 0x02000},
13195 { 0x00010000, 0x0e000},
13196 { 0xffffffff, 0x00000}
79f4d13a
MC		 13197 }, mem_tbl_5755[] = {
13198 { 0x00000200, 0x00008},
13199 { 0x00004000, 0x00800},
13200 { 0x00006000, 0x00800},
13201 { 0x00008000, 0x02000},
13202 { 0x00010000, 0x0c000},
13203 { 0xffffffff, 0x00000}
b16250e3
MC		 13204 }, mem_tbl_5906[] = {
13205 { 0x00000200, 0x00008},
13206 { 0x00004000, 0x00400},
13207 { 0x00006000, 0x00400},
13208 { 0x00008000, 0x01000},
13209 { 0x00010000, 0x01000},
13210 { 0xffffffff, 0x00000}
8b5a6c42
MC		 13211 }, mem_tbl_5717[] = {
13212 { 0x00000200, 0x00008},
13213 { 0x00010000, 0x0a000},
13214 { 0x00020000, 0x13c00},
13215 { 0xffffffff, 0x00000}
13216 }, mem_tbl_57765[] = {
13217 { 0x00000200, 0x00008},
13218 { 0x00004000, 0x00800},
13219 { 0x00006000, 0x09800},
13220 { 0x00010000, 0x0a000},
13221 { 0xffffffff, 0x00000}
7942e1db
MC		 13222 };
13223 struct mem_entry *mem_tbl;
13224 int err = 0;
13225 int i;
13226
63c3a66f 13227 if (tg3_flag(tp, 5717_PLUS))
8b5a6c42 13228 mem_tbl = mem_tbl_5717;
c65a17f4 13229 else if (tg3_flag(tp, 57765_CLASS) ||
4153577a 13230 tg3_asic_rev(tp) == ASIC_REV_5762)
8b5a6c42 13231 mem_tbl = mem_tbl_57765;
63c3a66f 13232 else if (tg3_flag(tp, 5755_PLUS))
321d32a0 13233 mem_tbl = mem_tbl_5755;
4153577a 13234 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
321d32a0 13235 mem_tbl = mem_tbl_5906;
63c3a66f 13236 else if (tg3_flag(tp, 5705_PLUS))
321d32a0
MC		 13237 mem_tbl = mem_tbl_5705;
13238 else
7942e1db
MC		 13239 mem_tbl = mem_tbl_570x;
13240
13241 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
be98da6a
MC		 13242 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13243 if (err)
7942e1db
MC		 13244 break;
13245 }
6aa20a22 13246
7942e1db
MC		 13247 return err;
13248}
13249
bb158d69
MC		 13250#define TG3_TSO_MSS 500
13251
13252#define TG3_TSO_IP_HDR_LEN 20
13253#define TG3_TSO_TCP_HDR_LEN 20
13254#define TG3_TSO_TCP_OPT_LEN 12
13255
13256static const u8 tg3_tso_header[] = {
132570x08, 0x00,
132580x45, 0x00, 0x00, 0x00,
132590x00, 0x00, 0x40, 0x00,
132600x40, 0x06, 0x00, 0x00,
132610x0a, 0x00, 0x00, 0x01,
132620x0a, 0x00, 0x00, 0x02,
132630x0d, 0x00, 0xe0, 0x00,
132640x00, 0x00, 0x01, 0x00,
132650x00, 0x00, 0x02, 0x00,
132660x80, 0x10, 0x10, 0x00,
132670x14, 0x09, 0x00, 0x00,
132680x01, 0x01, 0x08, 0x0a,
132690x11, 0x11, 0x11, 0x11,
132700x11, 0x11, 0x11, 0x11,
13271};
9f40dead 13272
28a45957 13273static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
c76949a6 13274{
5e5a7f37 13275 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
bb158d69 13276 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
84b67b27 13277 u32 budget;
9205fd9c
ED		 13278 struct sk_buff *skb;
13279 u8 *tx_data, *rx_data;
c76949a6
MC		 13280 dma_addr_t map;
13281 int num_pkts, tx_len, rx_len, i, err;
13282 struct tg3_rx_buffer_desc *desc;
898a56f8 13283 struct tg3_napi *tnapi, *rnapi;
8fea32b9 13284 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
c76949a6 13285
c8873405
MC		 13286 tnapi = &tp->napi[0];
13287 rnapi = &tp->napi[0];
0c1d0e2b 13288 if (tp->irq_cnt > 1) {
63c3a66f 13289 if (tg3_flag(tp, ENABLE_RSS))
1da85aa3 13290 rnapi = &tp->napi[1];
63c3a66f 13291 if (tg3_flag(tp, ENABLE_TSS))
c8873405 13292 tnapi = &tp->napi[1];
0c1d0e2b 13293 }
fd2ce37f 13294 coal_now = tnapi->coal_now | rnapi->coal_now;
898a56f8 13295
c76949a6
MC		 13296 err = -EIO;
13297
4852a861 13298 tx_len = pktsz;
a20e9c62 13299 skb = netdev_alloc_skb(tp->dev, tx_len);
a50bb7b9
JJ		 13300 if (!skb)
13301 return -ENOMEM;
13302
c76949a6 13303 tx_data = skb_put(skb, tx_len);
d458cdf7
JP		 13304 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13305 memset(tx_data + ETH_ALEN, 0x0, 8);
c76949a6 13306
4852a861 13307 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
c76949a6 13308
28a45957 13309 if (tso_loopback) {
bb158d69
MC		 13310 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13311
13312 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13313 TG3_TSO_TCP_OPT_LEN;
13314
13315 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13316 sizeof(tg3_tso_header));
13317 mss = TG3_TSO_MSS;
13318
13319 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13320 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13321
13322 /* Set the total length field in the IP header */
13323 iph->tot_len = htons((u16)(mss + hdr_len));
13324
13325 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13326 TXD_FLAG_CPU_POST_DMA);
13327
63c3a66f
JP		 13328 if (tg3_flag(tp, HW_TSO_1) ||
13329 tg3_flag(tp, HW_TSO_2) ||
13330 tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13331 struct tcphdr *th;
13332 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13333 th = (struct tcphdr *)&tx_data[val];
13334 th->check = 0;
13335 } else
13336 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13337
63c3a66f 13338 if (tg3_flag(tp, HW_TSO_3)) {
bb158d69
MC		 13339 mss |= (hdr_len & 0xc) << 12;
13340 if (hdr_len & 0x10)
13341 base_flags |= 0x00000010;
13342 base_flags |= (hdr_len & 0x3e0) << 5;
63c3a66f 13343 } else if (tg3_flag(tp, HW_TSO_2))
bb158d69 13344 mss |= hdr_len << 9;
63c3a66f 13345 else if (tg3_flag(tp, HW_TSO_1) ||
4153577a 13346 tg3_asic_rev(tp) == ASIC_REV_5705) {
bb158d69
MC		 13347 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13348 } else {
13349 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13350 }
13351
13352 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13353 } else {
13354 num_pkts = 1;
13355 data_off = ETH_HLEN;
c441b456
MC		 13356
13357 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13358 tx_len > VLAN_ETH_FRAME_LEN)
13359 base_flags |= TXD_FLAG_JMB_PKT;
bb158d69
MC		 13360 }
13361
13362 for (i = data_off; i < tx_len; i++)
c76949a6
MC		 13363 tx_data[i] = (u8) (i & 0xff);
13364
f4188d8a
AD		 13365 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13366 if (pci_dma_mapping_error(tp->pdev, map)) {
a21771dd
MC		 13367 dev_kfree_skb(skb);
13368 return -EIO;
13369 }
c76949a6 13370
0d681b27
MC		 13371 val = tnapi->tx_prod;
13372 tnapi->tx_buffers[val].skb = skb;
13373 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13374
c76949a6 13375 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13376 rnapi->coal_now);
c76949a6
MC		 13377
13378 udelay(10);
13379
898a56f8 13380 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
c76949a6 13381
84b67b27
MC		 13382 budget = tg3_tx_avail(tnapi);
13383 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
d1a3b737
MC		 13384 base_flags | TXD_FLAG_END, mss, 0)) {
13385 tnapi->tx_buffers[val].skb = NULL;
13386 dev_kfree_skb(skb);
13387 return -EIO;
13388 }
c76949a6 13389
f3f3f27e 13390 tnapi->tx_prod++;
c76949a6 13391
6541b806
MC		 13392 /* Sync BD data before updating mailbox */
13393 wmb();
13394
f3f3f27e
MC		 13395 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13396 tr32_mailbox(tnapi->prodmbox);
c76949a6
MC		 13397
13398 udelay(10);
13399
303fc921
MC		 13400 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13401 for (i = 0; i < 35; i++) {
c76949a6 13402 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
fd2ce37f 13403 coal_now);
c76949a6
MC		 13404
13405 udelay(10);
13406
898a56f8
MC		 13407 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13408 rx_idx = rnapi->hw_status->idx[0].rx_producer;
f3f3f27e 13409 if ((tx_idx == tnapi->tx_prod) &&
c76949a6
MC		 13410 (rx_idx == (rx_start_idx + num_pkts)))
13411 break;
13412 }
13413
ba1142e4 13414 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
c76949a6
MC		 13415 dev_kfree_skb(skb);
13416
f3f3f27e 13417 if (tx_idx != tnapi->tx_prod)
c76949a6
MC		 13418 goto out;
13419
13420 if (rx_idx != rx_start_idx + num_pkts)
13421 goto out;
13422
bb158d69
MC		 13423 val = data_off;
13424 while (rx_idx != rx_start_idx) {
13425 desc = &rnapi->rx_rcb[rx_start_idx++];
13426 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13427 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
c76949a6 13428
bb158d69
MC		 13429 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13430 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13431 goto out;
c76949a6 13432
bb158d69
MC		 13433 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13434 - ETH_FCS_LEN;
c76949a6 13435
28a45957 13436 if (!tso_loopback) {
bb158d69
MC		 13437 if (rx_len != tx_len)
13438 goto out;
4852a861 13439
bb158d69
MC		 13440 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13441 if (opaque_key != RXD_OPAQUE_RING_STD)
13442 goto out;
13443 } else {
13444 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13445 goto out;
13446 }
13447 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13448 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
54e0a67f 13449 >> RXD_TCPCSUM_SHIFT != 0xffff) {
4852a861 13450 goto out;
bb158d69 13451 }
4852a861 13452
bb158d69 13453 if (opaque_key == RXD_OPAQUE_RING_STD) {
9205fd9c 13454 rx_data = tpr->rx_std_buffers[desc_idx].data;
bb158d69
MC		 13455 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13456 mapping);
13457 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
9205fd9c 13458 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
bb158d69
MC		 13459 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13460 mapping);
13461 } else
13462 goto out;
c76949a6 13463
bb158d69
MC		 13464 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13465 PCI_DMA_FROMDEVICE);
c76949a6 13466
9205fd9c 13467 rx_data += TG3_RX_OFFSET(tp);
bb158d69 13468 for (i = data_off; i < rx_len; i++, val++) {
9205fd9c 13469 if (*(rx_data + i) != (u8) (val & 0xff))
bb158d69
MC		 13470 goto out;
13471 }
c76949a6 13472 }
bb158d69 13473
c76949a6 13474 err = 0;
6aa20a22 13475
9205fd9c 13476 /* tg3_free_rings will unmap and free the rx_data */
c76949a6
MC		 13477out:
13478 return err;
13479}
13480
00c266b7
MC		 13481#define TG3_STD_LOOPBACK_FAILED 1
13482#define TG3_JMB_LOOPBACK_FAILED 2
bb158d69 13483#define TG3_TSO_LOOPBACK_FAILED 4
28a45957
MC		 13484#define TG3_LOOPBACK_FAILED \
13485 (TG3_STD_LOOPBACK_FAILED | \
13486 TG3_JMB_LOOPBACK_FAILED | \
13487 TG3_TSO_LOOPBACK_FAILED)
00c266b7 13488
941ec90f 13489static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
9f40dead 13490{
28a45957 13491 int err = -EIO;
2215e24c 13492 u32 eee_cap;
c441b456
MC		 13493 u32 jmb_pkt_sz = 9000;
13494
13495 if (tp->dma_limit)
13496 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
9f40dead 13497
ab789046
MC		 13498 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13499 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13500
28a45957 13501 if (!netif_running(tp->dev)) {
93df8b8f
NNS		 13502 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13503 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13504 if (do_extlpbk)
93df8b8f 13505 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
28a45957
MC		 13506 goto done;
13507 }
13508
953c96e0 13509 err = tg3_reset_hw(tp, true);
ab789046 13510 if (err) {
93df8b8f
NNS		 13511 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13512 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
941ec90f 13513 if (do_extlpbk)
93df8b8f 13514 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
ab789046
MC		 13515 goto done;
13516 }
9f40dead 13517
63c3a66f 13518 if (tg3_flag(tp, ENABLE_RSS)) {
4a85f098
MC		 13519 int i;
13520
13521 /* Reroute all rx packets to the 1st queue */
13522 for (i = MAC_RSS_INDIR_TBL_0;
13523 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13524 tw32(i, 0x0);
13525 }
13526
6e01b20b
MC		 13527 /* HW errata - mac loopback fails in some cases on 5780.
13528 * Normal traffic and PHY loopback are not affected by
13529 * errata. Also, the MAC loopback test is deprecated for
13530 * all newer ASIC revisions.
13531 */
4153577a 13532 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
6e01b20b
MC		 13533 !tg3_flag(tp, CPMU_PRESENT)) {
13534 tg3_mac_loopback(tp, true);
9936bcf6 13535
28a45957 13536 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13537 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
6e01b20b
MC		 13538
13539 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13540 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13541 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
6e01b20b
MC		 13542
13543 tg3_mac_loopback(tp, false);
13544 }
4852a861 13545
f07e9af3 13546 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
63c3a66f 13547 !tg3_flag(tp, USE_PHYLIB)) {
5e5a7f37
MC		 13548 int i;
13549
941ec90f 13550 tg3_phy_lpbk_set(tp, 0, false);
5e5a7f37
MC		 13551
13552 /* Wait for link */
13553 for (i = 0; i < 100; i++) {
13554 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13555 break;
13556 mdelay(1);
13557 }
13558
28a45957 13559 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f 13560 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
63c3a66f 13561 if (tg3_flag(tp, TSO_CAPABLE) &&
28a45957 13562 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f 13563 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
63c3a66f 13564 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13565 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f 13566 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
9f40dead 13567
941ec90f
MC		 13568 if (do_extlpbk) {
13569 tg3_phy_lpbk_set(tp, 0, true);
13570
13571 /* All link indications report up, but the hardware
13572 * isn't really ready for about 20 msec. Double it
13573 * to be sure.
13574 */
13575 mdelay(40);
13576
13577 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
93df8b8f
NNS		 13578 data[TG3_EXT_LOOPB_TEST] |=
13579 TG3_STD_LOOPBACK_FAILED;
941ec90f
MC		 13580 if (tg3_flag(tp, TSO_CAPABLE) &&
13581 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
93df8b8f
NNS		 13582 data[TG3_EXT_LOOPB_TEST] |=
13583 TG3_TSO_LOOPBACK_FAILED;
941ec90f 13584 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
c441b456 13585 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
93df8b8f
NNS		 13586 data[TG3_EXT_LOOPB_TEST] |=
13587 TG3_JMB_LOOPBACK_FAILED;
941ec90f
MC		 13588 }
13589
5e5a7f37
MC		 13590 /* Re-enable gphy autopowerdown. */
13591 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13592 tg3_phy_toggle_apd(tp, true);
13593 }
6833c043 13594
93df8b8f
NNS		 13595 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13596 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
28a45957 13597
ab789046
MC		 13598done:
13599 tp->phy_flags |= eee_cap;
13600
9f40dead
MC		 13601 return err;
13602}
13603
4cafd3f5
MC		 13604static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13605 u64 *data)
13606{
566f86ad 13607 struct tg3 *tp = netdev_priv(dev);
941ec90f 13608 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
566f86ad 13609
2e460fc0
NS		 13610 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13611 if (tg3_power_up(tp)) {
13612 etest->flags |= ETH_TEST_FL_FAILED;
13613 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13614 return;
13615 }
13616 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
bed9829f 13617 }
bc1c7567 13618
566f86ad
MC		 13619 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13620
13621 if (tg3_test_nvram(tp) != 0) {
13622 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13623 data[TG3_NVRAM_TEST] = 1;
566f86ad 13624 }
941ec90f 13625 if (!doextlpbk && tg3_test_link(tp)) {
ca43007a 13626 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13627 data[TG3_LINK_TEST] = 1;
ca43007a 13628 }
a71116d1 13629 if (etest->flags & ETH_TEST_FL_OFFLINE) {
b02fd9e3 13630 int err, err2 = 0, irq_sync = 0;
bbe832c0
MC		 13631
13632 if (netif_running(dev)) {
b02fd9e3 13633 tg3_phy_stop(tp);
a71116d1 13634 tg3_netif_stop(tp);
bbe832c0
MC		 13635 irq_sync = 1;
13636 }
a71116d1 13637
bbe832c0 13638 tg3_full_lock(tp, irq_sync);
a71116d1 13639 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
ec41c7df 13640 err = tg3_nvram_lock(tp);
a71116d1 13641 tg3_halt_cpu(tp, RX_CPU_BASE);
63c3a66f 13642 if (!tg3_flag(tp, 5705_PLUS))
a71116d1 13643 tg3_halt_cpu(tp, TX_CPU_BASE);
ec41c7df
MC		 13644 if (!err)
13645 tg3_nvram_unlock(tp);
a71116d1 13646
f07e9af3 13647 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
d9ab5ad1
MC		 13648 tg3_phy_reset(tp);
13649
a71116d1
MC		 13650 if (tg3_test_registers(tp) != 0) {
13651 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13652 data[TG3_REGISTER_TEST] = 1;
a71116d1 13653 }
28a45957 13654
7942e1db
MC		 13655 if (tg3_test_memory(tp) != 0) {
13656 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13657 data[TG3_MEMORY_TEST] = 1;
7942e1db 13658 }
28a45957 13659
941ec90f
MC		 13660 if (doextlpbk)
13661 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13662
93df8b8f 13663 if (tg3_test_loopback(tp, data, doextlpbk))
c76949a6 13664 etest->flags |= ETH_TEST_FL_FAILED;
a71116d1 13665
f47c11ee
DM		 13666 tg3_full_unlock(tp);
13667
d4bc3927
MC		 13668 if (tg3_test_interrupt(tp) != 0) {
13669 etest->flags |= ETH_TEST_FL_FAILED;
93df8b8f 13670 data[TG3_INTERRUPT_TEST] = 1;
d4bc3927 13671 }
f47c11ee
DM		 13672
13673 tg3_full_lock(tp, 0);
d4bc3927 13674
a71116d1
MC		 13675 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13676 if (netif_running(dev)) {
63c3a66f 13677 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 13678 err2 = tg3_restart_hw(tp, true);
b02fd9e3 13679 if (!err2)
b9ec6c1b 13680 tg3_netif_start(tp);
a71116d1 13681 }
f47c11ee
DM		 13682
13683 tg3_full_unlock(tp);
b02fd9e3
MC		 13684
13685 if (irq_sync && !err2)
13686 tg3_phy_start(tp);
a71116d1 13687 }
80096068 13688 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
5137a2ee 13689 tg3_power_down_prepare(tp);
bc1c7567 13690
4cafd3f5
MC		 13691}
13692
7260899b 13693static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
0a633ac2
MC		 13694{
13695 struct tg3 *tp = netdev_priv(dev);
13696 struct hwtstamp_config stmpconf;
13697
13698 if (!tg3_flag(tp, PTP_CAPABLE))
7260899b 13699 return -EOPNOTSUPP;
0a633ac2
MC		 13700
13701 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13702 return -EFAULT;
13703
13704 if (stmpconf.flags)
13705 return -EINVAL;
13706
58b187c6
BH		 13707 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13708 stmpconf.tx_type != HWTSTAMP_TX_OFF)
0a633ac2 13709 return -ERANGE;
0a633ac2
MC		 13710
13711 switch (stmpconf.rx_filter) {
13712 case HWTSTAMP_FILTER_NONE:
13713 tp->rxptpctl = 0;
13714 break;
13715 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13716 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13717 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13718 break;
13719 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13720 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13721 TG3_RX_PTP_CTL_SYNC_EVNT;
13722 break;
13723 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13724 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13725 TG3_RX_PTP_CTL_DELAY_REQ;
13726 break;
13727 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13728 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13729 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13730 break;
13731 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13732 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13733 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13734 break;
13735 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13736 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13737 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13738 break;
13739 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13740 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13741 TG3_RX_PTP_CTL_SYNC_EVNT;
13742 break;
13743 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13744 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13745 TG3_RX_PTP_CTL_SYNC_EVNT;
13746 break;
13747 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13748 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13749 TG3_RX_PTP_CTL_SYNC_EVNT;
13750 break;
13751 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13752 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13753 TG3_RX_PTP_CTL_DELAY_REQ;
13754 break;
13755 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13756 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13757 TG3_RX_PTP_CTL_DELAY_REQ;
13758 break;
13759 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13760 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13761 TG3_RX_PTP_CTL_DELAY_REQ;
13762 break;
13763 default:
13764 return -ERANGE;
13765 }
13766
13767 if (netif_running(dev) && tp->rxptpctl)
13768 tw32(TG3_RX_PTP_CTL,
13769 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13770
58b187c6
BH		 13771 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13772 tg3_flag_set(tp, TX_TSTAMP_EN);
13773 else
13774 tg3_flag_clear(tp, TX_TSTAMP_EN);
13775
0a633ac2
MC		 13776 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13777 -EFAULT : 0;
13778}
13779
7260899b
BH		 13780static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13781{
13782 struct tg3 *tp = netdev_priv(dev);
13783 struct hwtstamp_config stmpconf;
13784
13785 if (!tg3_flag(tp, PTP_CAPABLE))
13786 return -EOPNOTSUPP;
13787
13788 stmpconf.flags = 0;
13789 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13790 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13791
13792 switch (tp->rxptpctl) {
13793 case 0:
13794 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13795 break;
13796 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13797 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13798 break;
13799 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13800 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13801 break;
13802 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13803 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13804 break;
13805 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13806 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13807 break;
13808 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13809 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13810 break;
13811 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13812 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13813 break;
13814 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13815 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13816 break;
13817 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13818 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13819 break;
13820 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13821 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13822 break;
13823 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13824 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13825 break;
13826 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13827 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13828 break;
13829 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13830 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13831 break;
13832 default:
13833 WARN_ON_ONCE(1);
13834 return -ERANGE;
13835 }
13836
13837 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13838 -EFAULT : 0;
13839}
13840
1da177e4
LT		 13841static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13842{
13843 struct mii_ioctl_data *data = if_mii(ifr);
13844 struct tg3 *tp = netdev_priv(dev);
13845 int err;
13846
63c3a66f 13847 if (tg3_flag(tp, USE_PHYLIB)) {
3f0e3ad7 13848 struct phy_device *phydev;
f07e9af3 13849 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
b02fd9e3 13850 return -EAGAIN;
ead2402c 13851 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
28b04113 13852 return phy_mii_ioctl(phydev, ifr, cmd);
b02fd9e3
MC		 13853 }
13854
33f401ae 13855 switch (cmd) {
1da177e4 13856 case SIOCGMIIPHY:
882e9793 13857 data->phy_id = tp->phy_addr;
1da177e4
LT		 13858
13859 /* fallthru */
13860 case SIOCGMIIREG: {
13861 u32 mii_regval;
13862
f07e9af3 13863 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13864 break; /* We have no PHY */
13865
34eea5ac 13866 if (!netif_running(dev))
bc1c7567
MC		 13867 return -EAGAIN;
13868
f47c11ee 13869 spin_lock_bh(&tp->lock);
5c358045
HM		 13870 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13871 data->reg_num & 0x1f, &mii_regval);
f47c11ee 13872 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13873
13874 data->val_out = mii_regval;
13875
13876 return err;
13877 }
13878
13879 case SIOCSMIIREG:
f07e9af3 13880 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1da177e4
LT		 13881 break; /* We have no PHY */
13882
34eea5ac 13883 if (!netif_running(dev))
bc1c7567
MC		 13884 return -EAGAIN;
13885
f47c11ee 13886 spin_lock_bh(&tp->lock);
5c358045
HM		 13887 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13888 data->reg_num & 0x1f, data->val_in);
f47c11ee 13889 spin_unlock_bh(&tp->lock);
1da177e4
LT		 13890
13891 return err;
13892
0a633ac2 13893 case SIOCSHWTSTAMP:
7260899b
BH		 13894 return tg3_hwtstamp_set(dev, ifr);
13895
13896 case SIOCGHWTSTAMP:
13897 return tg3_hwtstamp_get(dev, ifr);
0a633ac2 13898
1da177e4
LT		 13899 default:
13900 /* do nothing */
13901 break;
13902 }
13903 return -EOPNOTSUPP;
13904}
13905
15f9850d
DM		 13906static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13907{
13908 struct tg3 *tp = netdev_priv(dev);
13909
13910 memcpy(ec, &tp->coal, sizeof(*ec));
13911 return 0;
13912}
13913
d244c892
MC		 13914static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13915{
13916 struct tg3 *tp = netdev_priv(dev);
13917 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13918 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13919
63c3a66f 13920 if (!tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 13921 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13922 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13923 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13924 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13925 }
13926
13927 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13928 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13929 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13930 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13931 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13932 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13933 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13934 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13935 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13936 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13937 return -EINVAL;
13938
13939 /* No rx interrupts will be generated if both are zero */
13940 if ((ec->rx_coalesce_usecs == 0) &&
13941 (ec->rx_max_coalesced_frames == 0))
13942 return -EINVAL;
13943
13944 /* No tx interrupts will be generated if both are zero */
13945 if ((ec->tx_coalesce_usecs == 0) &&
13946 (ec->tx_max_coalesced_frames == 0))
13947 return -EINVAL;
13948
13949 /* Only copy relevant parameters, ignore all others. */
13950 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13951 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13952 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13953 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13954 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13955 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13956 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13957 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13958 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13959
13960 if (netif_running(dev)) {
13961 tg3_full_lock(tp, 0);
13962 __tg3_set_coalesce(tp, &tp->coal);
13963 tg3_full_unlock(tp);
13964 }
13965 return 0;
13966}
13967
1cbf9eb8
NS		 13968static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13969{
13970 struct tg3 *tp = netdev_priv(dev);
13971
13972 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13973 netdev_warn(tp->dev, "Board does not support EEE!\n");
13974 return -EOPNOTSUPP;
13975 }
13976
13977 if (edata->advertised != tp->eee.advertised) {
13978 netdev_warn(tp->dev,
13979 "Direct manipulation of EEE advertisement is not supported\n");
13980 return -EINVAL;
13981 }
13982
13983 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13984 netdev_warn(tp->dev,
13985 "Maximal Tx Lpi timer supported is %#x(u)\n",
13986 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13987 return -EINVAL;
13988 }
13989
13990 tp->eee = *edata;
13991
13992 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13993 tg3_warn_mgmt_link_flap(tp);
13994
13995 if (netif_running(tp->dev)) {
13996 tg3_full_lock(tp, 0);
13997 tg3_setup_eee(tp);
13998 tg3_phy_reset(tp);
13999 tg3_full_unlock(tp);
14000 }
14001
14002 return 0;
14003}
14004
14005static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14006{
14007 struct tg3 *tp = netdev_priv(dev);
14008
14009 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14010 netdev_warn(tp->dev,
14011 "Board does not support EEE!\n");
14012 return -EOPNOTSUPP;
14013 }
14014
14015 *edata = tp->eee;
14016 return 0;
14017}
14018
7282d491 14019static const struct ethtool_ops tg3_ethtool_ops = {
1da177e4
LT		 14020 .get_settings = tg3_get_settings,
14021 .set_settings = tg3_set_settings,
14022 .get_drvinfo = tg3_get_drvinfo,
14023 .get_regs_len = tg3_get_regs_len,
14024 .get_regs = tg3_get_regs,
14025 .get_wol = tg3_get_wol,
14026 .set_wol = tg3_set_wol,
14027 .get_msglevel = tg3_get_msglevel,
14028 .set_msglevel = tg3_set_msglevel,
14029 .nway_reset = tg3_nway_reset,
14030 .get_link = ethtool_op_get_link,
14031 .get_eeprom_len = tg3_get_eeprom_len,
14032 .get_eeprom = tg3_get_eeprom,
14033 .set_eeprom = tg3_set_eeprom,
14034 .get_ringparam = tg3_get_ringparam,
14035 .set_ringparam = tg3_set_ringparam,
14036 .get_pauseparam = tg3_get_pauseparam,
14037 .set_pauseparam = tg3_set_pauseparam,
4cafd3f5 14038 .self_test = tg3_self_test,
1da177e4 14039 .get_strings = tg3_get_strings,
81b8709c 14040 .set_phys_id = tg3_set_phys_id,
1da177e4 14041 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 14042 .get_coalesce = tg3_get_coalesce,
d244c892 14043 .set_coalesce = tg3_set_coalesce,
b9f2c044 14044 .get_sset_count = tg3_get_sset_count,
90415477
MC		 14045 .get_rxnfc = tg3_get_rxnfc,
14046 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14047 .get_rxfh_indir = tg3_get_rxfh_indir,
14048 .set_rxfh_indir = tg3_set_rxfh_indir,
0968169c
MC		 14049 .get_channels = tg3_get_channels,
14050 .set_channels = tg3_set_channels,
7d41e49a 14051 .get_ts_info = tg3_get_ts_info,
1cbf9eb8
NS		 14052 .get_eee = tg3_get_eee,
14053 .set_eee = tg3_set_eee,
1da177e4
LT		 14054};
14055
b4017c53
DM		 14056static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14057 struct rtnl_link_stats64 *stats)
14058{
14059 struct tg3 *tp = netdev_priv(dev);
14060
0f566b20
MC		 14061 spin_lock_bh(&tp->lock);
14062 if (!tp->hw_stats) {
14063 spin_unlock_bh(&tp->lock);
b4017c53 14064 return &tp->net_stats_prev;
0f566b20 14065 }
b4017c53 14066
b4017c53
DM		 14067 tg3_get_nstats(tp, stats);
14068 spin_unlock_bh(&tp->lock);
14069
14070 return stats;
14071}
14072
ccd5ba9d
MC		 14073static void tg3_set_rx_mode(struct net_device *dev)
14074{
14075 struct tg3 *tp = netdev_priv(dev);
14076
14077 if (!netif_running(dev))
14078 return;
14079
14080 tg3_full_lock(tp, 0);
14081 __tg3_set_rx_mode(dev);
14082 tg3_full_unlock(tp);
14083}
14084
faf1627a
MC		 14085static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14086 int new_mtu)
14087{
14088 dev->mtu = new_mtu;
14089
14090 if (new_mtu > ETH_DATA_LEN) {
14091 if (tg3_flag(tp, 5780_CLASS)) {
14092 netdev_update_features(dev);
14093 tg3_flag_clear(tp, TSO_CAPABLE);
14094 } else {
14095 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14096 }
14097 } else {
14098 if (tg3_flag(tp, 5780_CLASS)) {
14099 tg3_flag_set(tp, TSO_CAPABLE);
14100 netdev_update_features(dev);
14101 }
14102 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14103 }
14104}
14105
14106static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14107{
14108 struct tg3 *tp = netdev_priv(dev);
953c96e0
JP		 14109 int err;
14110 bool reset_phy = false;
faf1627a
MC		 14111
14112 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14113 return -EINVAL;
14114
14115 if (!netif_running(dev)) {
14116 /* We'll just catch it later when the
14117 * device is up'd.
14118 */
14119 tg3_set_mtu(dev, tp, new_mtu);
14120 return 0;
14121 }
14122
14123 tg3_phy_stop(tp);
14124
14125 tg3_netif_stop(tp);
14126
c6993dfd
NS		 14127 tg3_set_mtu(dev, tp, new_mtu);
14128
faf1627a
MC		 14129 tg3_full_lock(tp, 1);
14130
14131 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14132
2fae5e36
MC		 14133 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14134 * breaks all requests to 256 bytes.
14135 */
4153577a 14136 if (tg3_asic_rev(tp) == ASIC_REV_57766)
953c96e0 14137 reset_phy = true;
2fae5e36
MC		 14138
14139 err = tg3_restart_hw(tp, reset_phy);
faf1627a
MC		 14140
14141 if (!err)
14142 tg3_netif_start(tp);
14143
14144 tg3_full_unlock(tp);
14145
14146 if (!err)
14147 tg3_phy_start(tp);
14148
14149 return err;
14150}
14151
14152static const struct net_device_ops tg3_netdev_ops = {
14153 .ndo_open = tg3_open,
14154 .ndo_stop = tg3_close,
14155 .ndo_start_xmit = tg3_start_xmit,
14156 .ndo_get_stats64 = tg3_get_stats64,
14157 .ndo_validate_addr = eth_validate_addr,
14158 .ndo_set_rx_mode = tg3_set_rx_mode,
14159 .ndo_set_mac_address = tg3_set_mac_addr,
14160 .ndo_do_ioctl = tg3_ioctl,
14161 .ndo_tx_timeout = tg3_tx_timeout,
14162 .ndo_change_mtu = tg3_change_mtu,
14163 .ndo_fix_features = tg3_fix_features,
14164 .ndo_set_features = tg3_set_features,
14165#ifdef CONFIG_NET_POLL_CONTROLLER
14166 .ndo_poll_controller = tg3_poll_controller,
14167#endif
14168};
14169
229b1ad1 14170static void tg3_get_eeprom_size(struct tg3 *tp)
1da177e4 14171{
1b27777a 14172 u32 cursize, val, magic;
1da177e4
LT		 14173
14174 tp->nvram_size = EEPROM_CHIP_SIZE;
14175
e4f34110 14176 if (tg3_nvram_read(tp, 0, &magic) != 0)
1da177e4
LT		 14177 return;
14178
b16250e3
MC		 14179 if ((magic != TG3_EEPROM_MAGIC) &&
14180 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14181 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
1da177e4
LT		 14182 return;
14183
14184 /*
14185 * Size the chip by reading offsets at increasing powers of two.
14186 * When we encounter our validation signature, we know the addressing
14187 * has wrapped around, and thus have our chip size.
14188 */
1b27777a 14189 cursize = 0x10;
1da177e4
LT		 14190
14191 while (cursize < tp->nvram_size) {
e4f34110 14192 if (tg3_nvram_read(tp, cursize, &val) != 0)
1da177e4
LT		 14193 return;
14194
1820180b 14195 if (val == magic)
1da177e4
LT		 14196 break;
14197
14198 cursize <<= 1;
14199 }
14200
14201 tp->nvram_size = cursize;
14202}
6aa20a22 14203
229b1ad1 14204static void tg3_get_nvram_size(struct tg3 *tp)
1da177e4
LT		 14205{
14206 u32 val;
14207
63c3a66f 14208 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
1b27777a
MC		 14209 return;
14210
14211 /* Selfboot format */
1820180b 14212 if (val != TG3_EEPROM_MAGIC) {
1b27777a
MC		 14213 tg3_get_eeprom_size(tp);
14214 return;
14215 }
14216
6d348f2c 14217 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
1da177e4 14218 if (val != 0) {
6d348f2c
MC		 14219 /* This is confusing. We want to operate on the
14220 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14221 * call will read from NVRAM and byteswap the data
14222 * according to the byteswapping settings for all
14223 * other register accesses. This ensures the data we
14224 * want will always reside in the lower 16-bits.
14225 * However, the data in NVRAM is in LE format, which
14226 * means the data from the NVRAM read will always be
14227 * opposite the endianness of the CPU. The 16-bit
14228 * byteswap then brings the data to CPU endianness.
14229 */
14230 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
1da177e4
LT		 14231 return;
14232 }
14233 }
fd1122a2 14234 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
1da177e4
LT		 14235}
14236
229b1ad1 14237static void tg3_get_nvram_info(struct tg3 *tp)
1da177e4
LT		 14238{
14239 u32 nvcfg1;
14240
14241 nvcfg1 = tr32(NVRAM_CFG1);
14242 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
63c3a66f 14243 tg3_flag_set(tp, FLASH);
8590a603 14244 } else {
1da177e4
LT		 14245 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14246 tw32(NVRAM_CFG1, nvcfg1);
14247 }
14248
4153577a 14249 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
63c3a66f 14250 tg3_flag(tp, 5780_CLASS)) {
1da177e4 14251 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8590a603
MC		 14252 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14253 tp->nvram_jedecnum = JEDEC_ATMEL;
14254 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14255 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14256 break;
14257 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14258 tp->nvram_jedecnum = JEDEC_ATMEL;
14259 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14260 break;
14261 case FLASH_VENDOR_ATMEL_EEPROM:
14262 tp->nvram_jedecnum = JEDEC_ATMEL;
14263 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
63c3a66f 14264 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14265 break;
14266 case FLASH_VENDOR_ST:
14267 tp->nvram_jedecnum = JEDEC_ST;
14268 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
63c3a66f 14269 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14270 break;
14271 case FLASH_VENDOR_SAIFUN:
14272 tp->nvram_jedecnum = JEDEC_SAIFUN;
14273 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14274 break;
14275 case FLASH_VENDOR_SST_SMALL:
14276 case FLASH_VENDOR_SST_LARGE:
14277 tp->nvram_jedecnum = JEDEC_SST;
14278 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14279 break;
1da177e4 14280 }
8590a603 14281 } else {
1da177e4
LT		 14282 tp->nvram_jedecnum = JEDEC_ATMEL;
14283 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
63c3a66f 14284 tg3_flag_set(tp, NVRAM_BUFFERED);
1da177e4
LT		 14285 }
14286}
14287
229b1ad1 14288static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
a1b950d5
MC		 14289{
14290 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14291 case FLASH_5752PAGE_SIZE_256:
14292 tp->nvram_pagesize = 256;
14293 break;
14294 case FLASH_5752PAGE_SIZE_512:
14295 tp->nvram_pagesize = 512;
14296 break;
14297 case FLASH_5752PAGE_SIZE_1K:
14298 tp->nvram_pagesize = 1024;
14299 break;
14300 case FLASH_5752PAGE_SIZE_2K:
14301 tp->nvram_pagesize = 2048;
14302 break;
14303 case FLASH_5752PAGE_SIZE_4K:
14304 tp->nvram_pagesize = 4096;
14305 break;
14306 case FLASH_5752PAGE_SIZE_264:
14307 tp->nvram_pagesize = 264;
14308 break;
14309 case FLASH_5752PAGE_SIZE_528:
14310 tp->nvram_pagesize = 528;
14311 break;
14312 }
14313}
14314
229b1ad1 14315static void tg3_get_5752_nvram_info(struct tg3 *tp)
361b4ac2
MC		 14316{
14317 u32 nvcfg1;
14318
14319 nvcfg1 = tr32(NVRAM_CFG1);
14320
e6af301b
MC		 14321 /* NVRAM protection for TPM */
14322 if (nvcfg1 & (1 << 27))
63c3a66f 14323 tg3_flag_set(tp, PROTECTED_NVRAM);
e6af301b 14324
361b4ac2 14325 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14326 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14327 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14328 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14329 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603
MC		 14330 break;
14331 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14332 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14333 tg3_flag_set(tp, NVRAM_BUFFERED);
14334 tg3_flag_set(tp, FLASH);
8590a603
MC		 14335 break;
14336 case FLASH_5752VENDOR_ST_M45PE10:
14337 case FLASH_5752VENDOR_ST_M45PE20:
14338 case FLASH_5752VENDOR_ST_M45PE40:
14339 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14340 tg3_flag_set(tp, NVRAM_BUFFERED);
14341 tg3_flag_set(tp, FLASH);
8590a603 14342 break;
361b4ac2
MC		 14343 }
14344
63c3a66f 14345 if (tg3_flag(tp, FLASH)) {
a1b950d5 14346 tg3_nvram_get_pagesize(tp, nvcfg1);
8590a603 14347 } else {
361b4ac2
MC		 14348 /* For eeprom, set pagesize to maximum eeprom size */
14349 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14350
14351 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14352 tw32(NVRAM_CFG1, nvcfg1);
14353 }
14354}
14355
229b1ad1 14356static void tg3_get_5755_nvram_info(struct tg3 *tp)
d3c7b886 14357{
989a9d23 14358 u32 nvcfg1, protect = 0;
d3c7b886
MC		 14359
14360 nvcfg1 = tr32(NVRAM_CFG1);
14361
14362 /* NVRAM protection for TPM */
989a9d23 14363 if (nvcfg1 & (1 << 27)) {
63c3a66f 14364 tg3_flag_set(tp, PROTECTED_NVRAM);
989a9d23
MC		 14365 protect = 1;
14366 }
d3c7b886 14367
989a9d23
MC		 14368 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14369 switch (nvcfg1) {
8590a603
MC		 14370 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14371 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14372 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14373 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14374 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14375 tg3_flag_set(tp, NVRAM_BUFFERED);
14376 tg3_flag_set(tp, FLASH);
8590a603
MC		 14377 tp->nvram_pagesize = 264;
14378 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14379 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14380 tp->nvram_size = (protect ? 0x3e200 :
14381 TG3_NVRAM_SIZE_512KB);
14382 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14383 tp->nvram_size = (protect ? 0x1f200 :
14384 TG3_NVRAM_SIZE_256KB);
14385 else
14386 tp->nvram_size = (protect ? 0x1f200 :
14387 TG3_NVRAM_SIZE_128KB);
14388 break;
14389 case FLASH_5752VENDOR_ST_M45PE10:
14390 case FLASH_5752VENDOR_ST_M45PE20:
14391 case FLASH_5752VENDOR_ST_M45PE40:
14392 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14393 tg3_flag_set(tp, NVRAM_BUFFERED);
14394 tg3_flag_set(tp, FLASH);
8590a603
MC		 14395 tp->nvram_pagesize = 256;
14396 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14397 tp->nvram_size = (protect ?
14398 TG3_NVRAM_SIZE_64KB :
14399 TG3_NVRAM_SIZE_128KB);
14400 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14401 tp->nvram_size = (protect ?
14402 TG3_NVRAM_SIZE_64KB :
14403 TG3_NVRAM_SIZE_256KB);
14404 else
14405 tp->nvram_size = (protect ?
14406 TG3_NVRAM_SIZE_128KB :
14407 TG3_NVRAM_SIZE_512KB);
14408 break;
d3c7b886
MC		 14409 }
14410}
14411
229b1ad1 14412static void tg3_get_5787_nvram_info(struct tg3 *tp)
1b27777a
MC		 14413{
14414 u32 nvcfg1;
14415
14416 nvcfg1 = tr32(NVRAM_CFG1);
14417
14418 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8590a603
MC		 14419 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14420 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14421 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14422 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14423 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14424 tg3_flag_set(tp, NVRAM_BUFFERED);
8590a603 14425 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
1b27777a 14426
8590a603
MC		 14427 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14428 tw32(NVRAM_CFG1, nvcfg1);
14429 break;
14430 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14431 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14432 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14433 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14434 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14435 tg3_flag_set(tp, NVRAM_BUFFERED);
14436 tg3_flag_set(tp, FLASH);
8590a603
MC		 14437 tp->nvram_pagesize = 264;
14438 break;
14439 case FLASH_5752VENDOR_ST_M45PE10:
14440 case FLASH_5752VENDOR_ST_M45PE20:
14441 case FLASH_5752VENDOR_ST_M45PE40:
14442 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14443 tg3_flag_set(tp, NVRAM_BUFFERED);
14444 tg3_flag_set(tp, FLASH);
8590a603
MC		 14445 tp->nvram_pagesize = 256;
14446 break;
1b27777a
MC		 14447 }
14448}
14449
229b1ad1 14450static void tg3_get_5761_nvram_info(struct tg3 *tp)
6b91fa02
MC		 14451{
14452 u32 nvcfg1, protect = 0;
14453
14454 nvcfg1 = tr32(NVRAM_CFG1);
14455
14456 /* NVRAM protection for TPM */
14457 if (nvcfg1 & (1 << 27)) {
63c3a66f 14458 tg3_flag_set(tp, PROTECTED_NVRAM);
6b91fa02
MC		 14459 protect = 1;
14460 }
14461
14462 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14463 switch (nvcfg1) {
8590a603
MC		 14464 case FLASH_5761VENDOR_ATMEL_ADB021D:
14465 case FLASH_5761VENDOR_ATMEL_ADB041D:
14466 case FLASH_5761VENDOR_ATMEL_ADB081D:
14467 case FLASH_5761VENDOR_ATMEL_ADB161D:
14468 case FLASH_5761VENDOR_ATMEL_MDB021D:
14469 case FLASH_5761VENDOR_ATMEL_MDB041D:
14470 case FLASH_5761VENDOR_ATMEL_MDB081D:
14471 case FLASH_5761VENDOR_ATMEL_MDB161D:
14472 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14473 tg3_flag_set(tp, NVRAM_BUFFERED);
14474 tg3_flag_set(tp, FLASH);
14475 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
8590a603
MC		 14476 tp->nvram_pagesize = 256;
14477 break;
14478 case FLASH_5761VENDOR_ST_A_M45PE20:
14479 case FLASH_5761VENDOR_ST_A_M45PE40:
14480 case FLASH_5761VENDOR_ST_A_M45PE80:
14481 case FLASH_5761VENDOR_ST_A_M45PE16:
14482 case FLASH_5761VENDOR_ST_M_M45PE20:
14483 case FLASH_5761VENDOR_ST_M_M45PE40:
14484 case FLASH_5761VENDOR_ST_M_M45PE80:
14485 case FLASH_5761VENDOR_ST_M_M45PE16:
14486 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14487 tg3_flag_set(tp, NVRAM_BUFFERED);
14488 tg3_flag_set(tp, FLASH);
8590a603
MC		 14489 tp->nvram_pagesize = 256;
14490 break;
6b91fa02
MC		 14491 }
14492
14493 if (protect) {
14494 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14495 } else {
14496 switch (nvcfg1) {
8590a603
MC		 14497 case FLASH_5761VENDOR_ATMEL_ADB161D:
14498 case FLASH_5761VENDOR_ATMEL_MDB161D:
14499 case FLASH_5761VENDOR_ST_A_M45PE16:
14500 case FLASH_5761VENDOR_ST_M_M45PE16:
14501 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14502 break;
14503 case FLASH_5761VENDOR_ATMEL_ADB081D:
14504 case FLASH_5761VENDOR_ATMEL_MDB081D:
14505 case FLASH_5761VENDOR_ST_A_M45PE80:
14506 case FLASH_5761VENDOR_ST_M_M45PE80:
14507 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14508 break;
14509 case FLASH_5761VENDOR_ATMEL_ADB041D:
14510 case FLASH_5761VENDOR_ATMEL_MDB041D:
14511 case FLASH_5761VENDOR_ST_A_M45PE40:
14512 case FLASH_5761VENDOR_ST_M_M45PE40:
14513 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14514 break;
14515 case FLASH_5761VENDOR_ATMEL_ADB021D:
14516 case FLASH_5761VENDOR_ATMEL_MDB021D:
14517 case FLASH_5761VENDOR_ST_A_M45PE20:
14518 case FLASH_5761VENDOR_ST_M_M45PE20:
14519 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14520 break;
6b91fa02
MC		 14521 }
14522 }
14523}
14524
229b1ad1 14525static void tg3_get_5906_nvram_info(struct tg3 *tp)
b5d3772c
MC		 14526{
14527 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14528 tg3_flag_set(tp, NVRAM_BUFFERED);
b5d3772c
MC		 14529 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14530}
14531
229b1ad1 14532static void tg3_get_57780_nvram_info(struct tg3 *tp)
321d32a0
MC		 14533{
14534 u32 nvcfg1;
14535
14536 nvcfg1 = tr32(NVRAM_CFG1);
14537
14538 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14539 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14540 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14541 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14542 tg3_flag_set(tp, NVRAM_BUFFERED);
321d32a0
MC		 14543 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14544
14545 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14546 tw32(NVRAM_CFG1, nvcfg1);
14547 return;
14548 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14549 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14550 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14551 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14552 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14553 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14554 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14555 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14556 tg3_flag_set(tp, NVRAM_BUFFERED);
14557 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14558
14559 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14560 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14561 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14562 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14563 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14564 break;
14565 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14566 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14567 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14568 break;
14569 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14570 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14571 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14572 break;
14573 }
14574 break;
14575 case FLASH_5752VENDOR_ST_M45PE10:
14576 case FLASH_5752VENDOR_ST_M45PE20:
14577 case FLASH_5752VENDOR_ST_M45PE40:
14578 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14579 tg3_flag_set(tp, NVRAM_BUFFERED);
14580 tg3_flag_set(tp, FLASH);
321d32a0
MC		 14581
14582 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14583 case FLASH_5752VENDOR_ST_M45PE10:
14584 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14585 break;
14586 case FLASH_5752VENDOR_ST_M45PE20:
14587 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14588 break;
14589 case FLASH_5752VENDOR_ST_M45PE40:
14590 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14591 break;
14592 }
14593 break;
14594 default:
63c3a66f 14595 tg3_flag_set(tp, NO_NVRAM);
321d32a0
MC		 14596 return;
14597 }
14598
a1b950d5
MC		 14599 tg3_nvram_get_pagesize(tp, nvcfg1);
14600 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14601 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
a1b950d5
MC		 14602}
14603
14604
229b1ad1 14605static void tg3_get_5717_nvram_info(struct tg3 *tp)
a1b950d5
MC		 14606{
14607 u32 nvcfg1;
14608
14609 nvcfg1 = tr32(NVRAM_CFG1);
14610
14611 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14612 case FLASH_5717VENDOR_ATMEL_EEPROM:
14613 case FLASH_5717VENDOR_MICRO_EEPROM:
14614 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14615 tg3_flag_set(tp, NVRAM_BUFFERED);
a1b950d5
MC		 14616 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14617
14618 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14619 tw32(NVRAM_CFG1, nvcfg1);
14620 return;
14621 case FLASH_5717VENDOR_ATMEL_MDB011D:
14622 case FLASH_5717VENDOR_ATMEL_ADB011B:
14623 case FLASH_5717VENDOR_ATMEL_ADB011D:
14624 case FLASH_5717VENDOR_ATMEL_MDB021D:
14625 case FLASH_5717VENDOR_ATMEL_ADB021B:
14626 case FLASH_5717VENDOR_ATMEL_ADB021D:
14627 case FLASH_5717VENDOR_ATMEL_45USPT:
14628 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14629 tg3_flag_set(tp, NVRAM_BUFFERED);
14630 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14631
14632 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14633 case FLASH_5717VENDOR_ATMEL_MDB021D:
66ee33bf
MC		 14634 /* Detect size with tg3_nvram_get_size() */
14635 break;
a1b950d5
MC		 14636 case FLASH_5717VENDOR_ATMEL_ADB021B:
14637 case FLASH_5717VENDOR_ATMEL_ADB021D:
14638 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14639 break;
14640 default:
14641 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14642 break;
14643 }
321d32a0 14644 break;
a1b950d5
MC		 14645 case FLASH_5717VENDOR_ST_M_M25PE10:
14646 case FLASH_5717VENDOR_ST_A_M25PE10:
14647 case FLASH_5717VENDOR_ST_M_M45PE10:
14648 case FLASH_5717VENDOR_ST_A_M45PE10:
14649 case FLASH_5717VENDOR_ST_M_M25PE20:
14650 case FLASH_5717VENDOR_ST_A_M25PE20:
14651 case FLASH_5717VENDOR_ST_M_M45PE20:
14652 case FLASH_5717VENDOR_ST_A_M45PE20:
14653 case FLASH_5717VENDOR_ST_25USPT:
14654 case FLASH_5717VENDOR_ST_45USPT:
14655 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14656 tg3_flag_set(tp, NVRAM_BUFFERED);
14657 tg3_flag_set(tp, FLASH);
a1b950d5
MC		 14658
14659 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14660 case FLASH_5717VENDOR_ST_M_M25PE20:
a1b950d5 14661 case FLASH_5717VENDOR_ST_M_M45PE20:
66ee33bf
MC		 14662 /* Detect size with tg3_nvram_get_size() */
14663 break;
14664 case FLASH_5717VENDOR_ST_A_M25PE20:
a1b950d5
MC		 14665 case FLASH_5717VENDOR_ST_A_M45PE20:
14666 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14667 break;
14668 default:
14669 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14670 break;
14671 }
321d32a0 14672 break;
a1b950d5 14673 default:
63c3a66f 14674 tg3_flag_set(tp, NO_NVRAM);
a1b950d5 14675 return;
321d32a0 14676 }
a1b950d5
MC		 14677
14678 tg3_nvram_get_pagesize(tp, nvcfg1);
14679 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14680 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
321d32a0
MC		 14681}
14682
229b1ad1 14683static void tg3_get_5720_nvram_info(struct tg3 *tp)
9b91b5f1
MC		 14684{
14685 u32 nvcfg1, nvmpinstrp;
14686
14687 nvcfg1 = tr32(NVRAM_CFG1);
14688 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14689
4153577a 14690 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14691 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14692 tg3_flag_set(tp, NO_NVRAM);
14693 return;
14694 }
14695
14696 switch (nvmpinstrp) {
14697 case FLASH_5762_EEPROM_HD:
14698 nvmpinstrp = FLASH_5720_EEPROM_HD;
17e1a42f 14699 break;
c86a8560
MC		 14700 case FLASH_5762_EEPROM_LD:
14701 nvmpinstrp = FLASH_5720_EEPROM_LD;
17e1a42f 14702 break;
f6334bb8
MC		 14703 case FLASH_5720VENDOR_M_ST_M45PE20:
14704 /* This pinstrap supports multiple sizes, so force it
14705 * to read the actual size from location 0xf0.
14706 */
14707 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14708 break;
c86a8560
MC		 14709 }
14710 }
14711
9b91b5f1
MC		 14712 switch (nvmpinstrp) {
14713 case FLASH_5720_EEPROM_HD:
14714 case FLASH_5720_EEPROM_LD:
14715 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f 14716 tg3_flag_set(tp, NVRAM_BUFFERED);
9b91b5f1
MC		 14717
14718 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14719 tw32(NVRAM_CFG1, nvcfg1);
14720 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14721 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14722 else
14723 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14724 return;
14725 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14726 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14727 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14728 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14729 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14730 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14731 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14732 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14733 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14734 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14735 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14736 case FLASH_5720VENDOR_ATMEL_45USPT:
14737 tp->nvram_jedecnum = JEDEC_ATMEL;
63c3a66f
JP		 14738 tg3_flag_set(tp, NVRAM_BUFFERED);
14739 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14740
14741 switch (nvmpinstrp) {
14742 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14743 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14744 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14745 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14746 break;
14747 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14748 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14749 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14750 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14751 break;
14752 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14753 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14754 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14755 break;
14756 default:
4153577a 14757 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14758 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14759 break;
14760 }
14761 break;
14762 case FLASH_5720VENDOR_M_ST_M25PE10:
14763 case FLASH_5720VENDOR_M_ST_M45PE10:
14764 case FLASH_5720VENDOR_A_ST_M25PE10:
14765 case FLASH_5720VENDOR_A_ST_M45PE10:
14766 case FLASH_5720VENDOR_M_ST_M25PE20:
14767 case FLASH_5720VENDOR_M_ST_M45PE20:
14768 case FLASH_5720VENDOR_A_ST_M25PE20:
14769 case FLASH_5720VENDOR_A_ST_M45PE20:
14770 case FLASH_5720VENDOR_M_ST_M25PE40:
14771 case FLASH_5720VENDOR_M_ST_M45PE40:
14772 case FLASH_5720VENDOR_A_ST_M25PE40:
14773 case FLASH_5720VENDOR_A_ST_M45PE40:
14774 case FLASH_5720VENDOR_M_ST_M25PE80:
14775 case FLASH_5720VENDOR_M_ST_M45PE80:
14776 case FLASH_5720VENDOR_A_ST_M25PE80:
14777 case FLASH_5720VENDOR_A_ST_M45PE80:
14778 case FLASH_5720VENDOR_ST_25USPT:
14779 case FLASH_5720VENDOR_ST_45USPT:
14780 tp->nvram_jedecnum = JEDEC_ST;
63c3a66f
JP		 14781 tg3_flag_set(tp, NVRAM_BUFFERED);
14782 tg3_flag_set(tp, FLASH);
9b91b5f1
MC		 14783
14784 switch (nvmpinstrp) {
14785 case FLASH_5720VENDOR_M_ST_M25PE20:
14786 case FLASH_5720VENDOR_M_ST_M45PE20:
14787 case FLASH_5720VENDOR_A_ST_M25PE20:
14788 case FLASH_5720VENDOR_A_ST_M45PE20:
14789 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14790 break;
14791 case FLASH_5720VENDOR_M_ST_M25PE40:
14792 case FLASH_5720VENDOR_M_ST_M45PE40:
14793 case FLASH_5720VENDOR_A_ST_M25PE40:
14794 case FLASH_5720VENDOR_A_ST_M45PE40:
14795 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14796 break;
14797 case FLASH_5720VENDOR_M_ST_M25PE80:
14798 case FLASH_5720VENDOR_M_ST_M45PE80:
14799 case FLASH_5720VENDOR_A_ST_M25PE80:
14800 case FLASH_5720VENDOR_A_ST_M45PE80:
14801 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14802 break;
14803 default:
4153577a 14804 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c5d0b72e 14805 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
9b91b5f1
MC		 14806 break;
14807 }
14808 break;
14809 default:
63c3a66f 14810 tg3_flag_set(tp, NO_NVRAM);
9b91b5f1
MC		 14811 return;
14812 }
14813
14814 tg3_nvram_get_pagesize(tp, nvcfg1);
14815 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
63c3a66f 14816 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
c86a8560 14817
4153577a 14818 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
c86a8560
MC		 14819 u32 val;
14820
14821 if (tg3_nvram_read(tp, 0, &val))
14822 return;
14823
14824 if (val != TG3_EEPROM_MAGIC &&
14825 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14826 tg3_flag_set(tp, NO_NVRAM);
14827 }
9b91b5f1
MC		 14828}
14829
1da177e4 14830/* Chips other than 5700/5701 use the NVRAM for fetching info. */
229b1ad1 14831static void tg3_nvram_init(struct tg3 *tp)
1da177e4 14832{
7e6c63f0
HM		 14833 if (tg3_flag(tp, IS_SSB_CORE)) {
14834 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14835 tg3_flag_clear(tp, NVRAM);
14836 tg3_flag_clear(tp, NVRAM_BUFFERED);
14837 tg3_flag_set(tp, NO_NVRAM);
14838 return;
14839 }
14840
1da177e4
LT		 14841 tw32_f(GRC_EEPROM_ADDR,
14842 (EEPROM_ADDR_FSM_RESET |
14843 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14844 EEPROM_ADDR_CLKPERD_SHIFT)));
14845
9d57f01c 14846 msleep(1);
1da177e4
LT		 14847
14848 /* Enable seeprom accesses. */
14849 tw32_f(GRC_LOCAL_CTRL,
14850 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14851 udelay(100);
14852
4153577a
JP		 14853 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14854 tg3_asic_rev(tp) != ASIC_REV_5701) {
63c3a66f 14855 tg3_flag_set(tp, NVRAM);
1da177e4 14856
ec41c7df 14857 if (tg3_nvram_lock(tp)) {
5129c3a3
MC		 14858 netdev_warn(tp->dev,
14859 "Cannot get nvram lock, %s failed\n",
05dbe005 14860 __func__);
ec41c7df
MC		 14861 return;
14862 }
e6af301b 14863 tg3_enable_nvram_access(tp);
1da177e4 14864
989a9d23
MC		 14865 tp->nvram_size = 0;
14866
4153577a 14867 if (tg3_asic_rev(tp) == ASIC_REV_5752)
361b4ac2 14868 tg3_get_5752_nvram_info(tp);
4153577a 14869 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
d3c7b886 14870 tg3_get_5755_nvram_info(tp);
4153577a
JP		 14871 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14872 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14873 tg3_asic_rev(tp) == ASIC_REV_5785)
1b27777a 14874 tg3_get_5787_nvram_info(tp);
4153577a 14875 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
6b91fa02 14876 tg3_get_5761_nvram_info(tp);
4153577a 14877 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 14878 tg3_get_5906_nvram_info(tp);
4153577a 14879 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 14880 tg3_flag(tp, 57765_CLASS))
321d32a0 14881 tg3_get_57780_nvram_info(tp);
4153577a
JP		 14882 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14883 tg3_asic_rev(tp) == ASIC_REV_5719)
a1b950d5 14884 tg3_get_5717_nvram_info(tp);
4153577a
JP		 14885 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14886 tg3_asic_rev(tp) == ASIC_REV_5762)
9b91b5f1 14887 tg3_get_5720_nvram_info(tp);
361b4ac2
MC		 14888 else
14889 tg3_get_nvram_info(tp);
14890
989a9d23
MC		 14891 if (tp->nvram_size == 0)
14892 tg3_get_nvram_size(tp);
1da177e4 14893
e6af301b 14894 tg3_disable_nvram_access(tp);
381291b7 14895 tg3_nvram_unlock(tp);
1da177e4
LT		 14896
14897 } else {
63c3a66f
JP		 14898 tg3_flag_clear(tp, NVRAM);
14899 tg3_flag_clear(tp, NVRAM_BUFFERED);
1da177e4
LT		 14900
14901 tg3_get_eeprom_size(tp);
14902 }
14903}
14904
1da177e4
LT		 14905struct subsys_tbl_ent {
14906 u16 subsys_vendor, subsys_devid;
14907 u32 phy_id;
14908};
14909
229b1ad1 14910static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
1da177e4 14911 /* Broadcom boards. */
24daf2b0 14912 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14913 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
24daf2b0 14914 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14915 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
24daf2b0 14916 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14917 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
24daf2b0
MC		 14918 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14919 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14920 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14921 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
24daf2b0 14922 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14923 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14924 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14925 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14926 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14927 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
24daf2b0 14928 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14929 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
24daf2b0 14930 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14931 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
24daf2b0 14932 { TG3PCI_SUBVENDOR_ID_BROADCOM,
79eb6904 14933 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
1da177e4
LT		 14934
14935 /* 3com boards. */
24daf2b0 14936 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14937 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
24daf2b0 14938 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14939 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14940 { TG3PCI_SUBVENDOR_ID_3COM,
14941 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14942 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14943 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
24daf2b0 14944 { TG3PCI_SUBVENDOR_ID_3COM,
79eb6904 14945 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14946
14947 /* DELL boards. */
24daf2b0 14948 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14949 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
24daf2b0 14950 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14951 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
24daf2b0 14952 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14953 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
24daf2b0 14954 { TG3PCI_SUBVENDOR_ID_DELL,
79eb6904 14955 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
1da177e4
LT		 14956
14957 /* Compaq boards. */
24daf2b0 14958 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14959 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
24daf2b0 14960 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14961 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
24daf2b0
MC		 14962 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14963 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14964 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14965 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
24daf2b0 14966 { TG3PCI_SUBVENDOR_ID_COMPAQ,
79eb6904 14967 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
1da177e4
LT		 14968
14969 /* IBM boards. */
24daf2b0
MC		 14970 { TG3PCI_SUBVENDOR_ID_IBM,
14971 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
1da177e4
LT		 14972};
14973
229b1ad1 14974static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
1da177e4
LT		 14975{
14976 int i;
14977
14978 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14979 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14980 tp->pdev->subsystem_vendor) &&
14981 (subsys_id_to_phy_id[i].subsys_devid ==
14982 tp->pdev->subsystem_device))
14983 return &subsys_id_to_phy_id[i];
14984 }
14985 return NULL;
14986}
14987
229b1ad1 14988static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 14989{
1da177e4 14990 u32 val;
f49639e6 14991
79eb6904 14992 tp->phy_id = TG3_PHY_ID_INVALID;
7d0c41ef
MC		 14993 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14994
a85feb8c 14995 /* Assume an onboard device and WOL capable by default. */
63c3a66f
JP		 14996 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14997 tg3_flag_set(tp, WOL_CAP);
72b845e0 14998
4153577a 14999 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9d26e213 15000 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
63c3a66f
JP		 15001 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15002 tg3_flag_set(tp, IS_NIC);
9d26e213 15003 }
0527ba35
MC		 15004 val = tr32(VCPU_CFGSHDW);
15005 if (val & VCPU_CFGSHDW_ASPM_DBNC)
63c3a66f 15006 tg3_flag_set(tp, ASPM_WORKAROUND);
0527ba35 15007 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
6fdbab9d 15008 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
63c3a66f 15009 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15010 device_set_wakeup_enable(&tp->pdev->dev, true);
15011 }
05ac4cb7 15012 goto done;
b5d3772c
MC		 15013 }
15014
1da177e4
LT		 15015 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15016 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15017 u32 nic_cfg, led_cfg;
7c786065
NS		 15018 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15019 u32 nic_phy_id, ver, eeprom_phy_id;
7d0c41ef 15020 int eeprom_phy_serdes = 0;
1da177e4
LT		 15021
15022 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15023 tp->nic_sram_data_cfg = nic_cfg;
15024
15025 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15026 ver >>= NIC_SRAM_DATA_VER_SHIFT;
4153577a
JP		 15027 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15028 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15029 tg3_asic_rev(tp) != ASIC_REV_5703 &&
1da177e4
LT		 15030 (ver > 0) && (ver < 0x100))
15031 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15032
4153577a 15033 if (tg3_asic_rev(tp) == ASIC_REV_5785)
a9daf367
MC		 15034 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15035
7c786065
NS		 15036 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15037 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15038 tg3_asic_rev(tp) == ASIC_REV_5720)
15039 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15040
1da177e4
LT		 15041 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15042 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15043 eeprom_phy_serdes = 1;
15044
15045 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15046 if (nic_phy_id != 0) {
15047 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15048 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15049
15050 eeprom_phy_id = (id1 >> 16) << 10;
15051 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15052 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15053 } else
15054 eeprom_phy_id = 0;
15055
7d0c41ef 15056 tp->phy_id = eeprom_phy_id;
747e8f8b 15057 if (eeprom_phy_serdes) {
63c3a66f 15058 if (!tg3_flag(tp, 5705_PLUS))
f07e9af3 15059 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
a50d0796 15060 else
f07e9af3 15061 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
747e8f8b 15062 }
7d0c41ef 15063
63c3a66f 15064 if (tg3_flag(tp, 5750_PLUS))
1da177e4
LT		 15065 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15066 SHASTA_EXT_LED_MODE_MASK);
cbf46853 15067 else
1da177e4
LT		 15068 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15069
15070 switch (led_cfg) {
15071 default:
15072 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15073 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15074 break;
15075
15076 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15077 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15078 break;
15079
15080 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15081 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 15082
15083 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15084 * read on some older 5700/5701 bootcode.
15085 */
4153577a
JP		 15086 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15087 tg3_asic_rev(tp) == ASIC_REV_5701)
9ba27794
MC		 15088 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15089
1da177e4
LT		 15090 break;
15091
15092 case SHASTA_EXT_LED_SHARED:
15093 tp->led_ctrl = LED_CTRL_MODE_SHARED;
4153577a
JP		 15094 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15095 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
1da177e4
LT		 15096 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15097 LED_CTRL_MODE_PHY_2);
89f67978
NS		 15098
15099 if (tg3_flag(tp, 5717_PLUS) ||
15100 tg3_asic_rev(tp) == ASIC_REV_5762)
15101 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15102 LED_CTRL_BLINK_RATE_MASK;
15103
1da177e4
LT		 15104 break;
15105
15106 case SHASTA_EXT_LED_MAC:
15107 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15108 break;
15109
15110 case SHASTA_EXT_LED_COMBO:
15111 tp->led_ctrl = LED_CTRL_MODE_COMBO;
4153577a 15112 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
1da177e4
LT		 15113 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15114 LED_CTRL_MODE_PHY_2);
15115 break;
15116
855e1111 15117 }
1da177e4 15118
4153577a
JP		 15119 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15120 tg3_asic_rev(tp) == ASIC_REV_5701) &&
1da177e4
LT		 15121 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15122 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15123
4153577a 15124 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
b2a5c19c 15125 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
5f60891b 15126
9d26e213 15127 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
63c3a66f 15128 tg3_flag_set(tp, EEPROM_WRITE_PROT);
9d26e213
MC		 15129 if ((tp->pdev->subsystem_vendor ==
15130 PCI_VENDOR_ID_ARIMA) &&
15131 (tp->pdev->subsystem_device == 0x205a ||
15132 tp->pdev->subsystem_device == 0x2063))
63c3a66f 15133 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
9d26e213 15134 } else {
63c3a66f
JP		 15135 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15136 tg3_flag_set(tp, IS_NIC);
9d26e213 15137 }
1da177e4
LT		 15138
15139 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
63c3a66f
JP		 15140 tg3_flag_set(tp, ENABLE_ASF);
15141 if (tg3_flag(tp, 5750_PLUS))
15142 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
1da177e4 15143 }
b2b98d4a
MC		 15144
15145 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
63c3a66f
JP		 15146 tg3_flag(tp, 5750_PLUS))
15147 tg3_flag_set(tp, ENABLE_APE);
b2b98d4a 15148
f07e9af3 15149 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
a85feb8c 15150 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
63c3a66f 15151 tg3_flag_clear(tp, WOL_CAP);
1da177e4 15152
63c3a66f 15153 if (tg3_flag(tp, WOL_CAP) &&
6fdbab9d 15154 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
63c3a66f 15155 tg3_flag_set(tp, WOL_ENABLE);
6fdbab9d
RW		 15156 device_set_wakeup_enable(&tp->pdev->dev, true);
15157 }
0527ba35 15158
1da177e4 15159 if (cfg2 & (1 << 17))
f07e9af3 15160 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
1da177e4
LT		 15161
15162 /* serdes signal pre-emphasis in register 0x590 set by */
15163 /* bootcode if bit 18 is set */
15164 if (cfg2 & (1 << 18))
f07e9af3 15165 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
8ed5d97e 15166
63c3a66f 15167 if ((tg3_flag(tp, 57765_PLUS) ||
4153577a
JP		 15168 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15169 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
6833c043 15170 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
f07e9af3 15171 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
6833c043 15172
942d1af0 15173 if (tg3_flag(tp, PCI_EXPRESS)) {
8ed5d97e
MC		 15174 u32 cfg3;
15175
15176 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
942d1af0
NS		 15177 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15178 !tg3_flag(tp, 57765_PLUS) &&
15179 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
63c3a66f 15180 tg3_flag_set(tp, ASPM_WORKAROUND);
942d1af0
NS		 15181 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15182 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15183 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15184 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
8ed5d97e 15185 }
a9daf367 15186
14417063 15187 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
63c3a66f 15188 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
a9daf367 15189 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
63c3a66f 15190 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
a9daf367 15191 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
63c3a66f 15192 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
7c786065
NS		 15193
15194 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15195 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
1da177e4 15196 }
05ac4cb7 15197done:
63c3a66f 15198 if (tg3_flag(tp, WOL_CAP))
43067ed8 15199 device_set_wakeup_enable(&tp->pdev->dev,
63c3a66f 15200 tg3_flag(tp, WOL_ENABLE));
43067ed8
RW		 15201 else
15202 device_set_wakeup_capable(&tp->pdev->dev, false);
7d0c41ef
MC		 15203}
15204
c86a8560
MC		 15205static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15206{
15207 int i, err;
15208 u32 val2, off = offset * 8;
15209
15210 err = tg3_nvram_lock(tp);
15211 if (err)
15212 return err;
15213
15214 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15215 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15216 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15217 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15218 udelay(10);
15219
15220 for (i = 0; i < 100; i++) {
15221 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15222 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15223 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15224 break;
15225 }
15226 udelay(10);
15227 }
15228
15229 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15230
15231 tg3_nvram_unlock(tp);
15232 if (val2 & APE_OTP_STATUS_CMD_DONE)
15233 return 0;
15234
15235 return -EBUSY;
15236}
15237
229b1ad1 15238static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
b2a5c19c
MC		 15239{
15240 int i;
15241 u32 val;
15242
15243 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15244 tw32(OTP_CTRL, cmd);
15245
15246 /* Wait for up to 1 ms for command to execute. */
15247 for (i = 0; i < 100; i++) {
15248 val = tr32(OTP_STATUS);
15249 if (val & OTP_STATUS_CMD_DONE)
15250 break;
15251 udelay(10);
15252 }
15253
15254 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15255}
15256
15257/* Read the gphy configuration from the OTP region of the chip. The gphy
15258 * configuration is a 32-bit value that straddles the alignment boundary.
15259 * We do two 32-bit reads and then shift and merge the results.
15260 */
229b1ad1 15261static u32 tg3_read_otp_phycfg(struct tg3 *tp)
b2a5c19c
MC		 15262{
15263 u32 bhalf_otp, thalf_otp;
15264
15265 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15266
15267 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15268 return 0;
15269
15270 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15271
15272 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15273 return 0;
15274
15275 thalf_otp = tr32(OTP_READ_DATA);
15276
15277 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15278
15279 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15280 return 0;
15281
15282 bhalf_otp = tr32(OTP_READ_DATA);
15283
15284 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15285}
15286
229b1ad1 15287static void tg3_phy_init_link_config(struct tg3 *tp)
e256f8a3 15288{
202ff1c2 15289 u32 adv = ADVERTISED_Autoneg;
e256f8a3 15290
7c786065
NS		 15291 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15292 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15293 adv |= ADVERTISED_1000baseT_Half;
15294 adv |= ADVERTISED_1000baseT_Full;
15295 }
e256f8a3
MC		 15296
15297 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15298 adv |= ADVERTISED_100baseT_Half |
15299 ADVERTISED_100baseT_Full |
15300 ADVERTISED_10baseT_Half |
15301 ADVERTISED_10baseT_Full |
15302 ADVERTISED_TP;
15303 else
15304 adv |= ADVERTISED_FIBRE;
15305
15306 tp->link_config.advertising = adv;
e740522e
MC		 15307 tp->link_config.speed = SPEED_UNKNOWN;
15308 tp->link_config.duplex = DUPLEX_UNKNOWN;
e256f8a3 15309 tp->link_config.autoneg = AUTONEG_ENABLE;
e740522e
MC		 15310 tp->link_config.active_speed = SPEED_UNKNOWN;
15311 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
34655ad6
MC		 15312
15313 tp->old_link = -1;
e256f8a3
MC		 15314}
15315
229b1ad1 15316static int tg3_phy_probe(struct tg3 *tp)
7d0c41ef
MC		 15317{
15318 u32 hw_phy_id_1, hw_phy_id_2;
15319 u32 hw_phy_id, hw_phy_id_masked;
15320 int err;
1da177e4 15321
e256f8a3 15322 /* flow control autonegotiation is default behavior */
63c3a66f 15323 tg3_flag_set(tp, PAUSE_AUTONEG);
e256f8a3
MC		 15324 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15325
8151ad57
MC		 15326 if (tg3_flag(tp, ENABLE_APE)) {
15327 switch (tp->pci_fn) {
15328 case 0:
15329 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15330 break;
15331 case 1:
15332 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15333 break;
15334 case 2:
15335 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15336 break;
15337 case 3:
15338 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15339 break;
15340 }
15341 }
15342
942d1af0
NS		 15343 if (!tg3_flag(tp, ENABLE_ASF) &&
15344 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15345 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15346 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15347 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15348
63c3a66f 15349 if (tg3_flag(tp, USE_PHYLIB))
b02fd9e3
MC		 15350 return tg3_phy_init(tp);
15351
1da177e4 15352 /* Reading the PHY ID register can conflict with ASF
877d0310 15353 * firmware access to the PHY hardware.
1da177e4
LT		 15354 */
15355 err = 0;
63c3a66f 15356 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
79eb6904 15357 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
1da177e4
LT		 15358 } else {
15359 /* Now read the physical PHY_ID from the chip and verify
15360 * that it is sane. If it doesn't look good, we fall back
15361 * to either the hard-coded table based PHY_ID and failing
15362 * that the value found in the eeprom area.
15363 */
15364 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15365 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15366
15367 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15368 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15369 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15370
79eb6904 15371 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
1da177e4
LT		 15372 }
15373
79eb6904 15374 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
1da177e4 15375 tp->phy_id = hw_phy_id;
79eb6904 15376 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
f07e9af3 15377 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
da6b2d01 15378 else
f07e9af3 15379 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
1da177e4 15380 } else {
79eb6904 15381 if (tp->phy_id != TG3_PHY_ID_INVALID) {
7d0c41ef
MC		 15382 /* Do nothing, phy ID already set up in
15383 * tg3_get_eeprom_hw_cfg().
15384 */
1da177e4
LT		 15385 } else {
15386 struct subsys_tbl_ent *p;
15387
15388 /* No eeprom signature? Try the hardcoded
15389 * subsys device table.
15390 */
24daf2b0 15391 p = tg3_lookup_by_subsys(tp);
7e6c63f0
HM		 15392 if (p) {
15393 tp->phy_id = p->phy_id;
15394 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15395 /* For now we saw the IDs 0xbc050cd0,
15396 * 0xbc050f80 and 0xbc050c30 on devices
15397 * connected to an BCM4785 and there are
15398 * probably more. Just assume that the phy is
15399 * supported when it is connected to a SSB core
15400 * for now.
15401 */
1da177e4 15402 return -ENODEV;
7e6c63f0 15403 }
1da177e4 15404
1da177e4 15405 if (!tp->phy_id ||
79eb6904 15406 tp->phy_id == TG3_PHY_ID_BCM8002)
f07e9af3 15407 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
1da177e4
LT		 15408 }
15409 }
15410
a6b68dab 15411 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
4153577a
JP		 15412 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15413 tg3_asic_rev(tp) == ASIC_REV_5720 ||
c4dab506 15414 tg3_asic_rev(tp) == ASIC_REV_57766 ||
4153577a
JP		 15415 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15416 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15417 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15418 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
9e2ecbeb 15419 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
52b02d04
MC		 15420 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15421
9e2ecbeb
NS		 15422 tp->eee.supported = SUPPORTED_100baseT_Full |
15423 SUPPORTED_1000baseT_Full;
15424 tp->eee.advertised = ADVERTISED_100baseT_Full |
15425 ADVERTISED_1000baseT_Full;
15426 tp->eee.eee_enabled = 1;
15427 tp->eee.tx_lpi_enabled = 1;
15428 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15429 }
15430
e256f8a3
MC		 15431 tg3_phy_init_link_config(tp);
15432
942d1af0
NS		 15433 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15434 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
63c3a66f
JP		 15435 !tg3_flag(tp, ENABLE_APE) &&
15436 !tg3_flag(tp, ENABLE_ASF)) {
e2bf73e7 15437 u32 bmsr, dummy;
1da177e4
LT		 15438
15439 tg3_readphy(tp, MII_BMSR, &bmsr);
15440 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15441 (bmsr & BMSR_LSTATUS))
15442 goto skip_phy_reset;
6aa20a22 15443
1da177e4
LT		 15444 err = tg3_phy_reset(tp);
15445 if (err)
15446 return err;
15447
42b64a45 15448 tg3_phy_set_wirespeed(tp);
1da177e4 15449
e2bf73e7 15450 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
42b64a45
MC		 15451 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15452 tp->link_config.flowctrl);
1da177e4
LT		 15453
15454 tg3_writephy(tp, MII_BMCR,
15455 BMCR_ANENABLE | BMCR_ANRESTART);
15456 }
1da177e4
LT		 15457 }
15458
15459skip_phy_reset:
79eb6904 15460 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1da177e4
LT		 15461 err = tg3_init_5401phy_dsp(tp);
15462 if (err)
15463 return err;
1da177e4 15464
1da177e4
LT		 15465 err = tg3_init_5401phy_dsp(tp);
15466 }
15467
1da177e4
LT		 15468 return err;
15469}
15470
229b1ad1 15471static void tg3_read_vpd(struct tg3 *tp)
1da177e4 15472{
a4a8bb15 15473 u8 *vpd_data;
4181b2c8 15474 unsigned int block_end, rosize, len;
535a490e 15475 u32 vpdlen;
184b8904 15476 int j, i = 0;
a4a8bb15 15477
535a490e 15478 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
a4a8bb15
MC		 15479 if (!vpd_data)
15480 goto out_no_vpd;
1da177e4 15481
535a490e 15482 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
4181b2c8
MC		 15483 if (i < 0)
15484 goto out_not_found;
1da177e4 15485
4181b2c8
MC		 15486 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15487 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15488 i += PCI_VPD_LRDT_TAG_SIZE;
1da177e4 15489
535a490e 15490 if (block_end > vpdlen)
4181b2c8 15491 goto out_not_found;
af2c6a4a 15492
184b8904
MC		 15493 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15494 PCI_VPD_RO_KEYWORD_MFR_ID);
15495 if (j > 0) {
15496 len = pci_vpd_info_field_size(&vpd_data[j]);
15497
15498 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15499 if (j + len > block_end || len != 4 ||
15500 memcmp(&vpd_data[j], "1028", 4))
15501 goto partno;
15502
15503 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15504 PCI_VPD_RO_KEYWORD_VENDOR0);
15505 if (j < 0)
15506 goto partno;
15507
15508 len = pci_vpd_info_field_size(&vpd_data[j]);
15509
15510 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15511 if (j + len > block_end)
15512 goto partno;
15513
715230a4
KC		 15514 if (len >= sizeof(tp->fw_ver))
15515 len = sizeof(tp->fw_ver) - 1;
15516 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15517 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15518 &vpd_data[j]);
184b8904
MC		 15519 }
15520
15521partno:
4181b2c8
MC		 15522 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15523 PCI_VPD_RO_KEYWORD_PARTNO);
15524 if (i < 0)
15525 goto out_not_found;
af2c6a4a 15526
4181b2c8 15527 len = pci_vpd_info_field_size(&vpd_data[i]);
1da177e4 15528
4181b2c8
MC		 15529 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15530 if (len > TG3_BPN_SIZE ||
535a490e 15531 (len + i) > vpdlen)
4181b2c8 15532 goto out_not_found;
1da177e4 15533
4181b2c8 15534 memcpy(tp->board_part_number, &vpd_data[i], len);
1da177e4 15535
1da177e4 15536out_not_found:
a4a8bb15 15537 kfree(vpd_data);
37a949c5 15538 if (tp->board_part_number[0])
a4a8bb15
MC		 15539 return;
15540
15541out_no_vpd:
4153577a 15542 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
79d49695
MC		 15543 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15544 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
37a949c5
MC		 15545 strcpy(tp->board_part_number, "BCM5717");
15546 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15547 strcpy(tp->board_part_number, "BCM5718");
15548 else
15549 goto nomatch;
4153577a 15550 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
37a949c5
MC		 15551 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15552 strcpy(tp->board_part_number, "BCM57780");
15553 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15554 strcpy(tp->board_part_number, "BCM57760");
15555 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15556 strcpy(tp->board_part_number, "BCM57790");
15557 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15558 strcpy(tp->board_part_number, "BCM57788");
15559 else
15560 goto nomatch;
4153577a 15561 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
37a949c5
MC		 15562 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15563 strcpy(tp->board_part_number, "BCM57761");
15564 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15565 strcpy(tp->board_part_number, "BCM57765");
15566 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15567 strcpy(tp->board_part_number, "BCM57781");
15568 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15569 strcpy(tp->board_part_number, "BCM57785");
15570 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15571 strcpy(tp->board_part_number, "BCM57791");
15572 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15573 strcpy(tp->board_part_number, "BCM57795");
15574 else
15575 goto nomatch;
4153577a 15576 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
55086ad9
MC		 15577 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15578 strcpy(tp->board_part_number, "BCM57762");
15579 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15580 strcpy(tp->board_part_number, "BCM57766");
15581 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15582 strcpy(tp->board_part_number, "BCM57782");
15583 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15584 strcpy(tp->board_part_number, "BCM57786");
15585 else
15586 goto nomatch;
4153577a 15587 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c 15588 strcpy(tp->board_part_number, "BCM95906");
37a949c5
MC		 15589 } else {
15590nomatch:
b5d3772c 15591 strcpy(tp->board_part_number, "none");
37a949c5 15592 }
1da177e4
LT		 15593}
15594
229b1ad1 15595static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
9c8a620e
MC		 15596{
15597 u32 val;
15598
e4f34110 15599 if (tg3_nvram_read(tp, offset, &val) ||
9c8a620e 15600 (val & 0xfc000000) != 0x0c000000 ||
e4f34110 15601 tg3_nvram_read(tp, offset + 4, &val) ||
9c8a620e
MC		 15602 val != 0)
15603 return 0;
15604
15605 return 1;
15606}
15607
229b1ad1 15608static void tg3_read_bc_ver(struct tg3 *tp)
acd9c119 15609{
ff3a7cb2 15610 u32 val, offset, start, ver_offset;
75f9936e 15611 int i, dst_off;
ff3a7cb2 15612 bool newver = false;
acd9c119
MC		 15613
15614 if (tg3_nvram_read(tp, 0xc, &offset) ||
15615 tg3_nvram_read(tp, 0x4, &start))
15616 return;
15617
15618 offset = tg3_nvram_logical_addr(tp, offset);
15619
ff3a7cb2 15620 if (tg3_nvram_read(tp, offset, &val))
acd9c119
MC		 15621 return;
15622
ff3a7cb2
MC		 15623 if ((val & 0xfc000000) == 0x0c000000) {
15624 if (tg3_nvram_read(tp, offset + 4, &val))
acd9c119
MC		 15625 return;
15626
ff3a7cb2
MC		 15627 if (val == 0)
15628 newver = true;
15629 }
15630
75f9936e
MC		 15631 dst_off = strlen(tp->fw_ver);
15632
ff3a7cb2 15633 if (newver) {
75f9936e
MC		 15634 if (TG3_VER_SIZE - dst_off < 16 ||
15635 tg3_nvram_read(tp, offset + 8, &ver_offset))
ff3a7cb2
MC		 15636 return;
15637
15638 offset = offset + ver_offset - start;
15639 for (i = 0; i < 16; i += 4) {
15640 __be32 v;
15641 if (tg3_nvram_read_be32(tp, offset + i, &v))
15642 return;
15643
75f9936e 15644 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
ff3a7cb2
MC		 15645 }
15646 } else {
15647 u32 major, minor;
15648
15649 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15650 return;
15651
15652 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15653 TG3_NVM_BCVER_MAJSFT;
15654 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
75f9936e
MC		 15655 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15656 "v%d.%02d", major, minor);
acd9c119
MC		 15657 }
15658}
15659
229b1ad1 15660static void tg3_read_hwsb_ver(struct tg3 *tp)
a6f6cb1c
MC		 15661{
15662 u32 val, major, minor;
15663
15664 /* Use native endian representation */
15665 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15666 return;
15667
15668 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15669 TG3_NVM_HWSB_CFG1_MAJSFT;
15670 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15671 TG3_NVM_HWSB_CFG1_MINSFT;
15672
15673 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15674}
15675
229b1ad1 15676static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
dfe00d7d
MC		 15677{
15678 u32 offset, major, minor, build;
15679
75f9936e 15680 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
dfe00d7d
MC		 15681
15682 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15683 return;
15684
15685 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15686 case TG3_EEPROM_SB_REVISION_0:
15687 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15688 break;
15689 case TG3_EEPROM_SB_REVISION_2:
15690 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15691 break;
15692 case TG3_EEPROM_SB_REVISION_3:
15693 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15694 break;
a4153d40
MC		 15695 case TG3_EEPROM_SB_REVISION_4:
15696 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15697 break;
15698 case TG3_EEPROM_SB_REVISION_5:
15699 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15700 break;
bba226ac
MC		 15701 case TG3_EEPROM_SB_REVISION_6:
15702 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15703 break;
dfe00d7d
MC		 15704 default:
15705 return;
15706 }
15707
e4f34110 15708 if (tg3_nvram_read(tp, offset, &val))
dfe00d7d
MC		 15709 return;
15710
15711 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15712 TG3_EEPROM_SB_EDH_BLD_SHFT;
15713 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15714 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15715 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15716
15717 if (minor > 99 || build > 26)
15718 return;
15719
75f9936e
MC		 15720 offset = strlen(tp->fw_ver);
15721 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15722 " v%d.%02d", major, minor);
dfe00d7d
MC		 15723
15724 if (build > 0) {
75f9936e
MC		 15725 offset = strlen(tp->fw_ver);
15726 if (offset < TG3_VER_SIZE - 1)
15727 tp->fw_ver[offset] = 'a' + build - 1;
dfe00d7d
MC		 15728 }
15729}
15730
229b1ad1 15731static void tg3_read_mgmtfw_ver(struct tg3 *tp)
c4e6575c
MC		 15732{
15733 u32 val, offset, start;
acd9c119 15734 int i, vlen;
9c8a620e
MC		 15735
15736 for (offset = TG3_NVM_DIR_START;
15737 offset < TG3_NVM_DIR_END;
15738 offset += TG3_NVM_DIRENT_SIZE) {
e4f34110 15739 if (tg3_nvram_read(tp, offset, &val))
c4e6575c
MC		 15740 return;
15741
9c8a620e
MC		 15742 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15743 break;
15744 }
15745
15746 if (offset == TG3_NVM_DIR_END)
15747 return;
15748
63c3a66f 15749 if (!tg3_flag(tp, 5705_PLUS))
9c8a620e 15750 start = 0x08000000;
e4f34110 15751 else if (tg3_nvram_read(tp, offset - 4, &start))
9c8a620e
MC		 15752 return;
15753
e4f34110 15754 if (tg3_nvram_read(tp, offset + 4, &offset) ||
9c8a620e 15755 !tg3_fw_img_is_valid(tp, offset) ||
e4f34110 15756 tg3_nvram_read(tp, offset + 8, &val))
9c8a620e
MC		 15757 return;
15758
15759 offset += val - start;
15760
acd9c119 15761 vlen = strlen(tp->fw_ver);
9c8a620e 15762
acd9c119
MC		 15763 tp->fw_ver[vlen++] = ',';
15764 tp->fw_ver[vlen++] = ' ';
9c8a620e
MC		 15765
15766 for (i = 0; i < 4; i++) {
a9dc529d
MC		 15767 __be32 v;
15768 if (tg3_nvram_read_be32(tp, offset, &v))
c4e6575c
MC		 15769 return;
15770
b9fc7dc5 15771 offset += sizeof(v);
c4e6575c 15772
acd9c119
MC		 15773 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15774 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
9c8a620e 15775 break;
c4e6575c 15776 }
9c8a620e 15777
acd9c119
MC		 15778 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15779 vlen += sizeof(v);
c4e6575c 15780 }
acd9c119
MC		 15781}
15782
229b1ad1 15783static void tg3_probe_ncsi(struct tg3 *tp)
7fd76445 15784{
7fd76445 15785 u32 apedata;
7fd76445
MC		 15786
15787 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15788 if (apedata != APE_SEG_SIG_MAGIC)
15789 return;
15790
15791 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15792 if (!(apedata & APE_FW_STATUS_READY))
15793 return;
15794
165f4d1c
MC		 15795 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15796 tg3_flag_set(tp, APE_HAS_NCSI);
15797}
15798
229b1ad1 15799static void tg3_read_dash_ver(struct tg3 *tp)
165f4d1c
MC		 15800{
15801 int vlen;
15802 u32 apedata;
15803 char *fwtype;
15804
7fd76445
MC		 15805 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15806
165f4d1c 15807 if (tg3_flag(tp, APE_HAS_NCSI))
ecc79648 15808 fwtype = "NCSI";
c86a8560
MC		 15809 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15810 fwtype = "SMASH";
165f4d1c 15811 else
ecc79648
MC		 15812 fwtype = "DASH";
15813
7fd76445
MC		 15814 vlen = strlen(tp->fw_ver);
15815
ecc79648
MC		 15816 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15817 fwtype,
7fd76445
MC		 15818 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15819 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15820 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15821 (apedata & APE_FW_VERSION_BLDMSK));
15822}
15823
c86a8560
MC		 15824static void tg3_read_otp_ver(struct tg3 *tp)
15825{
15826 u32 val, val2;
15827
4153577a 15828 if (tg3_asic_rev(tp) != ASIC_REV_5762)
c86a8560
MC		 15829 return;
15830
15831 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15832 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15833 TG3_OTP_MAGIC0_VALID(val)) {
15834 u64 val64 = (u64) val << 32 | val2;
15835 u32 ver = 0;
15836 int i, vlen;
15837
15838 for (i = 0; i < 7; i++) {
15839 if ((val64 & 0xff) == 0)
15840 break;
15841 ver = val64 & 0xff;
15842 val64 >>= 8;
15843 }
15844 vlen = strlen(tp->fw_ver);
15845 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15846 }
15847}
15848
229b1ad1 15849static void tg3_read_fw_ver(struct tg3 *tp)
acd9c119
MC		 15850{
15851 u32 val;
75f9936e 15852 bool vpd_vers = false;
acd9c119 15853
75f9936e
MC		 15854 if (tp->fw_ver[0] != 0)
15855 vpd_vers = true;
df259d8c 15856
63c3a66f 15857 if (tg3_flag(tp, NO_NVRAM)) {
75f9936e 15858 strcat(tp->fw_ver, "sb");
c86a8560 15859 tg3_read_otp_ver(tp);
df259d8c
MC		 15860 return;
15861 }
15862
acd9c119
MC		 15863 if (tg3_nvram_read(tp, 0, &val))
15864 return;
15865
15866 if (val == TG3_EEPROM_MAGIC)
15867 tg3_read_bc_ver(tp);
15868 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15869 tg3_read_sb_ver(tp, val);
a6f6cb1c
MC		 15870 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15871 tg3_read_hwsb_ver(tp);
acd9c119 15872
165f4d1c
MC		 15873 if (tg3_flag(tp, ENABLE_ASF)) {
15874 if (tg3_flag(tp, ENABLE_APE)) {
15875 tg3_probe_ncsi(tp);
15876 if (!vpd_vers)
15877 tg3_read_dash_ver(tp);
15878 } else if (!vpd_vers) {
15879 tg3_read_mgmtfw_ver(tp);
15880 }
c9cab24e 15881 }
9c8a620e
MC		 15882
15883 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
c4e6575c
MC		 15884}
15885
7cb32cf2
MC		 15886static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15887{
63c3a66f 15888 if (tg3_flag(tp, LRG_PROD_RING_CAP))
de9f5230 15889 return TG3_RX_RET_MAX_SIZE_5717;
63c3a66f 15890 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
de9f5230 15891 return TG3_RX_RET_MAX_SIZE_5700;
7cb32cf2 15892 else
de9f5230 15893 return TG3_RX_RET_MAX_SIZE_5705;
7cb32cf2
MC		 15894}
15895
4143470c 15896static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
895950c2
JP		 15897 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15898 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15899 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15900 { },
15901};
15902
229b1ad1 15903static struct pci_dev *tg3_find_peer(struct tg3 *tp)
16c7fa7d
MC		 15904{
15905 struct pci_dev *peer;
15906 unsigned int func, devnr = tp->pdev->devfn & ~7;
15907
15908 for (func = 0; func < 8; func++) {
15909 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15910 if (peer && peer != tp->pdev)
15911 break;
15912 pci_dev_put(peer);
15913 }
15914 /* 5704 can be configured in single-port mode, set peer to
15915 * tp->pdev in that case.
15916 */
15917 if (!peer) {
15918 peer = tp->pdev;
15919 return peer;
15920 }
15921
15922 /*
15923 * We don't need to keep the refcount elevated; there's no way
15924 * to remove one half of this device without removing the other
15925 */
15926 pci_dev_put(peer);
15927
15928 return peer;
15929}
15930
229b1ad1 15931static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
42b123b1
MC		 15932{
15933 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
4153577a 15934 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
42b123b1
MC		 15935 u32 reg;
15936
15937 /* All devices that use the alternate
15938 * ASIC REV location have a CPMU.
15939 */
15940 tg3_flag_set(tp, CPMU_PRESENT);
15941
15942 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 15943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
42b123b1
MC		 15944 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 15946 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 15947 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15948 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 15949 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 15951 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
42b123b1
MC		 15953 reg = TG3PCI_GEN2_PRODID_ASICREV;
15954 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15955 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15956 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15957 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15958 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15959 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15960 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15961 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15962 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15963 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15964 reg = TG3PCI_GEN15_PRODID_ASICREV;
15965 else
15966 reg = TG3PCI_PRODID_ASICREV;
15967
15968 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15969 }
15970
15971 /* Wrong chip ID in 5752 A0. This code can be removed later
15972 * as A0 is not in production.
15973 */
4153577a 15974 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
42b123b1
MC		 15975 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15976
4153577a 15977 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
79d49695
MC		 15978 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15979
4153577a
JP		 15980 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15981 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15982 tg3_asic_rev(tp) == ASIC_REV_5720)
42b123b1
MC		 15983 tg3_flag_set(tp, 5717_PLUS);
15984
4153577a
JP		 15985 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15986 tg3_asic_rev(tp) == ASIC_REV_57766)
42b123b1
MC		 15987 tg3_flag_set(tp, 57765_CLASS);
15988
c65a17f4 15989 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
4153577a 15990 tg3_asic_rev(tp) == ASIC_REV_5762)
42b123b1
MC		 15991 tg3_flag_set(tp, 57765_PLUS);
15992
15993 /* Intentionally exclude ASIC_REV_5906 */
4153577a
JP		 15994 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15995 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15996 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15997 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15998 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15999 tg3_asic_rev(tp) == ASIC_REV_57780 ||
42b123b1
MC		 16000 tg3_flag(tp, 57765_PLUS))
16001 tg3_flag_set(tp, 5755_PLUS);
16002
4153577a
JP		 16003 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16004 tg3_asic_rev(tp) == ASIC_REV_5714)
42b123b1
MC		 16005 tg3_flag_set(tp, 5780_CLASS);
16006
4153577a
JP		 16007 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16008 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16009 tg3_asic_rev(tp) == ASIC_REV_5906 ||
42b123b1
MC		 16010 tg3_flag(tp, 5755_PLUS) ||
16011 tg3_flag(tp, 5780_CLASS))
16012 tg3_flag_set(tp, 5750_PLUS);
16013
4153577a 16014 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
42b123b1
MC		 16015 tg3_flag(tp, 5750_PLUS))
16016 tg3_flag_set(tp, 5705_PLUS);
16017}
16018
3d567e0e
NNS		 16019static bool tg3_10_100_only_device(struct tg3 *tp,
16020 const struct pci_device_id *ent)
16021{
16022 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16023
4153577a
JP		 16024 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16025 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
3d567e0e
NNS		 16026 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16027 return true;
16028
16029 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
4153577a 16030 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3d567e0e
NNS		 16031 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16032 return true;
16033 } else {
16034 return true;
16035 }
16036 }
16037
16038 return false;
16039}
16040
1dd06ae8 16041static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
1da177e4 16042{
1da177e4 16043 u32 misc_ctrl_reg;
1da177e4
LT		 16044 u32 pci_state_reg, grc_misc_cfg;
16045 u32 val;
16046 u16 pci_cmd;
5e7dfd0f 16047 int err;
1da177e4 16048
1da177e4
LT		 16049 /* Force memory write invalidate off. If we leave it on,
16050 * then on 5700_BX chips we have to enable a workaround.
16051 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16052 * to match the cacheline size. The Broadcom driver have this
16053 * workaround but turns MWI off all the times so never uses
16054 * it. This seems to suggest that the workaround is insufficient.
16055 */
16056 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16057 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16058 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16059
16821285
MC		 16060 /* Important! -- Make sure register accesses are byteswapped
16061 * correctly. Also, for those chips that require it, make
16062 * sure that indirect register accesses are enabled before
16063 * the first operation.
1da177e4
LT		 16064 */
16065 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16066 &misc_ctrl_reg);
16821285
MC		 16067 tp->misc_host_ctrl |= (misc_ctrl_reg &
16068 MISC_HOST_CTRL_CHIPREV);
16069 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16070 tp->misc_host_ctrl);
1da177e4 16071
42b123b1 16072 tg3_detect_asic_rev(tp, misc_ctrl_reg);
ff645bec 16073
6892914f
MC		 16074 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16075 * we need to disable memory and use config. cycles
16076 * only to access all registers. The 5702/03 chips
16077 * can mistakenly decode the special cycles from the
16078 * ICH chipsets as memory write cycles, causing corruption
16079 * of register and memory space. Only certain ICH bridges
16080 * will drive special cycles with non-zero data during the
16081 * address phase which can fall within the 5703's address
16082 * range. This is not an ICH bug as the PCI spec allows
16083 * non-zero address during special cycles. However, only
16084 * these ICH bridges are known to drive non-zero addresses
16085 * during special cycles.
16086 *
16087 * Since special cycles do not cross PCI bridges, we only
16088 * enable this workaround if the 5703 is on the secondary
16089 * bus of these ICH bridges.
16090 */
4153577a
JP		 16091 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16092 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
6892914f
MC		 16093 static struct tg3_dev_id {
16094 u32 vendor;
16095 u32 device;
16096 u32 rev;
16097 } ich_chipsets[] = {
16098 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16099 PCI_ANY_ID },
16100 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16101 PCI_ANY_ID },
16102 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16103 0xa },
16104 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16105 PCI_ANY_ID },
16106 { },
16107 };
16108 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16109 struct pci_dev *bridge = NULL;
16110
16111 while (pci_id->vendor != 0) {
16112 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16113 bridge);
16114 if (!bridge) {
16115 pci_id++;
16116 continue;
16117 }
16118 if (pci_id->rev != PCI_ANY_ID) {
44c10138 16119 if (bridge->revision > pci_id->rev)
6892914f
MC		 16120 continue;
16121 }
16122 if (bridge->subordinate &&
16123 (bridge->subordinate->number ==
16124 tp->pdev->bus->number)) {
63c3a66f 16125 tg3_flag_set(tp, ICH_WORKAROUND);
6892914f
MC		 16126 pci_dev_put(bridge);
16127 break;
16128 }
16129 }
16130 }
16131
4153577a 16132 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
41588ba1
MC		 16133 static struct tg3_dev_id {
16134 u32 vendor;
16135 u32 device;
16136 } bridge_chipsets[] = {
16137 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16138 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16139 { },
16140 };
16141 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16142 struct pci_dev *bridge = NULL;
16143
16144 while (pci_id->vendor != 0) {
16145 bridge = pci_get_device(pci_id->vendor,
16146 pci_id->device,
16147 bridge);
16148 if (!bridge) {
16149 pci_id++;
16150 continue;
16151 }
16152 if (bridge->subordinate &&
16153 (bridge->subordinate->number <=
16154 tp->pdev->bus->number) &&
b918c62e 16155 (bridge->subordinate->busn_res.end >=
41588ba1 16156 tp->pdev->bus->number)) {
63c3a66f 16157 tg3_flag_set(tp, 5701_DMA_BUG);
41588ba1
MC		 16158 pci_dev_put(bridge);
16159 break;
16160 }
16161 }
16162 }
16163
4a29cc2e
MC		 16164 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16165 * DMA addresses > 40-bit. This bridge may have other additional
16166 * 57xx devices behind it in some 4-port NIC designs for example.
16167 * Any tg3 device found behind the bridge will also need the 40-bit
16168 * DMA workaround.
16169 */
42b123b1 16170 if (tg3_flag(tp, 5780_CLASS)) {
63c3a66f 16171 tg3_flag_set(tp, 40BIT_DMA_BUG);
0f847584 16172 tp->msi_cap = tp->pdev->msi_cap;
859a5887 16173 } else {
4a29cc2e
MC		 16174 struct pci_dev *bridge = NULL;
16175
16176 do {
16177 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16178 PCI_DEVICE_ID_SERVERWORKS_EPB,
16179 bridge);
16180 if (bridge && bridge->subordinate &&
16181 (bridge->subordinate->number <=
16182 tp->pdev->bus->number) &&
b918c62e 16183 (bridge->subordinate->busn_res.end >=
4a29cc2e 16184 tp->pdev->bus->number)) {
63c3a66f 16185 tg3_flag_set(tp, 40BIT_DMA_BUG);
4a29cc2e
MC		 16186 pci_dev_put(bridge);
16187 break;
16188 }
16189 } while (bridge);
16190 }
4cf78e4f 16191
4153577a
JP		 16192 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16193 tg3_asic_rev(tp) == ASIC_REV_5714)
7544b097
MC		 16194 tp->pdev_peer = tg3_find_peer(tp);
16195
507399f1 16196 /* Determine TSO capabilities */
4153577a 16197 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
4d163b75 16198 ; /* Do nothing. HW bug. */
63c3a66f
JP		 16199 else if (tg3_flag(tp, 57765_PLUS))
16200 tg3_flag_set(tp, HW_TSO_3);
16201 else if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16202 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f
JP		 16203 tg3_flag_set(tp, HW_TSO_2);
16204 else if (tg3_flag(tp, 5750_PLUS)) {
16205 tg3_flag_set(tp, HW_TSO_1);
16206 tg3_flag_set(tp, TSO_BUG);
4153577a
JP		 16207 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16208 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
63c3a66f 16209 tg3_flag_clear(tp, TSO_BUG);
4153577a
JP		 16210 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16211 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16212 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
1caf13eb
MC		 16213 tg3_flag_set(tp, FW_TSO);
16214 tg3_flag_set(tp, TSO_BUG);
4153577a 16215 if (tg3_asic_rev(tp) == ASIC_REV_5705)
507399f1
MC		 16216 tp->fw_needed = FIRMWARE_TG3TSO5;
16217 else
16218 tp->fw_needed = FIRMWARE_TG3TSO;
16219 }
16220
dabc5c67 16221 /* Selectively allow TSO based on operating conditions */
6ff6f81d
MC		 16222 if (tg3_flag(tp, HW_TSO_1) ||
16223 tg3_flag(tp, HW_TSO_2) ||
16224 tg3_flag(tp, HW_TSO_3) ||
1caf13eb 16225 tg3_flag(tp, FW_TSO)) {
cf9ecf4b
MC		 16226 /* For firmware TSO, assume ASF is disabled.
16227 * We'll disable TSO later if we discover ASF
16228 * is enabled in tg3_get_eeprom_hw_cfg().
16229 */
dabc5c67 16230 tg3_flag_set(tp, TSO_CAPABLE);
cf9ecf4b 16231 } else {
dabc5c67
MC		 16232 tg3_flag_clear(tp, TSO_CAPABLE);
16233 tg3_flag_clear(tp, TSO_BUG);
16234 tp->fw_needed = NULL;
16235 }
16236
4153577a 16237 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
dabc5c67
MC		 16238 tp->fw_needed = FIRMWARE_TG3;
16239
c4dab506
NS		 16240 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16241 tp->fw_needed = FIRMWARE_TG357766;
16242
507399f1
MC		 16243 tp->irq_max = 1;
16244
63c3a66f
JP		 16245 if (tg3_flag(tp, 5750_PLUS)) {
16246 tg3_flag_set(tp, SUPPORT_MSI);
4153577a
JP		 16247 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16248 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16249 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16250 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
7544b097 16251 tp->pdev_peer == tp->pdev))
63c3a66f 16252 tg3_flag_clear(tp, SUPPORT_MSI);
7544b097 16253
63c3a66f 16254 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16255 tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16256 tg3_flag_set(tp, 1SHOT_MSI);
52c0fd83 16257 }
4f125f42 16258
63c3a66f
JP		 16259 if (tg3_flag(tp, 57765_PLUS)) {
16260 tg3_flag_set(tp, SUPPORT_MSIX);
507399f1
MC		 16261 tp->irq_max = TG3_IRQ_MAX_VECS;
16262 }
f6eb9b1f 16263 }
0e1406dd 16264
9102426a
MC		 16265 tp->txq_max = 1;
16266 tp->rxq_max = 1;
16267 if (tp->irq_max > 1) {
16268 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16269 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16270
4153577a
JP		 16271 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16272 tg3_asic_rev(tp) == ASIC_REV_5720)
9102426a
MC		 16273 tp->txq_max = tp->irq_max - 1;
16274 }
16275
b7abee6e 16276 if (tg3_flag(tp, 5755_PLUS) ||
4153577a 16277 tg3_asic_rev(tp) == ASIC_REV_5906)
63c3a66f 16278 tg3_flag_set(tp, SHORT_DMA_BUG);
f6eb9b1f 16279
4153577a 16280 if (tg3_asic_rev(tp) == ASIC_REV_5719)
a4cb428d 16281 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
e31aa987 16282
4153577a
JP		 16283 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16284 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16285 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16286 tg3_asic_rev(tp) == ASIC_REV_5762)
63c3a66f 16287 tg3_flag_set(tp, LRG_PROD_RING_CAP);
de9f5230 16288
63c3a66f 16289 if (tg3_flag(tp, 57765_PLUS) &&
4153577a 16290 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
63c3a66f 16291 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
b703df6f 16292
63c3a66f
JP		 16293 if (!tg3_flag(tp, 5705_PLUS) ||
16294 tg3_flag(tp, 5780_CLASS) ||
16295 tg3_flag(tp, USE_JUMBO_BDFLAG))
16296 tg3_flag_set(tp, JUMBO_CAPABLE);
0f893dc6 16297
52f4490c
MC		 16298 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16299 &pci_state_reg);
16300
708ebb3a 16301 if (pci_is_pcie(tp->pdev)) {
5e7dfd0f
MC		 16302 u16 lnkctl;
16303
63c3a66f 16304 tg3_flag_set(tp, PCI_EXPRESS);
5f5c51e3 16305
0f49bfbd 16306 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
5e7dfd0f 16307 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
4153577a 16308 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
63c3a66f 16309 tg3_flag_clear(tp, HW_TSO_2);
dabc5c67 16310 tg3_flag_clear(tp, TSO_CAPABLE);
7196cd6c 16311 }
4153577a
JP		 16312 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16313 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16314 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16315 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
63c3a66f 16316 tg3_flag_set(tp, CLKREQ_BUG);
4153577a 16317 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
63c3a66f 16318 tg3_flag_set(tp, L1PLLPD_EN);
c7835a77 16319 }
4153577a 16320 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
708ebb3a
JM		 16321 /* BCM5785 devices are effectively PCIe devices, and should
16322 * follow PCIe codepaths, but do not have a PCIe capabilities
16323 * section.
93a700a9 16324 */
63c3a66f
JP		 16325 tg3_flag_set(tp, PCI_EXPRESS);
16326 } else if (!tg3_flag(tp, 5705_PLUS) ||
16327 tg3_flag(tp, 5780_CLASS)) {
52f4490c
MC		 16328 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16329 if (!tp->pcix_cap) {
2445e461
MC		 16330 dev_err(&tp->pdev->dev,
16331 "Cannot find PCI-X capability, aborting\n");
52f4490c
MC		 16332 return -EIO;
16333 }
16334
16335 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
63c3a66f 16336 tg3_flag_set(tp, PCIX_MODE);
52f4490c 16337 }
1da177e4 16338
399de50b
MC		 16339 /* If we have an AMD 762 or VIA K8T800 chipset, write
16340 * reordering to the mailbox registers done by the host
16341 * controller can cause major troubles. We read back from
16342 * every mailbox register write to force the writes to be
16343 * posted to the chip in order.
16344 */
4143470c 16345 if (pci_dev_present(tg3_write_reorder_chipsets) &&
63c3a66f
JP		 16346 !tg3_flag(tp, PCI_EXPRESS))
16347 tg3_flag_set(tp, MBOX_WRITE_REORDER);
399de50b 16348
69fc4053
MC		 16349 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16350 &tp->pci_cacheline_sz);
16351 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16352 &tp->pci_lat_timer);
4153577a 16353 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
1da177e4
LT		 16354 tp->pci_lat_timer < 64) {
16355 tp->pci_lat_timer = 64;
69fc4053
MC		 16356 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16357 tp->pci_lat_timer);
1da177e4
LT		 16358 }
16359
16821285
MC		 16360 /* Important! -- It is critical that the PCI-X hw workaround
16361 * situation is decided before the first MMIO register access.
16362 */
4153577a 16363 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
52f4490c
MC		 16364 /* 5700 BX chips need to have their TX producer index
16365 * mailboxes written twice to workaround a bug.
16366 */
63c3a66f 16367 tg3_flag_set(tp, TXD_MBOX_HWBUG);
1da177e4 16368
52f4490c 16369 /* If we are in PCI-X mode, enable register write workaround.
1da177e4
LT		 16370 *
16371 * The workaround is to use indirect register accesses
16372 * for all chip writes not to mailbox registers.
16373 */
63c3a66f 16374 if (tg3_flag(tp, PCIX_MODE)) {
1da177e4 16375 u32 pm_reg;
1da177e4 16376
63c3a66f 16377 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16378
16379 /* The chip can have it's power management PCI config
16380 * space registers clobbered due to this bug.
16381 * So explicitly force the chip into D0 here.
16382 */
9974a356 16383 pci_read_config_dword(tp->pdev,
0319f30e 16384 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16385 &pm_reg);
16386 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16387 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9974a356 16388 pci_write_config_dword(tp->pdev,
0319f30e 16389 tp->pdev->pm_cap + PCI_PM_CTRL,
1da177e4
LT		 16390 pm_reg);
16391
16392 /* Also, force SERR#/PERR# in PCI command. */
16393 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16394 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16395 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16396 }
16397 }
16398
1da177e4 16399 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
63c3a66f 16400 tg3_flag_set(tp, PCI_HIGH_SPEED);
1da177e4 16401 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
63c3a66f 16402 tg3_flag_set(tp, PCI_32BIT);
1da177e4
LT		 16403
16404 /* Chip-specific fixup from Broadcom driver */
4153577a 16405 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
1da177e4
LT		 16406 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16407 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16408 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16409 }
16410
1ee582d8 16411 /* Default fast path register access methods */
20094930 16412 tp->read32 = tg3_read32;
1ee582d8 16413 tp->write32 = tg3_write32;
09ee929c 16414 tp->read32_mbox = tg3_read32;
20094930 16415 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 16416 tp->write32_tx_mbox = tg3_write32;
16417 tp->write32_rx_mbox = tg3_write32;
16418
16419 /* Various workaround register access methods */
63c3a66f 16420 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
1ee582d8 16421 tp->write32 = tg3_write_indirect_reg32;
4153577a 16422 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
63c3a66f 16423 (tg3_flag(tp, PCI_EXPRESS) &&
4153577a 16424 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
98efd8a6
MC		 16425 /*
16426 * Back to back register writes can cause problems on these
16427 * chips, the workaround is to read back all reg writes
16428 * except those to mailbox regs.
16429 *
16430 * See tg3_write_indirect_reg32().
16431 */
1ee582d8 16432 tp->write32 = tg3_write_flush_reg32;
98efd8a6
MC		 16433 }
16434
63c3a66f 16435 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
1ee582d8 16436 tp->write32_tx_mbox = tg3_write32_tx_mbox;
63c3a66f 16437 if (tg3_flag(tp, MBOX_WRITE_REORDER))
1ee582d8
MC		 16438 tp->write32_rx_mbox = tg3_write_flush_reg32;
16439 }
20094930 16440
63c3a66f 16441 if (tg3_flag(tp, ICH_WORKAROUND)) {
6892914f
MC		 16442 tp->read32 = tg3_read_indirect_reg32;
16443 tp->write32 = tg3_write_indirect_reg32;
16444 tp->read32_mbox = tg3_read_indirect_mbox;
16445 tp->write32_mbox = tg3_write_indirect_mbox;
16446 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16447 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16448
16449 iounmap(tp->regs);
22abe310 16450 tp->regs = NULL;
6892914f
MC		 16451
16452 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16453 pci_cmd &= ~PCI_COMMAND_MEMORY;
16454 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16455 }
4153577a 16456 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 16457 tp->read32_mbox = tg3_read32_mbox_5906;
16458 tp->write32_mbox = tg3_write32_mbox_5906;
16459 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16460 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16461 }
6892914f 16462
bbadf503 16463 if (tp->write32 == tg3_write_indirect_reg32 ||
63c3a66f 16464 (tg3_flag(tp, PCIX_MODE) &&
4153577a
JP		 16465 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16466 tg3_asic_rev(tp) == ASIC_REV_5701)))
63c3a66f 16467 tg3_flag_set(tp, SRAM_USE_CONFIG);
bbadf503 16468
16821285
MC		 16469 /* The memory arbiter has to be enabled in order for SRAM accesses
16470 * to succeed. Normally on powerup the tg3 chip firmware will make
16471 * sure it is enabled, but other entities such as system netboot
16472 * code might disable it.
16473 */
16474 val = tr32(MEMARB_MODE);
16475 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16476
9dc5e342 16477 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
4153577a 16478 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
9dc5e342
MC		 16479 tg3_flag(tp, 5780_CLASS)) {
16480 if (tg3_flag(tp, PCIX_MODE)) {
16481 pci_read_config_dword(tp->pdev,
16482 tp->pcix_cap + PCI_X_STATUS,
16483 &val);
16484 tp->pci_fn = val & 0x7;
16485 }
4153577a
JP		 16486 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16487 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16488 tg3_asic_rev(tp) == ASIC_REV_5720) {
9dc5e342 16489 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
857001f0
MC		 16490 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16491 val = tr32(TG3_CPMU_STATUS);
16492
4153577a 16493 if (tg3_asic_rev(tp) == ASIC_REV_5717)
857001f0
MC		 16494 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16495 else
9dc5e342
MC		 16496 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16497 TG3_CPMU_STATUS_FSHFT_5719;
69f11c99
MC		 16498 }
16499
7e6c63f0
HM		 16500 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16501 tp->write32_tx_mbox = tg3_write_flush_reg32;
16502 tp->write32_rx_mbox = tg3_write_flush_reg32;
16503 }
16504
7d0c41ef 16505 /* Get eeprom hw config before calling tg3_set_power_state().
63c3a66f 16506 * In particular, the TG3_FLAG_IS_NIC flag must be
7d0c41ef
MC		 16507 * determined before calling tg3_set_power_state() so that
16508 * we know whether or not to switch out of Vaux power.
16509 * When the flag is set, it means that GPIO1 is used for eeprom
16510 * write protect and also implies that it is a LOM where GPIOs
16511 * are not used to switch power.
6aa20a22 16512 */
7d0c41ef
MC		 16513 tg3_get_eeprom_hw_cfg(tp);
16514
1caf13eb 16515 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
cf9ecf4b
MC		 16516 tg3_flag_clear(tp, TSO_CAPABLE);
16517 tg3_flag_clear(tp, TSO_BUG);
16518 tp->fw_needed = NULL;
16519 }
16520
63c3a66f 16521 if (tg3_flag(tp, ENABLE_APE)) {
0d3031d9
MC		 16522 /* Allow reads and writes to the
16523 * APE register and memory space.
16524 */
16525 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
f92d9dc1
MC		 16526 PCISTATE_ALLOW_APE_SHMEM_WR |
16527 PCISTATE_ALLOW_APE_PSPACE_WR;
0d3031d9
MC		 16528 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16529 pci_state_reg);
c9cab24e
MC		 16530
16531 tg3_ape_lock_init(tp);
0d3031d9
MC		 16532 }
16533
16821285
MC		 16534 /* Set up tp->grc_local_ctrl before calling
16535 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16536 * will bring 5700's external PHY out of reset.
314fba34
MC		 16537 * It is also used as eeprom write protect on LOMs.
16538 */
16539 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
4153577a 16540 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
63c3a66f 16541 tg3_flag(tp, EEPROM_WRITE_PROT))
314fba34
MC		 16542 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16543 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 16544 /* Unused GPIO3 must be driven as output on 5752 because there
16545 * are no pull-up resistors on unused GPIO pins.
16546 */
4153577a 16547 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
3e7d83bc 16548 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 16549
4153577a
JP		 16550 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16551 tg3_asic_rev(tp) == ASIC_REV_57780 ||
55086ad9 16552 tg3_flag(tp, 57765_CLASS))
af36e6b6
MC		 16553 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16554
8d519ab2
MC		 16555 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16556 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
5f0c4a3c
MC		 16557 /* Turn off the debug UART. */
16558 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
63c3a66f 16559 if (tg3_flag(tp, IS_NIC))
5f0c4a3c
MC		 16560 /* Keep VMain power. */
16561 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16562 GRC_LCLCTRL_GPIO_OUTPUT0;
16563 }
16564
4153577a 16565 if (tg3_asic_rev(tp) == ASIC_REV_5762)
c86a8560
MC		 16566 tp->grc_local_ctrl |=
16567 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16568
16821285
MC		 16569 /* Switch out of Vaux if it is a NIC */
16570 tg3_pwrsrc_switch_to_vmain(tp);
1da177e4 16571
1da177e4
LT		 16572 /* Derive initial jumbo mode from MTU assigned in
16573 * ether_setup() via the alloc_etherdev() call
16574 */
63c3a66f
JP		 16575 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16576 tg3_flag_set(tp, JUMBO_RING_ENABLE);
1da177e4
LT		 16577
16578 /* Determine WakeOnLan speed to use. */
4153577a
JP		 16579 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16580 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16581 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16582 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
63c3a66f 16583 tg3_flag_clear(tp, WOL_SPEED_100MB);
1da177e4 16584 } else {
63c3a66f 16585 tg3_flag_set(tp, WOL_SPEED_100MB);
1da177e4
LT		 16586 }
16587
4153577a 16588 if (tg3_asic_rev(tp) == ASIC_REV_5906)
f07e9af3 16589 tp->phy_flags |= TG3_PHYFLG_IS_FET;
7f97a4bd 16590
1da177e4 16591 /* A few boards don't want Ethernet@WireSpeed phy feature */
4153577a
JP		 16592 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16593 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16594 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16595 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
f07e9af3
MC		 16596 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16597 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16598 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
1da177e4 16599
4153577a
JP		 16600 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16601 tg3_chip_rev(tp) == CHIPREV_5704_AX)
f07e9af3 16602 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
4153577a 16603 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
f07e9af3 16604 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
1da177e4 16605
63c3a66f 16606 if (tg3_flag(tp, 5705_PLUS) &&
f07e9af3 16607 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
4153577a
JP		 16608 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16609 tg3_asic_rev(tp) != ASIC_REV_57780 &&
63c3a66f 16610 !tg3_flag(tp, 57765_PLUS)) {
4153577a
JP		 16611 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16612 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16613 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16614 tg3_asic_rev(tp) == ASIC_REV_5761) {
d4011ada
MC		 16615 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16616 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
f07e9af3 16617 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
c1d2a196 16618 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
f07e9af3 16619 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
321d32a0 16620 } else
f07e9af3 16621 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
c424cb24 16622 }
1da177e4 16623
4153577a
JP		 16624 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16625 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
b2a5c19c
MC		 16626 tp->phy_otp = tg3_read_otp_phycfg(tp);
16627 if (tp->phy_otp == 0)
16628 tp->phy_otp = TG3_OTP_DEFAULT;
16629 }
16630
63c3a66f 16631 if (tg3_flag(tp, CPMU_PRESENT))
8ef21428
MC		 16632 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16633 else
16634 tp->mi_mode = MAC_MI_MODE_BASE;
16635
1da177e4 16636 tp->coalesce_mode = 0;
4153577a
JP		 16637 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16638 tg3_chip_rev(tp) != CHIPREV_5700_BX)
1da177e4
LT		 16639 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16640
4d958473 16641 /* Set these bits to enable statistics workaround. */
4153577a 16642 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
94962f7f 16643 tg3_asic_rev(tp) == ASIC_REV_5762 ||
4153577a
JP		 16644 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16645 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
4d958473
MC		 16646 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16647 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16648 }
16649
4153577a
JP		 16650 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16651 tg3_asic_rev(tp) == ASIC_REV_57780)
63c3a66f 16652 tg3_flag_set(tp, USE_PHYLIB);
57e6983c 16653
158d7abd
MC		 16654 err = tg3_mdio_init(tp);
16655 if (err)
16656 return err;
1da177e4
LT		 16657
16658 /* Initialize data/descriptor byte/word swapping. */
16659 val = tr32(GRC_MODE);
4153577a
JP		 16660 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16661 tg3_asic_rev(tp) == ASIC_REV_5762)
f2096f94
MC		 16662 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16663 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16664 GRC_MODE_B2HRX_ENABLE |
16665 GRC_MODE_HTX2B_ENABLE |
16666 GRC_MODE_HOST_STACKUP);
16667 else
16668 val &= GRC_MODE_HOST_STACKUP;
16669
1da177e4
LT		 16670 tw32(GRC_MODE, val | tp->grc_mode);
16671
16672 tg3_switch_clocks(tp);
16673
16674 /* Clear this out for sanity. */
16675 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16676
388d3335
NG		 16677 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16678 tw32(TG3PCI_REG_BASE_ADDR, 0);
16679
1da177e4
LT		 16680 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16681 &pci_state_reg);
16682 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
63c3a66f 16683 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
4153577a
JP		 16684 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16685 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16686 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16687 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
1da177e4
LT		 16688 void __iomem *sram_base;
16689
16690 /* Write some dummy words into the SRAM status block
16691 * area, see if it reads back correctly. If the return
16692 * value is bad, force enable the PCIX workaround.
16693 */
16694 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16695
16696 writel(0x00000000, sram_base);
16697 writel(0x00000000, sram_base + 4);
16698 writel(0xffffffff, sram_base + 4);
16699 if (readl(sram_base) != 0x00000000)
63c3a66f 16700 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
1da177e4
LT		 16701 }
16702 }
16703
16704 udelay(50);
16705 tg3_nvram_init(tp);
16706
c4dab506
NS		 16707 /* If the device has an NVRAM, no need to load patch firmware */
16708 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16709 !tg3_flag(tp, NO_NVRAM))
16710 tp->fw_needed = NULL;
16711
1da177e4
LT		 16712 grc_misc_cfg = tr32(GRC_MISC_CFG);
16713 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16714
4153577a 16715 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
1da177e4
LT		 16716 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16717 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
63c3a66f 16718 tg3_flag_set(tp, IS_5788);
1da177e4 16719
63c3a66f 16720 if (!tg3_flag(tp, IS_5788) &&
4153577a 16721 tg3_asic_rev(tp) != ASIC_REV_5700)
63c3a66f
JP		 16722 tg3_flag_set(tp, TAGGED_STATUS);
16723 if (tg3_flag(tp, TAGGED_STATUS)) {
fac9b83e
DM		 16724 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16725 HOSTCC_MODE_CLRTICK_TXBD);
16726
16727 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16728 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16729 tp->misc_host_ctrl);
16730 }
16731
3bda1258 16732 /* Preserve the APE MAC_MODE bits */
63c3a66f 16733 if (tg3_flag(tp, ENABLE_APE))
d2394e6b 16734 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
3bda1258 16735 else
6e01b20b 16736 tp->mac_mode = 0;
3bda1258 16737
3d567e0e 16738 if (tg3_10_100_only_device(tp, ent))
f07e9af3 16739 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
1da177e4
LT		 16740
16741 err = tg3_phy_probe(tp);
16742 if (err) {
2445e461 16743 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
1da177e4 16744 /* ... but do not return immediately ... */
b02fd9e3 16745 tg3_mdio_fini(tp);
1da177e4
LT		 16746 }
16747
184b8904 16748 tg3_read_vpd(tp);
c4e6575c 16749 tg3_read_fw_ver(tp);
1da177e4 16750
f07e9af3
MC		 16751 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16752 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16753 } else {
4153577a 16754 if (tg3_asic_rev(tp) == ASIC_REV_5700)
f07e9af3 16755 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4 16756 else
f07e9af3 16757 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
1da177e4
LT		 16758 }
16759
16760 /* 5700 {AX,BX} chips have a broken status block link
16761 * change bit implementation, so we must use the
16762 * status register in those cases.
16763 */
4153577a 16764 if (tg3_asic_rev(tp) == ASIC_REV_5700)
63c3a66f 16765 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4 16766 else
63c3a66f 16767 tg3_flag_clear(tp, USE_LINKCHG_REG);
1da177e4
LT		 16768
16769 /* The led_ctrl is set during tg3_phy_probe, here we might
16770 * have to force the link status polling mechanism based
16771 * upon subsystem IDs.
16772 */
16773 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
4153577a 16774 tg3_asic_rev(tp) == ASIC_REV_5701 &&
f07e9af3
MC		 16775 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16776 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
63c3a66f 16777 tg3_flag_set(tp, USE_LINKCHG_REG);
1da177e4
LT		 16778 }
16779
16780 /* For all SERDES we poll the MAC status register. */
f07e9af3 16781 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
63c3a66f 16782 tg3_flag_set(tp, POLL_SERDES);
1da177e4 16783 else
63c3a66f 16784 tg3_flag_clear(tp, POLL_SERDES);
1da177e4 16785
1743b83c
NS		 16786 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16787 tg3_flag_set(tp, POLL_CPMU_LINK);
16788
9205fd9c 16789 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
d2757fc4 16790 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
4153577a 16791 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
63c3a66f 16792 tg3_flag(tp, PCIX_MODE)) {
9205fd9c 16793 tp->rx_offset = NET_SKB_PAD;
d2757fc4 16794#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
9dc7a113 16795 tp->rx_copy_thresh = ~(u16)0;
d2757fc4
MC		 16796#endif
16797 }
1da177e4 16798
2c49a44d
MC		 16799 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16800 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
7cb32cf2
MC		 16801 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16802
2c49a44d 16803 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
f92905de
MC		 16804
16805 /* Increment the rx prod index on the rx std ring by at most
16806 * 8 for these chips to workaround hw errata.
16807 */
4153577a
JP		 16808 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16809 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16810 tg3_asic_rev(tp) == ASIC_REV_5755)
f92905de
MC		 16811 tp->rx_std_max_post = 8;
16812
63c3a66f 16813 if (tg3_flag(tp, ASPM_WORKAROUND))
8ed5d97e
MC		 16814 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16815 PCIE_PWR_MGMT_L1_THRESH_MSK;
16816
1da177e4
LT		 16817 return err;
16818}
16819
49b6e95f 16820#ifdef CONFIG_SPARC
229b1ad1 16821static int tg3_get_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16822{
16823 struct net_device *dev = tp->dev;
16824 struct pci_dev *pdev = tp->pdev;
49b6e95f 16825 struct device_node *dp = pci_device_to_OF_node(pdev);
374d4cac 16826 const unsigned char *addr;
49b6e95f
DM		 16827 int len;
16828
16829 addr = of_get_property(dp, "local-mac-address", &len);
d458cdf7
JP		 16830 if (addr && len == ETH_ALEN) {
16831 memcpy(dev->dev_addr, addr, ETH_ALEN);
49b6e95f 16832 return 0;
1da177e4
LT		 16833 }
16834 return -ENODEV;
16835}
16836
229b1ad1 16837static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
1da177e4
LT		 16838{
16839 struct net_device *dev = tp->dev;
16840
d458cdf7 16841 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
1da177e4
LT		 16842 return 0;
16843}
16844#endif
16845
229b1ad1 16846static int tg3_get_device_address(struct tg3 *tp)
1da177e4
LT		 16847{
16848 struct net_device *dev = tp->dev;
16849 u32 hi, lo, mac_offset;
008652b3 16850 int addr_ok = 0;
7e6c63f0 16851 int err;
1da177e4 16852
49b6e95f 16853#ifdef CONFIG_SPARC
1da177e4
LT		 16854 if (!tg3_get_macaddr_sparc(tp))
16855 return 0;
16856#endif
16857
7e6c63f0
HM		 16858 if (tg3_flag(tp, IS_SSB_CORE)) {
16859 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16860 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16861 return 0;
16862 }
16863
1da177e4 16864 mac_offset = 0x7c;
4153577a 16865 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
63c3a66f 16866 tg3_flag(tp, 5780_CLASS)) {
1da177e4
LT		 16867 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16868 mac_offset = 0xcc;
16869 if (tg3_nvram_lock(tp))
16870 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16871 else
16872 tg3_nvram_unlock(tp);
63c3a66f 16873 } else if (tg3_flag(tp, 5717_PLUS)) {
69f11c99 16874 if (tp->pci_fn & 1)
a1b950d5 16875 mac_offset = 0xcc;
69f11c99 16876 if (tp->pci_fn > 1)
a50d0796 16877 mac_offset += 0x18c;
4153577a 16878 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
b5d3772c 16879 mac_offset = 0x10;
1da177e4
LT		 16880
16881 /* First try to get it from MAC address mailbox. */
16882 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16883 if ((hi >> 16) == 0x484b) {
16884 dev->dev_addr[0] = (hi >> 8) & 0xff;
16885 dev->dev_addr[1] = (hi >> 0) & 0xff;
16886
16887 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16888 dev->dev_addr[2] = (lo >> 24) & 0xff;
16889 dev->dev_addr[3] = (lo >> 16) & 0xff;
16890 dev->dev_addr[4] = (lo >> 8) & 0xff;
16891 dev->dev_addr[5] = (lo >> 0) & 0xff;
1da177e4 16892
008652b3
MC		 16893 /* Some old bootcode may report a 0 MAC address in SRAM */
16894 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16895 }
16896 if (!addr_ok) {
16897 /* Next, try NVRAM. */
63c3a66f 16898 if (!tg3_flag(tp, NO_NVRAM) &&
df259d8c 16899 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
6d348f2c 16900 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
62cedd11
MC		 16901 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16902 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
008652b3
MC		 16903 }
16904 /* Finally just fetch it out of the MAC control regs. */
16905 else {
16906 hi = tr32(MAC_ADDR_0_HIGH);
16907 lo = tr32(MAC_ADDR_0_LOW);
16908
16909 dev->dev_addr[5] = lo & 0xff;
16910 dev->dev_addr[4] = (lo >> 8) & 0xff;
16911 dev->dev_addr[3] = (lo >> 16) & 0xff;
16912 dev->dev_addr[2] = (lo >> 24) & 0xff;
16913 dev->dev_addr[1] = hi & 0xff;
16914 dev->dev_addr[0] = (hi >> 8) & 0xff;
16915 }
1da177e4
LT		 16916 }
16917
16918 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
7582a335 16919#ifdef CONFIG_SPARC
1da177e4
LT		 16920 if (!tg3_get_default_macaddr_sparc(tp))
16921 return 0;
16922#endif
16923 return -EINVAL;
16924 }
16925 return 0;
16926}
16927
59e6b434
DM		 16928#define BOUNDARY_SINGLE_CACHELINE 1
16929#define BOUNDARY_MULTI_CACHELINE 2
16930
229b1ad1 16931static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
59e6b434
DM		 16932{
16933 int cacheline_size;
16934 u8 byte;
16935 int goal;
16936
16937 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16938 if (byte == 0)
16939 cacheline_size = 1024;
16940 else
16941 cacheline_size = (int) byte * 4;
16942
16943 /* On 5703 and later chips, the boundary bits have no
16944 * effect.
16945 */
4153577a
JP		 16946 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16947 tg3_asic_rev(tp) != ASIC_REV_5701 &&
63c3a66f 16948 !tg3_flag(tp, PCI_EXPRESS))
59e6b434
DM		 16949 goto out;
16950
16951#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16952 goal = BOUNDARY_MULTI_CACHELINE;
16953#else
16954#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16955 goal = BOUNDARY_SINGLE_CACHELINE;
16956#else
16957 goal = 0;
16958#endif
16959#endif
16960
63c3a66f 16961 if (tg3_flag(tp, 57765_PLUS)) {
cbf9ca6c
MC		 16962 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16963 goto out;
16964 }
16965
59e6b434
DM		 16966 if (!goal)
16967 goto out;
16968
16969 /* PCI controllers on most RISC systems tend to disconnect
16970 * when a device tries to burst across a cache-line boundary.
16971 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16972 *
16973 * Unfortunately, for PCI-E there are only limited
16974 * write-side controls for this, and thus for reads
16975 * we will still get the disconnects. We'll also waste
16976 * these PCI cycles for both read and write for chips
16977 * other than 5700 and 5701 which do not implement the
16978 * boundary bits.
16979 */
63c3a66f 16980 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 16981 switch (cacheline_size) {
16982 case 16:
16983 case 32:
16984 case 64:
16985 case 128:
16986 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16987 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16988 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16989 } else {
16990 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16991 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16992 }
16993 break;
16994
16995 case 256:
16996 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16997 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16998 break;
16999
17000 default:
17001 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17002 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17003 break;
855e1111 17004 }
63c3a66f 17005 } else if (tg3_flag(tp, PCI_EXPRESS)) {
59e6b434
DM		 17006 switch (cacheline_size) {
17007 case 16:
17008 case 32:
17009 case 64:
17010 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17011 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17012 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17013 break;
17014 }
17015 /* fallthrough */
17016 case 128:
17017 default:
17018 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17019 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17020 break;
855e1111 17021 }
59e6b434
DM		 17022 } else {
17023 switch (cacheline_size) {
17024 case 16:
17025 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17026 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17027 DMA_RWCTRL_WRITE_BNDRY_16);
17028 break;
17029 }
17030 /* fallthrough */
17031 case 32:
17032 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17033 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17034 DMA_RWCTRL_WRITE_BNDRY_32);
17035 break;
17036 }
17037 /* fallthrough */
17038 case 64:
17039 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17040 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17041 DMA_RWCTRL_WRITE_BNDRY_64);
17042 break;
17043 }
17044 /* fallthrough */
17045 case 128:
17046 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17047 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17048 DMA_RWCTRL_WRITE_BNDRY_128);
17049 break;
17050 }
17051 /* fallthrough */
17052 case 256:
17053 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17054 DMA_RWCTRL_WRITE_BNDRY_256);
17055 break;
17056 case 512:
17057 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17058 DMA_RWCTRL_WRITE_BNDRY_512);
17059 break;
17060 case 1024:
17061 default:
17062 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17063 DMA_RWCTRL_WRITE_BNDRY_1024);
17064 break;
855e1111 17065 }
59e6b434
DM		 17066 }
17067
17068out:
17069 return val;
17070}
17071
229b1ad1 17072static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
953c96e0 17073 int size, bool to_device)
1da177e4
LT		 17074{
17075 struct tg3_internal_buffer_desc test_desc;
17076 u32 sram_dma_descs;
17077 int i, ret;
17078
17079 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17080
17081 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17082 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17083 tw32(RDMAC_STATUS, 0);
17084 tw32(WDMAC_STATUS, 0);
17085
17086 tw32(BUFMGR_MODE, 0);
17087 tw32(FTQ_RESET, 0);
17088
17089 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17090 test_desc.addr_lo = buf_dma & 0xffffffff;
17091 test_desc.nic_mbuf = 0x00002100;
17092 test_desc.len = size;
17093
17094 /*
17095 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17096 * the *second* time the tg3 driver was getting loaded after an
17097 * initial scan.
17098 *
17099 * Broadcom tells me:
17100 * ...the DMA engine is connected to the GRC block and a DMA
17101 * reset may affect the GRC block in some unpredictable way...
17102 * The behavior of resets to individual blocks has not been tested.
17103 *
17104 * Broadcom noted the GRC reset will also reset all sub-components.
17105 */
17106 if (to_device) {
17107 test_desc.cqid_sqid = (13 << 8) | 2;
17108
17109 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17110 udelay(40);
17111 } else {
17112 test_desc.cqid_sqid = (16 << 8) | 7;
17113
17114 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17115 udelay(40);
17116 }
17117 test_desc.flags = 0x00000005;
17118
17119 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17120 u32 val;
17121
17122 val = *(((u32 *)&test_desc) + i);
17123 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17124 sram_dma_descs + (i * sizeof(u32)));
17125 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17126 }
17127 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17128
859a5887 17129 if (to_device)
1da177e4 17130 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
859a5887 17131 else
1da177e4 17132 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
1da177e4
LT		 17133
17134 ret = -ENODEV;
17135 for (i = 0; i < 40; i++) {
17136 u32 val;
17137
17138 if (to_device)
17139 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17140 else
17141 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17142 if ((val & 0xffff) == sram_dma_descs) {
17143 ret = 0;
17144 break;
17145 }
17146
17147 udelay(100);
17148 }
17149
17150 return ret;
17151}
17152
ded7340d 17153#define TEST_BUFFER_SIZE 0x2000
1da177e4 17154
4143470c 17155static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
895950c2
JP		 17156 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17157 { },
17158};
17159
229b1ad1 17160static int tg3_test_dma(struct tg3 *tp)
1da177e4
LT		 17161{
17162 dma_addr_t buf_dma;
59e6b434 17163 u32 *buf, saved_dma_rwctrl;
cbf9ca6c 17164 int ret = 0;
1da177e4 17165
4bae65c8
MC		 17166 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17167 &buf_dma, GFP_KERNEL);
1da177e4
LT		 17168 if (!buf) {
17169 ret = -ENOMEM;
17170 goto out_nofree;
17171 }
17172
17173 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17174 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17175
59e6b434 17176 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4 17177
63c3a66f 17178 if (tg3_flag(tp, 57765_PLUS))
cbf9ca6c
MC		 17179 goto out;
17180
63c3a66f 17181 if (tg3_flag(tp, PCI_EXPRESS)) {
1da177e4
LT		 17182 /* DMA read watermark not used on PCIE */
17183 tp->dma_rwctrl |= 0x00180000;
63c3a66f 17184 } else if (!tg3_flag(tp, PCIX_MODE)) {
4153577a
JP		 17185 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17186 tg3_asic_rev(tp) == ASIC_REV_5750)
1da177e4
LT		 17187 tp->dma_rwctrl |= 0x003f0000;
17188 else
17189 tp->dma_rwctrl |= 0x003f000f;
17190 } else {
4153577a
JP		 17191 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17192 tg3_asic_rev(tp) == ASIC_REV_5704) {
1da177e4 17193 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
49afdeb6 17194 u32 read_water = 0x7;
1da177e4 17195
4a29cc2e
MC		 17196 /* If the 5704 is behind the EPB bridge, we can
17197 * do the less restrictive ONE_DMA workaround for
17198 * better performance.
17199 */
63c3a66f 17200 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
4153577a 17201 tg3_asic_rev(tp) == ASIC_REV_5704)
4a29cc2e
MC		 17202 tp->dma_rwctrl |= 0x8000;
17203 else if (ccval == 0x6 || ccval == 0x7)
1da177e4
LT		 17204 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17205
4153577a 17206 if (tg3_asic_rev(tp) == ASIC_REV_5703)
49afdeb6 17207 read_water = 4;
59e6b434 17208 /* Set bit 23 to enable PCIX hw bug fix */
49afdeb6
MC		 17209 tp->dma_rwctrl |=
17210 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17211 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17212 (1 << 23);
4153577a 17213 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
4cf78e4f
MC		 17214 /* 5780 always in PCIX mode */
17215 tp->dma_rwctrl |= 0x00144000;
4153577a 17216 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
a4e2b347
MC		 17217 /* 5714 always in PCIX mode */
17218 tp->dma_rwctrl |= 0x00148000;
1da177e4
LT		 17219 } else {
17220 tp->dma_rwctrl |= 0x001b000f;
17221 }
17222 }
7e6c63f0
HM		 17223 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17224 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
1da177e4 17225
4153577a
JP		 17226 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17227 tg3_asic_rev(tp) == ASIC_REV_5704)
1da177e4
LT		 17228 tp->dma_rwctrl &= 0xfffffff0;
17229
4153577a
JP		 17230 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17231 tg3_asic_rev(tp) == ASIC_REV_5701) {
1da177e4
LT		 17232 /* Remove this if it causes problems for some boards. */
17233 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17234
17235 /* On 5700/5701 chips, we need to set this bit.
17236 * Otherwise the chip will issue cacheline transactions
17237 * to streamable DMA memory with not all the byte
17238 * enables turned on. This is an error on several
17239 * RISC PCI controllers, in particular sparc64.
17240 *
17241 * On 5703/5704 chips, this bit has been reassigned
17242 * a different meaning. In particular, it is used
17243 * on those chips to enable a PCI-X workaround.
17244 */
17245 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17246 }
17247
17248 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17249
1da177e4 17250
4153577a
JP		 17251 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17252 tg3_asic_rev(tp) != ASIC_REV_5701)
1da177e4
LT		 17253 goto out;
17254
59e6b434
DM		 17255 /* It is best to perform DMA test with maximum write burst size
17256 * to expose the 5700/5701 write DMA bug.
17257 */
17258 saved_dma_rwctrl = tp->dma_rwctrl;
17259 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17260 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17261
1da177e4
LT		 17262 while (1) {
17263 u32 *p = buf, i;
17264
17265 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17266 p[i] = i;
17267
17268 /* Send the buffer to the chip. */
953c96e0 17269 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
1da177e4 17270 if (ret) {
2445e461
MC		 17271 dev_err(&tp->pdev->dev,
17272 "%s: Buffer write failed. err = %d\n",
17273 __func__, ret);
1da177e4
LT		 17274 break;
17275 }
17276
1da177e4 17277 /* Now read it back. */
953c96e0 17278 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
1da177e4 17279 if (ret) {
5129c3a3
MC		 17280 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17281 "err = %d\n", __func__, ret);
1da177e4
LT		 17282 break;
17283 }
17284
17285 /* Verify it. */
17286 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17287 if (p[i] == i)
17288 continue;
17289
59e6b434
DM		 17290 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17291 DMA_RWCTRL_WRITE_BNDRY_16) {
17292 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 17293 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17294 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17295 break;
17296 } else {
2445e461
MC		 17297 dev_err(&tp->pdev->dev,
17298 "%s: Buffer corrupted on read back! "
17299 "(%d != %d)\n", __func__, p[i], i);
1da177e4
LT		 17300 ret = -ENODEV;
17301 goto out;
17302 }
17303 }
17304
17305 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17306 /* Success. */
17307 ret = 0;
17308 break;
17309 }
17310 }
59e6b434
DM		 17311 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17312 DMA_RWCTRL_WRITE_BNDRY_16) {
17313 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 17314 * now look for chipsets that are known to expose the
17315 * DMA bug without failing the test.
59e6b434 17316 */
4143470c 17317 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
6d1cfbab
MC		 17318 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17319 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
859a5887 17320 } else {
6d1cfbab
MC		 17321 /* Safe to use the calculated DMA boundary. */
17322 tp->dma_rwctrl = saved_dma_rwctrl;
859a5887 17323 }
6d1cfbab 17324
59e6b434
DM		 17325 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17326 }
1da177e4
LT		 17327
17328out:
4bae65c8 17329 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
1da177e4
LT		 17330out_nofree:
17331 return ret;
17332}
17333
229b1ad1 17334static void tg3_init_bufmgr_config(struct tg3 *tp)
1da177e4 17335{
63c3a66f 17336 if (tg3_flag(tp, 57765_PLUS)) {
666bc831
MC		 17337 tp->bufmgr_config.mbuf_read_dma_low_water =
17338 DEFAULT_MB_RDMA_LOW_WATER_5705;
17339 tp->bufmgr_config.mbuf_mac_rx_low_water =
17340 DEFAULT_MB_MACRX_LOW_WATER_57765;
17341 tp->bufmgr_config.mbuf_high_water =
17342 DEFAULT_MB_HIGH_WATER_57765;
17343
17344 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17345 DEFAULT_MB_RDMA_LOW_WATER_5705;
17346 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17347 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17348 tp->bufmgr_config.mbuf_high_water_jumbo =
17349 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
63c3a66f 17350 } else if (tg3_flag(tp, 5705_PLUS)) {
fdfec172
MC		 17351 tp->bufmgr_config.mbuf_read_dma_low_water =
17352 DEFAULT_MB_RDMA_LOW_WATER_5705;
17353 tp->bufmgr_config.mbuf_mac_rx_low_water =
17354 DEFAULT_MB_MACRX_LOW_WATER_5705;
17355 tp->bufmgr_config.mbuf_high_water =
17356 DEFAULT_MB_HIGH_WATER_5705;
4153577a 17357 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
b5d3772c
MC		 17358 tp->bufmgr_config.mbuf_mac_rx_low_water =
17359 DEFAULT_MB_MACRX_LOW_WATER_5906;
17360 tp->bufmgr_config.mbuf_high_water =
17361 DEFAULT_MB_HIGH_WATER_5906;
17362 }
fdfec172
MC		 17363
17364 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17365 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17366 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17367 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17368 tp->bufmgr_config.mbuf_high_water_jumbo =
17369 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17370 } else {
17371 tp->bufmgr_config.mbuf_read_dma_low_water =
17372 DEFAULT_MB_RDMA_LOW_WATER;
17373 tp->bufmgr_config.mbuf_mac_rx_low_water =
17374 DEFAULT_MB_MACRX_LOW_WATER;
17375 tp->bufmgr_config.mbuf_high_water =
17376 DEFAULT_MB_HIGH_WATER;
17377
17378 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17379 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17380 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17381 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17382 tp->bufmgr_config.mbuf_high_water_jumbo =
17383 DEFAULT_MB_HIGH_WATER_JUMBO;
17384 }
1da177e4
LT		 17385
17386 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17387 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17388}
17389
229b1ad1 17390static char *tg3_phy_string(struct tg3 *tp)
1da177e4 17391{
79eb6904
MC		 17392 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17393 case TG3_PHY_ID_BCM5400: return "5400";
17394 case TG3_PHY_ID_BCM5401: return "5401";
17395 case TG3_PHY_ID_BCM5411: return "5411";
17396 case TG3_PHY_ID_BCM5701: return "5701";
17397 case TG3_PHY_ID_BCM5703: return "5703";
17398 case TG3_PHY_ID_BCM5704: return "5704";
17399 case TG3_PHY_ID_BCM5705: return "5705";
17400 case TG3_PHY_ID_BCM5750: return "5750";
17401 case TG3_PHY_ID_BCM5752: return "5752";
17402 case TG3_PHY_ID_BCM5714: return "5714";
17403 case TG3_PHY_ID_BCM5780: return "5780";
17404 case TG3_PHY_ID_BCM5755: return "5755";
17405 case TG3_PHY_ID_BCM5787: return "5787";
17406 case TG3_PHY_ID_BCM5784: return "5784";
17407 case TG3_PHY_ID_BCM5756: return "5722/5756";
17408 case TG3_PHY_ID_BCM5906: return "5906";
17409 case TG3_PHY_ID_BCM5761: return "5761";
17410 case TG3_PHY_ID_BCM5718C: return "5718C";
17411 case TG3_PHY_ID_BCM5718S: return "5718S";
17412 case TG3_PHY_ID_BCM57765: return "57765";
302b500b 17413 case TG3_PHY_ID_BCM5719C: return "5719C";
6418f2c1 17414 case TG3_PHY_ID_BCM5720C: return "5720C";
c65a17f4 17415 case TG3_PHY_ID_BCM5762: return "5762C";
79eb6904 17416 case TG3_PHY_ID_BCM8002: return "8002/serdes";
1da177e4
LT		 17417 case 0: return "serdes";
17418 default: return "unknown";
855e1111 17419 }
1da177e4
LT		 17420}
17421
229b1ad1 17422static char *tg3_bus_string(struct tg3 *tp, char *str)
f9804ddb 17423{
63c3a66f 17424 if (tg3_flag(tp, PCI_EXPRESS)) {
f9804ddb
MC		 17425 strcpy(str, "PCI Express");
17426 return str;
63c3a66f 17427 } else if (tg3_flag(tp, PCIX_MODE)) {
f9804ddb
MC		 17428 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17429
17430 strcpy(str, "PCIX:");
17431
17432 if ((clock_ctrl == 7) ||
17433 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17434 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17435 strcat(str, "133MHz");
17436 else if (clock_ctrl == 0)
17437 strcat(str, "33MHz");
17438 else if (clock_ctrl == 2)
17439 strcat(str, "50MHz");
17440 else if (clock_ctrl == 4)
17441 strcat(str, "66MHz");
17442 else if (clock_ctrl == 6)
17443 strcat(str, "100MHz");
f9804ddb
MC		 17444 } else {
17445 strcpy(str, "PCI:");
63c3a66f 17446 if (tg3_flag(tp, PCI_HIGH_SPEED))
f9804ddb
MC		 17447 strcat(str, "66MHz");
17448 else
17449 strcat(str, "33MHz");
17450 }
63c3a66f 17451 if (tg3_flag(tp, PCI_32BIT))
f9804ddb
MC		 17452 strcat(str, ":32-bit");
17453 else
17454 strcat(str, ":64-bit");
17455 return str;
17456}
17457
229b1ad1 17458static void tg3_init_coal(struct tg3 *tp)
15f9850d
DM		 17459{
17460 struct ethtool_coalesce *ec = &tp->coal;
17461
17462 memset(ec, 0, sizeof(*ec));
17463 ec->cmd = ETHTOOL_GCOALESCE;
17464 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17465 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17466 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17467 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17468 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17469 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17470 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17471 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17472 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17473
17474 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17475 HOSTCC_MODE_CLRTICK_TXBD)) {
17476 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17477 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17478 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17479 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17480 }
d244c892 17481
63c3a66f 17482 if (tg3_flag(tp, 5705_PLUS)) {
d244c892
MC		 17483 ec->rx_coalesce_usecs_irq = 0;
17484 ec->tx_coalesce_usecs_irq = 0;
17485 ec->stats_block_coalesce_usecs = 0;
17486 }
15f9850d
DM		 17487}
17488
229b1ad1 17489static int tg3_init_one(struct pci_dev *pdev,
1da177e4
LT		 17490 const struct pci_device_id *ent)
17491{
1da177e4
LT		 17492 struct net_device *dev;
17493 struct tg3 *tp;
5865fc1b 17494 int i, err;
646c9edd 17495 u32 sndmbx, rcvmbx, intmbx;
f9804ddb 17496 char str[40];
72f2afb8 17497 u64 dma_mask, persist_dma_mask;
c8f44aff 17498 netdev_features_t features = 0;
1da177e4 17499
05dbe005 17500 printk_once(KERN_INFO "%s\n", version);
1da177e4
LT		 17501
17502 err = pci_enable_device(pdev);
17503 if (err) {
2445e461 17504 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 17505 return err;
17506 }
17507
1da177e4
LT		 17508 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17509 if (err) {
2445e461 17510 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 17511 goto err_out_disable_pdev;
17512 }
17513
17514 pci_set_master(pdev);
17515
fe5f5787 17516 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
1da177e4 17517 if (!dev) {
1da177e4 17518 err = -ENOMEM;
5865fc1b 17519 goto err_out_free_res;
1da177e4
LT		 17520 }
17521
1da177e4
LT		 17522 SET_NETDEV_DEV(dev, &pdev->dev);
17523
1da177e4
LT		 17524 tp = netdev_priv(dev);
17525 tp->pdev = pdev;
17526 tp->dev = dev;
1da177e4
LT		 17527 tp->rx_mode = TG3_DEF_RX_MODE;
17528 tp->tx_mode = TG3_DEF_TX_MODE;
9c13cb8b 17529 tp->irq_sync = 1;
8ef21428 17530
1da177e4
LT		 17531 if (tg3_debug > 0)
17532 tp->msg_enable = tg3_debug;
17533 else
17534 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17535
7e6c63f0
HM		 17536 if (pdev_is_ssb_gige_core(pdev)) {
17537 tg3_flag_set(tp, IS_SSB_CORE);
17538 if (ssb_gige_must_flush_posted_writes(pdev))
17539 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17540 if (ssb_gige_one_dma_at_once(pdev))
17541 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
ee002b64
HM		 17542 if (ssb_gige_have_roboswitch(pdev)) {
17543 tg3_flag_set(tp, USE_PHYLIB);
7e6c63f0 17544 tg3_flag_set(tp, ROBOSWITCH);
ee002b64 17545 }
7e6c63f0
HM		 17546 if (ssb_gige_is_rgmii(pdev))
17547 tg3_flag_set(tp, RGMII_MODE);
17548 }
17549
1da177e4
LT		 17550 /* The word/byte swap controls here control register access byte
17551 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17552 * setting below.
17553 */
17554 tp->misc_host_ctrl =
17555 MISC_HOST_CTRL_MASK_PCI_INT |
17556 MISC_HOST_CTRL_WORD_SWAP |
17557 MISC_HOST_CTRL_INDIR_ACCESS |
17558 MISC_HOST_CTRL_PCISTATE_RW;
17559
17560 /* The NONFRM (non-frame) byte/word swap controls take effect
17561 * on descriptor entries, anything which isn't packet data.
17562 *
17563 * The StrongARM chips on the board (one for tx, one for rx)
17564 * are running in big-endian mode.
17565 */
17566 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17567 GRC_MODE_WSWAP_NONFRM_DATA);
17568#ifdef __BIG_ENDIAN
17569 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17570#endif
17571 spin_lock_init(&tp->lock);
1da177e4 17572 spin_lock_init(&tp->indirect_lock);
c4028958 17573 INIT_WORK(&tp->reset_task, tg3_reset_task);
1da177e4 17574
d5fe488a 17575 tp->regs = pci_ioremap_bar(pdev, BAR_0);
ab0049b4 17576 if (!tp->regs) {
ab96b241 17577 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
1da177e4
LT		 17578 err = -ENOMEM;
17579 goto err_out_free_dev;
17580 }
17581
c9cab24e
MC		 17582 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17583 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17584 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17585 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17586 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
79d49695 17587 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
c9cab24e
MC		 17588 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17589 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
c65a17f4 17590 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
68273712
NS		 17591 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17592 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
c65a17f4
MC		 17593 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17594 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
68273712
NS		 17595 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17596 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
c9cab24e
MC		 17597 tg3_flag_set(tp, ENABLE_APE);
17598 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17599 if (!tp->aperegs) {
17600 dev_err(&pdev->dev,
17601 "Cannot map APE registers, aborting\n");
17602 err = -ENOMEM;
17603 goto err_out_iounmap;
17604 }
17605 }
17606
1da177e4
LT		 17607 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17608 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
1da177e4 17609
1da177e4 17610 dev->ethtool_ops = &tg3_ethtool_ops;
1da177e4 17611 dev->watchdog_timeo = TG3_TX_TIMEOUT;
2ffcc981 17612 dev->netdev_ops = &tg3_netdev_ops;
1da177e4 17613 dev->irq = pdev->irq;
1da177e4 17614
3d567e0e 17615 err = tg3_get_invariants(tp, ent);
1da177e4 17616 if (err) {
ab96b241
MC		 17617 dev_err(&pdev->dev,
17618 "Problem fetching invariants of chip, aborting\n");
c9cab24e 17619 goto err_out_apeunmap;
1da177e4
LT		 17620 }
17621
4a29cc2e
MC		 17622 /* The EPB bridge inside 5714, 5715, and 5780 and any
17623 * device behind the EPB cannot support DMA addresses > 40-bit.
72f2afb8
MC		 17624 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17625 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17626 * do DMA address check in tg3_start_xmit().
17627 */
63c3a66f 17628 if (tg3_flag(tp, IS_5788))
284901a9 17629 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
63c3a66f 17630 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
50cf156a 17631 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
72f2afb8 17632#ifdef CONFIG_HIGHMEM
6a35528a 17633 dma_mask = DMA_BIT_MASK(64);
72f2afb8 17634#endif
4a29cc2e 17635 } else
6a35528a 17636 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
72f2afb8
MC		 17637
17638 /* Configure DMA attributes. */
284901a9 17639 if (dma_mask > DMA_BIT_MASK(32)) {
72f2afb8
MC		 17640 err = pci_set_dma_mask(pdev, dma_mask);
17641 if (!err) {
0da0606f 17642 features |= NETIF_F_HIGHDMA;
72f2afb8
MC		 17643 err = pci_set_consistent_dma_mask(pdev,
17644 persist_dma_mask);
17645 if (err < 0) {
ab96b241
MC		 17646 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17647 "DMA for consistent allocations\n");
c9cab24e 17648 goto err_out_apeunmap;
72f2afb8
MC		 17649 }
17650 }
17651 }
284901a9
YH		 17652 if (err || dma_mask == DMA_BIT_MASK(32)) {
17653 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
72f2afb8 17654 if (err) {
ab96b241
MC		 17655 dev_err(&pdev->dev,
17656 "No usable DMA configuration, aborting\n");
c9cab24e 17657 goto err_out_apeunmap;
72f2afb8
MC		 17658 }
17659 }
17660
fdfec172 17661 tg3_init_bufmgr_config(tp);
1da177e4 17662
0da0606f
MC		 17663 /* 5700 B0 chips do not support checksumming correctly due
17664 * to hardware bugs.
17665 */
4153577a 17666 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
0da0606f
MC		 17667 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17668
17669 if (tg3_flag(tp, 5755_PLUS))
17670 features |= NETIF_F_IPV6_CSUM;
17671 }
17672
4e3a7aaa
MC		 17673 /* TSO is on by default on chips that support hardware TSO.
17674 * Firmware TSO on older chips gives lower performance, so it
17675 * is off by default, but can be enabled using ethtool.
17676 */
63c3a66f
JP		 17677 if ((tg3_flag(tp, HW_TSO_1) ||
17678 tg3_flag(tp, HW_TSO_2) ||
17679 tg3_flag(tp, HW_TSO_3)) &&
0da0606f
MC		 17680 (features & NETIF_F_IP_CSUM))
17681 features |= NETIF_F_TSO;
63c3a66f 17682 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
0da0606f
MC		 17683 if (features & NETIF_F_IPV6_CSUM)
17684 features |= NETIF_F_TSO6;
63c3a66f 17685 if (tg3_flag(tp, HW_TSO_3) ||
4153577a
JP		 17686 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17687 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17688 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17689 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17690 tg3_asic_rev(tp) == ASIC_REV_57780)
0da0606f 17691 features |= NETIF_F_TSO_ECN;
b0026624 17692 }
1da177e4 17693
51dfe7b9
VY		 17694 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17695 NETIF_F_HW_VLAN_CTAG_RX;
d542fe27
MC		 17696 dev->vlan_features |= features;
17697
06c03c02
MB		 17698 /*
17699 * Add loopback capability only for a subset of devices that support
17700 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17701 * loopback for the remaining devices.
17702 */
4153577a 17703 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
06c03c02
MB		 17704 !tg3_flag(tp, CPMU_PRESENT))
17705 /* Add the loopback capability */
0da0606f
MC		 17706 features |= NETIF_F_LOOPBACK;
17707
0da0606f 17708 dev->hw_features |= features;
e565eec3 17709 dev->priv_flags |= IFF_UNICAST_FLT;
06c03c02 17710
4153577a 17711 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
63c3a66f 17712 !tg3_flag(tp, TSO_CAPABLE) &&
1da177e4 17713 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
63c3a66f 17714 tg3_flag_set(tp, MAX_RXPEND_64);
1da177e4
LT		 17715 tp->rx_pending = 63;
17716 }
17717
1da177e4
LT		 17718 err = tg3_get_device_address(tp);
17719 if (err) {
ab96b241
MC		 17720 dev_err(&pdev->dev,
17721 "Could not obtain valid ethernet address, aborting\n");
c9cab24e 17722 goto err_out_apeunmap;
c88864df
MC		 17723 }
17724
1da177e4
LT		 17725 /*
17726 * Reset chip in case UNDI or EFI driver did not shutdown
17727 * DMA self test will enable WDMAC and we'll see (spurious)
17728 * pending DMA on the PCI bus at that point.
17729 */
17730 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17731 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
1da177e4 17732 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 17733 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 17734 }
17735
17736 err = tg3_test_dma(tp);
17737 if (err) {
ab96b241 17738 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
c88864df 17739 goto err_out_apeunmap;
1da177e4
LT		 17740 }
17741
78f90dcf
MC		 17742 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17743 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17744 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
6fd45cb8 17745 for (i = 0; i < tp->irq_max; i++) {
78f90dcf
MC		 17746 struct tg3_napi *tnapi = &tp->napi[i];
17747
17748 tnapi->tp = tp;
17749 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17750
17751 tnapi->int_mbox = intmbx;
93a700a9 17752 if (i <= 4)
78f90dcf
MC		 17753 intmbx += 0x8;
17754 else
17755 intmbx += 0x4;
17756
17757 tnapi->consmbox = rcvmbx;
17758 tnapi->prodmbox = sndmbx;
17759
66cfd1bd 17760 if (i)
78f90dcf 17761 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
66cfd1bd 17762 else
78f90dcf 17763 tnapi->coal_now = HOSTCC_MODE_NOW;
78f90dcf 17764
63c3a66f 17765 if (!tg3_flag(tp, SUPPORT_MSIX))
78f90dcf
MC		 17766 break;
17767
17768 /*
17769 * If we support MSIX, we'll be using RSS. If we're using
17770 * RSS, the first vector only handles link interrupts and the
17771 * remaining vectors handle rx and tx interrupts. Reuse the
17772 * mailbox values for the next iteration. The values we setup
17773 * above are still useful for the single vectored mode.
17774 */
17775 if (!i)
17776 continue;
17777
17778 rcvmbx += 0x8;
17779
17780 if (sndmbx & 0x4)
17781 sndmbx -= 0x4;
17782 else
17783 sndmbx += 0xc;
17784 }
17785
15f9850d
DM		 17786 tg3_init_coal(tp);
17787
c49a1561
MC		 17788 pci_set_drvdata(pdev, dev);
17789
4153577a
JP		 17790 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17791 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17792 tg3_asic_rev(tp) == ASIC_REV_5762)
fb4ce8ad
MC		 17793 tg3_flag_set(tp, PTP_CAPABLE);
17794
21f7638e
MC		 17795 tg3_timer_init(tp);
17796
402e1398
MC		 17797 tg3_carrier_off(tp);
17798
1da177e4
LT		 17799 err = register_netdev(dev);
17800 if (err) {
ab96b241 17801 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
0d3031d9 17802 goto err_out_apeunmap;
1da177e4
LT		 17803 }
17804
05dbe005
JP		 17805 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17806 tp->board_part_number,
4153577a 17807 tg3_chip_rev_id(tp),
05dbe005
JP		 17808 tg3_bus_string(tp, str),
17809 dev->dev_addr);
1da177e4 17810
f07e9af3 17811 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
3f0e3ad7 17812 struct phy_device *phydev;
ead2402c 17813 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
5129c3a3
MC		 17814 netdev_info(dev,
17815 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
05dbe005 17816 phydev->drv->name, dev_name(&phydev->dev));
f07e9af3
MC		 17817 } else {
17818 char *ethtype;
17819
17820 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17821 ethtype = "10/100Base-TX";
17822 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17823 ethtype = "1000Base-SX";
17824 else
17825 ethtype = "10/100/1000Base-T";
17826
5129c3a3 17827 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
47007831
MC		 17828 "(WireSpeed[%d], EEE[%d])\n",
17829 tg3_phy_string(tp), ethtype,
17830 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17831 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
f07e9af3 17832 }
05dbe005
JP		 17833
17834 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
dc668910 17835 (dev->features & NETIF_F_RXCSUM) != 0,
63c3a66f 17836 tg3_flag(tp, USE_LINKCHG_REG) != 0,
f07e9af3 17837 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
63c3a66f
JP		 17838 tg3_flag(tp, ENABLE_ASF) != 0,
17839 tg3_flag(tp, TSO_CAPABLE) != 0);
05dbe005
JP		 17840 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17841 tp->dma_rwctrl,
17842 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17843 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
1da177e4 17844
b45aa2f6
MC		 17845 pci_save_state(pdev);
17846
1da177e4
LT		 17847 return 0;
17848
0d3031d9
MC		 17849err_out_apeunmap:
17850 if (tp->aperegs) {
17851 iounmap(tp->aperegs);
17852 tp->aperegs = NULL;
17853 }
17854
1da177e4 17855err_out_iounmap:
6892914f
MC		 17856 if (tp->regs) {
17857 iounmap(tp->regs);
22abe310 17858 tp->regs = NULL;
6892914f 17859 }
1da177e4
LT		 17860
17861err_out_free_dev:
17862 free_netdev(dev);
17863
17864err_out_free_res:
17865 pci_release_regions(pdev);
17866
17867err_out_disable_pdev:
c80dc13d
GS		 17868 if (pci_is_enabled(pdev))
17869 pci_disable_device(pdev);
1da177e4
LT		 17870 return err;
17871}
17872
229b1ad1 17873static void tg3_remove_one(struct pci_dev *pdev)
1da177e4
LT		 17874{
17875 struct net_device *dev = pci_get_drvdata(pdev);
17876
17877 if (dev) {
17878 struct tg3 *tp = netdev_priv(dev);
17879
e3c5530b 17880 release_firmware(tp->fw);
077f849d 17881
db219973 17882 tg3_reset_task_cancel(tp);
158d7abd 17883
e730c823 17884 if (tg3_flag(tp, USE_PHYLIB)) {
b02fd9e3 17885 tg3_phy_fini(tp);
158d7abd 17886 tg3_mdio_fini(tp);
b02fd9e3 17887 }
158d7abd 17888
1da177e4 17889 unregister_netdev(dev);
0d3031d9
MC		 17890 if (tp->aperegs) {
17891 iounmap(tp->aperegs);
17892 tp->aperegs = NULL;
17893 }
6892914f
MC		 17894 if (tp->regs) {
17895 iounmap(tp->regs);
22abe310 17896 tp->regs = NULL;
6892914f 17897 }
1da177e4
LT		 17898 free_netdev(dev);
17899 pci_release_regions(pdev);
17900 pci_disable_device(pdev);
1da177e4
LT		 17901 }
17902}
17903
aa6027ca 17904#ifdef CONFIG_PM_SLEEP
c866b7ea 17905static int tg3_suspend(struct device *device)
1da177e4 17906{
c866b7ea 17907 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17908 struct net_device *dev = pci_get_drvdata(pdev);
17909 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17910 int err = 0;
17911
17912 rtnl_lock();
1da177e4
LT		 17913
17914 if (!netif_running(dev))
8496e85c 17915 goto unlock;
1da177e4 17916
db219973 17917 tg3_reset_task_cancel(tp);
b02fd9e3 17918 tg3_phy_stop(tp);
1da177e4
LT		 17919 tg3_netif_stop(tp);
17920
21f7638e 17921 tg3_timer_stop(tp);
1da177e4 17922
f47c11ee 17923 tg3_full_lock(tp, 1);
1da177e4 17924 tg3_disable_ints(tp);
f47c11ee 17925 tg3_full_unlock(tp);
1da177e4
LT		 17926
17927 netif_device_detach(dev);
17928
f47c11ee 17929 tg3_full_lock(tp, 0);
944d980e 17930 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
63c3a66f 17931 tg3_flag_clear(tp, INIT_COMPLETE);
f47c11ee 17932 tg3_full_unlock(tp);
1da177e4 17933
c866b7ea 17934 err = tg3_power_down_prepare(tp);
1da177e4 17935 if (err) {
b02fd9e3
MC		 17936 int err2;
17937
f47c11ee 17938 tg3_full_lock(tp, 0);
1da177e4 17939
63c3a66f 17940 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 17941 err2 = tg3_restart_hw(tp, true);
b02fd9e3 17942 if (err2)
b9ec6c1b 17943 goto out;
1da177e4 17944
21f7638e 17945 tg3_timer_start(tp);
1da177e4
LT		 17946
17947 netif_device_attach(dev);
17948 tg3_netif_start(tp);
17949
b9ec6c1b 17950out:
f47c11ee 17951 tg3_full_unlock(tp);
b02fd9e3
MC		 17952
17953 if (!err2)
17954 tg3_phy_start(tp);
1da177e4
LT		 17955 }
17956
8496e85c
RW		 17957unlock:
17958 rtnl_unlock();
1da177e4
LT		 17959 return err;
17960}
17961
c866b7ea 17962static int tg3_resume(struct device *device)
1da177e4 17963{
c866b7ea 17964 struct pci_dev *pdev = to_pci_dev(device);
1da177e4
LT		 17965 struct net_device *dev = pci_get_drvdata(pdev);
17966 struct tg3 *tp = netdev_priv(dev);
8496e85c
RW		 17967 int err = 0;
17968
17969 rtnl_lock();
1da177e4
LT		 17970
17971 if (!netif_running(dev))
8496e85c 17972 goto unlock;
1da177e4 17973
1da177e4
LT		 17974 netif_device_attach(dev);
17975
f47c11ee 17976 tg3_full_lock(tp, 0);
1da177e4 17977
2e460fc0
NS		 17978 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17979
63c3a66f 17980 tg3_flag_set(tp, INIT_COMPLETE);
942d1af0
NS		 17981 err = tg3_restart_hw(tp,
17982 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
b9ec6c1b
MC		 17983 if (err)
17984 goto out;
1da177e4 17985
21f7638e 17986 tg3_timer_start(tp);
1da177e4 17987
1da177e4
LT		 17988 tg3_netif_start(tp);
17989
b9ec6c1b 17990out:
f47c11ee 17991 tg3_full_unlock(tp);
1da177e4 17992
b02fd9e3
MC		 17993 if (!err)
17994 tg3_phy_start(tp);
17995
8496e85c
RW		 17996unlock:
17997 rtnl_unlock();
b9ec6c1b 17998 return err;
1da177e4 17999}
42df36a6 18000#endif /* CONFIG_PM_SLEEP */
1da177e4 18001
c866b7ea
RW		 18002static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18003
4c305fa2
NS		 18004static void tg3_shutdown(struct pci_dev *pdev)
18005{
18006 struct net_device *dev = pci_get_drvdata(pdev);
18007 struct tg3 *tp = netdev_priv(dev);
18008
18009 rtnl_lock();
18010 netif_device_detach(dev);
18011
18012 if (netif_running(dev))
18013 dev_close(dev);
18014
18015 if (system_state == SYSTEM_POWER_OFF)
18016 tg3_power_down(tp);
18017
18018 rtnl_unlock();
18019}
18020
b45aa2f6
MC		 18021/**
18022 * tg3_io_error_detected - called when PCI error is detected
18023 * @pdev: Pointer to PCI device
18024 * @state: The current pci connection state
18025 *
18026 * This function is called after a PCI bus error affecting
18027 * this device has been detected.
18028 */
18029static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18030 pci_channel_state_t state)
18031{
18032 struct net_device *netdev = pci_get_drvdata(pdev);
18033 struct tg3 *tp = netdev_priv(netdev);
18034 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18035
18036 netdev_info(netdev, "PCI I/O error detected\n");
18037
18038 rtnl_lock();
18039
d8af4dfd
GS		 18040 /* We probably don't have netdev yet */
18041 if (!netdev || !netif_running(netdev))
b45aa2f6
MC		 18042 goto done;
18043
18044 tg3_phy_stop(tp);
18045
18046 tg3_netif_stop(tp);
18047
21f7638e 18048 tg3_timer_stop(tp);
b45aa2f6
MC		 18049
18050 /* Want to make sure that the reset task doesn't run */
db219973 18051 tg3_reset_task_cancel(tp);
b45aa2f6
MC		 18052
18053 netif_device_detach(netdev);
18054
18055 /* Clean up software state, even if MMIO is blocked */
18056 tg3_full_lock(tp, 0);
18057 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18058 tg3_full_unlock(tp);
18059
18060done:
72bb72b0 18061 if (state == pci_channel_io_perm_failure) {
68293099
DB		 18062 if (netdev) {
18063 tg3_napi_enable(tp);
18064 dev_close(netdev);
18065 }
b45aa2f6 18066 err = PCI_ERS_RESULT_DISCONNECT;
72bb72b0 18067 } else {
b45aa2f6 18068 pci_disable_device(pdev);
72bb72b0 18069 }
b45aa2f6
MC		 18070
18071 rtnl_unlock();
18072
18073 return err;
18074}
18075
18076/**
18077 * tg3_io_slot_reset - called after the pci bus has been reset.
18078 * @pdev: Pointer to PCI device
18079 *
18080 * Restart the card from scratch, as if from a cold-boot.
18081 * At this point, the card has exprienced a hard reset,
18082 * followed by fixups by BIOS, and has its config space
18083 * set up identically to what it was at cold boot.
18084 */
18085static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18086{
18087 struct net_device *netdev = pci_get_drvdata(pdev);
18088 struct tg3 *tp = netdev_priv(netdev);
18089 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18090 int err;
18091
18092 rtnl_lock();
18093
18094 if (pci_enable_device(pdev)) {
68293099
DB		 18095 dev_err(&pdev->dev,
18096 "Cannot re-enable PCI device after reset.\n");
b45aa2f6
MC		 18097 goto done;
18098 }
18099
18100 pci_set_master(pdev);
18101 pci_restore_state(pdev);
18102 pci_save_state(pdev);
18103
68293099 18104 if (!netdev || !netif_running(netdev)) {
b45aa2f6
MC		 18105 rc = PCI_ERS_RESULT_RECOVERED;
18106 goto done;
18107 }
18108
18109 err = tg3_power_up(tp);
bed9829f 18110 if (err)
b45aa2f6 18111 goto done;
b45aa2f6
MC		 18112
18113 rc = PCI_ERS_RESULT_RECOVERED;
18114
18115done:
68293099 18116 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
72bb72b0
MC		 18117 tg3_napi_enable(tp);
18118 dev_close(netdev);
18119 }
b45aa2f6
MC		 18120 rtnl_unlock();
18121
18122 return rc;
18123}
18124
18125/**
18126 * tg3_io_resume - called when traffic can start flowing again.
18127 * @pdev: Pointer to PCI device
18128 *
18129 * This callback is called when the error recovery driver tells
18130 * us that its OK to resume normal operation.
18131 */
18132static void tg3_io_resume(struct pci_dev *pdev)
18133{
18134 struct net_device *netdev = pci_get_drvdata(pdev);
18135 struct tg3 *tp = netdev_priv(netdev);
18136 int err;
18137
18138 rtnl_lock();
18139
18140 if (!netif_running(netdev))
18141 goto done;
18142
18143 tg3_full_lock(tp, 0);
2e460fc0 18144 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
63c3a66f 18145 tg3_flag_set(tp, INIT_COMPLETE);
953c96e0 18146 err = tg3_restart_hw(tp, true);
b45aa2f6 18147 if (err) {
35763066 18148 tg3_full_unlock(tp);
b45aa2f6
MC		 18149 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18150 goto done;
18151 }
18152
18153 netif_device_attach(netdev);
18154
21f7638e 18155 tg3_timer_start(tp);
b45aa2f6
MC		 18156
18157 tg3_netif_start(tp);
18158
35763066
NNS		 18159 tg3_full_unlock(tp);
18160
b45aa2f6
MC		 18161 tg3_phy_start(tp);
18162
18163done:
18164 rtnl_unlock();
18165}
18166
3646f0e5 18167static const struct pci_error_handlers tg3_err_handler = {
b45aa2f6
MC		 18168 .error_detected = tg3_io_error_detected,
18169 .slot_reset = tg3_io_slot_reset,
18170 .resume = tg3_io_resume
18171};
18172
1da177e4
LT		 18173static struct pci_driver tg3_driver = {
18174 .name = DRV_MODULE_NAME,
18175 .id_table = tg3_pci_tbl,
18176 .probe = tg3_init_one,
229b1ad1 18177 .remove = tg3_remove_one,
b45aa2f6 18178 .err_handler = &tg3_err_handler,
42df36a6 18179 .driver.pm = &tg3_pm_ops,
4c305fa2 18180 .shutdown = tg3_shutdown,
1da177e4
LT		 18181};
18182
8dbb0dc2 18183module_pci_driver(tg3_driver);
Linux kernel - Deliverables
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