[deliverable/linux.git] / drivers / net / ethernet / cavium / liquidio / octeon_iq.h

/**********************************************************************
 * Author: Cavium, Inc.
 *
 * Contact: support@cavium.com
 *          Please include "LiquidIO" in the subject.
 *
 * Copyright (c) 2003-2015 Cavium, Inc.
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium, Inc. for more information
 **********************************************************************/

/*!  \file  octeon_iq.h
 *   \brief Host Driver: Implementation of Octeon input queues. "Input" is
 *   with respect to the Octeon device on the NIC. From this driver's
 *   point of view they are egress queues.
 */

#ifndef __OCTEON_IQ_H__
#define  __OCTEON_IQ_H__

#define IQ_STATUS_RUNNING   1

#define IQ_SEND_OK          0
#define IQ_SEND_STOP        1
#define IQ_SEND_FAILED     -1

/*-------------------------  INSTRUCTION QUEUE --------------------------*/

/* \cond */

#define REQTYPE_NONE                 0
#define REQTYPE_NORESP_NET           1
#define REQTYPE_NORESP_NET_SG        2
#define REQTYPE_RESP_NET             3
#define REQTYPE_RESP_NET_SG          4
#define REQTYPE_SOFT_COMMAND         5
#define REQTYPE_LAST                 5

struct octeon_request_list {
	u32 reqtype;
	void *buf;
};

/* \endcond */

/** Input Queue statistics. Each input queue has four stats fields. */
struct oct_iq_stats {
	u64 instr_posted; /**< Instructions posted to this queue. */
	u64 instr_processed; /**< Instructions processed in this queue. */
	u64 instr_dropped; /**< Instructions that could not be processed */
	u64 bytes_sent;  /**< Bytes sent through this queue. */
	u64 sgentry_sent;/**< Gather entries sent through this queue. */
	u64 tx_done;/**< Num of packets sent to network. */
	u64 tx_iq_busy;/**< Numof times this iq was found to be full. */
	u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */
	u64 tx_tot_bytes;/**< Total count of bytes sento to network. */
	u64 tx_gso;  /* count of tso */
	u64 tx_vxlan; /* tunnel */
	u64 tx_dmamap_fail;
	u64 tx_restart;
	/*u64 tx_timeout_count;*/
};

#define OCT_IQ_STATS_SIZE   (sizeof(struct oct_iq_stats))

/** The instruction (input) queue.
 *  The input queue is used to post raw (instruction) mode data or packet
 *  data to Octeon device from the host. Each input queue (upto 4) for
 *  a Octeon device has one such structure to represent it.
*/
struct octeon_instr_queue {
	struct octeon_device *oct_dev;

	/** A spinlock to protect access to the input ring.  */
	spinlock_t lock;

	/** A spinlock to protect while posting on the ring.  */
	spinlock_t post_lock;

	u32 pkt_in_done;

	/** A spinlock to protect access to the input ring.*/
	spinlock_t iq_flush_running_lock;

	/** Flag that indicates if the queue uses 64 byte commands. */
	u32 iqcmd_64B:1;

	/** Queue info. */
	union oct_txpciq txpciq;

	u32 rsvd:17;

	/* Controls whether extra flushing of IQ is done on Tx */
	u32 do_auto_flush:1;

	u32 status:8;

	/** Maximum no. of instructions in this queue. */
	u32 max_count;

	/** Index in input ring where the driver should write the next packet */
	u32 host_write_index;

	/** Index in input ring where Octeon is expected to read the next
	 * packet.
	 */
	u32 octeon_read_index;

	/** This index aids in finding the window in the queue where Octeon
	  * has read the commands.
	  */
	u32 flush_index;

	/** This field keeps track of the instructions pending in this queue. */
	atomic_t instr_pending;

	u32 reset_instr_cnt;

	/** Pointer to the Virtual Base addr of the input ring. */
	u8 *base_addr;

	struct octeon_request_list *request_list;

	/** Octeon doorbell register for the ring. */
	void __iomem *doorbell_reg;

	/** Octeon instruction count register for this ring. */
	void __iomem *inst_cnt_reg;

	/** Number of instructions pending to be posted to Octeon. */
	u32 fill_cnt;

	/** The max. number of instructions that can be held pending by the
	 * driver.
	 */
	u32 fill_threshold;

	/** The last time that the doorbell was rung. */
	u64 last_db_time;

	/** The doorbell timeout. If the doorbell was not rung for this time and
	  * fill_cnt is non-zero, ring the doorbell again.
	  */
	u32 db_timeout;

	/** Statistics for this input queue. */
	struct oct_iq_stats stats;

	/** DMA mapped base address of the input descriptor ring. */
	u64 base_addr_dma;

	/** Application context */
	void *app_ctx;

	/* network stack queue index */
	int q_index;

	/*os ifidx associated with this queue */
	int ifidx;

};

/*----------------------  INSTRUCTION FORMAT ----------------------------*/

/** 32-byte instruction format.
 *  Format of instruction for a 32-byte mode input queue.
 */
struct octeon_instr_32B {
	/** Pointer where the input data is available. */
	u64 dptr;

	/** Instruction Header.  */
	u64 ih;

	/** Pointer where the response for a RAW mode packet will be written
	 * by Octeon.
	 */
	u64 rptr;

	/** Input Request Header. Additional info about the input. */
	u64 irh;

};

#define OCT_32B_INSTR_SIZE     (sizeof(struct octeon_instr_32B))

/** 64-byte instruction format.
 *  Format of instruction for a 64-byte mode input queue.
 */
struct octeon_instr2_64B {
	/** Pointer where the input data is available. */
	u64 dptr;

	/** Instruction Header. */
	u64 ih2;

	/** Input Request Header. */
	u64 irh;

	/** opcode/subcode specific parameters */
	u64 ossp[2];

	/** Return Data Parameters */
	u64 rdp;

	/** Pointer where the response for a RAW mode packet will be written
	 * by Octeon.
	 */
	u64 rptr;

	u64 reserved;
};

struct octeon_instr3_64B {
	/** Pointer where the input data is available. */
	u64 dptr;

	/** Instruction Header. */
	u64 ih3;

	/** Instruction Header. */
	u64 pki_ih3;

	/** Input Request Header. */
	u64 irh;

	/** opcode/subcode specific parameters */
	u64 ossp[2];

	/** Return Data Parameters */
	u64 rdp;

	/** Pointer where the response for a RAW mode packet will be written
	 * by Octeon.
	 */
	u64 rptr;

};

union octeon_instr_64B {
	struct octeon_instr2_64B cmd2;
	struct octeon_instr3_64B cmd3;
};

#define OCT_64B_INSTR_SIZE     (sizeof(union octeon_instr_64B))

/** The size of each buffer in soft command buffer pool
 */
#define  SOFT_COMMAND_BUFFER_SIZE	1536

struct octeon_soft_command {
	/** Soft command buffer info. */
	struct list_head node;
	u64 dma_addr;
	u32 size;

	/** Command and return status */
	union octeon_instr_64B cmd;

#define COMPLETION_WORD_INIT    0xffffffffffffffffULL
	u64 *status_word;

	/** Data buffer info */
	void *virtdptr;
	u64 dmadptr;
	u32 datasize;

	/** Return buffer info */
	void *virtrptr;
	u64 dmarptr;
	u32 rdatasize;

	/** Context buffer info */
	void *ctxptr;
	u32  ctxsize;

	/** Time out and callback */
	size_t wait_time;
	size_t timeout;
	u32 iq_no;
	void (*callback)(struct octeon_device *, u32, void *);
	void *callback_arg;
};

/** Maximum number of buffers to allocate into soft command buffer pool
 */
#define  MAX_SOFT_COMMAND_BUFFERS	256

/** Head of a soft command buffer pool.
 */
struct octeon_sc_buffer_pool {
	/** List structure to add delete pending entries to */
	struct list_head head;

	/** A lock for this response list */
	spinlock_t lock;

	atomic_t alloc_buf_count;
};

int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
int octeon_free_sc_buffer_pool(struct octeon_device *oct);
struct octeon_soft_command *
	octeon_alloc_soft_command(struct octeon_device *oct,
				  u32 datasize, u32 rdatasize,
				  u32 ctxsize);
void octeon_free_soft_command(struct octeon_device *oct,
			      struct octeon_soft_command *sc);

/**
 *  octeon_init_instr_queue()
 *  @param octeon_dev      - pointer to the octeon device structure.
 *  @param txpciq          - queue to be initialized (0 <= q_no <= 3).
 *
 *  Called at driver init time for each input queue. iq_conf has the
 *  configuration parameters for the queue.
 *
 *  @return  Success: 0   Failure: 1
 */
int octeon_init_instr_queue(struct octeon_device *octeon_dev,
			    union oct_txpciq txpciq,
			    u32 num_descs);

/**
 *  octeon_delete_instr_queue()
 *  @param octeon_dev      - pointer to the octeon device structure.
 *  @param iq_no           - queue to be deleted (0 <= q_no <= 3).
 *
 *  Called at driver unload time for each input queue. Deletes all
 *  allocated resources for the input queue.
 *
 *  @return  Success: 0   Failure: 1
 */
int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);

int lio_wait_for_instr_fetch(struct octeon_device *oct);

int
octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
				void (*fn)(void *));

int
lio_process_iq_request_list(struct octeon_device *oct,
			    struct octeon_instr_queue *iq, u32 napi_budget);

int octeon_send_command(struct octeon_device *oct, u32 iq_no,
			u32 force_db, void *cmd, void *buf,
			u32 datasize, u32 reqtype);

void octeon_prepare_soft_command(struct octeon_device *oct,
				 struct octeon_soft_command *sc,
				 u8 opcode, u8 subcode,
				 u32 irh_ossp, u64 ossp0,
				 u64 ossp1);

int octeon_send_soft_command(struct octeon_device *oct,
			     struct octeon_soft_command *sc);

int octeon_setup_iq(struct octeon_device *oct, int ifidx,
		    int q_index, union oct_txpciq iq_no, u32 num_descs,
		    void *app_ctx);
int
octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
		u32 pending_thresh, u32 napi_budget);
#endif				/* __OCTEON_IQ_H__ */
Commit	Line	Data
f21fb3ed RV	1	/**********************************************************************
	2	* Author: Cavium, Inc.
	3	*
	4	* Contact: support@cavium.com
	5	* Please include "LiquidIO" in the subject.
	6	*
	7	* Copyright (c) 2003-2015 Cavium, Inc.
	8	*
	9	* This file is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License, Version 2, as
	11	* published by the Free Software Foundation.
	12	*
	13	* This file is distributed in the hope that it will be useful, but
	14	* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
	15	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
	16	* NONINFRINGEMENT. See the GNU General Public License for more
	17	* details.
	18	*
	19	* This file may also be available under a different license from Cavium.
	20	* Contact Cavium, Inc. for more information
	21	**********************************************************************/
	22
	23	/*! \file octeon_iq.h
	24	* \brief Host Driver: Implementation of Octeon input queues. "Input" is
	25	* with respect to the Octeon device on the NIC. From this driver's
	26	* point of view they are egress queues.
	27	*/
	28
	29	#ifndef __OCTEON_IQ_H__
	30	#define __OCTEON_IQ_H__
	31
	32	#define IQ_STATUS_RUNNING 1
	33
	34	#define IQ_SEND_OK 0
	35	#define IQ_SEND_STOP 1
	36	#define IQ_SEND_FAILED -1
	37
	38	/------------------------- INSTRUCTION QUEUE --------------------------/
	39
	40	/* \cond */
	41
	42	#define REQTYPE_NONE 0
	43	#define REQTYPE_NORESP_NET 1
	44	#define REQTYPE_NORESP_NET_SG 2
	45	#define REQTYPE_RESP_NET 3
	46	#define REQTYPE_RESP_NET_SG 4
	47	#define REQTYPE_SOFT_COMMAND 5
	48	#define REQTYPE_LAST 5
	49
	50	struct octeon_request_list {
	51	u32 reqtype;
	52	void *buf;
	53	};
	54
	55	/* \endcond */
	56
	57	/** Input Queue statistics. Each input queue has four stats fields. */
	58	struct oct_iq_stats {
	59	u64 instr_posted; /*< Instructions posted to this queue. /
	60	u64 instr_processed; /*< Instructions processed in this queue. /
	61	u64 instr_dropped; /*< Instructions that could not be processed /
	62	u64 bytes_sent; /*< Bytes sent through this queue. /
	63	u64 sgentry_sent;/*< Gather entries sent through this queue. /
	64	u64 tx_done;/*< Num of packets sent to network. /
65	u64 tx_iq_busy;/*< Numof times this iq was found to be full. /
66	u64 tx_dropped;/*< Numof pkts dropped dueto xmitpath errors. /
67	u64 tx_tot_bytes;/*< Total count of bytes sento to network. /
1f164717	68	u64 tx_gso; /* count of tso */
01fb237a	69	u64 tx_vxlan; /* tunnel */
1f164717 RV	70	u64 tx_dmamap_fail;
	71	u64 tx_restart;
	72	/u64 tx_timeout_count;/
f21fb3ed RV	73	};
	74
	75	#define OCT_IQ_STATS_SIZE (sizeof(struct oct_iq_stats))
	76
	77	/** The instruction (input) queue.
	78	* The input queue is used to post raw (instruction) mode data or packet
	79	* data to Octeon device from the host. Each input queue (upto 4) for
	80	* a Octeon device has one such structure to represent it.
	81	*/
	82	struct octeon_instr_queue {
6a885b60 RV	83	struct octeon_device *oct_dev;
6a885b60 RV	84
f21fb3ed RV	85	/** A spinlock to protect access to the input ring. */
	86	spinlock_t lock;
	87
9a96bde4 RV	88	/** A spinlock to protect while posting on the ring. */
	89	spinlock_t post_lock;
	90
cd8b1eb4 RV	91	u32 pkt_in_done;
cd8b1eb4 RV	92
9a96bde4 RV	93	/** A spinlock to protect access to the input ring.*/
	94	spinlock_t iq_flush_running_lock;
	95
f21fb3ed RV	96	/** Flag that indicates if the queue uses 64 byte commands. */
	97	u32 iqcmd_64B:1;
	98
26236fa9 RV	99	/** Queue info. */
26236fa9 RV	100	union oct_txpciq txpciq;
f21fb3ed RV	101
	102	u32 rsvd:17;
	103
a2c64b67	104	/* Controls whether extra flushing of IQ is done on Tx */
f21fb3ed RV	105	u32 do_auto_flush:1;
	106
	107	u32 status:8;
	108
	109	/** Maximum no. of instructions in this queue. */
	110	u32 max_count;
	111
	112	/** Index in input ring where the driver should write the next packet */
	113	u32 host_write_index;
	114
	115	/** Index in input ring where Octeon is expected to read the next
	116	* packet.
	117	*/
	118	u32 octeon_read_index;
	119
	120	/** This index aids in finding the window in the queue where Octeon
	121	* has read the commands.
	122	*/
	123	u32 flush_index;
	124
	125	/** This field keeps track of the instructions pending in this queue. */
	126	atomic_t instr_pending;
	127
	128	u32 reset_instr_cnt;
	129
	130	/** Pointer to the Virtual Base addr of the input ring. */
	131	u8 *base_addr;
	132
	133	struct octeon_request_list *request_list;
	134
	135	/** Octeon doorbell register for the ring. */
	136	void __iomem *doorbell_reg;
	137
	138	/** Octeon instruction count register for this ring. */
	139	void __iomem *inst_cnt_reg;
	140
	141	/** Number of instructions pending to be posted to Octeon. */
	142	u32 fill_cnt;
	143
	144	/** The max. number of instructions that can be held pending by the
	145	* driver.
	146	*/
	147	u32 fill_threshold;
	148
	149	/** The last time that the doorbell was rung. */
	150	u64 last_db_time;
	151
	152	/** The doorbell timeout. If the doorbell was not rung for this time and
	153	* fill_cnt is non-zero, ring the doorbell again.
	154	*/
	155	u32 db_timeout;
	156
	157	/** Statistics for this input queue. */
	158	struct oct_iq_stats stats;
	159
	160	/** DMA mapped base address of the input descriptor ring. */
	161	u64 base_addr_dma;
	162
	163	/** Application context */
	164	void *app_ctx;
0cece6c5 RV	165
	166	/* network stack queue index */
	167	int q_index;
	168
	169	/os ifidx associated with this queue /
	170	int ifidx;
	171
f21fb3ed RV	172	};
	173
	174	/---------------------- INSTRUCTION FORMAT ----------------------------/
	175
	176	/** 32-byte instruction format.
	177	* Format of instruction for a 32-byte mode input queue.
	178	*/
	179	struct octeon_instr_32B {
	180	/** Pointer where the input data is available. */
	181	u64 dptr;
	182
	183	/** Instruction Header. */
	184	u64 ih;
	185
	186	/** Pointer where the response for a RAW mode packet will be written
	187	* by Octeon.
	188	*/
	189	u64 rptr;
	190
	191	/** Input Request Header. Additional info about the input. */
	192	u64 irh;
	193
	194	};
	195
	196	#define OCT_32B_INSTR_SIZE (sizeof(struct octeon_instr_32B))
	197
	198	/** 64-byte instruction format.
	199	* Format of instruction for a 64-byte mode input queue.
	200	*/
6a885b60	201	struct octeon_instr2_64B {
f21fb3ed RV	202	/** Pointer where the input data is available. */
	203	u64 dptr;
	204
	205	/** Instruction Header. */
6a885b60	206	u64 ih2;
f21fb3ed RV	207
	208	/** Input Request Header. */
	209	u64 irh;
	210
	211	/** opcode/subcode specific parameters */
	212	u64 ossp[2];
	213
	214	/** Return Data Parameters */
	215	u64 rdp;
	216
	217	/** Pointer where the response for a RAW mode packet will be written
	218	* by Octeon.
	219	*/
	220	u64 rptr;
	221
	222	u64 reserved;
6a885b60 RV	223	};
	224
	225	struct octeon_instr3_64B {
	226	/** Pointer where the input data is available. */
	227	u64 dptr;
	228
	229	/** Instruction Header. */
	230	u64 ih3;
	231
	232	/** Instruction Header. */
	233	u64 pki_ih3;
	234
	235	/** Input Request Header. */
	236	u64 irh;
	237
	238	/** opcode/subcode specific parameters */
	239	u64 ossp[2];
	240
	241	/** Return Data Parameters */
	242	u64 rdp;
	243
	244	/** Pointer where the response for a RAW mode packet will be written
	245	* by Octeon.
	246	*/
	247	u64 rptr;
f21fb3ed RV	248
	249	};
	250
6a885b60 RV	251	union octeon_instr_64B {
	252	struct octeon_instr2_64B cmd2;
	253	struct octeon_instr3_64B cmd3;
	254	};
	255
	256	#define OCT_64B_INSTR_SIZE (sizeof(union octeon_instr_64B))
f21fb3ed RV	257
	258	/** The size of each buffer in soft command buffer pool
	259	*/
63da8404	260	#define SOFT_COMMAND_BUFFER_SIZE 1536
f21fb3ed RV	261
	262	struct octeon_soft_command {
	263	/** Soft command buffer info. */
	264	struct list_head node;
	265	u64 dma_addr;
	266	u32 size;
	267
	268	/** Command and return status */
6a885b60 RV	269	union octeon_instr_64B cmd;
6a885b60 RV	270
f21fb3ed RV	271	#define COMPLETION_WORD_INIT 0xffffffffffffffffULL
	272	u64 *status_word;
	273
	274	/** Data buffer info */
	275	void *virtdptr;
	276	u64 dmadptr;
	277	u32 datasize;
	278
	279	/** Return buffer info */
	280	void *virtrptr;
	281	u64 dmarptr;
	282	u32 rdatasize;
	283
	284	/** Context buffer info */
	285	void *ctxptr;
	286	u32 ctxsize;
	287
	288	/** Time out and callback */
	289	size_t wait_time;
	290	size_t timeout;
	291	u32 iq_no;
	292	void (callback)(struct octeon_device , u32, void *);
	293	void *callback_arg;
	294	};
	295
	296	/** Maximum number of buffers to allocate into soft command buffer pool
	297	*/
63da8404	298	#define MAX_SOFT_COMMAND_BUFFERS 256
f21fb3ed RV	299
	300	/** Head of a soft command buffer pool.
	301	*/
	302	struct octeon_sc_buffer_pool {
	303	/** List structure to add delete pending entries to */
	304	struct list_head head;
	305
	306	/** A lock for this response list */
	307	spinlock_t lock;
	308
	309	atomic_t alloc_buf_count;
	310	};
	311
	312	int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
	313	int octeon_free_sc_buffer_pool(struct octeon_device *oct);
	314	struct octeon_soft_command *
	315	octeon_alloc_soft_command(struct octeon_device *oct,
	316	u32 datasize, u32 rdatasize,
	317	u32 ctxsize);
	318	void octeon_free_soft_command(struct octeon_device *oct,
	319	struct octeon_soft_command *sc);
	320
	321	/**
	322	* octeon_init_instr_queue()
	323	* @param octeon_dev - pointer to the octeon device structure.
26236fa9	324	* @param txpciq - queue to be initialized (0 <= q_no <= 3).
f21fb3ed RV	325	*
	326	* Called at driver init time for each input queue. iq_conf has the
	327	* configuration parameters for the queue.
	328	*
	329	* @return Success: 0 Failure: 1
	330	*/
26236fa9 RV	331	int octeon_init_instr_queue(struct octeon_device *octeon_dev,
26236fa9 RV	332	union oct_txpciq txpciq,
f21fb3ed RV	333	u32 num_descs);
	334
	335	/**
	336	* octeon_delete_instr_queue()
	337	* @param octeon_dev - pointer to the octeon device structure.
	338	* @param iq_no - queue to be deleted (0 <= q_no <= 3).
	339	*
	340	* Called at driver unload time for each input queue. Deletes all
	341	* allocated resources for the input queue.
	342	*
	343	* @return Success: 0 Failure: 1
	344	*/
	345	int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
	346
	347	int lio_wait_for_instr_fetch(struct octeon_device *oct);
	348
	349	int
	350	octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
	351	void (fn)(void ));
	352
	353	int
	354	lio_process_iq_request_list(struct octeon_device *oct,
9a96bde4	355	struct octeon_instr_queue *iq, u32 napi_budget);
f21fb3ed RV	356
	357	int octeon_send_command(struct octeon_device *oct, u32 iq_no,
	358	u32 force_db, void cmd, void buf,
	359	u32 datasize, u32 reqtype);
	360
	361	void octeon_prepare_soft_command(struct octeon_device *oct,
	362	struct octeon_soft_command *sc,
	363	u8 opcode, u8 subcode,
	364	u32 irh_ossp, u64 ossp0,
	365	u64 ossp1);
	366
	367	int octeon_send_soft_command(struct octeon_device *oct,
	368	struct octeon_soft_command *sc);
	369
0cece6c5 RV	370	int octeon_setup_iq(struct octeon_device *oct, int ifidx,
	371	int q_index, union oct_txpciq iq_no, u32 num_descs,
	372	void *app_ctx);
9a96bde4 RV	373	int
	374	octeon_flush_iq(struct octeon_device oct, struct octeon_instr_queue iq,
	375	u32 pending_thresh, u32 napi_budget);
f21fb3ed	376	#endif /* __OCTEON_IQ_H__ */