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RDMA/cxgb4: Fix LE hash collision bug for passive open connection
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
51#include "t4_hw.h"
52
53#define FW_VERSION_MAJOR 1
54#define FW_VERSION_MINOR 1
55#define FW_VERSION_MICRO 0
56
3069ee9b
VP		 57#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
58
625ba2c2
DM		 59enum {
60 MAX_NPORTS = 4, /* max # of ports */
47d54d65 61 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 62 EC_LEN = 16, /* E/C length */
63 ID_LEN = 16, /* ID length */
64};
65
66enum {
67 MEM_EDC0,
68 MEM_EDC1,
69 MEM_MC
70};
71
3069ee9b 72enum {
3eb4afbf
VP		 73 MEMWIN0_APERTURE = 2048,
74 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 75 MEMWIN1_APERTURE = 32768,
76 MEMWIN1_BASE = 0x28000,
3eb4afbf
VP		 77 MEMWIN2_APERTURE = 65536,
78 MEMWIN2_BASE = 0x30000,
3069ee9b
VP		 79};
80
625ba2c2
DM		 81enum dev_master {
82 MASTER_CANT,
83 MASTER_MAY,
84 MASTER_MUST
85};
86
87enum dev_state {
88 DEV_STATE_UNINIT,
89 DEV_STATE_INIT,
90 DEV_STATE_ERR
91};
92
93enum {
94 PAUSE_RX = 1 << 0,
95 PAUSE_TX = 1 << 1,
96 PAUSE_AUTONEG = 1 << 2
97};
98
99struct port_stats {
100 u64 tx_octets; /* total # of octets in good frames */
101 u64 tx_frames; /* all good frames */
102 u64 tx_bcast_frames; /* all broadcast frames */
103 u64 tx_mcast_frames; /* all multicast frames */
104 u64 tx_ucast_frames; /* all unicast frames */
105 u64 tx_error_frames; /* all error frames */
106
107 u64 tx_frames_64; /* # of Tx frames in a particular range */
108 u64 tx_frames_65_127;
109 u64 tx_frames_128_255;
110 u64 tx_frames_256_511;
111 u64 tx_frames_512_1023;
112 u64 tx_frames_1024_1518;
113 u64 tx_frames_1519_max;
114
115 u64 tx_drop; /* # of dropped Tx frames */
116 u64 tx_pause; /* # of transmitted pause frames */
117 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
118 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
119 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
120 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
121 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
122 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
123 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
124 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
125
126 u64 rx_octets; /* total # of octets in good frames */
127 u64 rx_frames; /* all good frames */
128 u64 rx_bcast_frames; /* all broadcast frames */
129 u64 rx_mcast_frames; /* all multicast frames */
130 u64 rx_ucast_frames; /* all unicast frames */
131 u64 rx_too_long; /* # of frames exceeding MTU */
132 u64 rx_jabber; /* # of jabber frames */
133 u64 rx_fcs_err; /* # of received frames with bad FCS */
134 u64 rx_len_err; /* # of received frames with length error */
135 u64 rx_symbol_err; /* symbol errors */
136 u64 rx_runt; /* # of short frames */
137
138 u64 rx_frames_64; /* # of Rx frames in a particular range */
139 u64 rx_frames_65_127;
140 u64 rx_frames_128_255;
141 u64 rx_frames_256_511;
142 u64 rx_frames_512_1023;
143 u64 rx_frames_1024_1518;
144 u64 rx_frames_1519_max;
145
146 u64 rx_pause; /* # of received pause frames */
147 u64 rx_ppp0; /* # of received PPP prio 0 frames */
148 u64 rx_ppp1; /* # of received PPP prio 1 frames */
149 u64 rx_ppp2; /* # of received PPP prio 2 frames */
150 u64 rx_ppp3; /* # of received PPP prio 3 frames */
151 u64 rx_ppp4; /* # of received PPP prio 4 frames */
152 u64 rx_ppp5; /* # of received PPP prio 5 frames */
153 u64 rx_ppp6; /* # of received PPP prio 6 frames */
154 u64 rx_ppp7; /* # of received PPP prio 7 frames */
155
156 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
157 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
158 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
159 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
160 u64 rx_trunc0; /* buffer-group 0 truncated packets */
161 u64 rx_trunc1; /* buffer-group 1 truncated packets */
162 u64 rx_trunc2; /* buffer-group 2 truncated packets */
163 u64 rx_trunc3; /* buffer-group 3 truncated packets */
164};
165
166struct lb_port_stats {
167 u64 octets;
168 u64 frames;
169 u64 bcast_frames;
170 u64 mcast_frames;
171 u64 ucast_frames;
172 u64 error_frames;
173
174 u64 frames_64;
175 u64 frames_65_127;
176 u64 frames_128_255;
177 u64 frames_256_511;
178 u64 frames_512_1023;
179 u64 frames_1024_1518;
180 u64 frames_1519_max;
181
182 u64 drop;
183
184 u64 ovflow0;
185 u64 ovflow1;
186 u64 ovflow2;
187 u64 ovflow3;
188 u64 trunc0;
189 u64 trunc1;
190 u64 trunc2;
191 u64 trunc3;
192};
193
194struct tp_tcp_stats {
195 u32 tcpOutRsts;
196 u64 tcpInSegs;
197 u64 tcpOutSegs;
198 u64 tcpRetransSegs;
199};
200
201struct tp_err_stats {
202 u32 macInErrs[4];
203 u32 hdrInErrs[4];
204 u32 tcpInErrs[4];
205 u32 tnlCongDrops[4];
206 u32 ofldChanDrops[4];
207 u32 tnlTxDrops[4];
208 u32 ofldVlanDrops[4];
209 u32 tcp6InErrs[4];
210 u32 ofldNoNeigh;
211 u32 ofldCongDefer;
212};
213
214struct tp_params {
215 unsigned int ntxchan; /* # of Tx channels */
216 unsigned int tre; /* log2 of core clocks per TP tick */
dca4faeb
VP		 217 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
218 /* channel map */
636f9d37
VP		 219
220 uint32_t dack_re; /* DACK timer resolution */
221 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
625ba2c2
DM		 222};
223
224struct vpd_params {
225 unsigned int cclk;
226 u8 ec[EC_LEN + 1];
227 u8 sn[SERNUM_LEN + 1];
228 u8 id[ID_LEN + 1];
229};
230
231struct pci_params {
232 unsigned char speed;
233 unsigned char width;
234};
235
236struct adapter_params {
237 struct tp_params tp;
238 struct vpd_params vpd;
239 struct pci_params pci;
240
900a6596
DM		 241 unsigned int sf_size; /* serial flash size in bytes */
242 unsigned int sf_nsec; /* # of flash sectors */
243 unsigned int sf_fw_start; /* start of FW image in flash */
244
625ba2c2
DM		 245 unsigned int fw_vers;
246 unsigned int tp_vers;
247 u8 api_vers[7];
248
249 unsigned short mtus[NMTUS];
250 unsigned short a_wnd[NCCTRL_WIN];
251 unsigned short b_wnd[NCCTRL_WIN];
252
253 unsigned char nports; /* # of ethernet ports */
254 unsigned char portvec;
255 unsigned char rev; /* chip revision */
256 unsigned char offload;
257
9a4da2cd
VP		 258 unsigned char bypass;
259
625ba2c2
DM		 260 unsigned int ofldq_wr_cred;
261};
262
263struct trace_params {
264 u32 data[TRACE_LEN / 4];
265 u32 mask[TRACE_LEN / 4];
266 unsigned short snap_len;
267 unsigned short min_len;
268 unsigned char skip_ofst;
269 unsigned char skip_len;
270 unsigned char invert;
271 unsigned char port;
272};
273
274struct link_config {
275 unsigned short supported; /* link capabilities */
276 unsigned short advertising; /* advertised capabilities */
277 unsigned short requested_speed; /* speed user has requested */
278 unsigned short speed; /* actual link speed */
279 unsigned char requested_fc; /* flow control user has requested */
280 unsigned char fc; /* actual link flow control */
281 unsigned char autoneg; /* autonegotiating? */
282 unsigned char link_ok; /* link up? */
283};
284
285#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
286
287enum {
288 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
289 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
290 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
291 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
292};
293
294enum {
295 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
296 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
297};
298
299struct adapter;
625ba2c2
DM		 300struct sge_rspq;
301
302struct port_info {
303 struct adapter *adapter;
625ba2c2
DM		 304 u16 viid;
305 s16 xact_addr_filt; /* index of exact MAC address filter */
306 u16 rss_size; /* size of VI's RSS table slice */
307 s8 mdio_addr;
308 u8 port_type;
309 u8 mod_type;
310 u8 port_id;
311 u8 tx_chan;
312 u8 lport; /* associated offload logical port */
625ba2c2
DM		 313 u8 nqsets; /* # of qsets */
314 u8 first_qset; /* index of first qset */
f796564a 315 u8 rss_mode;
625ba2c2 316 struct link_config link_cfg;
671b0060 317 u16 *rss;
625ba2c2
DM		 318};
319
625ba2c2
DM		 320struct dentry;
321struct work_struct;
322
323enum { /* adapter flags */
324 FULL_INIT_DONE = (1 << 0),
325 USING_MSI = (1 << 1),
326 USING_MSIX = (1 << 2),
625ba2c2 327 FW_OK = (1 << 4),
13ee15d3 328 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 329 USING_SOFT_PARAMS = (1 << 6),
330 MASTER_PF = (1 << 7),
331 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 332};
333
334struct rx_sw_desc;
335
336struct sge_fl { /* SGE free-buffer queue state */
337 unsigned int avail; /* # of available Rx buffers */
338 unsigned int pend_cred; /* new buffers since last FL DB ring */
339 unsigned int cidx; /* consumer index */
340 unsigned int pidx; /* producer index */
341 unsigned long alloc_failed; /* # of times buffer allocation failed */
342 unsigned long large_alloc_failed;
343 unsigned long starving;
344 /* RO fields */
345 unsigned int cntxt_id; /* SGE context id for the free list */
346 unsigned int size; /* capacity of free list */
347 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
348 __be64 *desc; /* address of HW Rx descriptor ring */
349 dma_addr_t addr; /* bus address of HW ring start */
350};
351
352/* A packet gather list */
353struct pkt_gl {
e91b0f24 354 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 355 void *va; /* virtual address of first byte */
356 unsigned int nfrags; /* # of fragments */
357 unsigned int tot_len; /* total length of fragments */
358};
359
360typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
361 const struct pkt_gl *gl);
362
363struct sge_rspq { /* state for an SGE response queue */
364 struct napi_struct napi;
365 const __be64 *cur_desc; /* current descriptor in queue */
366 unsigned int cidx; /* consumer index */
367 u8 gen; /* current generation bit */
368 u8 intr_params; /* interrupt holdoff parameters */
369 u8 next_intr_params; /* holdoff params for next interrupt */
370 u8 pktcnt_idx; /* interrupt packet threshold */
371 u8 uld; /* ULD handling this queue */
372 u8 idx; /* queue index within its group */
373 int offset; /* offset into current Rx buffer */
374 u16 cntxt_id; /* SGE context id for the response q */
375 u16 abs_id; /* absolute SGE id for the response q */
376 __be64 *desc; /* address of HW response ring */
377 dma_addr_t phys_addr; /* physical address of the ring */
378 unsigned int iqe_len; /* entry size */
379 unsigned int size; /* capacity of response queue */
380 struct adapter *adap;
381 struct net_device *netdev; /* associated net device */
382 rspq_handler_t handler;
383};
384
385struct sge_eth_stats { /* Ethernet queue statistics */
386 unsigned long pkts; /* # of ethernet packets */
387 unsigned long lro_pkts; /* # of LRO super packets */
388 unsigned long lro_merged; /* # of wire packets merged by LRO */
389 unsigned long rx_cso; /* # of Rx checksum offloads */
390 unsigned long vlan_ex; /* # of Rx VLAN extractions */
391 unsigned long rx_drops; /* # of packets dropped due to no mem */
392};
393
394struct sge_eth_rxq { /* SW Ethernet Rx queue */
395 struct sge_rspq rspq;
396 struct sge_fl fl;
397 struct sge_eth_stats stats;
398} ____cacheline_aligned_in_smp;
399
400struct sge_ofld_stats { /* offload queue statistics */
401 unsigned long pkts; /* # of packets */
402 unsigned long imm; /* # of immediate-data packets */
403 unsigned long an; /* # of asynchronous notifications */
404 unsigned long nomem; /* # of responses deferred due to no mem */
405};
406
407struct sge_ofld_rxq { /* SW offload Rx queue */
408 struct sge_rspq rspq;
409 struct sge_fl fl;
410 struct sge_ofld_stats stats;
411} ____cacheline_aligned_in_smp;
412
413struct tx_desc {
414 __be64 flit[8];
415};
416
417struct tx_sw_desc;
418
419struct sge_txq {
420 unsigned int in_use; /* # of in-use Tx descriptors */
421 unsigned int size; /* # of descriptors */
422 unsigned int cidx; /* SW consumer index */
423 unsigned int pidx; /* producer index */
424 unsigned long stops; /* # of times q has been stopped */
425 unsigned long restarts; /* # of queue restarts */
426 unsigned int cntxt_id; /* SGE context id for the Tx q */
427 struct tx_desc *desc; /* address of HW Tx descriptor ring */
428 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
429 struct sge_qstat *stat; /* queue status entry */
430 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 431 spinlock_t db_lock;
432 int db_disabled;
433 unsigned short db_pidx;
625ba2c2
DM		 434};
435
436struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
437 struct sge_txq q;
438 struct netdev_queue *txq; /* associated netdev TX queue */
439 unsigned long tso; /* # of TSO requests */
440 unsigned long tx_cso; /* # of Tx checksum offloads */
441 unsigned long vlan_ins; /* # of Tx VLAN insertions */
442 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
443} ____cacheline_aligned_in_smp;
444
445struct sge_ofld_txq { /* state for an SGE offload Tx queue */
446 struct sge_txq q;
447 struct adapter *adap;
448 struct sk_buff_head sendq; /* list of backpressured packets */
449 struct tasklet_struct qresume_tsk; /* restarts the queue */
450 u8 full; /* the Tx ring is full */
451 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
452} ____cacheline_aligned_in_smp;
453
454struct sge_ctrl_txq { /* state for an SGE control Tx queue */
455 struct sge_txq q;
456 struct adapter *adap;
457 struct sk_buff_head sendq; /* list of backpressured packets */
458 struct tasklet_struct qresume_tsk; /* restarts the queue */
459 u8 full; /* the Tx ring is full */
460} ____cacheline_aligned_in_smp;
461
462struct sge {
463 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
464 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
465 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
466
467 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
468 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
469 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
470 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
471
472 struct sge_rspq intrq ____cacheline_aligned_in_smp;
473 spinlock_t intrq_lock;
474
475 u16 max_ethqsets; /* # of available Ethernet queue sets */
476 u16 ethqsets; /* # of active Ethernet queue sets */
477 u16 ethtxq_rover; /* Tx queue to clean up next */
478 u16 ofldqsets; /* # of active offload queue sets */
479 u16 rdmaqs; /* # of available RDMA Rx queues */
480 u16 ofld_rxq[MAX_OFLD_QSETS];
481 u16 rdma_rxq[NCHAN];
482 u16 timer_val[SGE_NTIMERS];
483 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 484 u32 fl_pg_order; /* large page allocation size */
485 u32 stat_len; /* length of status page at ring end */
486 u32 pktshift; /* padding between CPL & packet data */
487 u32 fl_align; /* response queue message alignment */
488 u32 fl_starve_thres; /* Free List starvation threshold */
625ba2c2
DM		 489 unsigned int starve_thres;
490 u8 idma_state[2];
e46dab4d
DM		 491 unsigned int egr_start;
492 unsigned int ingr_start;
625ba2c2
DM		 493 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
494 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
495 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
496 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
497 struct timer_list rx_timer; /* refills starving FLs */
498 struct timer_list tx_timer; /* checks Tx queues */
499};
500
501#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
502#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
503#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
504
505struct l2t_data;
506
507struct adapter {
508 void __iomem *regs;
509 struct pci_dev *pdev;
510 struct device *pdev_dev;
3069ee9b 511 unsigned int mbox;
060e0c75
DM		 512 unsigned int fn;
513 unsigned int flags;
625ba2c2 514
625ba2c2
DM		 515 int msg_enable;
516
517 struct adapter_params params;
518 struct cxgb4_virt_res vres;
519 unsigned int swintr;
520
521 unsigned int wol;
522
523 struct {
524 unsigned short vec;
8cd18ac4 525 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 526 } msix_info[MAX_INGQ + 1];
527
528 struct sge sge;
529
530 struct net_device *port[MAX_NPORTS];
531 u8 chan_map[NCHAN]; /* channel -> port map */
532
636f9d37
VP		 533 unsigned int l2t_start;
534 unsigned int l2t_end;
625ba2c2
DM		 535 struct l2t_data *l2t;
536 void *uld_handle[CXGB4_ULD_MAX];
537 struct list_head list_node;
538
539 struct tid_info tids;
540 void **tid_release_head;
541 spinlock_t tid_release_lock;
542 struct work_struct tid_release_task;
881806bc
VP		 543 struct work_struct db_full_task;
544 struct work_struct db_drop_task;
625ba2c2
DM		 545 bool tid_release_task_busy;
546
547 struct dentry *debugfs_root;
548
549 spinlock_t stats_lock;
550};
551
f2b7e78d
VP		 552/* Defined bit width of user definable filter tuples
553 */
554#define ETHTYPE_BITWIDTH 16
555#define FRAG_BITWIDTH 1
556#define MACIDX_BITWIDTH 9
557#define FCOE_BITWIDTH 1
558#define IPORT_BITWIDTH 3
559#define MATCHTYPE_BITWIDTH 3
560#define PROTO_BITWIDTH 8
561#define TOS_BITWIDTH 8
562#define PF_BITWIDTH 8
563#define VF_BITWIDTH 8
564#define IVLAN_BITWIDTH 16
565#define OVLAN_BITWIDTH 16
566
567/* Filter matching rules. These consist of a set of ingress packet field
568 * (value, mask) tuples. The associated ingress packet field matches the
569 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
570 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
571 * matches an ingress packet when all of the individual individual field
572 * matching rules are true.
573 *
574 * Partial field masks are always valid, however, while it may be easy to
575 * understand their meanings for some fields (e.g. IP address to match a
576 * subnet), for others making sensible partial masks is less intuitive (e.g.
577 * MPS match type) ...
578 *
579 * Most of the following data structures are modeled on T4 capabilities.
580 * Drivers for earlier chips use the subsets which make sense for those chips.
581 * We really need to come up with a hardware-independent mechanism to
582 * represent hardware filter capabilities ...
583 */
584struct ch_filter_tuple {
585 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
586 * register selects which of these fields will participate in the
587 * filter match rules -- up to a maximum of 36 bits. Because
588 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
589 * set of fields.
590 */
591 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
592 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
593 uint32_t ivlan_vld:1; /* inner VLAN valid */
594 uint32_t ovlan_vld:1; /* outer VLAN valid */
595 uint32_t pfvf_vld:1; /* PF/VF valid */
596 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
597 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
598 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
599 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
600 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
601 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
602 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
603 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
604 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
605 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
606
607 /* Uncompressed header matching field rules. These are always
608 * available for field rules.
609 */
610 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
611 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
612 uint16_t lport; /* local port */
613 uint16_t fport; /* foreign port */
614};
615
616/* A filter ioctl command.
617 */
618struct ch_filter_specification {
619 /* Administrative fields for filter.
620 */
621 uint32_t hitcnts:1; /* count filter hits in TCB */
622 uint32_t prio:1; /* filter has priority over active/server */
623
624 /* Fundamental filter typing. This is the one element of filter
625 * matching that doesn't exist as a (value, mask) tuple.
626 */
627 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
628
629 /* Packet dispatch information. Ingress packets which match the
630 * filter rules will be dropped, passed to the host or switched back
631 * out as egress packets.
632 */
633 uint32_t action:2; /* drop, pass, switch */
634
635 uint32_t rpttid:1; /* report TID in RSS hash field */
636
637 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
638 uint32_t iq:10; /* ingress queue */
639
640 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
641 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
642 /* 1 => TCB contains IQ ID */
643
644 /* Switch proxy/rewrite fields. An ingress packet which matches a
645 * filter with "switch" set will be looped back out as an egress
646 * packet -- potentially with some Ethernet header rewriting.
647 */
648 uint32_t eport:2; /* egress port to switch packet out */
649 uint32_t newdmac:1; /* rewrite destination MAC address */
650 uint32_t newsmac:1; /* rewrite source MAC address */
651 uint32_t newvlan:2; /* rewrite VLAN Tag */
652 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
653 uint8_t smac[ETH_ALEN]; /* new source MAC address */
654 uint16_t vlan; /* VLAN Tag to insert */
655
656 /* Filter rule value/mask pairs.
657 */
658 struct ch_filter_tuple val;
659 struct ch_filter_tuple mask;
660};
661
662enum {
663 FILTER_PASS = 0, /* default */
664 FILTER_DROP,
665 FILTER_SWITCH
666};
667
668enum {
669 VLAN_NOCHANGE = 0, /* default */
670 VLAN_REMOVE,
671 VLAN_INSERT,
672 VLAN_REWRITE
673};
674
625ba2c2
DM		 675static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
676{
677 return readl(adap->regs + reg_addr);
678}
679
680static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
681{
682 writel(val, adap->regs + reg_addr);
683}
684
685#ifndef readq
686static inline u64 readq(const volatile void __iomem *addr)
687{
688 return readl(addr) + ((u64)readl(addr + 4) << 32);
689}
690
691static inline void writeq(u64 val, volatile void __iomem *addr)
692{
693 writel(val, addr);
694 writel(val >> 32, addr + 4);
695}
696#endif
697
698static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
699{
700 return readq(adap->regs + reg_addr);
701}
702
703static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
704{
705 writeq(val, adap->regs + reg_addr);
706}
707
708/**
709 * netdev2pinfo - return the port_info structure associated with a net_device
710 * @dev: the netdev
711 *
712 * Return the struct port_info associated with a net_device
713 */
714static inline struct port_info *netdev2pinfo(const struct net_device *dev)
715{
716 return netdev_priv(dev);
717}
718
719/**
720 * adap2pinfo - return the port_info of a port
721 * @adap: the adapter
722 * @idx: the port index
723 *
724 * Return the port_info structure for the port of the given index.
725 */
726static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
727{
728 return netdev_priv(adap->port[idx]);
729}
730
731/**
732 * netdev2adap - return the adapter structure associated with a net_device
733 * @dev: the netdev
734 *
735 * Return the struct adapter associated with a net_device
736 */
737static inline struct adapter *netdev2adap(const struct net_device *dev)
738{
739 return netdev2pinfo(dev)->adapter;
740}
741
742void t4_os_portmod_changed(const struct adapter *adap, int port_id);
743void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
744
745void *t4_alloc_mem(size_t size);
625ba2c2
DM		 746
747void t4_free_sge_resources(struct adapter *adap);
748irq_handler_t t4_intr_handler(struct adapter *adap);
749netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
750int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
751 const struct pkt_gl *gl);
752int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
753int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
754int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
755 struct net_device *dev, int intr_idx,
756 struct sge_fl *fl, rspq_handler_t hnd);
757int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
758 struct net_device *dev, struct netdev_queue *netdevq,
759 unsigned int iqid);
760int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
761 struct net_device *dev, unsigned int iqid,
762 unsigned int cmplqid);
763int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
764 struct net_device *dev, unsigned int iqid);
765irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 766int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 767void t4_sge_start(struct adapter *adap);
768void t4_sge_stop(struct adapter *adap);
3069ee9b 769extern int dbfifo_int_thresh;
625ba2c2
DM		 770
771#define for_each_port(adapter, iter) \
772 for (iter = 0; iter < (adapter)->params.nports; ++iter)
773
9a4da2cd
VP		 774static inline int is_bypass(struct adapter *adap)
775{
776 return adap->params.bypass;
777}
778
779static inline int is_bypass_device(int device)
780{
781 /* this should be set based upon device capabilities */
782 switch (device) {
783 case 0x440b:
784 case 0x440c:
785 return 1;
786 default:
787 return 0;
788 }
789}
790
625ba2c2
DM		 791static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
792{
793 return adap->params.vpd.cclk / 1000;
794}
795
796static inline unsigned int us_to_core_ticks(const struct adapter *adap,
797 unsigned int us)
798{
799 return (us * adap->params.vpd.cclk) / 1000;
800}
801
52367a76
VP		 802static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
803 unsigned int ticks)
804{
805 /* add Core Clock / 2 to round ticks to nearest uS */
806 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
807 adapter->params.vpd.cclk);
808}
809
625ba2c2
DM		 810void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
811 u32 val);
812
813int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
814 void *rpl, bool sleep_ok);
815
816static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
817 int size, void *rpl)
818{
819 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
820}
821
822static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
823 int size, void *rpl)
824{
825 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
826}
827
13ee15d3
VP		 828void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
829 unsigned int data_reg, const u32 *vals,
830 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 831void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
832 unsigned int data_reg, u32 *vals, unsigned int nregs,
833 unsigned int start_idx);
834
835struct fw_filter_wr;
836
625ba2c2
DM		 837void t4_intr_enable(struct adapter *adapter);
838void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 839int t4_slow_intr_handler(struct adapter *adapter);
840
204dc3c0 841int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 842int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
843 struct link_config *lc);
844int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
5afc8b84
VP		 845int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
846 __be32 *buf);
625ba2c2 847int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 848int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
625ba2c2 849int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
636f9d37 850unsigned int t4_flash_cfg_addr(struct adapter *adapter);
404d9e3f 851int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
625ba2c2
DM		 852int t4_check_fw_version(struct adapter *adapter);
853int t4_prep_adapter(struct adapter *adapter);
854int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
855void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 856int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
857 int start, int n, const u16 *rspq, unsigned int nrspq);
858int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
859 unsigned int flags);
625ba2c2
DM		 860int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
861int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
862 u64 *parity);
863
864void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 865void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
636f9d37
VP		 866void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
867 unsigned int mask, unsigned int val);
625ba2c2
DM		 868void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
869 struct tp_tcp_stats *v6);
870void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
871 const unsigned short *alpha, const unsigned short *beta);
872
f2b7e78d
VP		 873void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
874
625ba2c2
DM		 875void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
876 const u8 *addr);
877int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
878 u64 mask0, u64 mask1, unsigned int crc, bool enable);
879
880int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
881 enum dev_master master, enum dev_state *state);
882int t4_fw_bye(struct adapter *adap, unsigned int mbox);
883int t4_early_init(struct adapter *adap, unsigned int mbox);
884int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
26f7cbc0
VP		 885int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
886int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
887int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
888 const u8 *fw_data, unsigned int size, int force);
636f9d37
VP		 889int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
890 unsigned int mtype, unsigned int maddr,
891 u32 *finiver, u32 *finicsum, u32 *cfcsum);
892int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
893 unsigned int cache_line_size);
894int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 895int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
896 unsigned int vf, unsigned int nparams, const u32 *params,
897 u32 *val);
898int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
899 unsigned int vf, unsigned int nparams, const u32 *params,
900 const u32 *val);
901int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
902 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
903 unsigned int rxqi, unsigned int rxq, unsigned int tc,
904 unsigned int vi, unsigned int cmask, unsigned int pmask,
905 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
906int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
907 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
908 unsigned int *rss_size);
625ba2c2 909int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 910 int mtu, int promisc, int all_multi, int bcast, int vlanex,
911 bool sleep_ok);
625ba2c2
DM		 912int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
913 unsigned int viid, bool free, unsigned int naddr,
914 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
915int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
916 int idx, const u8 *addr, bool persist, bool add_smt);
917int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
918 bool ucast, u64 vec, bool sleep_ok);
919int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
920 bool rx_en, bool tx_en);
921int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
922 unsigned int nblinks);
923int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
924 unsigned int mmd, unsigned int reg, u16 *valp);
925int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
926 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 927int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
928 unsigned int vf, unsigned int iqtype, unsigned int iqid,
929 unsigned int fl0id, unsigned int fl1id);
930int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
931 unsigned int vf, unsigned int eqid);
932int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
933 unsigned int vf, unsigned int eqid);
934int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
935 unsigned int vf, unsigned int eqid);
936int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 937void t4_db_full(struct adapter *adapter);
938void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 939int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len);
940int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
941 u32 addr, u32 val);
625ba2c2 942#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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