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Merge branch 'sfc-next'
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
625ba2c2
DM		 49#include <asm/io.h>
50#include "cxgb4_uld.h"
625ba2c2 51
3069ee9b
VP		 52#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
53
625ba2c2
DM		 54enum {
55 MAX_NPORTS = 4, /* max # of ports */
47d54d65 56 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
a94cd705 59 PN_LEN = 16, /* Part Number length */
625ba2c2
DM		 60};
61
812034f1
HS		 62enum {
63 T4_REGMAP_SIZE = (160 * 1024),
64 T5_REGMAP_SIZE = (332 * 1024),
65};
66
625ba2c2
DM		 67enum {
68 MEM_EDC0,
69 MEM_EDC1,
2422d9a3
SR		 70 MEM_MC,
71 MEM_MC0 = MEM_MC,
72 MEM_MC1
625ba2c2
DM		 73};
74
3069ee9b 75enum {
3eb4afbf
VP		 76 MEMWIN0_APERTURE = 2048,
77 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 78 MEMWIN1_APERTURE = 32768,
79 MEMWIN1_BASE = 0x28000,
2422d9a3 80 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 81 MEMWIN2_APERTURE = 65536,
82 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 83 MEMWIN2_APERTURE_T5 = 131072,
84 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 85};
86
625ba2c2
DM		 87enum dev_master {
88 MASTER_CANT,
89 MASTER_MAY,
90 MASTER_MUST
91};
92
93enum dev_state {
94 DEV_STATE_UNINIT,
95 DEV_STATE_INIT,
96 DEV_STATE_ERR
97};
98
99enum {
100 PAUSE_RX = 1 << 0,
101 PAUSE_TX = 1 << 1,
102 PAUSE_AUTONEG = 1 << 2
103};
104
105struct port_stats {
106 u64 tx_octets; /* total # of octets in good frames */
107 u64 tx_frames; /* all good frames */
108 u64 tx_bcast_frames; /* all broadcast frames */
109 u64 tx_mcast_frames; /* all multicast frames */
110 u64 tx_ucast_frames; /* all unicast frames */
111 u64 tx_error_frames; /* all error frames */
112
113 u64 tx_frames_64; /* # of Tx frames in a particular range */
114 u64 tx_frames_65_127;
115 u64 tx_frames_128_255;
116 u64 tx_frames_256_511;
117 u64 tx_frames_512_1023;
118 u64 tx_frames_1024_1518;
119 u64 tx_frames_1519_max;
120
121 u64 tx_drop; /* # of dropped Tx frames */
122 u64 tx_pause; /* # of transmitted pause frames */
123 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
124 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
125 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
126 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
127 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
128 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
129 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
130 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
131
132 u64 rx_octets; /* total # of octets in good frames */
133 u64 rx_frames; /* all good frames */
134 u64 rx_bcast_frames; /* all broadcast frames */
135 u64 rx_mcast_frames; /* all multicast frames */
136 u64 rx_ucast_frames; /* all unicast frames */
137 u64 rx_too_long; /* # of frames exceeding MTU */
138 u64 rx_jabber; /* # of jabber frames */
139 u64 rx_fcs_err; /* # of received frames with bad FCS */
140 u64 rx_len_err; /* # of received frames with length error */
141 u64 rx_symbol_err; /* symbol errors */
142 u64 rx_runt; /* # of short frames */
143
144 u64 rx_frames_64; /* # of Rx frames in a particular range */
145 u64 rx_frames_65_127;
146 u64 rx_frames_128_255;
147 u64 rx_frames_256_511;
148 u64 rx_frames_512_1023;
149 u64 rx_frames_1024_1518;
150 u64 rx_frames_1519_max;
151
152 u64 rx_pause; /* # of received pause frames */
153 u64 rx_ppp0; /* # of received PPP prio 0 frames */
154 u64 rx_ppp1; /* # of received PPP prio 1 frames */
155 u64 rx_ppp2; /* # of received PPP prio 2 frames */
156 u64 rx_ppp3; /* # of received PPP prio 3 frames */
157 u64 rx_ppp4; /* # of received PPP prio 4 frames */
158 u64 rx_ppp5; /* # of received PPP prio 5 frames */
159 u64 rx_ppp6; /* # of received PPP prio 6 frames */
160 u64 rx_ppp7; /* # of received PPP prio 7 frames */
161
162 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
163 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
164 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
165 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
166 u64 rx_trunc0; /* buffer-group 0 truncated packets */
167 u64 rx_trunc1; /* buffer-group 1 truncated packets */
168 u64 rx_trunc2; /* buffer-group 2 truncated packets */
169 u64 rx_trunc3; /* buffer-group 3 truncated packets */
170};
171
172struct lb_port_stats {
173 u64 octets;
174 u64 frames;
175 u64 bcast_frames;
176 u64 mcast_frames;
177 u64 ucast_frames;
178 u64 error_frames;
179
180 u64 frames_64;
181 u64 frames_65_127;
182 u64 frames_128_255;
183 u64 frames_256_511;
184 u64 frames_512_1023;
185 u64 frames_1024_1518;
186 u64 frames_1519_max;
187
188 u64 drop;
189
190 u64 ovflow0;
191 u64 ovflow1;
192 u64 ovflow2;
193 u64 ovflow3;
194 u64 trunc0;
195 u64 trunc1;
196 u64 trunc2;
197 u64 trunc3;
198};
199
200struct tp_tcp_stats {
201 u32 tcpOutRsts;
202 u64 tcpInSegs;
203 u64 tcpOutSegs;
204 u64 tcpRetransSegs;
205};
206
207struct tp_err_stats {
208 u32 macInErrs[4];
209 u32 hdrInErrs[4];
210 u32 tcpInErrs[4];
211 u32 tnlCongDrops[4];
212 u32 ofldChanDrops[4];
213 u32 tnlTxDrops[4];
214 u32 ofldVlanDrops[4];
215 u32 tcp6InErrs[4];
216 u32 ofldNoNeigh;
217 u32 ofldCongDefer;
218};
219
e85c9a7a
HS		 220struct sge_params {
221 u32 hps; /* host page size for our PF/VF */
222 u32 eq_qpp; /* egress queues/page for our PF/VF */
223 u32 iq_qpp; /* egress queues/page for our PF/VF */
224};
225
625ba2c2
DM		 226struct tp_params {
227 unsigned int ntxchan; /* # of Tx channels */
228 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 229 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 230 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
231 /* channel map */
636f9d37
VP		 232
233 uint32_t dack_re; /* DACK timer resolution */
234 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 235
236 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
237 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
238
239 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
240 * subset of the set of fields which may be present in the Compressed
241 * Filter Tuple portion of filters and TCP TCB connections. The
242 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
243 * Since a variable number of fields may or may not be present, their
244 * shifted field positions within the Compressed Filter Tuple may
245 * vary, or not even be present if the field isn't selected in
246 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
247 * places we store their offsets here, or a -1 if the field isn't
248 * present.
249 */
250 int vlan_shift;
251 int vnic_shift;
252 int port_shift;
253 int protocol_shift;
625ba2c2
DM		 254};
255
256struct vpd_params {
257 unsigned int cclk;
258 u8 ec[EC_LEN + 1];
259 u8 sn[SERNUM_LEN + 1];
260 u8 id[ID_LEN + 1];
a94cd705 261 u8 pn[PN_LEN + 1];
625ba2c2
DM		 262};
263
264struct pci_params {
265 unsigned char speed;
266 unsigned char width;
267};
268
d14807dd
HS		 269#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
270#define CHELSIO_CHIP_FPGA 0x100
271#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
272#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
273
274#define CHELSIO_T4 0x4
275#define CHELSIO_T5 0x5
276
277enum chip_type {
278 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
279 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
280 T4_FIRST_REV = T4_A1,
281 T4_LAST_REV = T4_A2,
282
283 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
284 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
285 T5_FIRST_REV = T5_A0,
286 T5_LAST_REV = T5_A1,
287};
288
49aa284f
HS		 289struct devlog_params {
290 u32 memtype; /* which memory (EDC0, EDC1, MC) */
291 u32 start; /* start of log in firmware memory */
292 u32 size; /* size of log */
293};
294
625ba2c2 295struct adapter_params {
e85c9a7a 296 struct sge_params sge;
625ba2c2
DM		 297 struct tp_params tp;
298 struct vpd_params vpd;
299 struct pci_params pci;
49aa284f
HS		 300 struct devlog_params devlog;
301 enum pcie_memwin drv_memwin;
625ba2c2 302
f1ff24aa
HS		 303 unsigned int cim_la_size;
304
900a6596
DM		 305 unsigned int sf_size; /* serial flash size in bytes */
306 unsigned int sf_nsec; /* # of flash sectors */
307 unsigned int sf_fw_start; /* start of FW image in flash */
308
625ba2c2
DM		 309 unsigned int fw_vers;
310 unsigned int tp_vers;
311 u8 api_vers[7];
312
313 unsigned short mtus[NMTUS];
314 unsigned short a_wnd[NCCTRL_WIN];
315 unsigned short b_wnd[NCCTRL_WIN];
316
317 unsigned char nports; /* # of ethernet ports */
318 unsigned char portvec;
d14807dd 319 enum chip_type chip; /* chip code */
625ba2c2
DM		 320 unsigned char offload;
321
9a4da2cd
VP		 322 unsigned char bypass;
323
625ba2c2 324 unsigned int ofldq_wr_cred;
1ac0f095 325 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763
HS		 326
327 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
328 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 329};
330
a3bfb617
HS		 331/* State needed to monitor the forward progress of SGE Ingress DMA activities
332 * and possible hangs.
333 */
334struct sge_idma_monitor_state {
335 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
336 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
337 unsigned int idma_state[2]; /* IDMA Hang detect state */
338 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
339 unsigned int idma_warn[2]; /* time to warning in HZ */
340};
341
16e47624
HS		 342#include "t4fw_api.h"
343
344#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 345 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
346 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
347 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
348 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 349#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
350
351struct fw_info {
352 u8 chip;
353 char *fs_name;
354 char *fw_mod_name;
355 struct fw_hdr fw_hdr;
356};
357
358
625ba2c2
DM		 359struct trace_params {
360 u32 data[TRACE_LEN / 4];
361 u32 mask[TRACE_LEN / 4];
362 unsigned short snap_len;
363 unsigned short min_len;
364 unsigned char skip_ofst;
365 unsigned char skip_len;
366 unsigned char invert;
367 unsigned char port;
368};
369
370struct link_config {
371 unsigned short supported; /* link capabilities */
372 unsigned short advertising; /* advertised capabilities */
373 unsigned short requested_speed; /* speed user has requested */
374 unsigned short speed; /* actual link speed */
375 unsigned char requested_fc; /* flow control user has requested */
376 unsigned char fc; /* actual link flow control */
377 unsigned char autoneg; /* autonegotiating? */
378 unsigned char link_ok; /* link up? */
379};
380
e2ac9628 381#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 382
383enum {
384 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
385 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
386 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
387 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 388 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
cf38be6d 389 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
625ba2c2
DM		 390};
391
812034f1
HS		 392enum {
393 MAX_TXQ_ENTRIES = 16384,
394 MAX_CTRL_TXQ_ENTRIES = 1024,
395 MAX_RSPQ_ENTRIES = 16384,
396 MAX_RX_BUFFERS = 16384,
397 MIN_TXQ_ENTRIES = 32,
398 MIN_CTRL_TXQ_ENTRIES = 32,
399 MIN_RSPQ_ENTRIES = 128,
400 MIN_FL_ENTRIES = 16
401};
402
625ba2c2 403enum {
cf38be6d
HS		 404 INGQ_EXTRAS = 2, /* firmware event queue and */
405 /* forwarded interrupts */
cf38be6d
HS		 406 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
407 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 408};
409
410struct adapter;
625ba2c2
DM		 411struct sge_rspq;
412
688848b1
AB		 413#include "cxgb4_dcb.h"
414
76fed8a9
VP		 415#ifdef CONFIG_CHELSIO_T4_FCOE
416#include "cxgb4_fcoe.h"
417#endif /* CONFIG_CHELSIO_T4_FCOE */
418
625ba2c2
DM		 419struct port_info {
420 struct adapter *adapter;
625ba2c2
DM		 421 u16 viid;
422 s16 xact_addr_filt; /* index of exact MAC address filter */
423 u16 rss_size; /* size of VI's RSS table slice */
424 s8 mdio_addr;
40e9de4b 425 enum fw_port_type port_type;
625ba2c2
DM		 426 u8 mod_type;
427 u8 port_id;
428 u8 tx_chan;
429 u8 lport; /* associated offload logical port */
625ba2c2
DM		 430 u8 nqsets; /* # of qsets */
431 u8 first_qset; /* index of first qset */
f796564a 432 u8 rss_mode;
625ba2c2 433 struct link_config link_cfg;
671b0060 434 u16 *rss;
688848b1
AB		 435#ifdef CONFIG_CHELSIO_T4_DCB
436 struct port_dcb_info dcb; /* Data Center Bridging support */
437#endif
76fed8a9
VP		 438#ifdef CONFIG_CHELSIO_T4_FCOE
439 struct cxgb_fcoe fcoe;
440#endif /* CONFIG_CHELSIO_T4_FCOE */
625ba2c2
DM		 441};
442
625ba2c2
DM		 443struct dentry;
444struct work_struct;
445
446enum { /* adapter flags */
447 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 448 DEV_ENABLED = (1 << 1),
449 USING_MSI = (1 << 2),
450 USING_MSIX = (1 << 3),
625ba2c2 451 FW_OK = (1 << 4),
13ee15d3 452 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 453 USING_SOFT_PARAMS = (1 << 6),
454 MASTER_PF = (1 << 7),
455 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 456};
457
458struct rx_sw_desc;
459
460struct sge_fl { /* SGE free-buffer queue state */
461 unsigned int avail; /* # of available Rx buffers */
462 unsigned int pend_cred; /* new buffers since last FL DB ring */
463 unsigned int cidx; /* consumer index */
464 unsigned int pidx; /* producer index */
465 unsigned long alloc_failed; /* # of times buffer allocation failed */
466 unsigned long large_alloc_failed;
467 unsigned long starving;
468 /* RO fields */
469 unsigned int cntxt_id; /* SGE context id for the free list */
470 unsigned int size; /* capacity of free list */
471 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
472 __be64 *desc; /* address of HW Rx descriptor ring */
473 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 474 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
475 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 476};
477
478/* A packet gather list */
479struct pkt_gl {
e91b0f24 480 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 481 void *va; /* virtual address of first byte */
482 unsigned int nfrags; /* # of fragments */
483 unsigned int tot_len; /* total length of fragments */
484};
485
486typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
487 const struct pkt_gl *gl);
488
489struct sge_rspq { /* state for an SGE response queue */
490 struct napi_struct napi;
491 const __be64 *cur_desc; /* current descriptor in queue */
492 unsigned int cidx; /* consumer index */
493 u8 gen; /* current generation bit */
494 u8 intr_params; /* interrupt holdoff parameters */
495 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 496 u8 adaptive_rx;
625ba2c2
DM		 497 u8 pktcnt_idx; /* interrupt packet threshold */
498 u8 uld; /* ULD handling this queue */
499 u8 idx; /* queue index within its group */
500 int offset; /* offset into current Rx buffer */
501 u16 cntxt_id; /* SGE context id for the response q */
502 u16 abs_id; /* absolute SGE id for the response q */
503 __be64 *desc; /* address of HW response ring */
504 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 505 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
506 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 507 unsigned int iqe_len; /* entry size */
508 unsigned int size; /* capacity of response queue */
509 struct adapter *adap;
510 struct net_device *netdev; /* associated net device */
511 rspq_handler_t handler;
3a336cb1
HS		 512#ifdef CONFIG_NET_RX_BUSY_POLL
513#define CXGB_POLL_STATE_IDLE 0
514#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
515#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
516#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
517#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
518#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
519 CXGB_POLL_STATE_POLL_YIELD)
520#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
521 CXGB_POLL_STATE_POLL)
522#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
523 CXGB_POLL_STATE_POLL_YIELD)
524 unsigned int bpoll_state;
525 spinlock_t bpoll_lock; /* lock for busy poll */
526#endif /* CONFIG_NET_RX_BUSY_POLL */
527
625ba2c2
DM		 528};
529
530struct sge_eth_stats { /* Ethernet queue statistics */
531 unsigned long pkts; /* # of ethernet packets */
532 unsigned long lro_pkts; /* # of LRO super packets */
533 unsigned long lro_merged; /* # of wire packets merged by LRO */
534 unsigned long rx_cso; /* # of Rx checksum offloads */
535 unsigned long vlan_ex; /* # of Rx VLAN extractions */
536 unsigned long rx_drops; /* # of packets dropped due to no mem */
537};
538
539struct sge_eth_rxq { /* SW Ethernet Rx queue */
540 struct sge_rspq rspq;
541 struct sge_fl fl;
542 struct sge_eth_stats stats;
543} ____cacheline_aligned_in_smp;
544
545struct sge_ofld_stats { /* offload queue statistics */
546 unsigned long pkts; /* # of packets */
547 unsigned long imm; /* # of immediate-data packets */
548 unsigned long an; /* # of asynchronous notifications */
549 unsigned long nomem; /* # of responses deferred due to no mem */
550};
551
552struct sge_ofld_rxq { /* SW offload Rx queue */
553 struct sge_rspq rspq;
554 struct sge_fl fl;
555 struct sge_ofld_stats stats;
556} ____cacheline_aligned_in_smp;
557
558struct tx_desc {
559 __be64 flit[8];
560};
561
562struct tx_sw_desc;
563
564struct sge_txq {
565 unsigned int in_use; /* # of in-use Tx descriptors */
566 unsigned int size; /* # of descriptors */
567 unsigned int cidx; /* SW consumer index */
568 unsigned int pidx; /* producer index */
569 unsigned long stops; /* # of times q has been stopped */
570 unsigned long restarts; /* # of queue restarts */
571 unsigned int cntxt_id; /* SGE context id for the Tx q */
572 struct tx_desc *desc; /* address of HW Tx descriptor ring */
573 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
574 struct sge_qstat *stat; /* queue status entry */
575 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 576 spinlock_t db_lock;
577 int db_disabled;
578 unsigned short db_pidx;
05eb2389 579 unsigned short db_pidx_inc;
df64e4d3
HS		 580 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
581 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 582};
583
584struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
585 struct sge_txq q;
586 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 587#ifdef CONFIG_CHELSIO_T4_DCB
588 u8 dcb_prio; /* DCB Priority bound to queue */
589#endif
625ba2c2
DM		 590 unsigned long tso; /* # of TSO requests */
591 unsigned long tx_cso; /* # of Tx checksum offloads */
592 unsigned long vlan_ins; /* # of Tx VLAN insertions */
593 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
594} ____cacheline_aligned_in_smp;
595
596struct sge_ofld_txq { /* state for an SGE offload Tx queue */
597 struct sge_txq q;
598 struct adapter *adap;
599 struct sk_buff_head sendq; /* list of backpressured packets */
600 struct tasklet_struct qresume_tsk; /* restarts the queue */
601 u8 full; /* the Tx ring is full */
602 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
603} ____cacheline_aligned_in_smp;
604
605struct sge_ctrl_txq { /* state for an SGE control Tx queue */
606 struct sge_txq q;
607 struct adapter *adap;
608 struct sk_buff_head sendq; /* list of backpressured packets */
609 struct tasklet_struct qresume_tsk; /* restarts the queue */
610 u8 full; /* the Tx ring is full */
611} ____cacheline_aligned_in_smp;
612
613struct sge {
614 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
615 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
616 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
617
618 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
619 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
620 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 621 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2
DM		 622 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
623
624 struct sge_rspq intrq ____cacheline_aligned_in_smp;
625 spinlock_t intrq_lock;
626
627 u16 max_ethqsets; /* # of available Ethernet queue sets */
628 u16 ethqsets; /* # of active Ethernet queue sets */
629 u16 ethtxq_rover; /* Tx queue to clean up next */
630 u16 ofldqsets; /* # of active offload queue sets */
631 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 632 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
625ba2c2 633 u16 ofld_rxq[MAX_OFLD_QSETS];
f36e58e5
HS		 634 u16 rdma_rxq[MAX_RDMA_QUEUES];
635 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 636 u16 timer_val[SGE_NTIMERS];
637 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 638 u32 fl_pg_order; /* large page allocation size */
639 u32 stat_len; /* length of status page at ring end */
640 u32 pktshift; /* padding between CPL & packet data */
641 u32 fl_align; /* response queue message alignment */
642 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 643
a3bfb617 644 struct sge_idma_monitor_state idma_monitor;
e46dab4d 645 unsigned int egr_start;
4b8e27a8 646 unsigned int egr_sz;
e46dab4d 647 unsigned int ingr_start;
4b8e27a8
HS		 648 unsigned int ingr_sz;
649 void **egr_map; /* qid->queue egress queue map */
650 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
651 unsigned long *starving_fl;
652 unsigned long *txq_maperr;
625ba2c2
DM		 653 struct timer_list rx_timer; /* refills starving FLs */
654 struct timer_list tx_timer; /* checks Tx queues */
655};
656
657#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
658#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
659#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 660#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 661
662struct l2t_data;
663
2422d9a3
SR		 664#ifdef CONFIG_PCI_IOV
665
7d6727cf
SR		 666/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
667 * Configuration initialization for T5 only has SR-IOV functionality enabled
668 * on PF0-3 in order to simplify everything.
2422d9a3 669 */
7d6727cf 670#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 671
672#endif
673
625ba2c2
DM		 674struct adapter {
675 void __iomem *regs;
22adfe0a 676 void __iomem *bar2;
0abfd152 677 u32 t4_bar0;
625ba2c2
DM		 678 struct pci_dev *pdev;
679 struct device *pdev_dev;
3069ee9b 680 unsigned int mbox;
060e0c75
DM		 681 unsigned int fn;
682 unsigned int flags;
2422d9a3 683 enum chip_type chip;
625ba2c2 684
625ba2c2
DM		 685 int msg_enable;
686
687 struct adapter_params params;
688 struct cxgb4_virt_res vres;
689 unsigned int swintr;
690
691 unsigned int wol;
692
693 struct {
694 unsigned short vec;
8cd18ac4 695 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 696 } msix_info[MAX_INGQ + 1];
697
698 struct sge sge;
699
700 struct net_device *port[MAX_NPORTS];
701 u8 chan_map[NCHAN]; /* channel -> port map */
702
793dad94 703 u32 filter_mode;
636f9d37
VP		 704 unsigned int l2t_start;
705 unsigned int l2t_end;
625ba2c2 706 struct l2t_data *l2t;
b5a02f50
AB		 707 unsigned int clipt_start;
708 unsigned int clipt_end;
709 struct clip_tbl *clipt;
625ba2c2
DM		 710 void *uld_handle[CXGB4_ULD_MAX];
711 struct list_head list_node;
01bcca68 712 struct list_head rcu_node;
625ba2c2
DM		 713
714 struct tid_info tids;
715 void **tid_release_head;
716 spinlock_t tid_release_lock;
29aaee65 717 struct workqueue_struct *workq;
625ba2c2 718 struct work_struct tid_release_task;
881806bc
VP		 719 struct work_struct db_full_task;
720 struct work_struct db_drop_task;
625ba2c2
DM		 721 bool tid_release_task_busy;
722
723 struct dentry *debugfs_root;
724
725 spinlock_t stats_lock;
fc5ab020 726 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 727};
728
f2b7e78d
VP		 729/* Defined bit width of user definable filter tuples
730 */
731#define ETHTYPE_BITWIDTH 16
732#define FRAG_BITWIDTH 1
733#define MACIDX_BITWIDTH 9
734#define FCOE_BITWIDTH 1
735#define IPORT_BITWIDTH 3
736#define MATCHTYPE_BITWIDTH 3
737#define PROTO_BITWIDTH 8
738#define TOS_BITWIDTH 8
739#define PF_BITWIDTH 8
740#define VF_BITWIDTH 8
741#define IVLAN_BITWIDTH 16
742#define OVLAN_BITWIDTH 16
743
744/* Filter matching rules. These consist of a set of ingress packet field
745 * (value, mask) tuples. The associated ingress packet field matches the
746 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
747 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
748 * matches an ingress packet when all of the individual individual field
749 * matching rules are true.
750 *
751 * Partial field masks are always valid, however, while it may be easy to
752 * understand their meanings for some fields (e.g. IP address to match a
753 * subnet), for others making sensible partial masks is less intuitive (e.g.
754 * MPS match type) ...
755 *
756 * Most of the following data structures are modeled on T4 capabilities.
757 * Drivers for earlier chips use the subsets which make sense for those chips.
758 * We really need to come up with a hardware-independent mechanism to
759 * represent hardware filter capabilities ...
760 */
761struct ch_filter_tuple {
762 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
763 * register selects which of these fields will participate in the
764 * filter match rules -- up to a maximum of 36 bits. Because
765 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
766 * set of fields.
767 */
768 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
769 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
770 uint32_t ivlan_vld:1; /* inner VLAN valid */
771 uint32_t ovlan_vld:1; /* outer VLAN valid */
772 uint32_t pfvf_vld:1; /* PF/VF valid */
773 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
774 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
775 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
776 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
777 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
778 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
779 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
780 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
781 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
782 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
783
784 /* Uncompressed header matching field rules. These are always
785 * available for field rules.
786 */
787 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
788 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
789 uint16_t lport; /* local port */
790 uint16_t fport; /* foreign port */
791};
792
793/* A filter ioctl command.
794 */
795struct ch_filter_specification {
796 /* Administrative fields for filter.
797 */
798 uint32_t hitcnts:1; /* count filter hits in TCB */
799 uint32_t prio:1; /* filter has priority over active/server */
800
801 /* Fundamental filter typing. This is the one element of filter
802 * matching that doesn't exist as a (value, mask) tuple.
803 */
804 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
805
806 /* Packet dispatch information. Ingress packets which match the
807 * filter rules will be dropped, passed to the host or switched back
808 * out as egress packets.
809 */
810 uint32_t action:2; /* drop, pass, switch */
811
812 uint32_t rpttid:1; /* report TID in RSS hash field */
813
814 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
815 uint32_t iq:10; /* ingress queue */
816
817 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
818 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
819 /* 1 => TCB contains IQ ID */
820
821 /* Switch proxy/rewrite fields. An ingress packet which matches a
822 * filter with "switch" set will be looped back out as an egress
823 * packet -- potentially with some Ethernet header rewriting.
824 */
825 uint32_t eport:2; /* egress port to switch packet out */
826 uint32_t newdmac:1; /* rewrite destination MAC address */
827 uint32_t newsmac:1; /* rewrite source MAC address */
828 uint32_t newvlan:2; /* rewrite VLAN Tag */
829 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
830 uint8_t smac[ETH_ALEN]; /* new source MAC address */
831 uint16_t vlan; /* VLAN Tag to insert */
832
833 /* Filter rule value/mask pairs.
834 */
835 struct ch_filter_tuple val;
836 struct ch_filter_tuple mask;
837};
838
839enum {
840 FILTER_PASS = 0, /* default */
841 FILTER_DROP,
842 FILTER_SWITCH
843};
844
845enum {
846 VLAN_NOCHANGE = 0, /* default */
847 VLAN_REMOVE,
848 VLAN_INSERT,
849 VLAN_REWRITE
850};
851
2422d9a3
SR		 852static inline int is_t5(enum chip_type chip)
853{
d14807dd 854 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
2422d9a3
SR		 855}
856
857static inline int is_t4(enum chip_type chip)
858{
d14807dd 859 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
2422d9a3
SR		 860}
861
625ba2c2
DM		 862static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
863{
864 return readl(adap->regs + reg_addr);
865}
866
867static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
868{
869 writel(val, adap->regs + reg_addr);
870}
871
872#ifndef readq
873static inline u64 readq(const volatile void __iomem *addr)
874{
875 return readl(addr) + ((u64)readl(addr + 4) << 32);
876}
877
878static inline void writeq(u64 val, volatile void __iomem *addr)
879{
880 writel(val, addr);
881 writel(val >> 32, addr + 4);
882}
883#endif
884
885static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
886{
887 return readq(adap->regs + reg_addr);
888}
889
890static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
891{
892 writeq(val, adap->regs + reg_addr);
893}
894
895/**
896 * netdev2pinfo - return the port_info structure associated with a net_device
897 * @dev: the netdev
898 *
899 * Return the struct port_info associated with a net_device
900 */
901static inline struct port_info *netdev2pinfo(const struct net_device *dev)
902{
903 return netdev_priv(dev);
904}
905
906/**
907 * adap2pinfo - return the port_info of a port
908 * @adap: the adapter
909 * @idx: the port index
910 *
911 * Return the port_info structure for the port of the given index.
912 */
913static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
914{
915 return netdev_priv(adap->port[idx]);
916}
917
918/**
919 * netdev2adap - return the adapter structure associated with a net_device
920 * @dev: the netdev
921 *
922 * Return the struct adapter associated with a net_device
923 */
924static inline struct adapter *netdev2adap(const struct net_device *dev)
925{
926 return netdev2pinfo(dev)->adapter;
927}
928
3a336cb1
HS		 929#ifdef CONFIG_NET_RX_BUSY_POLL
930static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
931{
932 spin_lock_init(&q->bpoll_lock);
933 q->bpoll_state = CXGB_POLL_STATE_IDLE;
934}
935
936static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
937{
938 bool rc = true;
939
940 spin_lock(&q->bpoll_lock);
941 if (q->bpoll_state & CXGB_POLL_LOCKED) {
942 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
943 rc = false;
944 } else {
945 q->bpoll_state = CXGB_POLL_STATE_NAPI;
946 }
947 spin_unlock(&q->bpoll_lock);
948 return rc;
949}
950
951static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
952{
953 bool rc = false;
954
955 spin_lock(&q->bpoll_lock);
956 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
957 rc = true;
958 q->bpoll_state = CXGB_POLL_STATE_IDLE;
959 spin_unlock(&q->bpoll_lock);
960 return rc;
961}
962
963static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
964{
965 bool rc = true;
966
967 spin_lock_bh(&q->bpoll_lock);
968 if (q->bpoll_state & CXGB_POLL_LOCKED) {
969 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
970 rc = false;
971 } else {
972 q->bpoll_state |= CXGB_POLL_STATE_POLL;
973 }
974 spin_unlock_bh(&q->bpoll_lock);
975 return rc;
976}
977
978static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
979{
980 bool rc = false;
981
982 spin_lock_bh(&q->bpoll_lock);
983 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
984 rc = true;
985 q->bpoll_state = CXGB_POLL_STATE_IDLE;
986 spin_unlock_bh(&q->bpoll_lock);
987 return rc;
988}
989
990static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
991{
992 return q->bpoll_state & CXGB_POLL_USER_PEND;
993}
994#else
995static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
996{
997}
998
999static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1000{
1001 return true;
1002}
1003
1004static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1005{
1006 return false;
1007}
1008
1009static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1010{
1011 return false;
1012}
1013
1014static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1015{
1016 return false;
1017}
1018
1019static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1020{
1021 return false;
1022}
1023#endif /* CONFIG_NET_RX_BUSY_POLL */
1024
812034f1
HS		 1025/* Return a version number to identify the type of adapter. The scheme is:
1026 * - bits 0..9: chip version
1027 * - bits 10..15: chip revision
1028 * - bits 16..23: register dump version
1029 */
1030static inline unsigned int mk_adap_vers(struct adapter *ap)
1031{
1032 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1033 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1034}
1035
1036/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1037static inline unsigned int qtimer_val(const struct adapter *adap,
1038 const struct sge_rspq *q)
1039{
1040 unsigned int idx = q->intr_params >> 1;
1041
1042 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1043}
1044
1045/* driver version & name used for ethtool_drvinfo */
1046extern char cxgb4_driver_name[];
1047extern const char cxgb4_driver_version[];
1048
625ba2c2
DM		 1049void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1050void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1051
1052void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1053
1054void t4_free_sge_resources(struct adapter *adap);
5fa76694 1055void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1056irq_handler_t t4_intr_handler(struct adapter *adap);
1057netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1058int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1059 const struct pkt_gl *gl);
1060int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1061int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1062int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1063 struct net_device *dev, int intr_idx,
145ef8a5 1064 struct sge_fl *fl, rspq_handler_t hnd, int cong);
625ba2c2
DM		 1065int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1066 struct net_device *dev, struct netdev_queue *netdevq,
1067 unsigned int iqid);
1068int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1069 struct net_device *dev, unsigned int iqid,
1070 unsigned int cmplqid);
1071int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1072 struct net_device *dev, unsigned int iqid);
1073irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1074int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1075void t4_sge_start(struct adapter *adap);
1076void t4_sge_stop(struct adapter *adap);
3a336cb1 1077int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1078int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1079 unsigned int cnt);
1080void cxgb4_set_ethtool_ops(struct net_device *netdev);
1081int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1082extern int dbfifo_int_thresh;
625ba2c2
DM		 1083
1084#define for_each_port(adapter, iter) \
1085 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1086
9a4da2cd
VP		 1087static inline int is_bypass(struct adapter *adap)
1088{
1089 return adap->params.bypass;
1090}
1091
1092static inline int is_bypass_device(int device)
1093{
1094 /* this should be set based upon device capabilities */
1095 switch (device) {
1096 case 0x440b:
1097 case 0x440c:
1098 return 1;
1099 default:
1100 return 0;
1101 }
1102}
1103
625ba2c2
DM		 1104static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1105{
1106 return adap->params.vpd.cclk / 1000;
1107}
1108
1109static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1110 unsigned int us)
1111{
1112 return (us * adap->params.vpd.cclk) / 1000;
1113}
1114
52367a76
VP		 1115static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1116 unsigned int ticks)
1117{
1118 /* add Core Clock / 2 to round ticks to nearest uS */
1119 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1120 adapter->params.vpd.cclk);
1121}
1122
625ba2c2
DM		 1123void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1124 u32 val);
1125
1126int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1127 void *rpl, bool sleep_ok);
1128
1129static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1130 int size, void *rpl)
1131{
1132 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1133}
1134
1135static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1136 int size, void *rpl)
1137{
1138 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1139}
1140
13ee15d3
VP		 1141void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1142 unsigned int data_reg, const u32 *vals,
1143 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1144void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1145 unsigned int data_reg, u32 *vals, unsigned int nregs,
1146 unsigned int start_idx);
0abfd152 1147void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1148
1149struct fw_filter_wr;
1150
625ba2c2
DM		 1151void t4_intr_enable(struct adapter *adapter);
1152void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1153int t4_slow_intr_handler(struct adapter *adapter);
1154
8203b509 1155int t4_wait_dev_ready(void __iomem *regs);
625ba2c2
DM		 1156int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1157 struct link_config *lc);
1158int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020
HS		 1159
1160#define T4_MEMORY_WRITE 0
1161#define T4_MEMORY_READ 1
1162int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1163 void *buf, int dir);
fc5ab020
HS		 1164static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1165 u32 len, __be32 *buf)
1166{
1167 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1168}
1169
812034f1
HS		 1170unsigned int t4_get_regs_len(struct adapter *adapter);
1171void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1172
625ba2c2 1173int t4_seeprom_wp(struct adapter *adapter, bool enable);
636f9d37 1174int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1175int t4_read_flash(struct adapter *adapter, unsigned int addr,
1176 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1177int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
49216c1c 1178int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1179int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1180 const u8 *fw_data, unsigned int size, int force);
636f9d37 1181unsigned int t4_flash_cfg_addr(struct adapter *adapter);
16e47624
HS		 1182int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1183int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1184int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1185int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1186 const u8 *fw_data, unsigned int fw_size,
1187 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1188int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1189
1190enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
dd0bcc0b 1191int cxgb4_t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1192 unsigned int qid,
1193 enum t4_bar2_qtype qtype,
1194 u64 *pbar2_qoffset,
1195 unsigned int *pbar2_qid);
1196
dc9daab2
HS		 1197unsigned int qtimer_val(const struct adapter *adap,
1198 const struct sge_rspq *q);
ae469b68
HS		 1199
1200int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1201int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1202int t4_init_tp_params(struct adapter *adap);
1203int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1204int t4_init_rss_mode(struct adapter *adap, int mbox);
625ba2c2
DM		 1205int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1206void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1207int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1208 int start, int n, const u16 *rspq, unsigned int nrspq);
1209int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1210 unsigned int flags);
c035e183
HS		 1211int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1212 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1213int t4_read_rss(struct adapter *adapter, u16 *entries);
1214void t4_read_rss_key(struct adapter *adapter, u32 *key);
1215void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1216void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1217 u32 *valp);
1218void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1219 u32 *vfl, u32 *vfh);
1220u32 t4_read_rss_pf_map(struct adapter *adapter);
1221u32 t4_read_rss_pf_mask(struct adapter *adapter);
1222
145ef8a5 1223unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1224void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1225void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1226int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1227 size_t n);
c778af7d
HS		 1228int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1229 size_t n);
f1ff24aa
HS		 1230int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1231 unsigned int *valp);
1232int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1233 const unsigned int *valp);
1234int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
74b3092c 1235void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1236const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1237void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 1238void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1239void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1240void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1241 unsigned int mask, unsigned int val);
2d277b3b 1242void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
625ba2c2
DM		 1243void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1244 struct tp_tcp_stats *v6);
1245void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1246 const unsigned short *alpha, const unsigned short *beta);
1247
797ff0f5
HS		 1248void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1249
f2b7e78d
VP		 1250void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1251
625ba2c2
DM		 1252void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1253 const u8 *addr);
1254int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1255 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1256
1257int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1258 enum dev_master master, enum dev_state *state);
1259int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1260int t4_early_init(struct adapter *adap, unsigned int mbox);
1261int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1262int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1263 unsigned int cache_line_size);
1264int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1265int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1266 unsigned int vf, unsigned int nparams, const u32 *params,
1267 u32 *val);
1268int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1269 unsigned int vf, unsigned int nparams, const u32 *params,
1270 const u32 *val);
688848b1
AB		 1271int t4_set_params_nosleep(struct adapter *adap, unsigned int mbox,
1272 unsigned int pf, unsigned int vf,
1273 unsigned int nparams, const u32 *params,
1274 const u32 *val);
625ba2c2
DM		 1275int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1276 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1277 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1278 unsigned int vi, unsigned int cmask, unsigned int pmask,
1279 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1280int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1281 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1282 unsigned int *rss_size);
625ba2c2 1283int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1284 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1285 bool sleep_ok);
625ba2c2
DM		 1286int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1287 unsigned int viid, bool free, unsigned int naddr,
1288 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1289int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1290 int idx, const u8 *addr, bool persist, bool add_smt);
1291int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1292 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1293int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1294 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1295int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1296 bool rx_en, bool tx_en);
1297int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1298 unsigned int nblinks);
1299int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1300 unsigned int mmd, unsigned int reg, u16 *valp);
1301int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1302 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 1303int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1304 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1305 unsigned int fl0id, unsigned int fl1id);
1306int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1307 unsigned int vf, unsigned int eqid);
1308int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1309 unsigned int vf, unsigned int eqid);
1310int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1311 unsigned int vf, unsigned int eqid);
1312int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1313void t4_db_full(struct adapter *adapter);
1314void t4_db_dropped(struct adapter *adapter);
8caa1e84
VP		 1315int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1316 u32 addr, u32 val);
68bce192 1317void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1318void t4_free_mem(void *addr);
a3bfb617
HS		 1319void t4_idma_monitor_init(struct adapter *adapter,
1320 struct sge_idma_monitor_state *idma);
1321void t4_idma_monitor(struct adapter *adapter,
1322 struct sge_idma_monitor_state *idma,
1323 int hz, int ticks);
625ba2c2 1324#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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