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cxgb4: Detect DB FULL events and notify RDMA ULD
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include <linux/bitops.h>
39#include <linux/cache.h>
40#include <linux/interrupt.h>
41#include <linux/list.h>
42#include <linux/netdevice.h>
43#include <linux/pci.h>
44#include <linux/spinlock.h>
45#include <linux/timer.h>
46#include <asm/io.h>
47#include "cxgb4_uld.h"
48#include "t4_hw.h"
49
50#define FW_VERSION_MAJOR 1
51#define FW_VERSION_MINOR 1
52#define FW_VERSION_MICRO 0
53
54enum {
55 MAX_NPORTS = 4, /* max # of ports */
47d54d65 56 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
59};
60
61enum {
62 MEM_EDC0,
63 MEM_EDC1,
64 MEM_MC
65};
66
67enum dev_master {
68 MASTER_CANT,
69 MASTER_MAY,
70 MASTER_MUST
71};
72
73enum dev_state {
74 DEV_STATE_UNINIT,
75 DEV_STATE_INIT,
76 DEV_STATE_ERR
77};
78
79enum {
80 PAUSE_RX = 1 << 0,
81 PAUSE_TX = 1 << 1,
82 PAUSE_AUTONEG = 1 << 2
83};
84
85struct port_stats {
86 u64 tx_octets; /* total # of octets in good frames */
87 u64 tx_frames; /* all good frames */
88 u64 tx_bcast_frames; /* all broadcast frames */
89 u64 tx_mcast_frames; /* all multicast frames */
90 u64 tx_ucast_frames; /* all unicast frames */
91 u64 tx_error_frames; /* all error frames */
92
93 u64 tx_frames_64; /* # of Tx frames in a particular range */
94 u64 tx_frames_65_127;
95 u64 tx_frames_128_255;
96 u64 tx_frames_256_511;
97 u64 tx_frames_512_1023;
98 u64 tx_frames_1024_1518;
99 u64 tx_frames_1519_max;
100
101 u64 tx_drop; /* # of dropped Tx frames */
102 u64 tx_pause; /* # of transmitted pause frames */
103 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
104 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
105 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
106 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
107 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
108 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
109 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
110 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
111
112 u64 rx_octets; /* total # of octets in good frames */
113 u64 rx_frames; /* all good frames */
114 u64 rx_bcast_frames; /* all broadcast frames */
115 u64 rx_mcast_frames; /* all multicast frames */
116 u64 rx_ucast_frames; /* all unicast frames */
117 u64 rx_too_long; /* # of frames exceeding MTU */
118 u64 rx_jabber; /* # of jabber frames */
119 u64 rx_fcs_err; /* # of received frames with bad FCS */
120 u64 rx_len_err; /* # of received frames with length error */
121 u64 rx_symbol_err; /* symbol errors */
122 u64 rx_runt; /* # of short frames */
123
124 u64 rx_frames_64; /* # of Rx frames in a particular range */
125 u64 rx_frames_65_127;
126 u64 rx_frames_128_255;
127 u64 rx_frames_256_511;
128 u64 rx_frames_512_1023;
129 u64 rx_frames_1024_1518;
130 u64 rx_frames_1519_max;
131
132 u64 rx_pause; /* # of received pause frames */
133 u64 rx_ppp0; /* # of received PPP prio 0 frames */
134 u64 rx_ppp1; /* # of received PPP prio 1 frames */
135 u64 rx_ppp2; /* # of received PPP prio 2 frames */
136 u64 rx_ppp3; /* # of received PPP prio 3 frames */
137 u64 rx_ppp4; /* # of received PPP prio 4 frames */
138 u64 rx_ppp5; /* # of received PPP prio 5 frames */
139 u64 rx_ppp6; /* # of received PPP prio 6 frames */
140 u64 rx_ppp7; /* # of received PPP prio 7 frames */
141
142 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
143 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
144 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
145 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
146 u64 rx_trunc0; /* buffer-group 0 truncated packets */
147 u64 rx_trunc1; /* buffer-group 1 truncated packets */
148 u64 rx_trunc2; /* buffer-group 2 truncated packets */
149 u64 rx_trunc3; /* buffer-group 3 truncated packets */
150};
151
152struct lb_port_stats {
153 u64 octets;
154 u64 frames;
155 u64 bcast_frames;
156 u64 mcast_frames;
157 u64 ucast_frames;
158 u64 error_frames;
159
160 u64 frames_64;
161 u64 frames_65_127;
162 u64 frames_128_255;
163 u64 frames_256_511;
164 u64 frames_512_1023;
165 u64 frames_1024_1518;
166 u64 frames_1519_max;
167
168 u64 drop;
169
170 u64 ovflow0;
171 u64 ovflow1;
172 u64 ovflow2;
173 u64 ovflow3;
174 u64 trunc0;
175 u64 trunc1;
176 u64 trunc2;
177 u64 trunc3;
178};
179
180struct tp_tcp_stats {
181 u32 tcpOutRsts;
182 u64 tcpInSegs;
183 u64 tcpOutSegs;
184 u64 tcpRetransSegs;
185};
186
187struct tp_err_stats {
188 u32 macInErrs[4];
189 u32 hdrInErrs[4];
190 u32 tcpInErrs[4];
191 u32 tnlCongDrops[4];
192 u32 ofldChanDrops[4];
193 u32 tnlTxDrops[4];
194 u32 ofldVlanDrops[4];
195 u32 tcp6InErrs[4];
196 u32 ofldNoNeigh;
197 u32 ofldCongDefer;
198};
199
200struct tp_params {
201 unsigned int ntxchan; /* # of Tx channels */
202 unsigned int tre; /* log2 of core clocks per TP tick */
203};
204
205struct vpd_params {
206 unsigned int cclk;
207 u8 ec[EC_LEN + 1];
208 u8 sn[SERNUM_LEN + 1];
209 u8 id[ID_LEN + 1];
210};
211
212struct pci_params {
213 unsigned char speed;
214 unsigned char width;
215};
216
217struct adapter_params {
218 struct tp_params tp;
219 struct vpd_params vpd;
220 struct pci_params pci;
221
900a6596
DM		 222 unsigned int sf_size; /* serial flash size in bytes */
223 unsigned int sf_nsec; /* # of flash sectors */
224 unsigned int sf_fw_start; /* start of FW image in flash */
225
625ba2c2
DM		 226 unsigned int fw_vers;
227 unsigned int tp_vers;
228 u8 api_vers[7];
229
230 unsigned short mtus[NMTUS];
231 unsigned short a_wnd[NCCTRL_WIN];
232 unsigned short b_wnd[NCCTRL_WIN];
233
234 unsigned char nports; /* # of ethernet ports */
235 unsigned char portvec;
236 unsigned char rev; /* chip revision */
237 unsigned char offload;
238
239 unsigned int ofldq_wr_cred;
240};
241
242struct trace_params {
243 u32 data[TRACE_LEN / 4];
244 u32 mask[TRACE_LEN / 4];
245 unsigned short snap_len;
246 unsigned short min_len;
247 unsigned char skip_ofst;
248 unsigned char skip_len;
249 unsigned char invert;
250 unsigned char port;
251};
252
253struct link_config {
254 unsigned short supported; /* link capabilities */
255 unsigned short advertising; /* advertised capabilities */
256 unsigned short requested_speed; /* speed user has requested */
257 unsigned short speed; /* actual link speed */
258 unsigned char requested_fc; /* flow control user has requested */
259 unsigned char fc; /* actual link flow control */
260 unsigned char autoneg; /* autonegotiating? */
261 unsigned char link_ok; /* link up? */
262};
263
264#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
265
266enum {
267 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
268 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
269 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
270 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
271};
272
273enum {
274 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
275 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
276};
277
278struct adapter;
625ba2c2
DM		 279struct sge_rspq;
280
281struct port_info {
282 struct adapter *adapter;
625ba2c2
DM		 283 u16 viid;
284 s16 xact_addr_filt; /* index of exact MAC address filter */
285 u16 rss_size; /* size of VI's RSS table slice */
286 s8 mdio_addr;
287 u8 port_type;
288 u8 mod_type;
289 u8 port_id;
290 u8 tx_chan;
291 u8 lport; /* associated offload logical port */
625ba2c2
DM		 292 u8 nqsets; /* # of qsets */
293 u8 first_qset; /* index of first qset */
f796564a 294 u8 rss_mode;
625ba2c2 295 struct link_config link_cfg;
671b0060 296 u16 *rss;
625ba2c2
DM		 297};
298
625ba2c2
DM		 299struct dentry;
300struct work_struct;
301
302enum { /* adapter flags */
303 FULL_INIT_DONE = (1 << 0),
304 USING_MSI = (1 << 1),
305 USING_MSIX = (1 << 2),
625ba2c2
DM		 306 FW_OK = (1 << 4),
307};
308
309struct rx_sw_desc;
310
311struct sge_fl { /* SGE free-buffer queue state */
312 unsigned int avail; /* # of available Rx buffers */
313 unsigned int pend_cred; /* new buffers since last FL DB ring */
314 unsigned int cidx; /* consumer index */
315 unsigned int pidx; /* producer index */
316 unsigned long alloc_failed; /* # of times buffer allocation failed */
317 unsigned long large_alloc_failed;
318 unsigned long starving;
319 /* RO fields */
320 unsigned int cntxt_id; /* SGE context id for the free list */
321 unsigned int size; /* capacity of free list */
322 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
323 __be64 *desc; /* address of HW Rx descriptor ring */
324 dma_addr_t addr; /* bus address of HW ring start */
325};
326
327/* A packet gather list */
328struct pkt_gl {
e91b0f24 329 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 330 void *va; /* virtual address of first byte */
331 unsigned int nfrags; /* # of fragments */
332 unsigned int tot_len; /* total length of fragments */
333};
334
335typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
336 const struct pkt_gl *gl);
337
338struct sge_rspq { /* state for an SGE response queue */
339 struct napi_struct napi;
340 const __be64 *cur_desc; /* current descriptor in queue */
341 unsigned int cidx; /* consumer index */
342 u8 gen; /* current generation bit */
343 u8 intr_params; /* interrupt holdoff parameters */
344 u8 next_intr_params; /* holdoff params for next interrupt */
345 u8 pktcnt_idx; /* interrupt packet threshold */
346 u8 uld; /* ULD handling this queue */
347 u8 idx; /* queue index within its group */
348 int offset; /* offset into current Rx buffer */
349 u16 cntxt_id; /* SGE context id for the response q */
350 u16 abs_id; /* absolute SGE id for the response q */
351 __be64 *desc; /* address of HW response ring */
352 dma_addr_t phys_addr; /* physical address of the ring */
353 unsigned int iqe_len; /* entry size */
354 unsigned int size; /* capacity of response queue */
355 struct adapter *adap;
356 struct net_device *netdev; /* associated net device */
357 rspq_handler_t handler;
358};
359
360struct sge_eth_stats { /* Ethernet queue statistics */
361 unsigned long pkts; /* # of ethernet packets */
362 unsigned long lro_pkts; /* # of LRO super packets */
363 unsigned long lro_merged; /* # of wire packets merged by LRO */
364 unsigned long rx_cso; /* # of Rx checksum offloads */
365 unsigned long vlan_ex; /* # of Rx VLAN extractions */
366 unsigned long rx_drops; /* # of packets dropped due to no mem */
367};
368
369struct sge_eth_rxq { /* SW Ethernet Rx queue */
370 struct sge_rspq rspq;
371 struct sge_fl fl;
372 struct sge_eth_stats stats;
373} ____cacheline_aligned_in_smp;
374
375struct sge_ofld_stats { /* offload queue statistics */
376 unsigned long pkts; /* # of packets */
377 unsigned long imm; /* # of immediate-data packets */
378 unsigned long an; /* # of asynchronous notifications */
379 unsigned long nomem; /* # of responses deferred due to no mem */
380};
381
382struct sge_ofld_rxq { /* SW offload Rx queue */
383 struct sge_rspq rspq;
384 struct sge_fl fl;
385 struct sge_ofld_stats stats;
386} ____cacheline_aligned_in_smp;
387
388struct tx_desc {
389 __be64 flit[8];
390};
391
392struct tx_sw_desc;
393
394struct sge_txq {
395 unsigned int in_use; /* # of in-use Tx descriptors */
396 unsigned int size; /* # of descriptors */
397 unsigned int cidx; /* SW consumer index */
398 unsigned int pidx; /* producer index */
399 unsigned long stops; /* # of times q has been stopped */
400 unsigned long restarts; /* # of queue restarts */
401 unsigned int cntxt_id; /* SGE context id for the Tx q */
402 struct tx_desc *desc; /* address of HW Tx descriptor ring */
403 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
404 struct sge_qstat *stat; /* queue status entry */
405 dma_addr_t phys_addr; /* physical address of the ring */
406};
407
408struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
409 struct sge_txq q;
410 struct netdev_queue *txq; /* associated netdev TX queue */
411 unsigned long tso; /* # of TSO requests */
412 unsigned long tx_cso; /* # of Tx checksum offloads */
413 unsigned long vlan_ins; /* # of Tx VLAN insertions */
414 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
415} ____cacheline_aligned_in_smp;
416
417struct sge_ofld_txq { /* state for an SGE offload Tx queue */
418 struct sge_txq q;
419 struct adapter *adap;
420 struct sk_buff_head sendq; /* list of backpressured packets */
421 struct tasklet_struct qresume_tsk; /* restarts the queue */
422 u8 full; /* the Tx ring is full */
423 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
424} ____cacheline_aligned_in_smp;
425
426struct sge_ctrl_txq { /* state for an SGE control Tx queue */
427 struct sge_txq q;
428 struct adapter *adap;
429 struct sk_buff_head sendq; /* list of backpressured packets */
430 struct tasklet_struct qresume_tsk; /* restarts the queue */
431 u8 full; /* the Tx ring is full */
432} ____cacheline_aligned_in_smp;
433
434struct sge {
435 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
436 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
437 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
438
439 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
440 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
441 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
442 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
443
444 struct sge_rspq intrq ____cacheline_aligned_in_smp;
445 spinlock_t intrq_lock;
446
447 u16 max_ethqsets; /* # of available Ethernet queue sets */
448 u16 ethqsets; /* # of active Ethernet queue sets */
449 u16 ethtxq_rover; /* Tx queue to clean up next */
450 u16 ofldqsets; /* # of active offload queue sets */
451 u16 rdmaqs; /* # of available RDMA Rx queues */
452 u16 ofld_rxq[MAX_OFLD_QSETS];
453 u16 rdma_rxq[NCHAN];
454 u16 timer_val[SGE_NTIMERS];
455 u8 counter_val[SGE_NCOUNTERS];
456 unsigned int starve_thres;
457 u8 idma_state[2];
e46dab4d
DM		 458 unsigned int egr_start;
459 unsigned int ingr_start;
625ba2c2
DM		 460 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
461 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
462 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
463 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
464 struct timer_list rx_timer; /* refills starving FLs */
465 struct timer_list tx_timer; /* checks Tx queues */
466};
467
468#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
469#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
470#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
471
472struct l2t_data;
473
474struct adapter {
475 void __iomem *regs;
476 struct pci_dev *pdev;
477 struct device *pdev_dev;
060e0c75
DM		 478 unsigned int fn;
479 unsigned int flags;
625ba2c2 480
625ba2c2
DM		 481 int msg_enable;
482
483 struct adapter_params params;
484 struct cxgb4_virt_res vres;
485 unsigned int swintr;
486
487 unsigned int wol;
488
489 struct {
490 unsigned short vec;
8cd18ac4 491 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 492 } msix_info[MAX_INGQ + 1];
493
494 struct sge sge;
495
496 struct net_device *port[MAX_NPORTS];
497 u8 chan_map[NCHAN]; /* channel -> port map */
498
499 struct l2t_data *l2t;
500 void *uld_handle[CXGB4_ULD_MAX];
501 struct list_head list_node;
502
503 struct tid_info tids;
504 void **tid_release_head;
505 spinlock_t tid_release_lock;
506 struct work_struct tid_release_task;
881806bc
VP		 507 struct work_struct db_full_task;
508 struct work_struct db_drop_task;
625ba2c2
DM		 509 bool tid_release_task_busy;
510
511 struct dentry *debugfs_root;
512
513 spinlock_t stats_lock;
514};
515
516static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
517{
518 return readl(adap->regs + reg_addr);
519}
520
521static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
522{
523 writel(val, adap->regs + reg_addr);
524}
525
526#ifndef readq
527static inline u64 readq(const volatile void __iomem *addr)
528{
529 return readl(addr) + ((u64)readl(addr + 4) << 32);
530}
531
532static inline void writeq(u64 val, volatile void __iomem *addr)
533{
534 writel(val, addr);
535 writel(val >> 32, addr + 4);
536}
537#endif
538
539static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
540{
541 return readq(adap->regs + reg_addr);
542}
543
544static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
545{
546 writeq(val, adap->regs + reg_addr);
547}
548
549/**
550 * netdev2pinfo - return the port_info structure associated with a net_device
551 * @dev: the netdev
552 *
553 * Return the struct port_info associated with a net_device
554 */
555static inline struct port_info *netdev2pinfo(const struct net_device *dev)
556{
557 return netdev_priv(dev);
558}
559
560/**
561 * adap2pinfo - return the port_info of a port
562 * @adap: the adapter
563 * @idx: the port index
564 *
565 * Return the port_info structure for the port of the given index.
566 */
567static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
568{
569 return netdev_priv(adap->port[idx]);
570}
571
572/**
573 * netdev2adap - return the adapter structure associated with a net_device
574 * @dev: the netdev
575 *
576 * Return the struct adapter associated with a net_device
577 */
578static inline struct adapter *netdev2adap(const struct net_device *dev)
579{
580 return netdev2pinfo(dev)->adapter;
581}
582
583void t4_os_portmod_changed(const struct adapter *adap, int port_id);
584void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
585
586void *t4_alloc_mem(size_t size);
625ba2c2
DM		 587
588void t4_free_sge_resources(struct adapter *adap);
589irq_handler_t t4_intr_handler(struct adapter *adap);
590netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
591int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
592 const struct pkt_gl *gl);
593int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
594int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
595int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
596 struct net_device *dev, int intr_idx,
597 struct sge_fl *fl, rspq_handler_t hnd);
598int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
599 struct net_device *dev, struct netdev_queue *netdevq,
600 unsigned int iqid);
601int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
602 struct net_device *dev, unsigned int iqid,
603 unsigned int cmplqid);
604int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
605 struct net_device *dev, unsigned int iqid);
606irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
607void t4_sge_init(struct adapter *adap);
608void t4_sge_start(struct adapter *adap);
609void t4_sge_stop(struct adapter *adap);
610
611#define for_each_port(adapter, iter) \
612 for (iter = 0; iter < (adapter)->params.nports; ++iter)
613
614static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
615{
616 return adap->params.vpd.cclk / 1000;
617}
618
619static inline unsigned int us_to_core_ticks(const struct adapter *adap,
620 unsigned int us)
621{
622 return (us * adap->params.vpd.cclk) / 1000;
623}
624
625void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
626 u32 val);
627
628int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
629 void *rpl, bool sleep_ok);
630
631static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
632 int size, void *rpl)
633{
634 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
635}
636
637static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
638 int size, void *rpl)
639{
640 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
641}
642
643void t4_intr_enable(struct adapter *adapter);
644void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 645int t4_slow_intr_handler(struct adapter *adapter);
646
204dc3c0 647int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 648int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
649 struct link_config *lc);
650int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
651int t4_seeprom_wp(struct adapter *adapter, bool enable);
625ba2c2
DM		 652int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
653int t4_check_fw_version(struct adapter *adapter);
654int t4_prep_adapter(struct adapter *adapter);
655int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
656void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 657int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
658 int start, int n, const u16 *rspq, unsigned int nrspq);
659int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
660 unsigned int flags);
625ba2c2
DM		 661int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
662int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
663 u64 *parity);
664
665void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 666void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
625ba2c2
DM		 667void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
668 struct tp_tcp_stats *v6);
669void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
670 const unsigned short *alpha, const unsigned short *beta);
671
672void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
673 const u8 *addr);
674int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
675 u64 mask0, u64 mask1, unsigned int crc, bool enable);
676
677int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
678 enum dev_master master, enum dev_state *state);
679int t4_fw_bye(struct adapter *adap, unsigned int mbox);
680int t4_early_init(struct adapter *adap, unsigned int mbox);
681int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
682int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
683 unsigned int vf, unsigned int nparams, const u32 *params,
684 u32 *val);
685int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
686 unsigned int vf, unsigned int nparams, const u32 *params,
687 const u32 *val);
688int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
689 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
690 unsigned int rxqi, unsigned int rxq, unsigned int tc,
691 unsigned int vi, unsigned int cmask, unsigned int pmask,
692 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
693int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
694 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
695 unsigned int *rss_size);
625ba2c2 696int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 697 int mtu, int promisc, int all_multi, int bcast, int vlanex,
698 bool sleep_ok);
625ba2c2
DM		 699int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
700 unsigned int viid, bool free, unsigned int naddr,
701 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
702int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
703 int idx, const u8 *addr, bool persist, bool add_smt);
704int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
705 bool ucast, u64 vec, bool sleep_ok);
706int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
707 bool rx_en, bool tx_en);
708int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
709 unsigned int nblinks);
710int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
711 unsigned int mmd, unsigned int reg, u16 *valp);
712int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
713 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 714int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
715 unsigned int vf, unsigned int iqtype, unsigned int iqid,
716 unsigned int fl0id, unsigned int fl1id);
717int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
718 unsigned int vf, unsigned int eqid);
719int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
720 unsigned int vf, unsigned int eqid);
721int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
722 unsigned int vf, unsigned int eqid);
723int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 724void t4_db_full(struct adapter *adapter);
725void t4_db_dropped(struct adapter *adapter);
625ba2c2 726#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
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