projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'regulator/for-next'
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
b72a32da 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
625ba2c2
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
dca4faeb
VP		 38#include "t4_hw.h"
39
625ba2c2
DM		 40#include <linux/bitops.h>
41#include <linux/cache.h>
42#include <linux/interrupt.h>
43#include <linux/list.h>
44#include <linux/netdevice.h>
45#include <linux/pci.h>
46#include <linux/spinlock.h>
47#include <linux/timer.h>
c0b8b992 48#include <linux/vmalloc.h>
098ef6c2 49#include <linux/etherdevice.h>
5e2a5ebc 50#include <linux/net_tstamp.h>
625ba2c2 51#include <asm/io.h>
27999805 52#include "t4_chip_type.h"
625ba2c2 53#include "cxgb4_uld.h"
625ba2c2 54
3069ee9b 55#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
94cdb8bb
HS		 56extern struct list_head adapter_list;
57extern struct mutex uld_mutex;
3069ee9b 58
625ba2c2 59enum {
098ef6c2
HS		 60 MAX_NPORTS = 4, /* max # of ports */
61 SERNUM_LEN = 24, /* Serial # length */
62 EC_LEN = 16, /* E/C length */
63 ID_LEN = 16, /* ID length */
64 PN_LEN = 16, /* Part Number length */
65 MACADDR_LEN = 12, /* MAC Address length */
625ba2c2
DM		 66};
67
812034f1
HS		 68enum {
69 T4_REGMAP_SIZE = (160 * 1024),
70 T5_REGMAP_SIZE = (332 * 1024),
71};
72
625ba2c2
DM		 73enum {
74 MEM_EDC0,
75 MEM_EDC1,
2422d9a3
SR		 76 MEM_MC,
77 MEM_MC0 = MEM_MC,
78 MEM_MC1
625ba2c2
DM		 79};
80
3069ee9b 81enum {
3eb4afbf
VP		 82 MEMWIN0_APERTURE = 2048,
83 MEMWIN0_BASE = 0x1b800,
3069ee9b
VP		 84 MEMWIN1_APERTURE = 32768,
85 MEMWIN1_BASE = 0x28000,
2422d9a3 86 MEMWIN1_BASE_T5 = 0x52000,
3eb4afbf
VP		 87 MEMWIN2_APERTURE = 65536,
88 MEMWIN2_BASE = 0x30000,
0abfd152
HS		 89 MEMWIN2_APERTURE_T5 = 131072,
90 MEMWIN2_BASE_T5 = 0x60000,
3069ee9b
VP		 91};
92
625ba2c2
DM		 93enum dev_master {
94 MASTER_CANT,
95 MASTER_MAY,
96 MASTER_MUST
97};
98
99enum dev_state {
100 DEV_STATE_UNINIT,
101 DEV_STATE_INIT,
102 DEV_STATE_ERR
103};
104
105enum {
106 PAUSE_RX = 1 << 0,
107 PAUSE_TX = 1 << 1,
108 PAUSE_AUTONEG = 1 << 2
109};
110
111struct port_stats {
112 u64 tx_octets; /* total # of octets in good frames */
113 u64 tx_frames; /* all good frames */
114 u64 tx_bcast_frames; /* all broadcast frames */
115 u64 tx_mcast_frames; /* all multicast frames */
116 u64 tx_ucast_frames; /* all unicast frames */
117 u64 tx_error_frames; /* all error frames */
118
119 u64 tx_frames_64; /* # of Tx frames in a particular range */
120 u64 tx_frames_65_127;
121 u64 tx_frames_128_255;
122 u64 tx_frames_256_511;
123 u64 tx_frames_512_1023;
124 u64 tx_frames_1024_1518;
125 u64 tx_frames_1519_max;
126
127 u64 tx_drop; /* # of dropped Tx frames */
128 u64 tx_pause; /* # of transmitted pause frames */
129 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
130 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
131 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
132 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
133 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
134 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
135 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
136 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
137
138 u64 rx_octets; /* total # of octets in good frames */
139 u64 rx_frames; /* all good frames */
140 u64 rx_bcast_frames; /* all broadcast frames */
141 u64 rx_mcast_frames; /* all multicast frames */
142 u64 rx_ucast_frames; /* all unicast frames */
143 u64 rx_too_long; /* # of frames exceeding MTU */
144 u64 rx_jabber; /* # of jabber frames */
145 u64 rx_fcs_err; /* # of received frames with bad FCS */
146 u64 rx_len_err; /* # of received frames with length error */
147 u64 rx_symbol_err; /* symbol errors */
148 u64 rx_runt; /* # of short frames */
149
150 u64 rx_frames_64; /* # of Rx frames in a particular range */
151 u64 rx_frames_65_127;
152 u64 rx_frames_128_255;
153 u64 rx_frames_256_511;
154 u64 rx_frames_512_1023;
155 u64 rx_frames_1024_1518;
156 u64 rx_frames_1519_max;
157
158 u64 rx_pause; /* # of received pause frames */
159 u64 rx_ppp0; /* # of received PPP prio 0 frames */
160 u64 rx_ppp1; /* # of received PPP prio 1 frames */
161 u64 rx_ppp2; /* # of received PPP prio 2 frames */
162 u64 rx_ppp3; /* # of received PPP prio 3 frames */
163 u64 rx_ppp4; /* # of received PPP prio 4 frames */
164 u64 rx_ppp5; /* # of received PPP prio 5 frames */
165 u64 rx_ppp6; /* # of received PPP prio 6 frames */
166 u64 rx_ppp7; /* # of received PPP prio 7 frames */
167
168 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
169 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
170 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
171 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
172 u64 rx_trunc0; /* buffer-group 0 truncated packets */
173 u64 rx_trunc1; /* buffer-group 1 truncated packets */
174 u64 rx_trunc2; /* buffer-group 2 truncated packets */
175 u64 rx_trunc3; /* buffer-group 3 truncated packets */
176};
177
178struct lb_port_stats {
179 u64 octets;
180 u64 frames;
181 u64 bcast_frames;
182 u64 mcast_frames;
183 u64 ucast_frames;
184 u64 error_frames;
185
186 u64 frames_64;
187 u64 frames_65_127;
188 u64 frames_128_255;
189 u64 frames_256_511;
190 u64 frames_512_1023;
191 u64 frames_1024_1518;
192 u64 frames_1519_max;
193
194 u64 drop;
195
196 u64 ovflow0;
197 u64 ovflow1;
198 u64 ovflow2;
199 u64 ovflow3;
200 u64 trunc0;
201 u64 trunc1;
202 u64 trunc2;
203 u64 trunc3;
204};
205
206struct tp_tcp_stats {
a4cfd929
HS		 207 u32 tcp_out_rsts;
208 u64 tcp_in_segs;
209 u64 tcp_out_segs;
210 u64 tcp_retrans_segs;
211};
212
213struct tp_usm_stats {
214 u32 frames;
215 u32 drops;
216 u64 octets;
625ba2c2
DM		 217};
218
a6222975
HS		 219struct tp_fcoe_stats {
220 u32 frames_ddp;
221 u32 frames_drop;
222 u64 octets_ddp;
625ba2c2
DM		 223};
224
225struct tp_err_stats {
a4cfd929
HS		 226 u32 mac_in_errs[4];
227 u32 hdr_in_errs[4];
228 u32 tcp_in_errs[4];
229 u32 tnl_cong_drops[4];
230 u32 ofld_chan_drops[4];
231 u32 tnl_tx_drops[4];
232 u32 ofld_vlan_drops[4];
233 u32 tcp6_in_errs[4];
234 u32 ofld_no_neigh;
235 u32 ofld_cong_defer;
236};
237
a6222975
HS		 238struct tp_cpl_stats {
239 u32 req[4];
240 u32 rsp[4];
241};
242
a4cfd929
HS		 243struct tp_rdma_stats {
244 u32 rqe_dfr_pkt;
245 u32 rqe_dfr_mod;
625ba2c2
DM		 246};
247
e85c9a7a
HS		 248struct sge_params {
249 u32 hps; /* host page size for our PF/VF */
250 u32 eq_qpp; /* egress queues/page for our PF/VF */
251 u32 iq_qpp; /* egress queues/page for our PF/VF */
252};
253
625ba2c2 254struct tp_params {
625ba2c2 255 unsigned int tre; /* log2 of core clocks per TP tick */
2d277b3b 256 unsigned int la_mask; /* what events are recorded by TP LA */
dca4faeb
VP		 257 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
258 /* channel map */
636f9d37
VP		 259
260 uint32_t dack_re; /* DACK timer resolution */
261 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
dcf7b6f5
KS		 262
263 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
264 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
265
266 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
267 * subset of the set of fields which may be present in the Compressed
268 * Filter Tuple portion of filters and TCP TCB connections. The
269 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
270 * Since a variable number of fields may or may not be present, their
271 * shifted field positions within the Compressed Filter Tuple may
272 * vary, or not even be present if the field isn't selected in
273 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
274 * places we store their offsets here, or a -1 if the field isn't
275 * present.
276 */
277 int vlan_shift;
278 int vnic_shift;
279 int port_shift;
280 int protocol_shift;
625ba2c2
DM		 281};
282
283struct vpd_params {
284 unsigned int cclk;
285 u8 ec[EC_LEN + 1];
286 u8 sn[SERNUM_LEN + 1];
287 u8 id[ID_LEN + 1];
a94cd705 288 u8 pn[PN_LEN + 1];
098ef6c2 289 u8 na[MACADDR_LEN + 1];
625ba2c2
DM		 290};
291
292struct pci_params {
293 unsigned char speed;
294 unsigned char width;
295};
296
49aa284f
HS		 297struct devlog_params {
298 u32 memtype; /* which memory (EDC0, EDC1, MC) */
299 u32 start; /* start of log in firmware memory */
300 u32 size; /* size of log */
301};
302
3ccc6cf7
HS		 303/* Stores chip specific parameters */
304struct arch_specific_params {
305 u8 nchan;
44588560 306 u8 pm_stats_cnt;
2216d014 307 u8 cng_ch_bits_log; /* congestion channel map bits width */
3ccc6cf7
HS		 308 u16 mps_rplc_size;
309 u16 vfcount;
310 u32 sge_fl_db;
311 u16 mps_tcam_size;
312};
313
625ba2c2 314struct adapter_params {
e85c9a7a 315 struct sge_params sge;
625ba2c2
DM		 316 struct tp_params tp;
317 struct vpd_params vpd;
318 struct pci_params pci;
49aa284f
HS		 319 struct devlog_params devlog;
320 enum pcie_memwin drv_memwin;
625ba2c2 321
f1ff24aa
HS		 322 unsigned int cim_la_size;
323
900a6596
DM		 324 unsigned int sf_size; /* serial flash size in bytes */
325 unsigned int sf_nsec; /* # of flash sectors */
326 unsigned int sf_fw_start; /* start of FW image in flash */
327
625ba2c2 328 unsigned int fw_vers;
0de72738 329 unsigned int bs_vers; /* bootstrap version */
625ba2c2 330 unsigned int tp_vers;
0de72738 331 unsigned int er_vers; /* expansion ROM version */
625ba2c2
DM		 332 u8 api_vers[7];
333
334 unsigned short mtus[NMTUS];
335 unsigned short a_wnd[NCCTRL_WIN];
336 unsigned short b_wnd[NCCTRL_WIN];
337
338 unsigned char nports; /* # of ethernet ports */
339 unsigned char portvec;
d14807dd 340 enum chip_type chip; /* chip code */
3ccc6cf7 341 struct arch_specific_params arch; /* chip specific params */
625ba2c2 342 unsigned char offload;
94cdb8bb 343 unsigned char crypto; /* HW capability for crypto */
625ba2c2 344
9a4da2cd
VP		 345 unsigned char bypass;
346
625ba2c2 347 unsigned int ofldq_wr_cred;
1ac0f095 348 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
4c2c5763 349
b72a32da 350 unsigned int nsched_cls; /* number of traffic classes */
4c2c5763
HS		 351 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
352 unsigned int max_ird_adapter; /* Max read depth per adapter */
625ba2c2
DM		 353};
354
a3bfb617
HS		 355/* State needed to monitor the forward progress of SGE Ingress DMA activities
356 * and possible hangs.
357 */
358struct sge_idma_monitor_state {
359 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
360 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
361 unsigned int idma_state[2]; /* IDMA Hang detect state */
362 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
363 unsigned int idma_warn[2]; /* time to warning in HZ */
364};
365
7f080c3f
HS		 366/* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
367 * The access and execute times are signed in order to accommodate negative
368 * error returns.
369 */
370struct mbox_cmd {
371 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
372 u64 timestamp; /* OS-dependent timestamp */
373 u32 seqno; /* sequence number */
374 s16 access; /* time (ms) to access mailbox */
375 s16 execute; /* time (ms) to execute */
376};
377
378struct mbox_cmd_log {
379 unsigned int size; /* number of entries in the log */
380 unsigned int cursor; /* next position in the log to write */
381 u32 seqno; /* next sequence number */
382 /* variable length mailbox command log starts here */
383};
384
385/* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
386 * return a pointer to the specified entry.
387 */
388static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
389 unsigned int entry_idx)
390{
391 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
392}
393
16e47624
HS		 394#include "t4fw_api.h"
395
396#define FW_VERSION(chip) ( \
b2e1a3f0
HS		 397 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
398 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
399 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
400 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
16e47624
HS		 401#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
402
403struct fw_info {
404 u8 chip;
405 char *fs_name;
406 char *fw_mod_name;
407 struct fw_hdr fw_hdr;
408};
409
625ba2c2
DM		 410struct trace_params {
411 u32 data[TRACE_LEN / 4];
412 u32 mask[TRACE_LEN / 4];
413 unsigned short snap_len;
414 unsigned short min_len;
415 unsigned char skip_ofst;
416 unsigned char skip_len;
417 unsigned char invert;
418 unsigned char port;
419};
420
421struct link_config {
422 unsigned short supported; /* link capabilities */
423 unsigned short advertising; /* advertised capabilities */
eb97ad99 424 unsigned short lp_advertising; /* peer advertised capabilities */
625ba2c2
DM		 425 unsigned short requested_speed; /* speed user has requested */
426 unsigned short speed; /* actual link speed */
427 unsigned char requested_fc; /* flow control user has requested */
428 unsigned char fc; /* actual link flow control */
429 unsigned char autoneg; /* autonegotiating? */
430 unsigned char link_ok; /* link up? */
ddc7740d 431 unsigned char link_down_rc; /* link down reason */
625ba2c2
DM		 432};
433
e2ac9628 434#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
625ba2c2
DM		 435
436enum {
437 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
f90ce561 438 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
625ba2c2
DM		 439 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
440 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
f36e58e5 441 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
f2692d16
VP		 442
443 /* # of streaming iSCSIT Rx queues */
444 MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS,
625ba2c2
DM		 445};
446
812034f1
HS		 447enum {
448 MAX_TXQ_ENTRIES = 16384,
449 MAX_CTRL_TXQ_ENTRIES = 1024,
450 MAX_RSPQ_ENTRIES = 16384,
451 MAX_RX_BUFFERS = 16384,
452 MIN_TXQ_ENTRIES = 32,
453 MIN_CTRL_TXQ_ENTRIES = 32,
454 MIN_RSPQ_ENTRIES = 128,
455 MIN_FL_ENTRIES = 16
456};
457
625ba2c2 458enum {
cf38be6d
HS		 459 INGQ_EXTRAS = 2, /* firmware event queue and */
460 /* forwarded interrupts */
f2692d16
VP		 461 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES +
462 MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS,
625ba2c2
DM		 463};
464
465struct adapter;
625ba2c2
DM		 466struct sge_rspq;
467
688848b1
AB		 468#include "cxgb4_dcb.h"
469
76fed8a9
VP		 470#ifdef CONFIG_CHELSIO_T4_FCOE
471#include "cxgb4_fcoe.h"
472#endif /* CONFIG_CHELSIO_T4_FCOE */
473
625ba2c2
DM		 474struct port_info {
475 struct adapter *adapter;
625ba2c2
DM		 476 u16 viid;
477 s16 xact_addr_filt; /* index of exact MAC address filter */
478 u16 rss_size; /* size of VI's RSS table slice */
479 s8 mdio_addr;
40e9de4b 480 enum fw_port_type port_type;
625ba2c2
DM		 481 u8 mod_type;
482 u8 port_id;
483 u8 tx_chan;
484 u8 lport; /* associated offload logical port */
625ba2c2
DM		 485 u8 nqsets; /* # of qsets */
486 u8 first_qset; /* index of first qset */
f796564a 487 u8 rss_mode;
625ba2c2 488 struct link_config link_cfg;
671b0060 489 u16 *rss;
a4cfd929 490 struct port_stats stats_base;
688848b1
AB		 491#ifdef CONFIG_CHELSIO_T4_DCB
492 struct port_dcb_info dcb; /* Data Center Bridging support */
493#endif
76fed8a9
VP		 494#ifdef CONFIG_CHELSIO_T4_FCOE
495 struct cxgb_fcoe fcoe;
496#endif /* CONFIG_CHELSIO_T4_FCOE */
5e2a5ebc
HS		 497 bool rxtstamp; /* Enable TS */
498 struct hwtstamp_config tstamp_config;
b72a32da 499 struct sched_table *sched_tbl;
625ba2c2
DM		 500};
501
625ba2c2
DM		 502struct dentry;
503struct work_struct;
504
505enum { /* adapter flags */
506 FULL_INIT_DONE = (1 << 0),
144be3d9
GS		 507 DEV_ENABLED = (1 << 1),
508 USING_MSI = (1 << 2),
509 USING_MSIX = (1 << 3),
625ba2c2 510 FW_OK = (1 << 4),
13ee15d3 511 RSS_TNLALLLOOKUP = (1 << 5),
52367a76
VP		 512 USING_SOFT_PARAMS = (1 << 6),
513 MASTER_PF = (1 << 7),
514 FW_OFLD_CONN = (1 << 9),
625ba2c2
DM		 515};
516
94cdb8bb
HS		 517enum {
518 ULP_CRYPTO_LOOKASIDE = 1 << 0,
519};
520
625ba2c2
DM		 521struct rx_sw_desc;
522
523struct sge_fl { /* SGE free-buffer queue state */
524 unsigned int avail; /* # of available Rx buffers */
525 unsigned int pend_cred; /* new buffers since last FL DB ring */
526 unsigned int cidx; /* consumer index */
527 unsigned int pidx; /* producer index */
528 unsigned long alloc_failed; /* # of times buffer allocation failed */
529 unsigned long large_alloc_failed;
70055dd0
HS		 530 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
531 unsigned long low; /* # of times momentarily starving */
625ba2c2
DM		 532 unsigned long starving;
533 /* RO fields */
534 unsigned int cntxt_id; /* SGE context id for the free list */
535 unsigned int size; /* capacity of free list */
536 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
537 __be64 *desc; /* address of HW Rx descriptor ring */
538 dma_addr_t addr; /* bus address of HW ring start */
df64e4d3
HS		 539 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
540 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 541};
542
543/* A packet gather list */
544struct pkt_gl {
5e2a5ebc 545 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
e91b0f24 546 struct page_frag frags[MAX_SKB_FRAGS];
625ba2c2
DM		 547 void *va; /* virtual address of first byte */
548 unsigned int nfrags; /* # of fragments */
549 unsigned int tot_len; /* total length of fragments */
550};
551
552typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
553 const struct pkt_gl *gl);
2337ba42
VP		 554typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
555/* LRO related declarations for ULD */
556struct t4_lro_mgr {
557#define MAX_LRO_SESSIONS 64
558 u8 lro_session_cnt; /* # of sessions to aggregate */
559 unsigned long lro_pkts; /* # of LRO super packets */
560 unsigned long lro_merged; /* # of wire packets merged by LRO */
561 struct sk_buff_head lroq; /* list of aggregated sessions */
562};
625ba2c2
DM		 563
564struct sge_rspq { /* state for an SGE response queue */
565 struct napi_struct napi;
566 const __be64 *cur_desc; /* current descriptor in queue */
567 unsigned int cidx; /* consumer index */
568 u8 gen; /* current generation bit */
569 u8 intr_params; /* interrupt holdoff parameters */
570 u8 next_intr_params; /* holdoff params for next interrupt */
e553ec3f 571 u8 adaptive_rx;
625ba2c2
DM		 572 u8 pktcnt_idx; /* interrupt packet threshold */
573 u8 uld; /* ULD handling this queue */
574 u8 idx; /* queue index within its group */
575 int offset; /* offset into current Rx buffer */
576 u16 cntxt_id; /* SGE context id for the response q */
577 u16 abs_id; /* absolute SGE id for the response q */
578 __be64 *desc; /* address of HW response ring */
579 dma_addr_t phys_addr; /* physical address of the ring */
df64e4d3
HS		 580 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
581 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 582 unsigned int iqe_len; /* entry size */
583 unsigned int size; /* capacity of response queue */
584 struct adapter *adap;
585 struct net_device *netdev; /* associated net device */
586 rspq_handler_t handler;
2337ba42
VP		 587 rspq_flush_handler_t flush_handler;
588 struct t4_lro_mgr lro_mgr;
3a336cb1
HS		 589#ifdef CONFIG_NET_RX_BUSY_POLL
590#define CXGB_POLL_STATE_IDLE 0
591#define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
592#define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
593#define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
594#define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
595#define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
596 CXGB_POLL_STATE_POLL_YIELD)
597#define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
598 CXGB_POLL_STATE_POLL)
599#define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
600 CXGB_POLL_STATE_POLL_YIELD)
601 unsigned int bpoll_state;
602 spinlock_t bpoll_lock; /* lock for busy poll */
603#endif /* CONFIG_NET_RX_BUSY_POLL */
604
625ba2c2
DM		 605};
606
607struct sge_eth_stats { /* Ethernet queue statistics */
608 unsigned long pkts; /* # of ethernet packets */
609 unsigned long lro_pkts; /* # of LRO super packets */
610 unsigned long lro_merged; /* # of wire packets merged by LRO */
611 unsigned long rx_cso; /* # of Rx checksum offloads */
612 unsigned long vlan_ex; /* # of Rx VLAN extractions */
613 unsigned long rx_drops; /* # of packets dropped due to no mem */
614};
615
616struct sge_eth_rxq { /* SW Ethernet Rx queue */
617 struct sge_rspq rspq;
618 struct sge_fl fl;
619 struct sge_eth_stats stats;
620} ____cacheline_aligned_in_smp;
621
622struct sge_ofld_stats { /* offload queue statistics */
623 unsigned long pkts; /* # of packets */
624 unsigned long imm; /* # of immediate-data packets */
625 unsigned long an; /* # of asynchronous notifications */
626 unsigned long nomem; /* # of responses deferred due to no mem */
627};
628
629struct sge_ofld_rxq { /* SW offload Rx queue */
630 struct sge_rspq rspq;
631 struct sge_fl fl;
632 struct sge_ofld_stats stats;
633} ____cacheline_aligned_in_smp;
634
635struct tx_desc {
636 __be64 flit[8];
637};
638
639struct tx_sw_desc;
640
641struct sge_txq {
642 unsigned int in_use; /* # of in-use Tx descriptors */
643 unsigned int size; /* # of descriptors */
644 unsigned int cidx; /* SW consumer index */
645 unsigned int pidx; /* producer index */
646 unsigned long stops; /* # of times q has been stopped */
647 unsigned long restarts; /* # of queue restarts */
648 unsigned int cntxt_id; /* SGE context id for the Tx q */
649 struct tx_desc *desc; /* address of HW Tx descriptor ring */
650 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
651 struct sge_qstat *stat; /* queue status entry */
652 dma_addr_t phys_addr; /* physical address of the ring */
3069ee9b
VP		 653 spinlock_t db_lock;
654 int db_disabled;
655 unsigned short db_pidx;
05eb2389 656 unsigned short db_pidx_inc;
df64e4d3
HS		 657 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
658 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
625ba2c2
DM		 659};
660
661struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
662 struct sge_txq q;
663 struct netdev_queue *txq; /* associated netdev TX queue */
10b00466
AB		 664#ifdef CONFIG_CHELSIO_T4_DCB
665 u8 dcb_prio; /* DCB Priority bound to queue */
666#endif
625ba2c2
DM		 667 unsigned long tso; /* # of TSO requests */
668 unsigned long tx_cso; /* # of Tx checksum offloads */
669 unsigned long vlan_ins; /* # of Tx VLAN insertions */
670 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
671} ____cacheline_aligned_in_smp;
672
673struct sge_ofld_txq { /* state for an SGE offload Tx queue */
674 struct sge_txq q;
675 struct adapter *adap;
676 struct sk_buff_head sendq; /* list of backpressured packets */
677 struct tasklet_struct qresume_tsk; /* restarts the queue */
126fca64 678 bool service_ofldq_running; /* service_ofldq() is processing sendq */
625ba2c2
DM		 679 u8 full; /* the Tx ring is full */
680 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
681} ____cacheline_aligned_in_smp;
682
683struct sge_ctrl_txq { /* state for an SGE control Tx queue */
684 struct sge_txq q;
685 struct adapter *adap;
686 struct sk_buff_head sendq; /* list of backpressured packets */
687 struct tasklet_struct qresume_tsk; /* restarts the queue */
688 u8 full; /* the Tx ring is full */
689} ____cacheline_aligned_in_smp;
690
94cdb8bb
HS		 691struct sge_uld_rxq_info {
692 char name[IFNAMSIZ]; /* name of ULD driver */
693 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
694 u16 *msix_tbl; /* msix_tbl for uld */
695 u16 *rspq_id; /* response queue id's of rxq */
696 u16 nrxq; /* # of ingress uld queues */
697 u16 nciq; /* # of completion queues */
698 u8 uld; /* uld type */
699};
700
625ba2c2
DM		 701struct sge {
702 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
703 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
704 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
705
706 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
f90ce561 707 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS];
f2692d16 708 struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES];
625ba2c2 709 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
cf38be6d 710 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
625ba2c2 711 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
94cdb8bb 712 struct sge_uld_rxq_info **uld_rxq_info;
625ba2c2
DM		 713
714 struct sge_rspq intrq ____cacheline_aligned_in_smp;
715 spinlock_t intrq_lock;
716
717 u16 max_ethqsets; /* # of available Ethernet queue sets */
718 u16 ethqsets; /* # of active Ethernet queue sets */
719 u16 ethtxq_rover; /* Tx queue to clean up next */
f90ce561 720 u16 iscsiqsets; /* # of active iSCSI queue sets */
f2692d16 721 u16 niscsitq; /* # of available iSCST Rx queues */
625ba2c2 722 u16 rdmaqs; /* # of available RDMA Rx queues */
cf38be6d 723 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
94cdb8bb 724 u16 nqs_per_uld; /* # of Rx queues per ULD */
f90ce561 725 u16 iscsi_rxq[MAX_OFLD_QSETS];
f2692d16 726 u16 iscsit_rxq[MAX_ISCSIT_QUEUES];
f36e58e5
HS		 727 u16 rdma_rxq[MAX_RDMA_QUEUES];
728 u16 rdma_ciq[MAX_RDMA_CIQS];
625ba2c2
DM		 729 u16 timer_val[SGE_NTIMERS];
730 u8 counter_val[SGE_NCOUNTERS];
52367a76
VP		 731 u32 fl_pg_order; /* large page allocation size */
732 u32 stat_len; /* length of status page at ring end */
733 u32 pktshift; /* padding between CPL & packet data */
734 u32 fl_align; /* response queue message alignment */
735 u32 fl_starve_thres; /* Free List starvation threshold */
0f4d201f 736
a3bfb617 737 struct sge_idma_monitor_state idma_monitor;
e46dab4d 738 unsigned int egr_start;
4b8e27a8 739 unsigned int egr_sz;
e46dab4d 740 unsigned int ingr_start;
4b8e27a8
HS		 741 unsigned int ingr_sz;
742 void **egr_map; /* qid->queue egress queue map */
743 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
744 unsigned long *starving_fl;
745 unsigned long *txq_maperr;
5b377d11 746 unsigned long *blocked_fl;
625ba2c2
DM		 747 struct timer_list rx_timer; /* refills starving FLs */
748 struct timer_list tx_timer; /* checks Tx queues */
749};
750
751#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
f90ce561 752#define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)
f2692d16 753#define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)
625ba2c2 754#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
cf38be6d 755#define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
625ba2c2
DM		 756
757struct l2t_data;
758
2422d9a3
SR		 759#ifdef CONFIG_PCI_IOV
760
7d6727cf
SR		 761/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
762 * Configuration initialization for T5 only has SR-IOV functionality enabled
763 * on PF0-3 in order to simplify everything.
2422d9a3 764 */
7d6727cf 765#define NUM_OF_PF_WITH_SRIOV 4
2422d9a3
SR		 766
767#endif
768
a4cfd929
HS		 769struct doorbell_stats {
770 u32 db_drop;
771 u32 db_empty;
772 u32 db_full;
773};
774
fc08a01a
HS		 775struct hash_mac_addr {
776 struct list_head list;
777 u8 addr[ETH_ALEN];
778};
779
94cdb8bb
HS		 780struct uld_msix_bmap {
781 unsigned long *msix_bmap;
782 unsigned int mapsize;
783 spinlock_t lock; /* lock for acquiring bitmap */
784};
785
786struct uld_msix_info {
787 unsigned short vec;
788 char desc[IFNAMSIZ + 10];
789};
790
661dbeb9
HS		 791struct vf_info {
792 unsigned char vf_mac_addr[ETH_ALEN];
793 bool pf_set_mac;
794};
795
625ba2c2
DM		 796struct adapter {
797 void __iomem *regs;
22adfe0a 798 void __iomem *bar2;
0abfd152 799 u32 t4_bar0;
625ba2c2
DM		 800 struct pci_dev *pdev;
801 struct device *pdev_dev;
0de72738 802 const char *name;
3069ee9b 803 unsigned int mbox;
b2612722 804 unsigned int pf;
060e0c75 805 unsigned int flags;
e7b48a32 806 unsigned int adap_idx;
2422d9a3 807 enum chip_type chip;
625ba2c2 808
625ba2c2
DM		 809 int msg_enable;
810
811 struct adapter_params params;
812 struct cxgb4_virt_res vres;
813 unsigned int swintr;
814
625ba2c2
DM		 815 struct {
816 unsigned short vec;
8cd18ac4 817 char desc[IFNAMSIZ + 10];
625ba2c2 818 } msix_info[MAX_INGQ + 1];
94cdb8bb
HS		 819 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
820 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
821 unsigned int msi_idx;
625ba2c2 822
a4cfd929 823 struct doorbell_stats db_stats;
625ba2c2
DM		 824 struct sge sge;
825
826 struct net_device *port[MAX_NPORTS];
827 u8 chan_map[NCHAN]; /* channel -> port map */
828
661dbeb9
HS		 829 struct vf_info *vfinfo;
830 u8 num_vfs;
831
793dad94 832 u32 filter_mode;
636f9d37
VP		 833 unsigned int l2t_start;
834 unsigned int l2t_end;
625ba2c2 835 struct l2t_data *l2t;
b5a02f50
AB		 836 unsigned int clipt_start;
837 unsigned int clipt_end;
838 struct clip_tbl *clipt;
94cdb8bb 839 struct cxgb4_pci_uld_info *uld;
625ba2c2 840 void *uld_handle[CXGB4_ULD_MAX];
94cdb8bb 841 unsigned int num_uld;
625ba2c2 842 struct list_head list_node;
01bcca68 843 struct list_head rcu_node;
fc08a01a 844 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
625ba2c2 845
7714cb9e
VP		 846 void *iscsi_ppm;
847
625ba2c2
DM		 848 struct tid_info tids;
849 void **tid_release_head;
850 spinlock_t tid_release_lock;
29aaee65 851 struct workqueue_struct *workq;
625ba2c2 852 struct work_struct tid_release_task;
881806bc
VP		 853 struct work_struct db_full_task;
854 struct work_struct db_drop_task;
625ba2c2
DM		 855 bool tid_release_task_busy;
856
7f080c3f
HS		 857 /* support for mailbox command/reply logging */
858#define T4_OS_LOG_MBOX_CMDS 256
859 struct mbox_cmd_log *mbox_log;
860
625ba2c2 861 struct dentry *debugfs_root;
621a5f7a
VK		 862 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
863 bool trace_rss; /* 1 implies that different RSS flit per filter is
8e3d04fd
HS		 864 * used per filter else if 0 default RSS flit is
865 * used for all 4 filters.
866 */
625ba2c2
DM		 867
868 spinlock_t stats_lock;
fc5ab020 869 spinlock_t win0_lock ____cacheline_aligned_in_smp;
625ba2c2
DM		 870};
871
b72a32da
RL		 872/* Support for "sched-class" command to allow a TX Scheduling Class to be
873 * programmed with various parameters.
874 */
875struct ch_sched_params {
876 s8 type; /* packet or flow */
877 union {
878 struct {
879 s8 level; /* scheduler hierarchy level */
880 s8 mode; /* per-class or per-flow */
881 s8 rateunit; /* bit or packet rate */
882 s8 ratemode; /* %port relative or kbps absolute */
883 s8 channel; /* scheduler channel [0..N] */
884 s8 class; /* scheduler class [0..N] */
885 s32 minrate; /* minimum rate */
886 s32 maxrate; /* maximum rate */
887 s16 weight; /* percent weight */
888 s16 pktsize; /* average packet size */
889 } params;
890 } u;
6cede1f1
RL		 891};
892
10a2604e
RL		 893enum {
894 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
895};
896
897enum {
898 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
899};
900
901enum {
902 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
903};
904
905enum {
906 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
907};
908
909enum {
910 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
911};
912
6cede1f1
RL		 913/* Support for "sched_queue" command to allow one or more NIC TX Queues
914 * to be bound to a TX Scheduling Class.
915 */
916struct ch_sched_queue {
917 s8 queue; /* queue index */
918 s8 class; /* class index */
b72a32da
RL		 919};
920
f2b7e78d
VP		 921/* Defined bit width of user definable filter tuples
922 */
923#define ETHTYPE_BITWIDTH 16
924#define FRAG_BITWIDTH 1
925#define MACIDX_BITWIDTH 9
926#define FCOE_BITWIDTH 1
927#define IPORT_BITWIDTH 3
928#define MATCHTYPE_BITWIDTH 3
929#define PROTO_BITWIDTH 8
930#define TOS_BITWIDTH 8
931#define PF_BITWIDTH 8
932#define VF_BITWIDTH 8
933#define IVLAN_BITWIDTH 16
934#define OVLAN_BITWIDTH 16
935
936/* Filter matching rules. These consist of a set of ingress packet field
937 * (value, mask) tuples. The associated ingress packet field matches the
938 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
939 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
940 * matches an ingress packet when all of the individual individual field
941 * matching rules are true.
942 *
943 * Partial field masks are always valid, however, while it may be easy to
944 * understand their meanings for some fields (e.g. IP address to match a
945 * subnet), for others making sensible partial masks is less intuitive (e.g.
946 * MPS match type) ...
947 *
948 * Most of the following data structures are modeled on T4 capabilities.
949 * Drivers for earlier chips use the subsets which make sense for those chips.
950 * We really need to come up with a hardware-independent mechanism to
951 * represent hardware filter capabilities ...
952 */
953struct ch_filter_tuple {
954 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
955 * register selects which of these fields will participate in the
956 * filter match rules -- up to a maximum of 36 bits. Because
957 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
958 * set of fields.
959 */
960 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
961 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
962 uint32_t ivlan_vld:1; /* inner VLAN valid */
963 uint32_t ovlan_vld:1; /* outer VLAN valid */
964 uint32_t pfvf_vld:1; /* PF/VF valid */
965 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
966 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
967 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
968 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
969 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
970 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
971 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
972 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
973 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
974 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
975
976 /* Uncompressed header matching field rules. These are always
977 * available for field rules.
978 */
979 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
980 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
981 uint16_t lport; /* local port */
982 uint16_t fport; /* foreign port */
983};
984
985/* A filter ioctl command.
986 */
987struct ch_filter_specification {
988 /* Administrative fields for filter.
989 */
990 uint32_t hitcnts:1; /* count filter hits in TCB */
991 uint32_t prio:1; /* filter has priority over active/server */
992
993 /* Fundamental filter typing. This is the one element of filter
994 * matching that doesn't exist as a (value, mask) tuple.
995 */
996 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
997
998 /* Packet dispatch information. Ingress packets which match the
999 * filter rules will be dropped, passed to the host or switched back
1000 * out as egress packets.
1001 */
1002 uint32_t action:2; /* drop, pass, switch */
1003
1004 uint32_t rpttid:1; /* report TID in RSS hash field */
1005
1006 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1007 uint32_t iq:10; /* ingress queue */
1008
1009 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1010 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1011 /* 1 => TCB contains IQ ID */
1012
1013 /* Switch proxy/rewrite fields. An ingress packet which matches a
1014 * filter with "switch" set will be looped back out as an egress
1015 * packet -- potentially with some Ethernet header rewriting.
1016 */
1017 uint32_t eport:2; /* egress port to switch packet out */
1018 uint32_t newdmac:1; /* rewrite destination MAC address */
1019 uint32_t newsmac:1; /* rewrite source MAC address */
1020 uint32_t newvlan:2; /* rewrite VLAN Tag */
1021 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1022 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1023 uint16_t vlan; /* VLAN Tag to insert */
1024
1025 /* Filter rule value/mask pairs.
1026 */
1027 struct ch_filter_tuple val;
1028 struct ch_filter_tuple mask;
1029};
1030
1031enum {
1032 FILTER_PASS = 0, /* default */
1033 FILTER_DROP,
1034 FILTER_SWITCH
1035};
1036
1037enum {
1038 VLAN_NOCHANGE = 0, /* default */
1039 VLAN_REMOVE,
1040 VLAN_INSERT,
1041 VLAN_REWRITE
1042};
1043
a4cfd929
HS		 1044static inline int is_offload(const struct adapter *adap)
1045{
1046 return adap->params.offload;
1047}
1048
94cdb8bb
HS		 1049static inline int is_pci_uld(const struct adapter *adap)
1050{
1051 return adap->params.crypto;
1052}
1053
625ba2c2
DM		 1054static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1055{
1056 return readl(adap->regs + reg_addr);
1057}
1058
1059static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1060{
1061 writel(val, adap->regs + reg_addr);
1062}
1063
1064#ifndef readq
1065static inline u64 readq(const volatile void __iomem *addr)
1066{
1067 return readl(addr) + ((u64)readl(addr + 4) << 32);
1068}
1069
1070static inline void writeq(u64 val, volatile void __iomem *addr)
1071{
1072 writel(val, addr);
1073 writel(val >> 32, addr + 4);
1074}
1075#endif
1076
1077static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1078{
1079 return readq(adap->regs + reg_addr);
1080}
1081
1082static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1083{
1084 writeq(val, adap->regs + reg_addr);
1085}
1086
098ef6c2
HS		 1087/**
1088 * t4_set_hw_addr - store a port's MAC address in SW
1089 * @adapter: the adapter
1090 * @port_idx: the port index
1091 * @hw_addr: the Ethernet address
1092 *
1093 * Store the Ethernet address of the given port in SW. Called by the common
1094 * code when it retrieves a port's Ethernet address from EEPROM.
1095 */
1096static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1097 u8 hw_addr[])
1098{
1099 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1100 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1101}
1102
625ba2c2
DM		 1103/**
1104 * netdev2pinfo - return the port_info structure associated with a net_device
1105 * @dev: the netdev
1106 *
1107 * Return the struct port_info associated with a net_device
1108 */
1109static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1110{
1111 return netdev_priv(dev);
1112}
1113
1114/**
1115 * adap2pinfo - return the port_info of a port
1116 * @adap: the adapter
1117 * @idx: the port index
1118 *
1119 * Return the port_info structure for the port of the given index.
1120 */
1121static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1122{
1123 return netdev_priv(adap->port[idx]);
1124}
1125
1126/**
1127 * netdev2adap - return the adapter structure associated with a net_device
1128 * @dev: the netdev
1129 *
1130 * Return the struct adapter associated with a net_device
1131 */
1132static inline struct adapter *netdev2adap(const struct net_device *dev)
1133{
1134 return netdev2pinfo(dev)->adapter;
1135}
1136
3a336cb1
HS		 1137#ifdef CONFIG_NET_RX_BUSY_POLL
1138static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1139{
1140 spin_lock_init(&q->bpoll_lock);
1141 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1142}
1143
1144static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1145{
1146 bool rc = true;
1147
1148 spin_lock(&q->bpoll_lock);
1149 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1150 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1151 rc = false;
1152 } else {
1153 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1154 }
1155 spin_unlock(&q->bpoll_lock);
1156 return rc;
1157}
1158
1159static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1160{
1161 bool rc = false;
1162
1163 spin_lock(&q->bpoll_lock);
1164 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1165 rc = true;
1166 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1167 spin_unlock(&q->bpoll_lock);
1168 return rc;
1169}
1170
1171static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1172{
1173 bool rc = true;
1174
1175 spin_lock_bh(&q->bpoll_lock);
1176 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1177 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1178 rc = false;
1179 } else {
1180 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1181 }
1182 spin_unlock_bh(&q->bpoll_lock);
1183 return rc;
1184}
1185
1186static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1187{
1188 bool rc = false;
1189
1190 spin_lock_bh(&q->bpoll_lock);
1191 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1192 rc = true;
1193 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1194 spin_unlock_bh(&q->bpoll_lock);
1195 return rc;
1196}
1197
1198static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1199{
1200 return q->bpoll_state & CXGB_POLL_USER_PEND;
1201}
1202#else
1203static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1204{
1205}
1206
1207static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1208{
1209 return true;
1210}
1211
1212static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1213{
1214 return false;
1215}
1216
1217static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1218{
1219 return false;
1220}
1221
1222static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1223{
1224 return false;
1225}
1226
1227static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1228{
1229 return false;
1230}
1231#endif /* CONFIG_NET_RX_BUSY_POLL */
1232
812034f1
HS		 1233/* Return a version number to identify the type of adapter. The scheme is:
1234 * - bits 0..9: chip version
1235 * - bits 10..15: chip revision
1236 * - bits 16..23: register dump version
1237 */
1238static inline unsigned int mk_adap_vers(struct adapter *ap)
1239{
1240 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1241 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1242}
1243
1244/* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1245static inline unsigned int qtimer_val(const struct adapter *adap,
1246 const struct sge_rspq *q)
1247{
1248 unsigned int idx = q->intr_params >> 1;
1249
1250 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1251}
1252
1253/* driver version & name used for ethtool_drvinfo */
1254extern char cxgb4_driver_name[];
1255extern const char cxgb4_driver_version[];
1256
625ba2c2
DM		 1257void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1258void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1259
1260void *t4_alloc_mem(size_t size);
625ba2c2
DM		 1261
1262void t4_free_sge_resources(struct adapter *adap);
5fa76694 1263void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
625ba2c2
DM		 1264irq_handler_t t4_intr_handler(struct adapter *adap);
1265netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1266int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1267 const struct pkt_gl *gl);
1268int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1269int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1270int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1271 struct net_device *dev, int intr_idx,
2337ba42
VP		 1272 struct sge_fl *fl, rspq_handler_t hnd,
1273 rspq_flush_handler_t flush_handler, int cong);
625ba2c2
DM		 1274int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1275 struct net_device *dev, struct netdev_queue *netdevq,
1276 unsigned int iqid);
1277int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1278 struct net_device *dev, unsigned int iqid,
1279 unsigned int cmplqid);
1280int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1281 struct net_device *dev, unsigned int iqid);
1282irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
52367a76 1283int t4_sge_init(struct adapter *adap);
625ba2c2
DM		 1284void t4_sge_start(struct adapter *adap);
1285void t4_sge_stop(struct adapter *adap);
3a336cb1 1286int cxgb_busy_poll(struct napi_struct *napi);
812034f1
HS		 1287void cxgb4_set_ethtool_ops(struct net_device *netdev);
1288int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
3069ee9b 1289extern int dbfifo_int_thresh;
625ba2c2
DM		 1290
1291#define for_each_port(adapter, iter) \
1292 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1293
9a4da2cd
VP		 1294static inline int is_bypass(struct adapter *adap)
1295{
1296 return adap->params.bypass;
1297}
1298
1299static inline int is_bypass_device(int device)
1300{
1301 /* this should be set based upon device capabilities */
1302 switch (device) {
1303 case 0x440b:
1304 case 0x440c:
1305 return 1;
1306 default:
1307 return 0;
1308 }
1309}
1310
01b69614
HS		 1311static inline int is_10gbt_device(int device)
1312{
1313 /* this should be set based upon device capabilities */
1314 switch (device) {
1315 case 0x4409:
1316 case 0x4486:
1317 return 1;
1318
1319 default:
1320 return 0;
1321 }
1322}
1323
625ba2c2
DM		 1324static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1325{
1326 return adap->params.vpd.cclk / 1000;
1327}
1328
1329static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1330 unsigned int us)
1331{
1332 return (us * adap->params.vpd.cclk) / 1000;
1333}
1334
52367a76
VP		 1335static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1336 unsigned int ticks)
1337{
1338 /* add Core Clock / 2 to round ticks to nearest uS */
1339 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1340 adapter->params.vpd.cclk);
1341}
1342
625ba2c2
DM		 1343void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1344 u32 val);
1345
01b69614
HS		 1346int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1347 int size, void *rpl, bool sleep_ok, int timeout);
625ba2c2
DM		 1348int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1349 void *rpl, bool sleep_ok);
1350
01b69614
HS		 1351static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1352 const void *cmd, int size, void *rpl,
1353 int timeout)
1354{
1355 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1356 timeout);
1357}
1358
625ba2c2
DM		 1359static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1360 int size, void *rpl)
1361{
1362 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1363}
1364
1365static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1366 int size, void *rpl)
1367{
1368 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1369}
1370
fc08a01a
HS		 1371/**
1372 * hash_mac_addr - return the hash value of a MAC address
1373 * @addr: the 48-bit Ethernet MAC address
1374 *
1375 * Hashes a MAC address according to the hash function used by HW inexact
1376 * (hash) address matching.
1377 */
1378static inline int hash_mac_addr(const u8 *addr)
1379{
1380 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1381 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1382
1383 a ^= b;
1384 a ^= (a >> 12);
1385 a ^= (a >> 6);
1386 return a & 0x3f;
1387}
1388
94cdb8bb
HS		 1389int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1390 unsigned int cnt);
1391static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1392 unsigned int us, unsigned int cnt,
1393 unsigned int size, unsigned int iqe_size)
1394{
1395 q->adap = adap;
1396 cxgb4_set_rspq_intr_params(q, us, cnt);
1397 q->iqe_len = iqe_size;
1398 q->size = size;
1399}
1400
13ee15d3
VP		 1401void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1402 unsigned int data_reg, const u32 *vals,
1403 unsigned int nregs, unsigned int start_idx);
f2b7e78d
VP		 1404void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1405 unsigned int data_reg, u32 *vals, unsigned int nregs,
1406 unsigned int start_idx);
0abfd152 1407void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
f2b7e78d
VP		 1408
1409struct fw_filter_wr;
1410
625ba2c2
DM		 1411void t4_intr_enable(struct adapter *adapter);
1412void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 1413int t4_slow_intr_handler(struct adapter *adapter);
1414
8203b509 1415int t4_wait_dev_ready(void __iomem *regs);
4036da90 1416int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
625ba2c2
DM		 1417 struct link_config *lc);
1418int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
fc5ab020 1419
b562fc37
HS		 1420u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1421u32 t4_get_util_window(struct adapter *adap);
1422void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1423
fc5ab020
HS		 1424#define T4_MEMORY_WRITE 0
1425#define T4_MEMORY_READ 1
1426int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
f01aa633 1427 void *buf, int dir);
fc5ab020
HS		 1428static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1429 u32 len, __be32 *buf)
1430{
1431 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1432}
1433
812034f1
HS		 1434unsigned int t4_get_regs_len(struct adapter *adapter);
1435void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1436
625ba2c2 1437int t4_seeprom_wp(struct adapter *adapter, bool enable);
098ef6c2
HS		 1438int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1439int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
49216c1c
HS		 1440int t4_read_flash(struct adapter *adapter, unsigned int addr,
1441 unsigned int nwords, u32 *data, int byte_oriented);
625ba2c2 1442int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
01b69614
HS		 1443int t4_load_phy_fw(struct adapter *adap,
1444 int win, spinlock_t *lock,
1445 int (*phy_fw_version)(const u8 *, size_t),
1446 const u8 *phy_fw_data, size_t phy_fw_size);
1447int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
49216c1c 1448int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
22c0b963
HS		 1449int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1450 const u8 *fw_data, unsigned int size, int force);
acac5962 1451int t4_fl_pkt_align(struct adapter *adap);
636f9d37 1452unsigned int t4_flash_cfg_addr(struct adapter *adapter);
a69265e9 1453int t4_check_fw_version(struct adapter *adap);
16e47624 1454int t4_get_fw_version(struct adapter *adapter, u32 *vers);
0de72738 1455int t4_get_bs_version(struct adapter *adapter, u32 *vers);
16e47624 1456int t4_get_tp_version(struct adapter *adapter, u32 *vers);
ba3f8cd5 1457int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
16e47624
HS		 1458int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1459 const u8 *fw_data, unsigned int fw_size,
1460 struct fw_hdr *card_fw, enum dev_state state, int *reset);
625ba2c2 1461int t4_prep_adapter(struct adapter *adapter);
e85c9a7a
HS		 1462
1463enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 1464int t4_bar2_sge_qregs(struct adapter *adapter,
e85c9a7a
HS		 1465 unsigned int qid,
1466 enum t4_bar2_qtype qtype,
66cf188e 1467 int user,
e85c9a7a
HS		 1468 u64 *pbar2_qoffset,
1469 unsigned int *pbar2_qid);
1470
dc9daab2
HS		 1471unsigned int qtimer_val(const struct adapter *adap,
1472 const struct sge_rspq *q);
ae469b68
HS		 1473
1474int t4_init_devlog_params(struct adapter *adapter);
e85c9a7a 1475int t4_init_sge_params(struct adapter *adapter);
dcf7b6f5
KS		 1476int t4_init_tp_params(struct adapter *adap);
1477int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
c035e183 1478int t4_init_rss_mode(struct adapter *adap, int mbox);
c3e324e3
HS		 1479int t4_init_portinfo(struct port_info *pi, int mbox,
1480 int port, int pf, int vf, u8 mac[]);
625ba2c2
DM		 1481int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1482void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 1483int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1484 int start, int n, const u16 *rspq, unsigned int nrspq);
1485int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1486 unsigned int flags);
c035e183
HS		 1487int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1488 unsigned int flags, unsigned int defq);
688ea5fe
HS		 1489int t4_read_rss(struct adapter *adapter, u16 *entries);
1490void t4_read_rss_key(struct adapter *adapter, u32 *key);
1491void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1492void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1493 u32 *valp);
1494void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1495 u32 *vfl, u32 *vfh);
1496u32 t4_read_rss_pf_map(struct adapter *adapter);
1497u32 t4_read_rss_pf_mask(struct adapter *adapter);
1498
145ef8a5 1499unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
b3bbe36a
HS		 1500void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1501void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
e5f0e43b
HS		 1502int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1503 size_t n);
c778af7d
HS		 1504int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1505 size_t n);
f1ff24aa
HS		 1506int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1507 unsigned int *valp);
1508int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1509 const unsigned int *valp);
1510int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
19689609
HS		 1511void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1512 unsigned int *pif_req_wrptr,
1513 unsigned int *pif_rsp_wrptr);
26fae93f 1514void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
74b3092c 1515void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
72aca4bf 1516const char *t4_get_port_type_description(enum fw_port_type port_type);
625ba2c2 1517void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
a4cfd929
HS		 1518void t4_get_port_stats_offset(struct adapter *adap, int idx,
1519 struct port_stats *stats,
1520 struct port_stats *offset);
65046e84 1521void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
625ba2c2 1522void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
bad43792 1523void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
636f9d37
VP		 1524void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1525 unsigned int mask, unsigned int val);
2d277b3b 1526void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
a4cfd929 1527void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
a6222975 1528void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
a4cfd929
HS		 1529void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1530void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
625ba2c2
DM		 1531void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1532 struct tp_tcp_stats *v6);
a6222975
HS		 1533void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1534 struct tp_fcoe_stats *st);
625ba2c2
DM		 1535void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1536 const unsigned short *alpha, const unsigned short *beta);
1537
797ff0f5
HS		 1538void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1539
7864026b 1540void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
f2b7e78d
VP		 1541void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1542
625ba2c2
DM		 1543void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1544 const u8 *addr);
1545int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1546 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1547
1548int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1549 enum dev_master master, enum dev_state *state);
1550int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1551int t4_early_init(struct adapter *adap, unsigned int mbox);
1552int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
636f9d37
VP		 1553int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1554 unsigned int cache_line_size);
1555int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
625ba2c2
DM		 1556int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1557 unsigned int vf, unsigned int nparams, const u32 *params,
1558 u32 *val);
01b69614
HS		 1559int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1560 unsigned int vf, unsigned int nparams, const u32 *params,
1561 u32 *val, int rw);
1562int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1563 unsigned int pf, unsigned int vf,
1564 unsigned int nparams, const u32 *params,
1565 const u32 *val, int timeout);
625ba2c2
DM		 1566int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1567 unsigned int vf, unsigned int nparams, const u32 *params,
1568 const u32 *val);
1569int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1570 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1571 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1572 unsigned int vi, unsigned int cmask, unsigned int pmask,
1573 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1574int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1575 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1576 unsigned int *rss_size);
4f3a0fcf
HS		 1577int t4_free_vi(struct adapter *adap, unsigned int mbox,
1578 unsigned int pf, unsigned int vf,
1579 unsigned int viid);
625ba2c2 1580int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 1581 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1582 bool sleep_ok);
625ba2c2
DM		 1583int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1584 unsigned int viid, bool free, unsigned int naddr,
1585 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
fc08a01a
HS		 1586int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1587 unsigned int viid, unsigned int naddr,
1588 const u8 **addr, bool sleep_ok);
625ba2c2
DM		 1589int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1590 int idx, const u8 *addr, bool persist, bool add_smt);
1591int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1592 bool ucast, u64 vec, bool sleep_ok);
688848b1
AB		 1593int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1594 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
625ba2c2
DM		 1595int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1596 bool rx_en, bool tx_en);
1597int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1598 unsigned int nblinks);
1599int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1600 unsigned int mmd, unsigned int reg, u16 *valp);
1601int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1602 unsigned int mmd, unsigned int reg, u16 val);
ebf4dc2b
HS		 1603int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1604 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1605 unsigned int fl0id, unsigned int fl1id);
625ba2c2
DM		 1606int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1607 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1608 unsigned int fl0id, unsigned int fl1id);
1609int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1610 unsigned int vf, unsigned int eqid);
1611int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1612 unsigned int vf, unsigned int eqid);
1613int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1614 unsigned int vf, unsigned int eqid);
5d700ecb 1615int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
23853a0a 1616void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
625ba2c2 1617int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
881806bc
VP		 1618void t4_db_full(struct adapter *adapter);
1619void t4_db_dropped(struct adapter *adapter);
8e3d04fd
HS		 1620int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1621 int filter_index, int enable);
1622void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1623 int filter_index, int *enabled);
8caa1e84
VP		 1624int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1625 u32 addr, u32 val);
b72a32da
RL		 1626int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1627 int rateunit, int ratemode, int channel, int class,
1628 int minrate, int maxrate, int weight, int pktsize);
68bce192 1629void t4_sge_decode_idma_state(struct adapter *adapter, int state);
fd88b31a 1630void t4_free_mem(void *addr);
a3bfb617
HS		 1631void t4_idma_monitor_init(struct adapter *adapter,
1632 struct sge_idma_monitor_state *idma);
1633void t4_idma_monitor(struct adapter *adapter,
1634 struct sge_idma_monitor_state *idma,
1635 int hz, int ticks);
858aa65c
HS		 1636int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1637 unsigned int naddr, u8 *addr);
94cdb8bb
HS		 1638void uld_mem_free(struct adapter *adap);
1639int uld_mem_alloc(struct adapter *adap);
1640void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
625ba2c2 1641#endif /* __CXGB4_H__ */
Linux kernel - Deliverables
This page took 0.596704 seconds and 5 git commands to generate.