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Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_msg.h
CommitLineData
bbc02c7e
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
ce100b8b 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
bbc02c7e
DM		 5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __T4_MSG_H
36#define __T4_MSG_H
37
38#include <linux/types.h>
39
40enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
b96c5cbb 54 CPL_TX_DATA_ISO = 0x1F,
bbc02c7e
DM		 55
56 CPL_CLOSE_LISTSRV_RPL = 0x20,
57 CPL_L2T_WRITE_RPL = 0x23,
58 CPL_PASS_OPEN_RPL = 0x24,
59 CPL_ACT_OPEN_RPL = 0x25,
60 CPL_PEER_CLOSE = 0x26,
61 CPL_ABORT_REQ_RSS = 0x2B,
62 CPL_ABORT_RPL_RSS = 0x2D,
63
d6657781 64 CPL_RX_PHYS_ADDR = 0x30,
bbc02c7e
DM		 65 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_ISCSI_HDR = 0x33,
67 CPL_RDMA_CQE = 0x35,
68 CPL_RDMA_CQE_READ_RSP = 0x36,
69 CPL_RDMA_CQE_ERR = 0x37,
70 CPL_RX_DATA = 0x39,
71 CPL_SET_TCB_RPL = 0x3A,
72 CPL_RX_PKT = 0x3B,
73 CPL_RX_DDP_COMPLETE = 0x3F,
74
75 CPL_ACT_ESTABLISH = 0x40,
76 CPL_PASS_ESTABLISH = 0x41,
77 CPL_RX_DATA_DDP = 0x42,
78 CPL_PASS_ACCEPT_REQ = 0x44,
2422d9a3 79 CPL_TRACE_PKT_T5 = 0x48,
a2b81b35 80 CPL_RX_ISCSI_DDP = 0x49,
bbc02c7e
DM		 81
82 CPL_RDMA_READ_REQ = 0x60,
83
84 CPL_PASS_OPEN_REQ6 = 0x81,
85 CPL_ACT_OPEN_REQ6 = 0x83,
86
d6657781
HS		 87 CPL_TX_TLS_PDU = 0x88,
88 CPL_TX_SEC_PDU = 0x8A,
89 CPL_TX_TLS_ACK = 0x8B,
90
bbc02c7e
DM		 91 CPL_RDMA_TERMINATE = 0xA2,
92 CPL_RDMA_WRITE = 0xA4,
93 CPL_SGE_EGR_UPDATE = 0xA5,
94
95 CPL_TRACE_PKT = 0xB0,
a2b81b35 96 CPL_ISCSI_DATA = 0xB2,
bbc02c7e
DM		 97
98 CPL_FW4_MSG = 0xC0,
99 CPL_FW4_PLD = 0xC1,
100 CPL_FW4_ACK = 0xC3,
101
d6657781
HS		 102 CPL_RX_PHYS_DSGL = 0xD0,
103
bbc02c7e
DM		 104 CPL_FW6_MSG = 0xE0,
105 CPL_FW6_PLD = 0xE1,
106 CPL_TX_PKT_LSO = 0xED,
107 CPL_TX_PKT_XT = 0xEE,
108
109 NUM_CPL_CMDS
110};
111
112enum CPL_error {
113 CPL_ERR_NONE = 0,
4c72efef
H		 114 CPL_ERR_TCAM_PARITY = 1,
115 CPL_ERR_TCAM_MISS = 2,
bbc02c7e
DM		 116 CPL_ERR_TCAM_FULL = 3,
117 CPL_ERR_BAD_LENGTH = 15,
118 CPL_ERR_BAD_ROUTE = 18,
119 CPL_ERR_CONN_RESET = 20,
120 CPL_ERR_CONN_EXIST_SYNRECV = 21,
121 CPL_ERR_CONN_EXIST = 22,
122 CPL_ERR_ARP_MISS = 23,
123 CPL_ERR_BAD_SYN = 24,
124 CPL_ERR_CONN_TIMEDOUT = 30,
125 CPL_ERR_XMIT_TIMEDOUT = 31,
126 CPL_ERR_PERSIST_TIMEDOUT = 32,
127 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
128 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
129 CPL_ERR_RTX_NEG_ADVICE = 35,
130 CPL_ERR_PERSIST_NEG_ADVICE = 36,
7a2cea2a 131 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
bbc02c7e
DM		 132 CPL_ERR_ABORT_FAILED = 42,
133 CPL_ERR_IWARP_FLM = 50,
134};
135
6c53e938
HS		 136enum {
137 CPL_CONN_POLICY_AUTO = 0,
138 CPL_CONN_POLICY_ASK = 1,
139 CPL_CONN_POLICY_FILTER = 2,
140 CPL_CONN_POLICY_DENY = 3
141};
142
bbc02c7e
DM		 143enum {
144 ULP_MODE_NONE = 0,
145 ULP_MODE_ISCSI = 2,
146 ULP_MODE_RDMA = 4,
b48f3b9c 147 ULP_MODE_TCPDDP = 5,
bbc02c7e
DM		 148 ULP_MODE_FCOE = 6,
149};
150
151enum {
152 ULP_CRC_HEADER = 1 << 0,
153 ULP_CRC_DATA = 1 << 1
154};
155
156enum {
157 CPL_ABORT_SEND_RST = 0,
158 CPL_ABORT_NO_RST,
159};
160
161enum { /* TX_PKT_XT checksum types */
162 TX_CSUM_TCP = 0,
163 TX_CSUM_UDP = 1,
164 TX_CSUM_CRC16 = 4,
165 TX_CSUM_CRC32 = 5,
166 TX_CSUM_CRC32C = 6,
167 TX_CSUM_FCOE = 7,
168 TX_CSUM_TCPIP = 8,
169 TX_CSUM_UDPIP = 9,
170 TX_CSUM_TCPIP6 = 10,
171 TX_CSUM_UDPIP6 = 11,
172 TX_CSUM_IP = 12,
173};
174
175union opcode_tid {
176 __be32 opcode_tid;
177 u8 opcode;
178};
179
6c53e938
HS		 180#define CPL_OPCODE_S 24
181#define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
182#define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
183#define TID_G(x) ((x) & 0xFFFFFF)
184
185/* tid is assumed to be 24-bits */
186#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
187
bbc02c7e 188#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
6c53e938
HS		 189
190/* extract the TID from a CPL command */
191#define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
bbc02c7e
DM		 192
193/* partitioning of TID fields that also carry a queue id */
6c53e938
HS		 194#define TID_TID_S 0
195#define TID_TID_M 0x3fff
196#define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
197
198#define TID_QID_S 14
199#define TID_QID_M 0x3ff
200#define TID_QID_V(x) ((x) << TID_QID_S)
201#define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
bbc02c7e
DM		 202
203struct rss_header {
204 u8 opcode;
205#if defined(__LITTLE_ENDIAN_BITFIELD)
206 u8 channel:2;
207 u8 filter_hit:1;
208 u8 filter_tid:1;
209 u8 hash_type:2;
210 u8 ipv6:1;
211 u8 send2fw:1;
212#else
213 u8 send2fw:1;
214 u8 ipv6:1;
215 u8 hash_type:2;
216 u8 filter_tid:1;
217 u8 filter_hit:1;
218 u8 channel:2;
219#endif
220 __be16 qid;
221 __be32 hash_val;
222};
223
224struct work_request_hdr {
225 __be32 wr_hi;
226 __be32 wr_mid;
227 __be64 wr_lo;
228};
229
5be78ee9 230/* wr_hi fields */
6c53e938
HS		 231#define WR_OP_S 24
232#define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
5be78ee9 233
bbc02c7e
DM		 234#define WR_HDR struct work_request_hdr wr
235
1cab775c 236/* option 0 fields */
d7990b0c
AB		 237#define TX_CHAN_S 2
238#define TX_CHAN_V(x) ((x) << TX_CHAN_S)
239
240#define ULP_MODE_S 8
241#define ULP_MODE_V(x) ((x) << ULP_MODE_S)
242
243#define RCV_BUFSIZ_S 12
244#define RCV_BUFSIZ_M 0x3FFU
245#define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
246
247#define SMAC_SEL_S 28
248#define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
249
250#define L2T_IDX_S 36
251#define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
252
253#define WND_SCALE_S 50
254#define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
255
256#define KEEP_ALIVE_S 54
257#define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
258#define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
259
260#define MSS_IDX_S 60
261#define MSS_IDX_M 0xF
262#define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
263#define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
1cab775c
VP		 264
265/* option 2 fields */
d7990b0c
AB		 266#define RSS_QUEUE_S 0
267#define RSS_QUEUE_M 0x3FF
268#define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
269#define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
270
271#define RSS_QUEUE_VALID_S 10
272#define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
273#define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
274
275#define RX_FC_DISABLE_S 20
276#define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
277#define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
278
279#define RX_FC_VALID_S 22
280#define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
281#define RX_FC_VALID_F RX_FC_VALID_V(1U)
282
283#define RX_CHANNEL_S 26
284#define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
285
286#define WND_SCALE_EN_S 28
287#define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
288#define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
289
290#define T5_OPT_2_VALID_S 31
291#define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
292#define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
1cab775c 293
bbc02c7e
DM		 294struct cpl_pass_open_req {
295 WR_HDR;
296 union opcode_tid ot;
297 __be16 local_port;
298 __be16 peer_port;
299 __be32 local_ip;
300 __be32 peer_ip;
301 __be64 opt0;
bbc02c7e 302 __be64 opt1;
bbc02c7e
DM		 303};
304
6c53e938
HS		 305/* option 0 fields */
306#define NO_CONG_S 4
307#define NO_CONG_V(x) ((x) << NO_CONG_S)
308#define NO_CONG_F NO_CONG_V(1U)
309
310#define DELACK_S 5
311#define DELACK_V(x) ((x) << DELACK_S)
312#define DELACK_F DELACK_V(1U)
313
314#define DSCP_S 22
315#define DSCP_M 0x3F
316#define DSCP_V(x) ((x) << DSCP_S)
317#define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
318
319#define TCAM_BYPASS_S 48
320#define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
321#define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
322
323#define NAGLE_S 49
324#define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
325#define NAGLE_F NAGLE_V(1ULL)
326
327/* option 1 fields */
328#define SYN_RSS_ENABLE_S 0
329#define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
330#define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
331
332#define SYN_RSS_QUEUE_S 2
333#define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
334
335#define CONN_POLICY_S 22
336#define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
337
bbc02c7e
DM		 338struct cpl_pass_open_req6 {
339 WR_HDR;
340 union opcode_tid ot;
341 __be16 local_port;
342 __be16 peer_port;
343 __be64 local_ip_hi;
344 __be64 local_ip_lo;
345 __be64 peer_ip_hi;
346 __be64 peer_ip_lo;
347 __be64 opt0;
348 __be64 opt1;
349};
350
351struct cpl_pass_open_rpl {
352 union opcode_tid ot;
353 u8 rsvd[3];
354 u8 status;
355};
356
a84f0e13
VP		 357struct tcp_options {
358 __be16 mss;
359 __u8 wsf;
360#if defined(__LITTLE_ENDIAN_BITFIELD)
361 __u8:4;
362 __u8 unknown:1;
363 __u8:1;
364 __u8 sack:1;
365 __u8 tstamp:1;
366#else
367 __u8 tstamp:1;
368 __u8 sack:1;
369 __u8:1;
370 __u8 unknown:1;
371 __u8:4;
372#endif
373};
374
375struct cpl_pass_accept_req {
376 union opcode_tid ot;
377 __be16 rsvd;
378 __be16 len;
379 __be32 hdr_len;
380 __be16 vlan;
381 __be16 l2info;
382 __be32 tos_stid;
383 struct tcp_options tcpopt;
384};
385
386/* cpl_pass_accept_req.hdr_len fields */
387#define SYN_RX_CHAN_S 0
388#define SYN_RX_CHAN_M 0xF
389#define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
390#define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
391
392#define TCP_HDR_LEN_S 10
393#define TCP_HDR_LEN_M 0x3F
394#define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
395#define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
396
397#define IP_HDR_LEN_S 16
398#define IP_HDR_LEN_M 0x3FF
399#define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
400#define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
401
402#define ETH_HDR_LEN_S 26
403#define ETH_HDR_LEN_M 0x1F
404#define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
405#define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
406
407/* cpl_pass_accept_req.l2info fields */
408#define SYN_MAC_IDX_S 0
409#define SYN_MAC_IDX_M 0x1FF
410#define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
411#define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
412
413#define SYN_XACT_MATCH_S 9
414#define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
415#define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
416
417#define SYN_INTF_S 12
418#define SYN_INTF_M 0xF
419#define SYN_INTF_V(x) ((x) << SYN_INTF_S)
420#define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
421
422enum { /* TCP congestion control algorithms */
423 CONG_ALG_RENO,
424 CONG_ALG_TAHOE,
425 CONG_ALG_NEWRENO,
426 CONG_ALG_HIGHSPEED
427};
428
429#define CONG_CNTRL_S 14
430#define CONG_CNTRL_M 0x3
431#define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
432#define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
433
434#define T5_ISS_S 18
435#define T5_ISS_V(x) ((x) << T5_ISS_S)
436#define T5_ISS_F T5_ISS_V(1U)
437
bbc02c7e
DM		 438struct cpl_pass_accept_rpl {
439 WR_HDR;
440 union opcode_tid ot;
441 __be32 opt2;
bbc02c7e
DM		 442 __be64 opt0;
443};
444
6c53e938
HS		 445/* option 2 fields */
446#define RX_COALESCE_VALID_S 11
447#define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
448#define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
449
450#define RX_COALESCE_S 12
451#define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
452
453#define PACE_S 16
454#define PACE_V(x) ((x) << PACE_S)
455
456#define TX_QUEUE_S 23
457#define TX_QUEUE_M 0x7
458#define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
459#define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
460
461#define CCTRL_ECN_S 27
462#define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
463#define CCTRL_ECN_F CCTRL_ECN_V(1U)
464
465#define TSTAMPS_EN_S 29
466#define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
467#define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
468
469#define SACK_EN_S 30
470#define SACK_EN_V(x) ((x) << SACK_EN_S)
471#define SACK_EN_F SACK_EN_V(1U)
472
92e7ae71
HS		 473struct cpl_t5_pass_accept_rpl {
474 WR_HDR;
475 union opcode_tid ot;
476 __be32 opt2;
477 __be64 opt0;
478 __be32 iss;
479 __be32 rsvd;
480};
481
bbc02c7e
DM		 482struct cpl_act_open_req {
483 WR_HDR;
484 union opcode_tid ot;
485 __be16 local_port;
486 __be16 peer_port;
487 __be32 local_ip;
488 __be32 peer_ip;
489 __be64 opt0;
490 __be32 params;
491 __be32 opt2;
492};
493
d7990b0c
AB		 494#define FILTER_TUPLE_S 24
495#define FILTER_TUPLE_M 0xFFFFFFFFFF
496#define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
497#define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
2422d9a3
SR		 498struct cpl_t5_act_open_req {
499 WR_HDR;
500 union opcode_tid ot;
501 __be16 local_port;
502 __be16 peer_port;
503 __be32 local_ip;
504 __be32 peer_ip;
505 __be64 opt0;
506 __be32 rsvd;
507 __be32 opt2;
508 __be64 params;
509};
510
27999805
H		 511struct cpl_t6_act_open_req {
512 WR_HDR;
513 union opcode_tid ot;
514 __be16 local_port;
515 __be16 peer_port;
516 __be32 local_ip;
517 __be32 peer_ip;
518 __be64 opt0;
519 __be32 rsvd;
520 __be32 opt2;
521 __be64 params;
522 __be32 rsvd2;
523 __be32 opt3;
524};
525
bbc02c7e
DM		 526struct cpl_act_open_req6 {
527 WR_HDR;
528 union opcode_tid ot;
529 __be16 local_port;
530 __be16 peer_port;
531 __be64 local_ip_hi;
532 __be64 local_ip_lo;
533 __be64 peer_ip_hi;
534 __be64 peer_ip_lo;
535 __be64 opt0;
536 __be32 params;
537 __be32 opt2;
538};
539
80f40c1f
VP		 540struct cpl_t5_act_open_req6 {
541 WR_HDR;
542 union opcode_tid ot;
543 __be16 local_port;
544 __be16 peer_port;
545 __be64 local_ip_hi;
546 __be64 local_ip_lo;
547 __be64 peer_ip_hi;
548 __be64 peer_ip_lo;
549 __be64 opt0;
550 __be32 rsvd;
551 __be32 opt2;
552 __be64 params;
553};
554
27999805
H		 555struct cpl_t6_act_open_req6 {
556 WR_HDR;
557 union opcode_tid ot;
558 __be16 local_port;
559 __be16 peer_port;
560 __be64 local_ip_hi;
561 __be64 local_ip_lo;
562 __be64 peer_ip_hi;
563 __be64 peer_ip_lo;
564 __be64 opt0;
565 __be32 rsvd;
566 __be32 opt2;
567 __be64 params;
568 __be32 rsvd2;
569 __be32 opt3;
570};
571
bbc02c7e
DM		 572struct cpl_act_open_rpl {
573 union opcode_tid ot;
574 __be32 atid_status;
bbc02c7e
DM		 575};
576
6c53e938
HS		 577/* cpl_act_open_rpl.atid_status fields */
578#define AOPEN_STATUS_S 0
579#define AOPEN_STATUS_M 0xFF
580#define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
581
582#define AOPEN_ATID_S 8
583#define AOPEN_ATID_M 0xFFFFFF
584#define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
585
bbc02c7e
DM		 586struct cpl_pass_establish {
587 union opcode_tid ot;
588 __be32 rsvd;
589 __be32 tos_stid;
bbc02c7e
DM		 590 __be16 mac_idx;
591 __be16 tcp_opt;
bbc02c7e
DM		 592 __be32 snd_isn;
593 __be32 rcv_isn;
594};
595
6c53e938
HS		 596/* cpl_pass_establish.tos_stid fields */
597#define PASS_OPEN_TID_S 0
598#define PASS_OPEN_TID_M 0xFFFFFF
599#define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
600#define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
601
602#define PASS_OPEN_TOS_S 24
603#define PASS_OPEN_TOS_M 0xFF
604#define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
605#define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
606
607/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
608#define TCPOPT_WSCALE_OK_S 5
609#define TCPOPT_WSCALE_OK_M 0x1
610#define TCPOPT_WSCALE_OK_G(x) \
611 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
612
613#define TCPOPT_SACK_S 6
614#define TCPOPT_SACK_M 0x1
615#define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
616
617#define TCPOPT_TSTAMP_S 7
618#define TCPOPT_TSTAMP_M 0x1
619#define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
620
621#define TCPOPT_SND_WSCALE_S 8
622#define TCPOPT_SND_WSCALE_M 0xF
623#define TCPOPT_SND_WSCALE_G(x) \
624 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
625
626#define TCPOPT_MSS_S 12
627#define TCPOPT_MSS_M 0xF
628#define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
629
27999805
H		 630#define T6_TCP_HDR_LEN_S 8
631#define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
632#define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
633
634#define T6_IP_HDR_LEN_S 14
635#define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
636#define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
637
638#define T6_ETH_HDR_LEN_S 24
639#define T6_ETH_HDR_LEN_M 0xFF
640#define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
641#define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
642
bbc02c7e
DM		 643struct cpl_act_establish {
644 union opcode_tid ot;
645 __be32 rsvd;
646 __be32 tos_atid;
647 __be16 mac_idx;
648 __be16 tcp_opt;
649 __be32 snd_isn;
650 __be32 rcv_isn;
651};
652
653struct cpl_get_tcb {
654 WR_HDR;
655 union opcode_tid ot;
656 __be16 reply_ctrl;
bbc02c7e
DM		 657 __be16 cookie;
658};
659
bdc590b9
HS		 660/* cpl_get_tcb.reply_ctrl fields */
661#define QUEUENO_S 0
662#define QUEUENO_V(x) ((x) << QUEUENO_S)
663
664#define REPLY_CHAN_S 14
665#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
666#define REPLY_CHAN_F REPLY_CHAN_V(1U)
667
668#define NO_REPLY_S 15
669#define NO_REPLY_V(x) ((x) << NO_REPLY_S)
670#define NO_REPLY_F NO_REPLY_V(1U)
671
bbc02c7e
DM		 672struct cpl_set_tcb_field {
673 WR_HDR;
674 union opcode_tid ot;
675 __be16 reply_ctrl;
676 __be16 word_cookie;
bbc02c7e
DM		 677 __be64 mask;
678 __be64 val;
679};
680
bdc590b9
HS		 681/* cpl_set_tcb_field.word_cookie fields */
682#define TCB_WORD_S 0
683#define TCB_WORD(x) ((x) << TCB_WORD_S)
684
685#define TCB_COOKIE_S 5
686#define TCB_COOKIE_M 0x7
687#define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
688#define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
689
bbc02c7e
DM		 690struct cpl_set_tcb_rpl {
691 union opcode_tid ot;
692 __be16 rsvd;
693 u8 cookie;
694 u8 status;
695 __be64 oldval;
696};
697
698struct cpl_close_con_req {
699 WR_HDR;
700 union opcode_tid ot;
701 __be32 rsvd;
702};
703
704struct cpl_close_con_rpl {
705 union opcode_tid ot;
706 u8 rsvd[3];
707 u8 status;
708 __be32 snd_nxt;
709 __be32 rcv_nxt;
710};
711
712struct cpl_close_listsvr_req {
713 WR_HDR;
714 union opcode_tid ot;
715 __be16 reply_ctrl;
bbc02c7e
DM		 716 __be16 rsvd;
717};
718
bdc590b9
HS		 719/* additional cpl_close_listsvr_req.reply_ctrl field */
720#define LISTSVR_IPV6_S 14
721#define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
722#define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
723
bbc02c7e
DM		 724struct cpl_close_listsvr_rpl {
725 union opcode_tid ot;
726 u8 rsvd[3];
727 u8 status;
728};
729
730struct cpl_abort_req_rss {
731 union opcode_tid ot;
732 u8 rsvd[3];
733 u8 status;
734};
735
736struct cpl_abort_req {
737 WR_HDR;
738 union opcode_tid ot;
739 __be32 rsvd0;
740 u8 rsvd1;
741 u8 cmd;
742 u8 rsvd2[6];
743};
744
745struct cpl_abort_rpl_rss {
746 union opcode_tid ot;
747 u8 rsvd[3];
748 u8 status;
749};
750
751struct cpl_abort_rpl {
752 WR_HDR;
753 union opcode_tid ot;
754 __be32 rsvd0;
755 u8 rsvd1;
756 u8 cmd;
757 u8 rsvd2[6];
758};
759
760struct cpl_peer_close {
761 union opcode_tid ot;
762 __be32 rcv_nxt;
763};
764
765struct cpl_tid_release {
766 WR_HDR;
767 union opcode_tid ot;
768 __be32 rsvd;
769};
770
771struct cpl_tx_pkt_core {
772 __be32 ctrl0;
bbc02c7e
DM		 773 __be16 pack;
774 __be16 len;
775 __be64 ctrl1;
bbc02c7e
DM		 776};
777
778struct cpl_tx_pkt {
779 WR_HDR;
780 struct cpl_tx_pkt_core c;
781};
782
783#define cpl_tx_pkt_xt cpl_tx_pkt
784
1ecc7b7a
HS		 785/* cpl_tx_pkt_core.ctrl0 fields */
786#define TXPKT_VF_S 0
787#define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
788
789#define TXPKT_PF_S 8
790#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
791
792#define TXPKT_VF_VLD_S 11
793#define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
794#define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
795
796#define TXPKT_OVLAN_IDX_S 12
797#define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
798
397665da
AB		 799#define TXPKT_T5_OVLAN_IDX_S 12
800#define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
801
1ecc7b7a
HS		 802#define TXPKT_INTF_S 16
803#define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
804
805#define TXPKT_INS_OVLAN_S 21
806#define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
807#define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
808
809#define TXPKT_OPCODE_S 24
810#define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
811
812/* cpl_tx_pkt_core.ctrl1 fields */
813#define TXPKT_CSUM_END_S 12
814#define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
815
816#define TXPKT_CSUM_START_S 20
817#define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
818
819#define TXPKT_IPHDR_LEN_S 20
820#define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
821
822#define TXPKT_CSUM_LOC_S 30
823#define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
824
825#define TXPKT_ETHHDR_LEN_S 34
826#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
827
3ccc6cf7
HS		 828#define T6_TXPKT_ETHHDR_LEN_S 32
829#define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
830
1ecc7b7a
HS		 831#define TXPKT_CSUM_TYPE_S 40
832#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
833
834#define TXPKT_VLAN_S 44
835#define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
836
837#define TXPKT_VLAN_VLD_S 60
838#define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
839#define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
840
841#define TXPKT_IPCSUM_DIS_S 62
842#define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
843#define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
844
845#define TXPKT_L4CSUM_DIS_S 63
846#define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
847#define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
848
1704d748 849struct cpl_tx_pkt_lso_core {
bbc02c7e 850 __be32 lso_ctrl;
bbc02c7e
DM		 851 __be16 ipid_ofst;
852 __be16 mss;
853 __be32 seqno_offset;
854 __be32 len;
855 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
856};
857
bdc590b9
HS		 858/* cpl_tx_pkt_lso_core.lso_ctrl fields */
859#define LSO_TCPHDR_LEN_S 0
860#define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
861
862#define LSO_IPHDR_LEN_S 4
863#define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
864
865#define LSO_ETHHDR_LEN_S 16
866#define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
867
868#define LSO_IPV6_S 20
869#define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
870#define LSO_IPV6_F LSO_IPV6_V(1U)
871
872#define LSO_LAST_SLICE_S 22
873#define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
874#define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
875
876#define LSO_FIRST_SLICE_S 23
877#define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
878#define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
879
880#define LSO_OPCODE_S 24
881#define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
882
883#define LSO_T5_XFER_SIZE_S 0
884#define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
885
1704d748
CL		 886struct cpl_tx_pkt_lso {
887 WR_HDR;
888 struct cpl_tx_pkt_lso_core c;
889 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
890};
891
bbc02c7e
DM		 892struct cpl_iscsi_hdr {
893 union opcode_tid ot;
894 __be16 pdu_len_ddp;
bbc02c7e
DM		 895 __be16 len;
896 __be32 seq;
897 __be16 urg;
898 u8 rsvd;
899 u8 status;
900};
901
bdc590b9
HS		 902/* cpl_iscsi_hdr.pdu_len_ddp fields */
903#define ISCSI_PDU_LEN_S 0
904#define ISCSI_PDU_LEN_M 0x7FFF
905#define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
906#define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
907
908#define ISCSI_DDP_S 15
909#define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
910#define ISCSI_DDP_F ISCSI_DDP_V(1U)
911
76c144bd
VP		 912struct cpl_rx_data_ddp {
913 union opcode_tid ot;
914 __be16 urg;
915 __be16 len;
916 __be32 seq;
917 union {
918 __be32 nxt_seq;
919 __be32 ddp_report;
920 };
921 __be32 ulp_crc;
922 __be32 ddpvld;
923};
924
925#define cpl_rx_iscsi_ddp cpl_rx_data_ddp
926
b96c5cbb
VP		 927struct cpl_iscsi_data {
928 union opcode_tid ot;
929 __u8 rsvd0[2];
930 __be16 len;
931 __be32 seq;
932 __be16 urg;
933 __u8 rsvd1;
934 __u8 status;
935};
936
937struct cpl_tx_data_iso {
938 __be32 op_to_scsi;
939 __u8 reserved1;
940 __u8 ahs_len;
941 __be16 mpdu;
942 __be32 burst_size;
943 __be32 len;
944 __be32 reserved2_seglen_offset;
945 __be32 datasn_offset;
946 __be32 buffer_offset;
947 __be32 reserved3;
948
949 /* encapsulated CPL_TX_DATA follows here */
950};
951
952/* cpl_tx_data_iso.op_to_scsi fields */
953#define CPL_TX_DATA_ISO_OP_S 24
954#define CPL_TX_DATA_ISO_OP_M 0xff
955#define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
956#define CPL_TX_DATA_ISO_OP_G(x) \
957 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
958
959#define CPL_TX_DATA_ISO_FIRST_S 23
960#define CPL_TX_DATA_ISO_FIRST_M 0x1
961#define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
962#define CPL_TX_DATA_ISO_FIRST_G(x) \
963 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
964#define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
965
966#define CPL_TX_DATA_ISO_LAST_S 22
967#define CPL_TX_DATA_ISO_LAST_M 0x1
968#define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
969#define CPL_TX_DATA_ISO_LAST_G(x) \
970 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
971#define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
972
973#define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
974#define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
975#define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
976#define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
977 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
978#define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
979
980#define CPL_TX_DATA_ISO_HDRCRC_S 20
981#define CPL_TX_DATA_ISO_HDRCRC_M 0x1
982#define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
983#define CPL_TX_DATA_ISO_HDRCRC_G(x) \
984 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
985#define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
986
987#define CPL_TX_DATA_ISO_PLDCRC_S 19
988#define CPL_TX_DATA_ISO_PLDCRC_M 0x1
989#define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
990#define CPL_TX_DATA_ISO_PLDCRC_G(x) \
991 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
992#define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
993
994#define CPL_TX_DATA_ISO_IMMEDIATE_S 18
995#define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
996#define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
997#define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
998 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
999#define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1000
1001#define CPL_TX_DATA_ISO_SCSI_S 16
1002#define CPL_TX_DATA_ISO_SCSI_M 0x3
1003#define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1004#define CPL_TX_DATA_ISO_SCSI_G(x) \
1005 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1006
1007/* cpl_tx_data_iso.reserved2_seglen_offset fields */
1008#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1009#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1010#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1011 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1012#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1013 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1014 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1015
bbc02c7e
DM		 1016struct cpl_rx_data {
1017 union opcode_tid ot;
1018 __be16 rsvd;
1019 __be16 len;
1020 __be32 seq;
1021 __be16 urg;
1022#if defined(__LITTLE_ENDIAN_BITFIELD)
1023 u8 dack_mode:2;
1024 u8 psh:1;
1025 u8 heartbeat:1;
1026 u8 ddp_off:1;
1027 u8 :3;
1028#else
1029 u8 :3;
1030 u8 ddp_off:1;
1031 u8 heartbeat:1;
1032 u8 psh:1;
1033 u8 dack_mode:2;
1034#endif
1035 u8 status;
1036};
1037
1038struct cpl_rx_data_ack {
1039 WR_HDR;
1040 union opcode_tid ot;
1041 __be32 credit_dack;
bbc02c7e
DM		 1042};
1043
d7990b0c
AB		 1044/* cpl_rx_data_ack.ack_seq fields */
1045#define RX_CREDITS_S 0
1046#define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1047
1048#define RX_FORCE_ACK_S 28
1049#define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1050#define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1051
cb6a8ff0
VP		 1052#define RX_DACK_MODE_S 29
1053#define RX_DACK_MODE_M 0x3
1054#define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1055#define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1056
1057#define RX_DACK_CHANGE_S 31
1058#define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1059#define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1060
bbc02c7e 1061struct cpl_rx_pkt {
87b6cf51 1062 struct rss_header rsshdr;
bbc02c7e
DM		 1063 u8 opcode;
1064#if defined(__LITTLE_ENDIAN_BITFIELD)
1065 u8 iff:4;
1066 u8 csum_calc:1;
1067 u8 ipmi_pkt:1;
1068 u8 vlan_ex:1;
1069 u8 ip_frag:1;
1070#else
1071 u8 ip_frag:1;
1072 u8 vlan_ex:1;
1073 u8 ipmi_pkt:1;
1074 u8 csum_calc:1;
1075 u8 iff:4;
1076#endif
1077 __be16 csum;
1078 __be16 vlan;
1079 __be16 len;
1080 __be32 l2info;
bbc02c7e
DM		 1081 __be16 hdr_len;
1082 __be16 err_vec;
1083};
1084
27999805
H		 1085#define RX_T6_ETHHDR_LEN_M 0xFF
1086#define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1087
76fed8a9
VP		 1088#define RXF_PSH_S 20
1089#define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1090#define RXF_PSH_F RXF_PSH_V(1U)
1091
1092#define RXF_SYN_S 21
1093#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1094#define RXF_SYN_F RXF_SYN_V(1U)
1095
bdc590b9
HS		 1096#define RXF_UDP_S 22
1097#define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1098#define RXF_UDP_F RXF_UDP_V(1U)
1099
1100#define RXF_TCP_S 23
1101#define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1102#define RXF_TCP_F RXF_TCP_V(1U)
1103
1104#define RXF_IP_S 24
1105#define RXF_IP_V(x) ((x) << RXF_IP_S)
1106#define RXF_IP_F RXF_IP_V(1U)
1107
1108#define RXF_IP6_S 25
1109#define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1110#define RXF_IP6_F RXF_IP6_V(1U)
1111
76fed8a9
VP		 1112#define RXF_SYN_COOKIE_S 26
1113#define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1114#define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1115
1116#define RXF_FCOE_S 26
1117#define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1118#define RXF_FCOE_F RXF_FCOE_V(1U)
1119
1120#define RXF_LRO_S 27
1121#define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1122#define RXF_LRO_F RXF_LRO_V(1U)
1123
1cab775c 1124/* rx_pkt.l2info fields */
bdc590b9
HS		 1125#define RX_ETHHDR_LEN_S 0
1126#define RX_ETHHDR_LEN_M 0x1F
1127#define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1128#define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1129
1130#define RX_T5_ETHHDR_LEN_S 0
1131#define RX_T5_ETHHDR_LEN_M 0x3F
1132#define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1133#define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1134
1135#define RX_MACIDX_S 8
1136#define RX_MACIDX_M 0x1FF
1137#define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1138#define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1139
1140#define RXF_SYN_S 21
1141#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1142#define RXF_SYN_F RXF_SYN_V(1U)
1143
1144#define RX_CHAN_S 28
1145#define RX_CHAN_M 0xF
1146#define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1147#define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1cab775c
VP		 1148
1149/* rx_pkt.hdr_len fields */
bdc590b9
HS		 1150#define RX_TCPHDR_LEN_S 0
1151#define RX_TCPHDR_LEN_M 0x3F
1152#define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1153#define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1cab775c 1154
bdc590b9
HS		 1155#define RX_IPHDR_LEN_S 6
1156#define RX_IPHDR_LEN_M 0x3FF
1157#define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1158#define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1cab775c 1159
76fed8a9
VP		 1160/* rx_pkt.err_vec fields */
1161#define RXERR_CSUM_S 13
1162#define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1163#define RXERR_CSUM_F RXERR_CSUM_V(1U)
1164
bbc02c7e
DM		 1165struct cpl_trace_pkt {
1166 u8 opcode;
1167 u8 intf;
1168#if defined(__LITTLE_ENDIAN_BITFIELD)
1169 u8 runt:4;
1170 u8 filter_hit:4;
1171 u8 :6;
1172 u8 err:1;
1173 u8 trunc:1;
1174#else
1175 u8 filter_hit:4;
1176 u8 runt:4;
1177 u8 trunc:1;
1178 u8 err:1;
1179 u8 :6;
1180#endif
1181 __be16 rsvd;
1182 __be16 len;
1183 __be64 tstamp;
1184};
1185
2422d9a3
SR		 1186struct cpl_t5_trace_pkt {
1187 __u8 opcode;
1188 __u8 intf;
1189#if defined(__LITTLE_ENDIAN_BITFIELD)
1190 __u8 runt:4;
1191 __u8 filter_hit:4;
1192 __u8:6;
1193 __u8 err:1;
1194 __u8 trunc:1;
1195#else
1196 __u8 filter_hit:4;
1197 __u8 runt:4;
1198 __u8 trunc:1;
1199 __u8 err:1;
1200 __u8:6;
1201#endif
1202 __be16 rsvd;
1203 __be16 len;
1204 __be64 tstamp;
1205 __be64 rsvd1;
1206};
1207
bbc02c7e
DM		 1208struct cpl_l2t_write_req {
1209 WR_HDR;
1210 union opcode_tid ot;
1211 __be16 params;
bbc02c7e
DM		 1212 __be16 l2t_idx;
1213 __be16 vlan;
1214 u8 dst_mac[6];
1215};
1216
bdc590b9
HS		 1217/* cpl_l2t_write_req.params fields */
1218#define L2T_W_INFO_S 2
1219#define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1220
1221#define L2T_W_PORT_S 8
1222#define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1223
1224#define L2T_W_NOREPLY_S 15
1225#define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1226#define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1227
ac8e4c69
H		 1228#define CPL_L2T_VLAN_NONE 0xfff
1229
bbc02c7e
DM		 1230struct cpl_l2t_write_rpl {
1231 union opcode_tid ot;
1232 u8 status;
1233 u8 rsvd[3];
1234};
1235
1236struct cpl_rdma_terminate {
1237 union opcode_tid ot;
1238 __be16 rsvd;
1239 __be16 len;
1240};
1241
1242struct cpl_sge_egr_update {
1243 __be32 opcode_qid;
bbc02c7e
DM		 1244 __be16 cidx;
1245 __be16 pidx;
1246};
1247
bdc590b9
HS		 1248/* cpl_sge_egr_update.ot fields */
1249#define EGR_QID_S 0
1250#define EGR_QID_M 0x1FFFF
1251#define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1252
b407a4a9
VP		 1253/* cpl_fw*.type values */
1254enum {
1255 FW_TYPE_CMD_RPL = 0,
1256 FW_TYPE_WR_RPL = 1,
1257 FW_TYPE_CQE = 2,
1258 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1259 FW_TYPE_RSSCPL = 4,
1260};
1261
bbc02c7e
DM		 1262struct cpl_fw4_pld {
1263 u8 opcode;
1264 u8 rsvd0[3];
1265 u8 type;
1266 u8 rsvd1;
1267 __be16 len;
1268 __be64 data;
1269 __be64 rsvd2;
1270};
1271
1272struct cpl_fw6_pld {
1273 u8 opcode;
1274 u8 rsvd[5];
1275 __be16 len;
1276 __be64 data[4];
1277};
1278
1279struct cpl_fw4_msg {
1280 u8 opcode;
1281 u8 type;
1282 __be16 rsvd0;
1283 __be32 rsvd1;
1284 __be64 data[2];
1285};
1286
1287struct cpl_fw4_ack {
1288 union opcode_tid ot;
1289 u8 credits;
1290 u8 rsvd0[2];
1291 u8 seq_vld;
1292 __be32 snd_nxt;
1293 __be32 snd_una;
1294 __be64 rsvd1;
1295};
1296
b96c5cbb
VP		 1297enum {
1298 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
1299 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
1300 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
1301};
1302
bbc02c7e
DM		 1303struct cpl_fw6_msg {
1304 u8 opcode;
1305 u8 type;
1306 __be16 rsvd0;
1307 __be32 rsvd1;
1308 __be64 data[4];
1309};
1310
1704d748
CL		 1311/* cpl_fw6_msg.type values */
1312enum {
1313 FW6_TYPE_CMD_RPL = 0,
5be78ee9
VP		 1314 FW6_TYPE_WR_RPL = 1,
1315 FW6_TYPE_CQE = 2,
1316 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
b407a4a9 1317 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
5be78ee9
VP		 1318};
1319
1320struct cpl_fw6_msg_ofld_connection_wr_rpl {
1321 __u64 cookie;
1322 __be32 tid; /* or atid in case of active failure */
1323 __u8 t_state;
1324 __u8 retval;
1325 __u8 rsvd[2];
1704d748
CL		 1326};
1327
b96c5cbb
VP		 1328struct cpl_tx_data {
1329 union opcode_tid ot;
1330 __be32 len;
1331 __be32 rsvd;
1332 __be32 flags;
1333};
1334
1335/* cpl_tx_data.flags field */
1336#define TX_FORCE_S 13
1337#define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1338
bbc02c7e
DM		 1339enum {
1340 ULP_TX_MEM_READ = 2,
1341 ULP_TX_MEM_WRITE = 3,
1342 ULP_TX_PKT = 4
1343};
1344
1345enum {
1346 ULP_TX_SC_NOOP = 0x80,
1347 ULP_TX_SC_IMM = 0x81,
1348 ULP_TX_SC_DSGL = 0x82,
1349 ULP_TX_SC_ISGL = 0x83
1350};
1351
d7990b0c
AB		 1352#define ULPTX_CMD_S 24
1353#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1354
bbc02c7e
DM		 1355struct ulptx_sge_pair {
1356 __be32 len[2];
1357 __be64 addr[2];
1358};
1359
1360struct ulptx_sgl {
1361 __be32 cmd_nsge;
bbc02c7e
DM		 1362 __be32 len0;
1363 __be64 addr0;
1364 struct ulptx_sge_pair sge[0];
1365};
1366
40c46635
VP		 1367struct ulptx_idata {
1368 __be32 cmd_more;
1369 __be32 len;
1370};
1371
d6657781
HS		 1372struct ulp_txpkt {
1373 __be32 cmd_dest;
1374 __be32 len;
1375};
1376
1377#define ULPTX_CMD_S 24
1378#define ULPTX_CMD_M 0xFF
1379#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1380
bdc590b9
HS		 1381#define ULPTX_NSGE_S 0
1382#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1383
1384#define ULPTX_MORE_S 23
1385#define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1386#define ULPTX_MORE_F ULPTX_MORE_V(1U)
1387
d6657781
HS		 1388#define ULP_TXPKT_DEST_S 16
1389#define ULP_TXPKT_DEST_M 0x3
1390#define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1391
1392#define ULP_TXPKT_FID_S 4
1393#define ULP_TXPKT_FID_M 0x7ff
1394#define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1395
1396#define ULP_TXPKT_RO_S 3
1397#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1398#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1399
1400#define ULP_TX_SC_MORE_S 23
1401#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1402#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1403
bbc02c7e
DM		 1404struct ulp_mem_io {
1405 WR_HDR;
1406 __be32 cmd;
bbc02c7e
DM		 1407 __be32 len16; /* command length */
1408 __be32 dlen; /* data length in 32-byte units */
bbc02c7e 1409 __be32 lock_addr;
bbc02c7e
DM		 1410};
1411
bdc590b9
HS		 1412#define ULP_MEMIO_LOCK_S 31
1413#define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1414#define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1415
d7990b0c
AB		 1416/* additional ulp_mem_io.cmd fields */
1417#define ULP_MEMIO_ORDER_S 23
1418#define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1419#define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1420
1421#define T5_ULP_MEMIO_IMM_S 23
1422#define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1423#define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1424
bdc590b9
HS		 1425#define T5_ULP_MEMIO_ORDER_S 22
1426#define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1427#define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
42b6a949 1428
92f850ec
H		 1429#define T5_ULP_MEMIO_FID_S 4
1430#define T5_ULP_MEMIO_FID_M 0x7ff
1431#define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1432
d7990b0c
AB		 1433/* ulp_mem_io.lock_addr fields */
1434#define ULP_MEMIO_ADDR_S 0
1435#define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1436
1437/* ulp_mem_io.dlen fields */
1438#define ULP_MEMIO_DATA_LEN_S 0
1439#define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1440
d6657781
HS		 1441#define ULPTX_NSGE_S 0
1442#define ULPTX_NSGE_M 0xFFFF
1443#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1444#define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1445
1446struct ulptx_sc_memrd {
1447 __be32 cmd_to_len;
1448 __be32 addr;
1449};
1450
1451#define ULP_TXPKT_DATAMODIFY_S 23
1452#define ULP_TXPKT_DATAMODIFY_M 0x1
1453#define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1454#define ULP_TXPKT_DATAMODIFY_G(x) \
1455 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1456#define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1457
1458#define ULP_TXPKT_CHANNELID_S 22
1459#define ULP_TXPKT_CHANNELID_M 0x1
1460#define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1461#define ULP_TXPKT_CHANNELID_G(x) \
1462 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1463#define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1464
1465#define SCMD_SEQ_NO_CTRL_S 29
1466#define SCMD_SEQ_NO_CTRL_M 0x3
1467#define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1468#define SCMD_SEQ_NO_CTRL_G(x) \
1469 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1470
1471/* StsFieldPrsnt- Status field at the end of the TLS PDU */
1472#define SCMD_STATUS_PRESENT_S 28
1473#define SCMD_STATUS_PRESENT_M 0x1
1474#define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1475#define SCMD_STATUS_PRESENT_G(x) \
1476 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1477#define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1478
1479/* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
1480 * 3-15: Reserved.
1481 */
1482#define SCMD_PROTO_VERSION_S 24
1483#define SCMD_PROTO_VERSION_M 0xf
1484#define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1485#define SCMD_PROTO_VERSION_G(x) \
1486 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1487
1488/* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
1489#define SCMD_ENC_DEC_CTRL_S 23
1490#define SCMD_ENC_DEC_CTRL_M 0x1
1491#define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1492#define SCMD_ENC_DEC_CTRL_G(x) \
1493 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1494#define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1495
1496/* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
1497#define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1498#define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1499#define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1500 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1501#define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1502 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1503#define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1504
1505/* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
1506 * 4:Generic-AES, 5-15: Reserved.
1507 */
1508#define SCMD_CIPH_MODE_S 18
1509#define SCMD_CIPH_MODE_M 0xf
1510#define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1511#define SCMD_CIPH_MODE_G(x) \
1512 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1513
1514/* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
1515 * 4-15: Reserved
1516 */
1517#define SCMD_AUTH_MODE_S 14
1518#define SCMD_AUTH_MODE_M 0xf
1519#define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1520#define SCMD_AUTH_MODE_G(x) \
1521 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1522
1523/* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
1524 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved
1525 */
1526#define SCMD_HMAC_CTRL_S 11
1527#define SCMD_HMAC_CTRL_M 0x7
1528#define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1529#define SCMD_HMAC_CTRL_G(x) \
1530 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1531
1532/* IvSize - IV size in units of 2 bytes */
1533#define SCMD_IV_SIZE_S 7
1534#define SCMD_IV_SIZE_M 0xf
1535#define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1536#define SCMD_IV_SIZE_G(x) \
1537 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1538
1539/* NumIVs - Number of IVs */
1540#define SCMD_NUM_IVS_S 0
1541#define SCMD_NUM_IVS_M 0x7f
1542#define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1543#define SCMD_NUM_IVS_G(x) \
1544 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1545
1546/* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber
1547 * (below) are used as Cid (connection id for debug status), these
1548 * bits are padded to zero for forming the 64 bit
1549 * sequence number for TLS
1550 */
1551#define SCMD_ENB_DBGID_S 31
1552#define SCMD_ENB_DBGID_M 0x1
1553#define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1554#define SCMD_ENB_DBGID_G(x) \
1555 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1556
1557/* IV generation in SW. */
1558#define SCMD_IV_GEN_CTRL_S 30
1559#define SCMD_IV_GEN_CTRL_M 0x1
1560#define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1561#define SCMD_IV_GEN_CTRL_G(x) \
1562 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1563#define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1564
1565/* More frags */
1566#define SCMD_MORE_FRAGS_S 20
1567#define SCMD_MORE_FRAGS_M 0x1
1568#define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1569#define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1570
1571/*last frag */
1572#define SCMD_LAST_FRAG_S 19
1573#define SCMD_LAST_FRAG_M 0x1
1574#define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1575#define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1576
1577/* TlsCompPdu */
1578#define SCMD_TLS_COMPPDU_S 18
1579#define SCMD_TLS_COMPPDU_M 0x1
1580#define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1581#define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1582
1583/* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/
1584#define SCMD_KEY_CTX_INLINE_S 17
1585#define SCMD_KEY_CTX_INLINE_M 0x1
1586#define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1587#define SCMD_KEY_CTX_INLINE_G(x) \
1588 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1589#define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1590
1591/* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
1592#define SCMD_TLS_FRAG_ENABLE_S 16
1593#define SCMD_TLS_FRAG_ENABLE_M 0x1
1594#define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1595#define SCMD_TLS_FRAG_ENABLE_G(x) \
1596 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1597#define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1598
1599/* MacOnly - Only send the MAC and discard PDU. This is valid for hash only
1600 * modes, in this case TLS_TX will drop the PDU and only
1601 * send back the MAC bytes.
1602 */
1603#define SCMD_MAC_ONLY_S 15
1604#define SCMD_MAC_ONLY_M 0x1
1605#define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1606#define SCMD_MAC_ONLY_G(x) \
1607 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1608#define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1609
1610/* AadIVDrop - Drop the AAD and IV fields. Useful in protocols
1611 * which have complex AAD and IV formations Eg:AES-CCM
1612 */
1613#define SCMD_AADIVDROP_S 14
1614#define SCMD_AADIVDROP_M 0x1
1615#define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1616#define SCMD_AADIVDROP_G(x) \
1617 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1618#define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1619
1620/* HdrLength - Length of all headers excluding TLS header
1621 * present before start of crypto PDU/payload.
1622 */
1623#define SCMD_HDR_LEN_S 0
1624#define SCMD_HDR_LEN_M 0x3fff
1625#define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1626#define SCMD_HDR_LEN_G(x) \
1627 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1628
1629struct cpl_tx_sec_pdu {
1630 __be32 op_ivinsrtofst;
1631 __be32 pldlen;
1632 __be32 aadstart_cipherstop_hi;
1633 __be32 cipherstop_lo_authinsert;
1634 __be32 seqno_numivs;
1635 __be32 ivgen_hdrlen;
1636 __be64 scmd1;
1637};
1638
1639#define CPL_TX_SEC_PDU_OPCODE_S 24
1640#define CPL_TX_SEC_PDU_OPCODE_M 0xff
1641#define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1642#define CPL_TX_SEC_PDU_OPCODE_G(x) \
1643 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1644
1645/* RX Channel Id */
1646#define CPL_TX_SEC_PDU_RXCHID_S 22
1647#define CPL_TX_SEC_PDU_RXCHID_M 0x1
1648#define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1649#define CPL_TX_SEC_PDU_RXCHID_G(x) \
1650 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1651#define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1652
1653/* Ack Follows */
1654#define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1655#define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1656#define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1657#define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1658 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1659#define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1660
1661/* Loopback bit in cpl_tx_sec_pdu */
1662#define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1663#define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1664#define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1665#define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1666 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1667#define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1668
1669/* Length of cpl header encapsulated */
1670#define CPL_TX_SEC_PDU_CPLLEN_S 16
1671#define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1672#define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1673#define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1674 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1675
1676/* PlaceHolder */
1677#define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1678#define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1679#define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1680#define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1681 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1682 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1683
1684/* IvInsrtOffset: Insertion location for IV */
1685#define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1686#define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1687#define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1688#define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1689 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1690 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1691
1692/* AadStartOffset: Offset in bytes for AAD start from
1693 * the first byte following the pkt headers (0-255 bytes)
1694 */
1695#define CPL_TX_SEC_PDU_AADSTART_S 24
1696#define CPL_TX_SEC_PDU_AADSTART_M 0xff
1697#define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1698#define CPL_TX_SEC_PDU_AADSTART_G(x) \
1699 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1700 CPL_TX_SEC_PDU_AADSTART_M)
1701
1702/* AadStopOffset: offset in bytes for AAD stop/end from the first byte following
1703 * the pkt headers (0-511 bytes)
1704 */
1705#define CPL_TX_SEC_PDU_AADSTOP_S 15
1706#define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
1707#define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
1708#define CPL_TX_SEC_PDU_AADSTOP_G(x) \
1709 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
1710
1711/* CipherStartOffset: offset in bytes for encryption/decryption start from the
1712 * first byte following the pkt headers (0-1023 bytes)
1713 */
1714#define CPL_TX_SEC_PDU_CIPHERSTART_S 5
1715#define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
1716#define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
1717#define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
1718 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
1719 CPL_TX_SEC_PDU_CIPHERSTART_M)
1720
1721/* CipherStopOffset: offset in bytes for encryption/decryption end
1722 * from end of the payload of this command (0-511 bytes)
1723 */
1724#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
1725#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
1726#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
1727 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
1728#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
1729 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
1730 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
1731
1732#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
1733#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
1734#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
1735 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
1736#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
1737 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
1738 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
1739
1740/* AuthStartOffset: offset in bytes for authentication start from
1741 * the first byte following the pkt headers (0-1023)
1742 */
1743#define CPL_TX_SEC_PDU_AUTHSTART_S 18
1744#define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
1745#define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
1746#define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
1747 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
1748 CPL_TX_SEC_PDU_AUTHSTART_M)
1749
1750/* AuthStopOffset: offset in bytes for authentication
1751 * end from end of the payload of this command (0-511 Bytes)
1752 */
1753#define CPL_TX_SEC_PDU_AUTHSTOP_S 9
1754#define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
1755#define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
1756#define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
1757 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
1758 CPL_TX_SEC_PDU_AUTHSTOP_M)
1759
1760/* AuthInsrtOffset: offset in bytes for authentication insertion
1761 * from end of the payload of this command (0-511 bytes)
1762 */
1763#define CPL_TX_SEC_PDU_AUTHINSERT_S 0
1764#define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
1765#define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
1766#define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
1767 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
1768 CPL_TX_SEC_PDU_AUTHINSERT_M)
1769
1770struct cpl_rx_phys_dsgl {
1771 __be32 op_to_tid;
1772 __be32 pcirlxorder_to_noofsgentr;
1773 struct rss_header rss_hdr_int;
1774};
1775
1776#define CPL_RX_PHYS_DSGL_OPCODE_S 24
1777#define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
1778#define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
1779#define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
1780 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
1781
1782#define CPL_RX_PHYS_DSGL_ISRDMA_S 23
1783#define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
1784#define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
1785#define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
1786 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
1787#define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
1788
1789#define CPL_RX_PHYS_DSGL_RSVD1_S 20
1790#define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
1791#define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
1792#define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
1793 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
1794 CPL_RX_PHYS_DSGL_RSVD1_M)
1795
1796#define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
1797#define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
1798#define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
1799 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
1800#define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
1801 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
1802 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
1803#define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
1804
1805#define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
1806#define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
1807#define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
1808 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
1809#define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
1810 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
1811 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
1812
1813#define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
1814
1815#define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
1816#define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
1817#define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
1818 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
1819#define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
1820 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
1821 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
1822#define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
1823
1824#define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
1825#define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
1826#define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
1827#define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
1828 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
1829 CPL_RX_PHYS_DSGL_PCITPHNT_M)
1830
1831#define CPL_RX_PHYS_DSGL_DCAID_S 16
1832#define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
1833#define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
1834#define CPL_RX_PHYS_DSGL_DCAID_G(x) \
1835 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
1836 CPL_RX_PHYS_DSGL_DCAID_M)
1837
1838#define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
1839#define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
1840#define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
1841 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
1842#define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
1843 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
1844 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
1845
bbc02c7e 1846#endif /* __T4_MSG_H */
Linux kernel - Deliverables
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