[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4vf / t4vf_common.h

/*
 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
 * driver for Linux.
 *
 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __T4VF_COMMON_H__
#define __T4VF_COMMON_H__

#include "../cxgb4/t4_hw.h"
#include "../cxgb4/t4fw_api.h"

#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)

/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
 *
 *   V  = "4" for T4; "5" for T5, etc. or
 *      = "a" for T4 FPGA; "b" for T4 FPGA, etc.
 *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
 *   PP = adapter product designation
 */
#define CHELSIO_T4		0x4
#define CHELSIO_T5		0x5
#define CHELSIO_T6		0x6

enum chip_type {
	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
	T4_FIRST_REV	= T4_A1,
	T4_LAST_REV	= T4_A2,

	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	T5_FIRST_REV	= T5_A0,
	T5_LAST_REV	= T5_A1,
};

/*
 * The "len16" field of a Firmware Command Structure ...
 */
#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)

/*
 * Per-VF statistics.
 */
struct t4vf_port_stats {
	/*
	 * TX statistics.
	 */
	u64 tx_bcast_bytes;		/* broadcast */
	u64 tx_bcast_frames;
	u64 tx_mcast_bytes;		/* multicast */
	u64 tx_mcast_frames;
	u64 tx_ucast_bytes;		/* unicast */
	u64 tx_ucast_frames;
	u64 tx_drop_frames;		/* TX dropped frames */
	u64 tx_offload_bytes;		/* offload */
	u64 tx_offload_frames;

	/*
	 * RX statistics.
	 */
	u64 rx_bcast_bytes;		/* broadcast */
	u64 rx_bcast_frames;
	u64 rx_mcast_bytes;		/* multicast */
	u64 rx_mcast_frames;
	u64 rx_ucast_bytes;
	u64 rx_ucast_frames;		/* unicast */

	u64 rx_err_frames;		/* RX error frames */
};

/*
 * Per-"port" (Virtual Interface) link configuration ...
 */
struct link_config {
	unsigned int   supported;        /* link capabilities */
	unsigned int   advertising;      /* advertised capabilities */
	unsigned short lp_advertising;   /* peer advertised capabilities */
	unsigned int   requested_speed;  /* speed user has requested */
	unsigned int   speed;            /* actual link speed */
	unsigned char  requested_fc;     /* flow control user has requested */
	unsigned char  fc;               /* actual link flow control */
	unsigned char  autoneg;          /* autonegotiating? */
	unsigned char  link_ok;          /* link up? */
};

enum {
	PAUSE_RX      = 1 << 0,
	PAUSE_TX      = 1 << 1,
	PAUSE_AUTONEG = 1 << 2
};

/*
 * General device parameters ...
 */
struct dev_params {
	u32 fwrev;			/* firmware version */
	u32 tprev;			/* TP Microcode Version */
};

/*
 * Scatter Gather Engine parameters.  These are almost all determined by the
 * Physical Function Driver.  We just need to grab them to see within which
 * environment we're playing ...
 */
struct sge_params {
	u32 sge_control;		/* padding, boundaries, lengths, etc. */
	u32 sge_control2;		/* T5: more of the same */
	u32 sge_host_page_size;		/* PF0-7 page sizes */
	u32 sge_egress_queues_per_page;	/* PF0-7 egress queues/page */
	u32 sge_ingress_queues_per_page;/* PF0-7 ingress queues/page */
	u32 sge_vf_hps;                 /* host page size for our vf */
	u32 sge_vf_eq_qpp;		/* egress queues/page for our VF */
	u32 sge_vf_iq_qpp;		/* ingress queues/page for our VF */
	u32 sge_fl_buffer_size[16];	/* free list buffer sizes */
	u32 sge_ingress_rx_threshold;	/* RX counter interrupt threshold[4] */
	u32 sge_congestion_control;     /* congestion thresholds, etc. */
	u32 sge_timer_value_0_and_1;	/* interrupt coalescing timer values */
	u32 sge_timer_value_2_and_3;
	u32 sge_timer_value_4_and_5;
};

/*
 * Vital Product Data parameters.
 */
struct vpd_params {
	u32 cclk;			/* Core Clock (KHz) */
};

/* Stores chip specific parameters */
struct arch_specific_params {
	u32 sge_fl_db;
	u16 mps_tcam_size;
};

/*
 * Global Receive Side Scaling (RSS) parameters in host-native format.
 */
struct rss_params {
	unsigned int mode;		/* RSS mode */
	union {
	    struct {
		unsigned int synmapen:1;	/* SYN Map Enable */
		unsigned int syn4tupenipv6:1;	/* enable hashing 4-tuple IPv6 SYNs */
		unsigned int syn2tupenipv6:1;	/* enable hashing 2-tuple IPv6 SYNs */
		unsigned int syn4tupenipv4:1;	/* enable hashing 4-tuple IPv4 SYNs */
		unsigned int syn2tupenipv4:1;	/* enable hashing 2-tuple IPv4 SYNs */
		unsigned int ofdmapen:1;	/* Offload Map Enable */
		unsigned int tnlmapen:1;	/* Tunnel Map Enable */
		unsigned int tnlalllookup:1;	/* Tunnel All Lookup */
		unsigned int hashtoeplitz:1;	/* use Toeplitz hash */
	    } basicvirtual;
	} u;
};

/*
 * Virtual Interface RSS Configuration in host-native format.
 */
union rss_vi_config {
    struct {
	u16 defaultq;			/* Ingress Queue ID for !tnlalllookup */
	unsigned int ip6fourtupen:1;	/* hash 4-tuple IPv6 ingress packets */
	unsigned int ip6twotupen:1;	/* hash 2-tuple IPv6 ingress packets */
	unsigned int ip4fourtupen:1;	/* hash 4-tuple IPv4 ingress packets */
	unsigned int ip4twotupen:1;	/* hash 2-tuple IPv4 ingress packets */
	int udpen;			/* hash 4-tuple UDP ingress packets */
    } basicvirtual;
};

/*
 * Maximum resources provisioned for a PCI VF.
 */
struct vf_resources {
	unsigned int nvi;		/* N virtual interfaces */
	unsigned int neq;		/* N egress Qs */
	unsigned int nethctrl;		/* N egress ETH or CTRL Qs */
	unsigned int niqflint;		/* N ingress Qs/w free list(s) & intr */
	unsigned int niq;		/* N ingress Qs */
	unsigned int tc;		/* PCI-E traffic class */
	unsigned int pmask;		/* port access rights mask */
	unsigned int nexactf;		/* N exact MPS filters */
	unsigned int r_caps;		/* read capabilities */
	unsigned int wx_caps;		/* write/execute capabilities */
};

/*
 * Per-"adapter" (Virtual Function) parameters.
 */
struct adapter_params {
	struct dev_params dev;		/* general device parameters */
	struct sge_params sge;		/* Scatter Gather Engine */
	struct vpd_params vpd;		/* Vital Product Data */
	struct rss_params rss;		/* Receive Side Scaling */
	struct vf_resources vfres;	/* Virtual Function Resource limits */
	struct arch_specific_params arch; /* chip specific params */
	enum chip_type chip;		/* chip code */
	u8 nports;			/* # of Ethernet "ports" */
};

/* Firmware Mailbox Command/Reply log.  All values are in Host-Endian format.
 * The access and execute times are signed in order to accommodate negative
 * error returns.
 */
struct mbox_cmd {
	u64 cmd[MBOX_LEN / 8];		/* a Firmware Mailbox Command/Reply */
	u64 timestamp;			/* OS-dependent timestamp */
	u32 seqno;			/* sequence number */
	s16 access;			/* time (ms) to access mailbox */
	s16 execute;			/* time (ms) to execute */
};

struct mbox_cmd_log {
	unsigned int size;		/* number of entries in the log */
	unsigned int cursor;		/* next position in the log to write */
	u32 seqno;			/* next sequence number */
	/* variable length mailbox command log starts here */
};

/* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
 * return a pointer to the specified entry.
 */
static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
						  unsigned int entry_idx)
{
	return &((struct mbox_cmd *)&(log)[1])[entry_idx];
}

#include "adapter.h"

#ifndef PCI_VENDOR_ID_CHELSIO
# define PCI_VENDOR_ID_CHELSIO 0x1425
#endif

#define for_each_port(adapter, iter) \
	for (iter = 0; iter < (adapter)->params.nports; iter++)

static inline bool is_10g_port(const struct link_config *lc)
{
	return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
}

/* Return true if the Link Configuration supports "High Speeds" (those greater
 * than 1Gb/s).
 */
static inline bool is_x_10g_port(const struct link_config *lc)
{
	unsigned int speeds, high_speeds;

	speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported));
	high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);

	return high_speeds != 0;
}

static inline unsigned int core_ticks_per_usec(const struct adapter *adapter)
{
	return adapter->params.vpd.cclk / 1000;
}

static inline unsigned int us_to_core_ticks(const struct adapter *adapter,
					    unsigned int us)
{
	return (us * adapter->params.vpd.cclk) / 1000;
}

static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
					    unsigned int ticks)
{
	return (ticks * 1000) / adapter->params.vpd.cclk;
}

int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);

static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
			       int size, void *rpl)
{
	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
}

static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
				  int size, void *rpl)
{
	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
}

#define CHELSIO_PCI_ID_VER(dev_id)  ((dev_id) >> 12)

static inline int is_t4(enum chip_type chip)
{
	return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
}

/**
 *	hash_mac_addr - return the hash value of a MAC address
 *	@addr: the 48-bit Ethernet MAC address
 *
 *	Hashes a MAC address according to the hash function used by hardware
 *	inexact (hash) address matching.
 */
static inline int hash_mac_addr(const u8 *addr)
{
	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];

	a ^= b;
	a ^= (a >> 12);
	a ^= (a >> 6);
	return a & 0x3f;
}

int t4vf_wait_dev_ready(struct adapter *);
int t4vf_port_init(struct adapter *, int);

int t4vf_fw_reset(struct adapter *);
int t4vf_set_params(struct adapter *, unsigned int, const u32 *, const u32 *);

int t4vf_fl_pkt_align(struct adapter *adapter);
enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
int t4vf_bar2_sge_qregs(struct adapter *adapter,
			unsigned int qid,
			enum t4_bar2_qtype qtype,
			u64 *pbar2_qoffset,
			unsigned int *pbar2_qid);

int t4vf_get_sge_params(struct adapter *);
int t4vf_get_vpd_params(struct adapter *);
int t4vf_get_dev_params(struct adapter *);
int t4vf_get_rss_glb_config(struct adapter *);
int t4vf_get_vfres(struct adapter *);

int t4vf_read_rss_vi_config(struct adapter *, unsigned int,
			    union rss_vi_config *);
int t4vf_write_rss_vi_config(struct adapter *, unsigned int,
			     union rss_vi_config *);
int t4vf_config_rss_range(struct adapter *, unsigned int, int, int,
			  const u16 *, int);

int t4vf_alloc_vi(struct adapter *, int);
int t4vf_free_vi(struct adapter *, int);
int t4vf_enable_vi(struct adapter *, unsigned int, bool, bool);
int t4vf_identify_port(struct adapter *, unsigned int, unsigned int);

int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int,
		    bool);
int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int,
			const u8 **, u16 *, u64 *, bool);
int t4vf_free_mac_filt(struct adapter *, unsigned int, unsigned int naddr,
		       const u8 **, bool);
int t4vf_change_mac(struct adapter *, unsigned int, int, const u8 *, bool);
int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool);
int t4vf_get_port_stats(struct adapter *, int, struct t4vf_port_stats *);

int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int,
		 unsigned int);
int t4vf_eth_eq_free(struct adapter *, unsigned int);

int t4vf_handle_fw_rpl(struct adapter *, const __be64 *);
int t4vf_prep_adapter(struct adapter *);

#endif /* __T4VF_COMMON_H__ */
Commit	Line	Data
16f8bd4b CL	1	/*
	2	* This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
	3	* driver for Linux.
	4	*
	5	* Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
	6	*
	7	* This software is available to you under a choice of one of two
	8	* licenses. You may choose to be licensed under the terms of the GNU
	9	* General Public License (GPL) Version 2, available from the file
	10	* COPYING in the main directory of this source tree, or the
	11	* OpenIB.org BSD license below:
	12	*
	13	* Redistribution and use in source and binary forms, with or
	14	* without modification, are permitted provided that the following
	15	* conditions are met:
	16	*
	17	* - Redistributions of source code must retain the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer.
	20	*
	21	* - Redistributions in binary form must reproduce the above
	22	* copyright notice, this list of conditions and the following
	23	* disclaimer in the documentation and/or other materials
	24	* provided with the distribution.
	25	*
	26	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	27	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	28	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	29	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	30	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	31	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	32	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	33	* SOFTWARE.
	34	*/
	35
	36	#ifndef __T4VF_COMMON_H__
	37	#define __T4VF_COMMON_H__
	38
ae7b7576	39	#include "../cxgb4/t4_hw.h"
16f8bd4b CL	40	#include "../cxgb4/t4fw_api.h"
16f8bd4b CL	41
622c62b5	42	#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) \| (revision))
70ee3666	43	#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
622c62b5 SR	44	#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
622c62b5 SR	45
70ee3666 HS	46	/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
	47	*
	48	* V = "4" for T4; "5" for T5, etc. or
	49	* = "a" for T4 FPGA; "b" for T4 FPGA, etc.
	50	* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
	51	* PP = adapter product designation
	52	*/
622c62b5 SR	53	#define CHELSIO_T4 0x4
622c62b5 SR	54	#define CHELSIO_T5 0x5
41fc2e41	55	#define CHELSIO_T6 0x6
622c62b5 SR	56
622c62b5 SR	57	enum chip_type {
70ee3666 HS	58	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
70ee3666 HS	59	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
622c62b5	60	T4_FIRST_REV = T4_A1,
70ee3666	61	T4_LAST_REV = T4_A2,
622c62b5	62
70ee3666 HS	63	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
	64	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
	65	T5_FIRST_REV = T5_A0,
622c62b5 SR	66	T5_LAST_REV = T5_A1,
	67	};
	68
16f8bd4b CL	69	/*
	70	* The "len16" field of a Firmware Command Structure ...
	71	*/
e2ac9628	72	#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
16f8bd4b CL	73
	74	/*
	75	* Per-VF statistics.
	76	*/
	77	struct t4vf_port_stats {
	78	/*
	79	* TX statistics.
	80	*/
	81	u64 tx_bcast_bytes; /* broadcast */
	82	u64 tx_bcast_frames;
	83	u64 tx_mcast_bytes; /* multicast */
	84	u64 tx_mcast_frames;
	85	u64 tx_ucast_bytes; /* unicast */
	86	u64 tx_ucast_frames;
	87	u64 tx_drop_frames; /* TX dropped frames */
	88	u64 tx_offload_bytes; /* offload */
	89	u64 tx_offload_frames;
	90
	91	/*
	92	* RX statistics.
	93	*/
	94	u64 rx_bcast_bytes; /* broadcast */
	95	u64 rx_bcast_frames;
	96	u64 rx_mcast_bytes; /* multicast */
	97	u64 rx_mcast_frames;
	98	u64 rx_ucast_bytes;
	99	u64 rx_ucast_frames; /* unicast */
	100
	101	u64 rx_err_frames; /* RX error frames */
	102	};
	103
	104	/*
	105	* Per-"port" (Virtual Interface) link configuration ...
	106	*/
	107	struct link_config {
	108	unsigned int supported; /* link capabilities */
	109	unsigned int advertising; /* advertised capabilities */
eb97ad99	110	unsigned short lp_advertising; /* peer advertised capabilities */
9b86a8d1 HS	111	unsigned int requested_speed; /* speed user has requested */
9b86a8d1 HS	112	unsigned int speed; /* actual link speed */
16f8bd4b CL	113	unsigned char requested_fc; /* flow control user has requested */
	114	unsigned char fc; /* actual link flow control */
	115	unsigned char autoneg; /* autonegotiating? */
	116	unsigned char link_ok; /* link up? */
	117	};
	118
	119	enum {
	120	PAUSE_RX = 1 << 0,
	121	PAUSE_TX = 1 << 1,
	122	PAUSE_AUTONEG = 1 << 2
	123	};
	124
	125	/*
	126	* General device parameters ...
	127	*/
	128	struct dev_params {
	129	u32 fwrev; /* firmware version */
	130	u32 tprev; /* TP Microcode Version */
	131	};
	132
	133	/*
	134	* Scatter Gather Engine parameters. These are almost all determined by the
	135	* Physical Function Driver. We just need to grab them to see within which
	136	* environment we're playing ...
	137	*/
	138	struct sge_params {
	139	u32 sge_control; /* padding, boundaries, lengths, etc. */
ce8f407a	140	u32 sge_control2; /* T5: more of the same */
e0a8b34a HS	141	u32 sge_host_page_size; /* PF0-7 page sizes */
	142	u32 sge_egress_queues_per_page; /* PF0-7 egress queues/page */
	143	u32 sge_ingress_queues_per_page;/* PF0-7 ingress queues/page */
e85c9a7a	144	u32 sge_vf_hps; /* host page size for our vf */
e0a8b34a HS	145	u32 sge_vf_eq_qpp; /* egress queues/page for our VF */
e0a8b34a HS	146	u32 sge_vf_iq_qpp; /* ingress queues/page for our VF */
16f8bd4b CL	147	u32 sge_fl_buffer_size[16]; /* free list buffer sizes */
16f8bd4b CL	148	u32 sge_ingress_rx_threshold; /* RX counter interrupt threshold[4] */
50d21a66	149	u32 sge_congestion_control; /* congestion thresholds, etc. */
16f8bd4b CL	150	u32 sge_timer_value_0_and_1; /* interrupt coalescing timer values */
	151	u32 sge_timer_value_2_and_3;
	152	u32 sge_timer_value_4_and_5;
	153	};
	154
	155	/*
	156	* Vital Product Data parameters.
	157	*/
	158	struct vpd_params {
	159	u32 cclk; /* Core Clock (KHz) */
	160	};
	161
41fc2e41 HS	162	/* Stores chip specific parameters */
	163	struct arch_specific_params {
	164	u32 sge_fl_db;
	165	u16 mps_tcam_size;
	166	};
	167
16f8bd4b CL	168	/*
	169	* Global Receive Side Scaling (RSS) parameters in host-native format.
	170	*/
	171	struct rss_params {
	172	unsigned int mode; /* RSS mode */
	173	union {
	174	struct {
65495745 HH	175	unsigned int synmapen:1; /* SYN Map Enable */
	176	unsigned int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
	177	unsigned int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
	178	unsigned int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
	179	unsigned int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
	180	unsigned int ofdmapen:1; /* Offload Map Enable */
	181	unsigned int tnlmapen:1; /* Tunnel Map Enable */
	182	unsigned int tnlalllookup:1; /* Tunnel All Lookup */
	183	unsigned int hashtoeplitz:1; /* use Toeplitz hash */
16f8bd4b CL	184	} basicvirtual;
	185	} u;
	186	};
	187
	188	/*
	189	* Virtual Interface RSS Configuration in host-native format.
	190	*/
	191	union rss_vi_config {
	192	struct {
	193	u16 defaultq; /* Ingress Queue ID for !tnlalllookup */
65495745 HH	194	unsigned int ip6fourtupen:1; /* hash 4-tuple IPv6 ingress packets */
	195	unsigned int ip6twotupen:1; /* hash 2-tuple IPv6 ingress packets */
	196	unsigned int ip4fourtupen:1; /* hash 4-tuple IPv4 ingress packets */
	197	unsigned int ip4twotupen:1; /* hash 2-tuple IPv4 ingress packets */
16f8bd4b CL	198	int udpen; /* hash 4-tuple UDP ingress packets */
	199	} basicvirtual;
	200	};
	201
	202	/*
	203	* Maximum resources provisioned for a PCI VF.
	204	*/
	205	struct vf_resources {
	206	unsigned int nvi; /* N virtual interfaces */
	207	unsigned int neq; /* N egress Qs */
	208	unsigned int nethctrl; /* N egress ETH or CTRL Qs */
	209	unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
	210	unsigned int niq; /* N ingress Qs */
	211	unsigned int tc; /* PCI-E traffic class */
	212	unsigned int pmask; /* port access rights mask */
	213	unsigned int nexactf; /* N exact MPS filters */
	214	unsigned int r_caps; /* read capabilities */
	215	unsigned int wx_caps; /* write/execute capabilities */
	216	};
	217
	218	/*
	219	* Per-"adapter" (Virtual Function) parameters.
	220	*/
	221	struct adapter_params {
	222	struct dev_params dev; /* general device parameters */
	223	struct sge_params sge; /* Scatter Gather Engine */
	224	struct vpd_params vpd; /* Vital Product Data */
	225	struct rss_params rss; /* Receive Side Scaling */
	226	struct vf_resources vfres; /* Virtual Function Resource limits */
41fc2e41	227	struct arch_specific_params arch; /* chip specific params */
70ee3666	228	enum chip_type chip; /* chip code */
16f8bd4b CL	229	u8 nports; /* # of Ethernet "ports" */
	230	};
	231
ae7b7576 HS	232	/* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
	233	* The access and execute times are signed in order to accommodate negative
	234	* error returns.
	235	*/
	236	struct mbox_cmd {
	237	u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
	238	u64 timestamp; /* OS-dependent timestamp */
	239	u32 seqno; /* sequence number */
	240	s16 access; /* time (ms) to access mailbox */
	241	s16 execute; /* time (ms) to execute */
	242	};
	243
	244	struct mbox_cmd_log {
	245	unsigned int size; /* number of entries in the log */
	246	unsigned int cursor; /* next position in the log to write */
	247	u32 seqno; /* next sequence number */
	248	/* variable length mailbox command log starts here */
	249	};
	250
	251	/* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
	252	* return a pointer to the specified entry.
	253	*/
	254	static inline struct mbox_cmd mbox_cmd_log_entry(struct mbox_cmd_log log,
	255	unsigned int entry_idx)
	256	{
	257	return &((struct mbox_cmd *)&(log)[1])[entry_idx];
	258	}
	259
16f8bd4b CL	260	#include "adapter.h"
	261
	262	#ifndef PCI_VENDOR_ID_CHELSIO
	263	# define PCI_VENDOR_ID_CHELSIO 0x1425
	264	#endif
	265
	266	#define for_each_port(adapter, iter) \
	267	for (iter = 0; iter < (adapter)->params.nports; iter++)
	268
	269	static inline bool is_10g_port(const struct link_config *lc)
	270	{
5ad24def	271	return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0;
16f8bd4b CL	272	}
16f8bd4b CL	273
9b86a8d1 HS	274	/* Return true if the Link Configuration supports "High Speeds" (those greater
	275	* than 1Gb/s).
	276	*/
897d55df HS	277	static inline bool is_x_10g_port(const struct link_config *lc)
897d55df HS	278	{
9b86a8d1 HS	279	unsigned int speeds, high_speeds;
	280
	281	speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported));
	282	high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M \| FW_PORT_CAP_SPEED_1G);
	283
	284	return high_speeds != 0;
897d55df HS	285	}
897d55df HS	286
16f8bd4b CL	287	static inline unsigned int core_ticks_per_usec(const struct adapter *adapter)
	288	{
	289	return adapter->params.vpd.cclk / 1000;
	290	}
	291
	292	static inline unsigned int us_to_core_ticks(const struct adapter *adapter,
	293	unsigned int us)
	294	{
	295	return (us * adapter->params.vpd.cclk) / 1000;
	296	}
	297
	298	static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
	299	unsigned int ticks)
	300	{
	301	return (ticks * 1000) / adapter->params.vpd.cclk;
	302	}
	303
	304	int t4vf_wr_mbox_core(struct adapter , const void , int, void *, bool);
	305
	306	static inline int t4vf_wr_mbox(struct adapter adapter, const void cmd,
	307	int size, void *rpl)
	308	{
	309	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
	310	}
	311
	312	static inline int t4vf_wr_mbox_ns(struct adapter adapter, const void cmd,
	313	int size, void *rpl)
	314	{
	315	return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
	316	}
	317
e0a8b34a HS	318	#define CHELSIO_PCI_ID_VER(dev_id) ((dev_id) >> 12)
e0a8b34a HS	319
622c62b5 SR	320	static inline int is_t4(enum chip_type chip)
622c62b5 SR	321	{
70ee3666	322	return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
622c62b5 SR	323	}
622c62b5 SR	324
fe5d2709 HS	325	/**
	326	* hash_mac_addr - return the hash value of a MAC address
	327	* @addr: the 48-bit Ethernet MAC address
	328	*
	329	* Hashes a MAC address according to the hash function used by hardware
	330	* inexact (hash) address matching.
	331	*/
	332	static inline int hash_mac_addr(const u8 *addr)
	333	{
	334	u32 a = ((u32)addr[0] << 16) \| ((u32)addr[1] << 8) \| addr[2];
	335	u32 b = ((u32)addr[3] << 16) \| ((u32)addr[4] << 8) \| addr[5];
	336
	337	a ^= b;
	338	a ^= (a >> 12);
	339	a ^= (a >> 6);
	340	return a & 0x3f;
	341	}
	342
d289f864 BP	343	int t4vf_wait_dev_ready(struct adapter *);
d289f864 BP	344	int t4vf_port_init(struct adapter *, int);
16f8bd4b	345
e68e6133	346	int t4vf_fw_reset(struct adapter *);
16f8bd4b CL	347	int t4vf_set_params(struct adapter , unsigned int, const u32 , const u32 *);
16f8bd4b CL	348
cb440364	349	int t4vf_fl_pkt_align(struct adapter *adapter);
e85c9a7a	350	enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
b2612722 HS	351	int t4vf_bar2_sge_qregs(struct adapter *adapter,
	352	unsigned int qid,
	353	enum t4_bar2_qtype qtype,
	354	u64 *pbar2_qoffset,
	355	unsigned int *pbar2_qid);
e85c9a7a	356
16f8bd4b CL	357	int t4vf_get_sge_params(struct adapter *);
	358	int t4vf_get_vpd_params(struct adapter *);
	359	int t4vf_get_dev_params(struct adapter *);
	360	int t4vf_get_rss_glb_config(struct adapter *);
	361	int t4vf_get_vfres(struct adapter *);
	362
	363	int t4vf_read_rss_vi_config(struct adapter *, unsigned int,
	364	union rss_vi_config *);
	365	int t4vf_write_rss_vi_config(struct adapter *, unsigned int,
	366	union rss_vi_config *);
	367	int t4vf_config_rss_range(struct adapter *, unsigned int, int, int,
	368	const u16 *, int);
	369
	370	int t4vf_alloc_vi(struct adapter *, int);
	371	int t4vf_free_vi(struct adapter *, int);
	372	int t4vf_enable_vi(struct adapter *, unsigned int, bool, bool);
	373	int t4vf_identify_port(struct adapter *, unsigned int, unsigned int);
	374
	375	int t4vf_set_rxmode(struct adapter *, unsigned int, int, int, int, int, int,
	376	bool);
	377	int t4vf_alloc_mac_filt(struct adapter *, unsigned int, bool, unsigned int,
	378	const u8 *, u16 , u64 *, bool);
fe5d2709 HS	379	int t4vf_free_mac_filt(struct adapter *, unsigned int, unsigned int naddr,
fe5d2709 HS	380	const u8 **, bool);
16f8bd4b CL	381	int t4vf_change_mac(struct adapter , unsigned int, int, const u8 , bool);
	382	int t4vf_set_addr_hash(struct adapter *, unsigned int, bool, u64, bool);
	383	int t4vf_get_port_stats(struct adapter , int, struct t4vf_port_stats );
	384
	385	int t4vf_iq_free(struct adapter *, unsigned int, unsigned int, unsigned int,
	386	unsigned int);
	387	int t4vf_eth_eq_free(struct adapter *, unsigned int);
	388
	389	int t4vf_handle_fw_rpl(struct adapter , const __be64 );
e0a8b34a	390	int t4vf_prep_adapter(struct adapter *);
16f8bd4b CL	391
16f8bd4b CL	392	#endif /* __T4VF_COMMON_H__ */