Commit | Line | Data |
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6b7c5b94 | 1 | /* |
7dfbe7d7 | 2 | * Copyright (C) 2005 - 2016 Broadcom |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
d2145cde | 11 | * linux-drivers@emulex.com |
6b7c5b94 | 12 | * |
d2145cde AK |
13 | * Emulex |
14 | * 3333 Susan Street | |
15 | * Costa Mesa, CA 92626 | |
6b7c5b94 SP |
16 | */ |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
6b7c5b94 SP |
23 | #include <linux/delay.h> |
24 | #include <net/tcp.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/workqueue.h> | |
29 | #include <linux/interrupt.h> | |
84517482 | 30 | #include <linux/firmware.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ab1594e9 | 32 | #include <linux/u64_stats_sync.h> |
d658d98a | 33 | #include <linux/cpumask.h> |
29e9122b VD |
34 | #include <linux/hwmon.h> |
35 | #include <linux/hwmon-sysfs.h> | |
6b7c5b94 SP |
36 | |
37 | #include "be_hw.h" | |
045508a8 | 38 | #include "be_roce.h" |
6b7c5b94 | 39 | |
368f2f13 | 40 | #define DRV_VER "11.1.0.0" |
6b7c5b94 | 41 | #define DRV_NAME "be2net" |
00d3d51e SB |
42 | #define BE_NAME "Emulex BladeEngine2" |
43 | #define BE3_NAME "Emulex BladeEngine3" | |
44 | #define OC_NAME "Emulex OneConnect" | |
fe6d2a38 SP |
45 | #define OC_NAME_BE OC_NAME "(be3)" |
46 | #define OC_NAME_LANCER OC_NAME "(Lancer)" | |
ecedb6ae | 47 | #define OC_NAME_SH OC_NAME "(Skyhawk)" |
f3effb45 | 48 | #define DRV_DESC "Emulex OneConnect NIC Driver" |
6b7c5b94 | 49 | |
c4ca2374 | 50 | #define BE_VENDOR_ID 0x19a2 |
fe6d2a38 | 51 | #define EMULEX_VENDOR_ID 0x10df |
c4ca2374 | 52 | #define BE_DEVICE_ID1 0x211 |
12d7ea2c | 53 | #define BE_DEVICE_ID2 0x221 |
fe6d2a38 SP |
54 | #define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ |
55 | #define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ | |
56 | #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ | |
12f4d0a8 | 57 | #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ |
ecedb6ae | 58 | #define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ |
76b73530 | 59 | #define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ |
4762f6ce AK |
60 | #define OC_SUBSYS_DEVICE_ID1 0xE602 |
61 | #define OC_SUBSYS_DEVICE_ID2 0xE642 | |
62 | #define OC_SUBSYS_DEVICE_ID3 0xE612 | |
63 | #define OC_SUBSYS_DEVICE_ID4 0xE652 | |
c4ca2374 | 64 | |
6b7c5b94 | 65 | /* Number of bytes of an RX frame that are copied to skb->data */ |
2e588f84 | 66 | #define BE_HDR_LEN ((u16) 64) |
bb349bb4 ED |
67 | /* allocate extra space to allow tunneling decapsulation without head reallocation */ |
68 | #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) | |
69 | ||
6b7c5b94 SP |
70 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 |
71 | #define BE_MIN_MTU 256 | |
0d3f5cce KA |
72 | #define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ |
73 | (ETH_HLEN + ETH_FCS_LEN)) | |
6b7c5b94 | 74 | |
127bfce5 | 75 | /* Accommodate for QnQ configurations where VLAN insertion is enabled in HW */ |
76 | #define BE_MAX_GSO_SIZE (65535 - 2 * VLAN_HLEN) | |
77 | ||
6b7c5b94 | 78 | #define BE_NUM_VLANS_SUPPORTED 64 |
2632bafd | 79 | #define BE_MAX_EQD 128u |
6b7c5b94 SP |
80 | #define BE_MAX_TX_FRAG_COUNT 30 |
81 | ||
82 | #define EVNT_Q_LEN 1024 | |
83 | #define TX_Q_LEN 2048 | |
84 | #define TX_CQ_LEN 1024 | |
85 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
86 | #define RX_CQ_LEN 1024 | |
5fb379ee | 87 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
88 | #define MCC_CQ_LEN 256 |
89 | ||
10ef9ab4 | 90 | #define BE2_MAX_RSS_QS 4 |
68d7bdcb SP |
91 | #define BE3_MAX_RSS_QS 16 |
92 | #define BE3_MAX_TX_QS 16 | |
93 | #define BE3_MAX_EVT_QS 16 | |
e3dc867c | 94 | #define BE3_SRIOV_MAX_EVT_QS 8 |
ee9ad280 SB |
95 | #define SH_VF_MAX_NIC_EQS 3 /* Skyhawk VFs can have a max of 4 EQs |
96 | * and at least 1 is granted to either | |
97 | * SURF/DPDK | |
98 | */ | |
68d7bdcb | 99 | |
de2b1e03 SK |
100 | #define MAX_PORT_RSS_TABLES 15 |
101 | #define MAX_NIC_FUNCS 16 | |
68d7bdcb SP |
102 | #define MAX_RX_QS 32 |
103 | #define MAX_EVT_QS 32 | |
104 | #define MAX_TX_QS 32 | |
10ef9ab4 | 105 | |
045508a8 | 106 | #define MAX_ROCE_EQS 5 |
68d7bdcb | 107 | #define MAX_MSIX_VECTORS 32 |
92bf14ab | 108 | #define MIN_MSIX_VECTORS 1 |
6b7c5b94 | 109 | #define BE_NAPI_WEIGHT 64 |
10ef9ab4 | 110 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ |
6b7c5b94 | 111 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) |
69304cc9 | 112 | #define MAX_NUM_POST_ERX_DB 255u |
6b7c5b94 | 113 | |
7c5a5242 | 114 | #define MAX_VFS 30 /* Max VFs supported by BE3 FW */ |
8788fdc2 | 115 | #define FW_VER_LEN 32 |
a155a5db SB |
116 | #define CNTL_SERIAL_NUM_WORDS 8 /* Controller serial number words */ |
117 | #define CNTL_SERIAL_NUM_WORD_SZ (sizeof(u16)) /* Byte-sz of serial num word */ | |
8788fdc2 | 118 | |
e2557877 VD |
119 | #define RSS_INDIR_TABLE_LEN 128 |
120 | #define RSS_HASH_KEY_LEN 40 | |
121 | ||
51d1f98a AK |
122 | #define BE_UNKNOWN_PHY_STATE 0xFF |
123 | ||
6b7c5b94 SP |
124 | struct be_dma_mem { |
125 | void *va; | |
126 | dma_addr_t dma; | |
127 | u32 size; | |
128 | }; | |
129 | ||
130 | struct be_queue_info { | |
b0fd2eb2 | 131 | u32 len; |
132 | u32 entry_size; /* Size of an element in the queue */ | |
133 | u32 tail, head; | |
134 | atomic_t used; /* Number of valid elements in the queue */ | |
135 | u32 id; | |
6b7c5b94 | 136 | struct be_dma_mem dma_mem; |
6b7c5b94 | 137 | bool created; |
6b7c5b94 SP |
138 | }; |
139 | ||
b0fd2eb2 | 140 | static inline u32 MODULO(u32 val, u32 limit) |
5fb379ee SP |
141 | { |
142 | BUG_ON(limit & (limit - 1)); | |
143 | return val & (limit - 1); | |
144 | } | |
145 | ||
b0fd2eb2 | 146 | static inline void index_adv(u32 *index, u32 val, u32 limit) |
5fb379ee SP |
147 | { |
148 | *index = MODULO((*index + val), limit); | |
149 | } | |
150 | ||
b0fd2eb2 | 151 | static inline void index_inc(u32 *index, u32 limit) |
5fb379ee SP |
152 | { |
153 | *index = MODULO((*index + 1), limit); | |
154 | } | |
155 | ||
156 | static inline void *queue_head_node(struct be_queue_info *q) | |
157 | { | |
158 | return q->dma_mem.va + q->head * q->entry_size; | |
159 | } | |
160 | ||
161 | static inline void *queue_tail_node(struct be_queue_info *q) | |
162 | { | |
163 | return q->dma_mem.va + q->tail * q->entry_size; | |
164 | } | |
165 | ||
3de09455 SK |
166 | static inline void *queue_index_node(struct be_queue_info *q, u16 index) |
167 | { | |
168 | return q->dma_mem.va + index * q->entry_size; | |
169 | } | |
170 | ||
5fb379ee SP |
171 | static inline void queue_head_inc(struct be_queue_info *q) |
172 | { | |
173 | index_inc(&q->head, q->len); | |
174 | } | |
175 | ||
b0fd2eb2 | 176 | static inline void index_dec(u32 *index, u32 limit) |
652bf646 PR |
177 | { |
178 | *index = MODULO((*index - 1), limit); | |
179 | } | |
180 | ||
5fb379ee SP |
181 | static inline void queue_tail_inc(struct be_queue_info *q) |
182 | { | |
183 | index_inc(&q->tail, q->len); | |
184 | } | |
185 | ||
5fb379ee SP |
186 | struct be_eq_obj { |
187 | struct be_queue_info q; | |
188 | char desc[32]; | |
189 | ||
190 | /* Adaptive interrupt coalescing (AIC) info */ | |
191 | bool enable_aic; | |
10ef9ab4 SP |
192 | u32 min_eqd; /* in usecs */ |
193 | u32 max_eqd; /* in usecs */ | |
194 | u32 eqd; /* configured val when aic is off */ | |
195 | u32 cur_eqd; /* in usecs */ | |
5fb379ee | 196 | |
10ef9ab4 | 197 | u8 idx; /* array index */ |
f2f781a7 | 198 | u8 msix_idx; |
d0b9cec3 | 199 | u16 spurious_intr; |
5fb379ee | 200 | struct napi_struct napi; |
10ef9ab4 | 201 | struct be_adapter *adapter; |
d658d98a | 202 | cpumask_var_t affinity_mask; |
6384a4d0 SP |
203 | |
204 | #ifdef CONFIG_NET_RX_BUSY_POLL | |
205 | #define BE_EQ_IDLE 0 | |
206 | #define BE_EQ_NAPI 1 /* napi owns this EQ */ | |
207 | #define BE_EQ_POLL 2 /* poll owns this EQ */ | |
208 | #define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) | |
209 | #define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ | |
210 | #define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ | |
211 | #define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) | |
212 | #define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) | |
213 | unsigned int state; | |
214 | spinlock_t lock; /* lock to serialize napi and busy-poll */ | |
215 | #endif /* CONFIG_NET_RX_BUSY_POLL */ | |
10ef9ab4 | 216 | } ____cacheline_aligned_in_smp; |
5fb379ee | 217 | |
2632bafd SP |
218 | struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ |
219 | bool enable; | |
220 | u32 min_eqd; /* in usecs */ | |
221 | u32 max_eqd; /* in usecs */ | |
222 | u32 prev_eqd; /* in usecs */ | |
223 | u32 et_eqd; /* configured val when aic is off */ | |
224 | ulong jiffies; | |
225 | u64 rx_pkts_prev; /* Used to calculate RX pps */ | |
226 | u64 tx_reqs_prev; /* Used to calculate TX pps */ | |
227 | }; | |
228 | ||
6384a4d0 SP |
229 | enum { |
230 | NAPI_POLLING, | |
231 | BUSY_POLLING | |
232 | }; | |
233 | ||
5fb379ee SP |
234 | struct be_mcc_obj { |
235 | struct be_queue_info q; | |
236 | struct be_queue_info cq; | |
7a1e9b20 | 237 | bool rearm_cq; |
5fb379ee SP |
238 | }; |
239 | ||
3abcdeda | 240 | struct be_tx_stats { |
ac124ff9 SP |
241 | u64 tx_bytes; |
242 | u64 tx_pkts; | |
8670f2a5 | 243 | u64 tx_vxlan_offload_pkts; |
ac124ff9 | 244 | u64 tx_reqs; |
ac124ff9 SP |
245 | u64 tx_compl; |
246 | ulong tx_jiffies; | |
247 | u32 tx_stops; | |
bc617526 | 248 | u32 tx_drv_drops; /* pkts dropped by driver */ |
512bb8a2 KA |
249 | /* the error counters are described in be_ethtool.c */ |
250 | u32 tx_hdr_parse_err; | |
251 | u32 tx_dma_err; | |
252 | u32 tx_tso_err; | |
253 | u32 tx_spoof_check_err; | |
254 | u32 tx_qinq_err; | |
255 | u32 tx_internal_parity_err; | |
ab1594e9 SP |
256 | struct u64_stats_sync sync; |
257 | struct u64_stats_sync sync_compl; | |
6b7c5b94 SP |
258 | }; |
259 | ||
152ffe5b SB |
260 | /* Structure to hold some data of interest obtained from a TX CQE */ |
261 | struct be_tx_compl_info { | |
262 | u8 status; /* Completion status */ | |
263 | u16 end_index; /* Completed TXQ Index */ | |
264 | }; | |
265 | ||
6b7c5b94 | 266 | struct be_tx_obj { |
94d73aaa | 267 | u32 db_offset; |
6b7c5b94 SP |
268 | struct be_queue_info q; |
269 | struct be_queue_info cq; | |
152ffe5b | 270 | struct be_tx_compl_info txcp; |
6b7c5b94 SP |
271 | /* Remember the skbs that were transmitted */ |
272 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
3c8def97 | 273 | struct be_tx_stats stats; |
5f07b3c5 SP |
274 | u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ |
275 | u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ | |
276 | u16 last_req_hdr; /* index of the last req's hdr-wrb */ | |
10ef9ab4 | 277 | } ____cacheline_aligned_in_smp; |
6b7c5b94 SP |
278 | |
279 | /* Struct to remember the pages posted for rx frags */ | |
280 | struct be_rx_page_info { | |
281 | struct page *page; | |
e50287be | 282 | /* set to page-addr for last frag of the page & frag-addr otherwise */ |
fac6da5b | 283 | DEFINE_DMA_UNMAP_ADDR(bus); |
6b7c5b94 | 284 | u16 page_offset; |
e50287be | 285 | bool last_frag; /* last frag of the page */ |
6b7c5b94 SP |
286 | }; |
287 | ||
3abcdeda | 288 | struct be_rx_stats { |
3abcdeda | 289 | u64 rx_bytes; |
3abcdeda | 290 | u64 rx_pkts; |
8670f2a5 | 291 | u64 rx_vxlan_offload_pkts; |
ac124ff9 SP |
292 | u32 rx_drops_no_skbs; /* skb allocation errors */ |
293 | u32 rx_drops_no_frags; /* HW has no fetched frags */ | |
294 | u32 rx_post_fail; /* page post alloc failures */ | |
ac124ff9 | 295 | u32 rx_compl; |
3abcdeda | 296 | u32 rx_mcast_pkts; |
ac124ff9 | 297 | u32 rx_compl_err; /* completions with err set */ |
ab1594e9 | 298 | struct u64_stats_sync sync; |
3abcdeda SP |
299 | }; |
300 | ||
2e588f84 SP |
301 | struct be_rx_compl_info { |
302 | u32 rss_hash; | |
6709d952 | 303 | u16 vlan_tag; |
2e588f84 | 304 | u16 pkt_size; |
12004ae9 | 305 | u16 port; |
2e588f84 SP |
306 | u8 vlanf; |
307 | u8 num_rcvd; | |
308 | u8 err; | |
309 | u8 ipf; | |
310 | u8 tcpf; | |
311 | u8 udpf; | |
312 | u8 ip_csum; | |
313 | u8 l4_csum; | |
314 | u8 ipv6; | |
f93f160b | 315 | u8 qnq; |
2e588f84 | 316 | u8 pkt_type; |
e38b1706 | 317 | u8 ip_frag; |
c9c47142 | 318 | u8 tunneled; |
2e588f84 SP |
319 | }; |
320 | ||
6b7c5b94 | 321 | struct be_rx_obj { |
3abcdeda | 322 | struct be_adapter *adapter; |
6b7c5b94 SP |
323 | struct be_queue_info q; |
324 | struct be_queue_info cq; | |
2e588f84 | 325 | struct be_rx_compl_info rxcp; |
6b7c5b94 | 326 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; |
3abcdeda SP |
327 | struct be_rx_stats stats; |
328 | u8 rss_id; | |
329 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | |
10ef9ab4 | 330 | } ____cacheline_aligned_in_smp; |
6b7c5b94 | 331 | |
609ff3bb | 332 | struct be_drv_stats { |
ac124ff9 | 333 | u32 eth_red_drops; |
d3de1540 | 334 | u32 dma_map_errors; |
ac124ff9 SP |
335 | u32 rx_drops_no_pbuf; |
336 | u32 rx_drops_no_txpb; | |
337 | u32 rx_drops_no_erx_descr; | |
338 | u32 rx_drops_no_tpre_descr; | |
339 | u32 rx_drops_too_many_frags; | |
ac124ff9 SP |
340 | u32 forwarded_packets; |
341 | u32 rx_drops_mtu; | |
342 | u32 rx_crc_errors; | |
343 | u32 rx_alignment_symbol_errors; | |
344 | u32 rx_pause_frames; | |
345 | u32 rx_priority_pause_frames; | |
346 | u32 rx_control_frames; | |
347 | u32 rx_in_range_errors; | |
348 | u32 rx_out_range_errors; | |
349 | u32 rx_frame_too_long; | |
18fb06a1 | 350 | u32 rx_address_filtered; |
ac124ff9 SP |
351 | u32 rx_dropped_too_small; |
352 | u32 rx_dropped_too_short; | |
353 | u32 rx_dropped_header_too_small; | |
354 | u32 rx_dropped_tcp_length; | |
355 | u32 rx_dropped_runt; | |
356 | u32 rx_ip_checksum_errs; | |
357 | u32 rx_tcp_checksum_errs; | |
358 | u32 rx_udp_checksum_errs; | |
359 | u32 tx_pauseframes; | |
360 | u32 tx_priority_pauseframes; | |
361 | u32 tx_controlframes; | |
362 | u32 rxpp_fifo_overflow_drop; | |
363 | u32 rx_input_fifo_overflow_drop; | |
364 | u32 pmem_fifo_overflow_drop; | |
365 | u32 jabber_events; | |
461ae379 AK |
366 | u32 rx_roce_bytes_lsd; |
367 | u32 rx_roce_bytes_msd; | |
368 | u32 rx_roce_frames; | |
369 | u32 roce_drops_payload_len; | |
370 | u32 roce_drops_crc; | |
609ff3bb AK |
371 | }; |
372 | ||
c502224e SK |
373 | /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ |
374 | #define BE_RESET_VLAN_TAG_ID 0xFFFF | |
375 | ||
64600ea5 | 376 | struct be_vf_cfg { |
11ac75ed SP |
377 | unsigned char mac_addr[ETH_ALEN]; |
378 | int if_handle; | |
379 | int pmac_id; | |
380 | u16 vlan_tag; | |
381 | u32 tx_rate; | |
bdce2ad7 | 382 | u32 plink_tracking; |
435452aa | 383 | u32 privileges; |
e7bcbd7b | 384 | bool spoofchk; |
64600ea5 AK |
385 | }; |
386 | ||
39f1d94d SP |
387 | enum vf_state { |
388 | ENABLED = 0, | |
389 | ASSIGNED = 1 | |
390 | }; | |
391 | ||
83b06116 VV |
392 | #define BE_FLAGS_LINK_STATUS_INIT BIT(1) |
393 | #define BE_FLAGS_SRIOV_ENABLED BIT(2) | |
394 | #define BE_FLAGS_WORKER_SCHEDULED BIT(3) | |
83b06116 VV |
395 | #define BE_FLAGS_NAPI_ENABLED BIT(6) |
396 | #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) | |
397 | #define BE_FLAGS_VXLAN_OFFLOADS BIT(8) | |
398 | #define BE_FLAGS_SETUP_DONE BIT(9) | |
51d1f98a | 399 | #define BE_FLAGS_PHY_MISCONFIGURED BIT(10) |
eb7dd46c | 400 | #define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) |
760c295e | 401 | #define BE_FLAGS_OS2BMC BIT(12) |
710f3e59 | 402 | #define BE_FLAGS_TRY_RECOVERY BIT(13) |
b236916a | 403 | |
c9c47142 SP |
404 | #define BE_UC_PMAC_COUNT 30 |
405 | #define BE_VF_UC_PMAC_COUNT 2 | |
f0613380 | 406 | |
972f37b4 PR |
407 | #define MAX_ERR_RECOVERY_RETRY_COUNT 3 |
408 | #define ERR_DETECTION_DELAY 1000 | |
972f37b4 | 409 | |
5c510811 SK |
410 | /* Ethtool set_dump flags */ |
411 | #define LANCER_INITIATE_FW_DUMP 0x1 | |
f0613380 | 412 | #define LANCER_DELETE_FW_DUMP 0x2 |
5c510811 | 413 | |
42f11cf2 | 414 | struct phy_info { |
21252377 VV |
415 | /* From SFF-8472 spec */ |
416 | #define SFP_VENDOR_NAME_LEN 17 | |
42f11cf2 AK |
417 | u8 transceiver; |
418 | u8 autoneg; | |
419 | u8 fc_autoneg; | |
420 | u8 port_type; | |
421 | u16 phy_type; | |
422 | u16 interface_type; | |
423 | u32 misc_params; | |
424 | u16 auto_speeds_supported; | |
425 | u16 fixed_speeds_supported; | |
426 | int link_speed; | |
42f11cf2 AK |
427 | u32 advertising; |
428 | u32 supported; | |
6809cee0 | 429 | u8 cable_type; |
21252377 VV |
430 | u8 vendor_name[SFP_VENDOR_NAME_LEN]; |
431 | u8 vendor_pn[SFP_VENDOR_NAME_LEN]; | |
42f11cf2 AK |
432 | }; |
433 | ||
92bf14ab SP |
434 | struct be_resources { |
435 | u16 max_vfs; /* Total VFs "really" supported by FW/HW */ | |
436 | u16 max_mcast_mac; | |
437 | u16 max_tx_qs; | |
438 | u16 max_rss_qs; | |
439 | u16 max_rx_qs; | |
f2858738 | 440 | u16 max_cq_count; |
92bf14ab SP |
441 | u16 max_uc_mac; /* Max UC MACs programmable */ |
442 | u16 max_vlans; /* Number of vlans supported */ | |
f2858738 VV |
443 | u16 max_iface_count; |
444 | u16 max_mcc_count; | |
92bf14ab | 445 | u16 max_evt_qs; |
ce7faf0a | 446 | u16 max_nic_evt_qs; /* NIC's share of evt qs */ |
92bf14ab | 447 | u32 if_cap_flags; |
10cccf60 | 448 | u32 vf_if_cap_flags; /* VF if capability flags */ |
b9263cbf | 449 | u32 flags; |
de2b1e03 SK |
450 | /* Calculated PF Pool's share of RSS Tables. This is not enforced by |
451 | * the FW, but is a self-imposed driver limitation. | |
452 | */ | |
453 | u16 max_rss_tables; | |
454 | }; | |
455 | ||
456 | /* These are port-wide values */ | |
457 | struct be_port_resources { | |
458 | u16 max_vfs; | |
459 | u16 nic_pfs; | |
92bf14ab SP |
460 | }; |
461 | ||
760c295e VD |
462 | #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC) |
463 | ||
e2557877 VD |
464 | struct rss_info { |
465 | u64 rss_flags; | |
466 | u8 rsstable[RSS_INDIR_TABLE_LEN]; | |
467 | u8 rss_queue[RSS_INDIR_TABLE_LEN]; | |
468 | u8 rss_hkey[RSS_HASH_KEY_LEN]; | |
469 | }; | |
470 | ||
29e9122b VD |
471 | #define BE_INVALID_DIE_TEMP 0xFF |
472 | struct be_hwmon { | |
473 | struct device *hwmon_dev; | |
474 | u8 be_on_die_temp; /* Unit: millidegree Celsius */ | |
475 | }; | |
476 | ||
804abcdb SB |
477 | /* Macros to read/write the 'features' word of be_wrb_params structure. |
478 | */ | |
479 | #define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT | |
480 | #define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) | |
481 | ||
482 | #define BE_WRB_F_GET(word, name) \ | |
483 | (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) | |
484 | ||
485 | #define BE_WRB_F_SET(word, name, val) \ | |
486 | ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) | |
487 | ||
488 | /* Feature/offload bits */ | |
489 | enum { | |
490 | BE_WRB_F_CRC_BIT, /* Ethernet CRC */ | |
491 | BE_WRB_F_IPCS_BIT, /* IP csum */ | |
492 | BE_WRB_F_TCPCS_BIT, /* TCP csum */ | |
493 | BE_WRB_F_UDPCS_BIT, /* UDP csum */ | |
494 | BE_WRB_F_LSO_BIT, /* LSO */ | |
495 | BE_WRB_F_LSO6_BIT, /* LSO6 */ | |
496 | BE_WRB_F_VLAN_BIT, /* VLAN */ | |
760c295e VD |
497 | BE_WRB_F_VLAN_SKIP_HW_BIT, /* Skip VLAN tag (workaround) */ |
498 | BE_WRB_F_OS2BMC_BIT /* Send packet to the management ring */ | |
804abcdb SB |
499 | }; |
500 | ||
501 | /* The structure below provides a HW-agnostic abstraction of WRB params | |
502 | * retrieved from a TX skb. This is in turn passed to chip specific routines | |
503 | * during transmit, to set the corresponding params in the WRB. | |
504 | */ | |
505 | struct be_wrb_params { | |
506 | u32 features; /* Feature bits */ | |
507 | u16 vlan_tag; /* VLAN tag */ | |
508 | u16 lso_mss; /* MSS for LSO */ | |
509 | }; | |
510 | ||
b7172414 SP |
511 | struct be_eth_addr { |
512 | unsigned char mac[ETH_ALEN]; | |
513 | }; | |
514 | ||
710f3e59 SB |
515 | #define BE_SEC 1000 /* in msec */ |
516 | #define BE_MIN (60 * BE_SEC) /* in msec */ | |
517 | #define BE_HOUR (60 * BE_MIN) /* in msec */ | |
518 | ||
519 | #define ERR_RECOVERY_MAX_RETRY_COUNT 3 | |
520 | #define ERR_RECOVERY_DETECTION_DELAY BE_SEC | |
521 | #define ERR_RECOVERY_RETRY_DELAY (30 * BE_SEC) | |
522 | ||
523 | /* UE-detection-duration in BEx/Skyhawk: | |
524 | * All PFs must wait for this duration after they detect UE before reading | |
525 | * SLIPORT_SEMAPHORE register. At the end of this duration, the Firmware | |
526 | * guarantees that the SLIPORT_SEMAPHORE register is updated to indicate | |
527 | * if the UE is recoverable. | |
528 | */ | |
529 | #define ERR_RECOVERY_UE_DETECT_DURATION BE_SEC | |
530 | ||
531 | /* Initial idle time (in msec) to elapse after driver load, | |
532 | * before UE recovery is allowed. | |
533 | */ | |
534 | #define ERR_IDLE_HR 24 | |
535 | #define ERR_RECOVERY_IDLE_TIME (ERR_IDLE_HR * BE_HOUR) | |
536 | ||
537 | /* Time interval (in msec) after which UE recovery can be repeated */ | |
538 | #define ERR_INTERVAL_HR 72 | |
539 | #define ERR_RECOVERY_INTERVAL (ERR_INTERVAL_HR * BE_HOUR) | |
540 | ||
541 | /* BEx/SH UE recovery state machine */ | |
542 | enum { | |
543 | ERR_RECOVERY_ST_NONE = 0, /* No Recovery */ | |
544 | ERR_RECOVERY_ST_DETECT = 1, /* UE detection duration */ | |
545 | ERR_RECOVERY_ST_RESET = 2, /* Reset Phase (PF0 only) */ | |
546 | ERR_RECOVERY_ST_PRE_POLL = 3, /* Pre-Poll Phase (all PFs) */ | |
547 | ERR_RECOVERY_ST_REINIT = 4 /* Re-initialize Phase */ | |
548 | }; | |
549 | ||
550 | struct be_error_recovery { | |
551 | /* Lancer error recovery variables */ | |
552 | u8 recovery_retries; | |
553 | ||
554 | /* BEx/Skyhawk error recovery variables */ | |
555 | u8 recovery_state; | |
556 | u16 ue_to_reset_time; /* Time after UE, to soft reset | |
557 | * the chip - PF0 only | |
558 | */ | |
559 | u16 ue_to_poll_time; /* Time after UE, to Restart Polling | |
560 | * of SLIPORT_SEMAPHORE reg | |
561 | */ | |
562 | u16 last_err_code; | |
563 | bool recovery_supported; | |
564 | unsigned long probe_time; | |
565 | unsigned long last_recovery_time; | |
566 | ||
567 | /* Common to both Lancer & BEx/SH error recovery */ | |
568 | u32 resched_delay; | |
569 | struct delayed_work err_detection_work; | |
570 | }; | |
571 | ||
572 | /* Ethtool priv_flags */ | |
573 | #define BE_DISABLE_TPE_RECOVERY 0x1 | |
574 | ||
6b7c5b94 SP |
575 | struct be_adapter { |
576 | struct pci_dev *pdev; | |
577 | struct net_device *netdev; | |
578 | ||
c5b3ad4c | 579 | u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ |
8788fdc2 | 580 | u8 __iomem *db; /* Door Bell */ |
25848c90 | 581 | u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ |
8788fdc2 | 582 | |
2984961c | 583 | struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ |
8788fdc2 SP |
584 | struct be_dma_mem mbox_mem; |
585 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
586 | * is stored for freeing purpose */ | |
587 | struct be_dma_mem mbox_mem_alloced; | |
588 | ||
589 | struct be_mcc_obj mcc_obj; | |
b7172414 | 590 | struct mutex mcc_lock; /* For serializing mcc cmds to BE card */ |
8788fdc2 | 591 | spinlock_t mcc_cq_lock; |
6b7c5b94 | 592 | |
e261768e SP |
593 | u16 cfg_num_rx_irqs; /* configured via set-channels */ |
594 | u16 cfg_num_tx_irqs; /* configured via set-channels */ | |
92bf14ab SP |
595 | u16 num_evt_qs; |
596 | u16 num_msix_vec; | |
597 | struct be_eq_obj eq_obj[MAX_EVT_QS]; | |
10ef9ab4 | 598 | struct msix_entry msix_entries[MAX_MSIX_VECTORS]; |
6b7c5b94 SP |
599 | bool isr_registered; |
600 | ||
601 | /* TX Rings */ | |
92bf14ab | 602 | u16 num_tx_qs; |
3c8def97 | 603 | struct be_tx_obj tx_obj[MAX_TX_QS]; |
6b7c5b94 SP |
604 | |
605 | /* Rx rings */ | |
92bf14ab | 606 | u16 num_rx_qs; |
71bb8bd0 VV |
607 | u16 num_rss_qs; |
608 | u16 need_def_rxq; | |
10ef9ab4 | 609 | struct be_rx_obj rx_obj[MAX_RX_QS]; |
6b7c5b94 SP |
610 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ |
611 | ||
609ff3bb | 612 | struct be_drv_stats drv_stats; |
2632bafd | 613 | struct be_aic_obj aic_obj[MAX_EVT_QS]; |
cc4ce020 | 614 | u8 vlan_prio_bmap; /* Available Priority BitMap */ |
fdf81bfb | 615 | u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */ |
5b8821b7 | 616 | struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ |
6b7c5b94 | 617 | |
3abcdeda | 618 | struct be_dma_mem stats_cmd; |
6b7c5b94 SP |
619 | /* Work queue used to perform periodic tasks like getting statistics */ |
620 | struct delayed_work work; | |
609ff3bb | 621 | u16 work_counter; |
6b7c5b94 | 622 | |
972f37b4 | 623 | u8 recovery_retries; |
954f6825 | 624 | u8 err_flags; |
a69bf3c5 | 625 | bool pcicfg_mapped; /* pcicfg obtained via pci_iomap() */ |
b236916a | 626 | u32 flags; |
f25b119c | 627 | u32 cmd_privileges; |
6b7c5b94 | 628 | /* Ethtool knobs and info */ |
6b7c5b94 | 629 | char fw_ver[FW_VER_LEN]; |
eeb65ced | 630 | char fw_on_flash[FW_VER_LEN]; |
f66b7cfd SP |
631 | |
632 | /* IFACE filtering fields */ | |
30128031 | 633 | int if_handle; /* Used to configure filtering */ |
f66b7cfd | 634 | u32 if_flags; /* Interface filtering flags */ |
fbc13f01 | 635 | u32 *pmac_id; /* MAC addr handle used by BE card */ |
b7172414 | 636 | struct be_eth_addr *uc_list;/* list of uc-addrs programmed (not perm) */ |
f66b7cfd | 637 | u32 uc_macs; /* Count of secondary UC MAC programmed */ |
b7172414 SP |
638 | struct be_eth_addr *mc_list;/* list of mcast addrs programmed */ |
639 | u32 mc_count; | |
f66b7cfd SP |
640 | unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; |
641 | u16 vlans_added; | |
92fbb1df SB |
642 | bool update_uc_list; |
643 | bool update_mc_list; | |
b7172414 | 644 | struct mutex rx_filter_lock;/* For protecting vids[] & mc/uc_list[] */ |
f66b7cfd | 645 | |
1a642469 | 646 | u32 beacon_state; /* for set_phys_id */ |
6b7c5b94 | 647 | |
6b7c5b94 | 648 | u32 port_num; |
21252377 | 649 | char port_name; |
f93f160b | 650 | u8 mc_type; |
3486be29 | 651 | u32 function_mode; |
3abcdeda | 652 | u32 function_caps; |
9e90c961 AK |
653 | u32 rx_fc; /* Rx flow control */ |
654 | u32 tx_fc; /* Tx flow control */ | |
b2aebe6d | 655 | bool stats_cmd_sent; |
045508a8 | 656 | struct { |
045508a8 PP |
657 | u32 size; |
658 | u32 total_size; | |
659 | u64 io_addr; | |
660 | } roce_db; | |
661 | u32 num_msix_roce_vec; | |
662 | struct ocrdma_dev *ocrdma_dev; | |
663 | struct list_head entry; | |
664 | ||
dd131e76 | 665 | u32 flash_status; |
5eeff635 | 666 | struct completion et_cmd_compl; |
ba343c77 | 667 | |
bec84e6b | 668 | struct be_resources pool_res; /* resources available for the port */ |
92bf14ab SP |
669 | struct be_resources res; /* resources available for the func */ |
670 | u16 num_vfs; /* Number of VFs provisioned by PF */ | |
980df249 SR |
671 | u8 pf_num; /* Numbering used by FW, starts at 0 */ |
672 | u8 vf_num; /* Numbering used by FW, starts at 1 */ | |
39f1d94d | 673 | u8 virtfn; |
11ac75ed SP |
674 | struct be_vf_cfg *vf_cfg; |
675 | bool be3_native; | |
fe6d2a38 | 676 | u32 sli_family; |
9e1453c5 | 677 | u8 hba_port_num; |
3968fa1e | 678 | u16 pvid; |
c9c47142 | 679 | __be16 vxlan_port; |
630f4b70 | 680 | int vxlan_port_count; |
1e5b311a | 681 | int vxlan_port_aliases; |
42f11cf2 | 682 | struct phy_info phy; |
4762f6ce | 683 | u8 wol_cap; |
76a9e08e | 684 | bool wol_en; |
0ad3157e | 685 | u16 asic_rev; |
bc0c3405 | 686 | u16 qnq_vid; |
941a77d5 | 687 | u32 msg_enable; |
7aeb2156 | 688 | int be_get_temp_freq; |
29e9122b | 689 | struct be_hwmon hwmon_info; |
e2557877 | 690 | struct rss_info rss_info; |
760c295e VD |
691 | /* Filters for packets that need to be sent to BMC */ |
692 | u32 bmc_filt_mask; | |
fd7ff6f0 | 693 | u32 fat_dump_len; |
a155a5db | 694 | u16 serial_num[CNTL_SERIAL_NUM_WORDS]; |
51d1f98a | 695 | u8 phy_state; /* state of sfp optics (functional, faulted, etc.,) */ |
c27ebf58 | 696 | u8 dev_mac[ETH_ALEN]; |
710f3e59 SB |
697 | u32 priv_flags; /* ethtool get/set_priv_flags() */ |
698 | struct be_error_recovery error_recovery; | |
6b7c5b94 SP |
699 | }; |
700 | ||
b7172414 SP |
701 | /* Used for defered FW config cmds. Add fields to this struct as reqd */ |
702 | struct be_cmd_work { | |
703 | struct work_struct work; | |
704 | struct be_adapter *adapter; | |
705 | union { | |
706 | __be16 vxlan_port; | |
707 | } info; | |
708 | }; | |
709 | ||
39f1d94d | 710 | #define be_physfn(adapter) (!adapter->virtfn) |
2c7a9dc1 | 711 | #define be_virtfn(adapter) (adapter->virtfn) |
f174c7ec VV |
712 | #define sriov_enabled(adapter) (adapter->flags & \ |
713 | BE_FLAGS_SRIOV_ENABLED) | |
bec84e6b | 714 | |
11ac75ed SP |
715 | #define for_all_vfs(adapter, vf_cfg, i) \ |
716 | for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ | |
717 | i++, vf_cfg++) | |
ba343c77 | 718 | |
5b8821b7 SP |
719 | #define ON 1 |
720 | #define OFF 0 | |
ca34fe38 | 721 | |
92bf14ab SP |
722 | #define be_max_vlans(adapter) (adapter->res.max_vlans) |
723 | #define be_max_uc(adapter) (adapter->res.max_uc_mac) | |
724 | #define be_max_mc(adapter) (adapter->res.max_mcast_mac) | |
bec84e6b | 725 | #define be_max_vfs(adapter) (adapter->pool_res.max_vfs) |
92bf14ab SP |
726 | #define be_max_rss(adapter) (adapter->res.max_rss_qs) |
727 | #define be_max_txqs(adapter) (adapter->res.max_tx_qs) | |
728 | #define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) | |
729 | #define be_max_rxqs(adapter) (adapter->res.max_rx_qs) | |
ce7faf0a SP |
730 | /* Max number of EQs available for the function (NIC + RoCE (if enabled)) */ |
731 | #define be_max_func_eqs(adapter) (adapter->res.max_evt_qs) | |
732 | /* Max number of EQs available avaialble only for NIC */ | |
733 | #define be_max_nic_eqs(adapter) (adapter->res.max_nic_evt_qs) | |
92bf14ab | 734 | #define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) |
de2b1e03 SK |
735 | #define be_max_pf_pool_rss_tables(adapter) \ |
736 | (adapter->pool_res.max_rss_tables) | |
e261768e SP |
737 | /* Max irqs avaialble for NIC */ |
738 | #define be_max_irqs(adapter) \ | |
739 | (min_t(u16, be_max_nic_eqs(adapter), num_online_cpus())) | |
92bf14ab | 740 | |
e261768e SP |
741 | /* Max irqs *needed* for RX queues */ |
742 | static inline u16 be_max_rx_irqs(struct be_adapter *adapter) | |
92bf14ab | 743 | { |
e261768e | 744 | /* If no RSS, need atleast one irq for def-RXQ */ |
92bf14ab SP |
745 | u16 num = max_t(u16, be_max_rss(adapter), 1); |
746 | ||
e261768e SP |
747 | return min_t(u16, num, be_max_irqs(adapter)); |
748 | } | |
749 | ||
750 | /* Max irqs *needed* for TX queues */ | |
751 | static inline u16 be_max_tx_irqs(struct be_adapter *adapter) | |
752 | { | |
753 | return min_t(u16, be_max_txqs(adapter), be_max_irqs(adapter)); | |
754 | } | |
755 | ||
756 | /* Max irqs *needed* for combined queues */ | |
757 | static inline u16 be_max_qp_irqs(struct be_adapter *adapter) | |
758 | { | |
759 | return min(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter)); | |
760 | } | |
761 | ||
762 | /* Max irqs *needed* for RX and TX queues together */ | |
763 | static inline u16 be_max_any_irqs(struct be_adapter *adapter) | |
764 | { | |
765 | return max(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter)); | |
92bf14ab SP |
766 | } |
767 | ||
f93f160b VV |
768 | /* Is BE in pvid_tagging mode */ |
769 | #define be_pvid_tagging_enabled(adapter) (adapter->pvid) | |
770 | ||
771 | /* Is BE in QNQ multi-channel mode */ | |
66064dbc | 772 | #define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) |
f93f160b | 773 | |
ca34fe38 SP |
774 | #define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ |
775 | adapter->pdev->device == OC_DEVICE_ID4) | |
fe6d2a38 | 776 | |
76b73530 PR |
777 | #define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ |
778 | adapter->pdev->device == OC_DEVICE_ID6) | |
d3bd3a5e | 779 | |
ca34fe38 SP |
780 | #define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ |
781 | adapter->pdev->device == OC_DEVICE_ID2) | |
782 | ||
783 | #define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ | |
784 | adapter->pdev->device == OC_DEVICE_ID1) | |
785 | ||
786 | #define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) | |
d3bd3a5e | 787 | |
dbf0f2a7 SP |
788 | #define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ |
789 | (adapter->function_mode & RDMA_ENABLED)) | |
045508a8 | 790 | |
0fc0b732 | 791 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 | 792 | |
ac6a0c4a | 793 | #define msix_enabled(adapter) (adapter->num_msix_vec > 0) |
10ef9ab4 SP |
794 | #define num_irqs(adapter) (msix_enabled(adapter) ? \ |
795 | adapter->num_msix_vec : 1) | |
796 | #define tx_stats(txo) (&(txo)->stats) | |
797 | #define rx_stats(rxo) (&(rxo)->stats) | |
6b7c5b94 | 798 | |
10ef9ab4 SP |
799 | /* The default RXQ is the last RXQ */ |
800 | #define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) | |
6b7c5b94 | 801 | |
3abcdeda SP |
802 | #define for_all_rx_queues(adapter, rxo, i) \ |
803 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ | |
804 | i++, rxo++) | |
805 | ||
3abcdeda | 806 | #define for_all_rss_queues(adapter, rxo, i) \ |
71bb8bd0 | 807 | for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ |
3abcdeda SP |
808 | i++, rxo++) |
809 | ||
3c8def97 SP |
810 | #define for_all_tx_queues(adapter, txo, i) \ |
811 | for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ | |
812 | i++, txo++) | |
813 | ||
10ef9ab4 SP |
814 | #define for_all_evt_queues(adapter, eqo, i) \ |
815 | for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ | |
816 | i++, eqo++) | |
817 | ||
6384a4d0 SP |
818 | #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ |
819 | for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ | |
820 | i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) | |
821 | ||
a4906ea0 SP |
822 | #define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ |
823 | for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ | |
824 | i += adapter->num_evt_qs, txo += adapter->num_evt_qs) | |
825 | ||
10ef9ab4 SP |
826 | #define is_mcc_eqo(eqo) (eqo->idx == 0) |
827 | #define mcc_eqo(adapter) (&adapter->eq_obj[0]) | |
828 | ||
6b7c5b94 SP |
829 | #define PAGE_SHIFT_4K 12 |
830 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
831 | ||
832 | /* Returns number of pages spanned by the data starting at the given addr */ | |
833 | #define PAGES_4K_SPANNED(_address, size) \ | |
834 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
835 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
836 | ||
6b7c5b94 SP |
837 | /* Returns bit offset within a DWORD of a bitfield */ |
838 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
839 | (((size_t)&(((_struct *)0)->field))%32) | |
840 | ||
841 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
842 | static inline u32 amap_mask(u32 bitsize) | |
843 | { | |
844 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
845 | } | |
846 | ||
847 | static inline void | |
848 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
849 | { | |
850 | u32 *dw = (u32 *) ptr + dw_offset; | |
851 | *dw &= ~(mask << offset); | |
852 | *dw |= (mask & value) << offset; | |
853 | } | |
854 | ||
855 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
856 | amap_set(ptr, \ | |
857 | offsetof(_struct, field)/32, \ | |
858 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
859 | AMAP_BIT_OFFSET(_struct, field), \ | |
860 | val) | |
861 | ||
862 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
863 | { | |
864 | u32 *dw = (u32 *) ptr; | |
865 | return mask & (*(dw + dw_offset) >> offset); | |
866 | } | |
867 | ||
868 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
869 | amap_get(ptr, \ | |
870 | offsetof(_struct, field)/32, \ | |
871 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
872 | AMAP_BIT_OFFSET(_struct, field)) | |
873 | ||
c3c18bc1 SP |
874 | #define GET_RX_COMPL_V0_BITS(field, ptr) \ |
875 | AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) | |
876 | ||
877 | #define GET_RX_COMPL_V1_BITS(field, ptr) \ | |
878 | AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) | |
879 | ||
880 | #define GET_TX_COMPL_BITS(field, ptr) \ | |
881 | AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) | |
882 | ||
883 | #define SET_TX_WRB_HDR_BITS(field, ptr, val) \ | |
884 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) | |
885 | ||
6b7c5b94 SP |
886 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) |
887 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
888 | static inline void swap_dws(void *wrb, int len) | |
889 | { | |
890 | #ifdef __BIG_ENDIAN | |
891 | u32 *dw = wrb; | |
892 | BUG_ON(len % 4); | |
893 | do { | |
894 | *dw = cpu_to_le32(*dw); | |
895 | dw++; | |
896 | len -= 4; | |
897 | } while (len); | |
898 | #endif /* __BIG_ENDIAN */ | |
899 | } | |
900 | ||
0532d4e3 KA |
901 | #define be_cmd_status(status) (status > 0 ? -EIO : status) |
902 | ||
6b7c5b94 SP |
903 | static inline u8 is_tcp_pkt(struct sk_buff *skb) |
904 | { | |
905 | u8 val = 0; | |
906 | ||
907 | if (ip_hdr(skb)->version == 4) | |
908 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
909 | else if (ip_hdr(skb)->version == 6) | |
910 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
911 | ||
912 | return val; | |
913 | } | |
914 | ||
915 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
916 | { | |
917 | u8 val = 0; | |
918 | ||
919 | if (ip_hdr(skb)->version == 4) | |
920 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
921 | else if (ip_hdr(skb)->version == 6) | |
922 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
923 | ||
924 | return val; | |
925 | } | |
926 | ||
93040ae5 SK |
927 | static inline bool is_ipv4_pkt(struct sk_buff *skb) |
928 | { | |
e8efcec5 | 929 | return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; |
93040ae5 SK |
930 | } |
931 | ||
710f3e59 SB |
932 | #define be_error_recovering(adapter) \ |
933 | (adapter->flags & BE_FLAGS_TRY_RECOVERY) | |
934 | ||
954f6825 VD |
935 | #define BE_ERROR_EEH 1 |
936 | #define BE_ERROR_UE BIT(1) | |
937 | #define BE_ERROR_FW BIT(2) | |
938 | #define BE_ERROR_HW (BE_ERROR_EEH | BE_ERROR_UE) | |
939 | #define BE_ERROR_ANY (BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW) | |
940 | #define BE_CLEAR_ALL 0xFF | |
941 | ||
942 | static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type) | |
4b972914 | 943 | { |
954f6825 | 944 | return (adapter->err_flags & err_type); |
4b972914 AK |
945 | } |
946 | ||
954f6825 | 947 | static inline void be_set_error(struct be_adapter *adapter, int err_type) |
6589ade0 | 948 | { |
954f6825 VD |
949 | struct net_device *netdev = adapter->netdev; |
950 | ||
951 | adapter->err_flags |= err_type; | |
952 | netif_carrier_off(netdev); | |
953 | ||
954 | dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name); | |
f67ef7ba PR |
955 | } |
956 | ||
954f6825 | 957 | static inline void be_clear_error(struct be_adapter *adapter, int err_type) |
f67ef7ba | 958 | { |
954f6825 | 959 | adapter->err_flags &= ~err_type; |
f67ef7ba PR |
960 | } |
961 | ||
954f6825 | 962 | static inline bool be_multi_rxq(const struct be_adapter *adapter) |
f67ef7ba | 963 | { |
954f6825 | 964 | return adapter->num_rx_qs > 1; |
6589ade0 SP |
965 | } |
966 | ||
31886e87 JP |
967 | void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
968 | u16 num_popped); | |
969 | void be_link_status_update(struct be_adapter *adapter, u8 link_status); | |
970 | void be_parse_stats(struct be_adapter *adapter); | |
971 | int be_load_fw(struct be_adapter *adapter, u8 *func); | |
972 | bool be_is_wol_supported(struct be_adapter *adapter); | |
973 | bool be_pause_supported(struct be_adapter *adapter); | |
974 | u32 be_get_fw_log_level(struct be_adapter *adapter); | |
68d7bdcb SP |
975 | int be_update_queues(struct be_adapter *adapter); |
976 | int be_poll(struct napi_struct *napi, int budget); | |
20947770 | 977 | void be_eqd_update(struct be_adapter *adapter, bool force_update); |
941a77d5 | 978 | |
045508a8 PP |
979 | /* |
980 | * internal function to initialize-cleanup roce device. | |
981 | */ | |
31886e87 JP |
982 | void be_roce_dev_add(struct be_adapter *); |
983 | void be_roce_dev_remove(struct be_adapter *); | |
045508a8 PP |
984 | |
985 | /* | |
986 | * internal function to open-close roce device during ifup-ifdown. | |
987 | */ | |
d114f99a | 988 | void be_roce_dev_shutdown(struct be_adapter *); |
045508a8 | 989 | |
6b7c5b94 | 990 | #endif /* BE_H */ |