[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_hw.h

/*
 * Copyright (C) 2005 - 2015 Emulex
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@emulex.com
 *
 * Emulex
 * 3333 Susan Street
 * Costa Mesa, CA 92626
 */

/********* Mailbox door bell *************/
/* Used for driver communication with the FW.
 * The software must write this register twice to post any command. First,
 * it writes the register with hi=1 and the upper bits of the physical address
 * for the MAILBOX structure. Software must poll the ready bit until this
 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
 * bits in the address. It must poll the ready bit until the command is
 * complete. Upon completion, the MAILBOX will contain a valid completion
 * queue entry.
 */
#define MPU_MAILBOX_DB_OFFSET	0x160
#define MPU_MAILBOX_DB_RDY_MASK	0x1 	/* bit 0 */
#define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */

#define MPU_EP_CONTROL 		0

/********** MPU semphore: used for SH & BE  *************/
#define SLIPORT_SOFTRESET_OFFSET		0x5c	/* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_BEx		0xac  /* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
#define POST_STAGE_MASK				0x0000FFFF
#define POST_ERR_MASK				0x1
#define POST_ERR_SHIFT				31
#define POST_ERR_RECOVERY_CODE_MASK		0xFFF

/* Soft Reset register masks */
#define SLIPORT_SOFTRESET_SR_MASK		0x00000080	/* SR bit */

/* MPU semphore POST stage values */
#define POST_STAGE_AWAITING_HOST_RDY 	0x1 /* FW awaiting goahead from host */
#define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
#define POST_STAGE_BE_RESET		0x3 /* Host wants to reset chip */
#define POST_STAGE_ARMFW_RDY		0xc000	/* FW is done with POST */
#define POST_STAGE_RECOVERABLE_ERR	0xE000	/* Recoverable err detected */

/* Lancer SLIPORT registers */
#define SLIPORT_STATUS_OFFSET		0x404
#define SLIPORT_CONTROL_OFFSET		0x408
#define SLIPORT_ERROR1_OFFSET		0x40C
#define SLIPORT_ERROR2_OFFSET		0x410
#define PHYSDEV_CONTROL_OFFSET		0x414

#define SLIPORT_STATUS_ERR_MASK		0x80000000
#define SLIPORT_STATUS_DIP_MASK		0x02000000
#define SLIPORT_STATUS_RN_MASK		0x01000000
#define SLIPORT_STATUS_RDY_MASK		0x00800000
#define SLI_PORT_CONTROL_IP_MASK	0x08000000
#define PHYSDEV_CONTROL_FW_RESET_MASK	0x00000002
#define PHYSDEV_CONTROL_DD_MASK		0x00000004
#define PHYSDEV_CONTROL_INP_MASK	0x40000000

#define SLIPORT_ERROR_NO_RESOURCE1	0x2
#define SLIPORT_ERROR_NO_RESOURCE2	0x9

#define SLIPORT_ERROR_FW_RESET1		0x2
#define SLIPORT_ERROR_FW_RESET2		0x0

/********* Memory BAR register ************/
#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 	0xfc
/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 * Disable" may still globally block interrupts in addition to individual
 * interrupt masks; a mechanism for the device driver to block all interrupts
 * atomically without having to arbitrate for the PCI Interrupt Disable bit
 * with the OS.
 */
#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	BIT(29) /* bit 29 */

/********* PCI Function Capability *********/
#define BE_FUNCTION_CAPS_RSS			0x2
#define BE_FUNCTION_CAPS_SUPER_NIC		0x40

/********* Power management (WOL) **********/
#define PCICFG_PM_CONTROL_OFFSET		0x44
#define PCICFG_PM_CONTROL_MASK			0x108	/* bits 3 & 8 */

/********* Online Control Registers *******/
#define PCICFG_ONLINE0				0xB0
#define PCICFG_ONLINE1				0xB4

/********* UE Status and Mask Registers ***/
#define PCICFG_UE_STATUS_LOW			0xA0
#define PCICFG_UE_STATUS_HIGH			0xA4
#define PCICFG_UE_STATUS_LOW_MASK		0xA8
#define PCICFG_UE_STATUS_HI_MASK		0xAC

/******** SLI_INTF ***********************/
#define SLI_INTF_REG_OFFSET			0x58
#define SLI_INTF_VALID_MASK			0xE0000000
#define SLI_INTF_VALID				0xC0000000
#define SLI_INTF_HINT2_MASK			0x1F000000
#define SLI_INTF_HINT2_SHIFT			24
#define SLI_INTF_HINT1_MASK			0x00FF0000
#define SLI_INTF_HINT1_SHIFT			16
#define SLI_INTF_FAMILY_MASK			0x00000F00
#define SLI_INTF_FAMILY_SHIFT			8
#define SLI_INTF_IF_TYPE_MASK			0x0000F000
#define SLI_INTF_IF_TYPE_SHIFT			12
#define SLI_INTF_REV_MASK			0x000000F0
#define SLI_INTF_REV_SHIFT			4
#define SLI_INTF_FT_MASK			0x00000001

#define SLI_INTF_TYPE_2		2
#define SLI_INTF_TYPE_3		3

/********* ISR0 Register offset **********/
#define CEV_ISR0_OFFSET 			0xC18
#define CEV_ISR_SIZE				4

/********* Event Q door bell *************/
#define DB_EQ_OFFSET			DB_CQ_OFFSET
#define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
#define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
#define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */

/* Clear the interrupt for this eq */
#define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
/* Must be 1 */
#define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
/* Number of event entries processed */
#define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
/* Rearm bit */
#define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
/* Rearm to interrupt delay encoding */
#define DB_EQ_R2I_DLY_SHIFT		(30)    /* bits 30 - 31 */

/* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different
 * values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is
 * programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay
 * between rearming the EQ and next interrupt on this EQ is desired.
 */
#define	R2I_DLY_ENC_0			0	/* No delay */
#define	R2I_DLY_ENC_1			1	/* maps to 160us EQ delay */
#define	R2I_DLY_ENC_2			2	/* maps to 96us EQ delay */
#define	R2I_DLY_ENC_3			3	/* maps to 48us EQ delay */

/********* Compl Q door bell *************/
#define DB_CQ_OFFSET 			0x120
#define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
#define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
#define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
						 placing at 11-15 */

/* Number of event entries processed */
#define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
/* Rearm bit */
#define DB_CQ_REARM_SHIFT		(29) 	/* bit 29 */

/********** TX ULP door bell *************/
#define DB_TXULP1_OFFSET		0x60
#define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
/* Number of tx entries posted */
#define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
#define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */

/********** RQ(erx) door bell ************/
#define DB_RQ_OFFSET 			0x100
#define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
/* Number of rx frags posted */
#define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */

/********** MCC door bell ************/
#define DB_MCCQ_OFFSET 			0x140
#define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
/* Number of entries posted */
#define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */

/********** SRIOV VF PCICFG OFFSET ********/
#define SRIOV_VF_PCICFG_OFFSET		(4096)

/********** FAT TABLE  ********/
#define RETRIEVE_FAT	0
#define QUERY_FAT	1

/************* Rx Packet Type Encoding **************/
#define BE_UNICAST_PACKET		0
#define BE_MULTICAST_PACKET		1
#define BE_BROADCAST_PACKET		2
#define BE_RSVD_PACKET			3

/*
 * BE descriptors: host memory data structures whose formats
 * are hardwired in BE silicon.
 */
/* Event Queue Descriptor */
#define EQ_ENTRY_VALID_MASK 		0x1	/* bit 0 */
#define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
#define EQ_ENTRY_RES_ID_SHIFT 		16

struct be_eq_entry {
	u32 evt;
};

/* TX Queue Descriptor */
#define ETH_WRB_FRAG_LEN_MASK		0xFFFF
struct be_eth_wrb {
	__le32 frag_pa_hi;		/* dword 0 */
	__le32 frag_pa_lo;		/* dword 1 */
	u32 rsvd0;			/* dword 2 */
	__le32 frag_len;		/* dword 3: bits 0 - 15 */
} __packed;

/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 * actual structure is defined as a byte : used to calculate
 * offset/shift/mask of each field */
struct amap_eth_hdr_wrb {
	u8 rsvd0[32];		/* dword 0 */
	u8 rsvd1[32];		/* dword 1 */
	u8 complete;		/* dword 2 */
	u8 event;
	u8 crc;
	u8 forward;
	u8 lso6;
	u8 mgmt;
	u8 ipcs;
	u8 udpcs;
	u8 tcpcs;
	u8 lso;
	u8 vlan;
	u8 gso[2];
	u8 num_wrb[5];
	u8 lso_mss[14];
	u8 len[16];		/* dword 3 */
	u8 vlan_tag[16];
} __packed;

#define TX_HDR_WRB_COMPL		1		/* word 2 */
#define TX_HDR_WRB_EVT			BIT(1)		/* word 2 */
#define TX_HDR_WRB_NUM_SHIFT		13		/* word 2: bits 13:17 */
#define TX_HDR_WRB_NUM_MASK		0x1F		/* word 2: bits 13:17 */

struct be_eth_hdr_wrb {
	__le32 dw[4];
};

/********* Tx Compl Status Encoding *********/
#define BE_TX_COMP_HDR_PARSE_ERR	0x2
#define BE_TX_COMP_NDMA_ERR		0x3
#define BE_TX_COMP_ACL_ERR		0x5

#define LANCER_TX_COMP_LSO_ERR			0x1
#define LANCER_TX_COMP_HSW_DROP_MAC_ERR		0x3
#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR	0x5
#define LANCER_TX_COMP_QINQ_ERR			0x7
#define LANCER_TX_COMP_PARITY_ERR		0xb
#define LANCER_TX_COMP_DMA_ERR			0xd

/* TX Compl Queue Descriptor */

/* Pseudo amap definition for eth_tx_compl in which each bit of the
 * actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_tx_compl {
	u8 wrb_index[16];	/* dword 0 */
	u8 ct[2]; 		/* dword 0 */
	u8 port[2];		/* dword 0 */
	u8 rsvd0[8];		/* dword 0 */
	u8 status[4];		/* dword 0 */
	u8 user_bytes[16];	/* dword 1 */
	u8 nwh_bytes[8];	/* dword 1 */
	u8 lso;			/* dword 1 */
	u8 cast_enc[2];		/* dword 1 */
	u8 rsvd1[5];		/* dword 1 */
	u8 rsvd2[32];		/* dword 2 */
	u8 pkts[16];		/* dword 3 */
	u8 ringid[11];		/* dword 3 */
	u8 hash_val[4];		/* dword 3 */
	u8 valid;		/* dword 3 */
} __packed;

struct be_eth_tx_compl {
	u32 dw[4];
};

/* RX Queue Descriptor */
struct be_eth_rx_d {
	u32 fragpa_hi;
	u32 fragpa_lo;
};

/* RX Compl Queue Descriptor */

/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
 * each bit of the actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_rx_compl_v0 {
	u8 vlan_tag[16];	/* dword 0 */
	u8 pktsize[14];		/* dword 0 */
	u8 port;		/* dword 0 */
	u8 ip_opt;		/* dword 0 */
	u8 err;			/* dword 1 */
	u8 rsshp;		/* dword 1 */
	u8 ipf;			/* dword 1 */
	u8 tcpf;		/* dword 1 */
	u8 udpf;		/* dword 1 */
	u8 ipcksm;		/* dword 1 */
	u8 l4_cksm;		/* dword 1 */
	u8 ip_version;		/* dword 1 */
	u8 macdst[6];		/* dword 1 */
	u8 vtp;			/* dword 1 */
	u8 ip_frag;		/* dword 1 */
	u8 fragndx[10];		/* dword 1 */
	u8 ct[2];		/* dword 1 */
	u8 sw;			/* dword 1 */
	u8 numfrags[3];		/* dword 1 */
	u8 rss_flush;		/* dword 2 */
	u8 cast_enc[2];		/* dword 2 */
	u8 qnq;			/* dword 2 */
	u8 rss_bank;		/* dword 2 */
	u8 rsvd1[23];		/* dword 2 */
	u8 lro_pkt;		/* dword 2 */
	u8 rsvd2[2];		/* dword 2 */
	u8 valid;		/* dword 2 */
	u8 rsshash[32];		/* dword 3 */
} __packed;

/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
 * each bit of the actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_rx_compl_v1 {
	u8 vlan_tag[16];	/* dword 0 */
	u8 pktsize[14];		/* dword 0 */
	u8 vtp;			/* dword 0 */
	u8 ip_opt;		/* dword 0 */
	u8 err;			/* dword 1 */
	u8 rsshp;		/* dword 1 */
	u8 ipf;			/* dword 1 */
	u8 tcpf;		/* dword 1 */
	u8 udpf;		/* dword 1 */
	u8 ipcksm;		/* dword 1 */
	u8 l4_cksm;		/* dword 1 */
	u8 ip_version;		/* dword 1 */
	u8 macdst[7];		/* dword 1 */
	u8 rsvd0;		/* dword 1 */
	u8 fragndx[10];		/* dword 1 */
	u8 ct[2];		/* dword 1 */
	u8 sw;			/* dword 1 */
	u8 numfrags[3];		/* dword 1 */
	u8 rss_flush;		/* dword 2 */
	u8 cast_enc[2];		/* dword 2 */
	u8 qnq;			/* dword 2 */
	u8 rss_bank;		/* dword 2 */
	u8 port[2];		/* dword 2 */
	u8 vntagp;		/* dword 2 */
	u8 header_len[8];	/* dword 2 */
	u8 header_split[2];	/* dword 2 */
	u8 rsvd1[12];		/* dword 2 */
	u8 tunneled;
	u8 valid;		/* dword 2 */
	u8 rsshash[32];		/* dword 3 */
} __packed;

struct be_eth_rx_compl {
	u32 dw[4];
};
Commit	Line	Data
6b7c5b94	1	/*
d19261b8	2	* Copyright (C) 2005 - 2015 Emulex
6b7c5b94 SP	3	* All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation. The full GNU General
	8	* Public License is included in this distribution in the file called COPYING.
	9	*
	10	* Contact Information:
d2145cde	11	* linux-drivers@emulex.com
6b7c5b94	12	*
d2145cde AK	13	* Emulex
	14	* 3333 Susan Street
	15	* Costa Mesa, CA 92626
6b7c5b94 SP	16	*/
	17
	18	/******* Mailbox door bell ***********/
	19	/* Used for driver communication with the FW.
	20	* The software must write this register twice to post any command. First,
	21	* it writes the register with hi=1 and the upper bits of the physical address
	22	* for the MAILBOX structure. Software must poll the ready bit until this
	23	* is acknowledged. Then, sotware writes the register with hi=0 with the lower
	24	* bits in the address. It must poll the ready bit until the command is
	25	* complete. Upon completion, the MAILBOX will contain a valid completion
	26	* queue entry.
	27	*/
	28	#define MPU_MAILBOX_DB_OFFSET 0x160
	29	#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
	30	#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
	31
	32	#define MPU_EP_CONTROL 0
	33
1bc8e7e4	34	/******** MPU semphore: used for SH & BE ***********/
710f3e59	35	#define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
c5b3ad4c SP	36	#define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
c5b3ad4c SP	37	#define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
1bc8e7e4 SP	38	#define POST_STAGE_MASK 0x0000FFFF
	39	#define POST_ERR_MASK 0x1
	40	#define POST_ERR_SHIFT 31
710f3e59 SB	41	#define POST_ERR_RECOVERY_CODE_MASK 0xFFF
	42
	43	/* Soft Reset register masks */
	44	#define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
fe6d2a38	45
6b7c5b94 SP	46	/* MPU semphore POST stage values */
	47	#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
	48	#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
	49	#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
	50	#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
710f3e59	51	#define POST_STAGE_RECOVERABLE_ERR 0xE000 /* Recoverable err detected */
37eed1cb	52
f67ef7ba	53	/* Lancer SLIPORT registers */
37eed1cb PR	54	#define SLIPORT_STATUS_OFFSET 0x404
37eed1cb PR	55	#define SLIPORT_CONTROL_OFFSET 0x408
e1cfb67a PR	56	#define SLIPORT_ERROR1_OFFSET 0x40C
e1cfb67a PR	57	#define SLIPORT_ERROR2_OFFSET 0x410
f67ef7ba	58	#define PHYSDEV_CONTROL_OFFSET 0x414
37eed1cb PR	59
37eed1cb PR	60	#define SLIPORT_STATUS_ERR_MASK 0x80000000
5c510811	61	#define SLIPORT_STATUS_DIP_MASK 0x02000000
37eed1cb PR	62	#define SLIPORT_STATUS_RN_MASK 0x01000000
37eed1cb PR	63	#define SLIPORT_STATUS_RDY_MASK 0x00800000
37eed1cb	64	#define SLI_PORT_CONTROL_IP_MASK 0x08000000
f67ef7ba	65	#define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
5c510811	66	#define PHYSDEV_CONTROL_DD_MASK 0x00000004
f67ef7ba	67	#define PHYSDEV_CONTROL_INP_MASK 0x40000000
37eed1cb	68
67297ad8 PR	69	#define SLIPORT_ERROR_NO_RESOURCE1 0x2
	70	#define SLIPORT_ERROR_NO_RESOURCE2 0x9
	71
4bebb56a SK	72	#define SLIPORT_ERROR_FW_RESET1 0x2
	73	#define SLIPORT_ERROR_FW_RESET2 0x0
	74
6b7c5b94 SP	75	/******* Memory BAR register **********/
	76	#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
	77	/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
	78	* Disable" may still globally block interrupts in addition to individual
	79	* interrupt masks; a mechanism for the device driver to block all interrupts
	80	* atomically without having to arbitrate for the PCI Interrupt Disable bit
	81	* with the OS.
	82	*/
83b06116	83	#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK BIT(29) /* bit 29 */
6b7c5b94	84
94d73aaa VV	85	/******* PCI Function Capability *******/
	86	#define BE_FUNCTION_CAPS_RSS 0x2
	87	#define BE_FUNCTION_CAPS_SUPER_NIC 0x40
	88
65155b37	89	/******* Power management (WOL) ********/
71d8d1b5 AK	90	#define PCICFG_PM_CONTROL_OFFSET 0x44
	91	#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
	92
7c185276 AK	93	/******* Online Control Registers *****/
	94	#define PCICFG_ONLINE0 0xB0
	95	#define PCICFG_ONLINE1 0xB4
	96
	97	/******* UE Status and Mask Registers */
	98	#define PCICFG_UE_STATUS_LOW 0xA0
	99	#define PCICFG_UE_STATUS_HIGH 0xA4
	100	#define PCICFG_UE_STATUS_LOW_MASK 0xA8
	101	#define PCICFG_UE_STATUS_HI_MASK 0xAC
	102
fe6d2a38 SP	103	/****** SLI_INTF *********************/
	104	#define SLI_INTF_REG_OFFSET 0x58
	105	#define SLI_INTF_VALID_MASK 0xE0000000
	106	#define SLI_INTF_VALID 0xC0000000
	107	#define SLI_INTF_HINT2_MASK 0x1F000000
	108	#define SLI_INTF_HINT2_SHIFT 24
	109	#define SLI_INTF_HINT1_MASK 0x00FF0000
	110	#define SLI_INTF_HINT1_SHIFT 16
	111	#define SLI_INTF_FAMILY_MASK 0x00000F00
	112	#define SLI_INTF_FAMILY_SHIFT 8
	113	#define SLI_INTF_IF_TYPE_MASK 0x0000F000
	114	#define SLI_INTF_IF_TYPE_SHIFT 12
	115	#define SLI_INTF_REV_MASK 0x000000F0
	116	#define SLI_INTF_REV_SHIFT 4
	117	#define SLI_INTF_FT_MASK 0x00000001
	118
045508a8 PP	119	#define SLI_INTF_TYPE_2 2
045508a8 PP	120	#define SLI_INTF_TYPE_3 3
fe6d2a38	121
c001c213 SP	122	/******* ISR0 Register offset ********/
	123	#define CEV_ISR0_OFFSET 0xC18
	124	#define CEV_ISR_SIZE 4
	125
6b7c5b94 SP	126	/******* Event Q door bell ***********/
	127	#define DB_EQ_OFFSET DB_CQ_OFFSET
	128	#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
fe6d2a38 SP	129	#define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
	130	#define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
	131
6b7c5b94 SP	132	/* Clear the interrupt for this eq */
	133	#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
	134	/* Must be 1 */
5fb379ee	135	#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
6b7c5b94 SP	136	/* Number of event entries processed */
	137	#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
	138	/* Rearm bit */
	139	#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
20947770 PR	140	/* Rearm to interrupt delay encoding */
	141	#define DB_EQ_R2I_DLY_SHIFT (30) /* bits 30 - 31 */
	142
	143	/* Rearm to interrupt (R2I) delay multiplier encoding represents 3 different
	144	* values configured in CEV_REARM2IRPT_DLY_MULT_CSR register. This value is
	145	* programmed by host driver while ringing an EQ doorbell(EQ_DB) if a delay
	146	* between rearming the EQ and next interrupt on this EQ is desired.
	147	*/
	148	#define R2I_DLY_ENC_0 0 /* No delay */
	149	#define R2I_DLY_ENC_1 1 /* maps to 160us EQ delay */
	150	#define R2I_DLY_ENC_2 2 /* maps to 96us EQ delay */
	151	#define R2I_DLY_ENC_3 3 /* maps to 48us EQ delay */
6b7c5b94 SP	152
	153	/******* Compl Q door bell ***********/
	154	#define DB_CQ_OFFSET 0x120
	155	#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
fe6d2a38 SP	156	#define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
	157	#define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
	158	placing at 11-15 */
	159
6b7c5b94 SP	160	/* Number of event entries processed */
	161	#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
	162	/* Rearm bit */
	163	#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
	164
	165	/******** TX ULP door bell ***********/
	166	#define DB_TXULP1_OFFSET 0x60
	167	#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
	168	/* Number of tx entries posted */
	169	#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
	170	#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
	171
	172	/******** RQ(erx) door bell **********/
	173	#define DB_RQ_OFFSET 0x100
	174	#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
	175	/* Number of rx frags posted */
	176	#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
	177
5fb379ee SP	178	/******** MCC door bell **********/
	179	#define DB_MCCQ_OFFSET 0x140
	180	#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
	181	/* Number of entries posted */
	182	#define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
	183
ba343c77 SB	184	/******** SRIOV VF PCICFG OFFSET ******/
	185	#define SRIOV_VF_PCICFG_OFFSET (4096)
	186
311fddc7 SK	187	/******** FAT TABLE ******/
	188	#define RETRIEVE_FAT 0
	189	#define QUERY_FAT 1
	190
1ef78abe AK	191	/*********** Rx Packet Type Encoding ************/
	192	#define BE_UNICAST_PACKET 0
	193	#define BE_MULTICAST_PACKET 1
	194	#define BE_BROADCAST_PACKET 2
	195	#define BE_RSVD_PACKET 3
3f0d4560	196
6b7c5b94 SP	197	/*
	198	* BE descriptors: host memory data structures whose formats
	199	* are hardwired in BE silicon.
	200	*/
	201	/* Event Queue Descriptor */
	202	#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
	203	#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
	204	#define EQ_ENTRY_RES_ID_SHIFT 16
3f0d4560	205
6b7c5b94 SP	206	struct be_eq_entry {
	207	u32 evt;
	208	};
	209
	210	/* TX Queue Descriptor */
	211	#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
	212	struct be_eth_wrb {
f986afcb SP	213	__le32 frag_pa_hi; /* dword 0 */
	214	__le32 frag_pa_lo; /* dword 1 */
	215	u32 rsvd0; /* dword 2 */
	216	__le32 frag_len; /* dword 3: bits 0 - 15 */
6b7c5b94 SP	217	} __packed;
	218
	219	/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
	220	* actual structure is defined as a byte : used to calculate
	221	* offset/shift/mask of each field */
	222	struct amap_eth_hdr_wrb {
	223	u8 rsvd0[32]; /* dword 0 */
	224	u8 rsvd1[32]; /* dword 1 */
	225	u8 complete; /* dword 2 */
	226	u8 event;
	227	u8 crc;
	228	u8 forward;
49e4b847	229	u8 lso6;
6b7c5b94 SP	230	u8 mgmt;
	231	u8 ipcs;
	232	u8 udpcs;
	233	u8 tcpcs;
	234	u8 lso;
	235	u8 vlan;
	236	u8 gso[2];
	237	u8 num_wrb[5];
	238	u8 lso_mss[14];
	239	u8 len[16]; /* dword 3 */
	240	u8 vlan_tag[16];
	241	} __packed;
	242
5f07b3c5	243	#define TX_HDR_WRB_COMPL 1 /* word 2 */
83b06116	244	#define TX_HDR_WRB_EVT BIT(1) /* word 2 */
5f07b3c5 SP	245	#define TX_HDR_WRB_NUM_SHIFT 13 /* word 2: bits 13:17 */
	246	#define TX_HDR_WRB_NUM_MASK 0x1F /* word 2: bits 13:17 */
	247
6b7c5b94	248	struct be_eth_hdr_wrb {
f986afcb	249	__le32 dw[4];
6b7c5b94 SP	250	};
6b7c5b94 SP	251
512bb8a2 KA	252	/******* Tx Compl Status Encoding *******/
	253	#define BE_TX_COMP_HDR_PARSE_ERR 0x2
	254	#define BE_TX_COMP_NDMA_ERR 0x3
	255	#define BE_TX_COMP_ACL_ERR 0x5
	256
	257	#define LANCER_TX_COMP_LSO_ERR 0x1
	258	#define LANCER_TX_COMP_HSW_DROP_MAC_ERR 0x3
	259	#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR 0x5
	260	#define LANCER_TX_COMP_QINQ_ERR 0x7
	261	#define LANCER_TX_COMP_PARITY_ERR 0xb
	262	#define LANCER_TX_COMP_DMA_ERR 0xd
	263
6b7c5b94 SP	264	/* TX Compl Queue Descriptor */
	265
	266	/* Pseudo amap definition for eth_tx_compl in which each bit of the
	267	* actual structure is defined as a byte: used to calculate
	268	* offset/shift/mask of each field */
	269	struct amap_eth_tx_compl {
	270	u8 wrb_index[16]; /* dword 0 */
	271	u8 ct[2]; /* dword 0 */
	272	u8 port[2]; /* dword 0 */
	273	u8 rsvd0[8]; /* dword 0 */
	274	u8 status[4]; /* dword 0 */
	275	u8 user_bytes[16]; /* dword 1 */
	276	u8 nwh_bytes[8]; /* dword 1 */
	277	u8 lso; /* dword 1 */
	278	u8 cast_enc[2]; /* dword 1 */
	279	u8 rsvd1[5]; /* dword 1 */
	280	u8 rsvd2[32]; /* dword 2 */
	281	u8 pkts[16]; /* dword 3 */
	282	u8 ringid[11]; /* dword 3 */
	283	u8 hash_val[4]; /* dword 3 */
	284	u8 valid; /* dword 3 */
	285	} __packed;
	286
	287	struct be_eth_tx_compl {
	288	u32 dw[4];
	289	};
	290
	291	/* RX Queue Descriptor */
	292	struct be_eth_rx_d {
	293	u32 fragpa_hi;
	294	u32 fragpa_lo;
	295	};
	296
	297	/* RX Compl Queue Descriptor */
	298
2e588f84 SP	299	/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
2e588f84 SP	300	* each bit of the actual structure is defined as a byte: used to calculate
6b7c5b94	301	* offset/shift/mask of each field */
2e588f84	302	struct amap_eth_rx_compl_v0 {
6b7c5b94 SP	303	u8 vlan_tag[16]; /* dword 0 */
	304	u8 pktsize[14]; /* dword 0 */
	305	u8 port; /* dword 0 */
	306	u8 ip_opt; /* dword 0 */
	307	u8 err; /* dword 1 */
	308	u8 rsshp; /* dword 1 */
	309	u8 ipf; /* dword 1 */
	310	u8 tcpf; /* dword 1 */
	311	u8 udpf; /* dword 1 */
	312	u8 ipcksm; /* dword 1 */
	313	u8 l4_cksm; /* dword 1 */
	314	u8 ip_version; /* dword 1 */
	315	u8 macdst[6]; /* dword 1 */
	316	u8 vtp; /* dword 1 */
e38b1706	317	u8 ip_frag; /* dword 1 */
6b7c5b94 SP	318	u8 fragndx[10]; /* dword 1 */
	319	u8 ct[2]; /* dword 1 */
	320	u8 sw; /* dword 1 */
	321	u8 numfrags[3]; /* dword 1 */
	322	u8 rss_flush; /* dword 2 */
	323	u8 cast_enc[2]; /* dword 2 */
f93f160b	324	u8 qnq; /* dword 2 */
6b7c5b94 SP	325	u8 rss_bank; /* dword 2 */
	326	u8 rsvd1[23]; /* dword 2 */
	327	u8 lro_pkt; /* dword 2 */
	328	u8 rsvd2[2]; /* dword 2 */
	329	u8 valid; /* dword 2 */
	330	u8 rsshash[32]; /* dword 3 */
	331	} __packed;
	332
2e588f84 SP	333	/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
	334	* each bit of the actual structure is defined as a byte: used to calculate
	335	* offset/shift/mask of each field */
	336	struct amap_eth_rx_compl_v1 {
	337	u8 vlan_tag[16]; /* dword 0 */
	338	u8 pktsize[14]; /* dword 0 */
	339	u8 vtp; /* dword 0 */
	340	u8 ip_opt; /* dword 0 */
	341	u8 err; /* dword 1 */
	342	u8 rsshp; /* dword 1 */
	343	u8 ipf; /* dword 1 */
	344	u8 tcpf; /* dword 1 */
	345	u8 udpf; /* dword 1 */
	346	u8 ipcksm; /* dword 1 */
	347	u8 l4_cksm; /* dword 1 */
	348	u8 ip_version; /* dword 1 */
	349	u8 macdst[7]; /* dword 1 */
	350	u8 rsvd0; /* dword 1 */
	351	u8 fragndx[10]; /* dword 1 */
	352	u8 ct[2]; /* dword 1 */
	353	u8 sw; /* dword 1 */
	354	u8 numfrags[3]; /* dword 1 */
	355	u8 rss_flush; /* dword 2 */
	356	u8 cast_enc[2]; /* dword 2 */
f93f160b	357	u8 qnq; /* dword 2 */
2e588f84 SP	358	u8 rss_bank; /* dword 2 */
	359	u8 port[2]; /* dword 2 */
	360	u8 vntagp; /* dword 2 */
	361	u8 header_len[8]; /* dword 2 */
	362	u8 header_split[2]; /* dword 2 */
c9c47142 SP	363	u8 rsvd1[12]; /* dword 2 */
c9c47142 SP	364	u8 tunneled;
2e588f84 SP	365	u8 valid; /* dword 2 */
	366	u8 rsshash[32]; /* dword 3 */
	367	} __packed;
	368
6b7c5b94 SP	369	struct be_eth_rx_compl {
	370	u32 dw[4];
	371	};