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Merge remote-tracking branch 'md/for-next'
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_adminq_cmd.h
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
3b120089 4 * Copyright(c) 2013 - 2016 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_ADMINQ_CMD_H_
28#define _I40E_ADMINQ_CMD_H_
29
30/* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
8c570dcc 36#define I40E_FW_API_VERSION_MAJOR 0x0001
97b884fe 37#define I40E_FW_API_VERSION_MINOR 0x0005
56a62fc8
JB		 38
39struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61};
62
63/* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68/* command flags and offsets*/
8c570dcc
JK		 69#define I40E_AQ_FLAG_DD_SHIFT 0
70#define I40E_AQ_FLAG_CMP_SHIFT 1
71#define I40E_AQ_FLAG_ERR_SHIFT 2
72#define I40E_AQ_FLAG_VFE_SHIFT 3
73#define I40E_AQ_FLAG_LB_SHIFT 9
74#define I40E_AQ_FLAG_RD_SHIFT 10
75#define I40E_AQ_FLAG_VFC_SHIFT 11
76#define I40E_AQ_FLAG_BUF_SHIFT 12
77#define I40E_AQ_FLAG_SI_SHIFT 13
78#define I40E_AQ_FLAG_EI_SHIFT 14
79#define I40E_AQ_FLAG_FE_SHIFT 15
80
2101bac2
JK		 81#define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82#define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84#define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87#define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90#define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91#define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
56a62fc8
JB		 92
93/* error codes */
94enum i40e_admin_queue_err {
8c570dcc
JK		 95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
56a62fc8
JB		 118};
119
120/* Admin Queue command opcodes */
121enum i40e_admin_queue_opc {
122 /* aq commands */
8c570dcc
JK		 123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
56a62fc8
JB		 127
128 /* resource ownership */
8c570dcc
JK		 129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
56a62fc8 131
8c570dcc
JK		 132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
56a62fc8 134
56a62fc8 135 /* LAA */
8c570dcc
JK		 136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
56a62fc8 138
981b7545 139 /* PXE */
8c570dcc 140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
981b7545 141
56a62fc8 142 /* internal switch commands */
8c570dcc
JK		 143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
fa5623a6 148 i40e_aqc_opc_set_switch_config = 0x0205,
33365143
SN		 149 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
150 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
8c570dcc
JK		 151
152 i40e_aqc_opc_add_vsi = 0x0210,
153 i40e_aqc_opc_update_vsi_parameters = 0x0211,
154 i40e_aqc_opc_get_vsi_parameters = 0x0212,
155
156 i40e_aqc_opc_add_pv = 0x0220,
157 i40e_aqc_opc_update_pv_parameters = 0x0221,
158 i40e_aqc_opc_get_pv_parameters = 0x0222,
159
160 i40e_aqc_opc_add_veb = 0x0230,
161 i40e_aqc_opc_update_veb_parameters = 0x0231,
162 i40e_aqc_opc_get_veb_parameters = 0x0232,
163
164 i40e_aqc_opc_delete_element = 0x0243,
165
166 i40e_aqc_opc_add_macvlan = 0x0250,
167 i40e_aqc_opc_remove_macvlan = 0x0251,
168 i40e_aqc_opc_add_vlan = 0x0252,
169 i40e_aqc_opc_remove_vlan = 0x0253,
170 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
171 i40e_aqc_opc_add_tag = 0x0255,
172 i40e_aqc_opc_remove_tag = 0x0256,
173 i40e_aqc_opc_add_multicast_etag = 0x0257,
174 i40e_aqc_opc_remove_multicast_etag = 0x0258,
175 i40e_aqc_opc_update_tag = 0x0259,
176 i40e_aqc_opc_add_control_packet_filter = 0x025A,
177 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
178 i40e_aqc_opc_add_cloud_filters = 0x025C,
179 i40e_aqc_opc_remove_cloud_filters = 0x025D,
180
181 i40e_aqc_opc_add_mirror_rule = 0x0260,
182 i40e_aqc_opc_delete_mirror_rule = 0x0261,
56a62fc8 183
56a62fc8 184 /* DCB commands */
8c570dcc
JK		 185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
186 i40e_aqc_opc_dcb_updated = 0x0302,
56a62fc8
JB		 187
188 /* TX scheduler */
8c570dcc
JK		 189 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
190 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
191 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
192 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
193 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
194 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
195
196 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
197 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
198 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
199 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
200 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
201 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
202 i40e_aqc_opc_query_port_ets_config = 0x0419,
203 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
204 i40e_aqc_opc_suspend_port_tx = 0x041B,
205 i40e_aqc_opc_resume_port_tx = 0x041C,
206 i40e_aqc_opc_configure_partition_bw = 0x041D,
7d94906b
CW		 207 /* hmc */
208 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
209 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
56a62fc8 210
56a62fc8 211 /* phy commands*/
8c570dcc
JK		 212 i40e_aqc_opc_get_phy_abilities = 0x0600,
213 i40e_aqc_opc_set_phy_config = 0x0601,
214 i40e_aqc_opc_set_mac_config = 0x0603,
215 i40e_aqc_opc_set_link_restart_an = 0x0605,
216 i40e_aqc_opc_get_link_status = 0x0607,
217 i40e_aqc_opc_set_phy_int_mask = 0x0613,
218 i40e_aqc_opc_get_local_advt_reg = 0x0614,
219 i40e_aqc_opc_set_local_advt_reg = 0x0615,
220 i40e_aqc_opc_get_partner_advt = 0x0616,
221 i40e_aqc_opc_set_lb_modes = 0x0618,
222 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
223 i40e_aqc_opc_set_phy_debug = 0x0622,
224 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
5394f02f 225 i40e_aqc_opc_run_phy_activity = 0x0626,
56a62fc8
JB		 226
227 /* NVM commands */
8c570dcc
JK		 228 i40e_aqc_opc_nvm_read = 0x0701,
229 i40e_aqc_opc_nvm_erase = 0x0702,
230 i40e_aqc_opc_nvm_update = 0x0703,
231 i40e_aqc_opc_nvm_config_read = 0x0704,
232 i40e_aqc_opc_nvm_config_write = 0x0705,
00ada50d 233 i40e_aqc_opc_oem_post_update = 0x0720,
6774faf9 234 i40e_aqc_opc_thermal_sensor = 0x0721,
56a62fc8
JB		 235
236 /* virtualization commands */
8c570dcc
JK		 237 i40e_aqc_opc_send_msg_to_pf = 0x0801,
238 i40e_aqc_opc_send_msg_to_vf = 0x0802,
239 i40e_aqc_opc_send_msg_to_peer = 0x0803,
56a62fc8
JB		 240
241 /* alternate structure */
8c570dcc
JK		 242 i40e_aqc_opc_alternate_write = 0x0900,
243 i40e_aqc_opc_alternate_write_indirect = 0x0901,
244 i40e_aqc_opc_alternate_read = 0x0902,
245 i40e_aqc_opc_alternate_read_indirect = 0x0903,
246 i40e_aqc_opc_alternate_write_done = 0x0904,
247 i40e_aqc_opc_alternate_set_mode = 0x0905,
248 i40e_aqc_opc_alternate_clear_port = 0x0906,
56a62fc8
JB		 249
250 /* LLDP commands */
8c570dcc
JK		 251 i40e_aqc_opc_lldp_get_mib = 0x0A00,
252 i40e_aqc_opc_lldp_update_mib = 0x0A01,
253 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
254 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
255 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
256 i40e_aqc_opc_lldp_stop = 0x0A05,
257 i40e_aqc_opc_lldp_start = 0x0A06,
9fa61dd2 258 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
672415c5
SN		 259 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
260 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
56a62fc8
JB		 261
262 /* Tunnel commands */
8c570dcc
JK		 263 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
264 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
e50c8d6d
ASJ		 265 i40e_aqc_opc_set_rss_key = 0x0B02,
266 i40e_aqc_opc_set_rss_lut = 0x0B03,
267 i40e_aqc_opc_get_rss_key = 0x0B04,
268 i40e_aqc_opc_get_rss_lut = 0x0B05,
56a62fc8
JB		 269
270 /* Async Events */
8c570dcc 271 i40e_aqc_opc_event_lan_overflow = 0x1001,
56a62fc8
JB		 272
273 /* OEM commands */
8c570dcc
JK		 274 i40e_aqc_opc_oem_parameter_change = 0xFE00,
275 i40e_aqc_opc_oem_device_status_change = 0xFE01,
672415c5
SN		 276 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
277 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
56a62fc8
JB		 278
279 /* debug commands */
8c570dcc
JK		 280 i40e_aqc_opc_debug_read_reg = 0xFF03,
281 i40e_aqc_opc_debug_write_reg = 0xFF04,
282 i40e_aqc_opc_debug_modify_reg = 0xFF07,
283 i40e_aqc_opc_debug_dump_internals = 0xFF08,
56a62fc8
JB		 284};
285
286/* command structures and indirect data structures */
287
288/* Structure naming conventions:
289 * - no suffix for direct command descriptor structures
290 * - _data for indirect sent data
291 * - _resp for indirect return data (data which is both will use _data)
292 * - _completion for direct return data
293 * - _element_ for repeated elements (may also be _data or _resp)
294 *
295 * Command structures are expected to overlay the params.raw member of the basic
296 * descriptor, and as such cannot exceed 16 bytes in length.
297 */
298
299/* This macro is used to generate a compilation error if a structure
300 * is not exactly the correct length. It gives a divide by zero error if the
301 * structure is not of the correct size, otherwise it creates an enum that is
302 * never used.
303 */
304#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
305 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
306
307/* This macro is used extensively to ensure that command structures are 16
308 * bytes in length as they have to map to the raw array of that size.
309 */
8c570dcc 310#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
56a62fc8
JB		 311
312/* internal (0x00XX) commands */
313
314/* Get version (direct 0x0001) */
315struct i40e_aqc_get_version {
316 __le32 rom_ver;
317 __le32 fw_build;
318 __le16 fw_major;
319 __le16 fw_minor;
320 __le16 api_major;
321 __le16 api_minor;
322};
323
324I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
325
981b7545 326/* Send driver version (indirect 0x0002) */
56a62fc8 327struct i40e_aqc_driver_version {
8c570dcc
JK		 328 u8 driver_major_ver;
329 u8 driver_minor_ver;
330 u8 driver_build_ver;
331 u8 driver_subbuild_ver;
332 u8 reserved[4];
333 __le32 address_high;
334 __le32 address_low;
56a62fc8
JB		 335};
336
337I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
338
339/* Queue Shutdown (direct 0x0003) */
340struct i40e_aqc_queue_shutdown {
8c570dcc
JK		 341 __le32 driver_unloading;
342#define I40E_AQ_DRIVER_UNLOADING 0x1
343 u8 reserved[12];
56a62fc8
JB		 344};
345
346I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
347
f94234ee
SN		 348/* Set PF context (0x0004, direct) */
349struct i40e_aqc_set_pf_context {
350 u8 pf_id;
351 u8 reserved[15];
352};
353
354I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
355
56a62fc8
JB		 356/* Request resource ownership (direct 0x0008)
357 * Release resource ownership (direct 0x0009)
358 */
8c570dcc
JK		 359#define I40E_AQ_RESOURCE_NVM 1
360#define I40E_AQ_RESOURCE_SDP 2
361#define I40E_AQ_RESOURCE_ACCESS_READ 1
362#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
363#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
364#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
56a62fc8
JB		 365
366struct i40e_aqc_request_resource {
8c570dcc
JK		 367 __le16 resource_id;
368 __le16 access_type;
369 __le32 timeout;
370 __le32 resource_number;
371 u8 reserved[4];
56a62fc8
JB		 372};
373
374I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
375
376/* Get function capabilities (indirect 0x000A)
377 * Get device capabilities (indirect 0x000B)
378 */
379struct i40e_aqc_list_capabilites {
380 u8 command_flags;
8c570dcc 381#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
56a62fc8
JB		 382 u8 pf_index;
383 u8 reserved[2];
384 __le32 count;
385 __le32 addr_high;
386 __le32 addr_low;
387};
388
389I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
390
391struct i40e_aqc_list_capabilities_element_resp {
8c570dcc
JK		 392 __le16 id;
393 u8 major_rev;
394 u8 minor_rev;
395 __le32 number;
396 __le32 logical_id;
397 __le32 phys_id;
398 u8 reserved[16];
56a62fc8
JB		 399};
400
401/* list of caps */
402
8c570dcc
JK		 403#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
404#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
405#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
406#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
407#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
408#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
4ba40bce 409#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
8c570dcc
JK		 410#define I40E_AQ_CAP_ID_SRIOV 0x0012
411#define I40E_AQ_CAP_ID_VF 0x0013
412#define I40E_AQ_CAP_ID_VMDQ 0x0014
413#define I40E_AQ_CAP_ID_8021QBG 0x0015
414#define I40E_AQ_CAP_ID_8021QBR 0x0016
415#define I40E_AQ_CAP_ID_VSI 0x0017
416#define I40E_AQ_CAP_ID_DCB 0x0018
417#define I40E_AQ_CAP_ID_FCOE 0x0021
35155fe6 418#define I40E_AQ_CAP_ID_ISCSI 0x0022
8c570dcc
JK		 419#define I40E_AQ_CAP_ID_RSS 0x0040
420#define I40E_AQ_CAP_ID_RXQ 0x0041
421#define I40E_AQ_CAP_ID_TXQ 0x0042
422#define I40E_AQ_CAP_ID_MSIX 0x0043
423#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
424#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
425#define I40E_AQ_CAP_ID_1588 0x0046
426#define I40E_AQ_CAP_ID_IWARP 0x0051
427#define I40E_AQ_CAP_ID_LED 0x0061
428#define I40E_AQ_CAP_ID_SDP 0x0062
429#define I40E_AQ_CAP_ID_MDIO 0x0063
406e734a 430#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
68a1c5a7 431#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
8c570dcc
JK		 432#define I40E_AQ_CAP_ID_FLEX10 0x00F1
433#define I40E_AQ_CAP_ID_CEM 0x00F2
56a62fc8
JB		 434
435/* Set CPPM Configuration (direct 0x0103) */
436struct i40e_aqc_cppm_configuration {
8c570dcc
JK		 437 __le16 command_flags;
438#define I40E_AQ_CPPM_EN_LTRC 0x0800
439#define I40E_AQ_CPPM_EN_DMCTH 0x1000
440#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
441#define I40E_AQ_CPPM_EN_HPTC 0x4000
442#define I40E_AQ_CPPM_EN_DMARC 0x8000
443 __le16 ttlx;
444 __le32 dmacr;
445 __le16 dmcth;
446 u8 hptc;
447 u8 reserved;
448 __le32 pfltrc;
56a62fc8
JB		 449};
450
451I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
452
453/* Set ARP Proxy command / response (indirect 0x0104) */
454struct i40e_aqc_arp_proxy_data {
8c570dcc 455 __le16 command_flags;
b7eeef49
CW		 456#define I40E_AQ_ARP_INIT_IPV4 0x0800
457#define I40E_AQ_ARP_UNSUP_CTL 0x1000
458#define I40E_AQ_ARP_ENA 0x2000
459#define I40E_AQ_ARP_ADD_IPV4 0x4000
460#define I40E_AQ_ARP_DEL_IPV4 0x8000
8c570dcc 461 __le16 table_id;
b7eeef49
CW		 462 __le32 enabled_offloads;
463#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
464#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
8c570dcc
JK		 465 __le32 ip_addr;
466 u8 mac_addr[6];
672415c5 467 u8 reserved[2];
56a62fc8
JB		 468};
469
8d5e33ad
SN		 470I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
471
56a62fc8
JB		 472/* Set NS Proxy Table Entry Command (indirect 0x0105) */
473struct i40e_aqc_ns_proxy_data {
8c570dcc
JK		 474 __le16 table_idx_mac_addr_0;
475 __le16 table_idx_mac_addr_1;
476 __le16 table_idx_ipv6_0;
477 __le16 table_idx_ipv6_1;
478 __le16 control;
b7eeef49
CW		 479#define I40E_AQ_NS_PROXY_ADD_0 0x0001
480#define I40E_AQ_NS_PROXY_DEL_0 0x0002
481#define I40E_AQ_NS_PROXY_ADD_1 0x0004
482#define I40E_AQ_NS_PROXY_DEL_1 0x0008
483#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
484#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
485#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
486#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
487#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
488#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
489#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
490#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
491#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
8c570dcc
JK		 492 u8 mac_addr_0[6];
493 u8 mac_addr_1[6];
494 u8 local_mac_addr[6];
495 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
496 u8 ipv6_addr_1[16];
56a62fc8
JB		 497};
498
8d5e33ad
SN		 499I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
500
56a62fc8
JB		 501/* Manage LAA Command (0x0106) - obsolete */
502struct i40e_aqc_mng_laa {
503 __le16 command_flags;
8c570dcc
JK		 504#define I40E_AQ_LAA_FLAG_WR 0x8000
505 u8 reserved[2];
506 __le32 sal;
507 __le16 sah;
508 u8 reserved2[6];
56a62fc8
JB		 509};
510
8d5e33ad
SN		 511I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
512
981b7545 513/* Manage MAC Address Read Command (indirect 0x0107) */
56a62fc8
JB		 514struct i40e_aqc_mac_address_read {
515 __le16 command_flags;
8c570dcc
JK		 516#define I40E_AQC_LAN_ADDR_VALID 0x10
517#define I40E_AQC_SAN_ADDR_VALID 0x20
518#define I40E_AQC_PORT_ADDR_VALID 0x40
519#define I40E_AQC_WOL_ADDR_VALID 0x80
cb2f65bc
GR		 520#define I40E_AQC_MC_MAG_EN_VALID 0x100
521#define I40E_AQC_ADDR_VALID_MASK 0x1F0
8c570dcc
JK		 522 u8 reserved[6];
523 __le32 addr_high;
524 __le32 addr_low;
56a62fc8
JB		 525};
526
527I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
528
529struct i40e_aqc_mac_address_read_data {
530 u8 pf_lan_mac[6];
531 u8 pf_san_mac[6];
532 u8 port_mac[6];
533 u8 pf_wol_mac[6];
534};
535
536I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
537
538/* Manage MAC Address Write Command (0x0108) */
539struct i40e_aqc_mac_address_write {
8c570dcc
JK		 540 __le16 command_flags;
541#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
542#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
543#define I40E_AQC_WRITE_TYPE_PORT 0x8000
cb2f65bc
GR		 544#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
545#define I40E_AQC_WRITE_TYPE_MASK 0xC000
546
8c570dcc
JK		 547 __le16 mac_sah;
548 __le32 mac_sal;
549 u8 reserved[8];
56a62fc8
JB		 550};
551
552I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
553
981b7545
SN		 554/* PXE commands (0x011x) */
555
556/* Clear PXE Command and response (direct 0x0110) */
557struct i40e_aqc_clear_pxe {
558 u8 rx_cnt;
559 u8 reserved[15];
560};
561
562I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
563
56a62fc8
JB		 564/* Switch configuration commands (0x02xx) */
565
566/* Used by many indirect commands that only pass an seid and a buffer in the
567 * command
568 */
569struct i40e_aqc_switch_seid {
8c570dcc
JK		 570 __le16 seid;
571 u8 reserved[6];
572 __le32 addr_high;
573 __le32 addr_low;
56a62fc8
JB		 574};
575
576I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
577
578/* Get Switch Configuration command (indirect 0x0200)
579 * uses i40e_aqc_switch_seid for the descriptor
580 */
581struct i40e_aqc_get_switch_config_header_resp {
8c570dcc
JK		 582 __le16 num_reported;
583 __le16 num_total;
584 u8 reserved[12];
56a62fc8
JB		 585};
586
8d5e33ad
SN		 587I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
588
56a62fc8 589struct i40e_aqc_switch_config_element_resp {
8c570dcc
JK		 590 u8 element_type;
591#define I40E_AQ_SW_ELEM_TYPE_MAC 1
592#define I40E_AQ_SW_ELEM_TYPE_PF 2
593#define I40E_AQ_SW_ELEM_TYPE_VF 3
594#define I40E_AQ_SW_ELEM_TYPE_EMP 4
595#define I40E_AQ_SW_ELEM_TYPE_BMC 5
596#define I40E_AQ_SW_ELEM_TYPE_PV 16
597#define I40E_AQ_SW_ELEM_TYPE_VEB 17
598#define I40E_AQ_SW_ELEM_TYPE_PA 18
599#define I40E_AQ_SW_ELEM_TYPE_VSI 19
600 u8 revision;
601#define I40E_AQ_SW_ELEM_REV_1 1
602 __le16 seid;
603 __le16 uplink_seid;
604 __le16 downlink_seid;
605 u8 reserved[3];
606 u8 connection_type;
607#define I40E_AQ_CONN_TYPE_REGULAR 0x1
608#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
609#define I40E_AQ_CONN_TYPE_CASCADED 0x3
610 __le16 scheduler_id;
611 __le16 element_info;
56a62fc8
JB		 612};
613
8d5e33ad
SN		 614I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
615
56a62fc8
JB		 616/* Get Switch Configuration (indirect 0x0200)
617 * an array of elements are returned in the response buffer
618 * the first in the array is the header, remainder are elements
619 */
620struct i40e_aqc_get_switch_config_resp {
8c570dcc
JK		 621 struct i40e_aqc_get_switch_config_header_resp header;
622 struct i40e_aqc_switch_config_element_resp element[1];
56a62fc8
JB		 623};
624
8d5e33ad
SN		 625I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
626
56a62fc8
JB		 627/* Add Statistics (direct 0x0201)
628 * Remove Statistics (direct 0x0202)
629 */
630struct i40e_aqc_add_remove_statistics {
8c570dcc
JK		 631 __le16 seid;
632 __le16 vlan;
633 __le16 stat_index;
634 u8 reserved[10];
56a62fc8
JB		 635};
636
637I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
638
639/* Set Port Parameters command (direct 0x0203) */
640struct i40e_aqc_set_port_parameters {
8c570dcc
JK		 641 __le16 command_flags;
642#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
643#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
644#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
645 __le16 bad_frame_vsi;
646 __le16 default_seid; /* reserved for command */
647 u8 reserved[10];
56a62fc8
JB		 648};
649
650I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
651
652/* Get Switch Resource Allocation (indirect 0x0204) */
653struct i40e_aqc_get_switch_resource_alloc {
8c570dcc
JK		 654 u8 num_entries; /* reserved for command */
655 u8 reserved[7];
656 __le32 addr_high;
657 __le32 addr_low;
56a62fc8
JB		 658};
659
660I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
661
662/* expect an array of these structs in the response buffer */
663struct i40e_aqc_switch_resource_alloc_element_resp {
8c570dcc
JK		 664 u8 resource_type;
665#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
666#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
667#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
668#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
669#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
670#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
671#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
672#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
673#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
674#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
675#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
676#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
677#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
678#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
679#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
680#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
681#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
682#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
683#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
684 u8 reserved1;
685 __le16 guaranteed;
686 __le16 total;
687 __le16 used;
688 __le16 total_unalloced;
689 u8 reserved2[6];
56a62fc8
JB		 690};
691
8d5e33ad
SN		 692I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
693
fa5623a6
SN		 694/* Set Switch Configuration (direct 0x0205) */
695struct i40e_aqc_set_switch_config {
696 __le16 flags;
697#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
698#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
699 __le16 valid_flags;
700 u8 reserved[12];
701};
702
703I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
704
33365143
SN		 705/* Read Receive control registers (direct 0x0206)
706 * Write Receive control registers (direct 0x0207)
707 * used for accessing Rx control registers that can be
708 * slow and need special handling when under high Rx load
709 */
710struct i40e_aqc_rx_ctl_reg_read_write {
711 __le32 reserved1;
712 __le32 address;
713 __le32 reserved2;
714 __le32 value;
715};
716
717I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
718
981b7545 719/* Add VSI (indirect 0x0210)
56a62fc8
JB		 720 * this indirect command uses struct i40e_aqc_vsi_properties_data
721 * as the indirect buffer (128 bytes)
722 *
981b7545
SN		 723 * Update VSI (indirect 0x211)
724 * uses the same data structure as Add VSI
725 *
726 * Get VSI (indirect 0x0212)
727 * uses the same completion and data structure as Add VSI
56a62fc8
JB		 728 */
729struct i40e_aqc_add_get_update_vsi {
8c570dcc
JK		 730 __le16 uplink_seid;
731 u8 connection_type;
732#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
733#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
734#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
735 u8 reserved1;
736 u8 vf_id;
737 u8 reserved2;
738 __le16 vsi_flags;
739#define I40E_AQ_VSI_TYPE_SHIFT 0x0
740#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
741#define I40E_AQ_VSI_TYPE_VF 0x0
742#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
743#define I40E_AQ_VSI_TYPE_PF 0x2
744#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
745#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
746 __le32 addr_high;
747 __le32 addr_low;
56a62fc8
JB		 748};
749
750I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
751
752struct i40e_aqc_add_get_update_vsi_completion {
753 __le16 seid;
754 __le16 vsi_number;
755 __le16 vsi_used;
756 __le16 vsi_free;
757 __le32 addr_high;
758 __le32 addr_low;
759};
760
761I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
762
763struct i40e_aqc_vsi_properties_data {
764 /* first 96 byte are written by SW */
8c570dcc
JK		 765 __le16 valid_sections;
766#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
767#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
768#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
769#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
770#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
771#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
772#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
773#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
774#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
775#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
56a62fc8 776 /* switch section */
8c570dcc
JK		 777 __le16 switch_id; /* 12bit id combined with flags below */
778#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
779#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
780#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
781#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
782#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
783 u8 sw_reserved[2];
56a62fc8 784 /* security section */
8c570dcc
JK		 785 u8 sec_flags;
786#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
787#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
788#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
789 u8 sec_reserved;
56a62fc8 790 /* VLAN section */
8c570dcc
JK		 791 __le16 pvid; /* VLANS include priority bits */
792 __le16 fcoe_pvid;
793 u8 port_vlan_flags;
794#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
795#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
796 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
797#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
798#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
799#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
800#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
801#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
802#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
803 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
804#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
805#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
806#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
807#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
808 u8 pvlan_reserved[3];
56a62fc8 809 /* ingress egress up sections */
8c570dcc
JK		 810 __le32 ingress_table; /* bitmap, 3 bits per up */
811#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
812#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
813 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
814#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
815#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
816 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
817#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
818#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
819 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
820#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
821#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
822 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
823#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
824#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
825 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
826#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
827#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
828 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
829#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
830#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
831 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
832#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
833#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
834 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
835 __le32 egress_table; /* same defines as for ingress table */
56a62fc8 836 /* cascaded PV section */
8c570dcc
JK		 837 __le16 cas_pv_tag;
838 u8 cas_pv_flags;
839#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
840#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
841 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
842#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
843#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
844#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
845#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
846#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
847#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
848 u8 cas_pv_reserved;
56a62fc8 849 /* queue mapping section */
8c570dcc
JK		 850 __le16 mapping_flags;
851#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
852#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
853 __le16 queue_mapping[16];
854#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
855#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
856 __le16 tc_mapping[8];
857#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
858#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
859 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
860#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
861#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
862 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
56a62fc8 863 /* queueing option section */
8c570dcc 864 u8 queueing_opt_flags;
e50c8d6d
ASJ		 865#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
866#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
8c570dcc
JK		 867#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
868#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
e50c8d6d
ASJ		 869#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
870#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
8c570dcc 871 u8 queueing_opt_reserved[3];
56a62fc8 872 /* scheduler section */
8c570dcc
JK		 873 u8 up_enable_bits;
874 u8 sched_reserved;
56a62fc8 875 /* outer up section */
8c570dcc
JK		 876 __le32 outer_up_table; /* same structure and defines as ingress tbl */
877 u8 cmd_reserved[8];
56a62fc8 878 /* last 32 bytes are written by FW */
8c570dcc 879 __le16 qs_handle[8];
56a62fc8 880#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
8c570dcc
JK		 881 __le16 stat_counter_idx;
882 __le16 sched_id;
883 u8 resp_reserved[12];
56a62fc8
JB		 884};
885
886I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
887
888/* Add Port Virtualizer (direct 0x0220)
889 * also used for update PV (direct 0x0221) but only flags are used
890 * (IS_CTRL_PORT only works on add PV)
891 */
892struct i40e_aqc_add_update_pv {
8c570dcc
JK		 893 __le16 command_flags;
894#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
895#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
896#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
897#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
898 __le16 uplink_seid;
899 __le16 connected_seid;
900 u8 reserved[10];
56a62fc8
JB		 901};
902
903I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
904
905struct i40e_aqc_add_update_pv_completion {
906 /* reserved for update; for add also encodes error if rc == ENOSPC */
8c570dcc
JK		 907 __le16 pv_seid;
908#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
909#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
910#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
911#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
912 u8 reserved[14];
56a62fc8
JB		 913};
914
915I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
916
917/* Get PV Params (direct 0x0222)
918 * uses i40e_aqc_switch_seid for the descriptor
919 */
920
921struct i40e_aqc_get_pv_params_completion {
8c570dcc
JK		 922 __le16 seid;
923 __le16 default_stag;
924 __le16 pv_flags; /* same flags as add_pv */
925#define I40E_AQC_GET_PV_PV_TYPE 0x1
926#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
927#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
928 u8 reserved[8];
929 __le16 default_port_seid;
56a62fc8
JB		 930};
931
932I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
933
934/* Add VEB (direct 0x0230) */
935struct i40e_aqc_add_veb {
8c570dcc
JK		 936 __le16 uplink_seid;
937 __le16 downlink_seid;
938 __le16 veb_flags;
939#define I40E_AQC_ADD_VEB_FLOATING 0x1
940#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
941#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
56a62fc8 942 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
8c570dcc
JK		 943#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
944#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
fa5623a6
SN		 945#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
946#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
8c570dcc
JK		 947 u8 enable_tcs;
948 u8 reserved[9];
56a62fc8
JB		 949};
950
951I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
952
953struct i40e_aqc_add_veb_completion {
8c570dcc
JK		 954 u8 reserved[6];
955 __le16 switch_seid;
56a62fc8 956 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
8c570dcc
JK		 957 __le16 veb_seid;
958#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
959#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
960#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
961#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
962 __le16 statistic_index;
963 __le16 vebs_used;
964 __le16 vebs_free;
56a62fc8
JB		 965};
966
967I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
968
969/* Get VEB Parameters (direct 0x0232)
970 * uses i40e_aqc_switch_seid for the descriptor
971 */
972struct i40e_aqc_get_veb_parameters_completion {
8c570dcc
JK		 973 __le16 seid;
974 __le16 switch_id;
975 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
976 __le16 statistic_index;
977 __le16 vebs_used;
978 __le16 vebs_free;
979 u8 reserved[4];
56a62fc8
JB		 980};
981
982I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
983
984/* Delete Element (direct 0x0243)
985 * uses the generic i40e_aqc_switch_seid
986 */
987
988/* Add MAC-VLAN (indirect 0x0250) */
989
990/* used for the command for most vlan commands */
991struct i40e_aqc_macvlan {
8c570dcc
JK		 992 __le16 num_addresses;
993 __le16 seid[3];
994#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
995#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
56a62fc8 996 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 997#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
998 __le32 addr_high;
999 __le32 addr_low;
56a62fc8
JB		 1000};
1001
1002I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1003
1004/* indirect data for command and response */
1005struct i40e_aqc_add_macvlan_element_data {
8c570dcc
JK		 1006 u8 mac_addr[6];
1007 __le16 vlan_tag;
1008 __le16 flags;
1009#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1010#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1011#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1012#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
90680779 1013#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
8c570dcc
JK		 1014 __le16 queue_number;
1015#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1016#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
56a62fc8
JB		 1017 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1018 /* response section */
8c570dcc
JK		 1019 u8 match_method;
1020#define I40E_AQC_MM_PERFECT_MATCH 0x01
1021#define I40E_AQC_MM_HASH_MATCH 0x02
1022#define I40E_AQC_MM_ERR_NO_RES 0xFF
1023 u8 reserved1[3];
56a62fc8
JB		 1024};
1025
1026struct i40e_aqc_add_remove_macvlan_completion {
1027 __le16 perfect_mac_used;
1028 __le16 perfect_mac_free;
1029 __le16 unicast_hash_free;
1030 __le16 multicast_hash_free;
1031 __le32 addr_high;
1032 __le32 addr_low;
1033};
1034
1035I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1036
1037/* Remove MAC-VLAN (indirect 0x0251)
1038 * uses i40e_aqc_macvlan for the descriptor
1039 * data points to an array of num_addresses of elements
1040 */
1041
1042struct i40e_aqc_remove_macvlan_element_data {
8c570dcc
JK		 1043 u8 mac_addr[6];
1044 __le16 vlan_tag;
1045 u8 flags;
1046#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1047#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1048#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1049#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1050 u8 reserved[3];
56a62fc8 1051 /* reply section */
8c570dcc
JK		 1052 u8 error_code;
1053#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1054#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1055 u8 reply_reserved[3];
56a62fc8
JB		 1056};
1057
1058/* Add VLAN (indirect 0x0252)
1059 * Remove VLAN (indirect 0x0253)
1060 * use the generic i40e_aqc_macvlan for the command
1061 */
1062struct i40e_aqc_add_remove_vlan_element_data {
8c570dcc
JK		 1063 __le16 vlan_tag;
1064 u8 vlan_flags;
56a62fc8 1065/* flags for add VLAN */
8c570dcc
JK		 1066#define I40E_AQC_ADD_VLAN_LOCAL 0x1
1067#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1068#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1069#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1070#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1071#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1072#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1073#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1074#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1075#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1076#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1077#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
56a62fc8 1078/* flags for remove VLAN */
8c570dcc
JK		 1079#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1080 u8 reserved;
1081 u8 result;
56a62fc8 1082/* flags for add VLAN */
8c570dcc
JK		 1083#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1084#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1085#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
56a62fc8 1086/* flags for remove VLAN */
8c570dcc
JK		 1087#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1088#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1089 u8 reserved1[3];
56a62fc8
JB		 1090};
1091
1092struct i40e_aqc_add_remove_vlan_completion {
8c570dcc
JK		 1093 u8 reserved[4];
1094 __le16 vlans_used;
1095 __le16 vlans_free;
1096 __le32 addr_high;
1097 __le32 addr_low;
56a62fc8
JB		 1098};
1099
1100/* Set VSI Promiscuous Modes (direct 0x0254) */
1101struct i40e_aqc_set_vsi_promiscuous_modes {
8c570dcc
JK		 1102 __le16 promiscuous_flags;
1103 __le16 valid_flags;
56a62fc8 1104/* flags used for both fields above */
8c570dcc
JK		 1105#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1106#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1107#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1108#define I40E_AQC_SET_VSI_DEFAULT 0x08
1109#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
3b120089 1110#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
8c570dcc
JK		 1111 __le16 seid;
1112#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1113 __le16 vlan_tag;
cb2f65bc 1114#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
8c570dcc
JK		 1115#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1116 u8 reserved[8];
56a62fc8
JB		 1117};
1118
1119I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1120
1121/* Add S/E-tag command (direct 0x0255)
1122 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1123 */
1124struct i40e_aqc_add_tag {
8c570dcc
JK		 1125 __le16 flags;
1126#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1127 __le16 seid;
1128#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1129#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
56a62fc8 1130 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1131 __le16 tag;
1132 __le16 queue_number;
1133 u8 reserved[8];
56a62fc8
JB		 1134};
1135
1136I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1137
1138struct i40e_aqc_add_remove_tag_completion {
8c570dcc
JK		 1139 u8 reserved[12];
1140 __le16 tags_used;
1141 __le16 tags_free;
56a62fc8
JB		 1142};
1143
1144I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1145
1146/* Remove S/E-tag command (direct 0x0256)
1147 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1148 */
1149struct i40e_aqc_remove_tag {
8c570dcc
JK		 1150 __le16 seid;
1151#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1152#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
56a62fc8 1153 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1154 __le16 tag;
1155 u8 reserved[12];
56a62fc8
JB		 1156};
1157
8d5e33ad
SN		 1158I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1159
56a62fc8
JB		 1160/* Add multicast E-Tag (direct 0x0257)
1161 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1162 * and no external data
1163 */
1164struct i40e_aqc_add_remove_mcast_etag {
8c570dcc
JK		 1165 __le16 pv_seid;
1166 __le16 etag;
1167 u8 num_unicast_etags;
1168 u8 reserved[3];
1169 __le32 addr_high; /* address of array of 2-byte s-tags */
1170 __le32 addr_low;
56a62fc8
JB		 1171};
1172
1173I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1174
1175struct i40e_aqc_add_remove_mcast_etag_completion {
8c570dcc
JK		 1176 u8 reserved[4];
1177 __le16 mcast_etags_used;
1178 __le16 mcast_etags_free;
1179 __le32 addr_high;
1180 __le32 addr_low;
56a62fc8
JB		 1181
1182};
1183
1184I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1185
1186/* Update S/E-Tag (direct 0x0259) */
1187struct i40e_aqc_update_tag {
8c570dcc
JK		 1188 __le16 seid;
1189#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1190#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
56a62fc8 1191 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1192 __le16 old_tag;
1193 __le16 new_tag;
1194 u8 reserved[10];
56a62fc8
JB		 1195};
1196
1197I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1198
1199struct i40e_aqc_update_tag_completion {
8c570dcc
JK		 1200 u8 reserved[12];
1201 __le16 tags_used;
1202 __le16 tags_free;
56a62fc8
JB		 1203};
1204
1205I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1206
1207/* Add Control Packet filter (direct 0x025A)
1208 * Remove Control Packet filter (direct 0x025B)
1209 * uses the i40e_aqc_add_oveb_cloud,
1210 * and the generic direct completion structure
1211 */
1212struct i40e_aqc_add_remove_control_packet_filter {
8c570dcc
JK		 1213 u8 mac[6];
1214 __le16 etype;
1215 __le16 flags;
1216#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1217#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1218#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1219#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1220#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1221 __le16 seid;
1222#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1223#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
56a62fc8 1224 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1225 __le16 queue;
1226 u8 reserved[2];
56a62fc8
JB		 1227};
1228
1229I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1230
1231struct i40e_aqc_add_remove_control_packet_filter_completion {
8c570dcc
JK		 1232 __le16 mac_etype_used;
1233 __le16 etype_used;
1234 __le16 mac_etype_free;
1235 __le16 etype_free;
1236 u8 reserved[8];
56a62fc8
JB		 1237};
1238
1239I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1240
1241/* Add Cloud filters (indirect 0x025C)
1242 * Remove Cloud filters (indirect 0x025D)
1243 * uses the i40e_aqc_add_remove_cloud_filters,
1244 * and the generic indirect completion structure
1245 */
1246struct i40e_aqc_add_remove_cloud_filters {
8c570dcc
JK		 1247 u8 num_filters;
1248 u8 reserved;
1249 __le16 seid;
1250#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1251#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
56a62fc8 1252 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
8c570dcc
JK		 1253 u8 reserved2[4];
1254 __le32 addr_high;
1255 __le32 addr_low;
56a62fc8
JB		 1256};
1257
1258I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1259
1260struct i40e_aqc_add_remove_cloud_filters_element_data {
8c570dcc
JK		 1261 u8 outer_mac[6];
1262 u8 inner_mac[6];
1263 __le16 inner_vlan;
56a62fc8
JB		 1264 union {
1265 struct {
1266 u8 reserved[12];
1267 u8 data[4];
1268 } v4;
1269 struct {
1270 u8 data[16];
6838b535
JB		 1271 } v6;
1272 } ipaddr;
8c570dcc
JK		 1273 __le16 flags;
1274#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
35155fe6 1275#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
56a62fc8 1276 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
981b7545 1277/* 0x0000 reserved */
8c570dcc 1278#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
981b7545 1279/* 0x0002 reserved */
8c570dcc
JK		 1280#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1281#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
981b7545 1282/* 0x0005 reserved */
8c570dcc 1283#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
981b7545 1284/* 0x0007 reserved */
56a62fc8 1285/* 0x0008 reserved */
8c570dcc
JK		 1286#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1287#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1288#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1289#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1290
1291#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1292#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1293#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1294#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1295#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1296
1297#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1298#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
59264253 1299#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
8c570dcc 1300#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
59264253 1301#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
8c570dcc 1302#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
2fcc1a40
SN		 1303#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1304#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
8c570dcc 1305
90680779
SN		 1306#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1307#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1308#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1309
8c570dcc
JK		 1310 __le32 tenant_id;
1311 u8 reserved[4];
1312 __le16 queue_number;
1313#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
35155fe6 1314#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
8c570dcc
JK		 1315 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1316 u8 reserved2[14];
56a62fc8 1317 /* response section */
8c570dcc
JK		 1318 u8 allocation_result;
1319#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1320#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1321 u8 response_reserved[7];
56a62fc8
JB		 1322};
1323
1324struct i40e_aqc_remove_cloud_filters_completion {
1325 __le16 perfect_ovlan_used;
1326 __le16 perfect_ovlan_free;
1327 __le16 vlan_used;
1328 __le16 vlan_free;
1329 __le32 addr_high;
1330 __le32 addr_low;
1331};
1332
1333I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1334
1335/* Add Mirror Rule (indirect or direct 0x0260)
1336 * Delete Mirror Rule (indirect or direct 0x0261)
1337 * note: some rule types (4,5) do not use an external buffer.
1338 * take care to set the flags correctly.
1339 */
1340struct i40e_aqc_add_delete_mirror_rule {
1341 __le16 seid;
1342 __le16 rule_type;
8c570dcc
JK		 1343#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1344#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
56a62fc8 1345 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
8c570dcc
JK		 1346#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1347#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1348#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1349#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1350#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
56a62fc8
JB		 1351 __le16 num_entries;
1352 __le16 destination; /* VSI for add, rule id for delete */
1353 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1354 __le32 addr_low;
1355};
1356
1357I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1358
1359struct i40e_aqc_add_delete_mirror_rule_completion {
8c570dcc
JK		 1360 u8 reserved[2];
1361 __le16 rule_id; /* only used on add */
1362 __le16 mirror_rules_used;
1363 __le16 mirror_rules_free;
1364 __le32 addr_high;
1365 __le32 addr_low;
56a62fc8
JB		 1366};
1367
1368I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1369
56a62fc8
JB		 1370/* DCB 0x03xx*/
1371
1372/* PFC Ignore (direct 0x0301)
1373 * the command and response use the same descriptor structure
1374 */
1375struct i40e_aqc_pfc_ignore {
8c570dcc
JK		 1376 u8 tc_bitmap;
1377 u8 command_flags; /* unused on response */
1378#define I40E_AQC_PFC_IGNORE_SET 0x80
1379#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1380 u8 reserved[14];
56a62fc8
JB		 1381};
1382
1383I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1384
1385/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1386 * with no parameters
1387 */
1388
1389/* TX scheduler 0x04xx */
1390
1391/* Almost all the indirect commands use
1392 * this generic struct to pass the SEID in param0
1393 */
1394struct i40e_aqc_tx_sched_ind {
8c570dcc
JK		 1395 __le16 vsi_seid;
1396 u8 reserved[6];
1397 __le32 addr_high;
1398 __le32 addr_low;
56a62fc8
JB		 1399};
1400
1401I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1402
1403/* Several commands respond with a set of queue set handles */
1404struct i40e_aqc_qs_handles_resp {
1405 __le16 qs_handles[8];
1406};
1407
1408/* Configure VSI BW limits (direct 0x0400) */
1409struct i40e_aqc_configure_vsi_bw_limit {
8c570dcc
JK		 1410 __le16 vsi_seid;
1411 u8 reserved[2];
1412 __le16 credit;
1413 u8 reserved1[2];
1414 u8 max_credit; /* 0-3, limit = 2^max */
1415 u8 reserved2[7];
56a62fc8
JB		 1416};
1417
1418I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1419
1420/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1421 * responds with i40e_aqc_qs_handles_resp
1422 */
1423struct i40e_aqc_configure_vsi_ets_sla_bw_data {
8c570dcc
JK		 1424 u8 tc_valid_bits;
1425 u8 reserved[15];
1426 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
56a62fc8
JB		 1427
1428 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1429 __le16 tc_bw_max[2];
1430 u8 reserved1[28];
56a62fc8
JB		 1431};
1432
8d5e33ad
SN		 1433I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1434
56a62fc8
JB		 1435/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1436 * responds with i40e_aqc_qs_handles_resp
1437 */
1438struct i40e_aqc_configure_vsi_tc_bw_data {
8c570dcc
JK		 1439 u8 tc_valid_bits;
1440 u8 reserved[3];
1441 u8 tc_bw_credits[8];
1442 u8 reserved1[4];
1443 __le16 qs_handles[8];
56a62fc8
JB		 1444};
1445
8d5e33ad
SN		 1446I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1447
56a62fc8
JB		 1448/* Query vsi bw configuration (indirect 0x0408) */
1449struct i40e_aqc_query_vsi_bw_config_resp {
8c570dcc
JK		 1450 u8 tc_valid_bits;
1451 u8 tc_suspended_bits;
1452 u8 reserved[14];
1453 __le16 qs_handles[8];
1454 u8 reserved1[4];
1455 __le16 port_bw_limit;
1456 u8 reserved2[2];
1457 u8 max_bw; /* 0-3, limit = 2^max */
1458 u8 reserved3[23];
56a62fc8
JB		 1459};
1460
8d5e33ad
SN		 1461I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1462
56a62fc8
JB		 1463/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1464struct i40e_aqc_query_vsi_ets_sla_config_resp {
8c570dcc
JK		 1465 u8 tc_valid_bits;
1466 u8 reserved[3];
1467 u8 share_credits[8];
1468 __le16 credits[8];
56a62fc8
JB		 1469
1470 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1471 __le16 tc_bw_max[2];
56a62fc8
JB		 1472};
1473
8d5e33ad
SN		 1474I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1475
56a62fc8
JB		 1476/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1477struct i40e_aqc_configure_switching_comp_bw_limit {
8c570dcc
JK		 1478 __le16 seid;
1479 u8 reserved[2];
1480 __le16 credit;
1481 u8 reserved1[2];
1482 u8 max_bw; /* 0-3, limit = 2^max */
1483 u8 reserved2[7];
56a62fc8
JB		 1484};
1485
1486I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1487
1488/* Enable Physical Port ETS (indirect 0x0413)
1489 * Modify Physical Port ETS (indirect 0x0414)
1490 * Disable Physical Port ETS (indirect 0x0415)
1491 */
1492struct i40e_aqc_configure_switching_comp_ets_data {
8c570dcc
JK		 1493 u8 reserved[4];
1494 u8 tc_valid_bits;
1495 u8 seepage;
1496#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1497 u8 tc_strict_priority_flags;
1498 u8 reserved1[17];
1499 u8 tc_bw_share_credits[8];
1500 u8 reserved2[96];
56a62fc8
JB		 1501};
1502
8d5e33ad
SN		 1503I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1504
56a62fc8
JB		 1505/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1506struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
8c570dcc
JK		 1507 u8 tc_valid_bits;
1508 u8 reserved[15];
1509 __le16 tc_bw_credit[8];
56a62fc8
JB		 1510
1511 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc
JK		 1512 __le16 tc_bw_max[2];
1513 u8 reserved1[28];
56a62fc8
JB		 1514};
1515
8d5e33ad
SN		 1516I40E_CHECK_STRUCT_LEN(0x40,
1517 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1518
56a62fc8
JB		 1519/* Configure Switching Component Bandwidth Allocation per Tc
1520 * (indirect 0x0417)
1521 */
1522struct i40e_aqc_configure_switching_comp_bw_config_data {
8c570dcc
JK		 1523 u8 tc_valid_bits;
1524 u8 reserved[2];
1525 u8 absolute_credits; /* bool */
1526 u8 tc_bw_share_credits[8];
1527 u8 reserved1[20];
56a62fc8
JB		 1528};
1529
8d5e33ad
SN		 1530I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1531
56a62fc8
JB		 1532/* Query Switching Component Configuration (indirect 0x0418) */
1533struct i40e_aqc_query_switching_comp_ets_config_resp {
8c570dcc
JK		 1534 u8 tc_valid_bits;
1535 u8 reserved[35];
1536 __le16 port_bw_limit;
1537 u8 reserved1[2];
1538 u8 tc_bw_max; /* 0-3, limit = 2^max */
1539 u8 reserved2[23];
56a62fc8
JB		 1540};
1541
8d5e33ad
SN		 1542I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1543
56a62fc8
JB		 1544/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1545struct i40e_aqc_query_port_ets_config_resp {
8c570dcc
JK		 1546 u8 reserved[4];
1547 u8 tc_valid_bits;
1548 u8 reserved1;
1549 u8 tc_strict_priority_bits;
1550 u8 reserved2;
1551 u8 tc_bw_share_credits[8];
1552 __le16 tc_bw_limits[8];
56a62fc8
JB		 1553
1554 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
8c570dcc
JK		 1555 __le16 tc_bw_max[2];
1556 u8 reserved3[32];
56a62fc8
JB		 1557};
1558
8d5e33ad
SN		 1559I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1560
56a62fc8
JB		 1561/* Query Switching Component Bandwidth Allocation per Traffic Type
1562 * (indirect 0x041A)
1563 */
1564struct i40e_aqc_query_switching_comp_bw_config_resp {
8c570dcc
JK		 1565 u8 tc_valid_bits;
1566 u8 reserved[2];
1567 u8 absolute_credits_enable; /* bool */
1568 u8 tc_bw_share_credits[8];
1569 __le16 tc_bw_limits[8];
56a62fc8
JB		 1570
1571 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
8c570dcc 1572 __le16 tc_bw_max[2];
56a62fc8
JB		 1573};
1574
8d5e33ad
SN		 1575I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1576
56a62fc8
JB		 1577/* Suspend/resume port TX traffic
1578 * (direct 0x041B and 0x041C) uses the generic SEID struct
1579 */
1580
befc229c
SN		 1581/* Configure partition BW
1582 * (indirect 0x041D)
1583 */
1584struct i40e_aqc_configure_partition_bw_data {
8c570dcc
JK		 1585 __le16 pf_valid_bits;
1586 u8 min_bw[16]; /* guaranteed bandwidth */
1587 u8 max_bw[16]; /* bandwidth limit */
befc229c
SN		 1588};
1589
8d5e33ad
SN		 1590I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1591
7d94906b
CW		 1592/* Get and set the active HMC resource profile and status.
1593 * (direct 0x0500) and (direct 0x0501)
1594 */
1595struct i40e_aq_get_set_hmc_resource_profile {
1596 u8 pm_profile;
1597 u8 pe_vf_enabled;
1598 u8 reserved[14];
1599};
1600
1601I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1602
1603enum i40e_aq_hmc_profile {
1604 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1605 I40E_HMC_PROFILE_DEFAULT = 1,
1606 I40E_HMC_PROFILE_FAVOR_VF = 2,
1607 I40E_HMC_PROFILE_EQUAL = 3,
1608};
1609
56a62fc8
JB		 1610/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1611
1612/* set in param0 for get phy abilities to report qualified modules */
8c570dcc
JK		 1613#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1614#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
56a62fc8
JB		 1615
1616enum i40e_aq_phy_type {
1617 I40E_PHY_TYPE_SGMII = 0x0,
1618 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1619 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1620 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1621 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1622 I40E_PHY_TYPE_XAUI = 0x5,
1623 I40E_PHY_TYPE_XFI = 0x6,
1624 I40E_PHY_TYPE_SFI = 0x7,
1625 I40E_PHY_TYPE_XLAUI = 0x8,
1626 I40E_PHY_TYPE_XLPPI = 0x9,
1627 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1628 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
f94234ee
SN		 1629 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1630 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
56a62fc8
JB		 1631 I40E_PHY_TYPE_100BASE_TX = 0x11,
1632 I40E_PHY_TYPE_1000BASE_T = 0x12,
1633 I40E_PHY_TYPE_10GBASE_T = 0x13,
1634 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1635 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1636 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1637 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1638 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1639 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1640 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
f94234ee
SN		 1641 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1642 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1643 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1644 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
56a62fc8
JB		 1645 I40E_PHY_TYPE_MAX
1646};
1647
1648#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1649#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1650#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1651#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1652#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1653
1654enum i40e_aq_link_speed {
1655 I40E_LINK_SPEED_UNKNOWN = 0,
2101bac2
JK		 1656 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1657 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1658 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1659 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1660 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT)
56a62fc8
JB		 1661};
1662
1663struct i40e_aqc_module_desc {
1664 u8 oui[3];
1665 u8 reserved1;
1666 u8 part_number[16];
1667 u8 revision[4];
1668 u8 reserved2[8];
1669};
1670
8d5e33ad
SN		 1671I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1672
56a62fc8 1673struct i40e_aq_get_phy_abilities_resp {
8c570dcc
JK		 1674 __le32 phy_type; /* bitmap using the above enum for offsets */
1675 u8 link_speed; /* bitmap using the above enum bit patterns */
1676 u8 abilities;
1677#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1678#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1679#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1680#define I40E_AQ_PHY_LINK_ENABLED 0x08
1681#define I40E_AQ_PHY_AN_ENABLED 0x10
1682#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1683 __le16 eee_capability;
1684#define I40E_AQ_EEE_100BASE_TX 0x0002
1685#define I40E_AQ_EEE_1000BASE_T 0x0004
1686#define I40E_AQ_EEE_10GBASE_T 0x0008
1687#define I40E_AQ_EEE_1000BASE_KX 0x0010
1688#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1689#define I40E_AQ_EEE_10GBASE_KR 0x0040
1690 __le32 eeer_val;
1691 u8 d3_lpan;
1692#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1693 u8 reserved[3];
1694 u8 phy_id[4];
1695 u8 module_type[3];
1696 u8 qualified_module_count;
1697#define I40E_AQ_PHY_MAX_QMS 16
1698 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
56a62fc8
JB		 1699};
1700
8d5e33ad
SN		 1701I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1702
56a62fc8
JB		 1703/* Set PHY Config (direct 0x0601) */
1704struct i40e_aq_set_phy_config { /* same bits as above in all */
8c570dcc
JK		 1705 __le32 phy_type;
1706 u8 link_speed;
1707 u8 abilities;
981b7545
SN		 1708/* bits 0-2 use the values from get_phy_abilities_resp */
1709#define I40E_AQ_PHY_ENABLE_LINK 0x08
1710#define I40E_AQ_PHY_ENABLE_AN 0x10
1711#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
8c570dcc
JK		 1712 __le16 eee_capability;
1713 __le32 eeer;
1714 u8 low_power_ctrl;
1715 u8 reserved[3];
56a62fc8
JB		 1716};
1717
1718I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1719
1720/* Set MAC Config command data structure (direct 0x0603) */
1721struct i40e_aq_set_mac_config {
8c570dcc
JK		 1722 __le16 max_frame_size;
1723 u8 params;
1724#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1725#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1726#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1727#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1728#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1729#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1730#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1731#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1732#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1733#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1734#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1735#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1736#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1737#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1738 u8 tx_timer_priority; /* bitmap */
1739 __le16 tx_timer_value;
1740 __le16 fc_refresh_threshold;
1741 u8 reserved[8];
56a62fc8
JB		 1742};
1743
1744I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1745
1746/* Restart Auto-Negotiation (direct 0x605) */
1747struct i40e_aqc_set_link_restart_an {
8c570dcc
JK		 1748 u8 command;
1749#define I40E_AQ_PHY_RESTART_AN 0x02
1750#define I40E_AQ_PHY_LINK_ENABLE 0x04
1751 u8 reserved[15];
56a62fc8
JB		 1752};
1753
1754I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1755
1756/* Get Link Status cmd & response data structure (direct 0x0607) */
1757struct i40e_aqc_get_link_status {
8c570dcc
JK		 1758 __le16 command_flags; /* only field set on command */
1759#define I40E_AQ_LSE_MASK 0x3
1760#define I40E_AQ_LSE_NOP 0x0
1761#define I40E_AQ_LSE_DISABLE 0x2
1762#define I40E_AQ_LSE_ENABLE 0x3
56a62fc8 1763/* only response uses this flag */
8c570dcc
JK		 1764#define I40E_AQ_LSE_IS_ENABLED 0x1
1765 u8 phy_type; /* i40e_aq_phy_type */
1766 u8 link_speed; /* i40e_aq_link_speed */
1767 u8 link_info;
1d55aa9c
SN		 1768#define I40E_AQ_LINK_UP 0x01 /* obsolete */
1769#define I40E_AQ_LINK_UP_FUNCTION 0x01
8c570dcc
JK		 1770#define I40E_AQ_LINK_FAULT 0x02
1771#define I40E_AQ_LINK_FAULT_TX 0x04
1772#define I40E_AQ_LINK_FAULT_RX 0x08
1773#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1d55aa9c 1774#define I40E_AQ_LINK_UP_PORT 0x20
8c570dcc
JK		 1775#define I40E_AQ_MEDIA_AVAILABLE 0x40
1776#define I40E_AQ_SIGNAL_DETECT 0x80
1777 u8 an_info;
1778#define I40E_AQ_AN_COMPLETED 0x01
1779#define I40E_AQ_LP_AN_ABILITY 0x02
1780#define I40E_AQ_PD_FAULT 0x04
1781#define I40E_AQ_FEC_EN 0x08
1782#define I40E_AQ_PHY_LOW_POWER 0x10
1783#define I40E_AQ_LINK_PAUSE_TX 0x20
1784#define I40E_AQ_LINK_PAUSE_RX 0x40
1785#define I40E_AQ_QUALIFIED_MODULE 0x80
1786 u8 ext_info;
1787#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1788#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1789#define I40E_AQ_LINK_TX_SHIFT 0x02
1790#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1791#define I40E_AQ_LINK_TX_ACTIVE 0x00
1792#define I40E_AQ_LINK_TX_DRAINED 0x01
1793#define I40E_AQ_LINK_TX_FLUSHED 0x03
1794#define I40E_AQ_LINK_FORCED_40G 0x10
1795 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1796 __le16 max_frame_size;
1797 u8 config;
1798#define I40E_AQ_CONFIG_CRC_ENA 0x04
1799#define I40E_AQ_CONFIG_PACING_MASK 0x78
5eb772f7
SN		 1800 u8 external_power_ability;
1801#define I40E_AQ_LINK_POWER_CLASS_1 0x00
1802#define I40E_AQ_LINK_POWER_CLASS_2 0x01
1803#define I40E_AQ_LINK_POWER_CLASS_3 0x02
1804#define I40E_AQ_LINK_POWER_CLASS_4 0x03
1805 u8 reserved[4];
56a62fc8
JB		 1806};
1807
1808I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1809
1810/* Set event mask command (direct 0x613) */
1811struct i40e_aqc_set_phy_int_mask {
8c570dcc
JK		 1812 u8 reserved[8];
1813 __le16 event_mask;
1814#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1815#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1816#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1817#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1818#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1819#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1820#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1821#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1822#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1823 u8 reserved1[6];
56a62fc8
JB		 1824};
1825
1826I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1827
1828/* Get Local AN advt register (direct 0x0614)
1829 * Set Local AN advt register (direct 0x0615)
1830 * Get Link Partner AN advt register (direct 0x0616)
1831 */
1832struct i40e_aqc_an_advt_reg {
8c570dcc
JK		 1833 __le32 local_an_reg0;
1834 __le16 local_an_reg1;
1835 u8 reserved[10];
56a62fc8
JB		 1836};
1837
1838I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1839
1840/* Set Loopback mode (0x0618) */
1841struct i40e_aqc_set_lb_mode {
8c570dcc
JK		 1842 __le16 lb_mode;
1843#define I40E_AQ_LB_PHY_LOCAL 0x01
1844#define I40E_AQ_LB_PHY_REMOTE 0x02
1845#define I40E_AQ_LB_MAC_LOCAL 0x04
1846 u8 reserved[14];
56a62fc8
JB		 1847};
1848
1849I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1850
f94234ee
SN		 1851/* Set PHY Debug command (0x0622) */
1852struct i40e_aqc_set_phy_debug {
8c570dcc 1853 u8 command_flags;
f94234ee
SN		 1854#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1855#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1856#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1857 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1858#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1859#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1860#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
06c0e39b 1861/* Disable link manageability on a single port */
f94234ee 1862#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
06c0e39b
KS		 1863/* Disable link manageability on all ports */
1864#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
8c570dcc 1865 u8 reserved[15];
56a62fc8
JB		 1866};
1867
f94234ee 1868I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
56a62fc8
JB		 1869
1870enum i40e_aq_phy_reg_type {
8c570dcc
JK		 1871 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1872 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1873 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
56a62fc8
JB		 1874};
1875
5394f02f
SN		 1876/* Run PHY Activity (0x0626) */
1877struct i40e_aqc_run_phy_activity {
1878 __le16 activity_id;
1879 u8 flags;
1880 u8 reserved1;
1881 __le32 control;
1882 __le32 data;
1883 u8 reserved2[4];
1884};
1885
1886I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1887
56a62fc8
JB		 1888/* NVM Read command (indirect 0x0701)
1889 * NVM Erase commands (direct 0x0702)
1890 * NVM Update commands (indirect 0x0703)
1891 */
1892struct i40e_aqc_nvm_update {
8c570dcc
JK		 1893 u8 command_flags;
1894#define I40E_AQ_NVM_LAST_CMD 0x01
1895#define I40E_AQ_NVM_FLASH_ONLY 0x80
1896 u8 module_pointer;
1897 __le16 length;
1898 __le32 offset;
1899 __le32 addr_high;
1900 __le32 addr_low;
56a62fc8
JB		 1901};
1902
1903I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1904
f94234ee
SN		 1905/* NVM Config Read (indirect 0x0704) */
1906struct i40e_aqc_nvm_config_read {
8c570dcc 1907 __le16 cmd_flags;
e910ca7c
JK		 1908#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1909#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1910#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
8c570dcc 1911 __le16 element_count;
e910ca7c
JK		 1912 __le16 element_id; /* Feature/field ID */
1913 __le16 element_id_msw; /* MSWord of field ID */
8c570dcc
JK		 1914 __le32 address_high;
1915 __le32 address_low;
f94234ee
SN		 1916};
1917
1918I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1919
1920/* NVM Config Write (indirect 0x0705) */
1921struct i40e_aqc_nvm_config_write {
8c570dcc
JK		 1922 __le16 cmd_flags;
1923 __le16 element_count;
1924 u8 reserved[4];
1925 __le32 address_high;
1926 __le32 address_low;
f94234ee
SN		 1927};
1928
1929I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1930
672415c5
SN		 1931/* Used for 0x0704 as well as for 0x0705 commands */
1932#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1933#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2101bac2 1934 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
672415c5 1935#define I40E_AQ_ANVM_FEATURE 0
2101bac2 1936#define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
f94234ee
SN		 1937struct i40e_aqc_nvm_config_data_feature {
1938 __le16 feature_id;
672415c5
SN		 1939#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1940#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1941#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
f94234ee
SN		 1942 __le16 feature_options;
1943 __le16 feature_selection;
1944};
1945
672415c5
SN		 1946I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1947
f94234ee 1948struct i40e_aqc_nvm_config_data_immediate_field {
672415c5
SN		 1949 __le32 field_id;
1950 __le32 field_value;
f94234ee 1951 __le16 field_options;
672415c5 1952 __le16 reserved;
f94234ee
SN		 1953};
1954
672415c5
SN		 1955I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1956
00ada50d
MK		 1957/* OEM Post Update (indirect 0x0720)
1958 * no command data struct used
1959 */
1960struct i40e_aqc_nvm_oem_post_update {
1961#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1962 u8 sel_data;
1963 u8 reserved[7];
1964};
1965
1966I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1967
1968struct i40e_aqc_nvm_oem_post_update_buffer {
1969 u8 str_len;
1970 u8 dev_addr;
1971 __le16 eeprom_addr;
1972 u8 data[36];
1973};
1974
1975I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1976
6774faf9
SN		 1977/* Thermal Sensor (indirect 0x0721)
1978 * read or set thermal sensor configs and values
1979 * takes a sensor and command specific data buffer, not detailed here
1980 */
1981struct i40e_aqc_thermal_sensor {
1982 u8 sensor_action;
1983#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
1984#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
1985#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
1986 u8 reserved[7];
1987 __le32 addr_high;
1988 __le32 addr_low;
1989};
1990
1991I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1992
56a62fc8
JB		 1993/* Send to PF command (indirect 0x0801) id is only used by PF
1994 * Send to VF command (indirect 0x0802) id is only used by PF
1995 * Send to Peer PF command (indirect 0x0803)
1996 */
1997struct i40e_aqc_pf_vf_message {
8c570dcc
JK		 1998 __le32 id;
1999 u8 reserved[4];
2000 __le32 addr_high;
2001 __le32 addr_low;
56a62fc8
JB		 2002};
2003
2004I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2005
2006/* Alternate structure */
2007
2008/* Direct write (direct 0x0900)
2009 * Direct read (direct 0x0902)
2010 */
2011struct i40e_aqc_alternate_write {
2012 __le32 address0;
2013 __le32 data0;
2014 __le32 address1;
2015 __le32 data1;
2016};
2017
2018I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2019
2020/* Indirect write (indirect 0x0901)
2021 * Indirect read (indirect 0x0903)
2022 */
2023
2024struct i40e_aqc_alternate_ind_write {
2025 __le32 address;
2026 __le32 length;
2027 __le32 addr_high;
2028 __le32 addr_low;
2029};
2030
2031I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2032
2033/* Done alternate write (direct 0x0904)
2034 * uses i40e_aq_desc
2035 */
2036struct i40e_aqc_alternate_write_done {
8c570dcc 2037 __le16 cmd_flags;
56a62fc8
JB		 2038#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2039#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2040#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2041#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
8c570dcc 2042 u8 reserved[14];
56a62fc8
JB		 2043};
2044
2045I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2046
2047/* Set OEM mode (direct 0x0905) */
2048struct i40e_aqc_alternate_set_mode {
8c570dcc 2049 __le32 mode;
56a62fc8
JB		 2050#define I40E_AQ_ALTERNATE_MODE_NONE 0
2051#define I40E_AQ_ALTERNATE_MODE_OEM 1
8c570dcc 2052 u8 reserved[12];
56a62fc8
JB		 2053};
2054
2055I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2056
2057/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2058
2059/* async events 0x10xx */
2060
2061/* Lan Queue Overflow Event (direct, 0x1001) */
2062struct i40e_aqc_lan_overflow {
8c570dcc
JK		 2063 __le32 prtdcb_rupto;
2064 __le32 otx_ctl;
2065 u8 reserved[8];
56a62fc8
JB		 2066};
2067
2068I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2069
2070/* Get LLDP MIB (indirect 0x0A00) */
2071struct i40e_aqc_lldp_get_mib {
8c570dcc
JK		 2072 u8 type;
2073 u8 reserved1;
2074#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2075#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2076#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2077#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2078#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2079#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2080#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2081#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2082#define I40E_AQ_LLDP_TX_SHIFT 0x4
2083#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
56a62fc8 2084/* TX pause flags use I40E_AQ_LINK_TX_* above */
8c570dcc
JK		 2085 __le16 local_len;
2086 __le16 remote_len;
2087 u8 reserved2[2];
2088 __le32 addr_high;
2089 __le32 addr_low;
56a62fc8
JB		 2090};
2091
2092I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2093
2094/* Configure LLDP MIB Change Event (direct 0x0A01)
2095 * also used for the event (with type in the command field)
2096 */
2097struct i40e_aqc_lldp_update_mib {
8c570dcc
JK		 2098 u8 command;
2099#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2100#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2101 u8 reserved[7];
2102 __le32 addr_high;
2103 __le32 addr_low;
56a62fc8
JB		 2104};
2105
2106I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2107
2108/* Add LLDP TLV (indirect 0x0A02)
2109 * Delete LLDP TLV (indirect 0x0A04)
2110 */
2111struct i40e_aqc_lldp_add_tlv {
8c570dcc
JK		 2112 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2113 u8 reserved1[1];
2114 __le16 len;
2115 u8 reserved2[4];
2116 __le32 addr_high;
2117 __le32 addr_low;
56a62fc8
JB		 2118};
2119
2120I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2121
2122/* Update LLDP TLV (indirect 0x0A03) */
2123struct i40e_aqc_lldp_update_tlv {
8c570dcc
JK		 2124 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2125 u8 reserved;
2126 __le16 old_len;
2127 __le16 new_offset;
2128 __le16 new_len;
2129 __le32 addr_high;
2130 __le32 addr_low;
56a62fc8
JB		 2131};
2132
2133I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2134
2135/* Stop LLDP (direct 0x0A05) */
2136struct i40e_aqc_lldp_stop {
8c570dcc
JK		 2137 u8 command;
2138#define I40E_AQ_LLDP_AGENT_STOP 0x0
2139#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2140 u8 reserved[15];
56a62fc8
JB		 2141};
2142
2143I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2144
2145/* Start LLDP (direct 0x0A06) */
2146
2147struct i40e_aqc_lldp_start {
8c570dcc
JK		 2148 u8 command;
2149#define I40E_AQ_LLDP_AGENT_START 0x1
2150 u8 reserved[15];
56a62fc8
JB		 2151};
2152
2153I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2154
9fa61dd2
NP		 2155/* Get CEE DCBX Oper Config (0x0A07)
2156 * uses the generic descriptor struct
2157 * returns below as indirect response
56a62fc8
JB		 2158 */
2159
9fa61dd2
NP		 2160#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2161#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2162#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2163#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2164#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2165#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
725821f3 2166
9fa61dd2
NP		 2167#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2168#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2169#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2170#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2171#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2172#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
cb2f65bc
GR		 2173#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2174#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
725821f3 2175#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
cb2f65bc
GR		 2176#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2177#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2178#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
17351401
SN		 2179
2180/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2181 * word boundary layout issues, which the Linux compilers silently deal
2182 * with by adding padding, making the actual struct larger than designed.
2183 * However, the FW compiler for the NIC is less lenient and complains
2184 * about the struct. Hence, the struct defined here has an extra byte in
2185 * fields reserved3 and reserved4 to directly acknowledge that padding,
2186 * and the new length is used in the length check macro.
2187 */
9fa61dd2
NP		 2188struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2189 u8 reserved1;
2190 u8 oper_num_tc;
2191 u8 oper_prio_tc[4];
2192 u8 reserved2;
2193 u8 oper_tc_bw[8];
2194 u8 oper_pfc_en;
17351401 2195 u8 reserved3[2];
9fa61dd2 2196 __le16 oper_app_prio;
17351401 2197 u8 reserved4[2];
9fa61dd2
NP		 2198 __le16 tlv_status;
2199};
2200
2201I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2202
2203struct i40e_aqc_get_cee_dcb_cfg_resp {
2204 u8 oper_num_tc;
2205 u8 oper_prio_tc[4];
2206 u8 oper_tc_bw[8];
2207 u8 oper_pfc_en;
2208 __le16 oper_app_prio;
672415c5
SN		 2209#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2210#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2211#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2212#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2213#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2214#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2215#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
9fa61dd2 2216 __le32 tlv_status;
672415c5
SN		 2217#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2218#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2219#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2220#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2221#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2222#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
9fa61dd2
NP		 2223 u8 reserved[12];
2224};
2225
2226I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2227
672415c5
SN		 2228/* Set Local LLDP MIB (indirect 0x0A08)
2229 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2230 */
2231struct i40e_aqc_lldp_set_local_mib {
2232#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2101bac2 2233#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
947570e8
GB		 2234#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2235#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2101bac2
JK		 2236#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \
2237 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
947570e8 2238#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
672415c5
SN		 2239 u8 type;
2240 u8 reserved0;
2241 __le16 length;
2242 u8 reserved1[4];
2243 __le32 address_high;
2244 __le32 address_low;
2245};
2246
2247I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2248
2249/* Stop/Start LLDP Agent (direct 0x0A09)
2250 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2251 */
2252struct i40e_aqc_lldp_stop_start_specific_agent {
2253#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2254#define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2101bac2 2255 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
672415c5
SN		 2256 u8 command;
2257 u8 reserved[15];
2258};
2259
2260I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2261
56a62fc8
JB		 2262/* Add Udp Tunnel command and completion (direct 0x0B00) */
2263struct i40e_aqc_add_udp_tunnel {
8c570dcc
JK		 2264 __le16 udp_port;
2265 u8 reserved0[3];
2266 u8 protocol_type;
0aebd2d9
SN		 2267#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2268#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2269#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2fcc1a40 2270#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
8c570dcc 2271 u8 reserved1[10];
56a62fc8
JB		 2272};
2273
2274I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2275
981b7545 2276struct i40e_aqc_add_udp_tunnel_completion {
8c570dcc
JK		 2277 __le16 udp_port;
2278 u8 filter_entry_index;
2279 u8 multiple_pfs;
2280#define I40E_AQC_SINGLE_PF 0x0
2281#define I40E_AQC_MULTIPLE_PFS 0x1
2282 u8 total_filters;
2283 u8 reserved[11];
981b7545
SN		 2284};
2285
2286I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2287
56a62fc8
JB		 2288/* remove UDP Tunnel command (0x0B01) */
2289struct i40e_aqc_remove_udp_tunnel {
8c570dcc
JK		 2290 u8 reserved[2];
2291 u8 index; /* 0 to 15 */
2292 u8 reserved2[13];
56a62fc8
JB		 2293};
2294
2295I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2296
2297struct i40e_aqc_del_udp_tunnel_completion {
8c570dcc
JK		 2298 __le16 udp_port;
2299 u8 index; /* 0 to 15 */
2300 u8 multiple_pfs;
2301 u8 total_filters_used;
2302 u8 reserved1[11];
56a62fc8
JB		 2303};
2304
2305I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2306
e50c8d6d 2307struct i40e_aqc_get_set_rss_key {
2101bac2 2308#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
e50c8d6d
ASJ		 2309#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2310#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2311 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2312 __le16 vsi_id;
2313 u8 reserved[6];
2314 __le32 addr_high;
2315 __le32 addr_low;
2316};
2317
2318I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2319
2320struct i40e_aqc_get_set_rss_key_data {
2321 u8 standard_rss_key[0x28];
2322 u8 extended_hash_key[0xc];
2323};
2324
2325I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2326
2327struct i40e_aqc_get_set_rss_lut {
2101bac2 2328#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
e50c8d6d
ASJ		 2329#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2330#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2331 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2332 __le16 vsi_id;
2333#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2101bac2 2334#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
e50c8d6d
ASJ		 2335
2336#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2337#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2338 __le16 flags;
2339 u8 reserved[4];
2340 __le32 addr_high;
2341 __le32 addr_low;
2342};
2343
2344I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2345
56a62fc8 2346/* tunnel key structure 0x0B10 */
981b7545 2347
56a62fc8 2348struct i40e_aqc_tunnel_key_structure {
981b7545
SN		 2349 u8 key1_off;
2350 u8 key2_off;
2351 u8 key1_len; /* 0 to 15 */
2352 u8 key2_len; /* 0 to 15 */
2353 u8 flags;
8c570dcc 2354#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
56a62fc8 2355/* response flags */
8c570dcc
JK		 2356#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2357#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2358#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
981b7545
SN		 2359 u8 network_key_index;
2360#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2361#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2362#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2363#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2364 u8 reserved[10];
56a62fc8
JB		 2365};
2366
2367I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2368
2369/* OEM mode commands (direct 0xFE0x) */
2370struct i40e_aqc_oem_param_change {
8c570dcc
JK		 2371 __le32 param_type;
2372#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2373#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2374#define I40E_AQ_OEM_PARAM_MAC 2
2375 __le32 param_value1;
35155fe6
SN		 2376 __le16 param_value2;
2377 u8 reserved[6];
56a62fc8
JB		 2378};
2379
2380I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2381
2382struct i40e_aqc_oem_state_change {
8c570dcc
JK		 2383 __le32 state;
2384#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2385#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2386 u8 reserved[12];
56a62fc8
JB		 2387};
2388
2389I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2390
672415c5
SN		 2391/* Initialize OCSD (0xFE02, direct) */
2392struct i40e_aqc_opc_oem_ocsd_initialize {
2393 u8 type_status;
2394 u8 reserved1[3];
2395 __le32 ocsd_memory_block_addr_high;
2396 __le32 ocsd_memory_block_addr_low;
2397 __le32 requested_update_interval;
2398};
2399
2400I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2401
2402/* Initialize OCBB (0xFE03, direct) */
2403struct i40e_aqc_opc_oem_ocbb_initialize {
2404 u8 type_status;
2405 u8 reserved1[3];
2406 __le32 ocbb_memory_block_addr_high;
2407 __le32 ocbb_memory_block_addr_low;
2408 u8 reserved2[4];
2409};
2410
2411I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2412
56a62fc8
JB		 2413/* debug commands */
2414
2415/* get device id (0xFF00) uses the generic structure */
2416
2417/* set test more (0xFF01, internal) */
2418
2419struct i40e_acq_set_test_mode {
8c570dcc
JK		 2420 u8 mode;
2421#define I40E_AQ_TEST_PARTIAL 0
2422#define I40E_AQ_TEST_FULL 1
2423#define I40E_AQ_TEST_NVM 2
2424 u8 reserved[3];
2425 u8 command;
2426#define I40E_AQ_TEST_OPEN 0
2427#define I40E_AQ_TEST_CLOSE 1
2428#define I40E_AQ_TEST_INC 2
2429 u8 reserved2[3];
2430 __le32 address_high;
2431 __le32 address_low;
56a62fc8
JB		 2432};
2433
2434I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2435
2436/* Debug Read Register command (0xFF03)
2437 * Debug Write Register command (0xFF04)
2438 */
2439struct i40e_aqc_debug_reg_read_write {
2440 __le32 reserved;
2441 __le32 address;
2442 __le32 value_high;
2443 __le32 value_low;
2444};
2445
2446I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2447
2448/* Scatter/gather Reg Read (indirect 0xFF05)
2449 * Scatter/gather Reg Write (indirect 0xFF06)
2450 */
2451
2452/* i40e_aq_desc is used for the command */
2453struct i40e_aqc_debug_reg_sg_element_data {
2454 __le32 address;
2455 __le32 value;
2456};
2457
2458/* Debug Modify register (direct 0xFF07) */
2459struct i40e_aqc_debug_modify_reg {
2460 __le32 address;
2461 __le32 value;
2462 __le32 clear_mask;
2463 __le32 set_mask;
2464};
2465
2466I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2467
2468/* dump internal data (0xFF08, indirect) */
2469
2470#define I40E_AQ_CLUSTER_ID_AUX 0
2471#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2472#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2473#define I40E_AQ_CLUSTER_ID_HMC 3
2474#define I40E_AQ_CLUSTER_ID_MAC0 4
2475#define I40E_AQ_CLUSTER_ID_MAC1 5
2476#define I40E_AQ_CLUSTER_ID_MAC2 6
2477#define I40E_AQ_CLUSTER_ID_MAC3 7
2478#define I40E_AQ_CLUSTER_ID_DCB 8
2479#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2480#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
981b7545 2481#define I40E_AQ_CLUSTER_ID_ALTRAM 11
56a62fc8
JB		 2482
2483struct i40e_aqc_debug_dump_internals {
8c570dcc
JK		 2484 u8 cluster_id;
2485 u8 table_id;
2486 __le16 data_size;
2487 __le32 idx;
2488 __le32 address_high;
2489 __le32 address_low;
56a62fc8
JB		 2490};
2491
2492I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2493
2494struct i40e_aqc_debug_modify_internals {
8c570dcc
JK		 2495 u8 cluster_id;
2496 u8 cluster_specific_params[7];
2497 __le32 address_high;
2498 __le32 address_low;
56a62fc8
JB		 2499};
2500
2501I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2502
2f175f55 2503#endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
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