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i40evf: Fix function header
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
e454d6bf 41#define DRV_VERSION_MINOR 4
eeb6b645 42#define DRV_VERSION_BUILD 5
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 307 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 308 i40e_down(vsi);
309 break;
310 }
311 i40e_service_event_schedule(pf);
312 pf->tx_timeout_recovery_level++;
313}
314
315/**
316 * i40e_release_rx_desc - Store the new tail and head values
317 * @rx_ring: ring to bump
318 * @val: new head index
319 **/
320static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
321{
322 rx_ring->next_to_use = val;
323
324 /* Force memory writes to complete before letting h/w
325 * know there are new descriptors to fetch. (Only
326 * applicable for weak-ordered memory model archs,
327 * such as IA-64).
328 */
329 wmb();
330 writel(val, rx_ring->tail);
331}
332
333/**
334 * i40e_get_vsi_stats_struct - Get System Network Statistics
335 * @vsi: the VSI we care about
336 *
337 * Returns the address of the device statistics structure.
338 * The statistics are actually updated from the service task.
339 **/
340struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
341{
342 return &vsi->net_stats;
343}
344
345/**
346 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
347 * @netdev: network interface device structure
348 *
349 * Returns the address of the device statistics structure.
350 * The statistics are actually updated from the service task.
351 **/
352static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
353 struct net_device *netdev,
980e9b11 354 struct rtnl_link_stats64 *stats)
41c445ff
JB		 355{
356 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 357 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
57a7744e 378 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
57a7744e 381 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
a5282f44 398 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 426 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 436 }
8e9dca53 437 }
41c445ff
JB		 438 vsi->stat_offsets_loaded = false;
439}
440
441/**
442 * i40e_pf_reset_stats - Reset all of the stats for the given pf
443 * @pf: the PF to be reset
444 **/
445void i40e_pf_reset_stats(struct i40e_pf *pf)
446{
447 memset(&pf->stats, 0, sizeof(pf->stats));
448 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
449 pf->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_stat_update48 - read and update a 48 bit stat from the chip
454 * @hw: ptr to the hardware info
455 * @hireg: the high 32 bit reg to read
456 * @loreg: the low 32 bit reg to read
457 * @offset_loaded: has the initial offset been loaded yet
458 * @offset: ptr to current offset value
459 * @stat: ptr to the stat
460 *
461 * Since the device stats are not reset at PFReset, they likely will not
462 * be zeroed when the driver starts. We'll save the first values read
463 * and use them as offsets to be subtracted from the raw values in order
464 * to report stats that count from zero. In the process, we also manage
465 * the potential roll-over.
466 **/
467static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
468 bool offset_loaded, u64 *offset, u64 *stat)
469{
470 u64 new_data;
471
ab60085e 472 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 473 new_data = rd32(hw, loreg);
474 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
475 } else {
476 new_data = rd64(hw, loreg);
477 }
478 if (!offset_loaded)
479 *offset = new_data;
480 if (likely(new_data >= *offset))
481 *stat = new_data - *offset;
482 else
483 *stat = (new_data + ((u64)1 << 48)) - *offset;
484 *stat &= 0xFFFFFFFFFFFFULL;
485}
486
487/**
488 * i40e_stat_update32 - read and update a 32 bit stat from the chip
489 * @hw: ptr to the hardware info
490 * @reg: the hw reg to read
491 * @offset_loaded: has the initial offset been loaded yet
492 * @offset: ptr to current offset value
493 * @stat: ptr to the stat
494 **/
495static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
496 bool offset_loaded, u64 *offset, u64 *stat)
497{
498 u32 new_data;
499
500 new_data = rd32(hw, reg);
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = (u32)(new_data - *offset);
505 else
506 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
507}
508
509/**
510 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
511 * @vsi: the VSI to be updated
512 **/
513void i40e_update_eth_stats(struct i40e_vsi *vsi)
514{
515 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
516 struct i40e_pf *pf = vsi->back;
517 struct i40e_hw *hw = &pf->hw;
518 struct i40e_eth_stats *oes;
519 struct i40e_eth_stats *es; /* device's eth stats */
520
521 es = &vsi->eth_stats;
522 oes = &vsi->eth_stats_offsets;
523
524 /* Gather up the stats that the hw collects */
525 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
526 vsi->stat_offsets_loaded,
527 &oes->tx_errors, &es->tx_errors);
528 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
529 vsi->stat_offsets_loaded,
530 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 531 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
532 vsi->stat_offsets_loaded,
533 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
534 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 537
538 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
539 I40E_GLV_GORCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_bytes, &es->rx_bytes);
542 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
543 I40E_GLV_UPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_unicast, &es->rx_unicast);
546 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
547 I40E_GLV_MPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_multicast, &es->rx_multicast);
550 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
551 I40E_GLV_BPRCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_broadcast, &es->rx_broadcast);
554
555 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
556 I40E_GLV_GOTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_bytes, &es->tx_bytes);
559 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
560 I40E_GLV_UPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_unicast, &es->tx_unicast);
563 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
564 I40E_GLV_MPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_multicast, &es->tx_multicast);
567 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
568 I40E_GLV_BPTCL(stat_idx),
569 vsi->stat_offsets_loaded,
570 &oes->tx_broadcast, &es->tx_broadcast);
571 vsi->stat_offsets_loaded = true;
572}
573
574/**
575 * i40e_update_veb_stats - Update Switch component statistics
576 * @veb: the VEB being updated
577 **/
578static void i40e_update_veb_stats(struct i40e_veb *veb)
579{
580 struct i40e_pf *pf = veb->pf;
581 struct i40e_hw *hw = &pf->hw;
582 struct i40e_eth_stats *oes;
583 struct i40e_eth_stats *es; /* device's eth stats */
584 int idx = 0;
585
586 idx = veb->stats_idx;
587 es = &veb->stats;
588 oes = &veb->stats_offsets;
589
590 /* Gather up the stats that the hw collects */
591 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
592 veb->stat_offsets_loaded,
593 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 594 if (hw->revision_id > 0)
595 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unknown_protocol,
598 &es->rx_unknown_protocol);
41c445ff
JB		 599 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
600 veb->stat_offsets_loaded,
601 &oes->rx_bytes, &es->rx_bytes);
602 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
603 veb->stat_offsets_loaded,
604 &oes->rx_unicast, &es->rx_unicast);
605 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->rx_multicast, &es->rx_multicast);
608 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->rx_broadcast, &es->rx_broadcast);
611
612 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
613 veb->stat_offsets_loaded,
614 &oes->tx_bytes, &es->tx_bytes);
615 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
616 veb->stat_offsets_loaded,
617 &oes->tx_unicast, &es->tx_unicast);
618 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
619 veb->stat_offsets_loaded,
620 &oes->tx_multicast, &es->tx_multicast);
621 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
622 veb->stat_offsets_loaded,
623 &oes->tx_broadcast, &es->tx_broadcast);
624 veb->stat_offsets_loaded = true;
625}
626
627/**
628 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
629 * @pf: the corresponding PF
630 *
631 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
632 **/
633static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
634{
635 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
636 struct i40e_hw_port_stats *nsd = &pf->stats;
637 struct i40e_hw *hw = &pf->hw;
638 u64 xoff = 0;
639 u16 i, v;
640
641 if ((hw->fc.current_mode != I40E_FC_FULL) &&
642 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
643 return;
644
645 xoff = nsd->link_xoff_rx;
646 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
647 pf->stat_offsets_loaded,
648 &osd->link_xoff_rx, &nsd->link_xoff_rx);
649
650 /* No new LFC xoff rx */
651 if (!(nsd->link_xoff_rx - xoff))
652 return;
653
654 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
655 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
656 struct i40e_vsi *vsi = pf->vsi[v];
657
ddfda80f 658 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 659 continue;
660
661 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 662 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 663 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
664 }
665 }
666}
667
668/**
669 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
670 * @pf: the corresponding PF
671 *
672 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
673 **/
674static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
675{
676 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
677 struct i40e_hw_port_stats *nsd = &pf->stats;
678 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
679 struct i40e_dcbx_config *dcb_cfg;
680 struct i40e_hw *hw = &pf->hw;
681 u16 i, v;
682 u8 tc;
683
684 dcb_cfg = &hw->local_dcbx_config;
685
686 /* See if DCB enabled with PFC TC */
687 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
688 !(dcb_cfg->pfc.pfcenable)) {
689 i40e_update_link_xoff_rx(pf);
690 return;
691 }
692
693 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
694 u64 prio_xoff = nsd->priority_xoff_rx[i];
695 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
696 pf->stat_offsets_loaded,
697 &osd->priority_xoff_rx[i],
698 &nsd->priority_xoff_rx[i]);
699
700 /* No new PFC xoff rx */
701 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
702 continue;
703 /* Get the TC for given priority */
704 tc = dcb_cfg->etscfg.prioritytable[i];
705 xoff[tc] = true;
706 }
707
708 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
709 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
710 struct i40e_vsi *vsi = pf->vsi[v];
711
ddfda80f 712 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 713 continue;
714
715 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 716 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 717
718 tc = ring->dcb_tc;
719 if (xoff[tc])
720 clear_bit(__I40E_HANG_CHECK_ARMED,
721 &ring->state);
722 }
723 }
724}
725
726/**
7812fddc 727 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 728 * @vsi: the VSI to be updated
729 *
730 * There are a few instances where we store the same stat in a
731 * couple of different structs. This is partly because we have
732 * the netdev stats that need to be filled out, which is slightly
733 * different from the "eth_stats" defined by the chip and used in
7812fddc 734 * VF communications. We sort it out here.
41c445ff 735 **/
7812fddc 736static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 737{
738 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 739 struct rtnl_link_stats64 *ons;
740 struct rtnl_link_stats64 *ns; /* netdev stats */
741 struct i40e_eth_stats *oes;
742 struct i40e_eth_stats *es; /* device's eth stats */
743 u32 tx_restart, tx_busy;
744 u32 rx_page, rx_buf;
745 u64 rx_p, rx_b;
746 u64 tx_p, tx_b;
41c445ff
JB		 747 u16 q;
748
749 if (test_bit(__I40E_DOWN, &vsi->state) ||
750 test_bit(__I40E_CONFIG_BUSY, &pf->state))
751 return;
752
753 ns = i40e_get_vsi_stats_struct(vsi);
754 ons = &vsi->net_stats_offsets;
755 es = &vsi->eth_stats;
756 oes = &vsi->eth_stats_offsets;
757
758 /* Gather up the netdev and vsi stats that the driver collects
759 * on the fly during packet processing
760 */
761 rx_b = rx_p = 0;
762 tx_b = tx_p = 0;
763 tx_restart = tx_busy = 0;
764 rx_page = 0;
765 rx_buf = 0;
980e9b11 766 rcu_read_lock();
41c445ff
JB		 767 for (q = 0; q < vsi->num_queue_pairs; q++) {
768 struct i40e_ring *p;
980e9b11
AD		 769 u64 bytes, packets;
770 unsigned int start;
771
772 /* locate Tx ring */
773 p = ACCESS_ONCE(vsi->tx_rings[q]);
774
775 do {
57a7744e 776 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 777 packets = p->stats.packets;
778 bytes = p->stats.bytes;
57a7744e 779 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 780 tx_b += bytes;
781 tx_p += packets;
782 tx_restart += p->tx_stats.restart_queue;
783 tx_busy += p->tx_stats.tx_busy;
41c445ff 784
980e9b11
AD		 785 /* Rx queue is part of the same block as Tx queue */
786 p = &p[1];
787 do {
57a7744e 788 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 789 packets = p->stats.packets;
790 bytes = p->stats.bytes;
57a7744e 791 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 792 rx_b += bytes;
793 rx_p += packets;
420136cc
MW		 794 rx_buf += p->rx_stats.alloc_buff_failed;
795 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 796 }
980e9b11 797 rcu_read_unlock();
41c445ff
JB		 798 vsi->tx_restart = tx_restart;
799 vsi->tx_busy = tx_busy;
800 vsi->rx_page_failed = rx_page;
801 vsi->rx_buf_failed = rx_buf;
802
803 ns->rx_packets = rx_p;
804 ns->rx_bytes = rx_b;
805 ns->tx_packets = tx_p;
806 ns->tx_bytes = tx_b;
807
41c445ff 808 /* update netdev stats from eth stats */
7812fddc 809 i40e_update_eth_stats(vsi);
41c445ff
JB		 810 ons->tx_errors = oes->tx_errors;
811 ns->tx_errors = es->tx_errors;
812 ons->multicast = oes->rx_multicast;
813 ns->multicast = es->rx_multicast;
41a9e55c
SN		 814 ons->rx_dropped = oes->rx_discards;
815 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 816 ons->tx_dropped = oes->tx_discards;
817 ns->tx_dropped = es->tx_discards;
818
7812fddc 819 /* pull in a couple PF stats if this is the main vsi */
41c445ff 820 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 821 ns->rx_crc_errors = pf->stats.crc_errors;
822 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
823 ns->rx_length_errors = pf->stats.rx_length_errors;
824 }
825}
41c445ff 826
7812fddc
SN		 827/**
828 * i40e_update_pf_stats - Update the pf statistics counters.
829 * @pf: the PF to be updated
830 **/
831static void i40e_update_pf_stats(struct i40e_pf *pf)
832{
833 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
834 struct i40e_hw_port_stats *nsd = &pf->stats;
835 struct i40e_hw *hw = &pf->hw;
836 u32 val;
837 int i;
41c445ff 838
7812fddc
SN		 839 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
840 I40E_GLPRT_GORCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
843 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
844 I40E_GLPRT_GOTCL(hw->port),
845 pf->stat_offsets_loaded,
846 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
847 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
848 pf->stat_offsets_loaded,
849 &osd->eth.rx_discards,
850 &nsd->eth.rx_discards);
851 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->eth.tx_discards,
854 &nsd->eth.tx_discards);
532d283d
SN		 855
856 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
857 I40E_GLPRT_UPRCL(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->eth.rx_unicast,
860 &nsd->eth.rx_unicast);
7812fddc
SN		 861 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
862 I40E_GLPRT_MPRCL(hw->port),
863 pf->stat_offsets_loaded,
864 &osd->eth.rx_multicast,
865 &nsd->eth.rx_multicast);
532d283d
SN		 866 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
867 I40E_GLPRT_BPRCL(hw->port),
868 pf->stat_offsets_loaded,
869 &osd->eth.rx_broadcast,
870 &nsd->eth.rx_broadcast);
871 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
872 I40E_GLPRT_UPTCL(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->eth.tx_unicast,
875 &nsd->eth.tx_unicast);
876 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
877 I40E_GLPRT_MPTCL(hw->port),
878 pf->stat_offsets_loaded,
879 &osd->eth.tx_multicast,
880 &nsd->eth.tx_multicast);
881 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
882 I40E_GLPRT_BPTCL(hw->port),
883 pf->stat_offsets_loaded,
884 &osd->eth.tx_broadcast,
885 &nsd->eth.tx_broadcast);
41c445ff 886
7812fddc
SN		 887 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
888 pf->stat_offsets_loaded,
889 &osd->tx_dropped_link_down,
890 &nsd->tx_dropped_link_down);
41c445ff 891
7812fddc
SN		 892 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
893 pf->stat_offsets_loaded,
894 &osd->crc_errors, &nsd->crc_errors);
41c445ff 895
7812fddc
SN		 896 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
897 pf->stat_offsets_loaded,
898 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 899
7812fddc
SN		 900 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
901 pf->stat_offsets_loaded,
902 &osd->mac_local_faults,
903 &nsd->mac_local_faults);
904 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->mac_remote_faults,
907 &nsd->mac_remote_faults);
41c445ff 908
7812fddc
SN		 909 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
910 pf->stat_offsets_loaded,
911 &osd->rx_length_errors,
912 &nsd->rx_length_errors);
41c445ff 913
7812fddc
SN		 914 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
915 pf->stat_offsets_loaded,
916 &osd->link_xon_rx, &nsd->link_xon_rx);
917 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->link_xon_tx, &nsd->link_xon_tx);
920 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
921 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
922 pf->stat_offsets_loaded,
923 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 924
7812fddc
SN		 925 for (i = 0; i < 8; i++) {
926 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 927 pf->stat_offsets_loaded,
7812fddc
SN		 928 &osd->priority_xon_rx[i],
929 &nsd->priority_xon_rx[i]);
930 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 931 pf->stat_offsets_loaded,
7812fddc
SN		 932 &osd->priority_xon_tx[i],
933 &nsd->priority_xon_tx[i]);
934 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 935 pf->stat_offsets_loaded,
7812fddc
SN		 936 &osd->priority_xoff_tx[i],
937 &nsd->priority_xoff_tx[i]);
938 i40e_stat_update32(hw,
939 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
41c445ff 940 pf->stat_offsets_loaded,
7812fddc
SN		 941 &osd->priority_xon_2_xoff[i],
942 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 943 }
944
7812fddc
SN		 945 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
946 I40E_GLPRT_PRC64L(hw->port),
947 pf->stat_offsets_loaded,
948 &osd->rx_size_64, &nsd->rx_size_64);
949 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
950 I40E_GLPRT_PRC127L(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->rx_size_127, &nsd->rx_size_127);
953 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
954 I40E_GLPRT_PRC255L(hw->port),
955 pf->stat_offsets_loaded,
956 &osd->rx_size_255, &nsd->rx_size_255);
957 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
958 I40E_GLPRT_PRC511L(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->rx_size_511, &nsd->rx_size_511);
961 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
962 I40E_GLPRT_PRC1023L(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->rx_size_1023, &nsd->rx_size_1023);
965 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
966 I40E_GLPRT_PRC1522L(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_size_1522, &nsd->rx_size_1522);
969 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
970 I40E_GLPRT_PRC9522L(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_size_big, &nsd->rx_size_big);
973
974 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
975 I40E_GLPRT_PTC64L(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->tx_size_64, &nsd->tx_size_64);
978 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
979 I40E_GLPRT_PTC127L(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->tx_size_127, &nsd->tx_size_127);
982 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
983 I40E_GLPRT_PTC255L(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->tx_size_255, &nsd->tx_size_255);
986 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
987 I40E_GLPRT_PTC511L(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->tx_size_511, &nsd->tx_size_511);
990 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
991 I40E_GLPRT_PTC1023L(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->tx_size_1023, &nsd->tx_size_1023);
994 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
995 I40E_GLPRT_PTC1522L(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->tx_size_1522, &nsd->tx_size_1522);
998 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
999 I40E_GLPRT_PTC9522L(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->tx_size_big, &nsd->tx_size_big);
1002
1003 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->rx_undersize, &nsd->rx_undersize);
1006 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->rx_fragments, &nsd->rx_fragments);
1009 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->rx_oversize, &nsd->rx_oversize);
1012 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_jabber, &nsd->rx_jabber);
1015
1016 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1017 nsd->tx_lpi_status =
1018 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1019 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1020 nsd->rx_lpi_status =
1021 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1022 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1023 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1024 pf->stat_offsets_loaded,
1025 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1026 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1027 pf->stat_offsets_loaded,
1028 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1029
41c445ff
JB		 1030 pf->stat_offsets_loaded = true;
1031}
1032
7812fddc
SN		 1033/**
1034 * i40e_update_stats - Update the various statistics counters.
1035 * @vsi: the VSI to be updated
1036 *
1037 * Update the various stats for this VSI and its related entities.
1038 **/
1039void i40e_update_stats(struct i40e_vsi *vsi)
1040{
1041 struct i40e_pf *pf = vsi->back;
1042
1043 if (vsi == pf->vsi[pf->lan_vsi])
1044 i40e_update_pf_stats(pf);
1045
1046 i40e_update_vsi_stats(vsi);
1047}
1048
41c445ff
JB		 1049/**
1050 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1051 * @vsi: the VSI to be searched
1052 * @macaddr: the MAC address
1053 * @vlan: the vlan
1054 * @is_vf: make sure its a vf filter, else doesn't matter
1055 * @is_netdev: make sure its a netdev filter, else doesn't matter
1056 *
1057 * Returns ptr to the filter object or NULL
1058 **/
1059static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1060 u8 *macaddr, s16 vlan,
1061 bool is_vf, bool is_netdev)
1062{
1063 struct i40e_mac_filter *f;
1064
1065 if (!vsi || !macaddr)
1066 return NULL;
1067
1068 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1069 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1070 (vlan == f->vlan) &&
1071 (!is_vf || f->is_vf) &&
1072 (!is_netdev || f->is_netdev))
1073 return f;
1074 }
1075 return NULL;
1076}
1077
1078/**
1079 * i40e_find_mac - Find a mac addr in the macvlan filters list
1080 * @vsi: the VSI to be searched
1081 * @macaddr: the MAC address we are searching for
1082 * @is_vf: make sure its a vf filter, else doesn't matter
1083 * @is_netdev: make sure its a netdev filter, else doesn't matter
1084 *
1085 * Returns the first filter with the provided MAC address or NULL if
1086 * MAC address was not found
1087 **/
1088struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1089 bool is_vf, bool is_netdev)
1090{
1091 struct i40e_mac_filter *f;
1092
1093 if (!vsi || !macaddr)
1094 return NULL;
1095
1096 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1097 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1098 (!is_vf || f->is_vf) &&
1099 (!is_netdev || f->is_netdev))
1100 return f;
1101 }
1102 return NULL;
1103}
1104
1105/**
1106 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1107 * @vsi: the VSI to be searched
1108 *
1109 * Returns true if VSI is in vlan mode or false otherwise
1110 **/
1111bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1112{
1113 struct i40e_mac_filter *f;
1114
1115 /* Only -1 for all the filters denotes not in vlan mode
1116 * so we have to go through all the list in order to make sure
1117 */
1118 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1119 if (f->vlan >= 0)
1120 return true;
1121 }
1122
1123 return false;
1124}
1125
1126/**
1127 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1128 * @vsi: the VSI to be searched
1129 * @macaddr: the mac address to be filtered
1130 * @is_vf: true if it is a vf
1131 * @is_netdev: true if it is a netdev
1132 *
1133 * Goes through all the macvlan filters and adds a
1134 * macvlan filter for each unique vlan that already exists
1135 *
1136 * Returns first filter found on success, else NULL
1137 **/
1138struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1139 bool is_vf, bool is_netdev)
1140{
1141 struct i40e_mac_filter *f;
1142
1143 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1144 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1145 is_vf, is_netdev)) {
1146 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1147 is_vf, is_netdev))
41c445ff
JB		 1148 return NULL;
1149 }
1150 }
1151
1152 return list_first_entry_or_null(&vsi->mac_filter_list,
1153 struct i40e_mac_filter, list);
1154}
1155
1156/**
1157 * i40e_add_filter - Add a mac/vlan filter to the VSI
1158 * @vsi: the VSI to be searched
1159 * @macaddr: the MAC address
1160 * @vlan: the vlan
1161 * @is_vf: make sure its a vf filter, else doesn't matter
1162 * @is_netdev: make sure its a netdev filter, else doesn't matter
1163 *
1164 * Returns ptr to the filter object or NULL when no memory available.
1165 **/
1166struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1167 u8 *macaddr, s16 vlan,
1168 bool is_vf, bool is_netdev)
1169{
1170 struct i40e_mac_filter *f;
1171
1172 if (!vsi || !macaddr)
1173 return NULL;
1174
1175 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1176 if (!f) {
1177 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1178 if (!f)
1179 goto add_filter_out;
1180
1181 memcpy(f->macaddr, macaddr, ETH_ALEN);
1182 f->vlan = vlan;
1183 f->changed = true;
1184
1185 INIT_LIST_HEAD(&f->list);
1186 list_add(&f->list, &vsi->mac_filter_list);
1187 }
1188
1189 /* increment counter and add a new flag if needed */
1190 if (is_vf) {
1191 if (!f->is_vf) {
1192 f->is_vf = true;
1193 f->counter++;
1194 }
1195 } else if (is_netdev) {
1196 if (!f->is_netdev) {
1197 f->is_netdev = true;
1198 f->counter++;
1199 }
1200 } else {
1201 f->counter++;
1202 }
1203
1204 /* changed tells sync_filters_subtask to
1205 * push the filter down to the firmware
1206 */
1207 if (f->changed) {
1208 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1209 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1210 }
1211
1212add_filter_out:
1213 return f;
1214}
1215
1216/**
1217 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1218 * @vsi: the VSI to be searched
1219 * @macaddr: the MAC address
1220 * @vlan: the vlan
1221 * @is_vf: make sure it's a vf filter, else doesn't matter
1222 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1223 **/
1224void i40e_del_filter(struct i40e_vsi *vsi,
1225 u8 *macaddr, s16 vlan,
1226 bool is_vf, bool is_netdev)
1227{
1228 struct i40e_mac_filter *f;
1229
1230 if (!vsi || !macaddr)
1231 return;
1232
1233 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1234 if (!f || f->counter == 0)
1235 return;
1236
1237 if (is_vf) {
1238 if (f->is_vf) {
1239 f->is_vf = false;
1240 f->counter--;
1241 }
1242 } else if (is_netdev) {
1243 if (f->is_netdev) {
1244 f->is_netdev = false;
1245 f->counter--;
1246 }
1247 } else {
1248 /* make sure we don't remove a filter in use by vf or netdev */
1249 int min_f = 0;
1250 min_f += (f->is_vf ? 1 : 0);
1251 min_f += (f->is_netdev ? 1 : 0);
1252
1253 if (f->counter > min_f)
1254 f->counter--;
1255 }
1256
1257 /* counter == 0 tells sync_filters_subtask to
1258 * remove the filter from the firmware's list
1259 */
1260 if (f->counter == 0) {
1261 f->changed = true;
1262 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1263 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1264 }
1265}
1266
1267/**
1268 * i40e_set_mac - NDO callback to set mac address
1269 * @netdev: network interface device structure
1270 * @p: pointer to an address structure
1271 *
1272 * Returns 0 on success, negative on failure
1273 **/
1274static int i40e_set_mac(struct net_device *netdev, void *p)
1275{
1276 struct i40e_netdev_priv *np = netdev_priv(netdev);
1277 struct i40e_vsi *vsi = np->vsi;
1278 struct sockaddr *addr = p;
1279 struct i40e_mac_filter *f;
1280
1281 if (!is_valid_ether_addr(addr->sa_data))
1282 return -EADDRNOTAVAIL;
1283
1284 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1285
1286 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1287 return 0;
1288
80f6428f
ASJ		 1289 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1290 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1291 return -EADDRNOTAVAIL;
1292
41c445ff
JB		 1293 if (vsi->type == I40E_VSI_MAIN) {
1294 i40e_status ret;
1295 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1296 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1297 addr->sa_data, NULL);
1298 if (ret) {
1299 netdev_info(netdev,
1300 "Addr change for Main VSI failed: %d\n",
1301 ret);
1302 return -EADDRNOTAVAIL;
1303 }
1304
1305 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1306 }
1307
1308 /* In order to be sure to not drop any packets, add the new address
1309 * then delete the old one.
1310 */
1311 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1312 if (!f)
1313 return -ENOMEM;
1314
1315 i40e_sync_vsi_filters(vsi);
1316 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1317 i40e_sync_vsi_filters(vsi);
1318
1319 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1320
1321 return 0;
1322}
1323
1324/**
1325 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1326 * @vsi: the VSI being setup
1327 * @ctxt: VSI context structure
1328 * @enabled_tc: Enabled TCs bitmap
1329 * @is_add: True if called before Add VSI
1330 *
1331 * Setup VSI queue mapping for enabled traffic classes.
1332 **/
1333static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1334 struct i40e_vsi_context *ctxt,
1335 u8 enabled_tc,
1336 bool is_add)
1337{
1338 struct i40e_pf *pf = vsi->back;
1339 u16 sections = 0;
1340 u8 netdev_tc = 0;
1341 u16 numtc = 0;
1342 u16 qcount;
1343 u8 offset;
1344 u16 qmap;
1345 int i;
4e3b35b0 1346 u16 num_tc_qps = 0;
41c445ff
JB		 1347
1348 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1349 offset = 0;
1350
1351 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1352 /* Find numtc from enabled TC bitmap */
1353 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1354 if (enabled_tc & (1 << i)) /* TC is enabled */
1355 numtc++;
1356 }
1357 if (!numtc) {
1358 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1359 numtc = 1;
1360 }
1361 } else {
1362 /* At least TC0 is enabled in case of non-DCB case */
1363 numtc = 1;
1364 }
1365
1366 vsi->tc_config.numtc = numtc;
1367 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1368 /* Number of queues per enabled TC */
1369 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1370 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1371
1372 /* Setup queue offset/count for all TCs for given VSI */
1373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1374 /* See if the given TC is enabled for the given VSI */
1375 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1376 int pow, num_qps;
1377
41c445ff
JB		 1378 switch (vsi->type) {
1379 case I40E_VSI_MAIN:
4e3b35b0 1380 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1381 break;
1382 case I40E_VSI_FDIR:
1383 case I40E_VSI_SRIOV:
1384 case I40E_VSI_VMDQ2:
1385 default:
4e3b35b0 1386 qcount = num_tc_qps;
41c445ff
JB		 1387 WARN_ON(i != 0);
1388 break;
1389 }
4e3b35b0
NP		 1390 vsi->tc_config.tc_info[i].qoffset = offset;
1391 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1392
1393 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1394 num_qps = qcount;
41c445ff 1395 pow = 0;
4e3b35b0 1396 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1397 pow++;
1398 num_qps >>= 1;
1399 }
1400
1401 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1402 qmap =
1403 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1404 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1405
4e3b35b0 1406 offset += qcount;
41c445ff
JB		 1407 } else {
1408 /* TC is not enabled so set the offset to
1409 * default queue and allocate one queue
1410 * for the given TC.
1411 */
1412 vsi->tc_config.tc_info[i].qoffset = 0;
1413 vsi->tc_config.tc_info[i].qcount = 1;
1414 vsi->tc_config.tc_info[i].netdev_tc = 0;
1415
1416 qmap = 0;
1417 }
1418 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1419 }
1420
1421 /* Set actual Tx/Rx queue pairs */
1422 vsi->num_queue_pairs = offset;
1423
1424 /* Scheduler section valid can only be set for ADD VSI */
1425 if (is_add) {
1426 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1427
1428 ctxt->info.up_enable_bits = enabled_tc;
1429 }
1430 if (vsi->type == I40E_VSI_SRIOV) {
1431 ctxt->info.mapping_flags |=
1432 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1433 for (i = 0; i < vsi->num_queue_pairs; i++)
1434 ctxt->info.queue_mapping[i] =
1435 cpu_to_le16(vsi->base_queue + i);
1436 } else {
1437 ctxt->info.mapping_flags |=
1438 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1439 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1440 }
1441 ctxt->info.valid_sections |= cpu_to_le16(sections);
1442}
1443
1444/**
1445 * i40e_set_rx_mode - NDO callback to set the netdev filters
1446 * @netdev: network interface device structure
1447 **/
1448static void i40e_set_rx_mode(struct net_device *netdev)
1449{
1450 struct i40e_netdev_priv *np = netdev_priv(netdev);
1451 struct i40e_mac_filter *f, *ftmp;
1452 struct i40e_vsi *vsi = np->vsi;
1453 struct netdev_hw_addr *uca;
1454 struct netdev_hw_addr *mca;
1455 struct netdev_hw_addr *ha;
1456
1457 /* add addr if not already in the filter list */
1458 netdev_for_each_uc_addr(uca, netdev) {
1459 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1460 if (i40e_is_vsi_in_vlan(vsi))
1461 i40e_put_mac_in_vlan(vsi, uca->addr,
1462 false, true);
1463 else
1464 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1465 false, true);
1466 }
1467 }
1468
1469 netdev_for_each_mc_addr(mca, netdev) {
1470 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1471 if (i40e_is_vsi_in_vlan(vsi))
1472 i40e_put_mac_in_vlan(vsi, mca->addr,
1473 false, true);
1474 else
1475 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1476 false, true);
1477 }
1478 }
1479
1480 /* remove filter if not in netdev list */
1481 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1482 bool found = false;
1483
1484 if (!f->is_netdev)
1485 continue;
1486
1487 if (is_multicast_ether_addr(f->macaddr)) {
1488 netdev_for_each_mc_addr(mca, netdev) {
1489 if (ether_addr_equal(mca->addr, f->macaddr)) {
1490 found = true;
1491 break;
1492 }
1493 }
1494 } else {
1495 netdev_for_each_uc_addr(uca, netdev) {
1496 if (ether_addr_equal(uca->addr, f->macaddr)) {
1497 found = true;
1498 break;
1499 }
1500 }
1501
1502 for_each_dev_addr(netdev, ha) {
1503 if (ether_addr_equal(ha->addr, f->macaddr)) {
1504 found = true;
1505 break;
1506 }
1507 }
1508 }
1509 if (!found)
1510 i40e_del_filter(
1511 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1512 }
1513
1514 /* check for other flag changes */
1515 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1516 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1517 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1518 }
1519}
1520
1521/**
1522 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1523 * @vsi: ptr to the VSI
1524 *
1525 * Push any outstanding VSI filter changes through the AdminQ.
1526 *
1527 * Returns 0 or error value
1528 **/
1529int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1530{
1531 struct i40e_mac_filter *f, *ftmp;
1532 bool promisc_forced_on = false;
1533 bool add_happened = false;
1534 int filter_list_len = 0;
1535 u32 changed_flags = 0;
dcae29be 1536 i40e_status aq_ret = 0;
41c445ff
JB		 1537 struct i40e_pf *pf;
1538 int num_add = 0;
1539 int num_del = 0;
1540 u16 cmd_flags;
1541
1542 /* empty array typed pointers, kcalloc later */
1543 struct i40e_aqc_add_macvlan_element_data *add_list;
1544 struct i40e_aqc_remove_macvlan_element_data *del_list;
1545
1546 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1547 usleep_range(1000, 2000);
1548 pf = vsi->back;
1549
1550 if (vsi->netdev) {
1551 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1552 vsi->current_netdev_flags = vsi->netdev->flags;
1553 }
1554
1555 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1556 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1557
1558 filter_list_len = pf->hw.aq.asq_buf_size /
1559 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1560 del_list = kcalloc(filter_list_len,
1561 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1562 GFP_KERNEL);
1563 if (!del_list)
1564 return -ENOMEM;
1565
1566 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1567 if (!f->changed)
1568 continue;
1569
1570 if (f->counter != 0)
1571 continue;
1572 f->changed = false;
1573 cmd_flags = 0;
1574
1575 /* add to delete list */
1576 memcpy(del_list[num_del].mac_addr,
1577 f->macaddr, ETH_ALEN);
1578 del_list[num_del].vlan_tag =
1579 cpu_to_le16((u16)(f->vlan ==
1580 I40E_VLAN_ANY ? 0 : f->vlan));
1581
41c445ff
JB		 1582 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1583 del_list[num_del].flags = cmd_flags;
1584 num_del++;
1585
1586 /* unlink from filter list */
1587 list_del(&f->list);
1588 kfree(f);
1589
1590 /* flush a full buffer */
1591 if (num_del == filter_list_len) {
dcae29be 1592 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1593 vsi->seid, del_list, num_del,
1594 NULL);
1595 num_del = 0;
1596 memset(del_list, 0, sizeof(*del_list));
1597
dcae29be 1598 if (aq_ret)
41c445ff
JB		 1599 dev_info(&pf->pdev->dev,
1600 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1601 aq_ret,
41c445ff
JB		 1602 pf->hw.aq.asq_last_status);
1603 }
1604 }
1605 if (num_del) {
dcae29be 1606 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1607 del_list, num_del, NULL);
1608 num_del = 0;
1609
dcae29be 1610 if (aq_ret)
41c445ff
JB		 1611 dev_info(&pf->pdev->dev,
1612 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1613 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1614 }
1615
1616 kfree(del_list);
1617 del_list = NULL;
1618
1619 /* do all the adds now */
1620 filter_list_len = pf->hw.aq.asq_buf_size /
1621 sizeof(struct i40e_aqc_add_macvlan_element_data),
1622 add_list = kcalloc(filter_list_len,
1623 sizeof(struct i40e_aqc_add_macvlan_element_data),
1624 GFP_KERNEL);
1625 if (!add_list)
1626 return -ENOMEM;
1627
1628 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1629 if (!f->changed)
1630 continue;
1631
1632 if (f->counter == 0)
1633 continue;
1634 f->changed = false;
1635 add_happened = true;
1636 cmd_flags = 0;
1637
1638 /* add to add array */
1639 memcpy(add_list[num_add].mac_addr,
1640 f->macaddr, ETH_ALEN);
1641 add_list[num_add].vlan_tag =
1642 cpu_to_le16(
1643 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1644 add_list[num_add].queue_number = 0;
1645
1646 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1647 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1648 num_add++;
1649
1650 /* flush a full buffer */
1651 if (num_add == filter_list_len) {
dcae29be
JB		 1652 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1653 add_list, num_add,
1654 NULL);
41c445ff
JB		 1655 num_add = 0;
1656
dcae29be 1657 if (aq_ret)
41c445ff
JB		 1658 break;
1659 memset(add_list, 0, sizeof(*add_list));
1660 }
1661 }
1662 if (num_add) {
dcae29be
JB		 1663 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1664 add_list, num_add, NULL);
41c445ff
JB		 1665 num_add = 0;
1666 }
1667 kfree(add_list);
1668 add_list = NULL;
1669
dcae29be 1670 if (add_happened && (!aq_ret)) {
41c445ff 1671 /* do nothing */;
dcae29be 1672 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1673 dev_info(&pf->pdev->dev,
1674 "add filter failed, err %d, aq_err %d\n",
dcae29be 1675 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1676 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1677 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1678 &vsi->state)) {
1679 promisc_forced_on = true;
1680 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1681 &vsi->state);
1682 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1683 }
1684 }
1685 }
1686
1687 /* check for changes in promiscuous modes */
1688 if (changed_flags & IFF_ALLMULTI) {
1689 bool cur_multipromisc;
1690 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1691 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1692 vsi->seid,
1693 cur_multipromisc,
1694 NULL);
1695 if (aq_ret)
41c445ff
JB		 1696 dev_info(&pf->pdev->dev,
1697 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1698 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1699 }
1700 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1701 bool cur_promisc;
1702 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1703 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1704 &vsi->state));
dcae29be
JB		 1705 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1706 vsi->seid,
1707 cur_promisc, NULL);
1708 if (aq_ret)
41c445ff
JB		 1709 dev_info(&pf->pdev->dev,
1710 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1711 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1712 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1713 vsi->seid,
1714 cur_promisc, NULL);
1715 if (aq_ret)
1716 dev_info(&pf->pdev->dev,
1717 "set brdcast promisc failed, err %d, aq_err %d\n",
1718 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1719 }
1720
1721 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1722 return 0;
1723}
1724
1725/**
1726 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1727 * @pf: board private structure
1728 **/
1729static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1730{
1731 int v;
1732
1733 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1734 return;
1735 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1736
1737 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1738 if (pf->vsi[v] &&
1739 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1740 i40e_sync_vsi_filters(pf->vsi[v]);
1741 }
1742}
1743
1744/**
1745 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1746 * @netdev: network interface device structure
1747 * @new_mtu: new value for maximum frame size
1748 *
1749 * Returns 0 on success, negative on failure
1750 **/
1751static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1752{
1753 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1754 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1755 struct i40e_vsi *vsi = np->vsi;
1756
1757 /* MTU < 68 is an error and causes problems on some kernels */
1758 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1759 return -EINVAL;
1760
1761 netdev_info(netdev, "changing MTU from %d to %d\n",
1762 netdev->mtu, new_mtu);
1763 netdev->mtu = new_mtu;
1764 if (netif_running(netdev))
1765 i40e_vsi_reinit_locked(vsi);
1766
1767 return 0;
1768}
1769
beb0dff1
JK		 1770/**
1771 * i40e_ioctl - Access the hwtstamp interface
1772 * @netdev: network interface device structure
1773 * @ifr: interface request data
1774 * @cmd: ioctl command
1775 **/
1776int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1777{
1778 struct i40e_netdev_priv *np = netdev_priv(netdev);
1779 struct i40e_pf *pf = np->vsi->back;
1780
1781 switch (cmd) {
1782 case SIOCGHWTSTAMP:
1783 return i40e_ptp_get_ts_config(pf, ifr);
1784 case SIOCSHWTSTAMP:
1785 return i40e_ptp_set_ts_config(pf, ifr);
1786 default:
1787 return -EOPNOTSUPP;
1788 }
1789}
1790
41c445ff
JB		 1791/**
1792 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1793 * @vsi: the vsi being adjusted
1794 **/
1795void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1796{
1797 struct i40e_vsi_context ctxt;
1798 i40e_status ret;
1799
1800 if ((vsi->info.valid_sections &
1801 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1802 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1803 return; /* already enabled */
1804
1805 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1806 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1807 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1808
1809 ctxt.seid = vsi->seid;
1810 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1811 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1812 if (ret) {
1813 dev_info(&vsi->back->pdev->dev,
1814 "%s: update vsi failed, aq_err=%d\n",
1815 __func__, vsi->back->hw.aq.asq_last_status);
1816 }
1817}
1818
1819/**
1820 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1821 * @vsi: the vsi being adjusted
1822 **/
1823void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1824{
1825 struct i40e_vsi_context ctxt;
1826 i40e_status ret;
1827
1828 if ((vsi->info.valid_sections &
1829 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1830 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1831 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1832 return; /* already disabled */
1833
1834 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1835 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1836 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1837
1838 ctxt.seid = vsi->seid;
1839 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1840 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1841 if (ret) {
1842 dev_info(&vsi->back->pdev->dev,
1843 "%s: update vsi failed, aq_err=%d\n",
1844 __func__, vsi->back->hw.aq.asq_last_status);
1845 }
1846}
1847
1848/**
1849 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1850 * @netdev: network interface to be adjusted
1851 * @features: netdev features to test if VLAN offload is enabled or not
1852 **/
1853static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1854{
1855 struct i40e_netdev_priv *np = netdev_priv(netdev);
1856 struct i40e_vsi *vsi = np->vsi;
1857
1858 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1859 i40e_vlan_stripping_enable(vsi);
1860 else
1861 i40e_vlan_stripping_disable(vsi);
1862}
1863
1864/**
1865 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1866 * @vsi: the vsi being configured
1867 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1868 **/
1869int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1870{
1871 struct i40e_mac_filter *f, *add_f;
1872 bool is_netdev, is_vf;
41c445ff
JB		 1873
1874 is_vf = (vsi->type == I40E_VSI_SRIOV);
1875 is_netdev = !!(vsi->netdev);
1876
1877 if (is_netdev) {
1878 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1879 is_vf, is_netdev);
1880 if (!add_f) {
1881 dev_info(&vsi->back->pdev->dev,
1882 "Could not add vlan filter %d for %pM\n",
1883 vid, vsi->netdev->dev_addr);
1884 return -ENOMEM;
1885 }
1886 }
1887
1888 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1889 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1890 if (!add_f) {
1891 dev_info(&vsi->back->pdev->dev,
1892 "Could not add vlan filter %d for %pM\n",
1893 vid, f->macaddr);
1894 return -ENOMEM;
1895 }
1896 }
1897
41c445ff
JB		 1898 /* Now if we add a vlan tag, make sure to check if it is the first
1899 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1900 * with 0, so we now accept untagged and specified tagged traffic
1901 * (and not any taged and untagged)
1902 */
1903 if (vid > 0) {
1904 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1905 I40E_VLAN_ANY,
1906 is_vf, is_netdev)) {
1907 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1908 I40E_VLAN_ANY, is_vf, is_netdev);
1909 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1910 is_vf, is_netdev);
1911 if (!add_f) {
1912 dev_info(&vsi->back->pdev->dev,
1913 "Could not add filter 0 for %pM\n",
1914 vsi->netdev->dev_addr);
1915 return -ENOMEM;
1916 }
1917 }
8d82a7c5 1918 }
41c445ff 1919
8d82a7c5
GR		 1920 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1921 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1922 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1923 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1924 is_vf, is_netdev)) {
1925 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1926 is_vf, is_netdev);
1927 add_f = i40e_add_filter(vsi, f->macaddr,
1928 0, is_vf, is_netdev);
1929 if (!add_f) {
1930 dev_info(&vsi->back->pdev->dev,
1931 "Could not add filter 0 for %pM\n",
1932 f->macaddr);
1933 return -ENOMEM;
1934 }
1935 }
1936 }
41c445ff
JB		 1937 }
1938
80f6428f
ASJ		 1939 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1940 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1941 return 0;
1942
1943 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1944}
1945
1946/**
1947 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1948 * @vsi: the vsi being configured
1949 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1950 *
1951 * Return: 0 on success or negative otherwise
41c445ff
JB		 1952 **/
1953int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1954{
1955 struct net_device *netdev = vsi->netdev;
1956 struct i40e_mac_filter *f, *add_f;
1957 bool is_vf, is_netdev;
1958 int filter_count = 0;
41c445ff
JB		 1959
1960 is_vf = (vsi->type == I40E_VSI_SRIOV);
1961 is_netdev = !!(netdev);
1962
1963 if (is_netdev)
1964 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1965
1966 list_for_each_entry(f, &vsi->mac_filter_list, list)
1967 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1968
41c445ff
JB		 1969 /* go through all the filters for this VSI and if there is only
1970 * vid == 0 it means there are no other filters, so vid 0 must
1971 * be replaced with -1. This signifies that we should from now
1972 * on accept any traffic (with any tag present, or untagged)
1973 */
1974 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1975 if (is_netdev) {
1976 if (f->vlan &&
1977 ether_addr_equal(netdev->dev_addr, f->macaddr))
1978 filter_count++;
1979 }
1980
1981 if (f->vlan)
1982 filter_count++;
1983 }
1984
1985 if (!filter_count && is_netdev) {
1986 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1987 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1988 is_vf, is_netdev);
1989 if (!f) {
1990 dev_info(&vsi->back->pdev->dev,
1991 "Could not add filter %d for %pM\n",
1992 I40E_VLAN_ANY, netdev->dev_addr);
1993 return -ENOMEM;
1994 }
1995 }
1996
1997 if (!filter_count) {
1998 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1999 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2000 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2001 is_vf, is_netdev);
2002 if (!add_f) {
2003 dev_info(&vsi->back->pdev->dev,
2004 "Could not add filter %d for %pM\n",
2005 I40E_VLAN_ANY, f->macaddr);
2006 return -ENOMEM;
2007 }
2008 }
2009 }
2010
80f6428f
ASJ		 2011 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2012 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2013 return 0;
2014
41c445ff
JB		 2015 return i40e_sync_vsi_filters(vsi);
2016}
2017
2018/**
2019 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2020 * @netdev: network interface to be adjusted
2021 * @vid: vlan id to be added
078b5876
JB		 2022 *
2023 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 2024 **/
2025static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2026 __always_unused __be16 proto, u16 vid)
2027{
2028 struct i40e_netdev_priv *np = netdev_priv(netdev);
2029 struct i40e_vsi *vsi = np->vsi;
078b5876 2030 int ret = 0;
41c445ff
JB		 2031
2032 if (vid > 4095)
078b5876
JB		 2033 return -EINVAL;
2034
2035 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2036
6982d429
ASJ		 2037 /* If the network stack called us with vid = 0 then
2038 * it is asking to receive priority tagged packets with
2039 * vlan id 0. Our HW receives them by default when configured
2040 * to receive untagged packets so there is no need to add an
2041 * extra filter for vlan 0 tagged packets.
41c445ff 2042 */
6982d429
ASJ		 2043 if (vid)
2044 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2045
078b5876
JB		 2046 if (!ret && (vid < VLAN_N_VID))
2047 set_bit(vid, vsi->active_vlans);
41c445ff 2048
078b5876 2049 return ret;
41c445ff
JB		 2050}
2051
2052/**
2053 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2054 * @netdev: network interface to be adjusted
2055 * @vid: vlan id to be removed
078b5876 2056 *
fdfd943e 2057 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2058 **/
2059static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2060 __always_unused __be16 proto, u16 vid)
2061{
2062 struct i40e_netdev_priv *np = netdev_priv(netdev);
2063 struct i40e_vsi *vsi = np->vsi;
2064
078b5876
JB		 2065 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2066
41c445ff
JB		 2067 /* return code is ignored as there is nothing a user
2068 * can do about failure to remove and a log message was
078b5876 2069 * already printed from the other function
41c445ff
JB		 2070 */
2071 i40e_vsi_kill_vlan(vsi, vid);
2072
2073 clear_bit(vid, vsi->active_vlans);
078b5876 2074
41c445ff
JB		 2075 return 0;
2076}
2077
2078/**
2079 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2080 * @vsi: the vsi being brought back up
2081 **/
2082static void i40e_restore_vlan(struct i40e_vsi *vsi)
2083{
2084 u16 vid;
2085
2086 if (!vsi->netdev)
2087 return;
2088
2089 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2090
2091 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2092 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2093 vid);
2094}
2095
2096/**
2097 * i40e_vsi_add_pvid - Add pvid for the VSI
2098 * @vsi: the vsi being adjusted
2099 * @vid: the vlan id to set as a PVID
2100 **/
dcae29be 2101int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2102{
2103 struct i40e_vsi_context ctxt;
dcae29be 2104 i40e_status aq_ret;
41c445ff
JB		 2105
2106 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2107 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2108 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2109 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2110 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2111
2112 ctxt.seid = vsi->seid;
2113 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2114 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2115 if (aq_ret) {
41c445ff
JB		 2116 dev_info(&vsi->back->pdev->dev,
2117 "%s: update vsi failed, aq_err=%d\n",
2118 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2119 return -ENOENT;
41c445ff
JB		 2120 }
2121
dcae29be 2122 return 0;
41c445ff
JB		 2123}
2124
2125/**
2126 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2127 * @vsi: the vsi being adjusted
2128 *
2129 * Just use the vlan_rx_register() service to put it back to normal
2130 **/
2131void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2132{
6c12fcbf
GR		 2133 i40e_vlan_stripping_disable(vsi);
2134
41c445ff 2135 vsi->info.pvid = 0;
41c445ff
JB		 2136}
2137
2138/**
2139 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2140 * @vsi: ptr to the VSI
2141 *
2142 * If this function returns with an error, then it's possible one or
2143 * more of the rings is populated (while the rest are not). It is the
2144 * callers duty to clean those orphaned rings.
2145 *
2146 * Return 0 on success, negative on failure
2147 **/
2148static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2149{
2150 int i, err = 0;
2151
2152 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2153 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2154
2155 return err;
2156}
2157
2158/**
2159 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2160 * @vsi: ptr to the VSI
2161 *
2162 * Free VSI's transmit software resources
2163 **/
2164static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2165{
2166 int i;
2167
8e9dca53
GR		 2168 if (!vsi->tx_rings)
2169 return;
2170
41c445ff 2171 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2172 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2173 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2174}
2175
2176/**
2177 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2178 * @vsi: ptr to the VSI
2179 *
2180 * If this function returns with an error, then it's possible one or
2181 * more of the rings is populated (while the rest are not). It is the
2182 * callers duty to clean those orphaned rings.
2183 *
2184 * Return 0 on success, negative on failure
2185 **/
2186static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2187{
2188 int i, err = 0;
2189
2190 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2191 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2192 return err;
2193}
2194
2195/**
2196 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2197 * @vsi: ptr to the VSI
2198 *
2199 * Free all receive software resources
2200 **/
2201static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2202{
2203 int i;
2204
8e9dca53
GR		 2205 if (!vsi->rx_rings)
2206 return;
2207
41c445ff 2208 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2209 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2210 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2211}
2212
2213/**
2214 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2215 * @ring: The Tx ring to configure
2216 *
2217 * Configure the Tx descriptor ring in the HMC context.
2218 **/
2219static int i40e_configure_tx_ring(struct i40e_ring *ring)
2220{
2221 struct i40e_vsi *vsi = ring->vsi;
2222 u16 pf_q = vsi->base_queue + ring->queue_index;
2223 struct i40e_hw *hw = &vsi->back->hw;
2224 struct i40e_hmc_obj_txq tx_ctx;
2225 i40e_status err = 0;
2226 u32 qtx_ctl = 0;
2227
2228 /* some ATR related tx ring init */
60ea5f83 2229 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2230 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2231 ring->atr_count = 0;
2232 } else {
2233 ring->atr_sample_rate = 0;
2234 }
2235
2236 /* initialize XPS */
2237 if (ring->q_vector && ring->netdev &&
4e3b35b0 2238 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2239 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2240 netif_set_xps_queue(ring->netdev,
2241 &ring->q_vector->affinity_mask,
2242 ring->queue_index);
2243
2244 /* clear the context structure first */
2245 memset(&tx_ctx, 0, sizeof(tx_ctx));
2246
2247 tx_ctx.new_context = 1;
2248 tx_ctx.base = (ring->dma / 128);
2249 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2250 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2251 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2252 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2253 /* FDIR VSI tx ring can still use RS bit and writebacks */
2254 if (vsi->type != I40E_VSI_FDIR)
2255 tx_ctx.head_wb_ena = 1;
2256 tx_ctx.head_wb_addr = ring->dma +
2257 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2258
2259 /* As part of VSI creation/update, FW allocates certain
2260 * Tx arbitration queue sets for each TC enabled for
2261 * the VSI. The FW returns the handles to these queue
2262 * sets as part of the response buffer to Add VSI,
2263 * Update VSI, etc. AQ commands. It is expected that
2264 * these queue set handles be associated with the Tx
2265 * queues by the driver as part of the TX queue context
2266 * initialization. This has to be done regardless of
2267 * DCB as by default everything is mapped to TC0.
2268 */
2269 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2270 tx_ctx.rdylist_act = 0;
2271
2272 /* clear the context in the HMC */
2273 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2274 if (err) {
2275 dev_info(&vsi->back->pdev->dev,
2276 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2277 ring->queue_index, pf_q, err);
2278 return -ENOMEM;
2279 }
2280
2281 /* set the context in the HMC */
2282 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2283 if (err) {
2284 dev_info(&vsi->back->pdev->dev,
2285 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2286 ring->queue_index, pf_q, err);
2287 return -ENOMEM;
2288 }
2289
2290 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2291 if (vsi->type == I40E_VSI_VMDQ2)
2292 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2293 else
2294 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2295 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2296 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2297 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2298 i40e_flush(hw);
2299
2300 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2301
2302 /* cache tail off for easier writes later */
2303 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2304
2305 return 0;
2306}
2307
2308/**
2309 * i40e_configure_rx_ring - Configure a receive ring context
2310 * @ring: The Rx ring to configure
2311 *
2312 * Configure the Rx descriptor ring in the HMC context.
2313 **/
2314static int i40e_configure_rx_ring(struct i40e_ring *ring)
2315{
2316 struct i40e_vsi *vsi = ring->vsi;
2317 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2318 u16 pf_q = vsi->base_queue + ring->queue_index;
2319 struct i40e_hw *hw = &vsi->back->hw;
2320 struct i40e_hmc_obj_rxq rx_ctx;
2321 i40e_status err = 0;
2322
2323 ring->state = 0;
2324
2325 /* clear the context structure first */
2326 memset(&rx_ctx, 0, sizeof(rx_ctx));
2327
2328 ring->rx_buf_len = vsi->rx_buf_len;
2329 ring->rx_hdr_len = vsi->rx_hdr_len;
2330
2331 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2332 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2333
2334 rx_ctx.base = (ring->dma / 128);
2335 rx_ctx.qlen = ring->count;
2336
2337 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2338 set_ring_16byte_desc_enabled(ring);
2339 rx_ctx.dsize = 0;
2340 } else {
2341 rx_ctx.dsize = 1;
2342 }
2343
2344 rx_ctx.dtype = vsi->dtype;
2345 if (vsi->dtype) {
2346 set_ring_ps_enabled(ring);
2347 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2348 I40E_RX_SPLIT_IP |
2349 I40E_RX_SPLIT_TCP_UDP |
2350 I40E_RX_SPLIT_SCTP;
2351 } else {
2352 rx_ctx.hsplit_0 = 0;
2353 }
2354
2355 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2356 (chain_len * ring->rx_buf_len));
2357 rx_ctx.tphrdesc_ena = 1;
2358 rx_ctx.tphwdesc_ena = 1;
2359 rx_ctx.tphdata_ena = 1;
2360 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2361 if (hw->revision_id == 0)
2362 rx_ctx.lrxqthresh = 0;
2363 else
2364 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2365 rx_ctx.crcstrip = 1;
2366 rx_ctx.l2tsel = 1;
2367 rx_ctx.showiv = 1;
acb3676b
CS		 2368 /* set the prefena field to 1 because the manual says to */
2369 rx_ctx.prefena = 1;
41c445ff
JB		 2370
2371 /* clear the context in the HMC */
2372 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2373 if (err) {
2374 dev_info(&vsi->back->pdev->dev,
2375 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2376 ring->queue_index, pf_q, err);
2377 return -ENOMEM;
2378 }
2379
2380 /* set the context in the HMC */
2381 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2382 if (err) {
2383 dev_info(&vsi->back->pdev->dev,
2384 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2385 ring->queue_index, pf_q, err);
2386 return -ENOMEM;
2387 }
2388
2389 /* cache tail for quicker writes, and clear the reg before use */
2390 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2391 writel(0, ring->tail);
2392
2393 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2394
2395 return 0;
2396}
2397
2398/**
2399 * i40e_vsi_configure_tx - Configure the VSI for Tx
2400 * @vsi: VSI structure describing this set of rings and resources
2401 *
2402 * Configure the Tx VSI for operation.
2403 **/
2404static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2405{
2406 int err = 0;
2407 u16 i;
2408
9f65e15b
AD		 2409 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2410 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2411
2412 return err;
2413}
2414
2415/**
2416 * i40e_vsi_configure_rx - Configure the VSI for Rx
2417 * @vsi: the VSI being configured
2418 *
2419 * Configure the Rx VSI for operation.
2420 **/
2421static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2422{
2423 int err = 0;
2424 u16 i;
2425
2426 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2427 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2428 + ETH_FCS_LEN + VLAN_HLEN;
2429 else
2430 vsi->max_frame = I40E_RXBUFFER_2048;
2431
2432 /* figure out correct receive buffer length */
2433 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2434 I40E_FLAG_RX_PS_ENABLED)) {
2435 case I40E_FLAG_RX_1BUF_ENABLED:
2436 vsi->rx_hdr_len = 0;
2437 vsi->rx_buf_len = vsi->max_frame;
2438 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2439 break;
2440 case I40E_FLAG_RX_PS_ENABLED:
2441 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2442 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2443 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2444 break;
2445 default:
2446 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2447 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2448 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2449 break;
2450 }
2451
2452 /* round up for the chip's needs */
2453 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2454 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2455 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2456 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2457
2458 /* set up individual rings */
2459 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2460 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2461
2462 return err;
2463}
2464
2465/**
2466 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2467 * @vsi: ptr to the VSI
2468 **/
2469static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2470{
e7046ee1 2471 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2472 u16 qoffset, qcount;
2473 int i, n;
2474
2475 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2476 return;
2477
2478 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2479 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2480 continue;
2481
2482 qoffset = vsi->tc_config.tc_info[n].qoffset;
2483 qcount = vsi->tc_config.tc_info[n].qcount;
2484 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2485 rx_ring = vsi->rx_rings[i];
2486 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2487 rx_ring->dcb_tc = n;
2488 tx_ring->dcb_tc = n;
2489 }
2490 }
2491}
2492
2493/**
2494 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2495 * @vsi: ptr to the VSI
2496 **/
2497static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2498{
2499 if (vsi->netdev)
2500 i40e_set_rx_mode(vsi->netdev);
2501}
2502
17a73f6b
JG		 2503/**
2504 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2505 * @vsi: Pointer to the targeted VSI
2506 *
2507 * This function replays the hlist on the hw where all the SB Flow Director
2508 * filters were saved.
2509 **/
2510static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2511{
2512 struct i40e_fdir_filter *filter;
2513 struct i40e_pf *pf = vsi->back;
2514 struct hlist_node *node;
2515
55a5e60b
ASJ		 2516 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2517 return;
2518
17a73f6b
JG		 2519 hlist_for_each_entry_safe(filter, node,
2520 &pf->fdir_filter_list, fdir_node) {
2521 i40e_add_del_fdir(vsi, filter, true);
2522 }
2523}
2524
41c445ff
JB		 2525/**
2526 * i40e_vsi_configure - Set up the VSI for action
2527 * @vsi: the VSI being configured
2528 **/
2529static int i40e_vsi_configure(struct i40e_vsi *vsi)
2530{
2531 int err;
2532
2533 i40e_set_vsi_rx_mode(vsi);
2534 i40e_restore_vlan(vsi);
2535 i40e_vsi_config_dcb_rings(vsi);
2536 err = i40e_vsi_configure_tx(vsi);
2537 if (!err)
2538 err = i40e_vsi_configure_rx(vsi);
2539
2540 return err;
2541}
2542
2543/**
2544 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2545 * @vsi: the VSI being configured
2546 **/
2547static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2548{
2549 struct i40e_pf *pf = vsi->back;
2550 struct i40e_q_vector *q_vector;
2551 struct i40e_hw *hw = &pf->hw;
2552 u16 vector;
2553 int i, q;
2554 u32 val;
2555 u32 qp;
2556
2557 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2558 * and PFINT_LNKLSTn registers, e.g.:
2559 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2560 */
2561 qp = vsi->base_queue;
2562 vector = vsi->base_vector;
493fb300
AD		 2563 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2564 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2565 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2566 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2567 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2568 q_vector->rx.itr);
2569 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2570 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2571 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2572 q_vector->tx.itr);
2573
2574 /* Linked list for the queuepairs assigned to this vector */
2575 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2576 for (q = 0; q < q_vector->num_ringpairs; q++) {
2577 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2578 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2579 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2580 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2581 (I40E_QUEUE_TYPE_TX
2582 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2583
2584 wr32(hw, I40E_QINT_RQCTL(qp), val);
2585
2586 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2587 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2588 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2589 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2590 (I40E_QUEUE_TYPE_RX
2591 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2592
2593 /* Terminate the linked list */
2594 if (q == (q_vector->num_ringpairs - 1))
2595 val |= (I40E_QUEUE_END_OF_LIST
2596 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2597
2598 wr32(hw, I40E_QINT_TQCTL(qp), val);
2599 qp++;
2600 }
2601 }
2602
2603 i40e_flush(hw);
2604}
2605
2606/**
2607 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2608 * @hw: ptr to the hardware info
2609 **/
2610static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2611{
2612 u32 val;
2613
2614 /* clear things first */
2615 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2616 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2617
2618 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2619 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2620 I40E_PFINT_ICR0_ENA_GRST_MASK |
2621 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2622 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2623 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2624 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2625 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2626 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2627
2628 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2629
2630 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2631 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2632 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2633
2634 /* OTHER_ITR_IDX = 0 */
2635 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2636}
2637
2638/**
2639 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2640 * @vsi: the VSI being configured
2641 **/
2642static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2643{
493fb300 2644 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2645 struct i40e_pf *pf = vsi->back;
2646 struct i40e_hw *hw = &pf->hw;
2647 u32 val;
2648
2649 /* set the ITR configuration */
2650 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2651 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2652 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2653 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2654 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2655 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2656
2657 i40e_enable_misc_int_causes(hw);
2658
2659 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2660 wr32(hw, I40E_PFINT_LNKLST0, 0);
2661
f29eaa3d 2662 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2663 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2664 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2665 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2666
2667 wr32(hw, I40E_QINT_RQCTL(0), val);
2668
2669 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2670 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2671 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2672
2673 wr32(hw, I40E_QINT_TQCTL(0), val);
2674 i40e_flush(hw);
2675}
2676
2ef28cfb
MW		 2677/**
2678 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2679 * @pf: board private structure
2680 **/
2681void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2682{
2683 struct i40e_hw *hw = &pf->hw;
2684
2685 wr32(hw, I40E_PFINT_DYN_CTL0,
2686 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2687 i40e_flush(hw);
2688}
2689
41c445ff
JB		 2690/**
2691 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2692 * @pf: board private structure
2693 **/
116a57d4 2694void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2695{
2696 struct i40e_hw *hw = &pf->hw;
2697 u32 val;
2698
2699 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2700 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2701 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2702
2703 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2704 i40e_flush(hw);
2705}
2706
2707/**
2708 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2709 * @vsi: pointer to a vsi
2710 * @vector: enable a particular Hw Interrupt vector
2711 **/
2712void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2713{
2714 struct i40e_pf *pf = vsi->back;
2715 struct i40e_hw *hw = &pf->hw;
2716 u32 val;
2717
2718 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2719 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2720 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2721 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2722 /* skip the flush */
41c445ff
JB		 2723}
2724
2725/**
2726 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2727 * @irq: interrupt number
2728 * @data: pointer to a q_vector
2729 **/
2730static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2731{
2732 struct i40e_q_vector *q_vector = data;
2733
cd0b6fa6 2734 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2735 return IRQ_HANDLED;
2736
2737 napi_schedule(&q_vector->napi);
2738
2739 return IRQ_HANDLED;
2740}
2741
41c445ff
JB		 2742/**
2743 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2744 * @vsi: the VSI being configured
2745 * @basename: name for the vector
2746 *
2747 * Allocates MSI-X vectors and requests interrupts from the kernel.
2748 **/
2749static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2750{
2751 int q_vectors = vsi->num_q_vectors;
2752 struct i40e_pf *pf = vsi->back;
2753 int base = vsi->base_vector;
2754 int rx_int_idx = 0;
2755 int tx_int_idx = 0;
2756 int vector, err;
2757
2758 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2759 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2760
cd0b6fa6 2761 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2762 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2763 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2764 tx_int_idx++;
cd0b6fa6 2765 } else if (q_vector->rx.ring) {
41c445ff
JB		 2766 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2767 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2768 } else if (q_vector->tx.ring) {
41c445ff
JB		 2769 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2770 "%s-%s-%d", basename, "tx", tx_int_idx++);
2771 } else {
2772 /* skip this unused q_vector */
2773 continue;
2774 }
2775 err = request_irq(pf->msix_entries[base + vector].vector,
2776 vsi->irq_handler,
2777 0,
2778 q_vector->name,
2779 q_vector);
2780 if (err) {
2781 dev_info(&pf->pdev->dev,
2782 "%s: request_irq failed, error: %d\n",
2783 __func__, err);
2784 goto free_queue_irqs;
2785 }
2786 /* assign the mask for this irq */
2787 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2788 &q_vector->affinity_mask);
2789 }
2790
63741846 2791 vsi->irqs_ready = true;
41c445ff
JB		 2792 return 0;
2793
2794free_queue_irqs:
2795 while (vector) {
2796 vector--;
2797 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2798 NULL);
2799 free_irq(pf->msix_entries[base + vector].vector,
2800 &(vsi->q_vectors[vector]));
2801 }
2802 return err;
2803}
2804
2805/**
2806 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2807 * @vsi: the VSI being un-configured
2808 **/
2809static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2810{
2811 struct i40e_pf *pf = vsi->back;
2812 struct i40e_hw *hw = &pf->hw;
2813 int base = vsi->base_vector;
2814 int i;
2815
2816 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2817 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2818 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2819 }
2820
2821 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2822 for (i = vsi->base_vector;
2823 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2824 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2825
2826 i40e_flush(hw);
2827 for (i = 0; i < vsi->num_q_vectors; i++)
2828 synchronize_irq(pf->msix_entries[i + base].vector);
2829 } else {
2830 /* Legacy and MSI mode - this stops all interrupt handling */
2831 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2832 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2833 i40e_flush(hw);
2834 synchronize_irq(pf->pdev->irq);
2835 }
2836}
2837
2838/**
2839 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2840 * @vsi: the VSI being configured
2841 **/
2842static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2843{
2844 struct i40e_pf *pf = vsi->back;
2845 int i;
2846
2847 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2848 for (i = vsi->base_vector;
2849 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2850 i40e_irq_dynamic_enable(vsi, i);
2851 } else {
2852 i40e_irq_dynamic_enable_icr0(pf);
2853 }
2854
1022cb6c 2855 i40e_flush(&pf->hw);
41c445ff
JB		 2856 return 0;
2857}
2858
2859/**
2860 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2861 * @pf: board private structure
2862 **/
2863static void i40e_stop_misc_vector(struct i40e_pf *pf)
2864{
2865 /* Disable ICR 0 */
2866 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2867 i40e_flush(&pf->hw);
2868}
2869
2870/**
2871 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2872 * @irq: interrupt number
2873 * @data: pointer to a q_vector
2874 *
2875 * This is the handler used for all MSI/Legacy interrupts, and deals
2876 * with both queue and non-queue interrupts. This is also used in
2877 * MSIX mode to handle the non-queue interrupts.
2878 **/
2879static irqreturn_t i40e_intr(int irq, void *data)
2880{
2881 struct i40e_pf *pf = (struct i40e_pf *)data;
2882 struct i40e_hw *hw = &pf->hw;
5e823066 2883 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2884 u32 icr0, icr0_remaining;
2885 u32 val, ena_mask;
2886
2887 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2888 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2889
116a57d4
SN		 2890 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2891 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2892 goto enable_intr;
41c445ff 2893
cd92e72f
SN		 2894 /* if interrupt but no bits showing, must be SWINT */
2895 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2896 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2897 pf->sw_int_count++;
2898
41c445ff
JB		 2899 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2900 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2901
2902 /* temporarily disable queue cause for NAPI processing */
2903 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2904 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2905 wr32(hw, I40E_QINT_RQCTL(0), qval);
2906
2907 qval = rd32(hw, I40E_QINT_TQCTL(0));
2908 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2909 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2910
2911 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2912 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2913 }
2914
2915 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2916 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2917 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2918 }
2919
2920 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2921 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2922 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2923 }
2924
2925 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2926 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2927 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2928 }
2929
2930 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2931 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2932 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2933 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2934 val = rd32(hw, I40E_GLGEN_RSTAT);
2935 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2936 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2937 if (val == I40E_RESET_CORER) {
41c445ff 2938 pf->corer_count++;
4eb3f768 2939 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2940 pf->globr_count++;
4eb3f768 2941 } else if (val == I40E_RESET_EMPR) {
41c445ff 2942 pf->empr_count++;
4eb3f768
SN		 2943 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2944 }
41c445ff
JB		 2945 }
2946
9c010ee0
ASJ		 2947 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2948 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2949 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2950 }
2951
beb0dff1
JK		 2952 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2953 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2954
2955 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 2956 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 2957 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 2958 }
beb0dff1
JK		 2959 }
2960
41c445ff
JB		 2961 /* If a critical error is pending we have no choice but to reset the
2962 * device.
2963 * Report and mask out any remaining unexpected interrupts.
2964 */
2965 icr0_remaining = icr0 & ena_mask;
2966 if (icr0_remaining) {
2967 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2968 icr0_remaining);
9c010ee0 2969 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2970 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2971 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2972 dev_info(&pf->pdev->dev, "device will be reset\n");
2973 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2974 i40e_service_event_schedule(pf);
41c445ff
JB		 2975 }
2976 ena_mask &= ~icr0_remaining;
2977 }
5e823066 2978 ret = IRQ_HANDLED;
41c445ff 2979
5e823066 2980enable_intr:
41c445ff
JB		 2981 /* re-enable interrupt causes */
2982 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2983 if (!test_bit(__I40E_DOWN, &pf->state)) {
2984 i40e_service_event_schedule(pf);
2985 i40e_irq_dynamic_enable_icr0(pf);
2986 }
2987
5e823066 2988 return ret;
41c445ff
JB		 2989}
2990
cbf61325
ASJ		 2991/**
2992 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2993 * @tx_ring: tx ring to clean
2994 * @budget: how many cleans we're allowed
2995 *
2996 * Returns true if there's any budget left (e.g. the clean is finished)
2997 **/
2998static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2999{
3000 struct i40e_vsi *vsi = tx_ring->vsi;
3001 u16 i = tx_ring->next_to_clean;
3002 struct i40e_tx_buffer *tx_buf;
3003 struct i40e_tx_desc *tx_desc;
3004
3005 tx_buf = &tx_ring->tx_bi[i];
3006 tx_desc = I40E_TX_DESC(tx_ring, i);
3007 i -= tx_ring->count;
3008
3009 do {
3010 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3011
3012 /* if next_to_watch is not set then there is no work pending */
3013 if (!eop_desc)
3014 break;
3015
3016 /* prevent any other reads prior to eop_desc */
3017 read_barrier_depends();
3018
3019 /* if the descriptor isn't done, no work yet to do */
3020 if (!(eop_desc->cmd_type_offset_bsz &
3021 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3022 break;
3023
3024 /* clear next_to_watch to prevent false hangs */
3025 tx_buf->next_to_watch = NULL;
3026
3027 /* unmap skb header data */
3028 dma_unmap_single(tx_ring->dev,
3029 dma_unmap_addr(tx_buf, dma),
3030 dma_unmap_len(tx_buf, len),
3031 DMA_TO_DEVICE);
3032
3033 dma_unmap_len_set(tx_buf, len, 0);
3034
3035
3036 /* move to the next desc and buffer to clean */
3037 tx_buf++;
3038 tx_desc++;
3039 i++;
3040 if (unlikely(!i)) {
3041 i -= tx_ring->count;
3042 tx_buf = tx_ring->tx_bi;
3043 tx_desc = I40E_TX_DESC(tx_ring, 0);
3044 }
3045
3046 /* update budget accounting */
3047 budget--;
3048 } while (likely(budget));
3049
3050 i += tx_ring->count;
3051 tx_ring->next_to_clean = i;
3052
3053 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3054 i40e_irq_dynamic_enable(vsi,
3055 tx_ring->q_vector->v_idx + vsi->base_vector);
3056 }
3057 return budget > 0;
3058}
3059
3060/**
3061 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3062 * @irq: interrupt number
3063 * @data: pointer to a q_vector
3064 **/
3065static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3066{
3067 struct i40e_q_vector *q_vector = data;
3068 struct i40e_vsi *vsi;
3069
3070 if (!q_vector->tx.ring)
3071 return IRQ_HANDLED;
3072
3073 vsi = q_vector->tx.ring->vsi;
3074 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3075
3076 return IRQ_HANDLED;
3077}
3078
41c445ff 3079/**
cd0b6fa6 3080 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3081 * @vsi: the VSI being configured
3082 * @v_idx: vector index
cd0b6fa6 3083 * @qp_idx: queue pair index
41c445ff 3084 **/
cd0b6fa6 3085static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3086{
493fb300 3087 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3088 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3089 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3090
3091 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3092 tx_ring->next = q_vector->tx.ring;
3093 q_vector->tx.ring = tx_ring;
41c445ff 3094 q_vector->tx.count++;
cd0b6fa6
AD		 3095
3096 rx_ring->q_vector = q_vector;
3097 rx_ring->next = q_vector->rx.ring;
3098 q_vector->rx.ring = rx_ring;
3099 q_vector->rx.count++;
41c445ff
JB		 3100}
3101
3102/**
3103 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3104 * @vsi: the VSI being configured
3105 *
3106 * This function maps descriptor rings to the queue-specific vectors
3107 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3108 * one vector per queue pair, but on a constrained vector budget, we
3109 * group the queue pairs as "efficiently" as possible.
3110 **/
3111static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3112{
3113 int qp_remaining = vsi->num_queue_pairs;
3114 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3115 int num_ringpairs;
41c445ff
JB		 3116 int v_start = 0;
3117 int qp_idx = 0;
3118
3119 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3120 * group them so there are multiple queues per vector.
3121 */
3122 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3123 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3124
3125 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3126
3127 q_vector->num_ringpairs = num_ringpairs;
3128
3129 q_vector->rx.count = 0;
3130 q_vector->tx.count = 0;
3131 q_vector->rx.ring = NULL;
3132 q_vector->tx.ring = NULL;
3133
3134 while (num_ringpairs--) {
3135 map_vector_to_qp(vsi, v_start, qp_idx);
3136 qp_idx++;
3137 qp_remaining--;
41c445ff
JB		 3138 }
3139 }
3140}
3141
3142/**
3143 * i40e_vsi_request_irq - Request IRQ from the OS
3144 * @vsi: the VSI being configured
3145 * @basename: name for the vector
3146 **/
3147static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3148{
3149 struct i40e_pf *pf = vsi->back;
3150 int err;
3151
3152 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3153 err = i40e_vsi_request_irq_msix(vsi, basename);
3154 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3155 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3156 pf->misc_int_name, pf);
3157 else
3158 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3159 pf->misc_int_name, pf);
3160
3161 if (err)
3162 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3163
3164 return err;
3165}
3166
3167#ifdef CONFIG_NET_POLL_CONTROLLER
3168/**
3169 * i40e_netpoll - A Polling 'interrupt'handler
3170 * @netdev: network interface device structure
3171 *
3172 * This is used by netconsole to send skbs without having to re-enable
3173 * interrupts. It's not called while the normal interrupt routine is executing.
3174 **/
3175static void i40e_netpoll(struct net_device *netdev)
3176{
3177 struct i40e_netdev_priv *np = netdev_priv(netdev);
3178 struct i40e_vsi *vsi = np->vsi;
3179 struct i40e_pf *pf = vsi->back;
3180 int i;
3181
3182 /* if interface is down do nothing */
3183 if (test_bit(__I40E_DOWN, &vsi->state))
3184 return;
3185
3186 pf->flags |= I40E_FLAG_IN_NETPOLL;
3187 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3188 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3189 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3190 } else {
3191 i40e_intr(pf->pdev->irq, netdev);
3192 }
3193 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3194}
3195#endif
3196
3197/**
3198 * i40e_vsi_control_tx - Start or stop a VSI's rings
3199 * @vsi: the VSI being configured
3200 * @enable: start or stop the rings
3201 **/
3202static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3203{
3204 struct i40e_pf *pf = vsi->back;
3205 struct i40e_hw *hw = &pf->hw;
3206 int i, j, pf_q;
3207 u32 tx_reg;
3208
3209 pf_q = vsi->base_queue;
3210 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3211
3212 /* warn the TX unit of coming changes */
3213 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3214 if (!enable)
3215 udelay(10);
3216
6c5ef620 3217 for (j = 0; j < 50; j++) {
41c445ff 3218 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3219 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3220 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3221 break;
3222 usleep_range(1000, 2000);
3223 }
fda972f6 3224 /* Skip if the queue is already in the requested state */
7c122007 3225 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3226 continue;
41c445ff
JB		 3227
3228 /* turn on/off the queue */
c5c9eb9e
SN		 3229 if (enable) {
3230 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3231 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3232 } else {
41c445ff 3233 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3234 }
41c445ff
JB		 3235
3236 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3237
3238 /* wait for the change to finish */
3239 for (j = 0; j < 10; j++) {
3240 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
7c122007
CS		 3241 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3242 break;
41c445ff
JB		 3243
3244 udelay(10);
3245 }
3246 if (j >= 10) {
3247 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3248 pf_q, (enable ? "en" : "dis"));
3249 return -ETIMEDOUT;
3250 }
3251 }
3252
7134f9ce
JB		 3253 if (hw->revision_id == 0)
3254 mdelay(50);
3255
41c445ff
JB		 3256 return 0;
3257}
3258
3259/**
3260 * i40e_vsi_control_rx - Start or stop a VSI's rings
3261 * @vsi: the VSI being configured
3262 * @enable: start or stop the rings
3263 **/
3264static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3265{
3266 struct i40e_pf *pf = vsi->back;
3267 struct i40e_hw *hw = &pf->hw;
3268 int i, j, pf_q;
3269 u32 rx_reg;
3270
3271 pf_q = vsi->base_queue;
3272 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3273 for (j = 0; j < 50; j++) {
41c445ff 3274 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3275 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3276 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3277 break;
3278 usleep_range(1000, 2000);
3279 }
41c445ff 3280
7c122007
CS		 3281 /* Skip if the queue is already in the requested state */
3282 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3283 continue;
41c445ff
JB		 3284
3285 /* turn on/off the queue */
3286 if (enable)
6c5ef620 3287 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3288 else
6c5ef620 3289 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3290 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3291
3292 /* wait for the change to finish */
3293 for (j = 0; j < 10; j++) {
3294 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3295
7c122007
CS		 3296 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3297 break;
41c445ff
JB		 3298
3299 udelay(10);
3300 }
3301 if (j >= 10) {
3302 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3303 pf_q, (enable ? "en" : "dis"));
3304 return -ETIMEDOUT;
3305 }
3306 }
3307
3308 return 0;
3309}
3310
3311/**
3312 * i40e_vsi_control_rings - Start or stop a VSI's rings
3313 * @vsi: the VSI being configured
3314 * @enable: start or stop the rings
3315 **/
fc18eaa0 3316int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3317{
3b867b28 3318 int ret = 0;
41c445ff
JB		 3319
3320 /* do rx first for enable and last for disable */
3321 if (request) {
3322 ret = i40e_vsi_control_rx(vsi, request);
3323 if (ret)
3324 return ret;
3325 ret = i40e_vsi_control_tx(vsi, request);
3326 } else {
3b867b28
ASJ		 3327 /* Ignore return value, we need to shutdown whatever we can */
3328 i40e_vsi_control_tx(vsi, request);
3329 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3330 }
3331
3332 return ret;
3333}
3334
3335/**
3336 * i40e_vsi_free_irq - Free the irq association with the OS
3337 * @vsi: the VSI being configured
3338 **/
3339static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3340{
3341 struct i40e_pf *pf = vsi->back;
3342 struct i40e_hw *hw = &pf->hw;
3343 int base = vsi->base_vector;
3344 u32 val, qp;
3345 int i;
3346
3347 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3348 if (!vsi->q_vectors)
3349 return;
3350
63741846
SN		 3351 if (!vsi->irqs_ready)
3352 return;
3353
3354 vsi->irqs_ready = false;
41c445ff
JB		 3355 for (i = 0; i < vsi->num_q_vectors; i++) {
3356 u16 vector = i + base;
3357
3358 /* free only the irqs that were actually requested */
78681b1f
SN		 3359 if (!vsi->q_vectors[i] ||
3360 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3361 continue;
3362
3363 /* clear the affinity_mask in the IRQ descriptor */
3364 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3365 NULL);
3366 free_irq(pf->msix_entries[vector].vector,
493fb300 3367 vsi->q_vectors[i]);
41c445ff
JB		 3368
3369 /* Tear down the interrupt queue link list
3370 *
3371 * We know that they come in pairs and always
3372 * the Rx first, then the Tx. To clear the
3373 * link list, stick the EOL value into the
3374 * next_q field of the registers.
3375 */
3376 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3377 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3378 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3379 val |= I40E_QUEUE_END_OF_LIST
3380 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3381 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3382
3383 while (qp != I40E_QUEUE_END_OF_LIST) {
3384 u32 next;
3385
3386 val = rd32(hw, I40E_QINT_RQCTL(qp));
3387
3388 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3389 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3390 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3391 I40E_QINT_RQCTL_INTEVENT_MASK);
3392
3393 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3394 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3395
3396 wr32(hw, I40E_QINT_RQCTL(qp), val);
3397
3398 val = rd32(hw, I40E_QINT_TQCTL(qp));
3399
3400 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3401 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3402
3403 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3404 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3405 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3406 I40E_QINT_TQCTL_INTEVENT_MASK);
3407
3408 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3409 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3410
3411 wr32(hw, I40E_QINT_TQCTL(qp), val);
3412 qp = next;
3413 }
3414 }
3415 } else {
3416 free_irq(pf->pdev->irq, pf);
3417
3418 val = rd32(hw, I40E_PFINT_LNKLST0);
3419 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3420 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3421 val |= I40E_QUEUE_END_OF_LIST
3422 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3423 wr32(hw, I40E_PFINT_LNKLST0, val);
3424
3425 val = rd32(hw, I40E_QINT_RQCTL(qp));
3426 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3427 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3428 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3429 I40E_QINT_RQCTL_INTEVENT_MASK);
3430
3431 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3432 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3433
3434 wr32(hw, I40E_QINT_RQCTL(qp), val);
3435
3436 val = rd32(hw, I40E_QINT_TQCTL(qp));
3437
3438 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3439 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3440 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3441 I40E_QINT_TQCTL_INTEVENT_MASK);
3442
3443 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3444 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3445
3446 wr32(hw, I40E_QINT_TQCTL(qp), val);
3447 }
3448}
3449
493fb300
AD		 3450/**
3451 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3452 * @vsi: the VSI being configured
3453 * @v_idx: Index of vector to be freed
3454 *
3455 * This function frees the memory allocated to the q_vector. In addition if
3456 * NAPI is enabled it will delete any references to the NAPI struct prior
3457 * to freeing the q_vector.
3458 **/
3459static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3460{
3461 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3462 struct i40e_ring *ring;
493fb300
AD		 3463
3464 if (!q_vector)
3465 return;
3466
3467 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3468 i40e_for_each_ring(ring, q_vector->tx)
3469 ring->q_vector = NULL;
3470
3471 i40e_for_each_ring(ring, q_vector->rx)
3472 ring->q_vector = NULL;
493fb300
AD		 3473
3474 /* only VSI w/ an associated netdev is set up w/ NAPI */
3475 if (vsi->netdev)
3476 netif_napi_del(&q_vector->napi);
3477
3478 vsi->q_vectors[v_idx] = NULL;
3479
3480 kfree_rcu(q_vector, rcu);
3481}
3482
41c445ff
JB		 3483/**
3484 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3485 * @vsi: the VSI being un-configured
3486 *
3487 * This frees the memory allocated to the q_vectors and
3488 * deletes references to the NAPI struct.
3489 **/
3490static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3491{
3492 int v_idx;
3493
493fb300
AD		 3494 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3495 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3496}
3497
3498/**
3499 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3500 * @pf: board private structure
3501 **/
3502static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3503{
3504 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3505 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3506 pci_disable_msix(pf->pdev);
3507 kfree(pf->msix_entries);
3508 pf->msix_entries = NULL;
3509 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3510 pci_disable_msi(pf->pdev);
3511 }
3512 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3513}
3514
3515/**
3516 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3517 * @pf: board private structure
3518 *
3519 * We go through and clear interrupt specific resources and reset the structure
3520 * to pre-load conditions
3521 **/
3522static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3523{
3524 int i;
3525
3526 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3527 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3528 if (pf->vsi[i])
3529 i40e_vsi_free_q_vectors(pf->vsi[i]);
3530 i40e_reset_interrupt_capability(pf);
3531}
3532
3533/**
3534 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3535 * @vsi: the VSI being configured
3536 **/
3537static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3538{
3539 int q_idx;
3540
3541 if (!vsi->netdev)
3542 return;
3543
3544 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3545 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3546}
3547
3548/**
3549 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3550 * @vsi: the VSI being configured
3551 **/
3552static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3553{
3554 int q_idx;
3555
3556 if (!vsi->netdev)
3557 return;
3558
3559 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3560 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3561}
3562
90ef8d47
SN		 3563/**
3564 * i40e_vsi_close - Shut down a VSI
3565 * @vsi: the vsi to be quelled
3566 **/
3567static void i40e_vsi_close(struct i40e_vsi *vsi)
3568{
3569 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3570 i40e_down(vsi);
3571 i40e_vsi_free_irq(vsi);
3572 i40e_vsi_free_tx_resources(vsi);
3573 i40e_vsi_free_rx_resources(vsi);
3574}
3575
41c445ff
JB		 3576/**
3577 * i40e_quiesce_vsi - Pause a given VSI
3578 * @vsi: the VSI being paused
3579 **/
3580static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3581{
3582 if (test_bit(__I40E_DOWN, &vsi->state))
3583 return;
3584
3585 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3586 if (vsi->netdev && netif_running(vsi->netdev)) {
3587 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3588 } else {
90ef8d47 3589 i40e_vsi_close(vsi);
41c445ff
JB		 3590 }
3591}
3592
3593/**
3594 * i40e_unquiesce_vsi - Resume a given VSI
3595 * @vsi: the VSI being resumed
3596 **/
3597static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3598{
3599 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3600 return;
3601
3602 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3603 if (vsi->netdev && netif_running(vsi->netdev))
3604 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3605 else
8276f757 3606 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3607}
3608
3609/**
3610 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3611 * @pf: the PF
3612 **/
3613static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3614{
3615 int v;
3616
3617 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3618 if (pf->vsi[v])
3619 i40e_quiesce_vsi(pf->vsi[v]);
3620 }
3621}
3622
3623/**
3624 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3625 * @pf: the PF
3626 **/
3627static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3628{
3629 int v;
3630
3631 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3632 if (pf->vsi[v])
3633 i40e_unquiesce_vsi(pf->vsi[v]);
3634 }
3635}
3636
3637/**
3638 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3639 * @dcbcfg: the corresponding DCBx configuration structure
3640 *
3641 * Return the number of TCs from given DCBx configuration
3642 **/
3643static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3644{
078b5876
JB		 3645 u8 num_tc = 0;
3646 int i;
41c445ff
JB		 3647
3648 /* Scan the ETS Config Priority Table to find
3649 * traffic class enabled for a given priority
3650 * and use the traffic class index to get the
3651 * number of traffic classes enabled
3652 */
3653 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3654 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3655 num_tc = dcbcfg->etscfg.prioritytable[i];
3656 }
3657
3658 /* Traffic class index starts from zero so
3659 * increment to return the actual count
3660 */
078b5876 3661 return num_tc + 1;
41c445ff
JB		 3662}
3663
3664/**
3665 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3666 * @dcbcfg: the corresponding DCBx configuration structure
3667 *
3668 * Query the current DCB configuration and return the number of
3669 * traffic classes enabled from the given DCBX config
3670 **/
3671static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3672{
3673 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3674 u8 enabled_tc = 1;
3675 u8 i;
3676
3677 for (i = 0; i < num_tc; i++)
3678 enabled_tc |= 1 << i;
3679
3680 return enabled_tc;
3681}
3682
3683/**
3684 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3685 * @pf: PF being queried
3686 *
3687 * Return number of traffic classes enabled for the given PF
3688 **/
3689static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3690{
3691 struct i40e_hw *hw = &pf->hw;
3692 u8 i, enabled_tc;
3693 u8 num_tc = 0;
3694 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3695
3696 /* If DCB is not enabled then always in single TC */
3697 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3698 return 1;
3699
3700 /* MFP mode return count of enabled TCs for this PF */
3701 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3702 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3703 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3704 if (enabled_tc & (1 << i))
3705 num_tc++;
3706 }
3707 return num_tc;
3708 }
3709
3710 /* SFP mode will be enabled for all TCs on port */
3711 return i40e_dcb_get_num_tc(dcbcfg);
3712}
3713
3714/**
3715 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3716 * @pf: PF being queried
3717 *
3718 * Return a bitmap for first enabled traffic class for this PF.
3719 **/
3720static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3721{
3722 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3723 u8 i = 0;
3724
3725 if (!enabled_tc)
3726 return 0x1; /* TC0 */
3727
3728 /* Find the first enabled TC */
3729 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3730 if (enabled_tc & (1 << i))
3731 break;
3732 }
3733
3734 return 1 << i;
3735}
3736
3737/**
3738 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3739 * @pf: PF being queried
3740 *
3741 * Return a bitmap for enabled traffic classes for this PF.
3742 **/
3743static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3744{
3745 /* If DCB is not enabled for this PF then just return default TC */
3746 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3747 return i40e_pf_get_default_tc(pf);
3748
3749 /* MFP mode will have enabled TCs set by FW */
3750 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3751 return pf->hw.func_caps.enabled_tcmap;
3752
3753 /* SFP mode we want PF to be enabled for all TCs */
3754 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3755}
3756
3757/**
3758 * i40e_vsi_get_bw_info - Query VSI BW Information
3759 * @vsi: the VSI being queried
3760 *
3761 * Returns 0 on success, negative value on failure
3762 **/
3763static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3764{
3765 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3766 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3767 struct i40e_pf *pf = vsi->back;
3768 struct i40e_hw *hw = &pf->hw;
dcae29be 3769 i40e_status aq_ret;
41c445ff 3770 u32 tc_bw_max;
41c445ff
JB		 3771 int i;
3772
3773 /* Get the VSI level BW configuration */
dcae29be
JB		 3774 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3775 if (aq_ret) {
41c445ff
JB		 3776 dev_info(&pf->pdev->dev,
3777 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3778 aq_ret, pf->hw.aq.asq_last_status);
3779 return -EINVAL;
41c445ff
JB		 3780 }
3781
3782 /* Get the VSI level BW configuration per TC */
dcae29be 3783 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3784 NULL);
dcae29be 3785 if (aq_ret) {
41c445ff
JB		 3786 dev_info(&pf->pdev->dev,
3787 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3788 aq_ret, pf->hw.aq.asq_last_status);
3789 return -EINVAL;
41c445ff
JB		 3790 }
3791
3792 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3793 dev_info(&pf->pdev->dev,
3794 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3795 bw_config.tc_valid_bits,
3796 bw_ets_config.tc_valid_bits);
3797 /* Still continuing */
3798 }
3799
3800 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3801 vsi->bw_max_quanta = bw_config.max_bw;
3802 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3803 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3804 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3805 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3806 vsi->bw_ets_limit_credits[i] =
3807 le16_to_cpu(bw_ets_config.credits[i]);
3808 /* 3 bits out of 4 for each TC */
3809 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3810 }
078b5876 3811
dcae29be 3812 return 0;
41c445ff
JB		 3813}
3814
3815/**
3816 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3817 * @vsi: the VSI being configured
3818 * @enabled_tc: TC bitmap
3819 * @bw_credits: BW shared credits per TC
3820 *
3821 * Returns 0 on success, negative value on failure
3822 **/
dcae29be 3823static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3824 u8 *bw_share)
3825{
3826 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3827 i40e_status aq_ret;
3828 int i;
41c445ff
JB		 3829
3830 bw_data.tc_valid_bits = enabled_tc;
3831 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3832 bw_data.tc_bw_credits[i] = bw_share[i];
3833
dcae29be
JB		 3834 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3835 NULL);
3836 if (aq_ret) {
41c445ff 3837 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3838 "AQ command Config VSI BW allocation per TC failed = %d\n",
3839 vsi->back->hw.aq.asq_last_status);
dcae29be 3840 return -EINVAL;
41c445ff
JB		 3841 }
3842
3843 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3844 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3845
dcae29be 3846 return 0;
41c445ff
JB		 3847}
3848
3849/**
3850 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3851 * @vsi: the VSI being configured
3852 * @enabled_tc: TC map to be enabled
3853 *
3854 **/
3855static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3856{
3857 struct net_device *netdev = vsi->netdev;
3858 struct i40e_pf *pf = vsi->back;
3859 struct i40e_hw *hw = &pf->hw;
3860 u8 netdev_tc = 0;
3861 int i;
3862 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3863
3864 if (!netdev)
3865 return;
3866
3867 if (!enabled_tc) {
3868 netdev_reset_tc(netdev);
3869 return;
3870 }
3871
3872 /* Set up actual enabled TCs on the VSI */
3873 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3874 return;
3875
3876 /* set per TC queues for the VSI */
3877 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3878 /* Only set TC queues for enabled tcs
3879 *
3880 * e.g. For a VSI that has TC0 and TC3 enabled the
3881 * enabled_tc bitmap would be 0x00001001; the driver
3882 * will set the numtc for netdev as 2 that will be
3883 * referenced by the netdev layer as TC 0 and 1.
3884 */
3885 if (vsi->tc_config.enabled_tc & (1 << i))
3886 netdev_set_tc_queue(netdev,
3887 vsi->tc_config.tc_info[i].netdev_tc,
3888 vsi->tc_config.tc_info[i].qcount,
3889 vsi->tc_config.tc_info[i].qoffset);
3890 }
3891
3892 /* Assign UP2TC map for the VSI */
3893 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3894 /* Get the actual TC# for the UP */
3895 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3896 /* Get the mapped netdev TC# for the UP */
3897 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3898 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3899 }
3900}
3901
3902/**
3903 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3904 * @vsi: the VSI being configured
3905 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3906 **/
3907static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3908 struct i40e_vsi_context *ctxt)
3909{
3910 /* copy just the sections touched not the entire info
3911 * since not all sections are valid as returned by
3912 * update vsi params
3913 */
3914 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3915 memcpy(&vsi->info.queue_mapping,
3916 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3917 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3918 sizeof(vsi->info.tc_mapping));
3919}
3920
3921/**
3922 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3923 * @vsi: VSI to be configured
3924 * @enabled_tc: TC bitmap
3925 *
3926 * This configures a particular VSI for TCs that are mapped to the
3927 * given TC bitmap. It uses default bandwidth share for TCs across
3928 * VSIs to configure TC for a particular VSI.
3929 *
3930 * NOTE:
3931 * It is expected that the VSI queues have been quisced before calling
3932 * this function.
3933 **/
3934static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3935{
3936 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3937 struct i40e_vsi_context ctxt;
3938 int ret = 0;
3939 int i;
3940
3941 /* Check if enabled_tc is same as existing or new TCs */
3942 if (vsi->tc_config.enabled_tc == enabled_tc)
3943 return ret;
3944
3945 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3946 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3947 if (enabled_tc & (1 << i))
3948 bw_share[i] = 1;
3949 }
3950
3951 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3952 if (ret) {
3953 dev_info(&vsi->back->pdev->dev,
3954 "Failed configuring TC map %d for VSI %d\n",
3955 enabled_tc, vsi->seid);
3956 goto out;
3957 }
3958
3959 /* Update Queue Pairs Mapping for currently enabled UPs */
3960 ctxt.seid = vsi->seid;
3961 ctxt.pf_num = vsi->back->hw.pf_id;
3962 ctxt.vf_num = 0;
3963 ctxt.uplink_seid = vsi->uplink_seid;
3964 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3965 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3966
3967 /* Update the VSI after updating the VSI queue-mapping information */
3968 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3969 if (ret) {
3970 dev_info(&vsi->back->pdev->dev,
3971 "update vsi failed, aq_err=%d\n",
3972 vsi->back->hw.aq.asq_last_status);
3973 goto out;
3974 }
3975 /* update the local VSI info with updated queue map */
3976 i40e_vsi_update_queue_map(vsi, &ctxt);
3977 vsi->info.valid_sections = 0;
3978
3979 /* Update current VSI BW information */
3980 ret = i40e_vsi_get_bw_info(vsi);
3981 if (ret) {
3982 dev_info(&vsi->back->pdev->dev,
3983 "Failed updating vsi bw info, aq_err=%d\n",
3984 vsi->back->hw.aq.asq_last_status);
3985 goto out;
3986 }
3987
3988 /* Update the netdev TC setup */
3989 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3990out:
3991 return ret;
3992}
3993
4e3b35b0
NP		 3994/**
3995 * i40e_veb_config_tc - Configure TCs for given VEB
3996 * @veb: given VEB
3997 * @enabled_tc: TC bitmap
3998 *
3999 * Configures given TC bitmap for VEB (switching) element
4000 **/
4001int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4002{
4003 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4004 struct i40e_pf *pf = veb->pf;
4005 int ret = 0;
4006 int i;
4007
4008 /* No TCs or already enabled TCs just return */
4009 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4010 return ret;
4011
4012 bw_data.tc_valid_bits = enabled_tc;
4013 /* bw_data.absolute_credits is not set (relative) */
4014
4015 /* Enable ETS TCs with equal BW Share for now */
4016 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4017 if (enabled_tc & (1 << i))
4018 bw_data.tc_bw_share_credits[i] = 1;
4019 }
4020
4021 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4022 &bw_data, NULL);
4023 if (ret) {
4024 dev_info(&pf->pdev->dev,
4025 "veb bw config failed, aq_err=%d\n",
4026 pf->hw.aq.asq_last_status);
4027 goto out;
4028 }
4029
4030 /* Update the BW information */
4031 ret = i40e_veb_get_bw_info(veb);
4032 if (ret) {
4033 dev_info(&pf->pdev->dev,
4034 "Failed getting veb bw config, aq_err=%d\n",
4035 pf->hw.aq.asq_last_status);
4036 }
4037
4038out:
4039 return ret;
4040}
4041
4042#ifdef CONFIG_I40E_DCB
4043/**
4044 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4045 * @pf: PF struct
4046 *
4047 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4048 * the caller would've quiesce all the VSIs before calling
4049 * this function
4050 **/
4051static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4052{
4053 u8 tc_map = 0;
4054 int ret;
4055 u8 v;
4056
4057 /* Enable the TCs available on PF to all VEBs */
4058 tc_map = i40e_pf_get_tc_map(pf);
4059 for (v = 0; v < I40E_MAX_VEB; v++) {
4060 if (!pf->veb[v])
4061 continue;
4062 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4063 if (ret) {
4064 dev_info(&pf->pdev->dev,
4065 "Failed configuring TC for VEB seid=%d\n",
4066 pf->veb[v]->seid);
4067 /* Will try to configure as many components */
4068 }
4069 }
4070
4071 /* Update each VSI */
4072 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4073 if (!pf->vsi[v])
4074 continue;
4075
4076 /* - Enable all TCs for the LAN VSI
4077 * - For all others keep them at TC0 for now
4078 */
4079 if (v == pf->lan_vsi)
4080 tc_map = i40e_pf_get_tc_map(pf);
4081 else
4082 tc_map = i40e_pf_get_default_tc(pf);
4083
4084 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4085 if (ret) {
4086 dev_info(&pf->pdev->dev,
4087 "Failed configuring TC for VSI seid=%d\n",
4088 pf->vsi[v]->seid);
4089 /* Will try to configure as many components */
4090 } else {
0672a091
NP		 4091 /* Re-configure VSI vectors based on updated TC map */
4092 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4093 if (pf->vsi[v]->netdev)
4094 i40e_dcbnl_set_all(pf->vsi[v]);
4095 }
4096 }
4097}
4098
4099/**
4100 * i40e_init_pf_dcb - Initialize DCB configuration
4101 * @pf: PF being configured
4102 *
4103 * Query the current DCB configuration and cache it
4104 * in the hardware structure
4105 **/
4106static int i40e_init_pf_dcb(struct i40e_pf *pf)
4107{
4108 struct i40e_hw *hw = &pf->hw;
4109 int err = 0;
4110
4111 if (pf->hw.func_caps.npar_enable)
4112 goto out;
4113
4114 /* Get the initial DCB configuration */
4115 err = i40e_init_dcb(hw);
4116 if (!err) {
4117 /* Device/Function is not DCBX capable */
4118 if ((!hw->func_caps.dcb) ||
4119 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4120 dev_info(&pf->pdev->dev,
4121 "DCBX offload is not supported or is disabled for this PF.\n");
4122
4123 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4124 goto out;
4125
4126 } else {
4127 /* When status is not DISABLED then DCBX in FW */
4128 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4129 DCB_CAP_DCBX_VER_IEEE;
4130 pf->flags |= I40E_FLAG_DCB_ENABLED;
4131 }
014269ff
NP		 4132 } else {
4133 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4134 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4135 }
4136
4137out:
4138 return err;
4139}
4140#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4141#define SPEED_SIZE 14
4142#define FC_SIZE 8
4143/**
4144 * i40e_print_link_message - print link up or down
4145 * @vsi: the VSI for which link needs a message
4146 */
4147static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4148{
4149 char speed[SPEED_SIZE] = "Unknown";
4150 char fc[FC_SIZE] = "RX/TX";
4151
4152 if (!isup) {
4153 netdev_info(vsi->netdev, "NIC Link is Down\n");
4154 return;
4155 }
4156
4157 switch (vsi->back->hw.phy.link_info.link_speed) {
4158 case I40E_LINK_SPEED_40GB:
4159 strncpy(speed, "40 Gbps", SPEED_SIZE);
4160 break;
4161 case I40E_LINK_SPEED_10GB:
4162 strncpy(speed, "10 Gbps", SPEED_SIZE);
4163 break;
4164 case I40E_LINK_SPEED_1GB:
4165 strncpy(speed, "1000 Mbps", SPEED_SIZE);
4166 break;
4167 default:
4168 break;
4169 }
4170
4171 switch (vsi->back->hw.fc.current_mode) {
4172 case I40E_FC_FULL:
4173 strncpy(fc, "RX/TX", FC_SIZE);
4174 break;
4175 case I40E_FC_TX_PAUSE:
4176 strncpy(fc, "TX", FC_SIZE);
4177 break;
4178 case I40E_FC_RX_PAUSE:
4179 strncpy(fc, "RX", FC_SIZE);
4180 break;
4181 default:
4182 strncpy(fc, "None", FC_SIZE);
4183 break;
4184 }
4185
4186 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4187 speed, fc);
4188}
4e3b35b0 4189
41c445ff
JB		 4190/**
4191 * i40e_up_complete - Finish the last steps of bringing up a connection
4192 * @vsi: the VSI being configured
4193 **/
4194static int i40e_up_complete(struct i40e_vsi *vsi)
4195{
4196 struct i40e_pf *pf = vsi->back;
4197 int err;
4198
4199 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4200 i40e_vsi_configure_msix(vsi);
4201 else
4202 i40e_configure_msi_and_legacy(vsi);
4203
4204 /* start rings */
4205 err = i40e_vsi_control_rings(vsi, true);
4206 if (err)
4207 return err;
4208
4209 clear_bit(__I40E_DOWN, &vsi->state);
4210 i40e_napi_enable_all(vsi);
4211 i40e_vsi_enable_irq(vsi);
4212
4213 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4214 (vsi->netdev)) {
cf05ed08 4215 i40e_print_link_message(vsi, true);
41c445ff
JB		 4216 netif_tx_start_all_queues(vsi->netdev);
4217 netif_carrier_on(vsi->netdev);
6d779b41 4218 } else if (vsi->netdev) {
cf05ed08 4219 i40e_print_link_message(vsi, false);
41c445ff 4220 }
ca64fa4e
ASJ		 4221
4222 /* replay FDIR SB filters */
4223 if (vsi->type == I40E_VSI_FDIR)
4224 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4225 i40e_service_event_schedule(pf);
4226
4227 return 0;
4228}
4229
4230/**
4231 * i40e_vsi_reinit_locked - Reset the VSI
4232 * @vsi: the VSI being configured
4233 *
4234 * Rebuild the ring structs after some configuration
4235 * has changed, e.g. MTU size.
4236 **/
4237static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4238{
4239 struct i40e_pf *pf = vsi->back;
4240
4241 WARN_ON(in_interrupt());
4242 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4243 usleep_range(1000, 2000);
4244 i40e_down(vsi);
4245
4246 /* Give a VF some time to respond to the reset. The
4247 * two second wait is based upon the watchdog cycle in
4248 * the VF driver.
4249 */
4250 if (vsi->type == I40E_VSI_SRIOV)
4251 msleep(2000);
4252 i40e_up(vsi);
4253 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4254}
4255
4256/**
4257 * i40e_up - Bring the connection back up after being down
4258 * @vsi: the VSI being configured
4259 **/
4260int i40e_up(struct i40e_vsi *vsi)
4261{
4262 int err;
4263
4264 err = i40e_vsi_configure(vsi);
4265 if (!err)
4266 err = i40e_up_complete(vsi);
4267
4268 return err;
4269}
4270
4271/**
4272 * i40e_down - Shutdown the connection processing
4273 * @vsi: the VSI being stopped
4274 **/
4275void i40e_down(struct i40e_vsi *vsi)
4276{
4277 int i;
4278
4279 /* It is assumed that the caller of this function
4280 * sets the vsi->state __I40E_DOWN bit.
4281 */
4282 if (vsi->netdev) {
4283 netif_carrier_off(vsi->netdev);
4284 netif_tx_disable(vsi->netdev);
4285 }
4286 i40e_vsi_disable_irq(vsi);
4287 i40e_vsi_control_rings(vsi, false);
4288 i40e_napi_disable_all(vsi);
4289
4290 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4291 i40e_clean_tx_ring(vsi->tx_rings[i]);
4292 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4293 }
4294}
4295
4296/**
4297 * i40e_setup_tc - configure multiple traffic classes
4298 * @netdev: net device to configure
4299 * @tc: number of traffic classes to enable
4300 **/
4301static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4302{
4303 struct i40e_netdev_priv *np = netdev_priv(netdev);
4304 struct i40e_vsi *vsi = np->vsi;
4305 struct i40e_pf *pf = vsi->back;
4306 u8 enabled_tc = 0;
4307 int ret = -EINVAL;
4308 int i;
4309
4310 /* Check if DCB enabled to continue */
4311 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4312 netdev_info(netdev, "DCB is not enabled for adapter\n");
4313 goto exit;
4314 }
4315
4316 /* Check if MFP enabled */
4317 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4318 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4319 goto exit;
4320 }
4321
4322 /* Check whether tc count is within enabled limit */
4323 if (tc > i40e_pf_get_num_tc(pf)) {
4324 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4325 goto exit;
4326 }
4327
4328 /* Generate TC map for number of tc requested */
4329 for (i = 0; i < tc; i++)
4330 enabled_tc |= (1 << i);
4331
4332 /* Requesting same TC configuration as already enabled */
4333 if (enabled_tc == vsi->tc_config.enabled_tc)
4334 return 0;
4335
4336 /* Quiesce VSI queues */
4337 i40e_quiesce_vsi(vsi);
4338
4339 /* Configure VSI for enabled TCs */
4340 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4341 if (ret) {
4342 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4343 vsi->seid);
4344 goto exit;
4345 }
4346
4347 /* Unquiesce VSI */
4348 i40e_unquiesce_vsi(vsi);
4349
4350exit:
4351 return ret;
4352}
4353
4354/**
4355 * i40e_open - Called when a network interface is made active
4356 * @netdev: network interface device structure
4357 *
4358 * The open entry point is called when a network interface is made
4359 * active by the system (IFF_UP). At this point all resources needed
4360 * for transmit and receive operations are allocated, the interrupt
4361 * handler is registered with the OS, the netdev watchdog subtask is
4362 * enabled, and the stack is notified that the interface is ready.
4363 *
4364 * Returns 0 on success, negative value on failure
4365 **/
4366static int i40e_open(struct net_device *netdev)
4367{
4368 struct i40e_netdev_priv *np = netdev_priv(netdev);
4369 struct i40e_vsi *vsi = np->vsi;
4370 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4371 int err;
4372
4eb3f768
SN		 4373 /* disallow open during test or if eeprom is broken */
4374 if (test_bit(__I40E_TESTING, &pf->state) ||
4375 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4376 return -EBUSY;
4377
4378 netif_carrier_off(netdev);
4379
6c167f58
EK		 4380 err = i40e_vsi_open(vsi);
4381 if (err)
4382 return err;
4383
059dab69
JB		 4384 /* configure global TSO hardware offload settings */
4385 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4386 TCP_FLAG_FIN) >> 16);
4387 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4388 TCP_FLAG_FIN |
4389 TCP_FLAG_CWR) >> 16);
4390 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4391
6c167f58
EK		 4392#ifdef CONFIG_I40E_VXLAN
4393 vxlan_get_rx_port(netdev);
4394#endif
4395
4396 return 0;
4397}
4398
4399/**
4400 * i40e_vsi_open -
4401 * @vsi: the VSI to open
4402 *
4403 * Finish initialization of the VSI.
4404 *
4405 * Returns 0 on success, negative value on failure
4406 **/
4407int i40e_vsi_open(struct i40e_vsi *vsi)
4408{
4409 struct i40e_pf *pf = vsi->back;
4410 char int_name[IFNAMSIZ];
4411 int err;
4412
41c445ff
JB		 4413 /* allocate descriptors */
4414 err = i40e_vsi_setup_tx_resources(vsi);
4415 if (err)
4416 goto err_setup_tx;
4417 err = i40e_vsi_setup_rx_resources(vsi);
4418 if (err)
4419 goto err_setup_rx;
4420
4421 err = i40e_vsi_configure(vsi);
4422 if (err)
4423 goto err_setup_rx;
4424
c22e3c6c
SN		 4425 if (vsi->netdev) {
4426 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4427 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4428 err = i40e_vsi_request_irq(vsi, int_name);
4429 if (err)
4430 goto err_setup_rx;
4431
4432 /* Notify the stack of the actual queue counts. */
4433 err = netif_set_real_num_tx_queues(vsi->netdev,
4434 vsi->num_queue_pairs);
4435 if (err)
4436 goto err_set_queues;
4437
4438 err = netif_set_real_num_rx_queues(vsi->netdev,
4439 vsi->num_queue_pairs);
4440 if (err)
4441 goto err_set_queues;
8a9eb7d3
SN		 4442
4443 } else if (vsi->type == I40E_VSI_FDIR) {
4444 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4445 dev_driver_string(&pf->pdev->dev));
4446 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4447 } else {
ce9ccb17 4448 err = -EINVAL;
6c167f58
EK		 4449 goto err_setup_rx;
4450 }
25946ddb 4451
41c445ff
JB		 4452 err = i40e_up_complete(vsi);
4453 if (err)
4454 goto err_up_complete;
4455
41c445ff
JB		 4456 return 0;
4457
4458err_up_complete:
4459 i40e_down(vsi);
25946ddb 4460err_set_queues:
41c445ff
JB		 4461 i40e_vsi_free_irq(vsi);
4462err_setup_rx:
4463 i40e_vsi_free_rx_resources(vsi);
4464err_setup_tx:
4465 i40e_vsi_free_tx_resources(vsi);
4466 if (vsi == pf->vsi[pf->lan_vsi])
4467 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4468
4469 return err;
4470}
4471
17a73f6b
JG		 4472/**
4473 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4474 * @pf: Pointer to pf
4475 *
4476 * This function destroys the hlist where all the Flow Director
4477 * filters were saved.
4478 **/
4479static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4480{
4481 struct i40e_fdir_filter *filter;
4482 struct hlist_node *node2;
4483
4484 hlist_for_each_entry_safe(filter, node2,
4485 &pf->fdir_filter_list, fdir_node) {
4486 hlist_del(&filter->fdir_node);
4487 kfree(filter);
4488 }
4489 pf->fdir_pf_active_filters = 0;
4490}
4491
41c445ff
JB		 4492/**
4493 * i40e_close - Disables a network interface
4494 * @netdev: network interface device structure
4495 *
4496 * The close entry point is called when an interface is de-activated
4497 * by the OS. The hardware is still under the driver's control, but
4498 * this netdev interface is disabled.
4499 *
4500 * Returns 0, this is not allowed to fail
4501 **/
4502static int i40e_close(struct net_device *netdev)
4503{
4504 struct i40e_netdev_priv *np = netdev_priv(netdev);
4505 struct i40e_vsi *vsi = np->vsi;
4506
90ef8d47 4507 i40e_vsi_close(vsi);
41c445ff
JB		 4508
4509 return 0;
4510}
4511
4512/**
4513 * i40e_do_reset - Start a PF or Core Reset sequence
4514 * @pf: board private structure
4515 * @reset_flags: which reset is requested
4516 *
4517 * The essential difference in resets is that the PF Reset
4518 * doesn't clear the packet buffers, doesn't reset the PE
4519 * firmware, and doesn't bother the other PFs on the chip.
4520 **/
4521void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4522{
4523 u32 val;
4524
4525 WARN_ON(in_interrupt());
4526
263fc48f
MW		 4527 if (i40e_check_asq_alive(&pf->hw))
4528 i40e_vc_notify_reset(pf);
4529
41c445ff
JB		 4530 /* do the biggest reset indicated */
4531 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4532
4533 /* Request a Global Reset
4534 *
4535 * This will start the chip's countdown to the actual full
4536 * chip reset event, and a warning interrupt to be sent
4537 * to all PFs, including the requestor. Our handler
4538 * for the warning interrupt will deal with the shutdown
4539 * and recovery of the switch setup.
4540 */
69bfb110 4541 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4542 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4543 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4544 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4545
4546 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4547
4548 /* Request a Core Reset
4549 *
4550 * Same as Global Reset, except does *not* include the MAC/PHY
4551 */
69bfb110 4552 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4553 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4554 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4555 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4556 i40e_flush(&pf->hw);
4557
7823fe34
SN		 4558 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4559
4560 /* Request a Firmware Reset
4561 *
4562 * Same as Global reset, plus restarting the
4563 * embedded firmware engine.
4564 */
4565 /* enable EMP Reset */
4566 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4567 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4568 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4569
4570 /* force the reset */
4571 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4572 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4573 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4574 i40e_flush(&pf->hw);
4575
41c445ff
JB		 4576 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4577
4578 /* Request a PF Reset
4579 *
4580 * Resets only the PF-specific registers
4581 *
4582 * This goes directly to the tear-down and rebuild of
4583 * the switch, since we need to do all the recovery as
4584 * for the Core Reset.
4585 */
69bfb110 4586 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4587 i40e_handle_reset_warning(pf);
4588
4589 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4590 int v;
4591
4592 /* Find the VSI(s) that requested a re-init */
4593 dev_info(&pf->pdev->dev,
4594 "VSI reinit requested\n");
4595 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4596 struct i40e_vsi *vsi = pf->vsi[v];
4597 if (vsi != NULL &&
4598 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4599 i40e_vsi_reinit_locked(pf->vsi[v]);
4600 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4601 }
4602 }
4603
4604 /* no further action needed, so return now */
4605 return;
4606 } else {
4607 dev_info(&pf->pdev->dev,
4608 "bad reset request 0x%08x\n", reset_flags);
4609 return;
4610 }
4611}
4612
4e3b35b0
NP		 4613#ifdef CONFIG_I40E_DCB
4614/**
4615 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4616 * @pf: board private structure
4617 * @old_cfg: current DCB config
4618 * @new_cfg: new DCB config
4619 **/
4620bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4621 struct i40e_dcbx_config *old_cfg,
4622 struct i40e_dcbx_config *new_cfg)
4623{
4624 bool need_reconfig = false;
4625
4626 /* Check if ETS configuration has changed */
4627 if (memcmp(&new_cfg->etscfg,
4628 &old_cfg->etscfg,
4629 sizeof(new_cfg->etscfg))) {
4630 /* If Priority Table has changed reconfig is needed */
4631 if (memcmp(&new_cfg->etscfg.prioritytable,
4632 &old_cfg->etscfg.prioritytable,
4633 sizeof(new_cfg->etscfg.prioritytable))) {
4634 need_reconfig = true;
69bfb110 4635 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4636 }
4637
4638 if (memcmp(&new_cfg->etscfg.tcbwtable,
4639 &old_cfg->etscfg.tcbwtable,
4640 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4641 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4642
4643 if (memcmp(&new_cfg->etscfg.tsatable,
4644 &old_cfg->etscfg.tsatable,
4645 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4646 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4647 }
4648
4649 /* Check if PFC configuration has changed */
4650 if (memcmp(&new_cfg->pfc,
4651 &old_cfg->pfc,
4652 sizeof(new_cfg->pfc))) {
4653 need_reconfig = true;
69bfb110 4654 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4655 }
4656
4657 /* Check if APP Table has changed */
4658 if (memcmp(&new_cfg->app,
4659 &old_cfg->app,
3d9667a9 4660 sizeof(new_cfg->app))) {
4e3b35b0 4661 need_reconfig = true;
69bfb110 4662 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4663 }
4e3b35b0
NP		 4664
4665 return need_reconfig;
4666}
4667
4668/**
4669 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4670 * @pf: board private structure
4671 * @e: event info posted on ARQ
4672 **/
4673static int i40e_handle_lldp_event(struct i40e_pf *pf,
4674 struct i40e_arq_event_info *e)
4675{
4676 struct i40e_aqc_lldp_get_mib *mib =
4677 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4678 struct i40e_hw *hw = &pf->hw;
4679 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4680 struct i40e_dcbx_config tmp_dcbx_cfg;
4681 bool need_reconfig = false;
4682 int ret = 0;
4683 u8 type;
4684
4685 /* Ignore if event is not for Nearest Bridge */
4686 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4687 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4688 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4689 return ret;
4690
4691 /* Check MIB Type and return if event for Remote MIB update */
4692 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4693 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4694 /* Update the remote cached instance and return */
4695 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4696 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4697 &hw->remote_dcbx_config);
4698 goto exit;
4699 }
4700
4701 /* Convert/store the DCBX data from LLDPDU temporarily */
4702 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4703 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4704 if (ret) {
4705 /* Error in LLDPDU parsing return */
4706 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4707 goto exit;
4708 }
4709
4710 /* No change detected in DCBX configs */
4711 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4712 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4713 goto exit;
4714 }
4715
4716 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4717
4718 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4719
4720 /* Overwrite the new configuration */
4721 *dcbx_cfg = tmp_dcbx_cfg;
4722
4723 if (!need_reconfig)
4724 goto exit;
4725
4726 /* Reconfiguration needed quiesce all VSIs */
4727 i40e_pf_quiesce_all_vsi(pf);
4728
4729 /* Changes in configuration update VEB/VSI */
4730 i40e_dcb_reconfigure(pf);
4731
4732 i40e_pf_unquiesce_all_vsi(pf);
4733exit:
4734 return ret;
4735}
4736#endif /* CONFIG_I40E_DCB */
4737
23326186
ASJ		 4738/**
4739 * i40e_do_reset_safe - Protected reset path for userland calls.
4740 * @pf: board private structure
4741 * @reset_flags: which reset is requested
4742 *
4743 **/
4744void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4745{
4746 rtnl_lock();
4747 i40e_do_reset(pf, reset_flags);
4748 rtnl_unlock();
4749}
4750
41c445ff
JB		 4751/**
4752 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4753 * @pf: board private structure
4754 * @e: event info posted on ARQ
4755 *
4756 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4757 * and VF queues
4758 **/
4759static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4760 struct i40e_arq_event_info *e)
4761{
4762 struct i40e_aqc_lan_overflow *data =
4763 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4764 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4765 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4766 struct i40e_hw *hw = &pf->hw;
4767 struct i40e_vf *vf;
4768 u16 vf_id;
4769
69bfb110
JB		 4770 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4771 queue, qtx_ctl);
41c445ff
JB		 4772
4773 /* Queue belongs to VF, find the VF and issue VF reset */
4774 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4775 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4776 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4777 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4778 vf_id -= hw->func_caps.vf_base_id;
4779 vf = &pf->vf[vf_id];
4780 i40e_vc_notify_vf_reset(vf);
4781 /* Allow VF to process pending reset notification */
4782 msleep(20);
4783 i40e_reset_vf(vf, false);
4784 }
4785}
4786
4787/**
4788 * i40e_service_event_complete - Finish up the service event
4789 * @pf: board private structure
4790 **/
4791static void i40e_service_event_complete(struct i40e_pf *pf)
4792{
4793 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4794
4795 /* flush memory to make sure state is correct before next watchog */
4796 smp_mb__before_clear_bit();
4797 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4798}
4799
55a5e60b
ASJ		 4800/**
4801 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4802 * @pf: board private structure
4803 **/
4804int i40e_get_current_fd_count(struct i40e_pf *pf)
4805{
4806 int val, fcnt_prog;
4807 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4808 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4809 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4810 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4811 return fcnt_prog;
4812}
4813
4814/**
4815 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4816 * @pf: board private structure
4817 **/
4818void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4819{
4820 u32 fcnt_prog, fcnt_avail;
4821
4822 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4823 * to re-enable
4824 */
4825 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4826 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4827 return;
4828 fcnt_prog = i40e_get_current_fd_count(pf);
89132783 4829 fcnt_avail = i40e_get_fd_cnt_all(pf);
55a5e60b
ASJ		 4830 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4831 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4832 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4833 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4834 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4835 }
4836 }
4837 /* Wait for some more space to be available to turn on ATR */
4838 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4839 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4840 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4841 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4842 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4843 }
4844 }
4845}
4846
41c445ff
JB		 4847/**
4848 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4849 * @pf: board private structure
4850 **/
4851static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4852{
4853 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4854 return;
4855
41c445ff
JB		 4856 /* if interface is down do nothing */
4857 if (test_bit(__I40E_DOWN, &pf->state))
4858 return;
55a5e60b
ASJ		 4859 i40e_fdir_check_and_reenable(pf);
4860
4861 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4862 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4863 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4864}
4865
4866/**
4867 * i40e_vsi_link_event - notify VSI of a link event
4868 * @vsi: vsi to be notified
4869 * @link_up: link up or down
4870 **/
4871static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4872{
4873 if (!vsi)
4874 return;
4875
4876 switch (vsi->type) {
4877 case I40E_VSI_MAIN:
4878 if (!vsi->netdev || !vsi->netdev_registered)
4879 break;
4880
4881 if (link_up) {
4882 netif_carrier_on(vsi->netdev);
4883 netif_tx_wake_all_queues(vsi->netdev);
4884 } else {
4885 netif_carrier_off(vsi->netdev);
4886 netif_tx_stop_all_queues(vsi->netdev);
4887 }
4888 break;
4889
4890 case I40E_VSI_SRIOV:
4891 break;
4892
4893 case I40E_VSI_VMDQ2:
4894 case I40E_VSI_CTRL:
4895 case I40E_VSI_MIRROR:
4896 default:
4897 /* there is no notification for other VSIs */
4898 break;
4899 }
4900}
4901
4902/**
4903 * i40e_veb_link_event - notify elements on the veb of a link event
4904 * @veb: veb to be notified
4905 * @link_up: link up or down
4906 **/
4907static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4908{
4909 struct i40e_pf *pf;
4910 int i;
4911
4912 if (!veb || !veb->pf)
4913 return;
4914 pf = veb->pf;
4915
4916 /* depth first... */
4917 for (i = 0; i < I40E_MAX_VEB; i++)
4918 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4919 i40e_veb_link_event(pf->veb[i], link_up);
4920
4921 /* ... now the local VSIs */
4922 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4923 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4924 i40e_vsi_link_event(pf->vsi[i], link_up);
4925}
4926
4927/**
4928 * i40e_link_event - Update netif_carrier status
4929 * @pf: board private structure
4930 **/
4931static void i40e_link_event(struct i40e_pf *pf)
4932{
4933 bool new_link, old_link;
4934
4935 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4936 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4937
4938 if (new_link == old_link)
4939 return;
6d779b41 4940 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 4941 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 4942
4943 /* Notify the base of the switch tree connected to
4944 * the link. Floating VEBs are not notified.
4945 */
4946 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4947 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4948 else
4949 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4950
4951 if (pf->vf)
4952 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4953
4954 if (pf->flags & I40E_FLAG_PTP)
4955 i40e_ptp_set_increment(pf);
41c445ff
JB		 4956}
4957
4958/**
4959 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4960 * @pf: board private structure
4961 *
4962 * Set the per-queue flags to request a check for stuck queues in the irq
4963 * clean functions, then force interrupts to be sure the irq clean is called.
4964 **/
4965static void i40e_check_hang_subtask(struct i40e_pf *pf)
4966{
4967 int i, v;
4968
4969 /* If we're down or resetting, just bail */
4970 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4971 return;
4972
4973 /* for each VSI/netdev
4974 * for each Tx queue
4975 * set the check flag
4976 * for each q_vector
4977 * force an interrupt
4978 */
4979 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4980 struct i40e_vsi *vsi = pf->vsi[v];
4981 int armed = 0;
4982
4983 if (!pf->vsi[v] ||
4984 test_bit(__I40E_DOWN, &vsi->state) ||
4985 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4986 continue;
4987
4988 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4989 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4990 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4991 &vsi->tx_rings[i]->state))
41c445ff
JB		 4992 armed++;
4993 }
4994
4995 if (armed) {
4996 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4997 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4998 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4999 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5000 } else {
5001 u16 vec = vsi->base_vector - 1;
5002 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5003 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5004 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5005 wr32(&vsi->back->hw,
5006 I40E_PFINT_DYN_CTLN(vec), val);
5007 }
5008 i40e_flush(&vsi->back->hw);
5009 }
5010 }
5011}
5012
5013/**
5014 * i40e_watchdog_subtask - Check and bring link up
5015 * @pf: board private structure
5016 **/
5017static void i40e_watchdog_subtask(struct i40e_pf *pf)
5018{
5019 int i;
5020
5021 /* if interface is down do nothing */
5022 if (test_bit(__I40E_DOWN, &pf->state) ||
5023 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5024 return;
5025
5026 /* Update the stats for active netdevs so the network stack
5027 * can look at updated numbers whenever it cares to
5028 */
5029 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
5030 if (pf->vsi[i] && pf->vsi[i]->netdev)
5031 i40e_update_stats(pf->vsi[i]);
5032
5033 /* Update the stats for the active switching components */
5034 for (i = 0; i < I40E_MAX_VEB; i++)
5035 if (pf->veb[i])
5036 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5037
5038 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5039}
5040
5041/**
5042 * i40e_reset_subtask - Set up for resetting the device and driver
5043 * @pf: board private structure
5044 **/
5045static void i40e_reset_subtask(struct i40e_pf *pf)
5046{
5047 u32 reset_flags = 0;
5048
23326186 5049 rtnl_lock();
41c445ff
JB		 5050 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5051 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5052 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5053 }
5054 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5055 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5056 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5057 }
5058 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5059 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5060 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5061 }
5062 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5063 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5064 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5065 }
5066
5067 /* If there's a recovery already waiting, it takes
5068 * precedence before starting a new reset sequence.
5069 */
5070 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5071 i40e_handle_reset_warning(pf);
23326186 5072 goto unlock;
41c445ff
JB		 5073 }
5074
5075 /* If we're already down or resetting, just bail */
5076 if (reset_flags &&
5077 !test_bit(__I40E_DOWN, &pf->state) &&
5078 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5079 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5080
5081unlock:
5082 rtnl_unlock();
41c445ff
JB		 5083}
5084
5085/**
5086 * i40e_handle_link_event - Handle link event
5087 * @pf: board private structure
5088 * @e: event info posted on ARQ
5089 **/
5090static void i40e_handle_link_event(struct i40e_pf *pf,
5091 struct i40e_arq_event_info *e)
5092{
5093 struct i40e_hw *hw = &pf->hw;
5094 struct i40e_aqc_get_link_status *status =
5095 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5096 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5097
5098 /* save off old link status information */
5099 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5100 sizeof(pf->hw.phy.link_info_old));
5101
5102 /* update link status */
5103 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5104 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5105 hw_link_info->link_info = status->link_info;
5106 hw_link_info->an_info = status->an_info;
5107 hw_link_info->ext_info = status->ext_info;
5108 hw_link_info->lse_enable =
5109 le16_to_cpu(status->command_flags) &
5110 I40E_AQ_LSE_ENABLE;
5111
5112 /* process the event */
5113 i40e_link_event(pf);
5114
5115 /* Do a new status request to re-enable LSE reporting
5116 * and load new status information into the hw struct,
5117 * then see if the status changed while processing the
5118 * initial event.
5119 */
5120 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5121 i40e_link_event(pf);
5122}
5123
5124/**
5125 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5126 * @pf: board private structure
5127 **/
5128static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5129{
5130 struct i40e_arq_event_info event;
5131 struct i40e_hw *hw = &pf->hw;
5132 u16 pending, i = 0;
5133 i40e_status ret;
5134 u16 opcode;
86df242b 5135 u32 oldval;
41c445ff
JB		 5136 u32 val;
5137
5138 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5139 return;
5140
86df242b
SN		 5141 /* check for error indications */
5142 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5143 oldval = val;
5144 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5145 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5146 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5147 }
5148 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5149 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5150 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5151 }
5152 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5153 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5154 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5155 }
5156 if (oldval != val)
5157 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5158
5159 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5160 oldval = val;
5161 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5162 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5163 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5164 }
5165 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5166 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5167 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5168 }
5169 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5170 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5171 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5172 }
5173 if (oldval != val)
5174 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5175
3197ce22 5176 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5177 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5178 if (!event.msg_buf)
5179 return;
5180
5181 do {
2f019123 5182 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5183 ret = i40e_clean_arq_element(hw, &event, &pending);
5184 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5185 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5186 break;
5187 } else if (ret) {
5188 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5189 break;
5190 }
5191
5192 opcode = le16_to_cpu(event.desc.opcode);
5193 switch (opcode) {
5194
5195 case i40e_aqc_opc_get_link_status:
5196 i40e_handle_link_event(pf, &event);
5197 break;
5198 case i40e_aqc_opc_send_msg_to_pf:
5199 ret = i40e_vc_process_vf_msg(pf,
5200 le16_to_cpu(event.desc.retval),
5201 le32_to_cpu(event.desc.cookie_high),
5202 le32_to_cpu(event.desc.cookie_low),
5203 event.msg_buf,
5204 event.msg_size);
5205 break;
5206 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5207 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5208#ifdef CONFIG_I40E_DCB
5209 rtnl_lock();
5210 ret = i40e_handle_lldp_event(pf, &event);
5211 rtnl_unlock();
5212#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5213 break;
5214 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5215 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5216 i40e_handle_lan_overflow_event(pf, &event);
5217 break;
0467bc91
SN		 5218 case i40e_aqc_opc_send_msg_to_peer:
5219 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5220 break;
41c445ff
JB		 5221 default:
5222 dev_info(&pf->pdev->dev,
0467bc91
SN		 5223 "ARQ Error: Unknown event 0x%04x received\n",
5224 opcode);
41c445ff
JB		 5225 break;
5226 }
5227 } while (pending && (i++ < pf->adminq_work_limit));
5228
5229 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5230 /* re-enable Admin queue interrupt cause */
5231 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5232 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5233 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5234 i40e_flush(hw);
5235
5236 kfree(event.msg_buf);
5237}
5238
4eb3f768
SN		 5239/**
5240 * i40e_verify_eeprom - make sure eeprom is good to use
5241 * @pf: board private structure
5242 **/
5243static void i40e_verify_eeprom(struct i40e_pf *pf)
5244{
5245 int err;
5246
5247 err = i40e_diag_eeprom_test(&pf->hw);
5248 if (err) {
5249 /* retry in case of garbage read */
5250 err = i40e_diag_eeprom_test(&pf->hw);
5251 if (err) {
5252 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5253 err);
5254 set_bit(__I40E_BAD_EEPROM, &pf->state);
5255 }
5256 }
5257
5258 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5259 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5260 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5261 }
5262}
5263
41c445ff
JB		 5264/**
5265 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5266 * @veb: pointer to the VEB instance
5267 *
5268 * This is a recursive function that first builds the attached VSIs then
5269 * recurses in to build the next layer of VEB. We track the connections
5270 * through our own index numbers because the seid's from the HW could
5271 * change across the reset.
5272 **/
5273static int i40e_reconstitute_veb(struct i40e_veb *veb)
5274{
5275 struct i40e_vsi *ctl_vsi = NULL;
5276 struct i40e_pf *pf = veb->pf;
5277 int v, veb_idx;
5278 int ret;
5279
5280 /* build VSI that owns this VEB, temporarily attached to base VEB */
5281 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5282 if (pf->vsi[v] &&
5283 pf->vsi[v]->veb_idx == veb->idx &&
5284 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5285 ctl_vsi = pf->vsi[v];
5286 break;
5287 }
5288 }
5289 if (!ctl_vsi) {
5290 dev_info(&pf->pdev->dev,
5291 "missing owner VSI for veb_idx %d\n", veb->idx);
5292 ret = -ENOENT;
5293 goto end_reconstitute;
5294 }
5295 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5296 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5297 ret = i40e_add_vsi(ctl_vsi);
5298 if (ret) {
5299 dev_info(&pf->pdev->dev,
5300 "rebuild of owner VSI failed: %d\n", ret);
5301 goto end_reconstitute;
5302 }
5303 i40e_vsi_reset_stats(ctl_vsi);
5304
5305 /* create the VEB in the switch and move the VSI onto the VEB */
5306 ret = i40e_add_veb(veb, ctl_vsi);
5307 if (ret)
5308 goto end_reconstitute;
5309
5310 /* create the remaining VSIs attached to this VEB */
5311 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5312 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5313 continue;
5314
5315 if (pf->vsi[v]->veb_idx == veb->idx) {
5316 struct i40e_vsi *vsi = pf->vsi[v];
5317 vsi->uplink_seid = veb->seid;
5318 ret = i40e_add_vsi(vsi);
5319 if (ret) {
5320 dev_info(&pf->pdev->dev,
5321 "rebuild of vsi_idx %d failed: %d\n",
5322 v, ret);
5323 goto end_reconstitute;
5324 }
5325 i40e_vsi_reset_stats(vsi);
5326 }
5327 }
5328
5329 /* create any VEBs attached to this VEB - RECURSION */
5330 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5331 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5332 pf->veb[veb_idx]->uplink_seid = veb->seid;
5333 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5334 if (ret)
5335 break;
5336 }
5337 }
5338
5339end_reconstitute:
5340 return ret;
5341}
5342
5343/**
5344 * i40e_get_capabilities - get info about the HW
5345 * @pf: the PF struct
5346 **/
5347static int i40e_get_capabilities(struct i40e_pf *pf)
5348{
5349 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5350 u16 data_size;
5351 int buf_len;
5352 int err;
5353
5354 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5355 do {
5356 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5357 if (!cap_buf)
5358 return -ENOMEM;
5359
5360 /* this loads the data into the hw struct for us */
5361 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5362 &data_size,
5363 i40e_aqc_opc_list_func_capabilities,
5364 NULL);
5365 /* data loaded, buffer no longer needed */
5366 kfree(cap_buf);
5367
5368 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5369 /* retry with a larger buffer */
5370 buf_len = data_size;
5371 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5372 dev_info(&pf->pdev->dev,
5373 "capability discovery failed: aq=%d\n",
5374 pf->hw.aq.asq_last_status);
5375 return -ENODEV;
5376 }
5377 } while (err);
5378
ac71b7ba
ASJ		 5379 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5380 (pf->hw.aq.fw_maj_ver < 2)) {
5381 pf->hw.func_caps.num_msix_vectors++;
5382 pf->hw.func_caps.num_msix_vectors_vf++;
5383 }
5384
41c445ff
JB		 5385 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5386 dev_info(&pf->pdev->dev,
5387 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5388 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5389 pf->hw.func_caps.num_msix_vectors,
5390 pf->hw.func_caps.num_msix_vectors_vf,
5391 pf->hw.func_caps.fd_filters_guaranteed,
5392 pf->hw.func_caps.fd_filters_best_effort,
5393 pf->hw.func_caps.num_tx_qp,
5394 pf->hw.func_caps.num_vsis);
5395
7134f9ce
JB		 5396#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5397 + pf->hw.func_caps.num_vfs)
5398 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5399 dev_info(&pf->pdev->dev,
5400 "got num_vsis %d, setting num_vsis to %d\n",
5401 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5402 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5403 }
5404
41c445ff
JB		 5405 return 0;
5406}
5407
cbf61325
ASJ		 5408static int i40e_vsi_clear(struct i40e_vsi *vsi);
5409
41c445ff 5410/**
cbf61325 5411 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5412 * @pf: board private structure
5413 **/
cbf61325 5414static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5415{
5416 struct i40e_vsi *vsi;
8a9eb7d3 5417 int i;
41c445ff 5418
cbf61325 5419 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5420 return;
5421
cbf61325 5422 /* find existing VSI and see if it needs configuring */
41c445ff 5423 vsi = NULL;
cbf61325
ASJ		 5424 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5425 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5426 vsi = pf->vsi[i];
cbf61325
ASJ		 5427 break;
5428 }
5429 }
5430
5431 /* create a new VSI if none exists */
41c445ff 5432 if (!vsi) {
cbf61325
ASJ		 5433 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5434 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5435 if (!vsi) {
5436 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5437 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5438 return;
41c445ff 5439 }
41c445ff 5440 }
cbf61325 5441
8a9eb7d3 5442 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5443}
5444
5445/**
5446 * i40e_fdir_teardown - release the Flow Director resources
5447 * @pf: board private structure
5448 **/
5449static void i40e_fdir_teardown(struct i40e_pf *pf)
5450{
5451 int i;
5452
17a73f6b 5453 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5454 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5455 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5456 i40e_vsi_release(pf->vsi[i]);
5457 break;
5458 }
5459 }
5460}
5461
5462/**
f650a38b 5463 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5464 * @pf: board private structure
5465 *
f650a38b
ASJ		 5466 * Close up the VFs and other things in prep for pf Reset.
5467 **/
5468static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5469{
41c445ff 5470 struct i40e_hw *hw = &pf->hw;
60442dea 5471 i40e_status ret = 0;
41c445ff
JB		 5472 u32 v;
5473
5474 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5475 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5476 return 0;
41c445ff 5477
69bfb110 5478 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5479
41c445ff
JB		 5480 /* quiesce the VSIs and their queues that are not already DOWN */
5481 i40e_pf_quiesce_all_vsi(pf);
5482
5483 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5484 if (pf->vsi[v])
5485 pf->vsi[v]->seid = 0;
5486 }
5487
5488 i40e_shutdown_adminq(&pf->hw);
5489
f650a38b 5490 /* call shutdown HMC */
60442dea
SN		 5491 if (hw->hmc.hmc_obj) {
5492 ret = i40e_shutdown_lan_hmc(hw);
5493 if (ret) {
5494 dev_warn(&pf->pdev->dev,
5495 "shutdown_lan_hmc failed: %d\n", ret);
5496 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5497 }
f650a38b
ASJ		 5498 }
5499 return ret;
5500}
5501
44033fac
JB		 5502/**
5503 * i40e_send_version - update firmware with driver version
5504 * @pf: PF struct
5505 */
5506static void i40e_send_version(struct i40e_pf *pf)
5507{
5508 struct i40e_driver_version dv;
5509
5510 dv.major_version = DRV_VERSION_MAJOR;
5511 dv.minor_version = DRV_VERSION_MINOR;
5512 dv.build_version = DRV_VERSION_BUILD;
5513 dv.subbuild_version = 0;
5514 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5515 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5516}
5517
f650a38b 5518/**
4dda12e6 5519 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5520 * @pf: board private structure
bc7d338f 5521 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5522 **/
bc7d338f 5523static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5524{
f650a38b
ASJ		 5525 struct i40e_hw *hw = &pf->hw;
5526 i40e_status ret;
5527 u32 v;
5528
41c445ff
JB		 5529 /* Now we wait for GRST to settle out.
5530 * We don't have to delete the VEBs or VSIs from the hw switch
5531 * because the reset will make them disappear.
5532 */
5533 ret = i40e_pf_reset(hw);
b5565400 5534 if (ret) {
41c445ff 5535 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5536 goto end_core_reset;
5537 }
41c445ff
JB		 5538 pf->pfr_count++;
5539
5540 if (test_bit(__I40E_DOWN, &pf->state))
5541 goto end_core_reset;
69bfb110 5542 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5543
5544 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5545 ret = i40e_init_adminq(&pf->hw);
5546 if (ret) {
5547 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5548 goto end_core_reset;
5549 }
5550
4eb3f768
SN		 5551 /* re-verify the eeprom if we just had an EMP reset */
5552 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5553 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5554 i40e_verify_eeprom(pf);
5555 }
5556
e78ac4bf 5557 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5558 ret = i40e_get_capabilities(pf);
5559 if (ret) {
5560 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5561 ret);
5562 goto end_core_reset;
5563 }
5564
41c445ff
JB		 5565 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5566 hw->func_caps.num_rx_qp,
5567 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5568 if (ret) {
5569 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5570 goto end_core_reset;
5571 }
5572 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5573 if (ret) {
5574 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5575 goto end_core_reset;
5576 }
5577
4e3b35b0
NP		 5578#ifdef CONFIG_I40E_DCB
5579 ret = i40e_init_pf_dcb(pf);
5580 if (ret) {
5581 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5582 goto end_core_reset;
5583 }
5584#endif /* CONFIG_I40E_DCB */
5585
41c445ff 5586 /* do basic switch setup */
bc7d338f 5587 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5588 if (ret)
5589 goto end_core_reset;
5590
5591 /* Rebuild the VSIs and VEBs that existed before reset.
5592 * They are still in our local switch element arrays, so only
5593 * need to rebuild the switch model in the HW.
5594 *
5595 * If there were VEBs but the reconstitution failed, we'll try
5596 * try to recover minimal use by getting the basic PF VSI working.
5597 */
5598 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5599 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5600 /* find the one VEB connected to the MAC, and find orphans */
5601 for (v = 0; v < I40E_MAX_VEB; v++) {
5602 if (!pf->veb[v])
5603 continue;
5604
5605 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5606 pf->veb[v]->uplink_seid == 0) {
5607 ret = i40e_reconstitute_veb(pf->veb[v]);
5608
5609 if (!ret)
5610 continue;
5611
5612 /* If Main VEB failed, we're in deep doodoo,
5613 * so give up rebuilding the switch and set up
5614 * for minimal rebuild of PF VSI.
5615 * If orphan failed, we'll report the error
5616 * but try to keep going.
5617 */
5618 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5619 dev_info(&pf->pdev->dev,
5620 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5621 ret);
5622 pf->vsi[pf->lan_vsi]->uplink_seid
5623 = pf->mac_seid;
5624 break;
5625 } else if (pf->veb[v]->uplink_seid == 0) {
5626 dev_info(&pf->pdev->dev,
5627 "rebuild of orphan VEB failed: %d\n",
5628 ret);
5629 }
5630 }
5631 }
5632 }
5633
5634 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5635 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5636 /* no VEB, so rebuild only the Main VSI */
5637 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5638 if (ret) {
5639 dev_info(&pf->pdev->dev,
5640 "rebuild of Main VSI failed: %d\n", ret);
5641 goto end_core_reset;
5642 }
5643 }
5644
5645 /* reinit the misc interrupt */
5646 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5647 ret = i40e_setup_misc_vector(pf);
5648
5649 /* restart the VSIs that were rebuilt and running before the reset */
5650 i40e_pf_unquiesce_all_vsi(pf);
5651
69f64b2b
MW		 5652 if (pf->num_alloc_vfs) {
5653 for (v = 0; v < pf->num_alloc_vfs; v++)
5654 i40e_reset_vf(&pf->vf[v], true);
5655 }
5656
41c445ff 5657 /* tell the firmware that we're starting */
44033fac 5658 i40e_send_version(pf);
41c445ff 5659
41c445ff
JB		 5660end_core_reset:
5661 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5662}
5663
f650a38b
ASJ		 5664/**
5665 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5666 * @pf: board private structure
5667 *
5668 * Close up the VFs and other things in prep for a Core Reset,
5669 * then get ready to rebuild the world.
5670 **/
5671static void i40e_handle_reset_warning(struct i40e_pf *pf)
5672{
5673 i40e_status ret;
5674
5675 ret = i40e_prep_for_reset(pf);
5676 if (!ret)
bc7d338f 5677 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5678}
5679
41c445ff
JB		 5680/**
5681 * i40e_handle_mdd_event
5682 * @pf: pointer to the pf structure
5683 *
5684 * Called from the MDD irq handler to identify possibly malicious vfs
5685 **/
5686static void i40e_handle_mdd_event(struct i40e_pf *pf)
5687{
5688 struct i40e_hw *hw = &pf->hw;
5689 bool mdd_detected = false;
5690 struct i40e_vf *vf;
5691 u32 reg;
5692 int i;
5693
5694 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5695 return;
5696
5697 /* find what triggered the MDD event */
5698 reg = rd32(hw, I40E_GL_MDET_TX);
5699 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5700 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5701 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5702 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5703 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5704 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5705 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5706 dev_info(&pf->pdev->dev,
f29eaa3d 5707 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5708 event, queue, func);
5709 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5710 mdd_detected = true;
5711 }
5712 reg = rd32(hw, I40E_GL_MDET_RX);
5713 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5714 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5715 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5716 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5717 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5718 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5719 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5720 dev_info(&pf->pdev->dev,
f29eaa3d 5721 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5722 event, queue, func);
5723 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5724 mdd_detected = true;
5725 }
5726
5727 /* see if one of the VFs needs its hand slapped */
5728 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5729 vf = &(pf->vf[i]);
5730 reg = rd32(hw, I40E_VP_MDET_TX(i));
5731 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5732 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5733 vf->num_mdd_events++;
5734 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5735 }
5736
5737 reg = rd32(hw, I40E_VP_MDET_RX(i));
5738 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5739 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5740 vf->num_mdd_events++;
5741 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5742 }
5743
5744 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5745 dev_info(&pf->pdev->dev,
5746 "Too many MDD events on VF %d, disabled\n", i);
5747 dev_info(&pf->pdev->dev,
5748 "Use PF Control I/F to re-enable the VF\n");
5749 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5750 }
5751 }
5752
5753 /* re-enable mdd interrupt cause */
5754 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5755 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5756 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5757 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5758 i40e_flush(hw);
5759}
5760
a1c9a9d9
JK		 5761#ifdef CONFIG_I40E_VXLAN
5762/**
5763 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5764 * @pf: board private structure
5765 **/
5766static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5767{
a1c9a9d9
JK		 5768 struct i40e_hw *hw = &pf->hw;
5769 i40e_status ret;
5770 u8 filter_index;
5771 __be16 port;
5772 int i;
5773
5774 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5775 return;
5776
5777 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5778
5779 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5780 if (pf->pending_vxlan_bitmap & (1 << i)) {
5781 pf->pending_vxlan_bitmap &= ~(1 << i);
5782 port = pf->vxlan_ports[i];
5783 ret = port ?
5784 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5785 I40E_AQC_TUNNEL_TYPE_VXLAN,
5786 &filter_index, NULL)
5787 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5788
5789 if (ret) {
5790 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5791 port ? "adding" : "deleting",
5792 ntohs(port), port ? i : i);
5793
5794 pf->vxlan_ports[i] = 0;
5795 } else {
5796 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5797 port ? "Added" : "Deleted",
5798 ntohs(port), port ? i : filter_index);
5799 }
5800 }
5801 }
5802}
5803
5804#endif
41c445ff
JB		 5805/**
5806 * i40e_service_task - Run the driver's async subtasks
5807 * @work: pointer to work_struct containing our data
5808 **/
5809static void i40e_service_task(struct work_struct *work)
5810{
5811 struct i40e_pf *pf = container_of(work,
5812 struct i40e_pf,
5813 service_task);
5814 unsigned long start_time = jiffies;
5815
5816 i40e_reset_subtask(pf);
5817 i40e_handle_mdd_event(pf);
5818 i40e_vc_process_vflr_event(pf);
5819 i40e_watchdog_subtask(pf);
5820 i40e_fdir_reinit_subtask(pf);
5821 i40e_check_hang_subtask(pf);
5822 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5823#ifdef CONFIG_I40E_VXLAN
5824 i40e_sync_vxlan_filters_subtask(pf);
5825#endif
41c445ff
JB		 5826 i40e_clean_adminq_subtask(pf);
5827
5828 i40e_service_event_complete(pf);
5829
5830 /* If the tasks have taken longer than one timer cycle or there
5831 * is more work to be done, reschedule the service task now
5832 * rather than wait for the timer to tick again.
5833 */
5834 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5835 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5836 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5837 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5838 i40e_service_event_schedule(pf);
5839}
5840
5841/**
5842 * i40e_service_timer - timer callback
5843 * @data: pointer to PF struct
5844 **/
5845static void i40e_service_timer(unsigned long data)
5846{
5847 struct i40e_pf *pf = (struct i40e_pf *)data;
5848
5849 mod_timer(&pf->service_timer,
5850 round_jiffies(jiffies + pf->service_timer_period));
5851 i40e_service_event_schedule(pf);
5852}
5853
5854/**
5855 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5856 * @vsi: the VSI being configured
5857 **/
5858static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5859{
5860 struct i40e_pf *pf = vsi->back;
5861
5862 switch (vsi->type) {
5863 case I40E_VSI_MAIN:
5864 vsi->alloc_queue_pairs = pf->num_lan_qps;
5865 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5866 I40E_REQ_DESCRIPTOR_MULTIPLE);
5867 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5868 vsi->num_q_vectors = pf->num_lan_msix;
5869 else
5870 vsi->num_q_vectors = 1;
5871
5872 break;
5873
5874 case I40E_VSI_FDIR:
5875 vsi->alloc_queue_pairs = 1;
5876 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5877 I40E_REQ_DESCRIPTOR_MULTIPLE);
5878 vsi->num_q_vectors = 1;
5879 break;
5880
5881 case I40E_VSI_VMDQ2:
5882 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5883 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5884 I40E_REQ_DESCRIPTOR_MULTIPLE);
5885 vsi->num_q_vectors = pf->num_vmdq_msix;
5886 break;
5887
5888 case I40E_VSI_SRIOV:
5889 vsi->alloc_queue_pairs = pf->num_vf_qps;
5890 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5891 I40E_REQ_DESCRIPTOR_MULTIPLE);
5892 break;
5893
5894 default:
5895 WARN_ON(1);
5896 return -ENODATA;
5897 }
5898
5899 return 0;
5900}
5901
f650a38b
ASJ		 5902/**
5903 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5904 * @type: VSI pointer
bc7d338f 5905 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5906 *
5907 * On error: returns error code (negative)
5908 * On success: returns 0
5909 **/
bc7d338f 5910static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5911{
5912 int size;
5913 int ret = 0;
5914
ac6c5e3d 5915 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5916 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5917 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5918 if (!vsi->tx_rings)
5919 return -ENOMEM;
f650a38b
ASJ		 5920 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5921
bc7d338f
ASJ		 5922 if (alloc_qvectors) {
5923 /* allocate memory for q_vector pointers */
5924 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5925 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5926 if (!vsi->q_vectors) {
5927 ret = -ENOMEM;
5928 goto err_vectors;
5929 }
f650a38b
ASJ		 5930 }
5931 return ret;
5932
5933err_vectors:
5934 kfree(vsi->tx_rings);
5935 return ret;
5936}
5937
41c445ff
JB		 5938/**
5939 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5940 * @pf: board private structure
5941 * @type: type of VSI
5942 *
5943 * On error: returns error code (negative)
5944 * On success: returns vsi index in PF (positive)
5945 **/
5946static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5947{
5948 int ret = -ENODEV;
5949 struct i40e_vsi *vsi;
5950 int vsi_idx;
5951 int i;
5952
5953 /* Need to protect the allocation of the VSIs at the PF level */
5954 mutex_lock(&pf->switch_mutex);
5955
5956 /* VSI list may be fragmented if VSI creation/destruction has
5957 * been happening. We can afford to do a quick scan to look
5958 * for any free VSIs in the list.
5959 *
5960 * find next empty vsi slot, looping back around if necessary
5961 */
5962 i = pf->next_vsi;
5963 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5964 i++;
5965 if (i >= pf->hw.func_caps.num_vsis) {
5966 i = 0;
5967 while (i < pf->next_vsi && pf->vsi[i])
5968 i++;
5969 }
5970
5971 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5972 vsi_idx = i; /* Found one! */
5973 } else {
5974 ret = -ENODEV;
493fb300 5975 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5976 }
5977 pf->next_vsi = ++i;
5978
5979 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5980 if (!vsi) {
5981 ret = -ENOMEM;
493fb300 5982 goto unlock_pf;
41c445ff
JB		 5983 }
5984 vsi->type = type;
5985 vsi->back = pf;
5986 set_bit(__I40E_DOWN, &vsi->state);
5987 vsi->flags = 0;
5988 vsi->idx = vsi_idx;
5989 vsi->rx_itr_setting = pf->rx_itr_default;
5990 vsi->tx_itr_setting = pf->tx_itr_default;
5991 vsi->netdev_registered = false;
5992 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5993 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 5994 vsi->irqs_ready = false;
41c445ff 5995
9f65e15b
AD		 5996 ret = i40e_set_num_rings_in_vsi(vsi);
5997 if (ret)
5998 goto err_rings;
5999
bc7d338f 6000 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6001 if (ret)
9f65e15b 6002 goto err_rings;
493fb300 6003
41c445ff
JB		 6004 /* Setup default MSIX irq handler for VSI */
6005 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6006
6007 pf->vsi[vsi_idx] = vsi;
6008 ret = vsi_idx;
493fb300
AD		 6009 goto unlock_pf;
6010
9f65e15b 6011err_rings:
493fb300
AD		 6012 pf->next_vsi = i - 1;
6013 kfree(vsi);
6014unlock_pf:
41c445ff
JB		 6015 mutex_unlock(&pf->switch_mutex);
6016 return ret;
6017}
6018
f650a38b
ASJ		 6019/**
6020 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6021 * @type: VSI pointer
bc7d338f 6022 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6023 *
6024 * On error: returns error code (negative)
6025 * On success: returns 0
6026 **/
bc7d338f 6027static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6028{
6029 /* free the ring and vector containers */
bc7d338f
ASJ		 6030 if (free_qvectors) {
6031 kfree(vsi->q_vectors);
6032 vsi->q_vectors = NULL;
6033 }
f650a38b
ASJ		 6034 kfree(vsi->tx_rings);
6035 vsi->tx_rings = NULL;
6036 vsi->rx_rings = NULL;
6037}
6038
41c445ff
JB		 6039/**
6040 * i40e_vsi_clear - Deallocate the VSI provided
6041 * @vsi: the VSI being un-configured
6042 **/
6043static int i40e_vsi_clear(struct i40e_vsi *vsi)
6044{
6045 struct i40e_pf *pf;
6046
6047 if (!vsi)
6048 return 0;
6049
6050 if (!vsi->back)
6051 goto free_vsi;
6052 pf = vsi->back;
6053
6054 mutex_lock(&pf->switch_mutex);
6055 if (!pf->vsi[vsi->idx]) {
6056 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6057 vsi->idx, vsi->idx, vsi, vsi->type);
6058 goto unlock_vsi;
6059 }
6060
6061 if (pf->vsi[vsi->idx] != vsi) {
6062 dev_err(&pf->pdev->dev,
6063 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6064 pf->vsi[vsi->idx]->idx,
6065 pf->vsi[vsi->idx],
6066 pf->vsi[vsi->idx]->type,
6067 vsi->idx, vsi, vsi->type);
6068 goto unlock_vsi;
6069 }
6070
6071 /* updates the pf for this cleared vsi */
6072 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6073 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6074
bc7d338f 6075 i40e_vsi_free_arrays(vsi, true);
493fb300 6076
41c445ff
JB		 6077 pf->vsi[vsi->idx] = NULL;
6078 if (vsi->idx < pf->next_vsi)
6079 pf->next_vsi = vsi->idx;
6080
6081unlock_vsi:
6082 mutex_unlock(&pf->switch_mutex);
6083free_vsi:
6084 kfree(vsi);
6085
6086 return 0;
6087}
6088
9f65e15b
AD		 6089/**
6090 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6091 * @vsi: the VSI being cleaned
6092 **/
be1d5eea 6093static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6094{
6095 int i;
6096
8e9dca53 6097 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6098 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6099 kfree_rcu(vsi->tx_rings[i], rcu);
6100 vsi->tx_rings[i] = NULL;
6101 vsi->rx_rings[i] = NULL;
6102 }
be1d5eea 6103 }
9f65e15b
AD		 6104}
6105
41c445ff
JB		 6106/**
6107 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6108 * @vsi: the VSI being configured
6109 **/
6110static int i40e_alloc_rings(struct i40e_vsi *vsi)
6111{
e7046ee1 6112 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6113 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6114 int i;
6115
41c445ff 6116 /* Set basic values in the rings to be used later during open() */
d7397644 6117 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6118 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6119 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6120 if (!tx_ring)
6121 goto err_out;
41c445ff
JB		 6122
6123 tx_ring->queue_index = i;
6124 tx_ring->reg_idx = vsi->base_queue + i;
6125 tx_ring->ring_active = false;
6126 tx_ring->vsi = vsi;
6127 tx_ring->netdev = vsi->netdev;
6128 tx_ring->dev = &pf->pdev->dev;
6129 tx_ring->count = vsi->num_desc;
6130 tx_ring->size = 0;
6131 tx_ring->dcb_tc = 0;
9f65e15b 6132 vsi->tx_rings[i] = tx_ring;
41c445ff 6133
9f65e15b 6134 rx_ring = &tx_ring[1];
41c445ff
JB		 6135 rx_ring->queue_index = i;
6136 rx_ring->reg_idx = vsi->base_queue + i;
6137 rx_ring->ring_active = false;
6138 rx_ring->vsi = vsi;
6139 rx_ring->netdev = vsi->netdev;
6140 rx_ring->dev = &pf->pdev->dev;
6141 rx_ring->count = vsi->num_desc;
6142 rx_ring->size = 0;
6143 rx_ring->dcb_tc = 0;
6144 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6145 set_ring_16byte_desc_enabled(rx_ring);
6146 else
6147 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6148 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6149 }
6150
6151 return 0;
9f65e15b
AD		 6152
6153err_out:
6154 i40e_vsi_clear_rings(vsi);
6155 return -ENOMEM;
41c445ff
JB		 6156}
6157
6158/**
6159 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6160 * @pf: board private structure
6161 * @vectors: the number of MSI-X vectors to request
6162 *
6163 * Returns the number of vectors reserved, or error
6164 **/
6165static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6166{
7b37f376
AG		 6167 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6168 I40E_MIN_MSIX, vectors);
6169 if (vectors < 0) {
41c445ff 6170 dev_info(&pf->pdev->dev,
7b37f376 6171 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6172 vectors = 0;
6173 }
6174
6175 return vectors;
6176}
6177
6178/**
6179 * i40e_init_msix - Setup the MSIX capability
6180 * @pf: board private structure
6181 *
6182 * Work with the OS to set up the MSIX vectors needed.
6183 *
6184 * Returns 0 on success, negative on failure
6185 **/
6186static int i40e_init_msix(struct i40e_pf *pf)
6187{
6188 i40e_status err = 0;
6189 struct i40e_hw *hw = &pf->hw;
6190 int v_budget, i;
6191 int vec;
6192
6193 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6194 return -ENODEV;
6195
6196 /* The number of vectors we'll request will be comprised of:
6197 * - Add 1 for "other" cause for Admin Queue events, etc.
6198 * - The number of LAN queue pairs
f8ff1464
ASJ		 6199 * - Queues being used for RSS.
6200 * We don't need as many as max_rss_size vectors.
6201 * use rss_size instead in the calculation since that
6202 * is governed by number of cpus in the system.
6203 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6204 * - The number of VMDq pairs
6205 * Once we count this up, try the request.
6206 *
6207 * If we can't get what we want, we'll simplify to nearly nothing
6208 * and try again. If that still fails, we punt.
6209 */
f8ff1464 6210 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6211 pf->num_vmdq_msix = pf->num_vmdq_qps;
6212 v_budget = 1 + pf->num_lan_msix;
6213 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6214 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6215 v_budget++;
6216
6217 /* Scale down if necessary, and the rings will share vectors */
6218 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6219
6220 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6221 GFP_KERNEL);
6222 if (!pf->msix_entries)
6223 return -ENOMEM;
6224
6225 for (i = 0; i < v_budget; i++)
6226 pf->msix_entries[i].entry = i;
6227 vec = i40e_reserve_msix_vectors(pf, v_budget);
6228 if (vec < I40E_MIN_MSIX) {
6229 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6230 kfree(pf->msix_entries);
6231 pf->msix_entries = NULL;
6232 return -ENODEV;
6233
6234 } else if (vec == I40E_MIN_MSIX) {
6235 /* Adjust for minimal MSIX use */
77fa28be 6236 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6237 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6238 pf->num_vmdq_vsis = 0;
6239 pf->num_vmdq_qps = 0;
6240 pf->num_vmdq_msix = 0;
6241 pf->num_lan_qps = 1;
6242 pf->num_lan_msix = 1;
6243
6244 } else if (vec != v_budget) {
6245 /* Scale vector usage down */
6246 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6247 vec--; /* reserve the misc vector */
6248
6249 /* partition out the remaining vectors */
6250 switch (vec) {
6251 case 2:
6252 pf->num_vmdq_vsis = 1;
6253 pf->num_lan_msix = 1;
6254 break;
6255 case 3:
6256 pf->num_vmdq_vsis = 1;
6257 pf->num_lan_msix = 2;
6258 break;
6259 default:
6260 pf->num_lan_msix = min_t(int, (vec / 2),
6261 pf->num_lan_qps);
6262 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6263 I40E_DEFAULT_NUM_VMDQ_VSI);
6264 break;
6265 }
6266 }
6267
6268 return err;
6269}
6270
493fb300 6271/**
90e04070 6272 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6273 * @vsi: the VSI being configured
6274 * @v_idx: index of the vector in the vsi struct
6275 *
6276 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6277 **/
90e04070 6278static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6279{
6280 struct i40e_q_vector *q_vector;
6281
6282 /* allocate q_vector */
6283 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6284 if (!q_vector)
6285 return -ENOMEM;
6286
6287 q_vector->vsi = vsi;
6288 q_vector->v_idx = v_idx;
6289 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6290 if (vsi->netdev)
6291 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6292 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6293
cd0b6fa6
AD		 6294 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6295 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6296
493fb300
AD		 6297 /* tie q_vector and vsi together */
6298 vsi->q_vectors[v_idx] = q_vector;
6299
6300 return 0;
6301}
6302
41c445ff 6303/**
90e04070 6304 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6305 * @vsi: the VSI being configured
6306 *
6307 * We allocate one q_vector per queue interrupt. If allocation fails we
6308 * return -ENOMEM.
6309 **/
90e04070 6310static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6311{
6312 struct i40e_pf *pf = vsi->back;
6313 int v_idx, num_q_vectors;
493fb300 6314 int err;
41c445ff
JB		 6315
6316 /* if not MSIX, give the one vector only to the LAN VSI */
6317 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6318 num_q_vectors = vsi->num_q_vectors;
6319 else if (vsi == pf->vsi[pf->lan_vsi])
6320 num_q_vectors = 1;
6321 else
6322 return -EINVAL;
6323
41c445ff 6324 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6325 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6326 if (err)
6327 goto err_out;
41c445ff
JB		 6328 }
6329
6330 return 0;
493fb300
AD		 6331
6332err_out:
6333 while (v_idx--)
6334 i40e_free_q_vector(vsi, v_idx);
6335
6336 return err;
41c445ff
JB		 6337}
6338
6339/**
6340 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6341 * @pf: board private structure to initialize
6342 **/
6343static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6344{
6345 int err = 0;
6346
6347 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6348 err = i40e_init_msix(pf);
6349 if (err) {
60ea5f83
JB		 6350 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6351 I40E_FLAG_RSS_ENABLED |
6352 I40E_FLAG_DCB_ENABLED |
6353 I40E_FLAG_SRIOV_ENABLED |
6354 I40E_FLAG_FD_SB_ENABLED |
6355 I40E_FLAG_FD_ATR_ENABLED |
6356 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6357
6358 /* rework the queue expectations without MSIX */
6359 i40e_determine_queue_usage(pf);
6360 }
6361 }
6362
6363 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6364 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6365 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6366 err = pci_enable_msi(pf->pdev);
6367 if (err) {
958a3e3b 6368 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6369 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6370 }
6371 }
6372
958a3e3b 6373 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6374 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6375
41c445ff
JB		 6376 /* track first vector for misc interrupts */
6377 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6378}
6379
6380/**
6381 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6382 * @pf: board private structure
6383 *
6384 * This sets up the handler for MSIX 0, which is used to manage the
6385 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6386 * when in MSI or Legacy interrupt mode.
6387 **/
6388static int i40e_setup_misc_vector(struct i40e_pf *pf)
6389{
6390 struct i40e_hw *hw = &pf->hw;
6391 int err = 0;
6392
6393 /* Only request the irq if this is the first time through, and
6394 * not when we're rebuilding after a Reset
6395 */
6396 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6397 err = request_irq(pf->msix_entries[0].vector,
6398 i40e_intr, 0, pf->misc_int_name, pf);
6399 if (err) {
6400 dev_info(&pf->pdev->dev,
77fa28be
CS		 6401 "request_irq for %s failed: %d\n",
6402 pf->misc_int_name, err);
41c445ff
JB		 6403 return -EFAULT;
6404 }
6405 }
6406
6407 i40e_enable_misc_int_causes(hw);
6408
6409 /* associate no queues to the misc vector */
6410 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6411 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6412
6413 i40e_flush(hw);
6414
6415 i40e_irq_dynamic_enable_icr0(pf);
6416
6417 return err;
6418}
6419
6420/**
6421 * i40e_config_rss - Prepare for RSS if used
6422 * @pf: board private structure
6423 **/
6424static int i40e_config_rss(struct i40e_pf *pf)
6425{
41c445ff
JB		 6426 /* Set of random keys generated using kernel random number generator */
6427 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6428 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6429 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6430 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6431 struct i40e_hw *hw = &pf->hw;
6432 u32 lut = 0;
6433 int i, j;
6434 u64 hena;
41c445ff
JB		 6435
6436 /* Fill out hash function seed */
6437 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6438 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6439
6440 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6441 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6442 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6443 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6444 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6445 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6446
6447 /* Populate the LUT with max no. of queues in round robin fashion */
6448 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6449
6450 /* The assumption is that lan qp count will be the highest
6451 * qp count for any PF VSI that needs RSS.
6452 * If multiple VSIs need RSS support, all the qp counts
6453 * for those VSIs should be a power of 2 for RSS to work.
6454 * If LAN VSI is the only consumer for RSS then this requirement
6455 * is not necessary.
6456 */
6457 if (j == pf->rss_size)
6458 j = 0;
6459 /* lut = 4-byte sliding window of 4 lut entries */
6460 lut = (lut << 8) | (j &
6461 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6462 /* On i = 3, we have 4 entries in lut; write to the register */
6463 if ((i & 3) == 3)
6464 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6465 }
6466 i40e_flush(hw);
6467
6468 return 0;
6469}
6470
f8ff1464
ASJ		 6471/**
6472 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6473 * @pf: board private structure
6474 * @queue_count: the requested queue count for rss.
6475 *
6476 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6477 * count which may be different from the requested queue count.
6478 **/
6479int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6480{
6481 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6482 return 0;
6483
6484 queue_count = min_t(int, queue_count, pf->rss_size_max);
6485 queue_count = rounddown_pow_of_two(queue_count);
6486
6487 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6488 i40e_prep_for_reset(pf);
6489
f8ff1464
ASJ		 6490 pf->rss_size = queue_count;
6491
6492 i40e_reset_and_rebuild(pf, true);
6493 i40e_config_rss(pf);
6494 }
6495 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6496 return pf->rss_size;
6497}
6498
41c445ff
JB		 6499/**
6500 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6501 * @pf: board private structure to initialize
6502 *
6503 * i40e_sw_init initializes the Adapter private data structure.
6504 * Fields are initialized based on PCI device information and
6505 * OS network device settings (MTU size).
6506 **/
6507static int i40e_sw_init(struct i40e_pf *pf)
6508{
6509 int err = 0;
6510 int size;
6511
6512 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6513 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6514 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6515 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6516 if (I40E_DEBUG_USER & debug)
6517 pf->hw.debug_mask = debug;
6518 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6519 I40E_DEFAULT_MSG_ENABLE);
6520 }
6521
6522 /* Set default capability flags */
6523 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6524 I40E_FLAG_MSI_ENABLED |
6525 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6526 I40E_FLAG_RX_1BUF_ENABLED;
6527
ca99eb99
MW		 6528 /* Set default ITR */
6529 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6530 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6531
7134f9ce
JB		 6532 /* Depending on PF configurations, it is possible that the RSS
6533 * maximum might end up larger than the available queues
6534 */
41c445ff 6535 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6536 pf->rss_size_max = min_t(int, pf->rss_size_max,
6537 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6538 if (pf->hw.func_caps.rss) {
6539 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6540 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6541 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6542 } else {
6543 pf->rss_size = 1;
6544 }
6545
2050bc65
CS		 6546 /* MFP mode enabled */
6547 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6548 pf->flags |= I40E_FLAG_MFP_ENABLED;
6549 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6550 }
6551
cbf61325
ASJ		 6552 /* FW/NVM is not yet fixed in this regard */
6553 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6554 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6555 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6556 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6557 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6558 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6559 } else {
6560 dev_info(&pf->pdev->dev,
0b67584f 6561 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6562 }
cbf61325
ASJ		 6563 pf->fdir_pf_filter_count =
6564 pf->hw.func_caps.fd_filters_guaranteed;
6565 pf->hw.fdir_shared_filter_count =
6566 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6567 }
6568
6569 if (pf->hw.func_caps.vmdq) {
6570 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6571 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6572 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6573 }
6574
41c445ff
JB		 6575#ifdef CONFIG_PCI_IOV
6576 if (pf->hw.func_caps.num_vfs) {
6577 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6578 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6579 pf->num_req_vfs = min_t(int,
6580 pf->hw.func_caps.num_vfs,
6581 I40E_MAX_VF_COUNT);
6582 }
6583#endif /* CONFIG_PCI_IOV */
6584 pf->eeprom_version = 0xDEAD;
6585 pf->lan_veb = I40E_NO_VEB;
6586 pf->lan_vsi = I40E_NO_VSI;
6587
6588 /* set up queue assignment tracking */
6589 size = sizeof(struct i40e_lump_tracking)
6590 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6591 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6592 if (!pf->qp_pile) {
6593 err = -ENOMEM;
6594 goto sw_init_done;
6595 }
6596 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6597 pf->qp_pile->search_hint = 0;
6598
6599 /* set up vector assignment tracking */
6600 size = sizeof(struct i40e_lump_tracking)
6601 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6602 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6603 if (!pf->irq_pile) {
6604 kfree(pf->qp_pile);
6605 err = -ENOMEM;
6606 goto sw_init_done;
6607 }
6608 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6609 pf->irq_pile->search_hint = 0;
6610
6611 mutex_init(&pf->switch_mutex);
6612
6613sw_init_done:
6614 return err;
6615}
6616
7c3c288b
ASJ		 6617/**
6618 * i40e_set_ntuple - set the ntuple feature flag and take action
6619 * @pf: board private structure to initialize
6620 * @features: the feature set that the stack is suggesting
6621 *
6622 * returns a bool to indicate if reset needs to happen
6623 **/
6624bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6625{
6626 bool need_reset = false;
6627
6628 /* Check if Flow Director n-tuple support was enabled or disabled. If
6629 * the state changed, we need to reset.
6630 */
6631 if (features & NETIF_F_NTUPLE) {
6632 /* Enable filters and mark for reset */
6633 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6634 need_reset = true;
6635 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6636 } else {
6637 /* turn off filters, mark for reset and clear SW filter list */
6638 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6639 need_reset = true;
6640 i40e_fdir_filter_exit(pf);
6641 }
6642 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6643 /* if ATR was disabled it can be re-enabled. */
6644 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6645 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6646 }
6647 return need_reset;
6648}
6649
41c445ff
JB		 6650/**
6651 * i40e_set_features - set the netdev feature flags
6652 * @netdev: ptr to the netdev being adjusted
6653 * @features: the feature set that the stack is suggesting
6654 **/
6655static int i40e_set_features(struct net_device *netdev,
6656 netdev_features_t features)
6657{
6658 struct i40e_netdev_priv *np = netdev_priv(netdev);
6659 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6660 struct i40e_pf *pf = vsi->back;
6661 bool need_reset;
41c445ff
JB		 6662
6663 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6664 i40e_vlan_stripping_enable(vsi);
6665 else
6666 i40e_vlan_stripping_disable(vsi);
6667
7c3c288b
ASJ		 6668 need_reset = i40e_set_ntuple(pf, features);
6669
6670 if (need_reset)
6671 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6672
41c445ff
JB		 6673 return 0;
6674}
6675
a1c9a9d9
JK		 6676#ifdef CONFIG_I40E_VXLAN
6677/**
6678 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6679 * @pf: board private structure
6680 * @port: The UDP port to look up
6681 *
6682 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6683 **/
6684static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6685{
6686 u8 i;
6687
6688 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6689 if (pf->vxlan_ports[i] == port)
6690 return i;
6691 }
6692
6693 return i;
6694}
6695
6696/**
6697 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6698 * @netdev: This physical port's netdev
6699 * @sa_family: Socket Family that VXLAN is notifying us about
6700 * @port: New UDP port number that VXLAN started listening to
6701 **/
6702static void i40e_add_vxlan_port(struct net_device *netdev,
6703 sa_family_t sa_family, __be16 port)
6704{
6705 struct i40e_netdev_priv *np = netdev_priv(netdev);
6706 struct i40e_vsi *vsi = np->vsi;
6707 struct i40e_pf *pf = vsi->back;
6708 u8 next_idx;
6709 u8 idx;
6710
6711 if (sa_family == AF_INET6)
6712 return;
6713
6714 idx = i40e_get_vxlan_port_idx(pf, port);
6715
6716 /* Check if port already exists */
6717 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6718 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6719 return;
6720 }
6721
6722 /* Now check if there is space to add the new port */
6723 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6724
6725 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6726 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6727 ntohs(port));
6728 return;
6729 }
6730
6731 /* New port: add it and mark its index in the bitmap */
6732 pf->vxlan_ports[next_idx] = port;
6733 pf->pending_vxlan_bitmap |= (1 << next_idx);
6734
6735 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6736}
6737
6738/**
6739 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6740 * @netdev: This physical port's netdev
6741 * @sa_family: Socket Family that VXLAN is notifying us about
6742 * @port: UDP port number that VXLAN stopped listening to
6743 **/
6744static void i40e_del_vxlan_port(struct net_device *netdev,
6745 sa_family_t sa_family, __be16 port)
6746{
6747 struct i40e_netdev_priv *np = netdev_priv(netdev);
6748 struct i40e_vsi *vsi = np->vsi;
6749 struct i40e_pf *pf = vsi->back;
6750 u8 idx;
6751
6752 if (sa_family == AF_INET6)
6753 return;
6754
6755 idx = i40e_get_vxlan_port_idx(pf, port);
6756
6757 /* Check if port already exists */
6758 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6759 /* if port exists, set it to 0 (mark for deletion)
6760 * and make it pending
6761 */
6762 pf->vxlan_ports[idx] = 0;
6763
6764 pf->pending_vxlan_bitmap |= (1 << idx);
6765
6766 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6767 } else {
6768 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6769 ntohs(port));
6770 }
6771}
6772
6773#endif
4ba0dea5
GR		 6774#ifdef HAVE_FDB_OPS
6775#ifdef USE_CONST_DEV_UC_CHAR
6776static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6777 struct net_device *dev,
6778 const unsigned char *addr,
6779 u16 flags)
6780#else
6781static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6782 struct net_device *dev,
6783 unsigned char *addr,
6784 u16 flags)
6785#endif
6786{
6787 struct i40e_netdev_priv *np = netdev_priv(dev);
6788 struct i40e_pf *pf = np->vsi->back;
6789 int err = 0;
6790
6791 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6792 return -EOPNOTSUPP;
6793
6794 /* Hardware does not support aging addresses so if a
6795 * ndm_state is given only allow permanent addresses
6796 */
6797 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6798 netdev_info(dev, "FDB only supports static addresses\n");
6799 return -EINVAL;
6800 }
6801
6802 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6803 err = dev_uc_add_excl(dev, addr);
6804 else if (is_multicast_ether_addr(addr))
6805 err = dev_mc_add_excl(dev, addr);
6806 else
6807 err = -EINVAL;
6808
6809 /* Only return duplicate errors if NLM_F_EXCL is set */
6810 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6811 err = 0;
6812
6813 return err;
6814}
6815
6816#ifndef USE_DEFAULT_FDB_DEL_DUMP
6817#ifdef USE_CONST_DEV_UC_CHAR
6818static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6819 struct net_device *dev,
6820 const unsigned char *addr)
6821#else
6822static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6823 struct net_device *dev,
6824 unsigned char *addr)
6825#endif
6826{
6827 struct i40e_netdev_priv *np = netdev_priv(dev);
6828 struct i40e_pf *pf = np->vsi->back;
6829 int err = -EOPNOTSUPP;
6830
6831 if (ndm->ndm_state & NUD_PERMANENT) {
6832 netdev_info(dev, "FDB only supports static addresses\n");
6833 return -EINVAL;
6834 }
6835
6836 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6837 if (is_unicast_ether_addr(addr))
6838 err = dev_uc_del(dev, addr);
6839 else if (is_multicast_ether_addr(addr))
6840 err = dev_mc_del(dev, addr);
6841 else
6842 err = -EINVAL;
6843 }
6844
6845 return err;
6846}
6847
6848static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6849 struct netlink_callback *cb,
6850 struct net_device *dev,
6851 int idx)
6852{
6853 struct i40e_netdev_priv *np = netdev_priv(dev);
6854 struct i40e_pf *pf = np->vsi->back;
6855
6856 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6857 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6858
6859 return idx;
6860}
6861
6862#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6863#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6864static const struct net_device_ops i40e_netdev_ops = {
6865 .ndo_open = i40e_open,
6866 .ndo_stop = i40e_close,
6867 .ndo_start_xmit = i40e_lan_xmit_frame,
6868 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6869 .ndo_set_rx_mode = i40e_set_rx_mode,
6870 .ndo_validate_addr = eth_validate_addr,
6871 .ndo_set_mac_address = i40e_set_mac,
6872 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6873 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6874 .ndo_tx_timeout = i40e_tx_timeout,
6875 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6876 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6877#ifdef CONFIG_NET_POLL_CONTROLLER
6878 .ndo_poll_controller = i40e_netpoll,
6879#endif
6880 .ndo_setup_tc = i40e_setup_tc,
6881 .ndo_set_features = i40e_set_features,
6882 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6883 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 6884 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 6885 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6886 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6887#ifdef CONFIG_I40E_VXLAN
6888 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6889 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6890#endif
4ba0dea5
GR		 6891#ifdef HAVE_FDB_OPS
6892 .ndo_fdb_add = i40e_ndo_fdb_add,
6893#ifndef USE_DEFAULT_FDB_DEL_DUMP
6894 .ndo_fdb_del = i40e_ndo_fdb_del,
6895 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6896#endif
6897#endif
41c445ff
JB		 6898};
6899
6900/**
6901 * i40e_config_netdev - Setup the netdev flags
6902 * @vsi: the VSI being configured
6903 *
6904 * Returns 0 on success, negative value on failure
6905 **/
6906static int i40e_config_netdev(struct i40e_vsi *vsi)
6907{
1a10370a 6908 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6909 struct i40e_pf *pf = vsi->back;
6910 struct i40e_hw *hw = &pf->hw;
6911 struct i40e_netdev_priv *np;
6912 struct net_device *netdev;
6913 u8 mac_addr[ETH_ALEN];
6914 int etherdev_size;
6915
6916 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6917 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6918 if (!netdev)
6919 return -ENOMEM;
6920
6921 vsi->netdev = netdev;
6922 np = netdev_priv(netdev);
6923 np->vsi = vsi;
6924
d70e941b 6925 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6926 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6927 NETIF_F_TSO;
41c445ff
JB		 6928
6929 netdev->features = NETIF_F_SG |
6930 NETIF_F_IP_CSUM |
6931 NETIF_F_SCTP_CSUM |
6932 NETIF_F_HIGHDMA |
6933 NETIF_F_GSO_UDP_TUNNEL |
6934 NETIF_F_HW_VLAN_CTAG_TX |
6935 NETIF_F_HW_VLAN_CTAG_RX |
6936 NETIF_F_HW_VLAN_CTAG_FILTER |
6937 NETIF_F_IPV6_CSUM |
6938 NETIF_F_TSO |
059dab69 6939 NETIF_F_TSO_ECN |
41c445ff
JB		 6940 NETIF_F_TSO6 |
6941 NETIF_F_RXCSUM |
6942 NETIF_F_RXHASH |
6943 0;
6944
2e86a0b6
ASJ		 6945 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
6946 netdev->features |= NETIF_F_NTUPLE;
6947
41c445ff
JB		 6948 /* copy netdev features into list of user selectable features */
6949 netdev->hw_features |= netdev->features;
6950
6951 if (vsi->type == I40E_VSI_MAIN) {
6952 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6953 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6954 } else {
6955 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6956 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6957 pf->vsi[pf->lan_vsi]->netdev->name);
6958 random_ether_addr(mac_addr);
6959 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6960 }
1a10370a 6961 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6962
6963 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6964 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6965 /* vlan gets same features (except vlan offload)
6966 * after any tweaks for specific VSI types
6967 */
6968 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6969 NETIF_F_HW_VLAN_CTAG_RX |
6970 NETIF_F_HW_VLAN_CTAG_FILTER);
6971 netdev->priv_flags |= IFF_UNICAST_FLT;
6972 netdev->priv_flags |= IFF_SUPP_NOFCS;
6973 /* Setup netdev TC information */
6974 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6975
6976 netdev->netdev_ops = &i40e_netdev_ops;
6977 netdev->watchdog_timeo = 5 * HZ;
6978 i40e_set_ethtool_ops(netdev);
6979
6980 return 0;
6981}
6982
6983/**
6984 * i40e_vsi_delete - Delete a VSI from the switch
6985 * @vsi: the VSI being removed
6986 *
6987 * Returns 0 on success, negative value on failure
6988 **/
6989static void i40e_vsi_delete(struct i40e_vsi *vsi)
6990{
6991 /* remove default VSI is not allowed */
6992 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6993 return;
6994
41c445ff 6995 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 6996}
6997
6998/**
6999 * i40e_add_vsi - Add a VSI to the switch
7000 * @vsi: the VSI being configured
7001 *
7002 * This initializes a VSI context depending on the VSI type to be added and
7003 * passes it down to the add_vsi aq command.
7004 **/
7005static int i40e_add_vsi(struct i40e_vsi *vsi)
7006{
7007 int ret = -ENODEV;
7008 struct i40e_mac_filter *f, *ftmp;
7009 struct i40e_pf *pf = vsi->back;
7010 struct i40e_hw *hw = &pf->hw;
7011 struct i40e_vsi_context ctxt;
7012 u8 enabled_tc = 0x1; /* TC0 enabled */
7013 int f_count = 0;
7014
7015 memset(&ctxt, 0, sizeof(ctxt));
7016 switch (vsi->type) {
7017 case I40E_VSI_MAIN:
7018 /* The PF's main VSI is already setup as part of the
7019 * device initialization, so we'll not bother with
7020 * the add_vsi call, but we will retrieve the current
7021 * VSI context.
7022 */
7023 ctxt.seid = pf->main_vsi_seid;
7024 ctxt.pf_num = pf->hw.pf_id;
7025 ctxt.vf_num = 0;
7026 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7027 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7028 if (ret) {
7029 dev_info(&pf->pdev->dev,
7030 "couldn't get pf vsi config, err %d, aq_err %d\n",
7031 ret, pf->hw.aq.asq_last_status);
7032 return -ENOENT;
7033 }
7034 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7035 vsi->info.valid_sections = 0;
7036
7037 vsi->seid = ctxt.seid;
7038 vsi->id = ctxt.vsi_number;
7039
7040 enabled_tc = i40e_pf_get_tc_map(pf);
7041
7042 /* MFP mode setup queue map and update VSI */
7043 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7044 memset(&ctxt, 0, sizeof(ctxt));
7045 ctxt.seid = pf->main_vsi_seid;
7046 ctxt.pf_num = pf->hw.pf_id;
7047 ctxt.vf_num = 0;
7048 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7049 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7050 if (ret) {
7051 dev_info(&pf->pdev->dev,
7052 "update vsi failed, aq_err=%d\n",
7053 pf->hw.aq.asq_last_status);
7054 ret = -ENOENT;
7055 goto err;
7056 }
7057 /* update the local VSI info queue map */
7058 i40e_vsi_update_queue_map(vsi, &ctxt);
7059 vsi->info.valid_sections = 0;
7060 } else {
7061 /* Default/Main VSI is only enabled for TC0
7062 * reconfigure it to enable all TCs that are
7063 * available on the port in SFP mode.
7064 */
7065 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7066 if (ret) {
7067 dev_info(&pf->pdev->dev,
7068 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7069 enabled_tc, ret,
7070 pf->hw.aq.asq_last_status);
7071 ret = -ENOENT;
7072 }
7073 }
7074 break;
7075
7076 case I40E_VSI_FDIR:
cbf61325
ASJ		 7077 ctxt.pf_num = hw->pf_id;
7078 ctxt.vf_num = 0;
7079 ctxt.uplink_seid = vsi->uplink_seid;
7080 ctxt.connection_type = 0x1; /* regular data port */
7081 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7082 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7083 break;
7084
7085 case I40E_VSI_VMDQ2:
7086 ctxt.pf_num = hw->pf_id;
7087 ctxt.vf_num = 0;
7088 ctxt.uplink_seid = vsi->uplink_seid;
7089 ctxt.connection_type = 0x1; /* regular data port */
7090 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7091
7092 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7093
7094 /* This VSI is connected to VEB so the switch_id
7095 * should be set to zero by default.
7096 */
7097 ctxt.info.switch_id = 0;
7098 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
7099 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7100
7101 /* Setup the VSI tx/rx queue map for TC0 only for now */
7102 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7103 break;
7104
7105 case I40E_VSI_SRIOV:
7106 ctxt.pf_num = hw->pf_id;
7107 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7108 ctxt.uplink_seid = vsi->uplink_seid;
7109 ctxt.connection_type = 0x1; /* regular data port */
7110 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7111
7112 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7113
7114 /* This VSI is connected to VEB so the switch_id
7115 * should be set to zero by default.
7116 */
7117 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7118
7119 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7120 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
7121 /* Setup the VSI tx/rx queue map for TC0 only for now */
7122 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7123 break;
7124
7125 default:
7126 return -ENODEV;
7127 }
7128
7129 if (vsi->type != I40E_VSI_MAIN) {
7130 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7131 if (ret) {
7132 dev_info(&vsi->back->pdev->dev,
7133 "add vsi failed, aq_err=%d\n",
7134 vsi->back->hw.aq.asq_last_status);
7135 ret = -ENOENT;
7136 goto err;
7137 }
7138 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7139 vsi->info.valid_sections = 0;
7140 vsi->seid = ctxt.seid;
7141 vsi->id = ctxt.vsi_number;
7142 }
7143
7144 /* If macvlan filters already exist, force them to get loaded */
7145 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7146 f->changed = true;
7147 f_count++;
7148 }
7149 if (f_count) {
7150 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7151 pf->flags |= I40E_FLAG_FILTER_SYNC;
7152 }
7153
7154 /* Update VSI BW information */
7155 ret = i40e_vsi_get_bw_info(vsi);
7156 if (ret) {
7157 dev_info(&pf->pdev->dev,
7158 "couldn't get vsi bw info, err %d, aq_err %d\n",
7159 ret, pf->hw.aq.asq_last_status);
7160 /* VSI is already added so not tearing that up */
7161 ret = 0;
7162 }
7163
7164err:
7165 return ret;
7166}
7167
7168/**
7169 * i40e_vsi_release - Delete a VSI and free its resources
7170 * @vsi: the VSI being removed
7171 *
7172 * Returns 0 on success or < 0 on error
7173 **/
7174int i40e_vsi_release(struct i40e_vsi *vsi)
7175{
7176 struct i40e_mac_filter *f, *ftmp;
7177 struct i40e_veb *veb = NULL;
7178 struct i40e_pf *pf;
7179 u16 uplink_seid;
7180 int i, n;
7181
7182 pf = vsi->back;
7183
7184 /* release of a VEB-owner or last VSI is not allowed */
7185 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7186 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7187 vsi->seid, vsi->uplink_seid);
7188 return -ENODEV;
7189 }
7190 if (vsi == pf->vsi[pf->lan_vsi] &&
7191 !test_bit(__I40E_DOWN, &pf->state)) {
7192 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7193 return -ENODEV;
7194 }
7195
7196 uplink_seid = vsi->uplink_seid;
7197 if (vsi->type != I40E_VSI_SRIOV) {
7198 if (vsi->netdev_registered) {
7199 vsi->netdev_registered = false;
7200 if (vsi->netdev) {
7201 /* results in a call to i40e_close() */
7202 unregister_netdev(vsi->netdev);
41c445ff
JB		 7203 }
7204 } else {
90ef8d47 7205 i40e_vsi_close(vsi);
41c445ff
JB		 7206 }
7207 i40e_vsi_disable_irq(vsi);
7208 }
7209
7210 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7211 i40e_del_filter(vsi, f->macaddr, f->vlan,
7212 f->is_vf, f->is_netdev);
7213 i40e_sync_vsi_filters(vsi);
7214
7215 i40e_vsi_delete(vsi);
7216 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7217 if (vsi->netdev) {
7218 free_netdev(vsi->netdev);
7219 vsi->netdev = NULL;
7220 }
41c445ff
JB		 7221 i40e_vsi_clear_rings(vsi);
7222 i40e_vsi_clear(vsi);
7223
7224 /* If this was the last thing on the VEB, except for the
7225 * controlling VSI, remove the VEB, which puts the controlling
7226 * VSI onto the next level down in the switch.
7227 *
7228 * Well, okay, there's one more exception here: don't remove
7229 * the orphan VEBs yet. We'll wait for an explicit remove request
7230 * from up the network stack.
7231 */
7232 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7233 if (pf->vsi[i] &&
7234 pf->vsi[i]->uplink_seid == uplink_seid &&
7235 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7236 n++; /* count the VSIs */
7237 }
7238 }
7239 for (i = 0; i < I40E_MAX_VEB; i++) {
7240 if (!pf->veb[i])
7241 continue;
7242 if (pf->veb[i]->uplink_seid == uplink_seid)
7243 n++; /* count the VEBs */
7244 if (pf->veb[i]->seid == uplink_seid)
7245 veb = pf->veb[i];
7246 }
7247 if (n == 0 && veb && veb->uplink_seid != 0)
7248 i40e_veb_release(veb);
7249
7250 return 0;
7251}
7252
7253/**
7254 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7255 * @vsi: ptr to the VSI
7256 *
7257 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7258 * corresponding SW VSI structure and initializes num_queue_pairs for the
7259 * newly allocated VSI.
7260 *
7261 * Returns 0 on success or negative on failure
7262 **/
7263static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7264{
7265 int ret = -ENOENT;
7266 struct i40e_pf *pf = vsi->back;
7267
493fb300 7268 if (vsi->q_vectors[0]) {
41c445ff
JB		 7269 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7270 vsi->seid);
7271 return -EEXIST;
7272 }
7273
7274 if (vsi->base_vector) {
f29eaa3d 7275 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7276 vsi->seid, vsi->base_vector);
7277 return -EEXIST;
7278 }
7279
90e04070 7280 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7281 if (ret) {
7282 dev_info(&pf->pdev->dev,
7283 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7284 vsi->num_q_vectors, vsi->seid, ret);
7285 vsi->num_q_vectors = 0;
7286 goto vector_setup_out;
7287 }
7288
958a3e3b
SN		 7289 if (vsi->num_q_vectors)
7290 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7291 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7292 if (vsi->base_vector < 0) {
7293 dev_info(&pf->pdev->dev,
f29eaa3d 7294 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7295 vsi->seid, vsi->base_vector);
7296 i40e_vsi_free_q_vectors(vsi);
7297 ret = -ENOENT;
7298 goto vector_setup_out;
7299 }
7300
7301vector_setup_out:
7302 return ret;
7303}
7304
bc7d338f
ASJ		 7305/**
7306 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7307 * @vsi: pointer to the vsi.
7308 *
7309 * This re-allocates a vsi's queue resources.
7310 *
7311 * Returns pointer to the successfully allocated and configured VSI sw struct
7312 * on success, otherwise returns NULL on failure.
7313 **/
7314static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7315{
7316 struct i40e_pf *pf = vsi->back;
7317 u8 enabled_tc;
7318 int ret;
7319
7320 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7321 i40e_vsi_clear_rings(vsi);
7322
7323 i40e_vsi_free_arrays(vsi, false);
7324 i40e_set_num_rings_in_vsi(vsi);
7325 ret = i40e_vsi_alloc_arrays(vsi, false);
7326 if (ret)
7327 goto err_vsi;
7328
7329 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7330 if (ret < 0) {
7331 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7332 vsi->seid, ret);
7333 goto err_vsi;
7334 }
7335 vsi->base_queue = ret;
7336
7337 /* Update the FW view of the VSI. Force a reset of TC and queue
7338 * layout configurations.
7339 */
7340 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7341 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7342 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7343 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7344
7345 /* assign it some queues */
7346 ret = i40e_alloc_rings(vsi);
7347 if (ret)
7348 goto err_rings;
7349
7350 /* map all of the rings to the q_vectors */
7351 i40e_vsi_map_rings_to_vectors(vsi);
7352 return vsi;
7353
7354err_rings:
7355 i40e_vsi_free_q_vectors(vsi);
7356 if (vsi->netdev_registered) {
7357 vsi->netdev_registered = false;
7358 unregister_netdev(vsi->netdev);
7359 free_netdev(vsi->netdev);
7360 vsi->netdev = NULL;
7361 }
7362 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7363err_vsi:
7364 i40e_vsi_clear(vsi);
7365 return NULL;
7366}
7367
41c445ff
JB		 7368/**
7369 * i40e_vsi_setup - Set up a VSI by a given type
7370 * @pf: board private structure
7371 * @type: VSI type
7372 * @uplink_seid: the switch element to link to
7373 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7374 *
7375 * This allocates the sw VSI structure and its queue resources, then add a VSI
7376 * to the identified VEB.
7377 *
7378 * Returns pointer to the successfully allocated and configure VSI sw struct on
7379 * success, otherwise returns NULL on failure.
7380 **/
7381struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7382 u16 uplink_seid, u32 param1)
7383{
7384 struct i40e_vsi *vsi = NULL;
7385 struct i40e_veb *veb = NULL;
7386 int ret, i;
7387 int v_idx;
7388
7389 /* The requested uplink_seid must be either
7390 * - the PF's port seid
7391 * no VEB is needed because this is the PF
7392 * or this is a Flow Director special case VSI
7393 * - seid of an existing VEB
7394 * - seid of a VSI that owns an existing VEB
7395 * - seid of a VSI that doesn't own a VEB
7396 * a new VEB is created and the VSI becomes the owner
7397 * - seid of the PF VSI, which is what creates the first VEB
7398 * this is a special case of the previous
7399 *
7400 * Find which uplink_seid we were given and create a new VEB if needed
7401 */
7402 for (i = 0; i < I40E_MAX_VEB; i++) {
7403 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7404 veb = pf->veb[i];
7405 break;
7406 }
7407 }
7408
7409 if (!veb && uplink_seid != pf->mac_seid) {
7410
7411 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7412 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7413 vsi = pf->vsi[i];
7414 break;
7415 }
7416 }
7417 if (!vsi) {
7418 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7419 uplink_seid);
7420 return NULL;
7421 }
7422
7423 if (vsi->uplink_seid == pf->mac_seid)
7424 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7425 vsi->tc_config.enabled_tc);
7426 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7427 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7428 vsi->tc_config.enabled_tc);
7429
7430 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7431 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7432 veb = pf->veb[i];
7433 }
7434 if (!veb) {
7435 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7436 return NULL;
7437 }
7438
7439 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7440 uplink_seid = veb->seid;
7441 }
7442
7443 /* get vsi sw struct */
7444 v_idx = i40e_vsi_mem_alloc(pf, type);
7445 if (v_idx < 0)
7446 goto err_alloc;
7447 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7448 if (!vsi)
7449 goto err_alloc;
41c445ff
JB		 7450 vsi->type = type;
7451 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7452
7453 if (type == I40E_VSI_MAIN)
7454 pf->lan_vsi = v_idx;
7455 else if (type == I40E_VSI_SRIOV)
7456 vsi->vf_id = param1;
7457 /* assign it some queues */
cbf61325
ASJ		 7458 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7459 vsi->idx);
41c445ff
JB		 7460 if (ret < 0) {
7461 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7462 vsi->seid, ret);
7463 goto err_vsi;
7464 }
7465 vsi->base_queue = ret;
7466
7467 /* get a VSI from the hardware */
7468 vsi->uplink_seid = uplink_seid;
7469 ret = i40e_add_vsi(vsi);
7470 if (ret)
7471 goto err_vsi;
7472
7473 switch (vsi->type) {
7474 /* setup the netdev if needed */
7475 case I40E_VSI_MAIN:
7476 case I40E_VSI_VMDQ2:
7477 ret = i40e_config_netdev(vsi);
7478 if (ret)
7479 goto err_netdev;
7480 ret = register_netdev(vsi->netdev);
7481 if (ret)
7482 goto err_netdev;
7483 vsi->netdev_registered = true;
7484 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7485#ifdef CONFIG_I40E_DCB
7486 /* Setup DCB netlink interface */
7487 i40e_dcbnl_setup(vsi);
7488#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7489 /* fall through */
7490
7491 case I40E_VSI_FDIR:
7492 /* set up vectors and rings if needed */
7493 ret = i40e_vsi_setup_vectors(vsi);
7494 if (ret)
7495 goto err_msix;
7496
7497 ret = i40e_alloc_rings(vsi);
7498 if (ret)
7499 goto err_rings;
7500
7501 /* map all of the rings to the q_vectors */
7502 i40e_vsi_map_rings_to_vectors(vsi);
7503
7504 i40e_vsi_reset_stats(vsi);
7505 break;
7506
7507 default:
7508 /* no netdev or rings for the other VSI types */
7509 break;
7510 }
7511
7512 return vsi;
7513
7514err_rings:
7515 i40e_vsi_free_q_vectors(vsi);
7516err_msix:
7517 if (vsi->netdev_registered) {
7518 vsi->netdev_registered = false;
7519 unregister_netdev(vsi->netdev);
7520 free_netdev(vsi->netdev);
7521 vsi->netdev = NULL;
7522 }
7523err_netdev:
7524 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7525err_vsi:
7526 i40e_vsi_clear(vsi);
7527err_alloc:
7528 return NULL;
7529}
7530
7531/**
7532 * i40e_veb_get_bw_info - Query VEB BW information
7533 * @veb: the veb to query
7534 *
7535 * Query the Tx scheduler BW configuration data for given VEB
7536 **/
7537static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7538{
7539 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7540 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7541 struct i40e_pf *pf = veb->pf;
7542 struct i40e_hw *hw = &pf->hw;
7543 u32 tc_bw_max;
7544 int ret = 0;
7545 int i;
7546
7547 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7548 &bw_data, NULL);
7549 if (ret) {
7550 dev_info(&pf->pdev->dev,
7551 "query veb bw config failed, aq_err=%d\n",
7552 hw->aq.asq_last_status);
7553 goto out;
7554 }
7555
7556 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7557 &ets_data, NULL);
7558 if (ret) {
7559 dev_info(&pf->pdev->dev,
7560 "query veb bw ets config failed, aq_err=%d\n",
7561 hw->aq.asq_last_status);
7562 goto out;
7563 }
7564
7565 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7566 veb->bw_max_quanta = ets_data.tc_bw_max;
7567 veb->is_abs_credits = bw_data.absolute_credits_enable;
7568 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7569 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7570 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7571 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7572 veb->bw_tc_limit_credits[i] =
7573 le16_to_cpu(bw_data.tc_bw_limits[i]);
7574 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7575 }
7576
7577out:
7578 return ret;
7579}
7580
7581/**
7582 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7583 * @pf: board private structure
7584 *
7585 * On error: returns error code (negative)
7586 * On success: returns vsi index in PF (positive)
7587 **/
7588static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7589{
7590 int ret = -ENOENT;
7591 struct i40e_veb *veb;
7592 int i;
7593
7594 /* Need to protect the allocation of switch elements at the PF level */
7595 mutex_lock(&pf->switch_mutex);
7596
7597 /* VEB list may be fragmented if VEB creation/destruction has
7598 * been happening. We can afford to do a quick scan to look
7599 * for any free slots in the list.
7600 *
7601 * find next empty veb slot, looping back around if necessary
7602 */
7603 i = 0;
7604 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7605 i++;
7606 if (i >= I40E_MAX_VEB) {
7607 ret = -ENOMEM;
7608 goto err_alloc_veb; /* out of VEB slots! */
7609 }
7610
7611 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7612 if (!veb) {
7613 ret = -ENOMEM;
7614 goto err_alloc_veb;
7615 }
7616 veb->pf = pf;
7617 veb->idx = i;
7618 veb->enabled_tc = 1;
7619
7620 pf->veb[i] = veb;
7621 ret = i;
7622err_alloc_veb:
7623 mutex_unlock(&pf->switch_mutex);
7624 return ret;
7625}
7626
7627/**
7628 * i40e_switch_branch_release - Delete a branch of the switch tree
7629 * @branch: where to start deleting
7630 *
7631 * This uses recursion to find the tips of the branch to be
7632 * removed, deleting until we get back to and can delete this VEB.
7633 **/
7634static void i40e_switch_branch_release(struct i40e_veb *branch)
7635{
7636 struct i40e_pf *pf = branch->pf;
7637 u16 branch_seid = branch->seid;
7638 u16 veb_idx = branch->idx;
7639 int i;
7640
7641 /* release any VEBs on this VEB - RECURSION */
7642 for (i = 0; i < I40E_MAX_VEB; i++) {
7643 if (!pf->veb[i])
7644 continue;
7645 if (pf->veb[i]->uplink_seid == branch->seid)
7646 i40e_switch_branch_release(pf->veb[i]);
7647 }
7648
7649 /* Release the VSIs on this VEB, but not the owner VSI.
7650 *
7651 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7652 * the VEB itself, so don't use (*branch) after this loop.
7653 */
7654 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7655 if (!pf->vsi[i])
7656 continue;
7657 if (pf->vsi[i]->uplink_seid == branch_seid &&
7658 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7659 i40e_vsi_release(pf->vsi[i]);
7660 }
7661 }
7662
7663 /* There's one corner case where the VEB might not have been
7664 * removed, so double check it here and remove it if needed.
7665 * This case happens if the veb was created from the debugfs
7666 * commands and no VSIs were added to it.
7667 */
7668 if (pf->veb[veb_idx])
7669 i40e_veb_release(pf->veb[veb_idx]);
7670}
7671
7672/**
7673 * i40e_veb_clear - remove veb struct
7674 * @veb: the veb to remove
7675 **/
7676static void i40e_veb_clear(struct i40e_veb *veb)
7677{
7678 if (!veb)
7679 return;
7680
7681 if (veb->pf) {
7682 struct i40e_pf *pf = veb->pf;
7683
7684 mutex_lock(&pf->switch_mutex);
7685 if (pf->veb[veb->idx] == veb)
7686 pf->veb[veb->idx] = NULL;
7687 mutex_unlock(&pf->switch_mutex);
7688 }
7689
7690 kfree(veb);
7691}
7692
7693/**
7694 * i40e_veb_release - Delete a VEB and free its resources
7695 * @veb: the VEB being removed
7696 **/
7697void i40e_veb_release(struct i40e_veb *veb)
7698{
7699 struct i40e_vsi *vsi = NULL;
7700 struct i40e_pf *pf;
7701 int i, n = 0;
7702
7703 pf = veb->pf;
7704
7705 /* find the remaining VSI and check for extras */
7706 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7707 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7708 n++;
7709 vsi = pf->vsi[i];
7710 }
7711 }
7712 if (n != 1) {
7713 dev_info(&pf->pdev->dev,
7714 "can't remove VEB %d with %d VSIs left\n",
7715 veb->seid, n);
7716 return;
7717 }
7718
7719 /* move the remaining VSI to uplink veb */
7720 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7721 if (veb->uplink_seid) {
7722 vsi->uplink_seid = veb->uplink_seid;
7723 if (veb->uplink_seid == pf->mac_seid)
7724 vsi->veb_idx = I40E_NO_VEB;
7725 else
7726 vsi->veb_idx = veb->veb_idx;
7727 } else {
7728 /* floating VEB */
7729 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7730 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7731 }
7732
7733 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7734 i40e_veb_clear(veb);
41c445ff
JB		 7735}
7736
7737/**
7738 * i40e_add_veb - create the VEB in the switch
7739 * @veb: the VEB to be instantiated
7740 * @vsi: the controlling VSI
7741 **/
7742static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7743{
56747264 7744 bool is_default = false;
e1c51b95 7745 bool is_cloud = false;
41c445ff
JB		 7746 int ret;
7747
7748 /* get a VEB from the hardware */
7749 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7750 veb->enabled_tc, is_default,
7751 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7752 if (ret) {
7753 dev_info(&veb->pf->pdev->dev,
7754 "couldn't add VEB, err %d, aq_err %d\n",
7755 ret, veb->pf->hw.aq.asq_last_status);
7756 return -EPERM;
7757 }
7758
7759 /* get statistics counter */
7760 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7761 &veb->stats_idx, NULL, NULL, NULL);
7762 if (ret) {
7763 dev_info(&veb->pf->pdev->dev,
7764 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7765 ret, veb->pf->hw.aq.asq_last_status);
7766 return -EPERM;
7767 }
7768 ret = i40e_veb_get_bw_info(veb);
7769 if (ret) {
7770 dev_info(&veb->pf->pdev->dev,
7771 "couldn't get VEB bw info, err %d, aq_err %d\n",
7772 ret, veb->pf->hw.aq.asq_last_status);
7773 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7774 return -ENOENT;
7775 }
7776
7777 vsi->uplink_seid = veb->seid;
7778 vsi->veb_idx = veb->idx;
7779 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7780
7781 return 0;
7782}
7783
7784/**
7785 * i40e_veb_setup - Set up a VEB
7786 * @pf: board private structure
7787 * @flags: VEB setup flags
7788 * @uplink_seid: the switch element to link to
7789 * @vsi_seid: the initial VSI seid
7790 * @enabled_tc: Enabled TC bit-map
7791 *
7792 * This allocates the sw VEB structure and links it into the switch
7793 * It is possible and legal for this to be a duplicate of an already
7794 * existing VEB. It is also possible for both uplink and vsi seids
7795 * to be zero, in order to create a floating VEB.
7796 *
7797 * Returns pointer to the successfully allocated VEB sw struct on
7798 * success, otherwise returns NULL on failure.
7799 **/
7800struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7801 u16 uplink_seid, u16 vsi_seid,
7802 u8 enabled_tc)
7803{
7804 struct i40e_veb *veb, *uplink_veb = NULL;
7805 int vsi_idx, veb_idx;
7806 int ret;
7807
7808 /* if one seid is 0, the other must be 0 to create a floating relay */
7809 if ((uplink_seid == 0 || vsi_seid == 0) &&
7810 (uplink_seid + vsi_seid != 0)) {
7811 dev_info(&pf->pdev->dev,
7812 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7813 uplink_seid, vsi_seid);
7814 return NULL;
7815 }
7816
7817 /* make sure there is such a vsi and uplink */
7818 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7819 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7820 break;
7821 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7822 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7823 vsi_seid);
7824 return NULL;
7825 }
7826
7827 if (uplink_seid && uplink_seid != pf->mac_seid) {
7828 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7829 if (pf->veb[veb_idx] &&
7830 pf->veb[veb_idx]->seid == uplink_seid) {
7831 uplink_veb = pf->veb[veb_idx];
7832 break;
7833 }
7834 }
7835 if (!uplink_veb) {
7836 dev_info(&pf->pdev->dev,
7837 "uplink seid %d not found\n", uplink_seid);
7838 return NULL;
7839 }
7840 }
7841
7842 /* get veb sw struct */
7843 veb_idx = i40e_veb_mem_alloc(pf);
7844 if (veb_idx < 0)
7845 goto err_alloc;
7846 veb = pf->veb[veb_idx];
7847 veb->flags = flags;
7848 veb->uplink_seid = uplink_seid;
7849 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7850 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7851
7852 /* create the VEB in the switch */
7853 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7854 if (ret)
7855 goto err_veb;
1bb8b935
SN		 7856 if (vsi_idx == pf->lan_vsi)
7857 pf->lan_veb = veb->idx;
41c445ff
JB		 7858
7859 return veb;
7860
7861err_veb:
7862 i40e_veb_clear(veb);
7863err_alloc:
7864 return NULL;
7865}
7866
7867/**
7868 * i40e_setup_pf_switch_element - set pf vars based on switch type
7869 * @pf: board private structure
7870 * @ele: element we are building info from
7871 * @num_reported: total number of elements
7872 * @printconfig: should we print the contents
7873 *
7874 * helper function to assist in extracting a few useful SEID values.
7875 **/
7876static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7877 struct i40e_aqc_switch_config_element_resp *ele,
7878 u16 num_reported, bool printconfig)
7879{
7880 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7881 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7882 u8 element_type = ele->element_type;
7883 u16 seid = le16_to_cpu(ele->seid);
7884
7885 if (printconfig)
7886 dev_info(&pf->pdev->dev,
7887 "type=%d seid=%d uplink=%d downlink=%d\n",
7888 element_type, seid, uplink_seid, downlink_seid);
7889
7890 switch (element_type) {
7891 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7892 pf->mac_seid = seid;
7893 break;
7894 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7895 /* Main VEB? */
7896 if (uplink_seid != pf->mac_seid)
7897 break;
7898 if (pf->lan_veb == I40E_NO_VEB) {
7899 int v;
7900
7901 /* find existing or else empty VEB */
7902 for (v = 0; v < I40E_MAX_VEB; v++) {
7903 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7904 pf->lan_veb = v;
7905 break;
7906 }
7907 }
7908 if (pf->lan_veb == I40E_NO_VEB) {
7909 v = i40e_veb_mem_alloc(pf);
7910 if (v < 0)
7911 break;
7912 pf->lan_veb = v;
7913 }
7914 }
7915
7916 pf->veb[pf->lan_veb]->seid = seid;
7917 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7918 pf->veb[pf->lan_veb]->pf = pf;
7919 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7920 break;
7921 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7922 if (num_reported != 1)
7923 break;
7924 /* This is immediately after a reset so we can assume this is
7925 * the PF's VSI
7926 */
7927 pf->mac_seid = uplink_seid;
7928 pf->pf_seid = downlink_seid;
7929 pf->main_vsi_seid = seid;
7930 if (printconfig)
7931 dev_info(&pf->pdev->dev,
7932 "pf_seid=%d main_vsi_seid=%d\n",
7933 pf->pf_seid, pf->main_vsi_seid);
7934 break;
7935 case I40E_SWITCH_ELEMENT_TYPE_PF:
7936 case I40E_SWITCH_ELEMENT_TYPE_VF:
7937 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7938 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7939 case I40E_SWITCH_ELEMENT_TYPE_PE:
7940 case I40E_SWITCH_ELEMENT_TYPE_PA:
7941 /* ignore these for now */
7942 break;
7943 default:
7944 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7945 element_type, seid);
7946 break;
7947 }
7948}
7949
7950/**
7951 * i40e_fetch_switch_configuration - Get switch config from firmware
7952 * @pf: board private structure
7953 * @printconfig: should we print the contents
7954 *
7955 * Get the current switch configuration from the device and
7956 * extract a few useful SEID values.
7957 **/
7958int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7959{
7960 struct i40e_aqc_get_switch_config_resp *sw_config;
7961 u16 next_seid = 0;
7962 int ret = 0;
7963 u8 *aq_buf;
7964 int i;
7965
7966 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7967 if (!aq_buf)
7968 return -ENOMEM;
7969
7970 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7971 do {
7972 u16 num_reported, num_total;
7973
7974 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7975 I40E_AQ_LARGE_BUF,
7976 &next_seid, NULL);
7977 if (ret) {
7978 dev_info(&pf->pdev->dev,
7979 "get switch config failed %d aq_err=%x\n",
7980 ret, pf->hw.aq.asq_last_status);
7981 kfree(aq_buf);
7982 return -ENOENT;
7983 }
7984
7985 num_reported = le16_to_cpu(sw_config->header.num_reported);
7986 num_total = le16_to_cpu(sw_config->header.num_total);
7987
7988 if (printconfig)
7989 dev_info(&pf->pdev->dev,
7990 "header: %d reported %d total\n",
7991 num_reported, num_total);
7992
7993 if (num_reported) {
7994 int sz = sizeof(*sw_config) * num_reported;
7995
7996 kfree(pf->sw_config);
7997 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7998 if (pf->sw_config)
7999 memcpy(pf->sw_config, sw_config, sz);
8000 }
8001
8002 for (i = 0; i < num_reported; i++) {
8003 struct i40e_aqc_switch_config_element_resp *ele =
8004 &sw_config->element[i];
8005
8006 i40e_setup_pf_switch_element(pf, ele, num_reported,
8007 printconfig);
8008 }
8009 } while (next_seid != 0);
8010
8011 kfree(aq_buf);
8012 return ret;
8013}
8014
8015/**
8016 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8017 * @pf: board private structure
bc7d338f 8018 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8019 *
8020 * Returns 0 on success, negative value on failure
8021 **/
bc7d338f 8022static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 8023{
895106a5 8024 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 8025 int ret;
8026
8027 /* find out what's out there already */
8028 ret = i40e_fetch_switch_configuration(pf, false);
8029 if (ret) {
8030 dev_info(&pf->pdev->dev,
8031 "couldn't fetch switch config, err %d, aq_err %d\n",
8032 ret, pf->hw.aq.asq_last_status);
8033 return ret;
8034 }
8035 i40e_pf_reset_stats(pf);
8036
41c445ff 8037 /* first time setup */
bc7d338f 8038 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8039 struct i40e_vsi *vsi = NULL;
8040 u16 uplink_seid;
8041
8042 /* Set up the PF VSI associated with the PF's main VSI
8043 * that is already in the HW switch
8044 */
8045 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8046 uplink_seid = pf->veb[pf->lan_veb]->seid;
8047 else
8048 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8049 if (pf->lan_vsi == I40E_NO_VSI)
8050 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8051 else if (reinit)
8052 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8053 if (!vsi) {
8054 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8055 i40e_fdir_teardown(pf);
8056 return -EAGAIN;
8057 }
41c445ff
JB		 8058 } else {
8059 /* force a reset of TC and queue layout configurations */
8060 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8061 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8062 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8063 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8064 }
8065 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8066
cbf61325
ASJ		 8067 i40e_fdir_sb_setup(pf);
8068
41c445ff
JB		 8069 /* Setup static PF queue filter control settings */
8070 ret = i40e_setup_pf_filter_control(pf);
8071 if (ret) {
8072 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8073 ret);
8074 /* Failure here should not stop continuing other steps */
8075 }
8076
8077 /* enable RSS in the HW, even for only one queue, as the stack can use
8078 * the hash
8079 */
8080 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8081 i40e_config_rss(pf);
8082
8083 /* fill in link information and enable LSE reporting */
8084 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
8085 i40e_link_event(pf);
8086
d52c20b7 8087 /* Initialize user-specific link properties */
41c445ff
JB		 8088 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8089 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 8090 /* requested_mode is set in probe or by ethtool */
8091 if (!pf->fc_autoneg_status)
8092 goto no_autoneg;
8093
8094 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
8095 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 8096 pf->hw.fc.current_mode = I40E_FC_FULL;
8097 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
8098 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
8099 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
8100 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
8101 else
d52c20b7
JB		 8102 pf->hw.fc.current_mode = I40E_FC_NONE;
8103
8104 /* sync the flow control settings with the auto-neg values */
8105 switch (pf->hw.fc.current_mode) {
8106 case I40E_FC_FULL:
8107 txfc = 1;
8108 rxfc = 1;
8109 break;
8110 case I40E_FC_TX_PAUSE:
8111 txfc = 1;
8112 rxfc = 0;
8113 break;
8114 case I40E_FC_RX_PAUSE:
8115 txfc = 0;
8116 rxfc = 1;
8117 break;
8118 case I40E_FC_NONE:
8119 case I40E_FC_DEFAULT:
8120 txfc = 0;
8121 rxfc = 0;
8122 break;
8123 case I40E_FC_PFC:
8124 /* TBD */
8125 break;
8126 /* no default case, we have to handle all possibilities here */
8127 }
8128
8129 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8130
8131 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8132 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8133 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8134
8135 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8136
d52c20b7
JB		 8137 goto fc_complete;
8138
8139no_autoneg:
8140 /* disable L2 flow control, user can turn it on if they wish */
8141 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8142 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8143 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8144
8145fc_complete:
beb0dff1
JK		 8146 i40e_ptp_init(pf);
8147
41c445ff
JB		 8148 return ret;
8149}
8150
41c445ff
JB		 8151/**
8152 * i40e_determine_queue_usage - Work out queue distribution
8153 * @pf: board private structure
8154 **/
8155static void i40e_determine_queue_usage(struct i40e_pf *pf)
8156{
41c445ff
JB		 8157 int queues_left;
8158
8159 pf->num_lan_qps = 0;
41c445ff
JB		 8160
8161 /* Find the max queues to be put into basic use. We'll always be
8162 * using TC0, whether or not DCB is running, and TC0 will get the
8163 * big RSS set.
8164 */
8165 queues_left = pf->hw.func_caps.num_tx_qp;
8166
cbf61325
ASJ		 8167 if ((queues_left == 1) ||
8168 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8169 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8170 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8171 /* one qp for PF, no queues for anything else */
8172 queues_left = 0;
8173 pf->rss_size = pf->num_lan_qps = 1;
8174
8175 /* make sure all the fancies are disabled */
60ea5f83
JB		 8176 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8177 I40E_FLAG_FD_SB_ENABLED |
8178 I40E_FLAG_FD_ATR_ENABLED |
8179 I40E_FLAG_DCB_ENABLED |
8180 I40E_FLAG_SRIOV_ENABLED |
8181 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8182 } else {
cbf61325
ASJ		 8183 /* Not enough queues for all TCs */
8184 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8185 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8186 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8187 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8188 }
8189 pf->num_lan_qps = pf->rss_size_max;
8190 queues_left -= pf->num_lan_qps;
8191 }
8192
8193 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8194 if (queues_left > 1) {
8195 queues_left -= 1; /* save 1 queue for FD */
8196 } else {
8197 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8198 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8199 }
41c445ff
JB		 8200 }
8201
8202 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8203 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8204 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8205 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8206 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8207 }
8208
8209 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8210 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8211 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8212 (queues_left / pf->num_vmdq_qps));
8213 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8214 }
8215
f8ff1464 8216 pf->queues_left = queues_left;
41c445ff
JB		 8217}
8218
8219/**
8220 * i40e_setup_pf_filter_control - Setup PF static filter control
8221 * @pf: PF to be setup
8222 *
8223 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8224 * settings. If PE/FCoE are enabled then it will also set the per PF
8225 * based filter sizes required for them. It also enables Flow director,
8226 * ethertype and macvlan type filter settings for the pf.
8227 *
8228 * Returns 0 on success, negative on failure
8229 **/
8230static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8231{
8232 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8233
8234 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8235
8236 /* Flow Director is enabled */
60ea5f83 8237 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8238 settings->enable_fdir = true;
8239
8240 /* Ethtype and MACVLAN filters enabled for PF */
8241 settings->enable_ethtype = true;
8242 settings->enable_macvlan = true;
8243
8244 if (i40e_set_filter_control(&pf->hw, settings))
8245 return -ENOENT;
8246
8247 return 0;
8248}
8249
0c22b3dd
JB		 8250#define INFO_STRING_LEN 255
8251static void i40e_print_features(struct i40e_pf *pf)
8252{
8253 struct i40e_hw *hw = &pf->hw;
8254 char *buf, *string;
8255
8256 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8257 if (!string) {
8258 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8259 return;
8260 }
8261
8262 buf = string;
8263
8264 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8265#ifdef CONFIG_PCI_IOV
8266 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8267#endif
8268 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8269 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8270
8271 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8272 buf += sprintf(buf, "RSS ");
0c22b3dd 8273 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8274 buf += sprintf(buf, "FD_ATR ");
8275 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8276 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8277 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8278 }
0c22b3dd
JB		 8279 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8280 buf += sprintf(buf, "DCB ");
8281 if (pf->flags & I40E_FLAG_PTP)
8282 buf += sprintf(buf, "PTP ");
8283
8284 BUG_ON(buf > (string + INFO_STRING_LEN));
8285 dev_info(&pf->pdev->dev, "%s\n", string);
8286 kfree(string);
8287}
8288
41c445ff
JB		 8289/**
8290 * i40e_probe - Device initialization routine
8291 * @pdev: PCI device information struct
8292 * @ent: entry in i40e_pci_tbl
8293 *
8294 * i40e_probe initializes a pf identified by a pci_dev structure.
8295 * The OS initialization, configuring of the pf private structure,
8296 * and a hardware reset occur.
8297 *
8298 * Returns 0 on success, negative on failure
8299 **/
8300static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8301{
41c445ff
JB		 8302 struct i40e_pf *pf;
8303 struct i40e_hw *hw;
93cd765b 8304 static u16 pfs_found;
d4dfb81a 8305 u16 link_status;
41c445ff
JB		 8306 int err = 0;
8307 u32 len;
8a9eb7d3 8308 u32 i;
41c445ff
JB		 8309
8310 err = pci_enable_device_mem(pdev);
8311 if (err)
8312 return err;
8313
8314 /* set up for high or low dma */
6494294f 8315 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8316 if (err) {
e3e3bfdd
JS		 8317 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8318 if (err) {
8319 dev_err(&pdev->dev,
8320 "DMA configuration failed: 0x%x\n", err);
8321 goto err_dma;
8322 }
41c445ff
JB		 8323 }
8324
8325 /* set up pci connections */
8326 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8327 IORESOURCE_MEM), i40e_driver_name);
8328 if (err) {
8329 dev_info(&pdev->dev,
8330 "pci_request_selected_regions failed %d\n", err);
8331 goto err_pci_reg;
8332 }
8333
8334 pci_enable_pcie_error_reporting(pdev);
8335 pci_set_master(pdev);
8336
8337 /* Now that we have a PCI connection, we need to do the
8338 * low level device setup. This is primarily setting up
8339 * the Admin Queue structures and then querying for the
8340 * device's current profile information.
8341 */
8342 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8343 if (!pf) {
8344 err = -ENOMEM;
8345 goto err_pf_alloc;
8346 }
8347 pf->next_vsi = 0;
8348 pf->pdev = pdev;
8349 set_bit(__I40E_DOWN, &pf->state);
8350
8351 hw = &pf->hw;
8352 hw->back = pf;
8353 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8354 pci_resource_len(pdev, 0));
8355 if (!hw->hw_addr) {
8356 err = -EIO;
8357 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8358 (unsigned int)pci_resource_start(pdev, 0),
8359 (unsigned int)pci_resource_len(pdev, 0), err);
8360 goto err_ioremap;
8361 }
8362 hw->vendor_id = pdev->vendor;
8363 hw->device_id = pdev->device;
8364 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8365 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8366 hw->subsystem_device_id = pdev->subsystem_device;
8367 hw->bus.device = PCI_SLOT(pdev->devfn);
8368 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8369 pf->instance = pfs_found;
41c445ff 8370
7134f9ce
JB		 8371 /* do a special CORER for clearing PXE mode once at init */
8372 if (hw->revision_id == 0 &&
8373 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8374 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8375 i40e_flush(hw);
8376 msleep(200);
8377 pf->corer_count++;
8378
8379 i40e_clear_pxe_mode(hw);
8380 }
8381
41c445ff
JB		 8382 /* Reset here to make sure all is clean and to define PF 'n' */
8383 err = i40e_pf_reset(hw);
8384 if (err) {
8385 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8386 goto err_pf_reset;
8387 }
8388 pf->pfr_count++;
8389
8390 hw->aq.num_arq_entries = I40E_AQ_LEN;
8391 hw->aq.num_asq_entries = I40E_AQ_LEN;
8392 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8393 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8394 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8395 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8396 "%s-pf%d:misc",
8397 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8398
8399 err = i40e_init_shared_code(hw);
8400 if (err) {
8401 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8402 goto err_pf_reset;
8403 }
8404
d52c20b7
JB		 8405 /* set up a default setting for link flow control */
8406 pf->hw.fc.requested_mode = I40E_FC_NONE;
8407
41c445ff
JB		 8408 err = i40e_init_adminq(hw);
8409 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8410 if (err) {
8411 dev_info(&pdev->dev,
8412 "init_adminq failed: %d expecting API %02x.%02x\n",
8413 err,
8414 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8415 goto err_pf_reset;
8416 }
8417
4eb3f768
SN		 8418 i40e_verify_eeprom(pf);
8419
2c5fe33b
JB		 8420 /* Rev 0 hardware was never productized */
8421 if (hw->revision_id < 1)
8422 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8423
6ff4ef86 8424 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8425 err = i40e_get_capabilities(pf);
8426 if (err)
8427 goto err_adminq_setup;
8428
8429 err = i40e_sw_init(pf);
8430 if (err) {
8431 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8432 goto err_sw_init;
8433 }
8434
8435 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8436 hw->func_caps.num_rx_qp,
8437 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8438 if (err) {
8439 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8440 goto err_init_lan_hmc;
8441 }
8442
8443 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8444 if (err) {
8445 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8446 err = -ENOENT;
8447 goto err_configure_lan_hmc;
8448 }
8449
8450 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8451 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8452 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8453 err = -EIO;
8454 goto err_mac_addr;
8455 }
8456 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8457 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8458
8459 pci_set_drvdata(pdev, pf);
8460 pci_save_state(pdev);
4e3b35b0
NP		 8461#ifdef CONFIG_I40E_DCB
8462 err = i40e_init_pf_dcb(pf);
8463 if (err) {
8464 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8465 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
014269ff 8466 /* Continue without DCB enabled */
4e3b35b0
NP		 8467 }
8468#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8469
8470 /* set up periodic task facility */
8471 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8472 pf->service_timer_period = HZ;
8473
8474 INIT_WORK(&pf->service_task, i40e_service_task);
8475 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8476 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8477 pf->link_check_timeout = jiffies;
8478
8e2773ae
SN		 8479 /* WoL defaults to disabled */
8480 pf->wol_en = false;
8481 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8482
41c445ff
JB		 8483 /* set up the main switch operations */
8484 i40e_determine_queue_usage(pf);
8485 i40e_init_interrupt_scheme(pf);
8486
8487 /* Set up the *vsi struct based on the number of VSIs in the HW,
8488 * and set up our local tracking of the MAIN PF vsi.
8489 */
8490 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8491 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8492 if (!pf->vsi) {
8493 err = -ENOMEM;
41c445ff 8494 goto err_switch_setup;
ed87ac09 8495 }
41c445ff 8496
bc7d338f 8497 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8498 if (err) {
8499 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8500 goto err_vsis;
8501 }
8a9eb7d3
SN		 8502 /* if FDIR VSI was set up, start it now */
8503 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8504 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8505 i40e_vsi_open(pf->vsi[i]);
8506 break;
8507 }
8508 }
41c445ff
JB		 8509
8510 /* The main driver is (mostly) up and happy. We need to set this state
8511 * before setting up the misc vector or we get a race and the vector
8512 * ends up disabled forever.
8513 */
8514 clear_bit(__I40E_DOWN, &pf->state);
8515
8516 /* In case of MSIX we are going to setup the misc vector right here
8517 * to handle admin queue events etc. In case of legacy and MSI
8518 * the misc functionality and queue processing is combined in
8519 * the same vector and that gets setup at open.
8520 */
8521 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8522 err = i40e_setup_misc_vector(pf);
8523 if (err) {
8524 dev_info(&pdev->dev,
8525 "setup of misc vector failed: %d\n", err);
8526 goto err_vsis;
8527 }
8528 }
8529
df805f62 8530#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8531 /* prep for VF support */
8532 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8533 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8534 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8535 u32 val;
8536
8537 /* disable link interrupts for VFs */
8538 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8539 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8540 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8541 i40e_flush(hw);
4aeec010
MW		 8542
8543 if (pci_num_vf(pdev)) {
8544 dev_info(&pdev->dev,
8545 "Active VFs found, allocating resources.\n");
8546 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8547 if (err)
8548 dev_info(&pdev->dev,
8549 "Error %d allocating resources for existing VFs\n",
8550 err);
8551 }
41c445ff 8552 }
df805f62 8553#endif /* CONFIG_PCI_IOV */
41c445ff 8554
93cd765b
ASJ		 8555 pfs_found++;
8556
41c445ff
JB		 8557 i40e_dbg_pf_init(pf);
8558
8559 /* tell the firmware that we're starting */
44033fac 8560 i40e_send_version(pf);
41c445ff
JB		 8561
8562 /* since everything's happy, start the service_task timer */
8563 mod_timer(&pf->service_timer,
8564 round_jiffies(jiffies + pf->service_timer_period));
8565
d4dfb81a
CS		 8566 /* Get the negotiated link width and speed from PCI config space */
8567 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8568
8569 i40e_set_pci_config_data(hw, link_status);
8570
69bfb110 8571 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8572 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8573 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8574 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8575 "Unknown"),
8576 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8577 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8578 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8579 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8580 "Unknown"));
8581
8582 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8583 hw->bus.speed < i40e_bus_speed_8000) {
8584 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8585 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8586 }
8587
0c22b3dd
JB		 8588 /* print a string summarizing features */
8589 i40e_print_features(pf);
8590
41c445ff
JB		 8591 return 0;
8592
8593 /* Unwind what we've done if something failed in the setup */
8594err_vsis:
8595 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8596 i40e_clear_interrupt_scheme(pf);
8597 kfree(pf->vsi);
04b03013
SN		 8598err_switch_setup:
8599 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8600 del_timer_sync(&pf->service_timer);
8601err_mac_addr:
8602err_configure_lan_hmc:
8603 (void)i40e_shutdown_lan_hmc(hw);
8604err_init_lan_hmc:
8605 kfree(pf->qp_pile);
8606 kfree(pf->irq_pile);
8607err_sw_init:
8608err_adminq_setup:
8609 (void)i40e_shutdown_adminq(hw);
8610err_pf_reset:
8611 iounmap(hw->hw_addr);
8612err_ioremap:
8613 kfree(pf);
8614err_pf_alloc:
8615 pci_disable_pcie_error_reporting(pdev);
8616 pci_release_selected_regions(pdev,
8617 pci_select_bars(pdev, IORESOURCE_MEM));
8618err_pci_reg:
8619err_dma:
8620 pci_disable_device(pdev);
8621 return err;
8622}
8623
8624/**
8625 * i40e_remove - Device removal routine
8626 * @pdev: PCI device information struct
8627 *
8628 * i40e_remove is called by the PCI subsystem to alert the driver
8629 * that is should release a PCI device. This could be caused by a
8630 * Hot-Plug event, or because the driver is going to be removed from
8631 * memory.
8632 **/
8633static void i40e_remove(struct pci_dev *pdev)
8634{
8635 struct i40e_pf *pf = pci_get_drvdata(pdev);
8636 i40e_status ret_code;
8637 u32 reg;
8638 int i;
8639
8640 i40e_dbg_pf_exit(pf);
8641
beb0dff1
JK		 8642 i40e_ptp_stop(pf);
8643
41c445ff
JB		 8644 /* no more scheduling of any task */
8645 set_bit(__I40E_DOWN, &pf->state);
8646 del_timer_sync(&pf->service_timer);
8647 cancel_work_sync(&pf->service_task);
8648
eb2d80bc
MW		 8649 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8650 i40e_free_vfs(pf);
8651 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8652 }
8653
41c445ff
JB		 8654 i40e_fdir_teardown(pf);
8655
8656 /* If there is a switch structure or any orphans, remove them.
8657 * This will leave only the PF's VSI remaining.
8658 */
8659 for (i = 0; i < I40E_MAX_VEB; i++) {
8660 if (!pf->veb[i])
8661 continue;
8662
8663 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8664 pf->veb[i]->uplink_seid == 0)
8665 i40e_switch_branch_release(pf->veb[i]);
8666 }
8667
8668 /* Now we can shutdown the PF's VSI, just before we kill
8669 * adminq and hmc.
8670 */
8671 if (pf->vsi[pf->lan_vsi])
8672 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8673
8674 i40e_stop_misc_vector(pf);
8675 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8676 synchronize_irq(pf->msix_entries[0].vector);
8677 free_irq(pf->msix_entries[0].vector, pf);
8678 }
8679
8680 /* shutdown and destroy the HMC */
60442dea
SN		 8681 if (pf->hw.hmc.hmc_obj) {
8682 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8683 if (ret_code)
8684 dev_warn(&pdev->dev,
8685 "Failed to destroy the HMC resources: %d\n",
8686 ret_code);
8687 }
41c445ff
JB		 8688
8689 /* shutdown the adminq */
41c445ff
JB		 8690 ret_code = i40e_shutdown_adminq(&pf->hw);
8691 if (ret_code)
8692 dev_warn(&pdev->dev,
8693 "Failed to destroy the Admin Queue resources: %d\n",
8694 ret_code);
8695
8696 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8697 i40e_clear_interrupt_scheme(pf);
8698 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8699 if (pf->vsi[i]) {
8700 i40e_vsi_clear_rings(pf->vsi[i]);
8701 i40e_vsi_clear(pf->vsi[i]);
8702 pf->vsi[i] = NULL;
8703 }
8704 }
8705
8706 for (i = 0; i < I40E_MAX_VEB; i++) {
8707 kfree(pf->veb[i]);
8708 pf->veb[i] = NULL;
8709 }
8710
8711 kfree(pf->qp_pile);
8712 kfree(pf->irq_pile);
8713 kfree(pf->sw_config);
8714 kfree(pf->vsi);
8715
8716 /* force a PF reset to clean anything leftover */
8717 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8718 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8719 i40e_flush(&pf->hw);
8720
8721 iounmap(pf->hw.hw_addr);
8722 kfree(pf);
8723 pci_release_selected_regions(pdev,
8724 pci_select_bars(pdev, IORESOURCE_MEM));
8725
8726 pci_disable_pcie_error_reporting(pdev);
8727 pci_disable_device(pdev);
8728}
8729
8730/**
8731 * i40e_pci_error_detected - warning that something funky happened in PCI land
8732 * @pdev: PCI device information struct
8733 *
8734 * Called to warn that something happened and the error handling steps
8735 * are in progress. Allows the driver to quiesce things, be ready for
8736 * remediation.
8737 **/
8738static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8739 enum pci_channel_state error)
8740{
8741 struct i40e_pf *pf = pci_get_drvdata(pdev);
8742
8743 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8744
8745 /* shutdown all operations */
9007bccd
SN		 8746 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8747 rtnl_lock();
8748 i40e_prep_for_reset(pf);
8749 rtnl_unlock();
8750 }
41c445ff
JB		 8751
8752 /* Request a slot reset */
8753 return PCI_ERS_RESULT_NEED_RESET;
8754}
8755
8756/**
8757 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8758 * @pdev: PCI device information struct
8759 *
8760 * Called to find if the driver can work with the device now that
8761 * the pci slot has been reset. If a basic connection seems good
8762 * (registers are readable and have sane content) then return a
8763 * happy little PCI_ERS_RESULT_xxx.
8764 **/
8765static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8766{
8767 struct i40e_pf *pf = pci_get_drvdata(pdev);
8768 pci_ers_result_t result;
8769 int err;
8770 u32 reg;
8771
8772 dev_info(&pdev->dev, "%s\n", __func__);
8773 if (pci_enable_device_mem(pdev)) {
8774 dev_info(&pdev->dev,
8775 "Cannot re-enable PCI device after reset.\n");
8776 result = PCI_ERS_RESULT_DISCONNECT;
8777 } else {
8778 pci_set_master(pdev);
8779 pci_restore_state(pdev);
8780 pci_save_state(pdev);
8781 pci_wake_from_d3(pdev, false);
8782
8783 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8784 if (reg == 0)
8785 result = PCI_ERS_RESULT_RECOVERED;
8786 else
8787 result = PCI_ERS_RESULT_DISCONNECT;
8788 }
8789
8790 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8791 if (err) {
8792 dev_info(&pdev->dev,
8793 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8794 err);
8795 /* non-fatal, continue */
8796 }
8797
8798 return result;
8799}
8800
8801/**
8802 * i40e_pci_error_resume - restart operations after PCI error recovery
8803 * @pdev: PCI device information struct
8804 *
8805 * Called to allow the driver to bring things back up after PCI error
8806 * and/or reset recovery has finished.
8807 **/
8808static void i40e_pci_error_resume(struct pci_dev *pdev)
8809{
8810 struct i40e_pf *pf = pci_get_drvdata(pdev);
8811
8812 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8813 if (test_bit(__I40E_SUSPENDED, &pf->state))
8814 return;
8815
8816 rtnl_lock();
41c445ff 8817 i40e_handle_reset_warning(pf);
9007bccd
SN		 8818 rtnl_lock();
8819}
8820
8821/**
8822 * i40e_shutdown - PCI callback for shutting down
8823 * @pdev: PCI device information struct
8824 **/
8825static void i40e_shutdown(struct pci_dev *pdev)
8826{
8827 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8828 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8829
8830 set_bit(__I40E_SUSPENDED, &pf->state);
8831 set_bit(__I40E_DOWN, &pf->state);
8832 rtnl_lock();
8833 i40e_prep_for_reset(pf);
8834 rtnl_unlock();
8835
8e2773ae
SN		 8836 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8837 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8838
9007bccd 8839 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8840 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8841 pci_set_power_state(pdev, PCI_D3hot);
8842 }
8843}
8844
8845#ifdef CONFIG_PM
8846/**
8847 * i40e_suspend - PCI callback for moving to D3
8848 * @pdev: PCI device information struct
8849 **/
8850static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8851{
8852 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8853 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8854
8855 set_bit(__I40E_SUSPENDED, &pf->state);
8856 set_bit(__I40E_DOWN, &pf->state);
8857 rtnl_lock();
8858 i40e_prep_for_reset(pf);
8859 rtnl_unlock();
8860
8e2773ae
SN		 8861 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8862 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8863
8864 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8865 pci_set_power_state(pdev, PCI_D3hot);
8866
8867 return 0;
41c445ff
JB		 8868}
8869
9007bccd
SN		 8870/**
8871 * i40e_resume - PCI callback for waking up from D3
8872 * @pdev: PCI device information struct
8873 **/
8874static int i40e_resume(struct pci_dev *pdev)
8875{
8876 struct i40e_pf *pf = pci_get_drvdata(pdev);
8877 u32 err;
8878
8879 pci_set_power_state(pdev, PCI_D0);
8880 pci_restore_state(pdev);
8881 /* pci_restore_state() clears dev->state_saves, so
8882 * call pci_save_state() again to restore it.
8883 */
8884 pci_save_state(pdev);
8885
8886 err = pci_enable_device_mem(pdev);
8887 if (err) {
8888 dev_err(&pdev->dev,
8889 "%s: Cannot enable PCI device from suspend\n",
8890 __func__);
8891 return err;
8892 }
8893 pci_set_master(pdev);
8894
8895 /* no wakeup events while running */
8896 pci_wake_from_d3(pdev, false);
8897
8898 /* handling the reset will rebuild the device state */
8899 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8900 clear_bit(__I40E_DOWN, &pf->state);
8901 rtnl_lock();
8902 i40e_reset_and_rebuild(pf, false);
8903 rtnl_unlock();
8904 }
8905
8906 return 0;
8907}
8908
8909#endif
41c445ff
JB		 8910static const struct pci_error_handlers i40e_err_handler = {
8911 .error_detected = i40e_pci_error_detected,
8912 .slot_reset = i40e_pci_error_slot_reset,
8913 .resume = i40e_pci_error_resume,
8914};
8915
8916static struct pci_driver i40e_driver = {
8917 .name = i40e_driver_name,
8918 .id_table = i40e_pci_tbl,
8919 .probe = i40e_probe,
8920 .remove = i40e_remove,
9007bccd
SN		 8921#ifdef CONFIG_PM
8922 .suspend = i40e_suspend,
8923 .resume = i40e_resume,
8924#endif
8925 .shutdown = i40e_shutdown,
41c445ff
JB		 8926 .err_handler = &i40e_err_handler,
8927 .sriov_configure = i40e_pci_sriov_configure,
8928};
8929
8930/**
8931 * i40e_init_module - Driver registration routine
8932 *
8933 * i40e_init_module is the first routine called when the driver is
8934 * loaded. All it does is register with the PCI subsystem.
8935 **/
8936static int __init i40e_init_module(void)
8937{
8938 pr_info("%s: %s - version %s\n", i40e_driver_name,
8939 i40e_driver_string, i40e_driver_version_str);
8940 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8941 i40e_dbg_init();
8942 return pci_register_driver(&i40e_driver);
8943}
8944module_init(i40e_init_module);
8945
8946/**
8947 * i40e_exit_module - Driver exit cleanup routine
8948 *
8949 * i40e_exit_module is called just before the driver is removed
8950 * from memory.
8951 **/
8952static void __exit i40e_exit_module(void)
8953{
8954 pci_unregister_driver(&i40e_driver);
8955 i40e_dbg_exit();
8956}
8957module_exit(i40e_exit_module);
Linux kernel - Deliverables
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