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ipv6: hash net ptr into fragmentation bucket selection
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
a36fdd8e 41#define DRV_VERSION_MINOR 2
ec7a06fd 42#define DRV_VERSION_BUILD 37
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
b40c82e6 453 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc 898/**
b40c82e6 899 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
532d283d
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
923 I40E_GLPRT_UPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_unicast,
926 &nsd->eth.rx_unicast);
7812fddc
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
928 I40E_GLPRT_MPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_multicast,
931 &nsd->eth.rx_multicast);
532d283d
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
933 I40E_GLPRT_BPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_broadcast,
936 &nsd->eth.rx_broadcast);
937 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
938 I40E_GLPRT_UPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_unicast,
941 &nsd->eth.tx_unicast);
942 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
943 I40E_GLPRT_MPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_multicast,
946 &nsd->eth.tx_multicast);
947 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
948 I40E_GLPRT_BPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_broadcast,
951 &nsd->eth.tx_broadcast);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_dropped_link_down,
956 &nsd->tx_dropped_link_down);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->crc_errors, &nsd->crc_errors);
41c445ff 961
7812fddc
SN		 962 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 965
7812fddc
SN		 966 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->mac_local_faults,
969 &nsd->mac_local_faults);
970 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->mac_remote_faults,
973 &nsd->mac_remote_faults);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->rx_length_errors,
978 &nsd->rx_length_errors);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->link_xon_rx, &nsd->link_xon_rx);
983 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->link_xon_tx, &nsd->link_xon_tx);
986 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
987 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 990
7812fddc
SN		 991 for (i = 0; i < 8; i++) {
992 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 993 pf->stat_offsets_loaded,
7812fddc
SN		 994 &osd->priority_xon_rx[i],
995 &nsd->priority_xon_rx[i]);
996 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 997 pf->stat_offsets_loaded,
7812fddc
SN		 998 &osd->priority_xon_tx[i],
999 &nsd->priority_xon_tx[i]);
1000 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xoff_tx[i],
1003 &nsd->priority_xoff_tx[i]);
1004 i40e_stat_update32(hw,
1005 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xon_2_xoff[i],
1008 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1009 }
1010
7812fddc
SN		 1011 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1012 I40E_GLPRT_PRC64L(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_size_64, &nsd->rx_size_64);
1015 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1016 I40E_GLPRT_PRC127L(hw->port),
1017 pf->stat_offsets_loaded,
1018 &osd->rx_size_127, &nsd->rx_size_127);
1019 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1020 I40E_GLPRT_PRC255L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_255, &nsd->rx_size_255);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1024 I40E_GLPRT_PRC511L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_511, &nsd->rx_size_511);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1028 I40E_GLPRT_PRC1023L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_1023, &nsd->rx_size_1023);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1032 I40E_GLPRT_PRC1522L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_1522, &nsd->rx_size_1522);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1036 I40E_GLPRT_PRC9522L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_big, &nsd->rx_size_big);
1039
1040 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1041 I40E_GLPRT_PTC64L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->tx_size_64, &nsd->tx_size_64);
1044 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1045 I40E_GLPRT_PTC127L(hw->port),
1046 pf->stat_offsets_loaded,
1047 &osd->tx_size_127, &nsd->tx_size_127);
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1049 I40E_GLPRT_PTC255L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_255, &nsd->tx_size_255);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1053 I40E_GLPRT_PTC511L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_511, &nsd->tx_size_511);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1057 I40E_GLPRT_PTC1023L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_1023, &nsd->tx_size_1023);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1061 I40E_GLPRT_PTC1522L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_1522, &nsd->tx_size_1522);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1065 I40E_GLPRT_PTC9522L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_big, &nsd->tx_size_big);
1068
1069 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->rx_undersize, &nsd->rx_undersize);
1072 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1073 pf->stat_offsets_loaded,
1074 &osd->rx_fragments, &nsd->rx_fragments);
1075 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1076 pf->stat_offsets_loaded,
1077 &osd->rx_oversize, &nsd->rx_oversize);
1078 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1079 pf->stat_offsets_loaded,
1080 &osd->rx_jabber, &nsd->rx_jabber);
1081
433c47de
ASJ		 1082 /* FDIR stats */
1083 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1084 pf->stat_offsets_loaded,
1085 &osd->fd_atr_match, &nsd->fd_atr_match);
1086 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1087 pf->stat_offsets_loaded,
1088 &osd->fd_sb_match, &nsd->fd_sb_match);
1089
7812fddc
SN		 1090 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1091 nsd->tx_lpi_status =
1092 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1093 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1094 nsd->rx_lpi_status =
1095 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1096 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1097 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1098 pf->stat_offsets_loaded,
1099 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1100 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1101 pf->stat_offsets_loaded,
1102 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1103
41c445ff
JB		 1104 pf->stat_offsets_loaded = true;
1105}
1106
7812fddc
SN		 1107/**
1108 * i40e_update_stats - Update the various statistics counters.
1109 * @vsi: the VSI to be updated
1110 *
1111 * Update the various stats for this VSI and its related entities.
1112 **/
1113void i40e_update_stats(struct i40e_vsi *vsi)
1114{
1115 struct i40e_pf *pf = vsi->back;
1116
1117 if (vsi == pf->vsi[pf->lan_vsi])
1118 i40e_update_pf_stats(pf);
1119
1120 i40e_update_vsi_stats(vsi);
38e00438
VD		 1121#ifdef I40E_FCOE
1122 i40e_update_fcoe_stats(vsi);
1123#endif
7812fddc
SN		 1124}
1125
41c445ff
JB		 1126/**
1127 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1128 * @vsi: the VSI to be searched
1129 * @macaddr: the MAC address
1130 * @vlan: the vlan
b40c82e6 1131 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1132 * @is_netdev: make sure its a netdev filter, else doesn't matter
1133 *
1134 * Returns ptr to the filter object or NULL
1135 **/
1136static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1137 u8 *macaddr, s16 vlan,
1138 bool is_vf, bool is_netdev)
1139{
1140 struct i40e_mac_filter *f;
1141
1142 if (!vsi || !macaddr)
1143 return NULL;
1144
1145 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1146 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1147 (vlan == f->vlan) &&
1148 (!is_vf || f->is_vf) &&
1149 (!is_netdev || f->is_netdev))
1150 return f;
1151 }
1152 return NULL;
1153}
1154
1155/**
1156 * i40e_find_mac - Find a mac addr in the macvlan filters list
1157 * @vsi: the VSI to be searched
1158 * @macaddr: the MAC address we are searching for
b40c82e6 1159 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1160 * @is_netdev: make sure its a netdev filter, else doesn't matter
1161 *
1162 * Returns the first filter with the provided MAC address or NULL if
1163 * MAC address was not found
1164 **/
1165struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1166 bool is_vf, bool is_netdev)
1167{
1168 struct i40e_mac_filter *f;
1169
1170 if (!vsi || !macaddr)
1171 return NULL;
1172
1173 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1174 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1175 (!is_vf || f->is_vf) &&
1176 (!is_netdev || f->is_netdev))
1177 return f;
1178 }
1179 return NULL;
1180}
1181
1182/**
1183 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1184 * @vsi: the VSI to be searched
1185 *
1186 * Returns true if VSI is in vlan mode or false otherwise
1187 **/
1188bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1189{
1190 struct i40e_mac_filter *f;
1191
1192 /* Only -1 for all the filters denotes not in vlan mode
1193 * so we have to go through all the list in order to make sure
1194 */
1195 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1196 if (f->vlan >= 0)
1197 return true;
1198 }
1199
1200 return false;
1201}
1202
1203/**
1204 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1205 * @vsi: the VSI to be searched
1206 * @macaddr: the mac address to be filtered
b40c82e6 1207 * @is_vf: true if it is a VF
41c445ff
JB		 1208 * @is_netdev: true if it is a netdev
1209 *
1210 * Goes through all the macvlan filters and adds a
1211 * macvlan filter for each unique vlan that already exists
1212 *
1213 * Returns first filter found on success, else NULL
1214 **/
1215struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1216 bool is_vf, bool is_netdev)
1217{
1218 struct i40e_mac_filter *f;
1219
1220 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1221 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1222 is_vf, is_netdev)) {
1223 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1224 is_vf, is_netdev))
41c445ff
JB		 1225 return NULL;
1226 }
1227 }
1228
1229 return list_first_entry_or_null(&vsi->mac_filter_list,
1230 struct i40e_mac_filter, list);
1231}
1232
8c27d42e
GR		 1233/**
1234 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1235 * @vsi: the PF Main VSI - inappropriate for any other VSI
1236 * @macaddr: the MAC address
30650cc5
SN		 1237 *
1238 * Some older firmware configurations set up a default promiscuous VLAN
1239 * filter that needs to be removed.
8c27d42e 1240 **/
30650cc5 1241static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1242{
1243 struct i40e_aqc_remove_macvlan_element_data element;
1244 struct i40e_pf *pf = vsi->back;
1245 i40e_status aq_ret;
1246
1247 /* Only appropriate for the PF main VSI */
1248 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1249 return -EINVAL;
8c27d42e 1250
30650cc5 1251 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1252 ether_addr_copy(element.mac_addr, macaddr);
1253 element.vlan_tag = 0;
1254 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1255 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1256 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1257 if (aq_ret)
30650cc5
SN		 1258 return -ENOENT;
1259
1260 return 0;
8c27d42e
GR		 1261}
1262
41c445ff
JB		 1263/**
1264 * i40e_add_filter - Add a mac/vlan filter to the VSI
1265 * @vsi: the VSI to be searched
1266 * @macaddr: the MAC address
1267 * @vlan: the vlan
b40c82e6 1268 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1269 * @is_netdev: make sure its a netdev filter, else doesn't matter
1270 *
1271 * Returns ptr to the filter object or NULL when no memory available.
1272 **/
1273struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1274 u8 *macaddr, s16 vlan,
1275 bool is_vf, bool is_netdev)
1276{
1277 struct i40e_mac_filter *f;
1278
1279 if (!vsi || !macaddr)
1280 return NULL;
1281
1282 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1283 if (!f) {
1284 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1285 if (!f)
1286 goto add_filter_out;
1287
9a173901 1288 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1289 f->vlan = vlan;
1290 f->changed = true;
1291
1292 INIT_LIST_HEAD(&f->list);
1293 list_add(&f->list, &vsi->mac_filter_list);
1294 }
1295
1296 /* increment counter and add a new flag if needed */
1297 if (is_vf) {
1298 if (!f->is_vf) {
1299 f->is_vf = true;
1300 f->counter++;
1301 }
1302 } else if (is_netdev) {
1303 if (!f->is_netdev) {
1304 f->is_netdev = true;
1305 f->counter++;
1306 }
1307 } else {
1308 f->counter++;
1309 }
1310
1311 /* changed tells sync_filters_subtask to
1312 * push the filter down to the firmware
1313 */
1314 if (f->changed) {
1315 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1316 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1317 }
1318
1319add_filter_out:
1320 return f;
1321}
1322
1323/**
1324 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1325 * @vsi: the VSI to be searched
1326 * @macaddr: the MAC address
1327 * @vlan: the vlan
b40c82e6 1328 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff
JB		 1329 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1330 **/
1331void i40e_del_filter(struct i40e_vsi *vsi,
1332 u8 *macaddr, s16 vlan,
1333 bool is_vf, bool is_netdev)
1334{
1335 struct i40e_mac_filter *f;
1336
1337 if (!vsi || !macaddr)
1338 return;
1339
1340 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1341 if (!f || f->counter == 0)
1342 return;
1343
1344 if (is_vf) {
1345 if (f->is_vf) {
1346 f->is_vf = false;
1347 f->counter--;
1348 }
1349 } else if (is_netdev) {
1350 if (f->is_netdev) {
1351 f->is_netdev = false;
1352 f->counter--;
1353 }
1354 } else {
b40c82e6 1355 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff
JB		 1356 int min_f = 0;
1357 min_f += (f->is_vf ? 1 : 0);
1358 min_f += (f->is_netdev ? 1 : 0);
1359
1360 if (f->counter > min_f)
1361 f->counter--;
1362 }
1363
1364 /* counter == 0 tells sync_filters_subtask to
1365 * remove the filter from the firmware's list
1366 */
1367 if (f->counter == 0) {
1368 f->changed = true;
1369 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1370 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1371 }
1372}
1373
1374/**
1375 * i40e_set_mac - NDO callback to set mac address
1376 * @netdev: network interface device structure
1377 * @p: pointer to an address structure
1378 *
1379 * Returns 0 on success, negative on failure
1380 **/
38e00438
VD		 1381#ifdef I40E_FCOE
1382int i40e_set_mac(struct net_device *netdev, void *p)
1383#else
41c445ff 1384static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1385#endif
41c445ff
JB		 1386{
1387 struct i40e_netdev_priv *np = netdev_priv(netdev);
1388 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1389 struct i40e_pf *pf = vsi->back;
1390 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1391 struct sockaddr *addr = p;
1392 struct i40e_mac_filter *f;
1393
1394 if (!is_valid_ether_addr(addr->sa_data))
1395 return -EADDRNOTAVAIL;
1396
30650cc5
SN		 1397 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1398 netdev_info(netdev, "already using mac address %pM\n",
1399 addr->sa_data);
1400 return 0;
1401 }
41c445ff 1402
80f6428f
ASJ		 1403 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1404 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1405 return -EADDRNOTAVAIL;
1406
30650cc5
SN		 1407 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1408 netdev_info(netdev, "returning to hw mac address %pM\n",
1409 hw->mac.addr);
1410 else
1411 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1412
41c445ff
JB		 1413 if (vsi->type == I40E_VSI_MAIN) {
1414 i40e_status ret;
1415 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1416 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1417 addr->sa_data, NULL);
1418 if (ret) {
1419 netdev_info(netdev,
1420 "Addr change for Main VSI failed: %d\n",
1421 ret);
1422 return -EADDRNOTAVAIL;
1423 }
41c445ff
JB		 1424 }
1425
30650cc5
SN		 1426 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1427 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1428
30650cc5
SN		 1429 memset(&element, 0, sizeof(element));
1430 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1431 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1432 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1433 } else {
6c8ad1ba
SN		 1434 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1435 false, false);
6c8ad1ba 1436 }
41c445ff 1437
30650cc5
SN		 1438 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1439 struct i40e_aqc_add_macvlan_element_data element;
1440
1441 memset(&element, 0, sizeof(element));
1442 ether_addr_copy(element.mac_addr, hw->mac.addr);
1443 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1444 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1445 } else {
1446 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1447 false, false);
1448 if (f)
1449 f->is_laa = true;
1450 }
1451
1452 i40e_sync_vsi_filters(vsi);
1453 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1454
1455 return 0;
1456}
1457
1458/**
1459 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1460 * @vsi: the VSI being setup
1461 * @ctxt: VSI context structure
1462 * @enabled_tc: Enabled TCs bitmap
1463 * @is_add: True if called before Add VSI
1464 *
1465 * Setup VSI queue mapping for enabled traffic classes.
1466 **/
38e00438
VD		 1467#ifdef I40E_FCOE
1468void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1469 struct i40e_vsi_context *ctxt,
1470 u8 enabled_tc,
1471 bool is_add)
1472#else
41c445ff
JB		 1473static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
38e00438 1477#endif
41c445ff
JB		 1478{
1479 struct i40e_pf *pf = vsi->back;
1480 u16 sections = 0;
1481 u8 netdev_tc = 0;
1482 u16 numtc = 0;
1483 u16 qcount;
1484 u8 offset;
1485 u16 qmap;
1486 int i;
4e3b35b0 1487 u16 num_tc_qps = 0;
41c445ff
JB		 1488
1489 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1490 offset = 0;
1491
1492 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1493 /* Find numtc from enabled TC bitmap */
1494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1495 if (enabled_tc & (1 << i)) /* TC is enabled */
1496 numtc++;
1497 }
1498 if (!numtc) {
1499 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1500 numtc = 1;
1501 }
1502 } else {
1503 /* At least TC0 is enabled in case of non-DCB case */
1504 numtc = 1;
1505 }
1506
1507 vsi->tc_config.numtc = numtc;
1508 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1509 /* Number of queues per enabled TC */
7f9ff476
AS		 1510 /* In MFP case we can have a much lower count of MSIx
1511 * vectors available and so we need to lower the used
1512 * q count.
1513 */
1514 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1515 num_tc_qps = qcount / numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1543
1e200e4a 1544 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1574 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1575 if (vsi->req_queue_pairs > 0)
1576 vsi->num_queue_pairs = vsi->req_queue_pairs;
1577 else
1578 vsi->num_queue_pairs = pf->num_lan_msix;
1579 }
41c445ff
JB		 1580
1581 /* Scheduler section valid can only be set for ADD VSI */
1582 if (is_add) {
1583 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1584
1585 ctxt->info.up_enable_bits = enabled_tc;
1586 }
1587 if (vsi->type == I40E_VSI_SRIOV) {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1590 for (i = 0; i < vsi->num_queue_pairs; i++)
1591 ctxt->info.queue_mapping[i] =
1592 cpu_to_le16(vsi->base_queue + i);
1593 } else {
1594 ctxt->info.mapping_flags |=
1595 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1596 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1597 }
1598 ctxt->info.valid_sections |= cpu_to_le16(sections);
1599}
1600
1601/**
1602 * i40e_set_rx_mode - NDO callback to set the netdev filters
1603 * @netdev: network interface device structure
1604 **/
38e00438
VD		 1605#ifdef I40E_FCOE
1606void i40e_set_rx_mode(struct net_device *netdev)
1607#else
41c445ff 1608static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1609#endif
41c445ff
JB		 1610{
1611 struct i40e_netdev_priv *np = netdev_priv(netdev);
1612 struct i40e_mac_filter *f, *ftmp;
1613 struct i40e_vsi *vsi = np->vsi;
1614 struct netdev_hw_addr *uca;
1615 struct netdev_hw_addr *mca;
1616 struct netdev_hw_addr *ha;
1617
1618 /* add addr if not already in the filter list */
1619 netdev_for_each_uc_addr(uca, netdev) {
1620 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1621 if (i40e_is_vsi_in_vlan(vsi))
1622 i40e_put_mac_in_vlan(vsi, uca->addr,
1623 false, true);
1624 else
1625 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1626 false, true);
1627 }
1628 }
1629
1630 netdev_for_each_mc_addr(mca, netdev) {
1631 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1632 if (i40e_is_vsi_in_vlan(vsi))
1633 i40e_put_mac_in_vlan(vsi, mca->addr,
1634 false, true);
1635 else
1636 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1637 false, true);
1638 }
1639 }
1640
1641 /* remove filter if not in netdev list */
1642 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1643 bool found = false;
1644
1645 if (!f->is_netdev)
1646 continue;
1647
1648 if (is_multicast_ether_addr(f->macaddr)) {
1649 netdev_for_each_mc_addr(mca, netdev) {
1650 if (ether_addr_equal(mca->addr, f->macaddr)) {
1651 found = true;
1652 break;
1653 }
1654 }
1655 } else {
1656 netdev_for_each_uc_addr(uca, netdev) {
1657 if (ether_addr_equal(uca->addr, f->macaddr)) {
1658 found = true;
1659 break;
1660 }
1661 }
1662
1663 for_each_dev_addr(netdev, ha) {
1664 if (ether_addr_equal(ha->addr, f->macaddr)) {
1665 found = true;
1666 break;
1667 }
1668 }
1669 }
1670 if (!found)
1671 i40e_del_filter(
1672 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1673 }
1674
1675 /* check for other flag changes */
1676 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1677 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1678 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1679 }
1680}
1681
1682/**
1683 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1684 * @vsi: ptr to the VSI
1685 *
1686 * Push any outstanding VSI filter changes through the AdminQ.
1687 *
1688 * Returns 0 or error value
1689 **/
1690int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1691{
1692 struct i40e_mac_filter *f, *ftmp;
1693 bool promisc_forced_on = false;
1694 bool add_happened = false;
1695 int filter_list_len = 0;
1696 u32 changed_flags = 0;
dcae29be 1697 i40e_status aq_ret = 0;
41c445ff
JB		 1698 struct i40e_pf *pf;
1699 int num_add = 0;
1700 int num_del = 0;
1701 u16 cmd_flags;
1702
1703 /* empty array typed pointers, kcalloc later */
1704 struct i40e_aqc_add_macvlan_element_data *add_list;
1705 struct i40e_aqc_remove_macvlan_element_data *del_list;
1706
1707 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1708 usleep_range(1000, 2000);
1709 pf = vsi->back;
1710
1711 if (vsi->netdev) {
1712 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1713 vsi->current_netdev_flags = vsi->netdev->flags;
1714 }
1715
1716 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1717 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1718
1719 filter_list_len = pf->hw.aq.asq_buf_size /
1720 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1721 del_list = kcalloc(filter_list_len,
1722 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1723 GFP_KERNEL);
1724 if (!del_list)
1725 return -ENOMEM;
1726
1727 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1728 if (!f->changed)
1729 continue;
1730
1731 if (f->counter != 0)
1732 continue;
1733 f->changed = false;
1734 cmd_flags = 0;
1735
1736 /* add to delete list */
9a173901 1737 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1738 del_list[num_del].vlan_tag =
1739 cpu_to_le16((u16)(f->vlan ==
1740 I40E_VLAN_ANY ? 0 : f->vlan));
1741
41c445ff
JB		 1742 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1743 del_list[num_del].flags = cmd_flags;
1744 num_del++;
1745
1746 /* unlink from filter list */
1747 list_del(&f->list);
1748 kfree(f);
1749
1750 /* flush a full buffer */
1751 if (num_del == filter_list_len) {
dcae29be 1752 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1753 vsi->seid, del_list, num_del,
1754 NULL);
1755 num_del = 0;
1756 memset(del_list, 0, sizeof(*del_list));
1757
fdfe9cbe
SN		 1758 if (aq_ret &&
1759 pf->hw.aq.asq_last_status !=
1760 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1761 dev_info(&pf->pdev->dev,
1762 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1763 aq_ret,
41c445ff
JB		 1764 pf->hw.aq.asq_last_status);
1765 }
1766 }
1767 if (num_del) {
dcae29be 1768 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1769 del_list, num_del, NULL);
1770 num_del = 0;
1771
fdfe9cbe
SN		 1772 if (aq_ret &&
1773 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1774 dev_info(&pf->pdev->dev,
1775 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1776 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1777 }
1778
1779 kfree(del_list);
1780 del_list = NULL;
1781
1782 /* do all the adds now */
1783 filter_list_len = pf->hw.aq.asq_buf_size /
1784 sizeof(struct i40e_aqc_add_macvlan_element_data),
1785 add_list = kcalloc(filter_list_len,
1786 sizeof(struct i40e_aqc_add_macvlan_element_data),
1787 GFP_KERNEL);
1788 if (!add_list)
1789 return -ENOMEM;
1790
1791 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1792 if (!f->changed)
1793 continue;
1794
1795 if (f->counter == 0)
1796 continue;
1797 f->changed = false;
1798 add_happened = true;
1799 cmd_flags = 0;
1800
1801 /* add to add array */
9a173901 1802 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1803 add_list[num_add].vlan_tag =
1804 cpu_to_le16(
1805 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1806 add_list[num_add].queue_number = 0;
1807
1808 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1809 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1810 num_add++;
1811
1812 /* flush a full buffer */
1813 if (num_add == filter_list_len) {
dcae29be
JB		 1814 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1815 add_list, num_add,
1816 NULL);
41c445ff
JB		 1817 num_add = 0;
1818
dcae29be 1819 if (aq_ret)
41c445ff
JB		 1820 break;
1821 memset(add_list, 0, sizeof(*add_list));
1822 }
1823 }
1824 if (num_add) {
dcae29be
JB		 1825 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1826 add_list, num_add, NULL);
41c445ff
JB		 1827 num_add = 0;
1828 }
1829 kfree(add_list);
1830 add_list = NULL;
1831
30650cc5
SN		 1832 if (add_happened && aq_ret &&
1833 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1834 dev_info(&pf->pdev->dev,
1835 "add filter failed, err %d, aq_err %d\n",
dcae29be 1836 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1837 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1838 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1839 &vsi->state)) {
1840 promisc_forced_on = true;
1841 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1842 &vsi->state);
1843 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1844 }
1845 }
1846 }
1847
1848 /* check for changes in promiscuous modes */
1849 if (changed_flags & IFF_ALLMULTI) {
1850 bool cur_multipromisc;
1851 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1852 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1853 vsi->seid,
1854 cur_multipromisc,
1855 NULL);
1856 if (aq_ret)
41c445ff
JB		 1857 dev_info(&pf->pdev->dev,
1858 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1859 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1860 }
1861 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1862 bool cur_promisc;
1863 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1864 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1865 &vsi->state));
dcae29be
JB		 1866 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1867 vsi->seid,
1868 cur_promisc, NULL);
1869 if (aq_ret)
41c445ff
JB		 1870 dev_info(&pf->pdev->dev,
1871 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1872 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1873 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1874 vsi->seid,
1875 cur_promisc, NULL);
1876 if (aq_ret)
1877 dev_info(&pf->pdev->dev,
1878 "set brdcast promisc failed, err %d, aq_err %d\n",
1879 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1880 }
1881
1882 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1883 return 0;
1884}
1885
1886/**
1887 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1888 * @pf: board private structure
1889 **/
1890static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1891{
1892 int v;
1893
1894 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1895 return;
1896 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1897
505682cd 1898 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1899 if (pf->vsi[v] &&
1900 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1901 i40e_sync_vsi_filters(pf->vsi[v]);
1902 }
1903}
1904
1905/**
1906 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1907 * @netdev: network interface device structure
1908 * @new_mtu: new value for maximum frame size
1909 *
1910 * Returns 0 on success, negative on failure
1911 **/
1912static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1913{
1914 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1915 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1916 struct i40e_vsi *vsi = np->vsi;
1917
1918 /* MTU < 68 is an error and causes problems on some kernels */
1919 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1920 return -EINVAL;
1921
1922 netdev_info(netdev, "changing MTU from %d to %d\n",
1923 netdev->mtu, new_mtu);
1924 netdev->mtu = new_mtu;
1925 if (netif_running(netdev))
1926 i40e_vsi_reinit_locked(vsi);
1927
1928 return 0;
1929}
1930
beb0dff1
JK		 1931/**
1932 * i40e_ioctl - Access the hwtstamp interface
1933 * @netdev: network interface device structure
1934 * @ifr: interface request data
1935 * @cmd: ioctl command
1936 **/
1937int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1938{
1939 struct i40e_netdev_priv *np = netdev_priv(netdev);
1940 struct i40e_pf *pf = np->vsi->back;
1941
1942 switch (cmd) {
1943 case SIOCGHWTSTAMP:
1944 return i40e_ptp_get_ts_config(pf, ifr);
1945 case SIOCSHWTSTAMP:
1946 return i40e_ptp_set_ts_config(pf, ifr);
1947 default:
1948 return -EOPNOTSUPP;
1949 }
1950}
1951
41c445ff
JB		 1952/**
1953 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1954 * @vsi: the vsi being adjusted
1955 **/
1956void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1957{
1958 struct i40e_vsi_context ctxt;
1959 i40e_status ret;
1960
1961 if ((vsi->info.valid_sections &
1962 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1963 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1964 return; /* already enabled */
1965
1966 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1967 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1968 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1969
1970 ctxt.seid = vsi->seid;
1971 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1972 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1973 if (ret) {
1974 dev_info(&vsi->back->pdev->dev,
1975 "%s: update vsi failed, aq_err=%d\n",
1976 __func__, vsi->back->hw.aq.asq_last_status);
1977 }
1978}
1979
1980/**
1981 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1982 * @vsi: the vsi being adjusted
1983 **/
1984void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1985{
1986 struct i40e_vsi_context ctxt;
1987 i40e_status ret;
1988
1989 if ((vsi->info.valid_sections &
1990 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1991 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1992 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1993 return; /* already disabled */
1994
1995 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1996 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1997 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1998
1999 ctxt.seid = vsi->seid;
2000 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2001 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2002 if (ret) {
2003 dev_info(&vsi->back->pdev->dev,
2004 "%s: update vsi failed, aq_err=%d\n",
2005 __func__, vsi->back->hw.aq.asq_last_status);
2006 }
2007}
2008
2009/**
2010 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2011 * @netdev: network interface to be adjusted
2012 * @features: netdev features to test if VLAN offload is enabled or not
2013 **/
2014static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2015{
2016 struct i40e_netdev_priv *np = netdev_priv(netdev);
2017 struct i40e_vsi *vsi = np->vsi;
2018
2019 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2020 i40e_vlan_stripping_enable(vsi);
2021 else
2022 i40e_vlan_stripping_disable(vsi);
2023}
2024
2025/**
2026 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2027 * @vsi: the vsi being configured
2028 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2029 **/
2030int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2031{
2032 struct i40e_mac_filter *f, *add_f;
2033 bool is_netdev, is_vf;
41c445ff
JB		 2034
2035 is_vf = (vsi->type == I40E_VSI_SRIOV);
2036 is_netdev = !!(vsi->netdev);
2037
2038 if (is_netdev) {
2039 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2040 is_vf, is_netdev);
2041 if (!add_f) {
2042 dev_info(&vsi->back->pdev->dev,
2043 "Could not add vlan filter %d for %pM\n",
2044 vid, vsi->netdev->dev_addr);
2045 return -ENOMEM;
2046 }
2047 }
2048
2049 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2050 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2051 if (!add_f) {
2052 dev_info(&vsi->back->pdev->dev,
2053 "Could not add vlan filter %d for %pM\n",
2054 vid, f->macaddr);
2055 return -ENOMEM;
2056 }
2057 }
2058
41c445ff
JB		 2059 /* Now if we add a vlan tag, make sure to check if it is the first
2060 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2061 * with 0, so we now accept untagged and specified tagged traffic
2062 * (and not any taged and untagged)
2063 */
2064 if (vid > 0) {
2065 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2066 I40E_VLAN_ANY,
2067 is_vf, is_netdev)) {
2068 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2069 I40E_VLAN_ANY, is_vf, is_netdev);
2070 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2071 is_vf, is_netdev);
2072 if (!add_f) {
2073 dev_info(&vsi->back->pdev->dev,
2074 "Could not add filter 0 for %pM\n",
2075 vsi->netdev->dev_addr);
2076 return -ENOMEM;
2077 }
2078 }
8d82a7c5 2079 }
41c445ff 2080
8d82a7c5
GR		 2081 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2082 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2083 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2084 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2085 is_vf, is_netdev)) {
2086 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2087 is_vf, is_netdev);
2088 add_f = i40e_add_filter(vsi, f->macaddr,
2089 0, is_vf, is_netdev);
2090 if (!add_f) {
2091 dev_info(&vsi->back->pdev->dev,
2092 "Could not add filter 0 for %pM\n",
2093 f->macaddr);
2094 return -ENOMEM;
2095 }
2096 }
2097 }
41c445ff
JB		 2098 }
2099
80f6428f
ASJ		 2100 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2101 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2102 return 0;
2103
2104 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2105}
2106
2107/**
2108 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2109 * @vsi: the vsi being configured
2110 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2111 *
2112 * Return: 0 on success or negative otherwise
41c445ff
JB		 2113 **/
2114int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2115{
2116 struct net_device *netdev = vsi->netdev;
2117 struct i40e_mac_filter *f, *add_f;
2118 bool is_vf, is_netdev;
2119 int filter_count = 0;
41c445ff
JB		 2120
2121 is_vf = (vsi->type == I40E_VSI_SRIOV);
2122 is_netdev = !!(netdev);
2123
2124 if (is_netdev)
2125 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2126
2127 list_for_each_entry(f, &vsi->mac_filter_list, list)
2128 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2129
41c445ff
JB		 2130 /* go through all the filters for this VSI and if there is only
2131 * vid == 0 it means there are no other filters, so vid 0 must
2132 * be replaced with -1. This signifies that we should from now
2133 * on accept any traffic (with any tag present, or untagged)
2134 */
2135 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2136 if (is_netdev) {
2137 if (f->vlan &&
2138 ether_addr_equal(netdev->dev_addr, f->macaddr))
2139 filter_count++;
2140 }
2141
2142 if (f->vlan)
2143 filter_count++;
2144 }
2145
2146 if (!filter_count && is_netdev) {
2147 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2148 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2149 is_vf, is_netdev);
2150 if (!f) {
2151 dev_info(&vsi->back->pdev->dev,
2152 "Could not add filter %d for %pM\n",
2153 I40E_VLAN_ANY, netdev->dev_addr);
2154 return -ENOMEM;
2155 }
2156 }
2157
2158 if (!filter_count) {
2159 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2160 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2161 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2162 is_vf, is_netdev);
2163 if (!add_f) {
2164 dev_info(&vsi->back->pdev->dev,
2165 "Could not add filter %d for %pM\n",
2166 I40E_VLAN_ANY, f->macaddr);
2167 return -ENOMEM;
2168 }
2169 }
2170 }
2171
80f6428f
ASJ		 2172 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2173 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2174 return 0;
2175
41c445ff
JB		 2176 return i40e_sync_vsi_filters(vsi);
2177}
2178
2179/**
2180 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2181 * @netdev: network interface to be adjusted
2182 * @vid: vlan id to be added
078b5876
JB		 2183 *
2184 * net_device_ops implementation for adding vlan ids
41c445ff 2185 **/
38e00438
VD		 2186#ifdef I40E_FCOE
2187int i40e_vlan_rx_add_vid(struct net_device *netdev,
2188 __always_unused __be16 proto, u16 vid)
2189#else
41c445ff
JB		 2190static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2191 __always_unused __be16 proto, u16 vid)
38e00438 2192#endif
41c445ff
JB		 2193{
2194 struct i40e_netdev_priv *np = netdev_priv(netdev);
2195 struct i40e_vsi *vsi = np->vsi;
078b5876 2196 int ret = 0;
41c445ff
JB		 2197
2198 if (vid > 4095)
078b5876
JB		 2199 return -EINVAL;
2200
2201 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2202
6982d429
ASJ		 2203 /* If the network stack called us with vid = 0 then
2204 * it is asking to receive priority tagged packets with
2205 * vlan id 0. Our HW receives them by default when configured
2206 * to receive untagged packets so there is no need to add an
2207 * extra filter for vlan 0 tagged packets.
41c445ff 2208 */
6982d429
ASJ		 2209 if (vid)
2210 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2211
078b5876
JB		 2212 if (!ret && (vid < VLAN_N_VID))
2213 set_bit(vid, vsi->active_vlans);
41c445ff 2214
078b5876 2215 return ret;
41c445ff
JB		 2216}
2217
2218/**
2219 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2220 * @netdev: network interface to be adjusted
2221 * @vid: vlan id to be removed
078b5876 2222 *
fdfd943e 2223 * net_device_ops implementation for removing vlan ids
41c445ff 2224 **/
38e00438
VD		 2225#ifdef I40E_FCOE
2226int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2227 __always_unused __be16 proto, u16 vid)
2228#else
41c445ff
JB		 2229static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2230 __always_unused __be16 proto, u16 vid)
38e00438 2231#endif
41c445ff
JB		 2232{
2233 struct i40e_netdev_priv *np = netdev_priv(netdev);
2234 struct i40e_vsi *vsi = np->vsi;
2235
078b5876
JB		 2236 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2237
41c445ff
JB		 2238 /* return code is ignored as there is nothing a user
2239 * can do about failure to remove and a log message was
078b5876 2240 * already printed from the other function
41c445ff
JB		 2241 */
2242 i40e_vsi_kill_vlan(vsi, vid);
2243
2244 clear_bit(vid, vsi->active_vlans);
078b5876 2245
41c445ff
JB		 2246 return 0;
2247}
2248
2249/**
2250 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2251 * @vsi: the vsi being brought back up
2252 **/
2253static void i40e_restore_vlan(struct i40e_vsi *vsi)
2254{
2255 u16 vid;
2256
2257 if (!vsi->netdev)
2258 return;
2259
2260 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2261
2262 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2263 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2264 vid);
2265}
2266
2267/**
2268 * i40e_vsi_add_pvid - Add pvid for the VSI
2269 * @vsi: the vsi being adjusted
2270 * @vid: the vlan id to set as a PVID
2271 **/
dcae29be 2272int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2273{
2274 struct i40e_vsi_context ctxt;
dcae29be 2275 i40e_status aq_ret;
41c445ff
JB		 2276
2277 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2278 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2279 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2280 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2281 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2282
2283 ctxt.seid = vsi->seid;
2284 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2285 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2286 if (aq_ret) {
41c445ff
JB		 2287 dev_info(&vsi->back->pdev->dev,
2288 "%s: update vsi failed, aq_err=%d\n",
2289 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2290 return -ENOENT;
41c445ff
JB		 2291 }
2292
dcae29be 2293 return 0;
41c445ff
JB		 2294}
2295
2296/**
2297 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2298 * @vsi: the vsi being adjusted
2299 *
2300 * Just use the vlan_rx_register() service to put it back to normal
2301 **/
2302void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2303{
6c12fcbf
GR		 2304 i40e_vlan_stripping_disable(vsi);
2305
41c445ff 2306 vsi->info.pvid = 0;
41c445ff
JB		 2307}
2308
2309/**
2310 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2311 * @vsi: ptr to the VSI
2312 *
2313 * If this function returns with an error, then it's possible one or
2314 * more of the rings is populated (while the rest are not). It is the
2315 * callers duty to clean those orphaned rings.
2316 *
2317 * Return 0 on success, negative on failure
2318 **/
2319static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2320{
2321 int i, err = 0;
2322
2323 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2324 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2325
2326 return err;
2327}
2328
2329/**
2330 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2331 * @vsi: ptr to the VSI
2332 *
2333 * Free VSI's transmit software resources
2334 **/
2335static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2336{
2337 int i;
2338
8e9dca53
GR		 2339 if (!vsi->tx_rings)
2340 return;
2341
41c445ff 2342 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2343 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2344 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2345}
2346
2347/**
2348 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2349 * @vsi: ptr to the VSI
2350 *
2351 * If this function returns with an error, then it's possible one or
2352 * more of the rings is populated (while the rest are not). It is the
2353 * callers duty to clean those orphaned rings.
2354 *
2355 * Return 0 on success, negative on failure
2356 **/
2357static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2358{
2359 int i, err = 0;
2360
2361 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2362 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2363#ifdef I40E_FCOE
2364 i40e_fcoe_setup_ddp_resources(vsi);
2365#endif
41c445ff
JB		 2366 return err;
2367}
2368
2369/**
2370 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2371 * @vsi: ptr to the VSI
2372 *
2373 * Free all receive software resources
2374 **/
2375static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2376{
2377 int i;
2378
8e9dca53
GR		 2379 if (!vsi->rx_rings)
2380 return;
2381
41c445ff 2382 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2383 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2384 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2385#ifdef I40E_FCOE
2386 i40e_fcoe_free_ddp_resources(vsi);
2387#endif
41c445ff
JB		 2388}
2389
3ffa037d
NP		 2390/**
2391 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2392 * @ring: The Tx ring to configure
2393 *
2394 * This enables/disables XPS for a given Tx descriptor ring
2395 * based on the TCs enabled for the VSI that ring belongs to.
2396 **/
2397static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2398{
2399 struct i40e_vsi *vsi = ring->vsi;
2400 cpumask_var_t mask;
2401
9a660eea
JB		 2402 if (!ring->q_vector || !ring->netdev)
2403 return;
2404
2405 /* Single TC mode enable XPS */
2406 if (vsi->tc_config.numtc <= 1) {
2407 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2408 netif_set_xps_queue(ring->netdev,
2409 &ring->q_vector->affinity_mask,
2410 ring->queue_index);
9a660eea
JB		 2411 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2412 /* Disable XPS to allow selection based on TC */
2413 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2414 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2415 free_cpumask_var(mask);
3ffa037d
NP		 2416 }
2417}
2418
41c445ff
JB		 2419/**
2420 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2421 * @ring: The Tx ring to configure
2422 *
2423 * Configure the Tx descriptor ring in the HMC context.
2424 **/
2425static int i40e_configure_tx_ring(struct i40e_ring *ring)
2426{
2427 struct i40e_vsi *vsi = ring->vsi;
2428 u16 pf_q = vsi->base_queue + ring->queue_index;
2429 struct i40e_hw *hw = &vsi->back->hw;
2430 struct i40e_hmc_obj_txq tx_ctx;
2431 i40e_status err = 0;
2432 u32 qtx_ctl = 0;
2433
2434 /* some ATR related tx ring init */
60ea5f83 2435 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2436 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2437 ring->atr_count = 0;
2438 } else {
2439 ring->atr_sample_rate = 0;
2440 }
2441
3ffa037d
NP		 2442 /* configure XPS */
2443 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2444
2445 /* clear the context structure first */
2446 memset(&tx_ctx, 0, sizeof(tx_ctx));
2447
2448 tx_ctx.new_context = 1;
2449 tx_ctx.base = (ring->dma / 128);
2450 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2451 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2452 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2453#ifdef I40E_FCOE
2454 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2455#endif
beb0dff1 2456 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2457 /* FDIR VSI tx ring can still use RS bit and writebacks */
2458 if (vsi->type != I40E_VSI_FDIR)
2459 tx_ctx.head_wb_ena = 1;
2460 tx_ctx.head_wb_addr = ring->dma +
2461 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2462
2463 /* As part of VSI creation/update, FW allocates certain
2464 * Tx arbitration queue sets for each TC enabled for
2465 * the VSI. The FW returns the handles to these queue
2466 * sets as part of the response buffer to Add VSI,
2467 * Update VSI, etc. AQ commands. It is expected that
2468 * these queue set handles be associated with the Tx
2469 * queues by the driver as part of the TX queue context
2470 * initialization. This has to be done regardless of
2471 * DCB as by default everything is mapped to TC0.
2472 */
2473 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2474 tx_ctx.rdylist_act = 0;
2475
2476 /* clear the context in the HMC */
2477 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2478 if (err) {
2479 dev_info(&vsi->back->pdev->dev,
2480 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2481 ring->queue_index, pf_q, err);
2482 return -ENOMEM;
2483 }
2484
2485 /* set the context in the HMC */
2486 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2487 if (err) {
2488 dev_info(&vsi->back->pdev->dev,
2489 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2490 ring->queue_index, pf_q, err);
2491 return -ENOMEM;
2492 }
2493
2494 /* Now associate this queue with this PCI function */
7a28d885 2495 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2496 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2497 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2498 I40E_QTX_CTL_VFVM_INDX_MASK;
2499 } else {
9d8bf547 2500 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2501 }
2502
13fd9774
SN		 2503 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2504 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2505 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2506 i40e_flush(hw);
2507
2508 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2509
2510 /* cache tail off for easier writes later */
2511 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2512
2513 return 0;
2514}
2515
2516/**
2517 * i40e_configure_rx_ring - Configure a receive ring context
2518 * @ring: The Rx ring to configure
2519 *
2520 * Configure the Rx descriptor ring in the HMC context.
2521 **/
2522static int i40e_configure_rx_ring(struct i40e_ring *ring)
2523{
2524 struct i40e_vsi *vsi = ring->vsi;
2525 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2526 u16 pf_q = vsi->base_queue + ring->queue_index;
2527 struct i40e_hw *hw = &vsi->back->hw;
2528 struct i40e_hmc_obj_rxq rx_ctx;
2529 i40e_status err = 0;
2530
2531 ring->state = 0;
2532
2533 /* clear the context structure first */
2534 memset(&rx_ctx, 0, sizeof(rx_ctx));
2535
2536 ring->rx_buf_len = vsi->rx_buf_len;
2537 ring->rx_hdr_len = vsi->rx_hdr_len;
2538
2539 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2540 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2541
2542 rx_ctx.base = (ring->dma / 128);
2543 rx_ctx.qlen = ring->count;
2544
2545 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2546 set_ring_16byte_desc_enabled(ring);
2547 rx_ctx.dsize = 0;
2548 } else {
2549 rx_ctx.dsize = 1;
2550 }
2551
2552 rx_ctx.dtype = vsi->dtype;
2553 if (vsi->dtype) {
2554 set_ring_ps_enabled(ring);
2555 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2556 I40E_RX_SPLIT_IP |
2557 I40E_RX_SPLIT_TCP_UDP |
2558 I40E_RX_SPLIT_SCTP;
2559 } else {
2560 rx_ctx.hsplit_0 = 0;
2561 }
2562
2563 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2564 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2565 if (hw->revision_id == 0)
2566 rx_ctx.lrxqthresh = 0;
2567 else
2568 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2569 rx_ctx.crcstrip = 1;
2570 rx_ctx.l2tsel = 1;
2571 rx_ctx.showiv = 1;
38e00438
VD		 2572#ifdef I40E_FCOE
2573 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2574#endif
acb3676b
CS		 2575 /* set the prefena field to 1 because the manual says to */
2576 rx_ctx.prefena = 1;
41c445ff
JB		 2577
2578 /* clear the context in the HMC */
2579 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2580 if (err) {
2581 dev_info(&vsi->back->pdev->dev,
2582 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2583 ring->queue_index, pf_q, err);
2584 return -ENOMEM;
2585 }
2586
2587 /* set the context in the HMC */
2588 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2589 if (err) {
2590 dev_info(&vsi->back->pdev->dev,
2591 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2592 ring->queue_index, pf_q, err);
2593 return -ENOMEM;
2594 }
2595
2596 /* cache tail for quicker writes, and clear the reg before use */
2597 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2598 writel(0, ring->tail);
2599
a132af24
MW		 2600 if (ring_is_ps_enabled(ring)) {
2601 i40e_alloc_rx_headers(ring);
2602 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2603 } else {
2604 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2605 }
41c445ff
JB		 2606
2607 return 0;
2608}
2609
2610/**
2611 * i40e_vsi_configure_tx - Configure the VSI for Tx
2612 * @vsi: VSI structure describing this set of rings and resources
2613 *
2614 * Configure the Tx VSI for operation.
2615 **/
2616static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2617{
2618 int err = 0;
2619 u16 i;
2620
9f65e15b
AD		 2621 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2622 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2623
2624 return err;
2625}
2626
2627/**
2628 * i40e_vsi_configure_rx - Configure the VSI for Rx
2629 * @vsi: the VSI being configured
2630 *
2631 * Configure the Rx VSI for operation.
2632 **/
2633static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2634{
2635 int err = 0;
2636 u16 i;
2637
2638 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2639 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2640 + ETH_FCS_LEN + VLAN_HLEN;
2641 else
2642 vsi->max_frame = I40E_RXBUFFER_2048;
2643
2644 /* figure out correct receive buffer length */
2645 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2646 I40E_FLAG_RX_PS_ENABLED)) {
2647 case I40E_FLAG_RX_1BUF_ENABLED:
2648 vsi->rx_hdr_len = 0;
2649 vsi->rx_buf_len = vsi->max_frame;
2650 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2651 break;
2652 case I40E_FLAG_RX_PS_ENABLED:
2653 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2654 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2655 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2656 break;
2657 default:
2658 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2659 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2660 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2661 break;
2662 }
2663
38e00438
VD		 2664#ifdef I40E_FCOE
2665 /* setup rx buffer for FCoE */
2666 if ((vsi->type == I40E_VSI_FCOE) &&
2667 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2668 vsi->rx_hdr_len = 0;
2669 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2670 vsi->max_frame = I40E_RXBUFFER_3072;
2671 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2672 }
2673
2674#endif /* I40E_FCOE */
41c445ff
JB		 2675 /* round up for the chip's needs */
2676 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2677 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2678 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2679 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2680
2681 /* set up individual rings */
2682 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2683 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2684
2685 return err;
2686}
2687
2688/**
2689 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2690 * @vsi: ptr to the VSI
2691 **/
2692static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2693{
e7046ee1 2694 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2695 u16 qoffset, qcount;
2696 int i, n;
2697
cd238a3e
PN		 2698 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2699 /* Reset the TC information */
2700 for (i = 0; i < vsi->num_queue_pairs; i++) {
2701 rx_ring = vsi->rx_rings[i];
2702 tx_ring = vsi->tx_rings[i];
2703 rx_ring->dcb_tc = 0;
2704 tx_ring->dcb_tc = 0;
2705 }
2706 }
41c445ff
JB		 2707
2708 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2709 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2710 continue;
2711
2712 qoffset = vsi->tc_config.tc_info[n].qoffset;
2713 qcount = vsi->tc_config.tc_info[n].qcount;
2714 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2715 rx_ring = vsi->rx_rings[i];
2716 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2717 rx_ring->dcb_tc = n;
2718 tx_ring->dcb_tc = n;
2719 }
2720 }
2721}
2722
2723/**
2724 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2725 * @vsi: ptr to the VSI
2726 **/
2727static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2728{
2729 if (vsi->netdev)
2730 i40e_set_rx_mode(vsi->netdev);
2731}
2732
17a73f6b
JG		 2733/**
2734 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2735 * @vsi: Pointer to the targeted VSI
2736 *
2737 * This function replays the hlist on the hw where all the SB Flow Director
2738 * filters were saved.
2739 **/
2740static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2741{
2742 struct i40e_fdir_filter *filter;
2743 struct i40e_pf *pf = vsi->back;
2744 struct hlist_node *node;
2745
55a5e60b
ASJ		 2746 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2747 return;
2748
17a73f6b
JG		 2749 hlist_for_each_entry_safe(filter, node,
2750 &pf->fdir_filter_list, fdir_node) {
2751 i40e_add_del_fdir(vsi, filter, true);
2752 }
2753}
2754
41c445ff
JB		 2755/**
2756 * i40e_vsi_configure - Set up the VSI for action
2757 * @vsi: the VSI being configured
2758 **/
2759static int i40e_vsi_configure(struct i40e_vsi *vsi)
2760{
2761 int err;
2762
2763 i40e_set_vsi_rx_mode(vsi);
2764 i40e_restore_vlan(vsi);
2765 i40e_vsi_config_dcb_rings(vsi);
2766 err = i40e_vsi_configure_tx(vsi);
2767 if (!err)
2768 err = i40e_vsi_configure_rx(vsi);
2769
2770 return err;
2771}
2772
2773/**
2774 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2775 * @vsi: the VSI being configured
2776 **/
2777static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2778{
2779 struct i40e_pf *pf = vsi->back;
2780 struct i40e_q_vector *q_vector;
2781 struct i40e_hw *hw = &pf->hw;
2782 u16 vector;
2783 int i, q;
2784 u32 val;
2785 u32 qp;
2786
2787 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2788 * and PFINT_LNKLSTn registers, e.g.:
2789 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2790 */
2791 qp = vsi->base_queue;
2792 vector = vsi->base_vector;
493fb300
AD		 2793 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2794 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2795 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2796 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2797 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2798 q_vector->rx.itr);
2799 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2800 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2801 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2802 q_vector->tx.itr);
2803
2804 /* Linked list for the queuepairs assigned to this vector */
2805 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2806 for (q = 0; q < q_vector->num_ringpairs; q++) {
2807 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2808 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2809 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2810 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2811 (I40E_QUEUE_TYPE_TX
2812 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2813
2814 wr32(hw, I40E_QINT_RQCTL(qp), val);
2815
2816 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2817 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2818 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2819 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2820 (I40E_QUEUE_TYPE_RX
2821 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2822
2823 /* Terminate the linked list */
2824 if (q == (q_vector->num_ringpairs - 1))
2825 val |= (I40E_QUEUE_END_OF_LIST
2826 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2827
2828 wr32(hw, I40E_QINT_TQCTL(qp), val);
2829 qp++;
2830 }
2831 }
2832
2833 i40e_flush(hw);
2834}
2835
2836/**
2837 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2838 * @hw: ptr to the hardware info
2839 **/
ab437b5a 2840static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 2841{
ab437b5a 2842 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 2843 u32 val;
2844
2845 /* clear things first */
2846 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2847 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2848
2849 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2850 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2851 I40E_PFINT_ICR0_ENA_GRST_MASK |
2852 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2853 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 2854 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2855 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2856 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2857
ab437b5a
JK		 2858 if (pf->flags & I40E_FLAG_PTP)
2859 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2860
41c445ff
JB		 2861 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2862
2863 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2864 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2865 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2866
2867 /* OTHER_ITR_IDX = 0 */
2868 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2869}
2870
2871/**
2872 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2873 * @vsi: the VSI being configured
2874 **/
2875static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2876{
493fb300 2877 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2878 struct i40e_pf *pf = vsi->back;
2879 struct i40e_hw *hw = &pf->hw;
2880 u32 val;
2881
2882 /* set the ITR configuration */
2883 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2884 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2885 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2886 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2887 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2888 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2889
ab437b5a 2890 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 2891
2892 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2893 wr32(hw, I40E_PFINT_LNKLST0, 0);
2894
f29eaa3d 2895 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2896 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2897 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2898 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2899
2900 wr32(hw, I40E_QINT_RQCTL(0), val);
2901
2902 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2903 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2904 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2905
2906 wr32(hw, I40E_QINT_TQCTL(0), val);
2907 i40e_flush(hw);
2908}
2909
2ef28cfb
MW		 2910/**
2911 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2912 * @pf: board private structure
2913 **/
2914void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2915{
2916 struct i40e_hw *hw = &pf->hw;
2917
2918 wr32(hw, I40E_PFINT_DYN_CTL0,
2919 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2920 i40e_flush(hw);
2921}
2922
41c445ff
JB		 2923/**
2924 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2925 * @pf: board private structure
2926 **/
116a57d4 2927void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2928{
2929 struct i40e_hw *hw = &pf->hw;
2930 u32 val;
2931
2932 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2933 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2934 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2935
2936 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2937 i40e_flush(hw);
2938}
2939
2940/**
2941 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2942 * @vsi: pointer to a vsi
2943 * @vector: enable a particular Hw Interrupt vector
2944 **/
2945void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2946{
2947 struct i40e_pf *pf = vsi->back;
2948 struct i40e_hw *hw = &pf->hw;
2949 u32 val;
2950
2951 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2952 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2953 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2954 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2955 /* skip the flush */
41c445ff
JB		 2956}
2957
5c2cebda
CW		 2958/**
2959 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2960 * @vsi: pointer to a vsi
03147773 2961 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 2962 **/
2963void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2964{
2965 struct i40e_pf *pf = vsi->back;
2966 struct i40e_hw *hw = &pf->hw;
2967 u32 val;
2968
2969 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2970 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2971 i40e_flush(hw);
2972}
2973
41c445ff
JB		 2974/**
2975 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2976 * @irq: interrupt number
2977 * @data: pointer to a q_vector
2978 **/
2979static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2980{
2981 struct i40e_q_vector *q_vector = data;
2982
cd0b6fa6 2983 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2984 return IRQ_HANDLED;
2985
2986 napi_schedule(&q_vector->napi);
2987
2988 return IRQ_HANDLED;
2989}
2990
41c445ff
JB		 2991/**
2992 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2993 * @vsi: the VSI being configured
2994 * @basename: name for the vector
2995 *
2996 * Allocates MSI-X vectors and requests interrupts from the kernel.
2997 **/
2998static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2999{
3000 int q_vectors = vsi->num_q_vectors;
3001 struct i40e_pf *pf = vsi->back;
3002 int base = vsi->base_vector;
3003 int rx_int_idx = 0;
3004 int tx_int_idx = 0;
3005 int vector, err;
3006
3007 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3008 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3009
cd0b6fa6 3010 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3011 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3012 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3013 tx_int_idx++;
cd0b6fa6 3014 } else if (q_vector->rx.ring) {
41c445ff
JB		 3015 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3016 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3017 } else if (q_vector->tx.ring) {
41c445ff
JB		 3018 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3019 "%s-%s-%d", basename, "tx", tx_int_idx++);
3020 } else {
3021 /* skip this unused q_vector */
3022 continue;
3023 }
3024 err = request_irq(pf->msix_entries[base + vector].vector,
3025 vsi->irq_handler,
3026 0,
3027 q_vector->name,
3028 q_vector);
3029 if (err) {
3030 dev_info(&pf->pdev->dev,
3031 "%s: request_irq failed, error: %d\n",
3032 __func__, err);
3033 goto free_queue_irqs;
3034 }
3035 /* assign the mask for this irq */
3036 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3037 &q_vector->affinity_mask);
3038 }
3039
63741846 3040 vsi->irqs_ready = true;
41c445ff
JB		 3041 return 0;
3042
3043free_queue_irqs:
3044 while (vector) {
3045 vector--;
3046 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3047 NULL);
3048 free_irq(pf->msix_entries[base + vector].vector,
3049 &(vsi->q_vectors[vector]));
3050 }
3051 return err;
3052}
3053
3054/**
3055 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3056 * @vsi: the VSI being un-configured
3057 **/
3058static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3059{
3060 struct i40e_pf *pf = vsi->back;
3061 struct i40e_hw *hw = &pf->hw;
3062 int base = vsi->base_vector;
3063 int i;
3064
3065 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3066 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3067 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3068 }
3069
3070 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3071 for (i = vsi->base_vector;
3072 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3073 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3074
3075 i40e_flush(hw);
3076 for (i = 0; i < vsi->num_q_vectors; i++)
3077 synchronize_irq(pf->msix_entries[i + base].vector);
3078 } else {
3079 /* Legacy and MSI mode - this stops all interrupt handling */
3080 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3081 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3082 i40e_flush(hw);
3083 synchronize_irq(pf->pdev->irq);
3084 }
3085}
3086
3087/**
3088 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3089 * @vsi: the VSI being configured
3090 **/
3091static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3092{
3093 struct i40e_pf *pf = vsi->back;
3094 int i;
3095
3096 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3097 for (i = vsi->base_vector;
3098 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3099 i40e_irq_dynamic_enable(vsi, i);
3100 } else {
3101 i40e_irq_dynamic_enable_icr0(pf);
3102 }
3103
1022cb6c 3104 i40e_flush(&pf->hw);
41c445ff
JB		 3105 return 0;
3106}
3107
3108/**
3109 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3110 * @pf: board private structure
3111 **/
3112static void i40e_stop_misc_vector(struct i40e_pf *pf)
3113{
3114 /* Disable ICR 0 */
3115 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3116 i40e_flush(&pf->hw);
3117}
3118
3119/**
3120 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3121 * @irq: interrupt number
3122 * @data: pointer to a q_vector
3123 *
3124 * This is the handler used for all MSI/Legacy interrupts, and deals
3125 * with both queue and non-queue interrupts. This is also used in
3126 * MSIX mode to handle the non-queue interrupts.
3127 **/
3128static irqreturn_t i40e_intr(int irq, void *data)
3129{
3130 struct i40e_pf *pf = (struct i40e_pf *)data;
3131 struct i40e_hw *hw = &pf->hw;
5e823066 3132 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3133 u32 icr0, icr0_remaining;
3134 u32 val, ena_mask;
3135
3136 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3137 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3138
116a57d4
SN		 3139 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3140 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3141 goto enable_intr;
41c445ff 3142
cd92e72f
SN		 3143 /* if interrupt but no bits showing, must be SWINT */
3144 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3145 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3146 pf->sw_int_count++;
3147
41c445ff
JB		 3148 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3149 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3150
3151 /* temporarily disable queue cause for NAPI processing */
3152 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3153 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3154 wr32(hw, I40E_QINT_RQCTL(0), qval);
3155
3156 qval = rd32(hw, I40E_QINT_TQCTL(0));
3157 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3158 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3159
3160 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3161 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3162 }
3163
3164 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3165 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3166 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3167 }
3168
3169 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3170 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3171 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3172 }
3173
3174 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3175 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3176 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3177 }
3178
3179 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3180 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3181 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3182 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3183 val = rd32(hw, I40E_GLGEN_RSTAT);
3184 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3185 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3186 if (val == I40E_RESET_CORER) {
41c445ff 3187 pf->corer_count++;
4eb3f768 3188 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3189 pf->globr_count++;
4eb3f768 3190 } else if (val == I40E_RESET_EMPR) {
41c445ff 3191 pf->empr_count++;
9df42d1a 3192 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3193 }
41c445ff
JB		 3194 }
3195
9c010ee0
ASJ		 3196 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3197 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3198 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3199 }
3200
beb0dff1
JK		 3201 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3202 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3203
3204 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3205 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3206 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3207 }
beb0dff1
JK		 3208 }
3209
41c445ff
JB		 3210 /* If a critical error is pending we have no choice but to reset the
3211 * device.
3212 * Report and mask out any remaining unexpected interrupts.
3213 */
3214 icr0_remaining = icr0 & ena_mask;
3215 if (icr0_remaining) {
3216 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3217 icr0_remaining);
9c010ee0 3218 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3219 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3220 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3221 dev_info(&pf->pdev->dev, "device will be reset\n");
3222 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3223 i40e_service_event_schedule(pf);
41c445ff
JB		 3224 }
3225 ena_mask &= ~icr0_remaining;
3226 }
5e823066 3227 ret = IRQ_HANDLED;
41c445ff 3228
5e823066 3229enable_intr:
41c445ff
JB		 3230 /* re-enable interrupt causes */
3231 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3232 if (!test_bit(__I40E_DOWN, &pf->state)) {
3233 i40e_service_event_schedule(pf);
3234 i40e_irq_dynamic_enable_icr0(pf);
3235 }
3236
5e823066 3237 return ret;
41c445ff
JB		 3238}
3239
cbf61325
ASJ		 3240/**
3241 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3242 * @tx_ring: tx ring to clean
3243 * @budget: how many cleans we're allowed
3244 *
3245 * Returns true if there's any budget left (e.g. the clean is finished)
3246 **/
3247static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3248{
3249 struct i40e_vsi *vsi = tx_ring->vsi;
3250 u16 i = tx_ring->next_to_clean;
3251 struct i40e_tx_buffer *tx_buf;
3252 struct i40e_tx_desc *tx_desc;
3253
3254 tx_buf = &tx_ring->tx_bi[i];
3255 tx_desc = I40E_TX_DESC(tx_ring, i);
3256 i -= tx_ring->count;
3257
3258 do {
3259 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3260
3261 /* if next_to_watch is not set then there is no work pending */
3262 if (!eop_desc)
3263 break;
3264
3265 /* prevent any other reads prior to eop_desc */
3266 read_barrier_depends();
3267
3268 /* if the descriptor isn't done, no work yet to do */
3269 if (!(eop_desc->cmd_type_offset_bsz &
3270 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3271 break;
3272
3273 /* clear next_to_watch to prevent false hangs */
3274 tx_buf->next_to_watch = NULL;
3275
49d7d933
ASJ		 3276 tx_desc->buffer_addr = 0;
3277 tx_desc->cmd_type_offset_bsz = 0;
3278 /* move past filter desc */
3279 tx_buf++;
3280 tx_desc++;
3281 i++;
3282 if (unlikely(!i)) {
3283 i -= tx_ring->count;
3284 tx_buf = tx_ring->tx_bi;
3285 tx_desc = I40E_TX_DESC(tx_ring, 0);
3286 }
cbf61325
ASJ		 3287 /* unmap skb header data */
3288 dma_unmap_single(tx_ring->dev,
3289 dma_unmap_addr(tx_buf, dma),
3290 dma_unmap_len(tx_buf, len),
3291 DMA_TO_DEVICE);
49d7d933
ASJ		 3292 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3293 kfree(tx_buf->raw_buf);
cbf61325 3294
49d7d933
ASJ		 3295 tx_buf->raw_buf = NULL;
3296 tx_buf->tx_flags = 0;
3297 tx_buf->next_to_watch = NULL;
cbf61325 3298 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3299 tx_desc->buffer_addr = 0;
3300 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3301
49d7d933 3302 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3303 tx_buf++;
3304 tx_desc++;
3305 i++;
3306 if (unlikely(!i)) {
3307 i -= tx_ring->count;
3308 tx_buf = tx_ring->tx_bi;
3309 tx_desc = I40E_TX_DESC(tx_ring, 0);
3310 }
3311
3312 /* update budget accounting */
3313 budget--;
3314 } while (likely(budget));
3315
3316 i += tx_ring->count;
3317 tx_ring->next_to_clean = i;
3318
3319 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3320 i40e_irq_dynamic_enable(vsi,
3321 tx_ring->q_vector->v_idx + vsi->base_vector);
3322 }
3323 return budget > 0;
3324}
3325
3326/**
3327 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3328 * @irq: interrupt number
3329 * @data: pointer to a q_vector
3330 **/
3331static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3332{
3333 struct i40e_q_vector *q_vector = data;
3334 struct i40e_vsi *vsi;
3335
3336 if (!q_vector->tx.ring)
3337 return IRQ_HANDLED;
3338
3339 vsi = q_vector->tx.ring->vsi;
3340 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3341
3342 return IRQ_HANDLED;
3343}
3344
41c445ff 3345/**
cd0b6fa6 3346 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3347 * @vsi: the VSI being configured
3348 * @v_idx: vector index
cd0b6fa6 3349 * @qp_idx: queue pair index
41c445ff 3350 **/
cd0b6fa6 3351static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3352{
493fb300 3353 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3354 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3355 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3356
3357 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3358 tx_ring->next = q_vector->tx.ring;
3359 q_vector->tx.ring = tx_ring;
41c445ff 3360 q_vector->tx.count++;
cd0b6fa6
AD		 3361
3362 rx_ring->q_vector = q_vector;
3363 rx_ring->next = q_vector->rx.ring;
3364 q_vector->rx.ring = rx_ring;
3365 q_vector->rx.count++;
41c445ff
JB		 3366}
3367
3368/**
3369 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3370 * @vsi: the VSI being configured
3371 *
3372 * This function maps descriptor rings to the queue-specific vectors
3373 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3374 * one vector per queue pair, but on a constrained vector budget, we
3375 * group the queue pairs as "efficiently" as possible.
3376 **/
3377static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3378{
3379 int qp_remaining = vsi->num_queue_pairs;
3380 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3381 int num_ringpairs;
41c445ff
JB		 3382 int v_start = 0;
3383 int qp_idx = 0;
3384
3385 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3386 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3387 * It is also important to go through all the vectors available to be
3388 * sure that if we don't use all the vectors, that the remaining vectors
3389 * are cleared. This is especially important when decreasing the
3390 * number of queues in use.
41c445ff 3391 */
70114ec4 3392 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3393 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3394
3395 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3396
3397 q_vector->num_ringpairs = num_ringpairs;
3398
3399 q_vector->rx.count = 0;
3400 q_vector->tx.count = 0;
3401 q_vector->rx.ring = NULL;
3402 q_vector->tx.ring = NULL;
3403
3404 while (num_ringpairs--) {
3405 map_vector_to_qp(vsi, v_start, qp_idx);
3406 qp_idx++;
3407 qp_remaining--;
41c445ff
JB		 3408 }
3409 }
3410}
3411
3412/**
3413 * i40e_vsi_request_irq - Request IRQ from the OS
3414 * @vsi: the VSI being configured
3415 * @basename: name for the vector
3416 **/
3417static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3418{
3419 struct i40e_pf *pf = vsi->back;
3420 int err;
3421
3422 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3423 err = i40e_vsi_request_irq_msix(vsi, basename);
3424 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3425 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3426 pf->int_name, pf);
41c445ff
JB		 3427 else
3428 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3429 pf->int_name, pf);
41c445ff
JB		 3430
3431 if (err)
3432 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3433
3434 return err;
3435}
3436
3437#ifdef CONFIG_NET_POLL_CONTROLLER
3438/**
3439 * i40e_netpoll - A Polling 'interrupt'handler
3440 * @netdev: network interface device structure
3441 *
3442 * This is used by netconsole to send skbs without having to re-enable
3443 * interrupts. It's not called while the normal interrupt routine is executing.
3444 **/
38e00438
VD		 3445#ifdef I40E_FCOE
3446void i40e_netpoll(struct net_device *netdev)
3447#else
41c445ff 3448static void i40e_netpoll(struct net_device *netdev)
38e00438 3449#endif
41c445ff
JB		 3450{
3451 struct i40e_netdev_priv *np = netdev_priv(netdev);
3452 struct i40e_vsi *vsi = np->vsi;
3453 struct i40e_pf *pf = vsi->back;
3454 int i;
3455
3456 /* if interface is down do nothing */
3457 if (test_bit(__I40E_DOWN, &vsi->state))
3458 return;
3459
3460 pf->flags |= I40E_FLAG_IN_NETPOLL;
3461 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3462 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3463 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3464 } else {
3465 i40e_intr(pf->pdev->irq, netdev);
3466 }
3467 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3468}
3469#endif
3470
23527308
NP		 3471/**
3472 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3473 * @pf: the PF being configured
3474 * @pf_q: the PF queue
3475 * @enable: enable or disable state of the queue
3476 *
3477 * This routine will wait for the given Tx queue of the PF to reach the
3478 * enabled or disabled state.
3479 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3480 * multiple retries; else will return 0 in case of success.
3481 **/
3482static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3483{
3484 int i;
3485 u32 tx_reg;
3486
3487 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3488 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3489 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3490 break;
3491
f98a2006 3492 usleep_range(10, 20);
23527308
NP		 3493 }
3494 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3495 return -ETIMEDOUT;
3496
3497 return 0;
3498}
3499
41c445ff
JB		 3500/**
3501 * i40e_vsi_control_tx - Start or stop a VSI's rings
3502 * @vsi: the VSI being configured
3503 * @enable: start or stop the rings
3504 **/
3505static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3506{
3507 struct i40e_pf *pf = vsi->back;
3508 struct i40e_hw *hw = &pf->hw;
23527308 3509 int i, j, pf_q, ret = 0;
41c445ff
JB		 3510 u32 tx_reg;
3511
3512 pf_q = vsi->base_queue;
3513 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3514
3515 /* warn the TX unit of coming changes */
3516 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3517 if (!enable)
f98a2006 3518 usleep_range(10, 20);
351499ab 3519
6c5ef620 3520 for (j = 0; j < 50; j++) {
41c445ff 3521 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3522 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3523 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3524 break;
3525 usleep_range(1000, 2000);
3526 }
fda972f6 3527 /* Skip if the queue is already in the requested state */
7c122007 3528 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3529 continue;
41c445ff
JB		 3530
3531 /* turn on/off the queue */
c5c9eb9e
SN		 3532 if (enable) {
3533 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3534 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3535 } else {
41c445ff 3536 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3537 }
41c445ff
JB		 3538
3539 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3540 /* No waiting for the Tx queue to disable */
3541 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3542 continue;
41c445ff
JB		 3543
3544 /* wait for the change to finish */
23527308
NP		 3545 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3546 if (ret) {
3547 dev_info(&pf->pdev->dev,
3548 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3549 __func__, vsi->seid, pf_q,
3550 (enable ? "en" : "dis"));
3551 break;
41c445ff
JB		 3552 }
3553 }
3554
7134f9ce
JB		 3555 if (hw->revision_id == 0)
3556 mdelay(50);
23527308
NP		 3557 return ret;
3558}
3559
3560/**
3561 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3562 * @pf: the PF being configured
3563 * @pf_q: the PF queue
3564 * @enable: enable or disable state of the queue
3565 *
3566 * This routine will wait for the given Rx queue of the PF to reach the
3567 * enabled or disabled state.
3568 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3569 * multiple retries; else will return 0 in case of success.
3570 **/
3571static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3572{
3573 int i;
3574 u32 rx_reg;
3575
3576 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3577 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3578 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3579 break;
3580
f98a2006 3581 usleep_range(10, 20);
23527308
NP		 3582 }
3583 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3584 return -ETIMEDOUT;
7134f9ce 3585
41c445ff
JB		 3586 return 0;
3587}
3588
3589/**
3590 * i40e_vsi_control_rx - Start or stop a VSI's rings
3591 * @vsi: the VSI being configured
3592 * @enable: start or stop the rings
3593 **/
3594static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3595{
3596 struct i40e_pf *pf = vsi->back;
3597 struct i40e_hw *hw = &pf->hw;
23527308 3598 int i, j, pf_q, ret = 0;
41c445ff
JB		 3599 u32 rx_reg;
3600
3601 pf_q = vsi->base_queue;
3602 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3603 for (j = 0; j < 50; j++) {
41c445ff 3604 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3605 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3606 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3607 break;
3608 usleep_range(1000, 2000);
3609 }
41c445ff 3610
7c122007
CS		 3611 /* Skip if the queue is already in the requested state */
3612 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3613 continue;
41c445ff
JB		 3614
3615 /* turn on/off the queue */
3616 if (enable)
6c5ef620 3617 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3618 else
6c5ef620 3619 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3620 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3621
3622 /* wait for the change to finish */
23527308
NP		 3623 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3624 if (ret) {
3625 dev_info(&pf->pdev->dev,
3626 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3627 __func__, vsi->seid, pf_q,
3628 (enable ? "en" : "dis"));
3629 break;
41c445ff
JB		 3630 }
3631 }
3632
23527308 3633 return ret;
41c445ff
JB		 3634}
3635
3636/**
3637 * i40e_vsi_control_rings - Start or stop a VSI's rings
3638 * @vsi: the VSI being configured
3639 * @enable: start or stop the rings
3640 **/
fc18eaa0 3641int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3642{
3b867b28 3643 int ret = 0;
41c445ff
JB		 3644
3645 /* do rx first for enable and last for disable */
3646 if (request) {
3647 ret = i40e_vsi_control_rx(vsi, request);
3648 if (ret)
3649 return ret;
3650 ret = i40e_vsi_control_tx(vsi, request);
3651 } else {
3b867b28
ASJ		 3652 /* Ignore return value, we need to shutdown whatever we can */
3653 i40e_vsi_control_tx(vsi, request);
3654 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3655 }
3656
3657 return ret;
3658}
3659
3660/**
3661 * i40e_vsi_free_irq - Free the irq association with the OS
3662 * @vsi: the VSI being configured
3663 **/
3664static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3665{
3666 struct i40e_pf *pf = vsi->back;
3667 struct i40e_hw *hw = &pf->hw;
3668 int base = vsi->base_vector;
3669 u32 val, qp;
3670 int i;
3671
3672 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3673 if (!vsi->q_vectors)
3674 return;
3675
63741846
SN		 3676 if (!vsi->irqs_ready)
3677 return;
3678
3679 vsi->irqs_ready = false;
41c445ff
JB		 3680 for (i = 0; i < vsi->num_q_vectors; i++) {
3681 u16 vector = i + base;
3682
3683 /* free only the irqs that were actually requested */
78681b1f
SN		 3684 if (!vsi->q_vectors[i] ||
3685 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3686 continue;
3687
3688 /* clear the affinity_mask in the IRQ descriptor */
3689 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3690 NULL);
3691 free_irq(pf->msix_entries[vector].vector,
493fb300 3692 vsi->q_vectors[i]);
41c445ff
JB		 3693
3694 /* Tear down the interrupt queue link list
3695 *
3696 * We know that they come in pairs and always
3697 * the Rx first, then the Tx. To clear the
3698 * link list, stick the EOL value into the
3699 * next_q field of the registers.
3700 */
3701 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3702 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3703 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3704 val |= I40E_QUEUE_END_OF_LIST
3705 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3706 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3707
3708 while (qp != I40E_QUEUE_END_OF_LIST) {
3709 u32 next;
3710
3711 val = rd32(hw, I40E_QINT_RQCTL(qp));
3712
3713 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3714 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3715 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3716 I40E_QINT_RQCTL_INTEVENT_MASK);
3717
3718 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3719 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3720
3721 wr32(hw, I40E_QINT_RQCTL(qp), val);
3722
3723 val = rd32(hw, I40E_QINT_TQCTL(qp));
3724
3725 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3726 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3727
3728 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3729 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3730 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3731 I40E_QINT_TQCTL_INTEVENT_MASK);
3732
3733 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3734 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3735
3736 wr32(hw, I40E_QINT_TQCTL(qp), val);
3737 qp = next;
3738 }
3739 }
3740 } else {
3741 free_irq(pf->pdev->irq, pf);
3742
3743 val = rd32(hw, I40E_PFINT_LNKLST0);
3744 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3745 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3746 val |= I40E_QUEUE_END_OF_LIST
3747 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3748 wr32(hw, I40E_PFINT_LNKLST0, val);
3749
3750 val = rd32(hw, I40E_QINT_RQCTL(qp));
3751 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3752 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3753 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3754 I40E_QINT_RQCTL_INTEVENT_MASK);
3755
3756 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3757 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3758
3759 wr32(hw, I40E_QINT_RQCTL(qp), val);
3760
3761 val = rd32(hw, I40E_QINT_TQCTL(qp));
3762
3763 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3764 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3765 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3766 I40E_QINT_TQCTL_INTEVENT_MASK);
3767
3768 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3769 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3770
3771 wr32(hw, I40E_QINT_TQCTL(qp), val);
3772 }
3773}
3774
493fb300
AD		 3775/**
3776 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3777 * @vsi: the VSI being configured
3778 * @v_idx: Index of vector to be freed
3779 *
3780 * This function frees the memory allocated to the q_vector. In addition if
3781 * NAPI is enabled it will delete any references to the NAPI struct prior
3782 * to freeing the q_vector.
3783 **/
3784static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3785{
3786 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3787 struct i40e_ring *ring;
493fb300
AD		 3788
3789 if (!q_vector)
3790 return;
3791
3792 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3793 i40e_for_each_ring(ring, q_vector->tx)
3794 ring->q_vector = NULL;
3795
3796 i40e_for_each_ring(ring, q_vector->rx)
3797 ring->q_vector = NULL;
493fb300
AD		 3798
3799 /* only VSI w/ an associated netdev is set up w/ NAPI */
3800 if (vsi->netdev)
3801 netif_napi_del(&q_vector->napi);
3802
3803 vsi->q_vectors[v_idx] = NULL;
3804
3805 kfree_rcu(q_vector, rcu);
3806}
3807
41c445ff
JB		 3808/**
3809 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3810 * @vsi: the VSI being un-configured
3811 *
3812 * This frees the memory allocated to the q_vectors and
3813 * deletes references to the NAPI struct.
3814 **/
3815static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3816{
3817 int v_idx;
3818
493fb300
AD		 3819 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3820 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3821}
3822
3823/**
3824 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3825 * @pf: board private structure
3826 **/
3827static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3828{
3829 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3830 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3831 pci_disable_msix(pf->pdev);
3832 kfree(pf->msix_entries);
3833 pf->msix_entries = NULL;
3b444399
SN		 3834 kfree(pf->irq_pile);
3835 pf->irq_pile = NULL;
41c445ff
JB		 3836 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3837 pci_disable_msi(pf->pdev);
3838 }
3839 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3840}
3841
3842/**
3843 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3844 * @pf: board private structure
3845 *
3846 * We go through and clear interrupt specific resources and reset the structure
3847 * to pre-load conditions
3848 **/
3849static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3850{
3851 int i;
3852
e147758d
SN		 3853 i40e_stop_misc_vector(pf);
3854 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3855 synchronize_irq(pf->msix_entries[0].vector);
3856 free_irq(pf->msix_entries[0].vector, pf);
3857 }
3858
41c445ff 3859 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3860 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3861 if (pf->vsi[i])
3862 i40e_vsi_free_q_vectors(pf->vsi[i]);
3863 i40e_reset_interrupt_capability(pf);
3864}
3865
3866/**
3867 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3868 * @vsi: the VSI being configured
3869 **/
3870static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3871{
3872 int q_idx;
3873
3874 if (!vsi->netdev)
3875 return;
3876
3877 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3878 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3879}
3880
3881/**
3882 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3883 * @vsi: the VSI being configured
3884 **/
3885static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3886{
3887 int q_idx;
3888
3889 if (!vsi->netdev)
3890 return;
3891
3892 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3893 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3894}
3895
90ef8d47
SN		 3896/**
3897 * i40e_vsi_close - Shut down a VSI
3898 * @vsi: the vsi to be quelled
3899 **/
3900static void i40e_vsi_close(struct i40e_vsi *vsi)
3901{
3902 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3903 i40e_down(vsi);
3904 i40e_vsi_free_irq(vsi);
3905 i40e_vsi_free_tx_resources(vsi);
3906 i40e_vsi_free_rx_resources(vsi);
3907}
3908
41c445ff
JB		 3909/**
3910 * i40e_quiesce_vsi - Pause a given VSI
3911 * @vsi: the VSI being paused
3912 **/
3913static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3914{
3915 if (test_bit(__I40E_DOWN, &vsi->state))
3916 return;
3917
d341b7a5
NP		 3918 /* No need to disable FCoE VSI when Tx suspended */
3919 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3920 vsi->type == I40E_VSI_FCOE) {
3921 dev_dbg(&vsi->back->pdev->dev,
3922 "%s: VSI seid %d skipping FCoE VSI disable\n",
3923 __func__, vsi->seid);
3924 return;
3925 }
3926
41c445ff
JB		 3927 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3928 if (vsi->netdev && netif_running(vsi->netdev)) {
3929 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3930 } else {
90ef8d47 3931 i40e_vsi_close(vsi);
41c445ff
JB		 3932 }
3933}
3934
3935/**
3936 * i40e_unquiesce_vsi - Resume a given VSI
3937 * @vsi: the VSI being resumed
3938 **/
3939static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3940{
3941 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3942 return;
3943
3944 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3945 if (vsi->netdev && netif_running(vsi->netdev))
3946 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3947 else
8276f757 3948 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3949}
3950
3951/**
3952 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3953 * @pf: the PF
3954 **/
3955static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3956{
3957 int v;
3958
505682cd 3959 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3960 if (pf->vsi[v])
3961 i40e_quiesce_vsi(pf->vsi[v]);
3962 }
3963}
3964
3965/**
3966 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3967 * @pf: the PF
3968 **/
3969static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3970{
3971 int v;
3972
505682cd 3973 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3974 if (pf->vsi[v])
3975 i40e_unquiesce_vsi(pf->vsi[v]);
3976 }
3977}
3978
69129dc3
NP		 3979#ifdef CONFIG_I40E_DCB
3980/**
3981 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
3982 * @vsi: the VSI being configured
3983 *
3984 * This function waits for the given VSI's Tx queues to be disabled.
3985 **/
3986static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
3987{
3988 struct i40e_pf *pf = vsi->back;
3989 int i, pf_q, ret;
3990
3991 pf_q = vsi->base_queue;
3992 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3993 /* Check and wait for the disable status of the queue */
3994 ret = i40e_pf_txq_wait(pf, pf_q, false);
3995 if (ret) {
3996 dev_info(&pf->pdev->dev,
3997 "%s: VSI seid %d Tx ring %d disable timeout\n",
3998 __func__, vsi->seid, pf_q);
3999 return ret;
4000 }
4001 }
4002
4003 return 0;
4004}
4005
4006/**
4007 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4008 * @pf: the PF
4009 *
4010 * This function waits for the Tx queues to be in disabled state for all the
4011 * VSIs that are managed by this PF.
4012 **/
4013static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4014{
4015 int v, ret = 0;
4016
4017 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4018 /* No need to wait for FCoE VSI queues */
4019 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4020 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4021 if (ret)
4022 break;
4023 }
4024 }
4025
4026 return ret;
4027}
4028
4029#endif
63d7e5a4
NP		 4030/**
4031 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4032 * @pf: pointer to PF
63d7e5a4
NP		 4033 *
4034 * Get TC map for ISCSI PF type that will include iSCSI TC
4035 * and LAN TC.
4036 **/
4037static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4038{
4039 struct i40e_dcb_app_priority_table app;
4040 struct i40e_hw *hw = &pf->hw;
4041 u8 enabled_tc = 1; /* TC0 is always enabled */
4042 u8 tc, i;
4043 /* Get the iSCSI APP TLV */
4044 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4045
4046 for (i = 0; i < dcbcfg->numapps; i++) {
4047 app = dcbcfg->app[i];
4048 if (app.selector == I40E_APP_SEL_TCPIP &&
4049 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4050 tc = dcbcfg->etscfg.prioritytable[app.priority];
4051 enabled_tc |= (1 << tc);
4052 break;
4053 }
4054 }
4055
4056 return enabled_tc;
4057}
4058
41c445ff
JB		 4059/**
4060 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4061 * @dcbcfg: the corresponding DCBx configuration structure
4062 *
4063 * Return the number of TCs from given DCBx configuration
4064 **/
4065static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4066{
078b5876
JB		 4067 u8 num_tc = 0;
4068 int i;
41c445ff
JB		 4069
4070 /* Scan the ETS Config Priority Table to find
4071 * traffic class enabled for a given priority
4072 * and use the traffic class index to get the
4073 * number of traffic classes enabled
4074 */
4075 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4076 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4077 num_tc = dcbcfg->etscfg.prioritytable[i];
4078 }
4079
4080 /* Traffic class index starts from zero so
4081 * increment to return the actual count
4082 */
078b5876 4083 return num_tc + 1;
41c445ff
JB		 4084}
4085
4086/**
4087 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4088 * @dcbcfg: the corresponding DCBx configuration structure
4089 *
4090 * Query the current DCB configuration and return the number of
4091 * traffic classes enabled from the given DCBX config
4092 **/
4093static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4094{
4095 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4096 u8 enabled_tc = 1;
4097 u8 i;
4098
4099 for (i = 0; i < num_tc; i++)
4100 enabled_tc |= 1 << i;
4101
4102 return enabled_tc;
4103}
4104
4105/**
4106 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4107 * @pf: PF being queried
4108 *
4109 * Return number of traffic classes enabled for the given PF
4110 **/
4111static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4112{
4113 struct i40e_hw *hw = &pf->hw;
4114 u8 i, enabled_tc;
4115 u8 num_tc = 0;
4116 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4117
4118 /* If DCB is not enabled then always in single TC */
4119 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4120 return 1;
4121
63d7e5a4
NP		 4122 /* SFP mode will be enabled for all TCs on port */
4123 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4124 return i40e_dcb_get_num_tc(dcbcfg);
4125
41c445ff 4126 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4127 if (pf->hw.func_caps.iscsi)
4128 enabled_tc = i40e_get_iscsi_tc_map(pf);
4129 else
fc51de96 4130 return 1; /* Only TC0 */
41c445ff 4131
63d7e5a4
NP		 4132 /* At least have TC0 */
4133 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4134 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4135 if (enabled_tc & (1 << i))
4136 num_tc++;
4137 }
4138 return num_tc;
41c445ff
JB		 4139}
4140
4141/**
4142 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4143 * @pf: PF being queried
4144 *
4145 * Return a bitmap for first enabled traffic class for this PF.
4146 **/
4147static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4148{
4149 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4150 u8 i = 0;
4151
4152 if (!enabled_tc)
4153 return 0x1; /* TC0 */
4154
4155 /* Find the first enabled TC */
4156 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4157 if (enabled_tc & (1 << i))
4158 break;
4159 }
4160
4161 return 1 << i;
4162}
4163
4164/**
4165 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4166 * @pf: PF being queried
4167 *
4168 * Return a bitmap for enabled traffic classes for this PF.
4169 **/
4170static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4171{
4172 /* If DCB is not enabled for this PF then just return default TC */
4173 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4174 return i40e_pf_get_default_tc(pf);
4175
41c445ff 4176 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4177 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4178 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4179
fc51de96 4180 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4181 if (pf->hw.func_caps.iscsi)
4182 return i40e_get_iscsi_tc_map(pf);
4183 else
fc51de96 4184 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4185}
4186
4187/**
4188 * i40e_vsi_get_bw_info - Query VSI BW Information
4189 * @vsi: the VSI being queried
4190 *
4191 * Returns 0 on success, negative value on failure
4192 **/
4193static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4194{
4195 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4196 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4197 struct i40e_pf *pf = vsi->back;
4198 struct i40e_hw *hw = &pf->hw;
dcae29be 4199 i40e_status aq_ret;
41c445ff 4200 u32 tc_bw_max;
41c445ff
JB		 4201 int i;
4202
4203 /* Get the VSI level BW configuration */
dcae29be
JB		 4204 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4205 if (aq_ret) {
41c445ff 4206 dev_info(&pf->pdev->dev,
b40c82e6 4207 "couldn't get PF vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4208 aq_ret, pf->hw.aq.asq_last_status);
4209 return -EINVAL;
41c445ff
JB		 4210 }
4211
4212 /* Get the VSI level BW configuration per TC */
dcae29be 4213 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4214 NULL);
dcae29be 4215 if (aq_ret) {
41c445ff 4216 dev_info(&pf->pdev->dev,
b40c82e6 4217 "couldn't get PF vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4218 aq_ret, pf->hw.aq.asq_last_status);
4219 return -EINVAL;
41c445ff
JB		 4220 }
4221
4222 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4223 dev_info(&pf->pdev->dev,
4224 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4225 bw_config.tc_valid_bits,
4226 bw_ets_config.tc_valid_bits);
4227 /* Still continuing */
4228 }
4229
4230 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4231 vsi->bw_max_quanta = bw_config.max_bw;
4232 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4233 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4234 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4235 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4236 vsi->bw_ets_limit_credits[i] =
4237 le16_to_cpu(bw_ets_config.credits[i]);
4238 /* 3 bits out of 4 for each TC */
4239 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4240 }
078b5876 4241
dcae29be 4242 return 0;
41c445ff
JB		 4243}
4244
4245/**
4246 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4247 * @vsi: the VSI being configured
4248 * @enabled_tc: TC bitmap
4249 * @bw_credits: BW shared credits per TC
4250 *
4251 * Returns 0 on success, negative value on failure
4252 **/
dcae29be 4253static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4254 u8 *bw_share)
4255{
4256 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4257 i40e_status aq_ret;
4258 int i;
41c445ff
JB		 4259
4260 bw_data.tc_valid_bits = enabled_tc;
4261 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4262 bw_data.tc_bw_credits[i] = bw_share[i];
4263
dcae29be
JB		 4264 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4265 NULL);
4266 if (aq_ret) {
41c445ff 4267 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4268 "AQ command Config VSI BW allocation per TC failed = %d\n",
4269 vsi->back->hw.aq.asq_last_status);
dcae29be 4270 return -EINVAL;
41c445ff
JB		 4271 }
4272
4273 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4274 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4275
dcae29be 4276 return 0;
41c445ff
JB		 4277}
4278
4279/**
4280 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4281 * @vsi: the VSI being configured
4282 * @enabled_tc: TC map to be enabled
4283 *
4284 **/
4285static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4286{
4287 struct net_device *netdev = vsi->netdev;
4288 struct i40e_pf *pf = vsi->back;
4289 struct i40e_hw *hw = &pf->hw;
4290 u8 netdev_tc = 0;
4291 int i;
4292 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4293
4294 if (!netdev)
4295 return;
4296
4297 if (!enabled_tc) {
4298 netdev_reset_tc(netdev);
4299 return;
4300 }
4301
4302 /* Set up actual enabled TCs on the VSI */
4303 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4304 return;
4305
4306 /* set per TC queues for the VSI */
4307 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4308 /* Only set TC queues for enabled tcs
4309 *
4310 * e.g. For a VSI that has TC0 and TC3 enabled the
4311 * enabled_tc bitmap would be 0x00001001; the driver
4312 * will set the numtc for netdev as 2 that will be
4313 * referenced by the netdev layer as TC 0 and 1.
4314 */
4315 if (vsi->tc_config.enabled_tc & (1 << i))
4316 netdev_set_tc_queue(netdev,
4317 vsi->tc_config.tc_info[i].netdev_tc,
4318 vsi->tc_config.tc_info[i].qcount,
4319 vsi->tc_config.tc_info[i].qoffset);
4320 }
4321
4322 /* Assign UP2TC map for the VSI */
4323 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4324 /* Get the actual TC# for the UP */
4325 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4326 /* Get the mapped netdev TC# for the UP */
4327 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4328 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4329 }
4330}
4331
4332/**
4333 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4334 * @vsi: the VSI being configured
4335 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4336 **/
4337static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4338 struct i40e_vsi_context *ctxt)
4339{
4340 /* copy just the sections touched not the entire info
4341 * since not all sections are valid as returned by
4342 * update vsi params
4343 */
4344 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4345 memcpy(&vsi->info.queue_mapping,
4346 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4347 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4348 sizeof(vsi->info.tc_mapping));
4349}
4350
4351/**
4352 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4353 * @vsi: VSI to be configured
4354 * @enabled_tc: TC bitmap
4355 *
4356 * This configures a particular VSI for TCs that are mapped to the
4357 * given TC bitmap. It uses default bandwidth share for TCs across
4358 * VSIs to configure TC for a particular VSI.
4359 *
4360 * NOTE:
4361 * It is expected that the VSI queues have been quisced before calling
4362 * this function.
4363 **/
4364static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4365{
4366 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4367 struct i40e_vsi_context ctxt;
4368 int ret = 0;
4369 int i;
4370
4371 /* Check if enabled_tc is same as existing or new TCs */
4372 if (vsi->tc_config.enabled_tc == enabled_tc)
4373 return ret;
4374
4375 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4376 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4377 if (enabled_tc & (1 << i))
4378 bw_share[i] = 1;
4379 }
4380
4381 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4382 if (ret) {
4383 dev_info(&vsi->back->pdev->dev,
4384 "Failed configuring TC map %d for VSI %d\n",
4385 enabled_tc, vsi->seid);
4386 goto out;
4387 }
4388
4389 /* Update Queue Pairs Mapping for currently enabled UPs */
4390 ctxt.seid = vsi->seid;
4391 ctxt.pf_num = vsi->back->hw.pf_id;
4392 ctxt.vf_num = 0;
4393 ctxt.uplink_seid = vsi->uplink_seid;
4394 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4395 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4396
4397 /* Update the VSI after updating the VSI queue-mapping information */
4398 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4399 if (ret) {
4400 dev_info(&vsi->back->pdev->dev,
4401 "update vsi failed, aq_err=%d\n",
4402 vsi->back->hw.aq.asq_last_status);
4403 goto out;
4404 }
4405 /* update the local VSI info with updated queue map */
4406 i40e_vsi_update_queue_map(vsi, &ctxt);
4407 vsi->info.valid_sections = 0;
4408
4409 /* Update current VSI BW information */
4410 ret = i40e_vsi_get_bw_info(vsi);
4411 if (ret) {
4412 dev_info(&vsi->back->pdev->dev,
4413 "Failed updating vsi bw info, aq_err=%d\n",
4414 vsi->back->hw.aq.asq_last_status);
4415 goto out;
4416 }
4417
4418 /* Update the netdev TC setup */
4419 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4420out:
4421 return ret;
4422}
4423
4e3b35b0
NP		 4424/**
4425 * i40e_veb_config_tc - Configure TCs for given VEB
4426 * @veb: given VEB
4427 * @enabled_tc: TC bitmap
4428 *
4429 * Configures given TC bitmap for VEB (switching) element
4430 **/
4431int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4432{
4433 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4434 struct i40e_pf *pf = veb->pf;
4435 int ret = 0;
4436 int i;
4437
4438 /* No TCs or already enabled TCs just return */
4439 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4440 return ret;
4441
4442 bw_data.tc_valid_bits = enabled_tc;
4443 /* bw_data.absolute_credits is not set (relative) */
4444
4445 /* Enable ETS TCs with equal BW Share for now */
4446 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4447 if (enabled_tc & (1 << i))
4448 bw_data.tc_bw_share_credits[i] = 1;
4449 }
4450
4451 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4452 &bw_data, NULL);
4453 if (ret) {
4454 dev_info(&pf->pdev->dev,
4455 "veb bw config failed, aq_err=%d\n",
4456 pf->hw.aq.asq_last_status);
4457 goto out;
4458 }
4459
4460 /* Update the BW information */
4461 ret = i40e_veb_get_bw_info(veb);
4462 if (ret) {
4463 dev_info(&pf->pdev->dev,
4464 "Failed getting veb bw config, aq_err=%d\n",
4465 pf->hw.aq.asq_last_status);
4466 }
4467
4468out:
4469 return ret;
4470}
4471
4472#ifdef CONFIG_I40E_DCB
4473/**
4474 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4475 * @pf: PF struct
4476 *
4477 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4478 * the caller would've quiesce all the VSIs before calling
4479 * this function
4480 **/
4481static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4482{
4483 u8 tc_map = 0;
4484 int ret;
4485 u8 v;
4486
4487 /* Enable the TCs available on PF to all VEBs */
4488 tc_map = i40e_pf_get_tc_map(pf);
4489 for (v = 0; v < I40E_MAX_VEB; v++) {
4490 if (!pf->veb[v])
4491 continue;
4492 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4493 if (ret) {
4494 dev_info(&pf->pdev->dev,
4495 "Failed configuring TC for VEB seid=%d\n",
4496 pf->veb[v]->seid);
4497 /* Will try to configure as many components */
4498 }
4499 }
4500
4501 /* Update each VSI */
505682cd 4502 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4503 if (!pf->vsi[v])
4504 continue;
4505
4506 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4507#ifdef I40E_FCOE
4508 * - For FCoE VSI only enable the TC configured
4509 * as per the APP TLV
4510#endif
4e3b35b0
NP		 4511 * - For all others keep them at TC0 for now
4512 */
4513 if (v == pf->lan_vsi)
4514 tc_map = i40e_pf_get_tc_map(pf);
4515 else
4516 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4517#ifdef I40E_FCOE
4518 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4519 tc_map = i40e_get_fcoe_tc_map(pf);
4520#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4521
4522 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4523 if (ret) {
4524 dev_info(&pf->pdev->dev,
4525 "Failed configuring TC for VSI seid=%d\n",
4526 pf->vsi[v]->seid);
4527 /* Will try to configure as many components */
4528 } else {
0672a091
NP		 4529 /* Re-configure VSI vectors based on updated TC map */
4530 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4531 if (pf->vsi[v]->netdev)
4532 i40e_dcbnl_set_all(pf->vsi[v]);
4533 }
4534 }
4535}
4536
2fd75f31
NP		 4537/**
4538 * i40e_resume_port_tx - Resume port Tx
4539 * @pf: PF struct
4540 *
4541 * Resume a port's Tx and issue a PF reset in case of failure to
4542 * resume.
4543 **/
4544static int i40e_resume_port_tx(struct i40e_pf *pf)
4545{
4546 struct i40e_hw *hw = &pf->hw;
4547 int ret;
4548
4549 ret = i40e_aq_resume_port_tx(hw, NULL);
4550 if (ret) {
4551 dev_info(&pf->pdev->dev,
4552 "AQ command Resume Port Tx failed = %d\n",
4553 pf->hw.aq.asq_last_status);
4554 /* Schedule PF reset to recover */
4555 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4556 i40e_service_event_schedule(pf);
4557 }
4558
4559 return ret;
4560}
4561
4e3b35b0
NP		 4562/**
4563 * i40e_init_pf_dcb - Initialize DCB configuration
4564 * @pf: PF being configured
4565 *
4566 * Query the current DCB configuration and cache it
4567 * in the hardware structure
4568 **/
4569static int i40e_init_pf_dcb(struct i40e_pf *pf)
4570{
4571 struct i40e_hw *hw = &pf->hw;
4572 int err = 0;
4573
025b4a54
ASJ		 4574 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4575 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4576 (pf->hw.aq.fw_maj_ver < 4))
4577 goto out;
4578
4e3b35b0
NP		 4579 /* Get the initial DCB configuration */
4580 err = i40e_init_dcb(hw);
4581 if (!err) {
4582 /* Device/Function is not DCBX capable */
4583 if ((!hw->func_caps.dcb) ||
4584 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4585 dev_info(&pf->pdev->dev,
4586 "DCBX offload is not supported or is disabled for this PF.\n");
4587
4588 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4589 goto out;
4590
4591 } else {
4592 /* When status is not DISABLED then DCBX in FW */
4593 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4594 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4595
4596 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4597 /* Enable DCB tagging only when more than one TC */
4598 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4599 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4600 dev_dbg(&pf->pdev->dev,
4601 "DCBX offload is supported for this PF.\n");
4e3b35b0 4602 }
014269ff 4603 } else {
aebfc816
SN		 4604 dev_info(&pf->pdev->dev,
4605 "AQ Querying DCB configuration failed: aq_err %d\n",
014269ff 4606 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4607 }
4608
4609out:
4610 return err;
4611}
4612#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4613#define SPEED_SIZE 14
4614#define FC_SIZE 8
4615/**
4616 * i40e_print_link_message - print link up or down
4617 * @vsi: the VSI for which link needs a message
4618 */
4619static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4620{
4621 char speed[SPEED_SIZE] = "Unknown";
4622 char fc[FC_SIZE] = "RX/TX";
4623
4624 if (!isup) {
4625 netdev_info(vsi->netdev, "NIC Link is Down\n");
4626 return;
4627 }
4628
148c2d80
GR		 4629 /* Warn user if link speed on NPAR enabled partition is not at
4630 * least 10GB
4631 */
4632 if (vsi->back->hw.func_caps.npar_enable &&
4633 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
4634 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
4635 netdev_warn(vsi->netdev,
4636 "The partition detected link speed that is less than 10Gbps\n");
4637
cf05ed08
JB		 4638 switch (vsi->back->hw.phy.link_info.link_speed) {
4639 case I40E_LINK_SPEED_40GB:
35a7d804 4640 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4641 break;
4642 case I40E_LINK_SPEED_10GB:
35a7d804 4643 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4644 break;
4645 case I40E_LINK_SPEED_1GB:
35a7d804 4646 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4647 break;
5960d33f
MW		 4648 case I40E_LINK_SPEED_100MB:
4649 strncpy(speed, "100 Mbps", SPEED_SIZE);
4650 break;
cf05ed08
JB		 4651 default:
4652 break;
4653 }
4654
4655 switch (vsi->back->hw.fc.current_mode) {
4656 case I40E_FC_FULL:
35a7d804 4657 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4658 break;
4659 case I40E_FC_TX_PAUSE:
35a7d804 4660 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4661 break;
4662 case I40E_FC_RX_PAUSE:
35a7d804 4663 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4664 break;
4665 default:
35a7d804 4666 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4667 break;
4668 }
4669
4670 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4671 speed, fc);
4672}
4e3b35b0 4673
41c445ff
JB		 4674/**
4675 * i40e_up_complete - Finish the last steps of bringing up a connection
4676 * @vsi: the VSI being configured
4677 **/
4678static int i40e_up_complete(struct i40e_vsi *vsi)
4679{
4680 struct i40e_pf *pf = vsi->back;
4681 int err;
4682
4683 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4684 i40e_vsi_configure_msix(vsi);
4685 else
4686 i40e_configure_msi_and_legacy(vsi);
4687
4688 /* start rings */
4689 err = i40e_vsi_control_rings(vsi, true);
4690 if (err)
4691 return err;
4692
4693 clear_bit(__I40E_DOWN, &vsi->state);
4694 i40e_napi_enable_all(vsi);
4695 i40e_vsi_enable_irq(vsi);
4696
4697 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4698 (vsi->netdev)) {
cf05ed08 4699 i40e_print_link_message(vsi, true);
41c445ff
JB		 4700 netif_tx_start_all_queues(vsi->netdev);
4701 netif_carrier_on(vsi->netdev);
6d779b41 4702 } else if (vsi->netdev) {
cf05ed08 4703 i40e_print_link_message(vsi, false);
7b592f61
CW		 4704 /* need to check for qualified module here*/
4705 if ((pf->hw.phy.link_info.link_info &
4706 I40E_AQ_MEDIA_AVAILABLE) &&
4707 (!(pf->hw.phy.link_info.an_info &
4708 I40E_AQ_QUALIFIED_MODULE)))
4709 netdev_err(vsi->netdev,
4710 "the driver failed to link because an unqualified module was detected.");
41c445ff 4711 }
ca64fa4e
ASJ		 4712
4713 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4714 if (vsi->type == I40E_VSI_FDIR) {
4715 /* reset fd counters */
4716 pf->fd_add_err = pf->fd_atr_cnt = 0;
4717 if (pf->fd_tcp_rule > 0) {
4718 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4719 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4720 pf->fd_tcp_rule = 0;
4721 }
ca64fa4e 4722 i40e_fdir_filter_restore(vsi);
1e1be8f6 4723 }
41c445ff
JB		 4724 i40e_service_event_schedule(pf);
4725
4726 return 0;
4727}
4728
4729/**
4730 * i40e_vsi_reinit_locked - Reset the VSI
4731 * @vsi: the VSI being configured
4732 *
4733 * Rebuild the ring structs after some configuration
4734 * has changed, e.g. MTU size.
4735 **/
4736static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4737{
4738 struct i40e_pf *pf = vsi->back;
4739
4740 WARN_ON(in_interrupt());
4741 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4742 usleep_range(1000, 2000);
4743 i40e_down(vsi);
4744
4745 /* Give a VF some time to respond to the reset. The
4746 * two second wait is based upon the watchdog cycle in
4747 * the VF driver.
4748 */
4749 if (vsi->type == I40E_VSI_SRIOV)
4750 msleep(2000);
4751 i40e_up(vsi);
4752 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4753}
4754
4755/**
4756 * i40e_up - Bring the connection back up after being down
4757 * @vsi: the VSI being configured
4758 **/
4759int i40e_up(struct i40e_vsi *vsi)
4760{
4761 int err;
4762
4763 err = i40e_vsi_configure(vsi);
4764 if (!err)
4765 err = i40e_up_complete(vsi);
4766
4767 return err;
4768}
4769
4770/**
4771 * i40e_down - Shutdown the connection processing
4772 * @vsi: the VSI being stopped
4773 **/
4774void i40e_down(struct i40e_vsi *vsi)
4775{
4776 int i;
4777
4778 /* It is assumed that the caller of this function
4779 * sets the vsi->state __I40E_DOWN bit.
4780 */
4781 if (vsi->netdev) {
4782 netif_carrier_off(vsi->netdev);
4783 netif_tx_disable(vsi->netdev);
4784 }
4785 i40e_vsi_disable_irq(vsi);
4786 i40e_vsi_control_rings(vsi, false);
4787 i40e_napi_disable_all(vsi);
4788
4789 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4790 i40e_clean_tx_ring(vsi->tx_rings[i]);
4791 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4792 }
4793}
4794
4795/**
4796 * i40e_setup_tc - configure multiple traffic classes
4797 * @netdev: net device to configure
4798 * @tc: number of traffic classes to enable
4799 **/
38e00438
VD		 4800#ifdef I40E_FCOE
4801int i40e_setup_tc(struct net_device *netdev, u8 tc)
4802#else
41c445ff 4803static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4804#endif
41c445ff
JB		 4805{
4806 struct i40e_netdev_priv *np = netdev_priv(netdev);
4807 struct i40e_vsi *vsi = np->vsi;
4808 struct i40e_pf *pf = vsi->back;
4809 u8 enabled_tc = 0;
4810 int ret = -EINVAL;
4811 int i;
4812
4813 /* Check if DCB enabled to continue */
4814 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4815 netdev_info(netdev, "DCB is not enabled for adapter\n");
4816 goto exit;
4817 }
4818
4819 /* Check if MFP enabled */
4820 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4821 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4822 goto exit;
4823 }
4824
4825 /* Check whether tc count is within enabled limit */
4826 if (tc > i40e_pf_get_num_tc(pf)) {
4827 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4828 goto exit;
4829 }
4830
4831 /* Generate TC map for number of tc requested */
4832 for (i = 0; i < tc; i++)
4833 enabled_tc |= (1 << i);
4834
4835 /* Requesting same TC configuration as already enabled */
4836 if (enabled_tc == vsi->tc_config.enabled_tc)
4837 return 0;
4838
4839 /* Quiesce VSI queues */
4840 i40e_quiesce_vsi(vsi);
4841
4842 /* Configure VSI for enabled TCs */
4843 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4844 if (ret) {
4845 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4846 vsi->seid);
4847 goto exit;
4848 }
4849
4850 /* Unquiesce VSI */
4851 i40e_unquiesce_vsi(vsi);
4852
4853exit:
4854 return ret;
4855}
4856
4857/**
4858 * i40e_open - Called when a network interface is made active
4859 * @netdev: network interface device structure
4860 *
4861 * The open entry point is called when a network interface is made
4862 * active by the system (IFF_UP). At this point all resources needed
4863 * for transmit and receive operations are allocated, the interrupt
4864 * handler is registered with the OS, the netdev watchdog subtask is
4865 * enabled, and the stack is notified that the interface is ready.
4866 *
4867 * Returns 0 on success, negative value on failure
4868 **/
38e00438 4869int i40e_open(struct net_device *netdev)
41c445ff
JB		 4870{
4871 struct i40e_netdev_priv *np = netdev_priv(netdev);
4872 struct i40e_vsi *vsi = np->vsi;
4873 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4874 int err;
4875
4eb3f768
SN		 4876 /* disallow open during test or if eeprom is broken */
4877 if (test_bit(__I40E_TESTING, &pf->state) ||
4878 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4879 return -EBUSY;
4880
4881 netif_carrier_off(netdev);
4882
6c167f58
EK		 4883 err = i40e_vsi_open(vsi);
4884 if (err)
4885 return err;
4886
059dab69
JB		 4887 /* configure global TSO hardware offload settings */
4888 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4889 TCP_FLAG_FIN) >> 16);
4890 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4891 TCP_FLAG_FIN |
4892 TCP_FLAG_CWR) >> 16);
4893 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4894
6c167f58
EK		 4895#ifdef CONFIG_I40E_VXLAN
4896 vxlan_get_rx_port(netdev);
4897#endif
4898
4899 return 0;
4900}
4901
4902/**
4903 * i40e_vsi_open -
4904 * @vsi: the VSI to open
4905 *
4906 * Finish initialization of the VSI.
4907 *
4908 * Returns 0 on success, negative value on failure
4909 **/
4910int i40e_vsi_open(struct i40e_vsi *vsi)
4911{
4912 struct i40e_pf *pf = vsi->back;
b294ac70 4913 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 4914 int err;
4915
41c445ff
JB		 4916 /* allocate descriptors */
4917 err = i40e_vsi_setup_tx_resources(vsi);
4918 if (err)
4919 goto err_setup_tx;
4920 err = i40e_vsi_setup_rx_resources(vsi);
4921 if (err)
4922 goto err_setup_rx;
4923
4924 err = i40e_vsi_configure(vsi);
4925 if (err)
4926 goto err_setup_rx;
4927
c22e3c6c
SN		 4928 if (vsi->netdev) {
4929 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4930 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4931 err = i40e_vsi_request_irq(vsi, int_name);
4932 if (err)
4933 goto err_setup_rx;
41c445ff 4934
c22e3c6c
SN		 4935 /* Notify the stack of the actual queue counts. */
4936 err = netif_set_real_num_tx_queues(vsi->netdev,
4937 vsi->num_queue_pairs);
4938 if (err)
4939 goto err_set_queues;
25946ddb 4940
c22e3c6c
SN		 4941 err = netif_set_real_num_rx_queues(vsi->netdev,
4942 vsi->num_queue_pairs);
4943 if (err)
4944 goto err_set_queues;
8a9eb7d3
SN		 4945
4946 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 4947 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 4948 dev_driver_string(&pf->pdev->dev),
4949 dev_name(&pf->pdev->dev));
8a9eb7d3 4950 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 4951
c22e3c6c 4952 } else {
ce9ccb17 4953 err = -EINVAL;
6c167f58
EK		 4954 goto err_setup_rx;
4955 }
25946ddb 4956
41c445ff
JB		 4957 err = i40e_up_complete(vsi);
4958 if (err)
4959 goto err_up_complete;
4960
41c445ff
JB		 4961 return 0;
4962
4963err_up_complete:
4964 i40e_down(vsi);
25946ddb 4965err_set_queues:
41c445ff
JB		 4966 i40e_vsi_free_irq(vsi);
4967err_setup_rx:
4968 i40e_vsi_free_rx_resources(vsi);
4969err_setup_tx:
4970 i40e_vsi_free_tx_resources(vsi);
4971 if (vsi == pf->vsi[pf->lan_vsi])
4972 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4973
4974 return err;
4975}
4976
17a73f6b
JG		 4977/**
4978 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 4979 * @pf: Pointer to PF
17a73f6b
JG		 4980 *
4981 * This function destroys the hlist where all the Flow Director
4982 * filters were saved.
4983 **/
4984static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4985{
4986 struct i40e_fdir_filter *filter;
4987 struct hlist_node *node2;
4988
4989 hlist_for_each_entry_safe(filter, node2,
4990 &pf->fdir_filter_list, fdir_node) {
4991 hlist_del(&filter->fdir_node);
4992 kfree(filter);
4993 }
4994 pf->fdir_pf_active_filters = 0;
4995}
4996
41c445ff
JB		 4997/**
4998 * i40e_close - Disables a network interface
4999 * @netdev: network interface device structure
5000 *
5001 * The close entry point is called when an interface is de-activated
5002 * by the OS. The hardware is still under the driver's control, but
5003 * this netdev interface is disabled.
5004 *
5005 * Returns 0, this is not allowed to fail
5006 **/
38e00438
VD		 5007#ifdef I40E_FCOE
5008int i40e_close(struct net_device *netdev)
5009#else
41c445ff 5010static int i40e_close(struct net_device *netdev)
38e00438 5011#endif
41c445ff
JB		 5012{
5013 struct i40e_netdev_priv *np = netdev_priv(netdev);
5014 struct i40e_vsi *vsi = np->vsi;
5015
90ef8d47 5016 i40e_vsi_close(vsi);
41c445ff
JB		 5017
5018 return 0;
5019}
5020
5021/**
5022 * i40e_do_reset - Start a PF or Core Reset sequence
5023 * @pf: board private structure
5024 * @reset_flags: which reset is requested
5025 *
5026 * The essential difference in resets is that the PF Reset
5027 * doesn't clear the packet buffers, doesn't reset the PE
5028 * firmware, and doesn't bother the other PFs on the chip.
5029 **/
5030void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5031{
5032 u32 val;
5033
5034 WARN_ON(in_interrupt());
5035
263fc48f
MW		 5036 if (i40e_check_asq_alive(&pf->hw))
5037 i40e_vc_notify_reset(pf);
5038
41c445ff
JB		 5039 /* do the biggest reset indicated */
5040 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
5041
5042 /* Request a Global Reset
5043 *
5044 * This will start the chip's countdown to the actual full
5045 * chip reset event, and a warning interrupt to be sent
5046 * to all PFs, including the requestor. Our handler
5047 * for the warning interrupt will deal with the shutdown
5048 * and recovery of the switch setup.
5049 */
69bfb110 5050 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5051 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5052 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5053 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5054
5055 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
5056
5057 /* Request a Core Reset
5058 *
5059 * Same as Global Reset, except does *not* include the MAC/PHY
5060 */
69bfb110 5061 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5062 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5063 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5064 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5065 i40e_flush(&pf->hw);
5066
5067 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
5068
5069 /* Request a PF Reset
5070 *
5071 * Resets only the PF-specific registers
5072 *
5073 * This goes directly to the tear-down and rebuild of
5074 * the switch, since we need to do all the recovery as
5075 * for the Core Reset.
5076 */
69bfb110 5077 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5078 i40e_handle_reset_warning(pf);
5079
5080 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
5081 int v;
5082
5083 /* Find the VSI(s) that requested a re-init */
5084 dev_info(&pf->pdev->dev,
5085 "VSI reinit requested\n");
505682cd 5086 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5087 struct i40e_vsi *vsi = pf->vsi[v];
5088 if (vsi != NULL &&
5089 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5090 i40e_vsi_reinit_locked(pf->vsi[v]);
5091 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5092 }
5093 }
5094
b5d06f05
NP		 5095 /* no further action needed, so return now */
5096 return;
5097 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
5098 int v;
5099
5100 /* Find the VSI(s) that needs to be brought down */
5101 dev_info(&pf->pdev->dev, "VSI down requested\n");
5102 for (v = 0; v < pf->num_alloc_vsi; v++) {
5103 struct i40e_vsi *vsi = pf->vsi[v];
5104 if (vsi != NULL &&
5105 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5106 set_bit(__I40E_DOWN, &vsi->state);
5107 i40e_down(vsi);
5108 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5109 }
5110 }
5111
41c445ff
JB		 5112 /* no further action needed, so return now */
5113 return;
5114 } else {
5115 dev_info(&pf->pdev->dev,
5116 "bad reset request 0x%08x\n", reset_flags);
5117 return;
5118 }
5119}
5120
4e3b35b0
NP		 5121#ifdef CONFIG_I40E_DCB
5122/**
5123 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5124 * @pf: board private structure
5125 * @old_cfg: current DCB config
5126 * @new_cfg: new DCB config
5127 **/
5128bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5129 struct i40e_dcbx_config *old_cfg,
5130 struct i40e_dcbx_config *new_cfg)
5131{
5132 bool need_reconfig = false;
5133
5134 /* Check if ETS configuration has changed */
5135 if (memcmp(&new_cfg->etscfg,
5136 &old_cfg->etscfg,
5137 sizeof(new_cfg->etscfg))) {
5138 /* If Priority Table has changed reconfig is needed */
5139 if (memcmp(&new_cfg->etscfg.prioritytable,
5140 &old_cfg->etscfg.prioritytable,
5141 sizeof(new_cfg->etscfg.prioritytable))) {
5142 need_reconfig = true;
69bfb110 5143 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5144 }
5145
5146 if (memcmp(&new_cfg->etscfg.tcbwtable,
5147 &old_cfg->etscfg.tcbwtable,
5148 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5149 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5150
5151 if (memcmp(&new_cfg->etscfg.tsatable,
5152 &old_cfg->etscfg.tsatable,
5153 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5154 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5155 }
5156
5157 /* Check if PFC configuration has changed */
5158 if (memcmp(&new_cfg->pfc,
5159 &old_cfg->pfc,
5160 sizeof(new_cfg->pfc))) {
5161 need_reconfig = true;
69bfb110 5162 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5163 }
5164
5165 /* Check if APP Table has changed */
5166 if (memcmp(&new_cfg->app,
5167 &old_cfg->app,
3d9667a9 5168 sizeof(new_cfg->app))) {
4e3b35b0 5169 need_reconfig = true;
69bfb110 5170 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5171 }
4e3b35b0 5172
9fa61dd2
NP		 5173 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5174 need_reconfig);
4e3b35b0
NP		 5175 return need_reconfig;
5176}
5177
5178/**
5179 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5180 * @pf: board private structure
5181 * @e: event info posted on ARQ
5182 **/
5183static int i40e_handle_lldp_event(struct i40e_pf *pf,
5184 struct i40e_arq_event_info *e)
5185{
5186 struct i40e_aqc_lldp_get_mib *mib =
5187 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5188 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5189 struct i40e_dcbx_config tmp_dcbx_cfg;
5190 bool need_reconfig = false;
5191 int ret = 0;
5192 u8 type;
5193
4d9b6043
NP		 5194 /* Not DCB capable or capability disabled */
5195 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5196 return ret;
5197
4e3b35b0
NP		 5198 /* Ignore if event is not for Nearest Bridge */
5199 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5200 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5201 dev_dbg(&pf->pdev->dev,
5202 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5203 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5204 return ret;
5205
5206 /* Check MIB Type and return if event for Remote MIB update */
5207 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5208 dev_dbg(&pf->pdev->dev,
5209 "%s: LLDP event mib type %s\n", __func__,
5210 type ? "remote" : "local");
4e3b35b0
NP		 5211 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5212 /* Update the remote cached instance and return */
5213 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5214 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5215 &hw->remote_dcbx_config);
5216 goto exit;
5217 }
5218
4e3b35b0 5219 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
9fa61dd2 5220 /* Store the old configuration */
750fcbcf 5221 memcpy(&tmp_dcbx_cfg, &hw->local_dcbx_config, sizeof(tmp_dcbx_cfg));
9fa61dd2 5222
750fcbcf
NP		 5223 /* Reset the old DCBx configuration data */
5224 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5225 /* Get updated DCBX data from firmware */
5226 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5227 if (ret) {
9fa61dd2 5228 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5229 goto exit;
5230 }
5231
5232 /* No change detected in DCBX configs */
750fcbcf
NP		 5233 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5234 sizeof(tmp_dcbx_cfg))) {
69bfb110 5235 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5236 goto exit;
5237 }
5238
750fcbcf
NP		 5239 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5240 &hw->local_dcbx_config);
4e3b35b0 5241
750fcbcf 5242 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5243
5244 if (!need_reconfig)
5245 goto exit;
5246
4d9b6043 5247 /* Enable DCB tagging only when more than one TC */
750fcbcf 5248 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5249 pf->flags |= I40E_FLAG_DCB_ENABLED;
5250 else
5251 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5252
69129dc3 5253 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5254 /* Reconfiguration needed quiesce all VSIs */
5255 i40e_pf_quiesce_all_vsi(pf);
5256
5257 /* Changes in configuration update VEB/VSI */
5258 i40e_dcb_reconfigure(pf);
5259
2fd75f31
NP		 5260 ret = i40e_resume_port_tx(pf);
5261
69129dc3 5262 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5263 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5264 if (ret)
5265 goto exit;
5266
5267 /* Wait for the PF's Tx queues to be disabled */
5268 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5269 if (ret) {
5270 /* Schedule PF reset to recover */
5271 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5272 i40e_service_event_schedule(pf);
5273 } else {
2fd75f31 5274 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5275 }
5276
4e3b35b0
NP		 5277exit:
5278 return ret;
5279}
5280#endif /* CONFIG_I40E_DCB */
5281
23326186
ASJ		 5282/**
5283 * i40e_do_reset_safe - Protected reset path for userland calls.
5284 * @pf: board private structure
5285 * @reset_flags: which reset is requested
5286 *
5287 **/
5288void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5289{
5290 rtnl_lock();
5291 i40e_do_reset(pf, reset_flags);
5292 rtnl_unlock();
5293}
5294
41c445ff
JB		 5295/**
5296 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5297 * @pf: board private structure
5298 * @e: event info posted on ARQ
5299 *
5300 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5301 * and VF queues
5302 **/
5303static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5304 struct i40e_arq_event_info *e)
5305{
5306 struct i40e_aqc_lan_overflow *data =
5307 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5308 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5309 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5310 struct i40e_hw *hw = &pf->hw;
5311 struct i40e_vf *vf;
5312 u16 vf_id;
5313
69bfb110
JB		 5314 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5315 queue, qtx_ctl);
41c445ff
JB		 5316
5317 /* Queue belongs to VF, find the VF and issue VF reset */
5318 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5319 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5320 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5321 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5322 vf_id -= hw->func_caps.vf_base_id;
5323 vf = &pf->vf[vf_id];
5324 i40e_vc_notify_vf_reset(vf);
5325 /* Allow VF to process pending reset notification */
5326 msleep(20);
5327 i40e_reset_vf(vf, false);
5328 }
5329}
5330
5331/**
5332 * i40e_service_event_complete - Finish up the service event
5333 * @pf: board private structure
5334 **/
5335static void i40e_service_event_complete(struct i40e_pf *pf)
5336{
5337 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5338
5339 /* flush memory to make sure state is correct before next watchog */
4e857c58 5340 smp_mb__before_atomic();
41c445ff
JB		 5341 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5342}
5343
55a5e60b 5344/**
12957388
ASJ		 5345 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5346 * @pf: board private structure
5347 **/
04294e38 5348u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5349{
04294e38 5350 u32 val, fcnt_prog;
12957388
ASJ		 5351
5352 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5353 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5354 return fcnt_prog;
5355}
5356
5357/**
04294e38 5358 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5359 * @pf: board private structure
5360 **/
04294e38 5361u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5362{
04294e38
ASJ		 5363 u32 val, fcnt_prog;
5364
55a5e60b
ASJ		 5365 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5366 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5367 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5368 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5369 return fcnt_prog;
5370}
1e1be8f6 5371
04294e38
ASJ		 5372/**
5373 * i40e_get_global_fd_count - Get total FD filters programmed on device
5374 * @pf: board private structure
5375 **/
5376u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5377{
5378 u32 val, fcnt_prog;
5379
5380 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5381 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5382 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5383 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5384 return fcnt_prog;
5385}
5386
55a5e60b
ASJ		 5387/**
5388 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5389 * @pf: board private structure
5390 **/
5391void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5392{
5393 u32 fcnt_prog, fcnt_avail;
5394
1e1be8f6
ASJ		 5395 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5396 return;
5397
55a5e60b
ASJ		 5398 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5399 * to re-enable
5400 */
04294e38 5401 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5402 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5403 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5404 (pf->fd_add_err == 0) ||
5405 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5406 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5407 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5408 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5409 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5410 }
5411 }
5412 /* Wait for some more space to be available to turn on ATR */
5413 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5414 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5415 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5416 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5417 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5418 }
5419 }
5420}
5421
1e1be8f6 5422#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5423#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5424/**
5425 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5426 * @pf: board private structure
5427 **/
5428static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5429{
04294e38 5430 unsigned long min_flush_time;
1e1be8f6 5431 int flush_wait_retry = 50;
04294e38
ASJ		 5432 bool disable_atr = false;
5433 int fd_room;
1e1be8f6
ASJ		 5434 int reg;
5435
1790ed0c
AA		 5436 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5437 return;
5438
1e1be8f6
ASJ		 5439 if (time_after(jiffies, pf->fd_flush_timestamp +
5440 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
04294e38
ASJ		 5441 /* If the flush is happening too quick and we have mostly
5442 * SB rules we should not re-enable ATR for some time.
5443 */
5444 min_flush_time = pf->fd_flush_timestamp
5445 + (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5446 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5447
5448 if (!(time_after(jiffies, min_flush_time)) &&
5449 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5450 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5451 disable_atr = true;
5452 }
5453
1e1be8f6 5454 pf->fd_flush_timestamp = jiffies;
1e1be8f6
ASJ		 5455 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5456 /* flush all filters */
5457 wr32(&pf->hw, I40E_PFQF_CTL_1,
5458 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5459 i40e_flush(&pf->hw);
60793f4a 5460 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5461 pf->fd_add_err = 0;
5462 do {
5463 /* Check FD flush status every 5-6msec */
5464 usleep_range(5000, 6000);
5465 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5466 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5467 break;
5468 } while (flush_wait_retry--);
5469 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5470 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5471 } else {
5472 /* replay sideband filters */
5473 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
04294e38
ASJ		 5474 if (!disable_atr)
5475 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
1e1be8f6
ASJ		 5476 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5477 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5478 }
5479 }
5480}
5481
5482/**
5483 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5484 * @pf: board private structure
5485 **/
04294e38 5486u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5487{
5488 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5489}
5490
5491/* We can see up to 256 filter programming desc in transit if the filters are
5492 * being applied really fast; before we see the first
5493 * filter miss error on Rx queue 0. Accumulating enough error messages before
5494 * reacting will make sure we don't cause flush too often.
5495 */
5496#define I40E_MAX_FD_PROGRAM_ERROR 256
5497
41c445ff
JB		 5498/**
5499 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5500 * @pf: board private structure
5501 **/
5502static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5503{
41c445ff 5504
41c445ff
JB		 5505 /* if interface is down do nothing */
5506 if (test_bit(__I40E_DOWN, &pf->state))
5507 return;
1e1be8f6 5508
1790ed0c
AA		 5509 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5510 return;
5511
04294e38 5512 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5513 i40e_fdir_flush_and_replay(pf);
5514
55a5e60b
ASJ		 5515 i40e_fdir_check_and_reenable(pf);
5516
41c445ff
JB		 5517}
5518
5519/**
5520 * i40e_vsi_link_event - notify VSI of a link event
5521 * @vsi: vsi to be notified
5522 * @link_up: link up or down
5523 **/
5524static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5525{
32b5b811 5526 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5527 return;
5528
5529 switch (vsi->type) {
5530 case I40E_VSI_MAIN:
38e00438
VD		 5531#ifdef I40E_FCOE
5532 case I40E_VSI_FCOE:
5533#endif
41c445ff
JB		 5534 if (!vsi->netdev || !vsi->netdev_registered)
5535 break;
5536
5537 if (link_up) {
5538 netif_carrier_on(vsi->netdev);
5539 netif_tx_wake_all_queues(vsi->netdev);
5540 } else {
5541 netif_carrier_off(vsi->netdev);
5542 netif_tx_stop_all_queues(vsi->netdev);
5543 }
5544 break;
5545
5546 case I40E_VSI_SRIOV:
41c445ff
JB		 5547 case I40E_VSI_VMDQ2:
5548 case I40E_VSI_CTRL:
5549 case I40E_VSI_MIRROR:
5550 default:
5551 /* there is no notification for other VSIs */
5552 break;
5553 }
5554}
5555
5556/**
5557 * i40e_veb_link_event - notify elements on the veb of a link event
5558 * @veb: veb to be notified
5559 * @link_up: link up or down
5560 **/
5561static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5562{
5563 struct i40e_pf *pf;
5564 int i;
5565
5566 if (!veb || !veb->pf)
5567 return;
5568 pf = veb->pf;
5569
5570 /* depth first... */
5571 for (i = 0; i < I40E_MAX_VEB; i++)
5572 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5573 i40e_veb_link_event(pf->veb[i], link_up);
5574
5575 /* ... now the local VSIs */
505682cd 5576 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5577 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5578 i40e_vsi_link_event(pf->vsi[i], link_up);
5579}
5580
5581/**
5582 * i40e_link_event - Update netif_carrier status
5583 * @pf: board private structure
5584 **/
5585static void i40e_link_event(struct i40e_pf *pf)
5586{
5587 bool new_link, old_link;
320684cd 5588 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 5589 u8 new_link_speed, old_link_speed;
41c445ff 5590
1e701e09
JB		 5591 /* set this to force the get_link_status call to refresh state */
5592 pf->hw.phy.get_link_info = true;
5593
41c445ff 5594 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5595 new_link = i40e_get_link_status(&pf->hw);
fef59ddf
CS		 5596 old_link_speed = pf->hw.phy.link_info_old.link_speed;
5597 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 5598
1e701e09 5599 if (new_link == old_link &&
fef59ddf 5600 new_link_speed == old_link_speed &&
320684cd
MW		 5601 (test_bit(__I40E_DOWN, &vsi->state) ||
5602 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5603 return;
320684cd
MW		 5604
5605 if (!test_bit(__I40E_DOWN, &vsi->state))
5606 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5607
5608 /* Notify the base of the switch tree connected to
5609 * the link. Floating VEBs are not notified.
5610 */
5611 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5612 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5613 else
320684cd 5614 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5615
5616 if (pf->vf)
5617 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5618
5619 if (pf->flags & I40E_FLAG_PTP)
5620 i40e_ptp_set_increment(pf);
41c445ff
JB		 5621}
5622
5623/**
5624 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5625 * @pf: board private structure
5626 *
5627 * Set the per-queue flags to request a check for stuck queues in the irq
5628 * clean functions, then force interrupts to be sure the irq clean is called.
5629 **/
5630static void i40e_check_hang_subtask(struct i40e_pf *pf)
5631{
5632 int i, v;
5633
5634 /* If we're down or resetting, just bail */
b67a0335
AA		 5635 if (test_bit(__I40E_DOWN, &pf->state) ||
5636 test_bit(__I40E_CONFIG_BUSY, &pf->state))
41c445ff
JB		 5637 return;
5638
5639 /* for each VSI/netdev
5640 * for each Tx queue
5641 * set the check flag
5642 * for each q_vector
5643 * force an interrupt
5644 */
505682cd 5645 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5646 struct i40e_vsi *vsi = pf->vsi[v];
5647 int armed = 0;
5648
5649 if (!pf->vsi[v] ||
5650 test_bit(__I40E_DOWN, &vsi->state) ||
5651 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5652 continue;
5653
5654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5655 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5656 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5657 &vsi->tx_rings[i]->state))
41c445ff
JB		 5658 armed++;
5659 }
5660
5661 if (armed) {
5662 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5663 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5664 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5665 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5666 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5667 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5668 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5669 } else {
5670 u16 vec = vsi->base_vector - 1;
5671 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5672 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5673 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5674 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5675 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5676 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5677 wr32(&vsi->back->hw,
5678 I40E_PFINT_DYN_CTLN(vec), val);
5679 }
5680 i40e_flush(&vsi->back->hw);
5681 }
5682 }
5683}
5684
5685/**
21536717 5686 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5687 * @pf: board private structure
5688 **/
5689static void i40e_watchdog_subtask(struct i40e_pf *pf)
5690{
5691 int i;
5692
5693 /* if interface is down do nothing */
5694 if (test_bit(__I40E_DOWN, &pf->state) ||
5695 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5696 return;
5697
21536717
SN		 5698 /* make sure we don't do these things too often */
5699 if (time_before(jiffies, (pf->service_timer_previous +
5700 pf->service_timer_period)))
5701 return;
5702 pf->service_timer_previous = jiffies;
5703
5704 i40e_check_hang_subtask(pf);
5705 i40e_link_event(pf);
5706
41c445ff
JB		 5707 /* Update the stats for active netdevs so the network stack
5708 * can look at updated numbers whenever it cares to
5709 */
505682cd 5710 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5711 if (pf->vsi[i] && pf->vsi[i]->netdev)
5712 i40e_update_stats(pf->vsi[i]);
5713
5714 /* Update the stats for the active switching components */
5715 for (i = 0; i < I40E_MAX_VEB; i++)
5716 if (pf->veb[i])
5717 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5718
5719 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5720}
5721
5722/**
5723 * i40e_reset_subtask - Set up for resetting the device and driver
5724 * @pf: board private structure
5725 **/
5726static void i40e_reset_subtask(struct i40e_pf *pf)
5727{
5728 u32 reset_flags = 0;
5729
23326186 5730 rtnl_lock();
41c445ff
JB		 5731 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5732 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5733 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5734 }
5735 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5736 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5737 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5738 }
5739 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5740 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5741 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5742 }
5743 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5744 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5745 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5746 }
b5d06f05
NP		 5747 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5748 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5749 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5750 }
41c445ff
JB		 5751
5752 /* If there's a recovery already waiting, it takes
5753 * precedence before starting a new reset sequence.
5754 */
5755 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5756 i40e_handle_reset_warning(pf);
23326186 5757 goto unlock;
41c445ff
JB		 5758 }
5759
5760 /* If we're already down or resetting, just bail */
5761 if (reset_flags &&
5762 !test_bit(__I40E_DOWN, &pf->state) &&
5763 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5764 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5765
5766unlock:
5767 rtnl_unlock();
41c445ff
JB		 5768}
5769
5770/**
5771 * i40e_handle_link_event - Handle link event
5772 * @pf: board private structure
5773 * @e: event info posted on ARQ
5774 **/
5775static void i40e_handle_link_event(struct i40e_pf *pf,
5776 struct i40e_arq_event_info *e)
5777{
5778 struct i40e_hw *hw = &pf->hw;
5779 struct i40e_aqc_get_link_status *status =
5780 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5781 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5782
5783 /* save off old link status information */
5784 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5785 sizeof(pf->hw.phy.link_info_old));
5786
1e701e09
JB		 5787 /* Do a new status request to re-enable LSE reporting
5788 * and load new status information into the hw struct
5789 * This completely ignores any state information
5790 * in the ARQ event info, instead choosing to always
5791 * issue the AQ update link status command.
5792 */
5793 i40e_link_event(pf);
5794
7b592f61
CW		 5795 /* check for unqualified module, if link is down */
5796 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5797 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5798 (!(status->link_info & I40E_AQ_LINK_UP)))
5799 dev_err(&pf->pdev->dev,
5800 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5801}
5802
5803/**
5804 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5805 * @pf: board private structure
5806 **/
5807static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5808{
5809 struct i40e_arq_event_info event;
5810 struct i40e_hw *hw = &pf->hw;
5811 u16 pending, i = 0;
5812 i40e_status ret;
5813 u16 opcode;
86df242b 5814 u32 oldval;
41c445ff
JB		 5815 u32 val;
5816
a316f651
ASJ		 5817 /* Do not run clean AQ when PF reset fails */
5818 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5819 return;
5820
86df242b
SN		 5821 /* check for error indications */
5822 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5823 oldval = val;
5824 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5825 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5826 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5827 }
5828 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5829 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5830 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5831 }
5832 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5833 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5834 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5835 }
5836 if (oldval != val)
5837 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5838
5839 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5840 oldval = val;
5841 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5842 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5843 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5844 }
5845 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5846 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5847 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5848 }
5849 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5850 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5851 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5852 }
5853 if (oldval != val)
5854 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5855
1001dc37
MW		 5856 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5857 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5858 if (!event.msg_buf)
5859 return;
5860
5861 do {
5862 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5863 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5864 break;
56497978 5865 else if (ret) {
41c445ff
JB		 5866 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5867 break;
5868 }
5869
5870 opcode = le16_to_cpu(event.desc.opcode);
5871 switch (opcode) {
5872
5873 case i40e_aqc_opc_get_link_status:
5874 i40e_handle_link_event(pf, &event);
5875 break;
5876 case i40e_aqc_opc_send_msg_to_pf:
5877 ret = i40e_vc_process_vf_msg(pf,
5878 le16_to_cpu(event.desc.retval),
5879 le32_to_cpu(event.desc.cookie_high),
5880 le32_to_cpu(event.desc.cookie_low),
5881 event.msg_buf,
1001dc37 5882 event.msg_len);
41c445ff
JB		 5883 break;
5884 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5885 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5886#ifdef CONFIG_I40E_DCB
5887 rtnl_lock();
5888 ret = i40e_handle_lldp_event(pf, &event);
5889 rtnl_unlock();
5890#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5891 break;
5892 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5893 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5894 i40e_handle_lan_overflow_event(pf, &event);
5895 break;
0467bc91
SN		 5896 case i40e_aqc_opc_send_msg_to_peer:
5897 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5898 break;
91a0f930
SN		 5899 case i40e_aqc_opc_nvm_erase:
5900 case i40e_aqc_opc_nvm_update:
5901 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
5902 break;
41c445ff
JB		 5903 default:
5904 dev_info(&pf->pdev->dev,
0467bc91
SN		 5905 "ARQ Error: Unknown event 0x%04x received\n",
5906 opcode);
41c445ff
JB		 5907 break;
5908 }
5909 } while (pending && (i++ < pf->adminq_work_limit));
5910
5911 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5912 /* re-enable Admin queue interrupt cause */
5913 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5914 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5915 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5916 i40e_flush(hw);
5917
5918 kfree(event.msg_buf);
5919}
5920
4eb3f768
SN		 5921/**
5922 * i40e_verify_eeprom - make sure eeprom is good to use
5923 * @pf: board private structure
5924 **/
5925static void i40e_verify_eeprom(struct i40e_pf *pf)
5926{
5927 int err;
5928
5929 err = i40e_diag_eeprom_test(&pf->hw);
5930 if (err) {
5931 /* retry in case of garbage read */
5932 err = i40e_diag_eeprom_test(&pf->hw);
5933 if (err) {
5934 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5935 err);
5936 set_bit(__I40E_BAD_EEPROM, &pf->state);
5937 }
5938 }
5939
5940 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5941 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5942 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5943 }
5944}
5945
386a0afa
AA		 5946/**
5947 * i40e_enable_pf_switch_lb
b40c82e6 5948 * @pf: pointer to the PF structure
386a0afa
AA		 5949 *
5950 * enable switch loop back or die - no point in a return value
5951 **/
5952static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
5953{
5954 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
5955 struct i40e_vsi_context ctxt;
5956 int aq_ret;
5957
5958 ctxt.seid = pf->main_vsi_seid;
5959 ctxt.pf_num = pf->hw.pf_id;
5960 ctxt.vf_num = 0;
5961 aq_ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
5962 if (aq_ret) {
5963 dev_info(&pf->pdev->dev,
b40c82e6 5964 "%s couldn't get PF vsi config, err %d, aq_err %d\n",
386a0afa
AA		 5965 __func__, aq_ret, pf->hw.aq.asq_last_status);
5966 return;
5967 }
5968 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5969 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5970 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5971
5972 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
5973 if (aq_ret) {
5974 dev_info(&pf->pdev->dev,
5975 "%s: update vsi switch failed, aq_err=%d\n",
5976 __func__, vsi->back->hw.aq.asq_last_status);
5977 }
5978}
5979
5980/**
5981 * i40e_disable_pf_switch_lb
b40c82e6 5982 * @pf: pointer to the PF structure
386a0afa
AA		 5983 *
5984 * disable switch loop back or die - no point in a return value
5985 **/
5986static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
5987{
5988 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
5989 struct i40e_vsi_context ctxt;
5990 int aq_ret;
5991
5992 ctxt.seid = pf->main_vsi_seid;
5993 ctxt.pf_num = pf->hw.pf_id;
5994 ctxt.vf_num = 0;
5995 aq_ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
5996 if (aq_ret) {
5997 dev_info(&pf->pdev->dev,
b40c82e6 5998 "%s couldn't get PF vsi config, err %d, aq_err %d\n",
386a0afa
AA		 5999 __func__, aq_ret, pf->hw.aq.asq_last_status);
6000 return;
6001 }
6002 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6003 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6004 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6005
6006 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6007 if (aq_ret) {
6008 dev_info(&pf->pdev->dev,
6009 "%s: update vsi switch failed, aq_err=%d\n",
6010 __func__, vsi->back->hw.aq.asq_last_status);
6011 }
6012}
6013
51616018
NP		 6014/**
6015 * i40e_config_bridge_mode - Configure the HW bridge mode
6016 * @veb: pointer to the bridge instance
6017 *
6018 * Configure the loop back mode for the LAN VSI that is downlink to the
6019 * specified HW bridge instance. It is expected this function is called
6020 * when a new HW bridge is instantiated.
6021 **/
6022static void i40e_config_bridge_mode(struct i40e_veb *veb)
6023{
6024 struct i40e_pf *pf = veb->pf;
6025
6026 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6027 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
6028 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6029 i40e_disable_pf_switch_lb(pf);
6030 else
6031 i40e_enable_pf_switch_lb(pf);
6032}
6033
41c445ff
JB		 6034/**
6035 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6036 * @veb: pointer to the VEB instance
6037 *
6038 * This is a recursive function that first builds the attached VSIs then
6039 * recurses in to build the next layer of VEB. We track the connections
6040 * through our own index numbers because the seid's from the HW could
6041 * change across the reset.
6042 **/
6043static int i40e_reconstitute_veb(struct i40e_veb *veb)
6044{
6045 struct i40e_vsi *ctl_vsi = NULL;
6046 struct i40e_pf *pf = veb->pf;
6047 int v, veb_idx;
6048 int ret;
6049
6050 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6051 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6052 if (pf->vsi[v] &&
6053 pf->vsi[v]->veb_idx == veb->idx &&
6054 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6055 ctl_vsi = pf->vsi[v];
6056 break;
6057 }
6058 }
6059 if (!ctl_vsi) {
6060 dev_info(&pf->pdev->dev,
6061 "missing owner VSI for veb_idx %d\n", veb->idx);
6062 ret = -ENOENT;
6063 goto end_reconstitute;
6064 }
6065 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6066 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6067 ret = i40e_add_vsi(ctl_vsi);
6068 if (ret) {
6069 dev_info(&pf->pdev->dev,
6070 "rebuild of owner VSI failed: %d\n", ret);
6071 goto end_reconstitute;
6072 }
6073 i40e_vsi_reset_stats(ctl_vsi);
6074
6075 /* create the VEB in the switch and move the VSI onto the VEB */
6076 ret = i40e_add_veb(veb, ctl_vsi);
6077 if (ret)
6078 goto end_reconstitute;
6079
51616018 6080 i40e_config_bridge_mode(veb);
b64ba084 6081
41c445ff 6082 /* create the remaining VSIs attached to this VEB */
505682cd 6083 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6084 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6085 continue;
6086
6087 if (pf->vsi[v]->veb_idx == veb->idx) {
6088 struct i40e_vsi *vsi = pf->vsi[v];
6089 vsi->uplink_seid = veb->seid;
6090 ret = i40e_add_vsi(vsi);
6091 if (ret) {
6092 dev_info(&pf->pdev->dev,
6093 "rebuild of vsi_idx %d failed: %d\n",
6094 v, ret);
6095 goto end_reconstitute;
6096 }
6097 i40e_vsi_reset_stats(vsi);
6098 }
6099 }
6100
6101 /* create any VEBs attached to this VEB - RECURSION */
6102 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6103 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6104 pf->veb[veb_idx]->uplink_seid = veb->seid;
6105 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6106 if (ret)
6107 break;
6108 }
6109 }
6110
6111end_reconstitute:
6112 return ret;
6113}
6114
6115/**
6116 * i40e_get_capabilities - get info about the HW
6117 * @pf: the PF struct
6118 **/
6119static int i40e_get_capabilities(struct i40e_pf *pf)
6120{
6121 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6122 u16 data_size;
6123 int buf_len;
6124 int err;
6125
6126 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6127 do {
6128 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6129 if (!cap_buf)
6130 return -ENOMEM;
6131
6132 /* this loads the data into the hw struct for us */
6133 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6134 &data_size,
6135 i40e_aqc_opc_list_func_capabilities,
6136 NULL);
6137 /* data loaded, buffer no longer needed */
6138 kfree(cap_buf);
6139
6140 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6141 /* retry with a larger buffer */
6142 buf_len = data_size;
6143 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6144 dev_info(&pf->pdev->dev,
6145 "capability discovery failed: aq=%d\n",
6146 pf->hw.aq.asq_last_status);
6147 return -ENODEV;
6148 }
6149 } while (err);
6150
ac71b7ba
ASJ		 6151 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
6152 (pf->hw.aq.fw_maj_ver < 2)) {
6153 pf->hw.func_caps.num_msix_vectors++;
6154 pf->hw.func_caps.num_msix_vectors_vf++;
6155 }
6156
41c445ff
JB		 6157 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6158 dev_info(&pf->pdev->dev,
6159 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6160 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6161 pf->hw.func_caps.num_msix_vectors,
6162 pf->hw.func_caps.num_msix_vectors_vf,
6163 pf->hw.func_caps.fd_filters_guaranteed,
6164 pf->hw.func_caps.fd_filters_best_effort,
6165 pf->hw.func_caps.num_tx_qp,
6166 pf->hw.func_caps.num_vsis);
6167
7134f9ce
JB		 6168#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6169 + pf->hw.func_caps.num_vfs)
6170 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6171 dev_info(&pf->pdev->dev,
6172 "got num_vsis %d, setting num_vsis to %d\n",
6173 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6174 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6175 }
6176
41c445ff
JB		 6177 return 0;
6178}
6179
cbf61325
ASJ		 6180static int i40e_vsi_clear(struct i40e_vsi *vsi);
6181
41c445ff 6182/**
cbf61325 6183 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6184 * @pf: board private structure
6185 **/
cbf61325 6186static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6187{
6188 struct i40e_vsi *vsi;
8a9eb7d3 6189 int i;
41c445ff 6190
407e063c
JB		 6191 /* quick workaround for an NVM issue that leaves a critical register
6192 * uninitialized
6193 */
6194 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6195 static const u32 hkey[] = {
6196 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6197 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6198 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6199 0x95b3a76d};
6200
6201 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6202 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6203 }
6204
cbf61325 6205 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6206 return;
6207
cbf61325 6208 /* find existing VSI and see if it needs configuring */
41c445ff 6209 vsi = NULL;
505682cd 6210 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6211 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6212 vsi = pf->vsi[i];
cbf61325
ASJ		 6213 break;
6214 }
6215 }
6216
6217 /* create a new VSI if none exists */
41c445ff 6218 if (!vsi) {
cbf61325
ASJ		 6219 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6220 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6221 if (!vsi) {
6222 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6223 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6224 return;
41c445ff 6225 }
cbf61325 6226 }
41c445ff 6227
8a9eb7d3 6228 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6229}
6230
6231/**
6232 * i40e_fdir_teardown - release the Flow Director resources
6233 * @pf: board private structure
6234 **/
6235static void i40e_fdir_teardown(struct i40e_pf *pf)
6236{
6237 int i;
6238
17a73f6b 6239 i40e_fdir_filter_exit(pf);
505682cd 6240 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6241 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6242 i40e_vsi_release(pf->vsi[i]);
6243 break;
6244 }
6245 }
6246}
6247
6248/**
f650a38b 6249 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6250 * @pf: board private structure
6251 *
b40c82e6 6252 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6253 **/
23cfbe07 6254static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6255{
41c445ff 6256 struct i40e_hw *hw = &pf->hw;
60442dea 6257 i40e_status ret = 0;
41c445ff
JB		 6258 u32 v;
6259
6260 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6261 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6262 return;
41c445ff 6263
69bfb110 6264 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6265
41c445ff
JB		 6266 /* quiesce the VSIs and their queues that are not already DOWN */
6267 i40e_pf_quiesce_all_vsi(pf);
6268
505682cd 6269 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6270 if (pf->vsi[v])
6271 pf->vsi[v]->seid = 0;
6272 }
6273
6274 i40e_shutdown_adminq(&pf->hw);
6275
f650a38b 6276 /* call shutdown HMC */
60442dea
SN		 6277 if (hw->hmc.hmc_obj) {
6278 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6279 if (ret)
60442dea
SN		 6280 dev_warn(&pf->pdev->dev,
6281 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6282 }
f650a38b
ASJ		 6283}
6284
44033fac
JB		 6285/**
6286 * i40e_send_version - update firmware with driver version
6287 * @pf: PF struct
6288 */
6289static void i40e_send_version(struct i40e_pf *pf)
6290{
6291 struct i40e_driver_version dv;
6292
6293 dv.major_version = DRV_VERSION_MAJOR;
6294 dv.minor_version = DRV_VERSION_MINOR;
6295 dv.build_version = DRV_VERSION_BUILD;
6296 dv.subbuild_version = 0;
35a7d804 6297 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6298 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6299}
6300
f650a38b 6301/**
4dda12e6 6302 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6303 * @pf: board private structure
bc7d338f 6304 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6305 **/
bc7d338f 6306static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6307{
f650a38b 6308 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6309 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6310 i40e_status ret;
6311 u32 v;
6312
41c445ff
JB		 6313 /* Now we wait for GRST to settle out.
6314 * We don't have to delete the VEBs or VSIs from the hw switch
6315 * because the reset will make them disappear.
6316 */
6317 ret = i40e_pf_reset(hw);
b5565400 6318 if (ret) {
41c445ff 6319 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6320 set_bit(__I40E_RESET_FAILED, &pf->state);
6321 goto clear_recovery;
b5565400 6322 }
41c445ff
JB		 6323 pf->pfr_count++;
6324
6325 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6326 goto clear_recovery;
69bfb110 6327 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6328
6329 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6330 ret = i40e_init_adminq(&pf->hw);
6331 if (ret) {
6332 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6333 goto clear_recovery;
41c445ff
JB		 6334 }
6335
4eb3f768 6336 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6337 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6338 i40e_verify_eeprom(pf);
4eb3f768 6339
e78ac4bf 6340 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6341 ret = i40e_get_capabilities(pf);
6342 if (ret) {
6343 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6344 ret);
6345 goto end_core_reset;
6346 }
6347
41c445ff
JB		 6348 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6349 hw->func_caps.num_rx_qp,
6350 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6351 if (ret) {
6352 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6353 goto end_core_reset;
6354 }
6355 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6356 if (ret) {
6357 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6358 goto end_core_reset;
6359 }
6360
4e3b35b0
NP		 6361#ifdef CONFIG_I40E_DCB
6362 ret = i40e_init_pf_dcb(pf);
6363 if (ret) {
aebfc816
SN		 6364 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6365 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6366 /* Continue without DCB enabled */
4e3b35b0
NP		 6367 }
6368#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6369#ifdef I40E_FCOE
6370 ret = i40e_init_pf_fcoe(pf);
6371 if (ret)
6372 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6373
38e00438 6374#endif
41c445ff 6375 /* do basic switch setup */
bc7d338f 6376 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6377 if (ret)
6378 goto end_core_reset;
6379
7e2453fe
JB		 6380 /* driver is only interested in link up/down and module qualification
6381 * reports from firmware
6382 */
6383 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6384 I40E_AQ_EVENT_LINK_UPDOWN |
6385 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6386 if (ret)
6387 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6388
cafa2ee6
ASJ		 6389 /* make sure our flow control settings are restored */
6390 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6391 if (ret)
6392 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6393
41c445ff
JB		 6394 /* Rebuild the VSIs and VEBs that existed before reset.
6395 * They are still in our local switch element arrays, so only
6396 * need to rebuild the switch model in the HW.
6397 *
6398 * If there were VEBs but the reconstitution failed, we'll try
6399 * try to recover minimal use by getting the basic PF VSI working.
6400 */
6401 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6402 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6403 /* find the one VEB connected to the MAC, and find orphans */
6404 for (v = 0; v < I40E_MAX_VEB; v++) {
6405 if (!pf->veb[v])
6406 continue;
6407
6408 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6409 pf->veb[v]->uplink_seid == 0) {
6410 ret = i40e_reconstitute_veb(pf->veb[v]);
6411
6412 if (!ret)
6413 continue;
6414
6415 /* If Main VEB failed, we're in deep doodoo,
6416 * so give up rebuilding the switch and set up
6417 * for minimal rebuild of PF VSI.
6418 * If orphan failed, we'll report the error
6419 * but try to keep going.
6420 */
6421 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6422 dev_info(&pf->pdev->dev,
6423 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6424 ret);
6425 pf->vsi[pf->lan_vsi]->uplink_seid
6426 = pf->mac_seid;
6427 break;
6428 } else if (pf->veb[v]->uplink_seid == 0) {
6429 dev_info(&pf->pdev->dev,
6430 "rebuild of orphan VEB failed: %d\n",
6431 ret);
6432 }
6433 }
6434 }
6435 }
6436
6437 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6438 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6439 /* no VEB, so rebuild only the Main VSI */
6440 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6441 if (ret) {
6442 dev_info(&pf->pdev->dev,
6443 "rebuild of Main VSI failed: %d\n", ret);
6444 goto end_core_reset;
6445 }
6446 }
6447
025b4a54
ASJ		 6448 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6449 (pf->hw.aq.fw_maj_ver < 4)) {
6450 msleep(75);
6451 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6452 if (ret)
6453 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6454 pf->hw.aq.asq_last_status);
cafa2ee6 6455 }
41c445ff
JB		 6456 /* reinit the misc interrupt */
6457 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6458 ret = i40e_setup_misc_vector(pf);
6459
6460 /* restart the VSIs that were rebuilt and running before the reset */
6461 i40e_pf_unquiesce_all_vsi(pf);
6462
69f64b2b
MW		 6463 if (pf->num_alloc_vfs) {
6464 for (v = 0; v < pf->num_alloc_vfs; v++)
6465 i40e_reset_vf(&pf->vf[v], true);
6466 }
6467
41c445ff 6468 /* tell the firmware that we're starting */
44033fac 6469 i40e_send_version(pf);
41c445ff
JB		 6470
6471end_core_reset:
a316f651
ASJ		 6472 clear_bit(__I40E_RESET_FAILED, &pf->state);
6473clear_recovery:
41c445ff
JB		 6474 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6475}
6476
f650a38b 6477/**
b40c82e6 6478 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6479 * @pf: board private structure
6480 *
6481 * Close up the VFs and other things in prep for a Core Reset,
6482 * then get ready to rebuild the world.
6483 **/
6484static void i40e_handle_reset_warning(struct i40e_pf *pf)
6485{
23cfbe07
SN		 6486 i40e_prep_for_reset(pf);
6487 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6488}
6489
41c445ff
JB		 6490/**
6491 * i40e_handle_mdd_event
b40c82e6 6492 * @pf: pointer to the PF structure
41c445ff
JB		 6493 *
6494 * Called from the MDD irq handler to identify possibly malicious vfs
6495 **/
6496static void i40e_handle_mdd_event(struct i40e_pf *pf)
6497{
6498 struct i40e_hw *hw = &pf->hw;
6499 bool mdd_detected = false;
df430b12 6500 bool pf_mdd_detected = false;
41c445ff
JB		 6501 struct i40e_vf *vf;
6502 u32 reg;
6503 int i;
6504
6505 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6506 return;
6507
6508 /* find what triggered the MDD event */
6509 reg = rd32(hw, I40E_GL_MDET_TX);
6510 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6511 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6512 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6513 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6514 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6515 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6516 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6517 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6518 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6519 pf->hw.func_caps.base_queue;
faf32978 6520 if (netif_msg_tx_err(pf))
b40c82e6 6521 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6522 event, queue, pf_num, vf_num);
41c445ff
JB		 6523 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6524 mdd_detected = true;
6525 }
6526 reg = rd32(hw, I40E_GL_MDET_RX);
6527 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6528 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6529 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6530 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6531 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6532 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6533 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6534 pf->hw.func_caps.base_queue;
faf32978
JB		 6535 if (netif_msg_rx_err(pf))
6536 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6537 event, queue, func);
41c445ff
JB		 6538 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6539 mdd_detected = true;
6540 }
6541
df430b12
NP		 6542 if (mdd_detected) {
6543 reg = rd32(hw, I40E_PF_MDET_TX);
6544 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6545 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6546 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6547 pf_mdd_detected = true;
6548 }
6549 reg = rd32(hw, I40E_PF_MDET_RX);
6550 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6551 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6552 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6553 pf_mdd_detected = true;
6554 }
6555 /* Queue belongs to the PF, initiate a reset */
6556 if (pf_mdd_detected) {
6557 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6558 i40e_service_event_schedule(pf);
6559 }
6560 }
6561
41c445ff
JB		 6562 /* see if one of the VFs needs its hand slapped */
6563 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6564 vf = &(pf->vf[i]);
6565 reg = rd32(hw, I40E_VP_MDET_TX(i));
6566 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6567 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6568 vf->num_mdd_events++;
faf32978
JB		 6569 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6570 i);
41c445ff
JB		 6571 }
6572
6573 reg = rd32(hw, I40E_VP_MDET_RX(i));
6574 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6575 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6576 vf->num_mdd_events++;
faf32978
JB		 6577 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6578 i);
41c445ff
JB		 6579 }
6580
6581 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6582 dev_info(&pf->pdev->dev,
6583 "Too many MDD events on VF %d, disabled\n", i);
6584 dev_info(&pf->pdev->dev,
6585 "Use PF Control I/F to re-enable the VF\n");
6586 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6587 }
6588 }
6589
6590 /* re-enable mdd interrupt cause */
6591 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6592 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6593 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6594 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6595 i40e_flush(hw);
6596}
6597
a1c9a9d9
JK		 6598#ifdef CONFIG_I40E_VXLAN
6599/**
6600 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6601 * @pf: board private structure
6602 **/
6603static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6604{
a1c9a9d9
JK		 6605 struct i40e_hw *hw = &pf->hw;
6606 i40e_status ret;
6607 u8 filter_index;
6608 __be16 port;
6609 int i;
6610
6611 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6612 return;
6613
6614 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6615
6616 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6617 if (pf->pending_vxlan_bitmap & (1 << i)) {
6618 pf->pending_vxlan_bitmap &= ~(1 << i);
6619 port = pf->vxlan_ports[i];
6620 ret = port ?
6621 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6622 I40E_AQC_TUNNEL_TYPE_VXLAN,
6623 &filter_index, NULL)
6624 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6625
6626 if (ret) {
6627 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6628 port ? "adding" : "deleting",
6629 ntohs(port), port ? i : i);
6630
6631 pf->vxlan_ports[i] = 0;
6632 } else {
6633 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6634 port ? "Added" : "Deleted",
6635 ntohs(port), port ? i : filter_index);
6636 }
6637 }
6638 }
6639}
6640
6641#endif
41c445ff
JB		 6642/**
6643 * i40e_service_task - Run the driver's async subtasks
6644 * @work: pointer to work_struct containing our data
6645 **/
6646static void i40e_service_task(struct work_struct *work)
6647{
6648 struct i40e_pf *pf = container_of(work,
6649 struct i40e_pf,
6650 service_task);
6651 unsigned long start_time = jiffies;
6652
e57a2fea
SN		 6653 /* don't bother with service tasks if a reset is in progress */
6654 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6655 i40e_service_event_complete(pf);
6656 return;
6657 }
6658
41c445ff
JB		 6659 i40e_reset_subtask(pf);
6660 i40e_handle_mdd_event(pf);
6661 i40e_vc_process_vflr_event(pf);
6662 i40e_watchdog_subtask(pf);
6663 i40e_fdir_reinit_subtask(pf);
41c445ff 6664 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6665#ifdef CONFIG_I40E_VXLAN
6666 i40e_sync_vxlan_filters_subtask(pf);
6667#endif
41c445ff
JB		 6668 i40e_clean_adminq_subtask(pf);
6669
6670 i40e_service_event_complete(pf);
6671
6672 /* If the tasks have taken longer than one timer cycle or there
6673 * is more work to be done, reschedule the service task now
6674 * rather than wait for the timer to tick again.
6675 */
6676 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6677 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6678 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6679 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6680 i40e_service_event_schedule(pf);
6681}
6682
6683/**
6684 * i40e_service_timer - timer callback
6685 * @data: pointer to PF struct
6686 **/
6687static void i40e_service_timer(unsigned long data)
6688{
6689 struct i40e_pf *pf = (struct i40e_pf *)data;
6690
6691 mod_timer(&pf->service_timer,
6692 round_jiffies(jiffies + pf->service_timer_period));
6693 i40e_service_event_schedule(pf);
6694}
6695
6696/**
6697 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6698 * @vsi: the VSI being configured
6699 **/
6700static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6701{
6702 struct i40e_pf *pf = vsi->back;
6703
6704 switch (vsi->type) {
6705 case I40E_VSI_MAIN:
6706 vsi->alloc_queue_pairs = pf->num_lan_qps;
6707 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6708 I40E_REQ_DESCRIPTOR_MULTIPLE);
6709 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6710 vsi->num_q_vectors = pf->num_lan_msix;
6711 else
6712 vsi->num_q_vectors = 1;
6713
6714 break;
6715
6716 case I40E_VSI_FDIR:
6717 vsi->alloc_queue_pairs = 1;
6718 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6719 I40E_REQ_DESCRIPTOR_MULTIPLE);
6720 vsi->num_q_vectors = 1;
6721 break;
6722
6723 case I40E_VSI_VMDQ2:
6724 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6725 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6726 I40E_REQ_DESCRIPTOR_MULTIPLE);
6727 vsi->num_q_vectors = pf->num_vmdq_msix;
6728 break;
6729
6730 case I40E_VSI_SRIOV:
6731 vsi->alloc_queue_pairs = pf->num_vf_qps;
6732 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6733 I40E_REQ_DESCRIPTOR_MULTIPLE);
6734 break;
6735
38e00438
VD		 6736#ifdef I40E_FCOE
6737 case I40E_VSI_FCOE:
6738 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6739 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6740 I40E_REQ_DESCRIPTOR_MULTIPLE);
6741 vsi->num_q_vectors = pf->num_fcoe_msix;
6742 break;
6743
6744#endif /* I40E_FCOE */
41c445ff
JB		 6745 default:
6746 WARN_ON(1);
6747 return -ENODATA;
6748 }
6749
6750 return 0;
6751}
6752
f650a38b
ASJ		 6753/**
6754 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6755 * @type: VSI pointer
bc7d338f 6756 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6757 *
6758 * On error: returns error code (negative)
6759 * On success: returns 0
6760 **/
bc7d338f 6761static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6762{
6763 int size;
6764 int ret = 0;
6765
ac6c5e3d 6766 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6767 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6768 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6769 if (!vsi->tx_rings)
6770 return -ENOMEM;
f650a38b
ASJ		 6771 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6772
bc7d338f
ASJ		 6773 if (alloc_qvectors) {
6774 /* allocate memory for q_vector pointers */
f57e4fbd 6775 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6776 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6777 if (!vsi->q_vectors) {
6778 ret = -ENOMEM;
6779 goto err_vectors;
6780 }
f650a38b
ASJ		 6781 }
6782 return ret;
6783
6784err_vectors:
6785 kfree(vsi->tx_rings);
6786 return ret;
6787}
6788
41c445ff
JB		 6789/**
6790 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6791 * @pf: board private structure
6792 * @type: type of VSI
6793 *
6794 * On error: returns error code (negative)
6795 * On success: returns vsi index in PF (positive)
6796 **/
6797static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6798{
6799 int ret = -ENODEV;
6800 struct i40e_vsi *vsi;
6801 int vsi_idx;
6802 int i;
6803
6804 /* Need to protect the allocation of the VSIs at the PF level */
6805 mutex_lock(&pf->switch_mutex);
6806
6807 /* VSI list may be fragmented if VSI creation/destruction has
6808 * been happening. We can afford to do a quick scan to look
6809 * for any free VSIs in the list.
6810 *
6811 * find next empty vsi slot, looping back around if necessary
6812 */
6813 i = pf->next_vsi;
505682cd 6814 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6815 i++;
505682cd 6816 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6817 i = 0;
6818 while (i < pf->next_vsi && pf->vsi[i])
6819 i++;
6820 }
6821
505682cd 6822 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6823 vsi_idx = i; /* Found one! */
6824 } else {
6825 ret = -ENODEV;
493fb300 6826 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6827 }
6828 pf->next_vsi = ++i;
6829
6830 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6831 if (!vsi) {
6832 ret = -ENOMEM;
493fb300 6833 goto unlock_pf;
41c445ff
JB		 6834 }
6835 vsi->type = type;
6836 vsi->back = pf;
6837 set_bit(__I40E_DOWN, &vsi->state);
6838 vsi->flags = 0;
6839 vsi->idx = vsi_idx;
6840 vsi->rx_itr_setting = pf->rx_itr_default;
6841 vsi->tx_itr_setting = pf->tx_itr_default;
5db4cb59
ASJ		 6842 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
6843 pf->rss_table_size : 64;
41c445ff
JB		 6844 vsi->netdev_registered = false;
6845 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6846 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6847 vsi->irqs_ready = false;
41c445ff 6848
9f65e15b
AD		 6849 ret = i40e_set_num_rings_in_vsi(vsi);
6850 if (ret)
6851 goto err_rings;
6852
bc7d338f 6853 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6854 if (ret)
9f65e15b 6855 goto err_rings;
493fb300 6856
41c445ff
JB		 6857 /* Setup default MSIX irq handler for VSI */
6858 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6859
6860 pf->vsi[vsi_idx] = vsi;
6861 ret = vsi_idx;
493fb300
AD		 6862 goto unlock_pf;
6863
9f65e15b 6864err_rings:
493fb300
AD		 6865 pf->next_vsi = i - 1;
6866 kfree(vsi);
6867unlock_pf:
41c445ff
JB		 6868 mutex_unlock(&pf->switch_mutex);
6869 return ret;
6870}
6871
f650a38b
ASJ		 6872/**
6873 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6874 * @type: VSI pointer
bc7d338f 6875 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6876 *
6877 * On error: returns error code (negative)
6878 * On success: returns 0
6879 **/
bc7d338f 6880static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6881{
6882 /* free the ring and vector containers */
bc7d338f
ASJ		 6883 if (free_qvectors) {
6884 kfree(vsi->q_vectors);
6885 vsi->q_vectors = NULL;
6886 }
f650a38b
ASJ		 6887 kfree(vsi->tx_rings);
6888 vsi->tx_rings = NULL;
6889 vsi->rx_rings = NULL;
6890}
6891
41c445ff
JB		 6892/**
6893 * i40e_vsi_clear - Deallocate the VSI provided
6894 * @vsi: the VSI being un-configured
6895 **/
6896static int i40e_vsi_clear(struct i40e_vsi *vsi)
6897{
6898 struct i40e_pf *pf;
6899
6900 if (!vsi)
6901 return 0;
6902
6903 if (!vsi->back)
6904 goto free_vsi;
6905 pf = vsi->back;
6906
6907 mutex_lock(&pf->switch_mutex);
6908 if (!pf->vsi[vsi->idx]) {
6909 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6910 vsi->idx, vsi->idx, vsi, vsi->type);
6911 goto unlock_vsi;
6912 }
6913
6914 if (pf->vsi[vsi->idx] != vsi) {
6915 dev_err(&pf->pdev->dev,
6916 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6917 pf->vsi[vsi->idx]->idx,
6918 pf->vsi[vsi->idx],
6919 pf->vsi[vsi->idx]->type,
6920 vsi->idx, vsi, vsi->type);
6921 goto unlock_vsi;
6922 }
6923
b40c82e6 6924 /* updates the PF for this cleared vsi */
41c445ff
JB		 6925 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6926 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6927
bc7d338f 6928 i40e_vsi_free_arrays(vsi, true);
493fb300 6929
41c445ff
JB		 6930 pf->vsi[vsi->idx] = NULL;
6931 if (vsi->idx < pf->next_vsi)
6932 pf->next_vsi = vsi->idx;
6933
6934unlock_vsi:
6935 mutex_unlock(&pf->switch_mutex);
6936free_vsi:
6937 kfree(vsi);
6938
6939 return 0;
6940}
6941
9f65e15b
AD		 6942/**
6943 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6944 * @vsi: the VSI being cleaned
6945 **/
be1d5eea 6946static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6947{
6948 int i;
6949
8e9dca53 6950 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6951 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6952 kfree_rcu(vsi->tx_rings[i], rcu);
6953 vsi->tx_rings[i] = NULL;
6954 vsi->rx_rings[i] = NULL;
6955 }
be1d5eea 6956 }
9f65e15b
AD		 6957}
6958
41c445ff
JB		 6959/**
6960 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6961 * @vsi: the VSI being configured
6962 **/
6963static int i40e_alloc_rings(struct i40e_vsi *vsi)
6964{
e7046ee1 6965 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6966 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6967 int i;
6968
41c445ff 6969 /* Set basic values in the rings to be used later during open() */
d7397644 6970 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6971 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6972 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6973 if (!tx_ring)
6974 goto err_out;
41c445ff
JB		 6975
6976 tx_ring->queue_index = i;
6977 tx_ring->reg_idx = vsi->base_queue + i;
6978 tx_ring->ring_active = false;
6979 tx_ring->vsi = vsi;
6980 tx_ring->netdev = vsi->netdev;
6981 tx_ring->dev = &pf->pdev->dev;
6982 tx_ring->count = vsi->num_desc;
6983 tx_ring->size = 0;
6984 tx_ring->dcb_tc = 0;
9f65e15b 6985 vsi->tx_rings[i] = tx_ring;
41c445ff 6986
9f65e15b 6987 rx_ring = &tx_ring[1];
41c445ff
JB		 6988 rx_ring->queue_index = i;
6989 rx_ring->reg_idx = vsi->base_queue + i;
6990 rx_ring->ring_active = false;
6991 rx_ring->vsi = vsi;
6992 rx_ring->netdev = vsi->netdev;
6993 rx_ring->dev = &pf->pdev->dev;
6994 rx_ring->count = vsi->num_desc;
6995 rx_ring->size = 0;
6996 rx_ring->dcb_tc = 0;
6997 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6998 set_ring_16byte_desc_enabled(rx_ring);
6999 else
7000 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7001 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7002 }
7003
7004 return 0;
9f65e15b
AD		 7005
7006err_out:
7007 i40e_vsi_clear_rings(vsi);
7008 return -ENOMEM;
41c445ff
JB		 7009}
7010
7011/**
7012 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7013 * @pf: board private structure
7014 * @vectors: the number of MSI-X vectors to request
7015 *
7016 * Returns the number of vectors reserved, or error
7017 **/
7018static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7019{
7b37f376
AG		 7020 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7021 I40E_MIN_MSIX, vectors);
7022 if (vectors < 0) {
41c445ff 7023 dev_info(&pf->pdev->dev,
7b37f376 7024 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7025 vectors = 0;
7026 }
7027
7028 return vectors;
7029}
7030
7031/**
7032 * i40e_init_msix - Setup the MSIX capability
7033 * @pf: board private structure
7034 *
7035 * Work with the OS to set up the MSIX vectors needed.
7036 *
3b444399 7037 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7038 **/
7039static int i40e_init_msix(struct i40e_pf *pf)
7040{
41c445ff 7041 struct i40e_hw *hw = &pf->hw;
1e200e4a 7042 int vectors_left;
41c445ff 7043 int v_budget, i;
3b444399 7044 int v_actual;
41c445ff
JB		 7045
7046 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7047 return -ENODEV;
7048
7049 /* The number of vectors we'll request will be comprised of:
7050 * - Add 1 for "other" cause for Admin Queue events, etc.
7051 * - The number of LAN queue pairs
f8ff1464
ASJ		 7052 * - Queues being used for RSS.
7053 * We don't need as many as max_rss_size vectors.
7054 * use rss_size instead in the calculation since that
7055 * is governed by number of cpus in the system.
7056 * - assumes symmetric Tx/Rx pairing
41c445ff 7057 * - The number of VMDq pairs
38e00438
VD		 7058#ifdef I40E_FCOE
7059 * - The number of FCOE qps.
7060#endif
41c445ff
JB		 7061 * Once we count this up, try the request.
7062 *
7063 * If we can't get what we want, we'll simplify to nearly nothing
7064 * and try again. If that still fails, we punt.
7065 */
1e200e4a
SN		 7066 vectors_left = hw->func_caps.num_msix_vectors;
7067 v_budget = 0;
7068
7069 /* reserve one vector for miscellaneous handler */
7070 if (vectors_left) {
7071 v_budget++;
7072 vectors_left--;
7073 }
7074
7075 /* reserve vectors for the main PF traffic queues */
7076 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7077 vectors_left -= pf->num_lan_msix;
7078 v_budget += pf->num_lan_msix;
7079
7080 /* reserve one vector for sideband flow director */
7081 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7082 if (vectors_left) {
7083 v_budget++;
7084 vectors_left--;
7085 } else {
7086 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7087 }
7088 }
83840e4b 7089
38e00438 7090#ifdef I40E_FCOE
1e200e4a 7091 /* can we reserve enough for FCoE? */
38e00438 7092 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7093 if (!vectors_left)
7094 pf->num_fcoe_msix = 0;
7095 else if (vectors_left >= pf->num_fcoe_qps)
7096 pf->num_fcoe_msix = pf->num_fcoe_qps;
7097 else
7098 pf->num_fcoe_msix = 1;
38e00438 7099 v_budget += pf->num_fcoe_msix;
1e200e4a 7100 vectors_left -= pf->num_fcoe_msix;
38e00438 7101 }
1e200e4a 7102
38e00438 7103#endif
1e200e4a
SN		 7104 /* any vectors left over go for VMDq support */
7105 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7106 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7107 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7108
7109 /* if we're short on vectors for what's desired, we limit
7110 * the queues per vmdq. If this is still more than are
7111 * available, the user will need to change the number of
7112 * queues/vectors used by the PF later with the ethtool
7113 * channels command
7114 */
7115 if (vmdq_vecs < vmdq_vecs_wanted)
7116 pf->num_vmdq_qps = 1;
7117 pf->num_vmdq_msix = pf->num_vmdq_qps;
7118
7119 v_budget += vmdq_vecs;
7120 vectors_left -= vmdq_vecs;
7121 }
41c445ff
JB		 7122
7123 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7124 GFP_KERNEL);
7125 if (!pf->msix_entries)
7126 return -ENOMEM;
7127
7128 for (i = 0; i < v_budget; i++)
7129 pf->msix_entries[i].entry = i;
3b444399 7130 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7131
3b444399 7132 if (v_actual != v_budget) {
a34977ba
ASJ		 7133 /* If we have limited resources, we will start with no vectors
7134 * for the special features and then allocate vectors to some
7135 * of these features based on the policy and at the end disable
7136 * the features that did not get any vectors.
7137 */
38e00438
VD		 7138#ifdef I40E_FCOE
7139 pf->num_fcoe_qps = 0;
7140 pf->num_fcoe_msix = 0;
7141#endif
a34977ba
ASJ		 7142 pf->num_vmdq_msix = 0;
7143 }
7144
3b444399 7145 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7146 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7147 kfree(pf->msix_entries);
7148 pf->msix_entries = NULL;
7149 return -ENODEV;
7150
3b444399 7151 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7152 /* Adjust for minimal MSIX use */
41c445ff
JB		 7153 pf->num_vmdq_vsis = 0;
7154 pf->num_vmdq_qps = 0;
41c445ff
JB		 7155 pf->num_lan_qps = 1;
7156 pf->num_lan_msix = 1;
7157
3b444399
SN		 7158 } else if (v_actual != v_budget) {
7159 int vec;
7160
a34977ba 7161 /* reserve the misc vector */
3b444399 7162 vec = v_actual - 1;
a34977ba 7163
41c445ff
JB		 7164 /* Scale vector usage down */
7165 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7166 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7167 pf->num_vmdq_qps = 1;
7168 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7169
7170 /* partition out the remaining vectors */
7171 switch (vec) {
7172 case 2:
41c445ff
JB		 7173 pf->num_lan_msix = 1;
7174 break;
7175 case 3:
38e00438
VD		 7176#ifdef I40E_FCOE
7177 /* give one vector to FCoE */
7178 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7179 pf->num_lan_msix = 1;
7180 pf->num_fcoe_msix = 1;
7181 }
7182#else
41c445ff 7183 pf->num_lan_msix = 2;
38e00438 7184#endif
41c445ff
JB		 7185 break;
7186 default:
38e00438
VD		 7187#ifdef I40E_FCOE
7188 /* give one vector to FCoE */
7189 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7190 pf->num_fcoe_msix = 1;
7191 vec--;
7192 }
7193#endif
1e200e4a
SN		 7194 /* give the rest to the PF */
7195 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7196 break;
7197 }
7198 }
7199
a34977ba
ASJ		 7200 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7201 (pf->num_vmdq_msix == 0)) {
7202 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7203 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7204 }
38e00438
VD		 7205#ifdef I40E_FCOE
7206
7207 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7208 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7209 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7210 }
7211#endif
3b444399 7212 return v_actual;
41c445ff
JB		 7213}
7214
493fb300 7215/**
90e04070 7216 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7217 * @vsi: the VSI being configured
7218 * @v_idx: index of the vector in the vsi struct
7219 *
7220 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7221 **/
90e04070 7222static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7223{
7224 struct i40e_q_vector *q_vector;
7225
7226 /* allocate q_vector */
7227 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7228 if (!q_vector)
7229 return -ENOMEM;
7230
7231 q_vector->vsi = vsi;
7232 q_vector->v_idx = v_idx;
7233 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7234 if (vsi->netdev)
7235 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7236 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7237
cd0b6fa6
AD		 7238 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7239 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7240
493fb300
AD		 7241 /* tie q_vector and vsi together */
7242 vsi->q_vectors[v_idx] = q_vector;
7243
7244 return 0;
7245}
7246
41c445ff 7247/**
90e04070 7248 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7249 * @vsi: the VSI being configured
7250 *
7251 * We allocate one q_vector per queue interrupt. If allocation fails we
7252 * return -ENOMEM.
7253 **/
90e04070 7254static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7255{
7256 struct i40e_pf *pf = vsi->back;
7257 int v_idx, num_q_vectors;
493fb300 7258 int err;
41c445ff
JB		 7259
7260 /* if not MSIX, give the one vector only to the LAN VSI */
7261 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7262 num_q_vectors = vsi->num_q_vectors;
7263 else if (vsi == pf->vsi[pf->lan_vsi])
7264 num_q_vectors = 1;
7265 else
7266 return -EINVAL;
7267
41c445ff 7268 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7269 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7270 if (err)
7271 goto err_out;
41c445ff
JB		 7272 }
7273
7274 return 0;
493fb300
AD		 7275
7276err_out:
7277 while (v_idx--)
7278 i40e_free_q_vector(vsi, v_idx);
7279
7280 return err;
41c445ff
JB		 7281}
7282
7283/**
7284 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7285 * @pf: board private structure to initialize
7286 **/
7287static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
7288{
3b444399
SN		 7289 int vectors = 0;
7290 ssize_t size;
41c445ff
JB		 7291
7292 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7293 vectors = i40e_init_msix(pf);
7294 if (vectors < 0) {
60ea5f83 7295 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7296#ifdef I40E_FCOE
7297 I40E_FLAG_FCOE_ENABLED |
7298#endif
60ea5f83 7299 I40E_FLAG_RSS_ENABLED |
4d9b6043 7300 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7301 I40E_FLAG_SRIOV_ENABLED |
7302 I40E_FLAG_FD_SB_ENABLED |
7303 I40E_FLAG_FD_ATR_ENABLED |
7304 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7305
7306 /* rework the queue expectations without MSIX */
7307 i40e_determine_queue_usage(pf);
7308 }
7309 }
7310
7311 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7312 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7313 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7314 vectors = pci_enable_msi(pf->pdev);
7315 if (vectors < 0) {
7316 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7317 vectors);
41c445ff
JB		 7318 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7319 }
3b444399 7320 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7321 }
7322
958a3e3b 7323 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7324 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7325
3b444399
SN		 7326 /* set up vector assignment tracking */
7327 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7328 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7329 pf->irq_pile->num_entries = vectors;
7330 pf->irq_pile->search_hint = 0;
7331
41c445ff 7332 /* track first vector for misc interrupts */
3b444399 7333 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
41c445ff
JB		 7334}
7335
7336/**
7337 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7338 * @pf: board private structure
7339 *
7340 * This sets up the handler for MSIX 0, which is used to manage the
7341 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7342 * when in MSI or Legacy interrupt mode.
7343 **/
7344static int i40e_setup_misc_vector(struct i40e_pf *pf)
7345{
7346 struct i40e_hw *hw = &pf->hw;
7347 int err = 0;
7348
7349 /* Only request the irq if this is the first time through, and
7350 * not when we're rebuilding after a Reset
7351 */
7352 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7353 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7354 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7355 if (err) {
7356 dev_info(&pf->pdev->dev,
77fa28be 7357 "request_irq for %s failed: %d\n",
b294ac70 7358 pf->int_name, err);
41c445ff
JB		 7359 return -EFAULT;
7360 }
7361 }
7362
ab437b5a 7363 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7364
7365 /* associate no queues to the misc vector */
7366 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7367 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7368
7369 i40e_flush(hw);
7370
7371 i40e_irq_dynamic_enable_icr0(pf);
7372
7373 return err;
7374}
7375
7376/**
7377 * i40e_config_rss - Prepare for RSS if used
7378 * @pf: board private structure
7379 **/
7380static int i40e_config_rss(struct i40e_pf *pf)
7381{
22f258a1 7382 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
66ddcffb 7383 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4617e8c0
ASJ		 7384 struct i40e_hw *hw = &pf->hw;
7385 u32 lut = 0;
7386 int i, j;
7387 u64 hena;
e157ea30 7388 u32 reg_val;
41c445ff 7389
22f258a1 7390 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7391 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7392 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7393
7394 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7395 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7396 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7397 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7398 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7399 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7400
66ddcffb
ASJ		 7401 vsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);
7402
e157ea30
CW		 7403 /* Check capability and Set table size and register per hw expectation*/
7404 reg_val = rd32(hw, I40E_PFQF_CTL_0);
d9e894ee 7405 if (pf->rss_table_size == 512)
e157ea30 7406 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
d9e894ee 7407 else
e157ea30 7408 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
e157ea30
CW		 7409 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7410
41c445ff 7411 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7412 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7413
7414 /* The assumption is that lan qp count will be the highest
7415 * qp count for any PF VSI that needs RSS.
7416 * If multiple VSIs need RSS support, all the qp counts
7417 * for those VSIs should be a power of 2 for RSS to work.
7418 * If LAN VSI is the only consumer for RSS then this requirement
7419 * is not necessary.
7420 */
66ddcffb 7421 if (j == vsi->rss_size)
41c445ff
JB		 7422 j = 0;
7423 /* lut = 4-byte sliding window of 4 lut entries */
7424 lut = (lut << 8) | (j &
7425 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7426 /* On i = 3, we have 4 entries in lut; write to the register */
7427 if ((i & 3) == 3)
7428 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7429 }
7430 i40e_flush(hw);
7431
7432 return 0;
7433}
7434
f8ff1464
ASJ		 7435/**
7436 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7437 * @pf: board private structure
7438 * @queue_count: the requested queue count for rss.
7439 *
7440 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7441 * count which may be different from the requested queue count.
7442 **/
7443int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7444{
9a3bd2f1
ASJ		 7445 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
7446 int new_rss_size;
7447
f8ff1464
ASJ		 7448 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7449 return 0;
7450
9a3bd2f1 7451 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 7452
9a3bd2f1
ASJ		 7453 if (queue_count != vsi->num_queue_pairs) {
7454 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 7455 i40e_prep_for_reset(pf);
7456
9a3bd2f1 7457 pf->rss_size = new_rss_size;
f8ff1464
ASJ		 7458
7459 i40e_reset_and_rebuild(pf, true);
7460 i40e_config_rss(pf);
7461 }
7462 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7463 return pf->rss_size;
7464}
7465
f4492db1
GR		 7466/**
7467 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
7468 * @pf: board private structure
7469 **/
7470i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
7471{
7472 i40e_status status;
7473 bool min_valid, max_valid;
7474 u32 max_bw, min_bw;
7475
7476 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
7477 &min_valid, &max_valid);
7478
7479 if (!status) {
7480 if (min_valid)
7481 pf->npar_min_bw = min_bw;
7482 if (max_valid)
7483 pf->npar_max_bw = max_bw;
7484 }
7485
7486 return status;
7487}
7488
7489/**
7490 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
7491 * @pf: board private structure
7492 **/
7493i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
7494{
7495 struct i40e_aqc_configure_partition_bw_data bw_data;
7496 i40e_status status;
7497
b40c82e6 7498 /* Set the valid bit for this PF */
f4492db1
GR		 7499 bw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);
7500 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
7501 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
7502
7503 /* Set the new bandwidths */
7504 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
7505
7506 return status;
7507}
7508
7509/**
7510 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
7511 * @pf: board private structure
7512 **/
7513i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
7514{
7515 /* Commit temporary BW setting to permanent NVM image */
7516 enum i40e_admin_queue_err last_aq_status;
7517 i40e_status ret;
7518 u16 nvm_word;
7519
7520 if (pf->hw.partition_id != 1) {
7521 dev_info(&pf->pdev->dev,
7522 "Commit BW only works on partition 1! This is partition %d",
7523 pf->hw.partition_id);
7524 ret = I40E_NOT_SUPPORTED;
7525 goto bw_commit_out;
7526 }
7527
7528 /* Acquire NVM for read access */
7529 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
7530 last_aq_status = pf->hw.aq.asq_last_status;
7531 if (ret) {
7532 dev_info(&pf->pdev->dev,
7533 "Cannot acquire NVM for read access, err %d: aq_err %d\n",
7534 ret, last_aq_status);
7535 goto bw_commit_out;
7536 }
7537
7538 /* Read word 0x10 of NVM - SW compatibility word 1 */
7539 ret = i40e_aq_read_nvm(&pf->hw,
7540 I40E_SR_NVM_CONTROL_WORD,
7541 0x10, sizeof(nvm_word), &nvm_word,
7542 false, NULL);
7543 /* Save off last admin queue command status before releasing
7544 * the NVM
7545 */
7546 last_aq_status = pf->hw.aq.asq_last_status;
7547 i40e_release_nvm(&pf->hw);
7548 if (ret) {
7549 dev_info(&pf->pdev->dev, "NVM read error, err %d aq_err %d\n",
7550 ret, last_aq_status);
7551 goto bw_commit_out;
7552 }
7553
7554 /* Wait a bit for NVM release to complete */
7555 msleep(50);
7556
7557 /* Acquire NVM for write access */
7558 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
7559 last_aq_status = pf->hw.aq.asq_last_status;
7560 if (ret) {
7561 dev_info(&pf->pdev->dev,
7562 "Cannot acquire NVM for write access, err %d: aq_err %d\n",
7563 ret, last_aq_status);
7564 goto bw_commit_out;
7565 }
7566 /* Write it back out unchanged to initiate update NVM,
7567 * which will force a write of the shadow (alt) RAM to
7568 * the NVM - thus storing the bandwidth values permanently.
7569 */
7570 ret = i40e_aq_update_nvm(&pf->hw,
7571 I40E_SR_NVM_CONTROL_WORD,
7572 0x10, sizeof(nvm_word),
7573 &nvm_word, true, NULL);
7574 /* Save off last admin queue command status before releasing
7575 * the NVM
7576 */
7577 last_aq_status = pf->hw.aq.asq_last_status;
7578 i40e_release_nvm(&pf->hw);
7579 if (ret)
7580 dev_info(&pf->pdev->dev,
7581 "BW settings NOT SAVED, err %d aq_err %d\n",
7582 ret, last_aq_status);
7583bw_commit_out:
7584
7585 return ret;
7586}
7587
41c445ff
JB		 7588/**
7589 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7590 * @pf: board private structure to initialize
7591 *
7592 * i40e_sw_init initializes the Adapter private data structure.
7593 * Fields are initialized based on PCI device information and
7594 * OS network device settings (MTU size).
7595 **/
7596static int i40e_sw_init(struct i40e_pf *pf)
7597{
7598 int err = 0;
7599 int size;
7600
7601 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7602 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7603 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7604 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7605 if (I40E_DEBUG_USER & debug)
7606 pf->hw.debug_mask = debug;
7607 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7608 I40E_DEFAULT_MSG_ENABLE);
7609 }
7610
7611 /* Set default capability flags */
7612 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7613 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 7614 I40E_FLAG_MSIX_ENABLED;
7615
7616 if (iommu_present(&pci_bus_type))
7617 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
7618 else
7619 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 7620
ca99eb99
MW		 7621 /* Set default ITR */
7622 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7623 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7624
7134f9ce
JB		 7625 /* Depending on PF configurations, it is possible that the RSS
7626 * maximum might end up larger than the available queues
7627 */
41c445ff 7628 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7629 pf->rss_size = 1;
5db4cb59 7630 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 7631 pf->rss_size_max = min_t(int, pf->rss_size_max,
7632 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7633 if (pf->hw.func_caps.rss) {
7634 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7635 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7636 }
7637
2050bc65
CS		 7638 /* MFP mode enabled */
7639 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7640 pf->flags |= I40E_FLAG_MFP_ENABLED;
7641 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 7642 if (i40e_get_npar_bw_setting(pf))
7643 dev_warn(&pf->pdev->dev,
7644 "Could not get NPAR bw settings\n");
7645 else
7646 dev_info(&pf->pdev->dev,
7647 "Min BW = %8.8x, Max BW = %8.8x\n",
7648 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 7649 }
7650
cbf61325
ASJ		 7651 /* FW/NVM is not yet fixed in this regard */
7652 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7653 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7654 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7655 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
b40c82e6 7656 /* Setup a counter for fd_atr per PF */
433c47de 7657 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7658 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7659 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
b40c82e6 7660 /* Setup a counter for fd_sb per PF */
433c47de 7661 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7662 } else {
7663 dev_info(&pf->pdev->dev,
0b67584f 7664 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7665 }
cbf61325
ASJ		 7666 pf->fdir_pf_filter_count =
7667 pf->hw.func_caps.fd_filters_guaranteed;
7668 pf->hw.fdir_shared_filter_count =
7669 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7670 }
7671
7672 if (pf->hw.func_caps.vmdq) {
7673 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7674 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7675 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7676 }
7677
38e00438
VD		 7678#ifdef I40E_FCOE
7679 err = i40e_init_pf_fcoe(pf);
7680 if (err)
7681 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7682
7683#endif /* I40E_FCOE */
41c445ff 7684#ifdef CONFIG_PCI_IOV
ba252f13 7685 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 7686 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7687 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7688 pf->num_req_vfs = min_t(int,
7689 pf->hw.func_caps.num_vfs,
7690 I40E_MAX_VF_COUNT);
7691 }
7692#endif /* CONFIG_PCI_IOV */
7693 pf->eeprom_version = 0xDEAD;
7694 pf->lan_veb = I40E_NO_VEB;
7695 pf->lan_vsi = I40E_NO_VSI;
7696
7697 /* set up queue assignment tracking */
7698 size = sizeof(struct i40e_lump_tracking)
7699 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7700 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7701 if (!pf->qp_pile) {
7702 err = -ENOMEM;
7703 goto sw_init_done;
7704 }
7705 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7706 pf->qp_pile->search_hint = 0;
7707
327fe04b
ASJ		 7708 pf->tx_timeout_recovery_level = 1;
7709
41c445ff
JB		 7710 mutex_init(&pf->switch_mutex);
7711
c668a12c
GR		 7712 /* If NPAR is enabled nudge the Tx scheduler */
7713 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
7714 i40e_set_npar_bw_setting(pf);
7715
41c445ff
JB		 7716sw_init_done:
7717 return err;
7718}
7719
7c3c288b
ASJ		 7720/**
7721 * i40e_set_ntuple - set the ntuple feature flag and take action
7722 * @pf: board private structure to initialize
7723 * @features: the feature set that the stack is suggesting
7724 *
7725 * returns a bool to indicate if reset needs to happen
7726 **/
7727bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7728{
7729 bool need_reset = false;
7730
7731 /* Check if Flow Director n-tuple support was enabled or disabled. If
7732 * the state changed, we need to reset.
7733 */
7734 if (features & NETIF_F_NTUPLE) {
7735 /* Enable filters and mark for reset */
7736 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7737 need_reset = true;
7738 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7739 } else {
7740 /* turn off filters, mark for reset and clear SW filter list */
7741 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7742 need_reset = true;
7743 i40e_fdir_filter_exit(pf);
7744 }
7745 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7746 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7747 /* reset fd counters */
7748 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7749 pf->fdir_pf_active_filters = 0;
7750 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7751 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7752 /* if ATR was auto disabled it can be re-enabled. */
7753 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7754 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7755 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7756 }
7757 return need_reset;
7758}
7759
41c445ff
JB		 7760/**
7761 * i40e_set_features - set the netdev feature flags
7762 * @netdev: ptr to the netdev being adjusted
7763 * @features: the feature set that the stack is suggesting
7764 **/
7765static int i40e_set_features(struct net_device *netdev,
7766 netdev_features_t features)
7767{
7768 struct i40e_netdev_priv *np = netdev_priv(netdev);
7769 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7770 struct i40e_pf *pf = vsi->back;
7771 bool need_reset;
41c445ff
JB		 7772
7773 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7774 i40e_vlan_stripping_enable(vsi);
7775 else
7776 i40e_vlan_stripping_disable(vsi);
7777
7c3c288b
ASJ		 7778 need_reset = i40e_set_ntuple(pf, features);
7779
7780 if (need_reset)
7781 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7782
41c445ff
JB		 7783 return 0;
7784}
7785
a1c9a9d9
JK		 7786#ifdef CONFIG_I40E_VXLAN
7787/**
7788 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7789 * @pf: board private structure
7790 * @port: The UDP port to look up
7791 *
7792 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7793 **/
7794static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7795{
7796 u8 i;
7797
7798 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7799 if (pf->vxlan_ports[i] == port)
7800 return i;
7801 }
7802
7803 return i;
7804}
7805
7806/**
7807 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7808 * @netdev: This physical port's netdev
7809 * @sa_family: Socket Family that VXLAN is notifying us about
7810 * @port: New UDP port number that VXLAN started listening to
7811 **/
7812static void i40e_add_vxlan_port(struct net_device *netdev,
7813 sa_family_t sa_family, __be16 port)
7814{
7815 struct i40e_netdev_priv *np = netdev_priv(netdev);
7816 struct i40e_vsi *vsi = np->vsi;
7817 struct i40e_pf *pf = vsi->back;
7818 u8 next_idx;
7819 u8 idx;
7820
7821 if (sa_family == AF_INET6)
7822 return;
7823
7824 idx = i40e_get_vxlan_port_idx(pf, port);
7825
7826 /* Check if port already exists */
7827 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7828 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7829 return;
7830 }
7831
7832 /* Now check if there is space to add the new port */
7833 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7834
7835 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7836 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7837 ntohs(port));
7838 return;
7839 }
7840
7841 /* New port: add it and mark its index in the bitmap */
7842 pf->vxlan_ports[next_idx] = port;
7843 pf->pending_vxlan_bitmap |= (1 << next_idx);
7844
7845 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7846}
7847
7848/**
7849 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7850 * @netdev: This physical port's netdev
7851 * @sa_family: Socket Family that VXLAN is notifying us about
7852 * @port: UDP port number that VXLAN stopped listening to
7853 **/
7854static void i40e_del_vxlan_port(struct net_device *netdev,
7855 sa_family_t sa_family, __be16 port)
7856{
7857 struct i40e_netdev_priv *np = netdev_priv(netdev);
7858 struct i40e_vsi *vsi = np->vsi;
7859 struct i40e_pf *pf = vsi->back;
7860 u8 idx;
7861
7862 if (sa_family == AF_INET6)
7863 return;
7864
7865 idx = i40e_get_vxlan_port_idx(pf, port);
7866
7867 /* Check if port already exists */
7868 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7869 /* if port exists, set it to 0 (mark for deletion)
7870 * and make it pending
7871 */
7872 pf->vxlan_ports[idx] = 0;
7873
7874 pf->pending_vxlan_bitmap |= (1 << idx);
7875
7876 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7877 } else {
7878 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7879 ntohs(port));
7880 }
7881}
7882
7883#endif
1f224ad2 7884static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7885 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7886{
7887 struct i40e_netdev_priv *np = netdev_priv(netdev);
7888 struct i40e_pf *pf = np->vsi->back;
7889 struct i40e_hw *hw = &pf->hw;
7890
7891 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7892 return -EOPNOTSUPP;
7893
7894 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7895 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7896
7897 return 0;
7898}
7899
2f90ade6
JB		 7900/**
7901 * i40e_ndo_fdb_add - add an entry to the hardware database
7902 * @ndm: the input from the stack
7903 * @tb: pointer to array of nladdr (unused)
7904 * @dev: the net device pointer
7905 * @addr: the MAC address entry being added
7906 * @flags: instructions from stack about fdb operation
7907 */
4ba0dea5
GR		 7908static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7909 struct net_device *dev,
f6f6424b 7910 const unsigned char *addr, u16 vid,
4ba0dea5 7911 u16 flags)
4ba0dea5
GR		 7912{
7913 struct i40e_netdev_priv *np = netdev_priv(dev);
7914 struct i40e_pf *pf = np->vsi->back;
7915 int err = 0;
7916
7917 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7918 return -EOPNOTSUPP;
7919
65891fea
OG		 7920 if (vid) {
7921 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
7922 return -EINVAL;
7923 }
7924
4ba0dea5
GR		 7925 /* Hardware does not support aging addresses so if a
7926 * ndm_state is given only allow permanent addresses
7927 */
7928 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7929 netdev_info(dev, "FDB only supports static addresses\n");
7930 return -EINVAL;
7931 }
7932
7933 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7934 err = dev_uc_add_excl(dev, addr);
7935 else if (is_multicast_ether_addr(addr))
7936 err = dev_mc_add_excl(dev, addr);
7937 else
7938 err = -EINVAL;
7939
7940 /* Only return duplicate errors if NLM_F_EXCL is set */
7941 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7942 err = 0;
7943
7944 return err;
7945}
7946
51616018
NP		 7947#ifdef HAVE_BRIDGE_ATTRIBS
7948/**
7949 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
7950 * @dev: the netdev being configured
7951 * @nlh: RTNL message
7952 *
7953 * Inserts a new hardware bridge if not already created and
7954 * enables the bridging mode requested (VEB or VEPA). If the
7955 * hardware bridge has already been inserted and the request
7956 * is to change the mode then that requires a PF reset to
7957 * allow rebuild of the components with required hardware
7958 * bridge mode enabled.
7959 **/
7960static int i40e_ndo_bridge_setlink(struct net_device *dev,
7961 struct nlmsghdr *nlh)
7962{
7963 struct i40e_netdev_priv *np = netdev_priv(dev);
7964 struct i40e_vsi *vsi = np->vsi;
7965 struct i40e_pf *pf = vsi->back;
7966 struct i40e_veb *veb = NULL;
7967 struct nlattr *attr, *br_spec;
7968 int i, rem;
7969
7970 /* Only for PF VSI for now */
7971 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
7972 return -EOPNOTSUPP;
7973
7974 /* Find the HW bridge for PF VSI */
7975 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7976 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7977 veb = pf->veb[i];
7978 }
7979
7980 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7981
7982 nla_for_each_nested(attr, br_spec, rem) {
7983 __u16 mode;
7984
7985 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7986 continue;
7987
7988 mode = nla_get_u16(attr);
7989 if ((mode != BRIDGE_MODE_VEPA) &&
7990 (mode != BRIDGE_MODE_VEB))
7991 return -EINVAL;
7992
7993 /* Insert a new HW bridge */
7994 if (!veb) {
7995 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7996 vsi->tc_config.enabled_tc);
7997 if (veb) {
7998 veb->bridge_mode = mode;
7999 i40e_config_bridge_mode(veb);
8000 } else {
8001 /* No Bridge HW offload available */
8002 return -ENOENT;
8003 }
8004 break;
8005 } else if (mode != veb->bridge_mode) {
8006 /* Existing HW bridge but different mode needs reset */
8007 veb->bridge_mode = mode;
8008 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
8009 break;
8010 }
8011 }
8012
8013 return 0;
8014}
8015
8016/**
8017 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8018 * @skb: skb buff
8019 * @pid: process id
8020 * @seq: RTNL message seq #
8021 * @dev: the netdev being configured
8022 * @filter_mask: unused
8023 *
8024 * Return the mode in which the hardware bridge is operating in
8025 * i.e VEB or VEPA.
8026 **/
8027#ifdef HAVE_BRIDGE_FILTER
8028static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8029 struct net_device *dev,
8030 u32 __always_unused filter_mask)
8031#else
8032static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8033 struct net_device *dev)
8034#endif /* HAVE_BRIDGE_FILTER */
8035{
8036 struct i40e_netdev_priv *np = netdev_priv(dev);
8037 struct i40e_vsi *vsi = np->vsi;
8038 struct i40e_pf *pf = vsi->back;
8039 struct i40e_veb *veb = NULL;
8040 int i;
8041
8042 /* Only for PF VSI for now */
8043 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8044 return -EOPNOTSUPP;
8045
8046 /* Find the HW bridge for the PF VSI */
8047 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8048 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8049 veb = pf->veb[i];
8050 }
8051
8052 if (!veb)
8053 return 0;
8054
8055 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode);
8056}
8057#endif /* HAVE_BRIDGE_ATTRIBS */
8058
37a2973a 8059static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8060 .ndo_open = i40e_open,
8061 .ndo_stop = i40e_close,
8062 .ndo_start_xmit = i40e_lan_xmit_frame,
8063 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8064 .ndo_set_rx_mode = i40e_set_rx_mode,
8065 .ndo_validate_addr = eth_validate_addr,
8066 .ndo_set_mac_address = i40e_set_mac,
8067 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8068 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8069 .ndo_tx_timeout = i40e_tx_timeout,
8070 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8071 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8072#ifdef CONFIG_NET_POLL_CONTROLLER
8073 .ndo_poll_controller = i40e_netpoll,
8074#endif
8075 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8076#ifdef I40E_FCOE
8077 .ndo_fcoe_enable = i40e_fcoe_enable,
8078 .ndo_fcoe_disable = i40e_fcoe_disable,
8079#endif
41c445ff
JB		 8080 .ndo_set_features = i40e_set_features,
8081 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8082 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8083 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8084 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8085 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8086 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 8087#ifdef CONFIG_I40E_VXLAN
8088 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8089 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8090#endif
1f224ad2 8091 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8092 .ndo_fdb_add = i40e_ndo_fdb_add,
51616018
NP		 8093#ifdef HAVE_BRIDGE_ATTRIBS
8094 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8095 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
8096#endif /* HAVE_BRIDGE_ATTRIBS */
41c445ff
JB		 8097};
8098
8099/**
8100 * i40e_config_netdev - Setup the netdev flags
8101 * @vsi: the VSI being configured
8102 *
8103 * Returns 0 on success, negative value on failure
8104 **/
8105static int i40e_config_netdev(struct i40e_vsi *vsi)
8106{
1a10370a 8107 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8108 struct i40e_pf *pf = vsi->back;
8109 struct i40e_hw *hw = &pf->hw;
8110 struct i40e_netdev_priv *np;
8111 struct net_device *netdev;
8112 u8 mac_addr[ETH_ALEN];
8113 int etherdev_size;
8114
8115 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8116 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8117 if (!netdev)
8118 return -ENOMEM;
8119
8120 vsi->netdev = netdev;
8121 np = netdev_priv(netdev);
8122 np->vsi = vsi;
8123
d70e941b 8124 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8125 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 8126 NETIF_F_TSO;
41c445ff
JB		 8127
8128 netdev->features = NETIF_F_SG |
8129 NETIF_F_IP_CSUM |
8130 NETIF_F_SCTP_CSUM |
8131 NETIF_F_HIGHDMA |
8132 NETIF_F_GSO_UDP_TUNNEL |
8133 NETIF_F_HW_VLAN_CTAG_TX |
8134 NETIF_F_HW_VLAN_CTAG_RX |
8135 NETIF_F_HW_VLAN_CTAG_FILTER |
8136 NETIF_F_IPV6_CSUM |
8137 NETIF_F_TSO |
059dab69 8138 NETIF_F_TSO_ECN |
41c445ff
JB		 8139 NETIF_F_TSO6 |
8140 NETIF_F_RXCSUM |
8141 NETIF_F_RXHASH |
8142 0;
8143
2e86a0b6
ASJ		 8144 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8145 netdev->features |= NETIF_F_NTUPLE;
8146
41c445ff
JB		 8147 /* copy netdev features into list of user selectable features */
8148 netdev->hw_features |= netdev->features;
8149
8150 if (vsi->type == I40E_VSI_MAIN) {
8151 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8152 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8153 /* The following steps are necessary to prevent reception
8154 * of tagged packets - some older NVM configurations load a
8155 * default a MAC-VLAN filter that accepts any tagged packet
8156 * which must be replaced by a normal filter.
8c27d42e 8157 */
30650cc5
SN		 8158 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
8159 i40e_add_filter(vsi, mac_addr,
8160 I40E_VLAN_ANY, false, true);
41c445ff
JB		 8161 } else {
8162 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8163 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8164 pf->vsi[pf->lan_vsi]->netdev->name);
8165 random_ether_addr(mac_addr);
8166 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
8167 }
1a10370a 8168 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 8169
9a173901
GR		 8170 ether_addr_copy(netdev->dev_addr, mac_addr);
8171 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8172 /* vlan gets same features (except vlan offload)
8173 * after any tweaks for specific VSI types
8174 */
8175 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8176 NETIF_F_HW_VLAN_CTAG_RX |
8177 NETIF_F_HW_VLAN_CTAG_FILTER);
8178 netdev->priv_flags |= IFF_UNICAST_FLT;
8179 netdev->priv_flags |= IFF_SUPP_NOFCS;
8180 /* Setup netdev TC information */
8181 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8182
8183 netdev->netdev_ops = &i40e_netdev_ops;
8184 netdev->watchdog_timeo = 5 * HZ;
8185 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8186#ifdef I40E_FCOE
8187 i40e_fcoe_config_netdev(netdev, vsi);
8188#endif
41c445ff
JB		 8189
8190 return 0;
8191}
8192
8193/**
8194 * i40e_vsi_delete - Delete a VSI from the switch
8195 * @vsi: the VSI being removed
8196 *
8197 * Returns 0 on success, negative value on failure
8198 **/
8199static void i40e_vsi_delete(struct i40e_vsi *vsi)
8200{
8201 /* remove default VSI is not allowed */
8202 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8203 return;
8204
41c445ff 8205 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8206}
8207
51616018
NP		 8208/**
8209 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8210 * @vsi: the VSI being queried
8211 *
8212 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8213 **/
8214int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8215{
8216 struct i40e_veb *veb;
8217 struct i40e_pf *pf = vsi->back;
8218
8219 /* Uplink is not a bridge so default to VEB */
8220 if (vsi->veb_idx == I40E_NO_VEB)
8221 return 1;
8222
8223 veb = pf->veb[vsi->veb_idx];
8224 /* Uplink is a bridge in VEPA mode */
8225 if (veb && (veb->bridge_mode & BRIDGE_MODE_VEPA))
8226 return 0;
8227
8228 /* Uplink is a bridge in VEB mode */
8229 return 1;
8230}
8231
41c445ff
JB		 8232/**
8233 * i40e_add_vsi - Add a VSI to the switch
8234 * @vsi: the VSI being configured
8235 *
8236 * This initializes a VSI context depending on the VSI type to be added and
8237 * passes it down to the add_vsi aq command.
8238 **/
8239static int i40e_add_vsi(struct i40e_vsi *vsi)
8240{
8241 int ret = -ENODEV;
8242 struct i40e_mac_filter *f, *ftmp;
8243 struct i40e_pf *pf = vsi->back;
8244 struct i40e_hw *hw = &pf->hw;
8245 struct i40e_vsi_context ctxt;
8246 u8 enabled_tc = 0x1; /* TC0 enabled */
8247 int f_count = 0;
8248
8249 memset(&ctxt, 0, sizeof(ctxt));
8250 switch (vsi->type) {
8251 case I40E_VSI_MAIN:
8252 /* The PF's main VSI is already setup as part of the
8253 * device initialization, so we'll not bother with
8254 * the add_vsi call, but we will retrieve the current
8255 * VSI context.
8256 */
8257 ctxt.seid = pf->main_vsi_seid;
8258 ctxt.pf_num = pf->hw.pf_id;
8259 ctxt.vf_num = 0;
8260 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8261 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8262 if (ret) {
8263 dev_info(&pf->pdev->dev,
b40c82e6 8264 "couldn't get PF vsi config, err %d, aq_err %d\n",
41c445ff
JB		 8265 ret, pf->hw.aq.asq_last_status);
8266 return -ENOENT;
8267 }
8268 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8269 vsi->info.valid_sections = 0;
8270
8271 vsi->seid = ctxt.seid;
8272 vsi->id = ctxt.vsi_number;
8273
8274 enabled_tc = i40e_pf_get_tc_map(pf);
8275
8276 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8277 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8278 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8279 memset(&ctxt, 0, sizeof(ctxt));
8280 ctxt.seid = pf->main_vsi_seid;
8281 ctxt.pf_num = pf->hw.pf_id;
8282 ctxt.vf_num = 0;
8283 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8284 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8285 if (ret) {
8286 dev_info(&pf->pdev->dev,
8287 "update vsi failed, aq_err=%d\n",
8288 pf->hw.aq.asq_last_status);
8289 ret = -ENOENT;
8290 goto err;
8291 }
8292 /* update the local VSI info queue map */
8293 i40e_vsi_update_queue_map(vsi, &ctxt);
8294 vsi->info.valid_sections = 0;
8295 } else {
8296 /* Default/Main VSI is only enabled for TC0
8297 * reconfigure it to enable all TCs that are
8298 * available on the port in SFP mode.
63d7e5a4
NP		 8299 * For MFP case the iSCSI PF would use this
8300 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8301 */
8302 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8303 if (ret) {
8304 dev_info(&pf->pdev->dev,
8305 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
8306 enabled_tc, ret,
8307 pf->hw.aq.asq_last_status);
8308 ret = -ENOENT;
8309 }
8310 }
8311 break;
8312
8313 case I40E_VSI_FDIR:
cbf61325
ASJ		 8314 ctxt.pf_num = hw->pf_id;
8315 ctxt.vf_num = 0;
8316 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8317 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 8318 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
51616018
NP		 8319 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8320 ctxt.info.valid_sections |=
79c21a82 8321 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 8322 ctxt.info.switch_id =
79c21a82 8323 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 8324 }
41c445ff 8325 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 8326 break;
8327
8328 case I40E_VSI_VMDQ2:
8329 ctxt.pf_num = hw->pf_id;
8330 ctxt.vf_num = 0;
8331 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8332 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8333 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
8334
41c445ff
JB		 8335 /* This VSI is connected to VEB so the switch_id
8336 * should be set to zero by default.
8337 */
51616018
NP		 8338 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8339 ctxt.info.valid_sections |=
8340 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8341 ctxt.info.switch_id =
8342 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8343 }
41c445ff
JB		 8344
8345 /* Setup the VSI tx/rx queue map for TC0 only for now */
8346 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8347 break;
8348
8349 case I40E_VSI_SRIOV:
8350 ctxt.pf_num = hw->pf_id;
8351 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
8352 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 8353 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 8354 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
8355
41c445ff
JB		 8356 /* This VSI is connected to VEB so the switch_id
8357 * should be set to zero by default.
8358 */
51616018
NP		 8359 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
8360 ctxt.info.valid_sections |=
8361 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8362 ctxt.info.switch_id =
8363 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8364 }
41c445ff
JB		 8365
8366 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
8367 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 8368 if (pf->vf[vsi->vf_id].spoofchk) {
8369 ctxt.info.valid_sections |=
8370 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
8371 ctxt.info.sec_flags |=
8372 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
8373 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
8374 }
41c445ff
JB		 8375 /* Setup the VSI tx/rx queue map for TC0 only for now */
8376 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
8377 break;
8378
38e00438
VD		 8379#ifdef I40E_FCOE
8380 case I40E_VSI_FCOE:
8381 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
8382 if (ret) {
8383 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
8384 return ret;
8385 }
8386 break;
8387
8388#endif /* I40E_FCOE */
41c445ff
JB		 8389 default:
8390 return -ENODEV;
8391 }
8392
8393 if (vsi->type != I40E_VSI_MAIN) {
8394 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
8395 if (ret) {
8396 dev_info(&vsi->back->pdev->dev,
8397 "add vsi failed, aq_err=%d\n",
8398 vsi->back->hw.aq.asq_last_status);
8399 ret = -ENOENT;
8400 goto err;
8401 }
8402 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
8403 vsi->info.valid_sections = 0;
8404 vsi->seid = ctxt.seid;
8405 vsi->id = ctxt.vsi_number;
8406 }
8407
8408 /* If macvlan filters already exist, force them to get loaded */
8409 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
8410 f->changed = true;
8411 f_count++;
6252c7e4
SN		 8412
8413 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 8414 struct i40e_aqc_remove_macvlan_element_data element;
8415
8416 memset(&element, 0, sizeof(element));
8417 ether_addr_copy(element.mac_addr, f->macaddr);
8418 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
8419 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
8420 &element, 1, NULL);
8421 if (ret) {
8422 /* some older FW has a different default */
8423 element.flags |=
8424 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
8425 i40e_aq_remove_macvlan(hw, vsi->seid,
8426 &element, 1, NULL);
8427 }
8428
8429 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 8430 I40E_AQC_WRITE_TYPE_LAA_WOL,
8431 f->macaddr, NULL);
8432 }
41c445ff
JB		 8433 }
8434 if (f_count) {
8435 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
8436 pf->flags |= I40E_FLAG_FILTER_SYNC;
8437 }
8438
8439 /* Update VSI BW information */
8440 ret = i40e_vsi_get_bw_info(vsi);
8441 if (ret) {
8442 dev_info(&pf->pdev->dev,
8443 "couldn't get vsi bw info, err %d, aq_err %d\n",
8444 ret, pf->hw.aq.asq_last_status);
8445 /* VSI is already added so not tearing that up */
8446 ret = 0;
8447 }
8448
8449err:
8450 return ret;
8451}
8452
8453/**
8454 * i40e_vsi_release - Delete a VSI and free its resources
8455 * @vsi: the VSI being removed
8456 *
8457 * Returns 0 on success or < 0 on error
8458 **/
8459int i40e_vsi_release(struct i40e_vsi *vsi)
8460{
8461 struct i40e_mac_filter *f, *ftmp;
8462 struct i40e_veb *veb = NULL;
8463 struct i40e_pf *pf;
8464 u16 uplink_seid;
8465 int i, n;
8466
8467 pf = vsi->back;
8468
8469 /* release of a VEB-owner or last VSI is not allowed */
8470 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
8471 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
8472 vsi->seid, vsi->uplink_seid);
8473 return -ENODEV;
8474 }
8475 if (vsi == pf->vsi[pf->lan_vsi] &&
8476 !test_bit(__I40E_DOWN, &pf->state)) {
8477 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
8478 return -ENODEV;
8479 }
8480
8481 uplink_seid = vsi->uplink_seid;
8482 if (vsi->type != I40E_VSI_SRIOV) {
8483 if (vsi->netdev_registered) {
8484 vsi->netdev_registered = false;
8485 if (vsi->netdev) {
8486 /* results in a call to i40e_close() */
8487 unregister_netdev(vsi->netdev);
41c445ff
JB		 8488 }
8489 } else {
90ef8d47 8490 i40e_vsi_close(vsi);
41c445ff
JB		 8491 }
8492 i40e_vsi_disable_irq(vsi);
8493 }
8494
8495 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
8496 i40e_del_filter(vsi, f->macaddr, f->vlan,
8497 f->is_vf, f->is_netdev);
8498 i40e_sync_vsi_filters(vsi);
8499
8500 i40e_vsi_delete(vsi);
8501 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 8502 if (vsi->netdev) {
8503 free_netdev(vsi->netdev);
8504 vsi->netdev = NULL;
8505 }
41c445ff
JB		 8506 i40e_vsi_clear_rings(vsi);
8507 i40e_vsi_clear(vsi);
8508
8509 /* If this was the last thing on the VEB, except for the
8510 * controlling VSI, remove the VEB, which puts the controlling
8511 * VSI onto the next level down in the switch.
8512 *
8513 * Well, okay, there's one more exception here: don't remove
8514 * the orphan VEBs yet. We'll wait for an explicit remove request
8515 * from up the network stack.
8516 */
505682cd 8517 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8518 if (pf->vsi[i] &&
8519 pf->vsi[i]->uplink_seid == uplink_seid &&
8520 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8521 n++; /* count the VSIs */
8522 }
8523 }
8524 for (i = 0; i < I40E_MAX_VEB; i++) {
8525 if (!pf->veb[i])
8526 continue;
8527 if (pf->veb[i]->uplink_seid == uplink_seid)
8528 n++; /* count the VEBs */
8529 if (pf->veb[i]->seid == uplink_seid)
8530 veb = pf->veb[i];
8531 }
8532 if (n == 0 && veb && veb->uplink_seid != 0)
8533 i40e_veb_release(veb);
8534
8535 return 0;
8536}
8537
8538/**
8539 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8540 * @vsi: ptr to the VSI
8541 *
8542 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8543 * corresponding SW VSI structure and initializes num_queue_pairs for the
8544 * newly allocated VSI.
8545 *
8546 * Returns 0 on success or negative on failure
8547 **/
8548static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8549{
8550 int ret = -ENOENT;
8551 struct i40e_pf *pf = vsi->back;
8552
493fb300 8553 if (vsi->q_vectors[0]) {
41c445ff
JB		 8554 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8555 vsi->seid);
8556 return -EEXIST;
8557 }
8558
8559 if (vsi->base_vector) {
f29eaa3d 8560 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8561 vsi->seid, vsi->base_vector);
8562 return -EEXIST;
8563 }
8564
90e04070 8565 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8566 if (ret) {
8567 dev_info(&pf->pdev->dev,
8568 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8569 vsi->num_q_vectors, vsi->seid, ret);
8570 vsi->num_q_vectors = 0;
8571 goto vector_setup_out;
8572 }
8573
958a3e3b
SN		 8574 if (vsi->num_q_vectors)
8575 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8576 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8577 if (vsi->base_vector < 0) {
8578 dev_info(&pf->pdev->dev,
049a2be8
SN		 8579 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8580 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8581 i40e_vsi_free_q_vectors(vsi);
8582 ret = -ENOENT;
8583 goto vector_setup_out;
8584 }
8585
8586vector_setup_out:
8587 return ret;
8588}
8589
bc7d338f
ASJ		 8590/**
8591 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8592 * @vsi: pointer to the vsi.
8593 *
8594 * This re-allocates a vsi's queue resources.
8595 *
8596 * Returns pointer to the successfully allocated and configured VSI sw struct
8597 * on success, otherwise returns NULL on failure.
8598 **/
8599static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8600{
8601 struct i40e_pf *pf = vsi->back;
8602 u8 enabled_tc;
8603 int ret;
8604
8605 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8606 i40e_vsi_clear_rings(vsi);
8607
8608 i40e_vsi_free_arrays(vsi, false);
8609 i40e_set_num_rings_in_vsi(vsi);
8610 ret = i40e_vsi_alloc_arrays(vsi, false);
8611 if (ret)
8612 goto err_vsi;
8613
8614 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8615 if (ret < 0) {
049a2be8
SN		 8616 dev_info(&pf->pdev->dev,
8617 "failed to get tracking for %d queues for VSI %d err=%d\n",
8618 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8619 goto err_vsi;
8620 }
8621 vsi->base_queue = ret;
8622
8623 /* Update the FW view of the VSI. Force a reset of TC and queue
8624 * layout configurations.
8625 */
8626 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8627 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8628 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8629 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8630
8631 /* assign it some queues */
8632 ret = i40e_alloc_rings(vsi);
8633 if (ret)
8634 goto err_rings;
8635
8636 /* map all of the rings to the q_vectors */
8637 i40e_vsi_map_rings_to_vectors(vsi);
8638 return vsi;
8639
8640err_rings:
8641 i40e_vsi_free_q_vectors(vsi);
8642 if (vsi->netdev_registered) {
8643 vsi->netdev_registered = false;
8644 unregister_netdev(vsi->netdev);
8645 free_netdev(vsi->netdev);
8646 vsi->netdev = NULL;
8647 }
8648 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8649err_vsi:
8650 i40e_vsi_clear(vsi);
8651 return NULL;
8652}
8653
41c445ff
JB		 8654/**
8655 * i40e_vsi_setup - Set up a VSI by a given type
8656 * @pf: board private structure
8657 * @type: VSI type
8658 * @uplink_seid: the switch element to link to
8659 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8660 *
8661 * This allocates the sw VSI structure and its queue resources, then add a VSI
8662 * to the identified VEB.
8663 *
8664 * Returns pointer to the successfully allocated and configure VSI sw struct on
8665 * success, otherwise returns NULL on failure.
8666 **/
8667struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8668 u16 uplink_seid, u32 param1)
8669{
8670 struct i40e_vsi *vsi = NULL;
8671 struct i40e_veb *veb = NULL;
8672 int ret, i;
8673 int v_idx;
8674
8675 /* The requested uplink_seid must be either
8676 * - the PF's port seid
8677 * no VEB is needed because this is the PF
8678 * or this is a Flow Director special case VSI
8679 * - seid of an existing VEB
8680 * - seid of a VSI that owns an existing VEB
8681 * - seid of a VSI that doesn't own a VEB
8682 * a new VEB is created and the VSI becomes the owner
8683 * - seid of the PF VSI, which is what creates the first VEB
8684 * this is a special case of the previous
8685 *
8686 * Find which uplink_seid we were given and create a new VEB if needed
8687 */
8688 for (i = 0; i < I40E_MAX_VEB; i++) {
8689 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8690 veb = pf->veb[i];
8691 break;
8692 }
8693 }
8694
8695 if (!veb && uplink_seid != pf->mac_seid) {
8696
505682cd 8697 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8698 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8699 vsi = pf->vsi[i];
8700 break;
8701 }
8702 }
8703 if (!vsi) {
8704 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8705 uplink_seid);
8706 return NULL;
8707 }
8708
8709 if (vsi->uplink_seid == pf->mac_seid)
8710 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8711 vsi->tc_config.enabled_tc);
8712 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8713 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8714 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8715 if (veb) {
8716 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8717 dev_info(&vsi->back->pdev->dev,
8718 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8719 __func__);
8720 return NULL;
8721 }
51616018 8722 i40e_config_bridge_mode(veb);
79c21a82 8723 }
41c445ff
JB		 8724 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8725 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8726 veb = pf->veb[i];
8727 }
8728 if (!veb) {
8729 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8730 return NULL;
8731 }
8732
8733 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8734 uplink_seid = veb->seid;
8735 }
8736
8737 /* get vsi sw struct */
8738 v_idx = i40e_vsi_mem_alloc(pf, type);
8739 if (v_idx < 0)
8740 goto err_alloc;
8741 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8742 if (!vsi)
8743 goto err_alloc;
41c445ff
JB		 8744 vsi->type = type;
8745 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8746
8747 if (type == I40E_VSI_MAIN)
8748 pf->lan_vsi = v_idx;
8749 else if (type == I40E_VSI_SRIOV)
8750 vsi->vf_id = param1;
8751 /* assign it some queues */
cbf61325
ASJ		 8752 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8753 vsi->idx);
41c445ff 8754 if (ret < 0) {
049a2be8
SN		 8755 dev_info(&pf->pdev->dev,
8756 "failed to get tracking for %d queues for VSI %d err=%d\n",
8757 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8758 goto err_vsi;
8759 }
8760 vsi->base_queue = ret;
8761
8762 /* get a VSI from the hardware */
8763 vsi->uplink_seid = uplink_seid;
8764 ret = i40e_add_vsi(vsi);
8765 if (ret)
8766 goto err_vsi;
8767
8768 switch (vsi->type) {
8769 /* setup the netdev if needed */
8770 case I40E_VSI_MAIN:
8771 case I40E_VSI_VMDQ2:
38e00438 8772 case I40E_VSI_FCOE:
41c445ff
JB		 8773 ret = i40e_config_netdev(vsi);
8774 if (ret)
8775 goto err_netdev;
8776 ret = register_netdev(vsi->netdev);
8777 if (ret)
8778 goto err_netdev;
8779 vsi->netdev_registered = true;
8780 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8781#ifdef CONFIG_I40E_DCB
8782 /* Setup DCB netlink interface */
8783 i40e_dcbnl_setup(vsi);
8784#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8785 /* fall through */
8786
8787 case I40E_VSI_FDIR:
8788 /* set up vectors and rings if needed */
8789 ret = i40e_vsi_setup_vectors(vsi);
8790 if (ret)
8791 goto err_msix;
8792
8793 ret = i40e_alloc_rings(vsi);
8794 if (ret)
8795 goto err_rings;
8796
8797 /* map all of the rings to the q_vectors */
8798 i40e_vsi_map_rings_to_vectors(vsi);
8799
8800 i40e_vsi_reset_stats(vsi);
8801 break;
8802
8803 default:
8804 /* no netdev or rings for the other VSI types */
8805 break;
8806 }
8807
8808 return vsi;
8809
8810err_rings:
8811 i40e_vsi_free_q_vectors(vsi);
8812err_msix:
8813 if (vsi->netdev_registered) {
8814 vsi->netdev_registered = false;
8815 unregister_netdev(vsi->netdev);
8816 free_netdev(vsi->netdev);
8817 vsi->netdev = NULL;
8818 }
8819err_netdev:
8820 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8821err_vsi:
8822 i40e_vsi_clear(vsi);
8823err_alloc:
8824 return NULL;
8825}
8826
8827/**
8828 * i40e_veb_get_bw_info - Query VEB BW information
8829 * @veb: the veb to query
8830 *
8831 * Query the Tx scheduler BW configuration data for given VEB
8832 **/
8833static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8834{
8835 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8836 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8837 struct i40e_pf *pf = veb->pf;
8838 struct i40e_hw *hw = &pf->hw;
8839 u32 tc_bw_max;
8840 int ret = 0;
8841 int i;
8842
8843 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8844 &bw_data, NULL);
8845 if (ret) {
8846 dev_info(&pf->pdev->dev,
8847 "query veb bw config failed, aq_err=%d\n",
8848 hw->aq.asq_last_status);
8849 goto out;
8850 }
8851
8852 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8853 &ets_data, NULL);
8854 if (ret) {
8855 dev_info(&pf->pdev->dev,
8856 "query veb bw ets config failed, aq_err=%d\n",
8857 hw->aq.asq_last_status);
8858 goto out;
8859 }
8860
8861 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8862 veb->bw_max_quanta = ets_data.tc_bw_max;
8863 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8864 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8865 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8866 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8867 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8868 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8869 veb->bw_tc_limit_credits[i] =
8870 le16_to_cpu(bw_data.tc_bw_limits[i]);
8871 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8872 }
8873
8874out:
8875 return ret;
8876}
8877
8878/**
8879 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8880 * @pf: board private structure
8881 *
8882 * On error: returns error code (negative)
8883 * On success: returns vsi index in PF (positive)
8884 **/
8885static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8886{
8887 int ret = -ENOENT;
8888 struct i40e_veb *veb;
8889 int i;
8890
8891 /* Need to protect the allocation of switch elements at the PF level */
8892 mutex_lock(&pf->switch_mutex);
8893
8894 /* VEB list may be fragmented if VEB creation/destruction has
8895 * been happening. We can afford to do a quick scan to look
8896 * for any free slots in the list.
8897 *
8898 * find next empty veb slot, looping back around if necessary
8899 */
8900 i = 0;
8901 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8902 i++;
8903 if (i >= I40E_MAX_VEB) {
8904 ret = -ENOMEM;
8905 goto err_alloc_veb; /* out of VEB slots! */
8906 }
8907
8908 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8909 if (!veb) {
8910 ret = -ENOMEM;
8911 goto err_alloc_veb;
8912 }
8913 veb->pf = pf;
8914 veb->idx = i;
8915 veb->enabled_tc = 1;
8916
8917 pf->veb[i] = veb;
8918 ret = i;
8919err_alloc_veb:
8920 mutex_unlock(&pf->switch_mutex);
8921 return ret;
8922}
8923
8924/**
8925 * i40e_switch_branch_release - Delete a branch of the switch tree
8926 * @branch: where to start deleting
8927 *
8928 * This uses recursion to find the tips of the branch to be
8929 * removed, deleting until we get back to and can delete this VEB.
8930 **/
8931static void i40e_switch_branch_release(struct i40e_veb *branch)
8932{
8933 struct i40e_pf *pf = branch->pf;
8934 u16 branch_seid = branch->seid;
8935 u16 veb_idx = branch->idx;
8936 int i;
8937
8938 /* release any VEBs on this VEB - RECURSION */
8939 for (i = 0; i < I40E_MAX_VEB; i++) {
8940 if (!pf->veb[i])
8941 continue;
8942 if (pf->veb[i]->uplink_seid == branch->seid)
8943 i40e_switch_branch_release(pf->veb[i]);
8944 }
8945
8946 /* Release the VSIs on this VEB, but not the owner VSI.
8947 *
8948 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8949 * the VEB itself, so don't use (*branch) after this loop.
8950 */
505682cd 8951 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8952 if (!pf->vsi[i])
8953 continue;
8954 if (pf->vsi[i]->uplink_seid == branch_seid &&
8955 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8956 i40e_vsi_release(pf->vsi[i]);
8957 }
8958 }
8959
8960 /* There's one corner case where the VEB might not have been
8961 * removed, so double check it here and remove it if needed.
8962 * This case happens if the veb was created from the debugfs
8963 * commands and no VSIs were added to it.
8964 */
8965 if (pf->veb[veb_idx])
8966 i40e_veb_release(pf->veb[veb_idx]);
8967}
8968
8969/**
8970 * i40e_veb_clear - remove veb struct
8971 * @veb: the veb to remove
8972 **/
8973static void i40e_veb_clear(struct i40e_veb *veb)
8974{
8975 if (!veb)
8976 return;
8977
8978 if (veb->pf) {
8979 struct i40e_pf *pf = veb->pf;
8980
8981 mutex_lock(&pf->switch_mutex);
8982 if (pf->veb[veb->idx] == veb)
8983 pf->veb[veb->idx] = NULL;
8984 mutex_unlock(&pf->switch_mutex);
8985 }
8986
8987 kfree(veb);
8988}
8989
8990/**
8991 * i40e_veb_release - Delete a VEB and free its resources
8992 * @veb: the VEB being removed
8993 **/
8994void i40e_veb_release(struct i40e_veb *veb)
8995{
8996 struct i40e_vsi *vsi = NULL;
8997 struct i40e_pf *pf;
8998 int i, n = 0;
8999
9000 pf = veb->pf;
9001
9002 /* find the remaining VSI and check for extras */
505682cd 9003 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9004 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9005 n++;
9006 vsi = pf->vsi[i];
9007 }
9008 }
9009 if (n != 1) {
9010 dev_info(&pf->pdev->dev,
9011 "can't remove VEB %d with %d VSIs left\n",
9012 veb->seid, n);
9013 return;
9014 }
9015
9016 /* move the remaining VSI to uplink veb */
9017 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9018 if (veb->uplink_seid) {
9019 vsi->uplink_seid = veb->uplink_seid;
9020 if (veb->uplink_seid == pf->mac_seid)
9021 vsi->veb_idx = I40E_NO_VEB;
9022 else
9023 vsi->veb_idx = veb->veb_idx;
9024 } else {
9025 /* floating VEB */
9026 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9027 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9028 }
9029
9030 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9031 i40e_veb_clear(veb);
41c445ff
JB		 9032}
9033
9034/**
9035 * i40e_add_veb - create the VEB in the switch
9036 * @veb: the VEB to be instantiated
9037 * @vsi: the controlling VSI
9038 **/
9039static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9040{
56747264 9041 bool is_default = false;
e1c51b95 9042 bool is_cloud = false;
41c445ff
JB		 9043 int ret;
9044
9045 /* get a VEB from the hardware */
9046 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9047 veb->enabled_tc, is_default,
9048 is_cloud, &veb->seid, NULL);
41c445ff
JB		 9049 if (ret) {
9050 dev_info(&veb->pf->pdev->dev,
9051 "couldn't add VEB, err %d, aq_err %d\n",
9052 ret, veb->pf->hw.aq.asq_last_status);
9053 return -EPERM;
9054 }
9055
9056 /* get statistics counter */
9057 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
9058 &veb->stats_idx, NULL, NULL, NULL);
9059 if (ret) {
9060 dev_info(&veb->pf->pdev->dev,
9061 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
9062 ret, veb->pf->hw.aq.asq_last_status);
9063 return -EPERM;
9064 }
9065 ret = i40e_veb_get_bw_info(veb);
9066 if (ret) {
9067 dev_info(&veb->pf->pdev->dev,
9068 "couldn't get VEB bw info, err %d, aq_err %d\n",
9069 ret, veb->pf->hw.aq.asq_last_status);
9070 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
9071 return -ENOENT;
9072 }
9073
9074 vsi->uplink_seid = veb->seid;
9075 vsi->veb_idx = veb->idx;
9076 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9077
9078 return 0;
9079}
9080
9081/**
9082 * i40e_veb_setup - Set up a VEB
9083 * @pf: board private structure
9084 * @flags: VEB setup flags
9085 * @uplink_seid: the switch element to link to
9086 * @vsi_seid: the initial VSI seid
9087 * @enabled_tc: Enabled TC bit-map
9088 *
9089 * This allocates the sw VEB structure and links it into the switch
9090 * It is possible and legal for this to be a duplicate of an already
9091 * existing VEB. It is also possible for both uplink and vsi seids
9092 * to be zero, in order to create a floating VEB.
9093 *
9094 * Returns pointer to the successfully allocated VEB sw struct on
9095 * success, otherwise returns NULL on failure.
9096 **/
9097struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9098 u16 uplink_seid, u16 vsi_seid,
9099 u8 enabled_tc)
9100{
9101 struct i40e_veb *veb, *uplink_veb = NULL;
9102 int vsi_idx, veb_idx;
9103 int ret;
9104
9105 /* if one seid is 0, the other must be 0 to create a floating relay */
9106 if ((uplink_seid == 0 || vsi_seid == 0) &&
9107 (uplink_seid + vsi_seid != 0)) {
9108 dev_info(&pf->pdev->dev,
9109 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9110 uplink_seid, vsi_seid);
9111 return NULL;
9112 }
9113
9114 /* make sure there is such a vsi and uplink */
505682cd 9115 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9116 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9117 break;
505682cd 9118 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9119 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9120 vsi_seid);
9121 return NULL;
9122 }
9123
9124 if (uplink_seid && uplink_seid != pf->mac_seid) {
9125 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9126 if (pf->veb[veb_idx] &&
9127 pf->veb[veb_idx]->seid == uplink_seid) {
9128 uplink_veb = pf->veb[veb_idx];
9129 break;
9130 }
9131 }
9132 if (!uplink_veb) {
9133 dev_info(&pf->pdev->dev,
9134 "uplink seid %d not found\n", uplink_seid);
9135 return NULL;
9136 }
9137 }
9138
9139 /* get veb sw struct */
9140 veb_idx = i40e_veb_mem_alloc(pf);
9141 if (veb_idx < 0)
9142 goto err_alloc;
9143 veb = pf->veb[veb_idx];
9144 veb->flags = flags;
9145 veb->uplink_seid = uplink_seid;
9146 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9147 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9148
9149 /* create the VEB in the switch */
9150 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9151 if (ret)
9152 goto err_veb;
1bb8b935
SN		 9153 if (vsi_idx == pf->lan_vsi)
9154 pf->lan_veb = veb->idx;
41c445ff
JB		 9155
9156 return veb;
9157
9158err_veb:
9159 i40e_veb_clear(veb);
9160err_alloc:
9161 return NULL;
9162}
9163
9164/**
b40c82e6 9165 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9166 * @pf: board private structure
9167 * @ele: element we are building info from
9168 * @num_reported: total number of elements
9169 * @printconfig: should we print the contents
9170 *
9171 * helper function to assist in extracting a few useful SEID values.
9172 **/
9173static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9174 struct i40e_aqc_switch_config_element_resp *ele,
9175 u16 num_reported, bool printconfig)
9176{
9177 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9178 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9179 u8 element_type = ele->element_type;
9180 u16 seid = le16_to_cpu(ele->seid);
9181
9182 if (printconfig)
9183 dev_info(&pf->pdev->dev,
9184 "type=%d seid=%d uplink=%d downlink=%d\n",
9185 element_type, seid, uplink_seid, downlink_seid);
9186
9187 switch (element_type) {
9188 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9189 pf->mac_seid = seid;
9190 break;
9191 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9192 /* Main VEB? */
9193 if (uplink_seid != pf->mac_seid)
9194 break;
9195 if (pf->lan_veb == I40E_NO_VEB) {
9196 int v;
9197
9198 /* find existing or else empty VEB */
9199 for (v = 0; v < I40E_MAX_VEB; v++) {
9200 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9201 pf->lan_veb = v;
9202 break;
9203 }
9204 }
9205 if (pf->lan_veb == I40E_NO_VEB) {
9206 v = i40e_veb_mem_alloc(pf);
9207 if (v < 0)
9208 break;
9209 pf->lan_veb = v;
9210 }
9211 }
9212
9213 pf->veb[pf->lan_veb]->seid = seid;
9214 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9215 pf->veb[pf->lan_veb]->pf = pf;
9216 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9217 break;
9218 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9219 if (num_reported != 1)
9220 break;
9221 /* This is immediately after a reset so we can assume this is
9222 * the PF's VSI
9223 */
9224 pf->mac_seid = uplink_seid;
9225 pf->pf_seid = downlink_seid;
9226 pf->main_vsi_seid = seid;
9227 if (printconfig)
9228 dev_info(&pf->pdev->dev,
9229 "pf_seid=%d main_vsi_seid=%d\n",
9230 pf->pf_seid, pf->main_vsi_seid);
9231 break;
9232 case I40E_SWITCH_ELEMENT_TYPE_PF:
9233 case I40E_SWITCH_ELEMENT_TYPE_VF:
9234 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9235 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9236 case I40E_SWITCH_ELEMENT_TYPE_PE:
9237 case I40E_SWITCH_ELEMENT_TYPE_PA:
9238 /* ignore these for now */
9239 break;
9240 default:
9241 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9242 element_type, seid);
9243 break;
9244 }
9245}
9246
9247/**
9248 * i40e_fetch_switch_configuration - Get switch config from firmware
9249 * @pf: board private structure
9250 * @printconfig: should we print the contents
9251 *
9252 * Get the current switch configuration from the device and
9253 * extract a few useful SEID values.
9254 **/
9255int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9256{
9257 struct i40e_aqc_get_switch_config_resp *sw_config;
9258 u16 next_seid = 0;
9259 int ret = 0;
9260 u8 *aq_buf;
9261 int i;
9262
9263 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
9264 if (!aq_buf)
9265 return -ENOMEM;
9266
9267 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
9268 do {
9269 u16 num_reported, num_total;
9270
9271 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
9272 I40E_AQ_LARGE_BUF,
9273 &next_seid, NULL);
9274 if (ret) {
9275 dev_info(&pf->pdev->dev,
9276 "get switch config failed %d aq_err=%x\n",
9277 ret, pf->hw.aq.asq_last_status);
9278 kfree(aq_buf);
9279 return -ENOENT;
9280 }
9281
9282 num_reported = le16_to_cpu(sw_config->header.num_reported);
9283 num_total = le16_to_cpu(sw_config->header.num_total);
9284
9285 if (printconfig)
9286 dev_info(&pf->pdev->dev,
9287 "header: %d reported %d total\n",
9288 num_reported, num_total);
9289
41c445ff
JB		 9290 for (i = 0; i < num_reported; i++) {
9291 struct i40e_aqc_switch_config_element_resp *ele =
9292 &sw_config->element[i];
9293
9294 i40e_setup_pf_switch_element(pf, ele, num_reported,
9295 printconfig);
9296 }
9297 } while (next_seid != 0);
9298
9299 kfree(aq_buf);
9300 return ret;
9301}
9302
9303/**
9304 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
9305 * @pf: board private structure
bc7d338f 9306 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 9307 *
9308 * Returns 0 on success, negative value on failure
9309 **/
bc7d338f 9310static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 9311{
9312 int ret;
9313
9314 /* find out what's out there already */
9315 ret = i40e_fetch_switch_configuration(pf, false);
9316 if (ret) {
9317 dev_info(&pf->pdev->dev,
9318 "couldn't fetch switch config, err %d, aq_err %d\n",
9319 ret, pf->hw.aq.asq_last_status);
9320 return ret;
9321 }
9322 i40e_pf_reset_stats(pf);
9323
41c445ff 9324 /* first time setup */
bc7d338f 9325 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 9326 struct i40e_vsi *vsi = NULL;
9327 u16 uplink_seid;
9328
9329 /* Set up the PF VSI associated with the PF's main VSI
9330 * that is already in the HW switch
9331 */
9332 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
9333 uplink_seid = pf->veb[pf->lan_veb]->seid;
9334 else
9335 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 9336 if (pf->lan_vsi == I40E_NO_VSI)
9337 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
9338 else if (reinit)
9339 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 9340 if (!vsi) {
9341 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
9342 i40e_fdir_teardown(pf);
9343 return -EAGAIN;
9344 }
41c445ff
JB		 9345 } else {
9346 /* force a reset of TC and queue layout configurations */
9347 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9348 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9349 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9350 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9351 }
9352 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
9353
cbf61325
ASJ		 9354 i40e_fdir_sb_setup(pf);
9355
41c445ff
JB		 9356 /* Setup static PF queue filter control settings */
9357 ret = i40e_setup_pf_filter_control(pf);
9358 if (ret) {
9359 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
9360 ret);
9361 /* Failure here should not stop continuing other steps */
9362 }
9363
9364 /* enable RSS in the HW, even for only one queue, as the stack can use
9365 * the hash
9366 */
9367 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
9368 i40e_config_rss(pf);
9369
9370 /* fill in link information and enable LSE reporting */
21af70fb 9371 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
a34a6711
MW		 9372 i40e_link_event(pf);
9373
d52c20b7 9374 /* Initialize user-specific link properties */
41c445ff
JB		 9375 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
9376 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 9377
beb0dff1
JK		 9378 i40e_ptp_init(pf);
9379
41c445ff
JB		 9380 return ret;
9381}
9382
41c445ff
JB		 9383/**
9384 * i40e_determine_queue_usage - Work out queue distribution
9385 * @pf: board private structure
9386 **/
9387static void i40e_determine_queue_usage(struct i40e_pf *pf)
9388{
41c445ff
JB		 9389 int queues_left;
9390
9391 pf->num_lan_qps = 0;
38e00438
VD		 9392#ifdef I40E_FCOE
9393 pf->num_fcoe_qps = 0;
9394#endif
41c445ff
JB		 9395
9396 /* Find the max queues to be put into basic use. We'll always be
9397 * using TC0, whether or not DCB is running, and TC0 will get the
9398 * big RSS set.
9399 */
9400 queues_left = pf->hw.func_caps.num_tx_qp;
9401
cbf61325 9402 if ((queues_left == 1) ||
9aa7e935 9403 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 9404 /* one qp for PF, no queues for anything else */
9405 queues_left = 0;
9406 pf->rss_size = pf->num_lan_qps = 1;
9407
9408 /* make sure all the fancies are disabled */
60ea5f83 9409 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9410#ifdef I40E_FCOE
9411 I40E_FLAG_FCOE_ENABLED |
9412#endif
60ea5f83
JB		 9413 I40E_FLAG_FD_SB_ENABLED |
9414 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9415 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 9416 I40E_FLAG_SRIOV_ENABLED |
9417 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 9418 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
9419 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 9420 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 9421 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 9422 /* one qp for PF */
9423 pf->rss_size = pf->num_lan_qps = 1;
9424 queues_left -= pf->num_lan_qps;
9425
9426 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 9427#ifdef I40E_FCOE
9428 I40E_FLAG_FCOE_ENABLED |
9429#endif
9aa7e935
FZ		 9430 I40E_FLAG_FD_SB_ENABLED |
9431 I40E_FLAG_FD_ATR_ENABLED |
9432 I40E_FLAG_DCB_ENABLED |
9433 I40E_FLAG_VMDQ_ENABLED);
41c445ff 9434 } else {
cbf61325 9435 /* Not enough queues for all TCs */
4d9b6043 9436 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 9437 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 9438 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 9439 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
9440 }
9a3bd2f1
ASJ		 9441 pf->num_lan_qps = max_t(int, pf->rss_size_max,
9442 num_online_cpus());
9443 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
9444 pf->hw.func_caps.num_tx_qp);
9445
cbf61325
ASJ		 9446 queues_left -= pf->num_lan_qps;
9447 }
9448
38e00438
VD		 9449#ifdef I40E_FCOE
9450 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
9451 if (I40E_DEFAULT_FCOE <= queues_left) {
9452 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
9453 } else if (I40E_MINIMUM_FCOE <= queues_left) {
9454 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
9455 } else {
9456 pf->num_fcoe_qps = 0;
9457 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
9458 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
9459 }
9460
9461 queues_left -= pf->num_fcoe_qps;
9462 }
9463
9464#endif
cbf61325
ASJ		 9465 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9466 if (queues_left > 1) {
9467 queues_left -= 1; /* save 1 queue for FD */
9468 } else {
9469 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9470 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
9471 }
41c445ff
JB		 9472 }
9473
9474 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
9475 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 9476 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
9477 (queues_left / pf->num_vf_qps));
41c445ff
JB		 9478 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
9479 }
9480
9481 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
9482 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
9483 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
9484 (queues_left / pf->num_vmdq_qps));
9485 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
9486 }
9487
f8ff1464 9488 pf->queues_left = queues_left;
38e00438
VD		 9489#ifdef I40E_FCOE
9490 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
9491#endif
41c445ff
JB		 9492}
9493
9494/**
9495 * i40e_setup_pf_filter_control - Setup PF static filter control
9496 * @pf: PF to be setup
9497 *
b40c82e6 9498 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 9499 * settings. If PE/FCoE are enabled then it will also set the per PF
9500 * based filter sizes required for them. It also enables Flow director,
9501 * ethertype and macvlan type filter settings for the pf.
9502 *
9503 * Returns 0 on success, negative on failure
9504 **/
9505static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
9506{
9507 struct i40e_filter_control_settings *settings = &pf->filter_settings;
9508
9509 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
9510
9511 /* Flow Director is enabled */
60ea5f83 9512 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 9513 settings->enable_fdir = true;
9514
9515 /* Ethtype and MACVLAN filters enabled for PF */
9516 settings->enable_ethtype = true;
9517 settings->enable_macvlan = true;
9518
9519 if (i40e_set_filter_control(&pf->hw, settings))
9520 return -ENOENT;
9521
9522 return 0;
9523}
9524
0c22b3dd
JB		 9525#define INFO_STRING_LEN 255
9526static void i40e_print_features(struct i40e_pf *pf)
9527{
9528 struct i40e_hw *hw = &pf->hw;
9529 char *buf, *string;
9530
9531 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9532 if (!string) {
9533 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9534 return;
9535 }
9536
9537 buf = string;
9538
9539 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9540#ifdef CONFIG_PCI_IOV
9541 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9542#endif
aba237d1
MW		 9543 buf += sprintf(buf, "VSIs: %d QP: %d RX: %s ",
9544 pf->hw.func_caps.num_vsis,
9545 pf->vsi[pf->lan_vsi]->num_queue_pairs,
9546 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 9547
9548 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9549 buf += sprintf(buf, "RSS ");
0c22b3dd 9550 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9551 buf += sprintf(buf, "FD_ATR ");
9552 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9553 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9554 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9555 }
4d9b6043 9556 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9557 buf += sprintf(buf, "DCB ");
9558 if (pf->flags & I40E_FLAG_PTP)
9559 buf += sprintf(buf, "PTP ");
38e00438
VD		 9560#ifdef I40E_FCOE
9561 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9562 buf += sprintf(buf, "FCOE ");
9563#endif
0c22b3dd
JB		 9564
9565 BUG_ON(buf > (string + INFO_STRING_LEN));
9566 dev_info(&pf->pdev->dev, "%s\n", string);
9567 kfree(string);
9568}
9569
41c445ff
JB		 9570/**
9571 * i40e_probe - Device initialization routine
9572 * @pdev: PCI device information struct
9573 * @ent: entry in i40e_pci_tbl
9574 *
b40c82e6
JK		 9575 * i40e_probe initializes a PF identified by a pci_dev structure.
9576 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 9577 * and a hardware reset occur.
9578 *
9579 * Returns 0 on success, negative on failure
9580 **/
9581static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9582{
e827845c 9583 struct i40e_aq_get_phy_abilities_resp abilities;
e815665e 9584 unsigned long ioremap_len;
41c445ff
JB		 9585 struct i40e_pf *pf;
9586 struct i40e_hw *hw;
93cd765b 9587 static u16 pfs_found;
d4dfb81a 9588 u16 link_status;
41c445ff
JB		 9589 int err = 0;
9590 u32 len;
8a9eb7d3 9591 u32 i;
41c445ff
JB		 9592
9593 err = pci_enable_device_mem(pdev);
9594 if (err)
9595 return err;
9596
9597 /* set up for high or low dma */
6494294f 9598 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9599 if (err) {
e3e3bfdd
JS		 9600 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9601 if (err) {
9602 dev_err(&pdev->dev,
9603 "DMA configuration failed: 0x%x\n", err);
9604 goto err_dma;
9605 }
41c445ff
JB		 9606 }
9607
9608 /* set up pci connections */
9609 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9610 IORESOURCE_MEM), i40e_driver_name);
9611 if (err) {
9612 dev_info(&pdev->dev,
9613 "pci_request_selected_regions failed %d\n", err);
9614 goto err_pci_reg;
9615 }
9616
9617 pci_enable_pcie_error_reporting(pdev);
9618 pci_set_master(pdev);
9619
9620 /* Now that we have a PCI connection, we need to do the
9621 * low level device setup. This is primarily setting up
9622 * the Admin Queue structures and then querying for the
9623 * device's current profile information.
9624 */
9625 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9626 if (!pf) {
9627 err = -ENOMEM;
9628 goto err_pf_alloc;
9629 }
9630 pf->next_vsi = 0;
9631 pf->pdev = pdev;
9632 set_bit(__I40E_DOWN, &pf->state);
9633
9634 hw = &pf->hw;
9635 hw->back = pf;
232f4706 9636
e815665e 9637 ioremap_len = min_t(unsigned long, pci_resource_len(pdev, 0),
232f4706
AS		 9638 I40E_MAX_CSR_SPACE);
9639
9640 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), ioremap_len);
41c445ff
JB		 9641 if (!hw->hw_addr) {
9642 err = -EIO;
9643 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9644 (unsigned int)pci_resource_start(pdev, 0),
9645 (unsigned int)pci_resource_len(pdev, 0), err);
9646 goto err_ioremap;
9647 }
9648 hw->vendor_id = pdev->vendor;
9649 hw->device_id = pdev->device;
9650 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9651 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9652 hw->subsystem_device_id = pdev->subsystem_device;
9653 hw->bus.device = PCI_SLOT(pdev->devfn);
9654 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9655 pf->instance = pfs_found;
41c445ff 9656
5b5faa43
SN		 9657 if (debug != -1) {
9658 pf->msg_enable = pf->hw.debug_mask;
9659 pf->msg_enable = debug;
9660 }
9661
7134f9ce
JB		 9662 /* do a special CORER for clearing PXE mode once at init */
9663 if (hw->revision_id == 0 &&
9664 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9665 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9666 i40e_flush(hw);
9667 msleep(200);
9668 pf->corer_count++;
9669
9670 i40e_clear_pxe_mode(hw);
9671 }
9672
41c445ff 9673 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9674 i40e_clear_hw(hw);
41c445ff
JB		 9675 err = i40e_pf_reset(hw);
9676 if (err) {
9677 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9678 goto err_pf_reset;
9679 }
9680 pf->pfr_count++;
9681
9682 hw->aq.num_arq_entries = I40E_AQ_LEN;
9683 hw->aq.num_asq_entries = I40E_AQ_LEN;
9684 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9685 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9686 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9687
b294ac70 9688 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 9689 "%s-%s:misc",
9690 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9691
9692 err = i40e_init_shared_code(hw);
9693 if (err) {
9694 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9695 goto err_pf_reset;
9696 }
9697
d52c20b7
JB		 9698 /* set up a default setting for link flow control */
9699 pf->hw.fc.requested_mode = I40E_FC_NONE;
9700
41c445ff
JB		 9701 err = i40e_init_adminq(hw);
9702 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9703 if (err) {
9704 dev_info(&pdev->dev,
7aa67613 9705 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9706 goto err_pf_reset;
9707 }
9708
7aa67613
CS		 9709 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9710 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9711 dev_info(&pdev->dev,
7aa67613
CS		 9712 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9713 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9714 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9715 dev_info(&pdev->dev,
7aa67613 9716 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 9717
4eb3f768
SN		 9718 i40e_verify_eeprom(pf);
9719
2c5fe33b
JB		 9720 /* Rev 0 hardware was never productized */
9721 if (hw->revision_id < 1)
9722 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9723
6ff4ef86 9724 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9725 err = i40e_get_capabilities(pf);
9726 if (err)
9727 goto err_adminq_setup;
9728
9729 err = i40e_sw_init(pf);
9730 if (err) {
9731 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9732 goto err_sw_init;
9733 }
9734
9735 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9736 hw->func_caps.num_rx_qp,
9737 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9738 if (err) {
9739 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9740 goto err_init_lan_hmc;
9741 }
9742
9743 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9744 if (err) {
9745 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9746 err = -ENOENT;
9747 goto err_configure_lan_hmc;
9748 }
9749
b686ece5
NP		 9750 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
9751 * Ignore error return codes because if it was already disabled via
9752 * hardware settings this will fail
9753 */
9754 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
9755 (pf->hw.aq.fw_maj_ver < 4)) {
9756 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
9757 i40e_aq_stop_lldp(hw, true, NULL);
9758 }
9759
41c445ff 9760 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9761 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9762 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9763 err = -EIO;
9764 goto err_mac_addr;
9765 }
9766 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9767 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9768 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9769 if (is_valid_ether_addr(hw->mac.port_addr))
9770 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9771#ifdef I40E_FCOE
9772 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9773 if (err)
9774 dev_info(&pdev->dev,
9775 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9776 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9777 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9778 hw->mac.san_addr);
9779 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9780 }
9781 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9782#endif /* I40E_FCOE */
41c445ff
JB		 9783
9784 pci_set_drvdata(pdev, pf);
9785 pci_save_state(pdev);
4e3b35b0
NP		 9786#ifdef CONFIG_I40E_DCB
9787 err = i40e_init_pf_dcb(pf);
9788 if (err) {
aebfc816 9789 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 9790 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9791 /* Continue without DCB enabled */
4e3b35b0
NP		 9792 }
9793#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9794
9795 /* set up periodic task facility */
9796 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9797 pf->service_timer_period = HZ;
9798
9799 INIT_WORK(&pf->service_task, i40e_service_task);
9800 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9801 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9802 pf->link_check_timeout = jiffies;
9803
8e2773ae
SN		 9804 /* WoL defaults to disabled */
9805 pf->wol_en = false;
9806 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9807
41c445ff
JB		 9808 /* set up the main switch operations */
9809 i40e_determine_queue_usage(pf);
9810 i40e_init_interrupt_scheme(pf);
9811
505682cd
MW		 9812 /* The number of VSIs reported by the FW is the minimum guaranteed
9813 * to us; HW supports far more and we share the remaining pool with
9814 * the other PFs. We allocate space for more than the guarantee with
9815 * the understanding that we might not get them all later.
41c445ff 9816 */
505682cd
MW		 9817 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9818 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9819 else
9820 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9821
9822 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9823 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9824 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9825 if (!pf->vsi) {
9826 err = -ENOMEM;
41c445ff 9827 goto err_switch_setup;
ed87ac09 9828 }
41c445ff 9829
bc7d338f 9830 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9831 if (err) {
9832 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9833 goto err_vsis;
9834 }
8a9eb7d3 9835 /* if FDIR VSI was set up, start it now */
505682cd 9836 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9837 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9838 i40e_vsi_open(pf->vsi[i]);
9839 break;
9840 }
9841 }
41c445ff 9842
7e2453fe
JB		 9843 /* driver is only interested in link up/down and module qualification
9844 * reports from firmware
9845 */
9846 err = i40e_aq_set_phy_int_mask(&pf->hw,
9847 I40E_AQ_EVENT_LINK_UPDOWN |
9848 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9849 if (err)
9850 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9851
025b4a54
ASJ		 9852 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
9853 (pf->hw.aq.fw_maj_ver < 4)) {
9854 msleep(75);
9855 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9856 if (err)
9857 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9858 pf->hw.aq.asq_last_status);
cafa2ee6 9859 }
41c445ff
JB		 9860 /* The main driver is (mostly) up and happy. We need to set this state
9861 * before setting up the misc vector or we get a race and the vector
9862 * ends up disabled forever.
9863 */
9864 clear_bit(__I40E_DOWN, &pf->state);
9865
9866 /* In case of MSIX we are going to setup the misc vector right here
9867 * to handle admin queue events etc. In case of legacy and MSI
9868 * the misc functionality and queue processing is combined in
9869 * the same vector and that gets setup at open.
9870 */
9871 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9872 err = i40e_setup_misc_vector(pf);
9873 if (err) {
9874 dev_info(&pdev->dev,
9875 "setup of misc vector failed: %d\n", err);
9876 goto err_vsis;
9877 }
9878 }
9879
df805f62 9880#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9881 /* prep for VF support */
9882 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9883 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9884 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9885 u32 val;
9886
9887 /* disable link interrupts for VFs */
9888 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9889 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9890 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9891 i40e_flush(hw);
4aeec010
MW		 9892
9893 if (pci_num_vf(pdev)) {
9894 dev_info(&pdev->dev,
9895 "Active VFs found, allocating resources.\n");
9896 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9897 if (err)
9898 dev_info(&pdev->dev,
9899 "Error %d allocating resources for existing VFs\n",
9900 err);
9901 }
41c445ff 9902 }
df805f62 9903#endif /* CONFIG_PCI_IOV */
41c445ff 9904
93cd765b
ASJ		 9905 pfs_found++;
9906
41c445ff
JB		 9907 i40e_dbg_pf_init(pf);
9908
9909 /* tell the firmware that we're starting */
44033fac 9910 i40e_send_version(pf);
41c445ff
JB		 9911
9912 /* since everything's happy, start the service_task timer */
9913 mod_timer(&pf->service_timer,
9914 round_jiffies(jiffies + pf->service_timer_period));
9915
38e00438
VD		 9916#ifdef I40E_FCOE
9917 /* create FCoE interface */
9918 i40e_fcoe_vsi_setup(pf);
9919
9920#endif
d4dfb81a
CS		 9921 /* Get the negotiated link width and speed from PCI config space */
9922 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9923
9924 i40e_set_pci_config_data(hw, link_status);
9925
69bfb110 9926 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9927 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9928 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9929 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9930 "Unknown"),
9931 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9932 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9933 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9934 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9935 "Unknown"));
9936
9937 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9938 hw->bus.speed < i40e_bus_speed_8000) {
9939 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9940 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9941 }
9942
e827845c
CS		 9943 /* get the requested speeds from the fw */
9944 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
9945 if (err)
9946 dev_info(&pf->pdev->dev, "get phy abilities failed, aq_err %d, advertised speed settings may not be correct\n",
9947 err);
9948 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
9949
0c22b3dd
JB		 9950 /* print a string summarizing features */
9951 i40e_print_features(pf);
9952
41c445ff
JB		 9953 return 0;
9954
9955 /* Unwind what we've done if something failed in the setup */
9956err_vsis:
9957 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9958 i40e_clear_interrupt_scheme(pf);
9959 kfree(pf->vsi);
04b03013
SN		 9960err_switch_setup:
9961 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9962 del_timer_sync(&pf->service_timer);
9963err_mac_addr:
9964err_configure_lan_hmc:
9965 (void)i40e_shutdown_lan_hmc(hw);
9966err_init_lan_hmc:
9967 kfree(pf->qp_pile);
41c445ff
JB		 9968err_sw_init:
9969err_adminq_setup:
9970 (void)i40e_shutdown_adminq(hw);
9971err_pf_reset:
9972 iounmap(hw->hw_addr);
9973err_ioremap:
9974 kfree(pf);
9975err_pf_alloc:
9976 pci_disable_pcie_error_reporting(pdev);
9977 pci_release_selected_regions(pdev,
9978 pci_select_bars(pdev, IORESOURCE_MEM));
9979err_pci_reg:
9980err_dma:
9981 pci_disable_device(pdev);
9982 return err;
9983}
9984
9985/**
9986 * i40e_remove - Device removal routine
9987 * @pdev: PCI device information struct
9988 *
9989 * i40e_remove is called by the PCI subsystem to alert the driver
9990 * that is should release a PCI device. This could be caused by a
9991 * Hot-Plug event, or because the driver is going to be removed from
9992 * memory.
9993 **/
9994static void i40e_remove(struct pci_dev *pdev)
9995{
9996 struct i40e_pf *pf = pci_get_drvdata(pdev);
9997 i40e_status ret_code;
41c445ff
JB		 9998 int i;
9999
10000 i40e_dbg_pf_exit(pf);
10001
beb0dff1
JK		 10002 i40e_ptp_stop(pf);
10003
41c445ff
JB		 10004 /* no more scheduling of any task */
10005 set_bit(__I40E_DOWN, &pf->state);
10006 del_timer_sync(&pf->service_timer);
10007 cancel_work_sync(&pf->service_task);
33c62b34 10008 i40e_fdir_teardown(pf);
41c445ff 10009
eb2d80bc
MW		 10010 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10011 i40e_free_vfs(pf);
10012 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10013 }
10014
41c445ff
JB		 10015 i40e_fdir_teardown(pf);
10016
10017 /* If there is a switch structure or any orphans, remove them.
10018 * This will leave only the PF's VSI remaining.
10019 */
10020 for (i = 0; i < I40E_MAX_VEB; i++) {
10021 if (!pf->veb[i])
10022 continue;
10023
10024 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10025 pf->veb[i]->uplink_seid == 0)
10026 i40e_switch_branch_release(pf->veb[i]);
10027 }
10028
10029 /* Now we can shutdown the PF's VSI, just before we kill
10030 * adminq and hmc.
10031 */
10032 if (pf->vsi[pf->lan_vsi])
10033 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10034
41c445ff 10035 /* shutdown and destroy the HMC */
60442dea
SN		 10036 if (pf->hw.hmc.hmc_obj) {
10037 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10038 if (ret_code)
10039 dev_warn(&pdev->dev,
10040 "Failed to destroy the HMC resources: %d\n",
10041 ret_code);
10042 }
41c445ff
JB		 10043
10044 /* shutdown the adminq */
41c445ff
JB		 10045 ret_code = i40e_shutdown_adminq(&pf->hw);
10046 if (ret_code)
10047 dev_warn(&pdev->dev,
10048 "Failed to destroy the Admin Queue resources: %d\n",
10049 ret_code);
10050
10051 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10052 i40e_clear_interrupt_scheme(pf);
505682cd 10053 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10054 if (pf->vsi[i]) {
10055 i40e_vsi_clear_rings(pf->vsi[i]);
10056 i40e_vsi_clear(pf->vsi[i]);
10057 pf->vsi[i] = NULL;
10058 }
10059 }
10060
10061 for (i = 0; i < I40E_MAX_VEB; i++) {
10062 kfree(pf->veb[i]);
10063 pf->veb[i] = NULL;
10064 }
10065
10066 kfree(pf->qp_pile);
41c445ff
JB		 10067 kfree(pf->vsi);
10068
41c445ff
JB		 10069 iounmap(pf->hw.hw_addr);
10070 kfree(pf);
10071 pci_release_selected_regions(pdev,
10072 pci_select_bars(pdev, IORESOURCE_MEM));
10073
10074 pci_disable_pcie_error_reporting(pdev);
10075 pci_disable_device(pdev);
10076}
10077
10078/**
10079 * i40e_pci_error_detected - warning that something funky happened in PCI land
10080 * @pdev: PCI device information struct
10081 *
10082 * Called to warn that something happened and the error handling steps
10083 * are in progress. Allows the driver to quiesce things, be ready for
10084 * remediation.
10085 **/
10086static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10087 enum pci_channel_state error)
10088{
10089 struct i40e_pf *pf = pci_get_drvdata(pdev);
10090
10091 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10092
10093 /* shutdown all operations */
9007bccd
SN		 10094 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10095 rtnl_lock();
10096 i40e_prep_for_reset(pf);
10097 rtnl_unlock();
10098 }
41c445ff
JB		 10099
10100 /* Request a slot reset */
10101 return PCI_ERS_RESULT_NEED_RESET;
10102}
10103
10104/**
10105 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10106 * @pdev: PCI device information struct
10107 *
10108 * Called to find if the driver can work with the device now that
10109 * the pci slot has been reset. If a basic connection seems good
10110 * (registers are readable and have sane content) then return a
10111 * happy little PCI_ERS_RESULT_xxx.
10112 **/
10113static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10114{
10115 struct i40e_pf *pf = pci_get_drvdata(pdev);
10116 pci_ers_result_t result;
10117 int err;
10118 u32 reg;
10119
10120 dev_info(&pdev->dev, "%s\n", __func__);
10121 if (pci_enable_device_mem(pdev)) {
10122 dev_info(&pdev->dev,
10123 "Cannot re-enable PCI device after reset.\n");
10124 result = PCI_ERS_RESULT_DISCONNECT;
10125 } else {
10126 pci_set_master(pdev);
10127 pci_restore_state(pdev);
10128 pci_save_state(pdev);
10129 pci_wake_from_d3(pdev, false);
10130
10131 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10132 if (reg == 0)
10133 result = PCI_ERS_RESULT_RECOVERED;
10134 else
10135 result = PCI_ERS_RESULT_DISCONNECT;
10136 }
10137
10138 err = pci_cleanup_aer_uncorrect_error_status(pdev);
10139 if (err) {
10140 dev_info(&pdev->dev,
10141 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
10142 err);
10143 /* non-fatal, continue */
10144 }
10145
10146 return result;
10147}
10148
10149/**
10150 * i40e_pci_error_resume - restart operations after PCI error recovery
10151 * @pdev: PCI device information struct
10152 *
10153 * Called to allow the driver to bring things back up after PCI error
10154 * and/or reset recovery has finished.
10155 **/
10156static void i40e_pci_error_resume(struct pci_dev *pdev)
10157{
10158 struct i40e_pf *pf = pci_get_drvdata(pdev);
10159
10160 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 10161 if (test_bit(__I40E_SUSPENDED, &pf->state))
10162 return;
10163
10164 rtnl_lock();
41c445ff 10165 i40e_handle_reset_warning(pf);
9007bccd
SN		 10166 rtnl_lock();
10167}
10168
10169/**
10170 * i40e_shutdown - PCI callback for shutting down
10171 * @pdev: PCI device information struct
10172 **/
10173static void i40e_shutdown(struct pci_dev *pdev)
10174{
10175 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10176 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10177
10178 set_bit(__I40E_SUSPENDED, &pf->state);
10179 set_bit(__I40E_DOWN, &pf->state);
10180 rtnl_lock();
10181 i40e_prep_for_reset(pf);
10182 rtnl_unlock();
10183
8e2773ae
SN		 10184 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10185 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10186
e147758d
SN		 10187 i40e_clear_interrupt_scheme(pf);
10188
9007bccd 10189 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 10190 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10191 pci_set_power_state(pdev, PCI_D3hot);
10192 }
10193}
10194
10195#ifdef CONFIG_PM
10196/**
10197 * i40e_suspend - PCI callback for moving to D3
10198 * @pdev: PCI device information struct
10199 **/
10200static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
10201{
10202 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 10203 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 10204
10205 set_bit(__I40E_SUSPENDED, &pf->state);
10206 set_bit(__I40E_DOWN, &pf->state);
88086e5d
MW		 10207 del_timer_sync(&pf->service_timer);
10208 cancel_work_sync(&pf->service_task);
9007bccd
SN		 10209 rtnl_lock();
10210 i40e_prep_for_reset(pf);
10211 rtnl_unlock();
10212
8e2773ae
SN		 10213 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
10214 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
10215
10216 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 10217 pci_set_power_state(pdev, PCI_D3hot);
10218
10219 return 0;
41c445ff
JB		 10220}
10221
9007bccd
SN		 10222/**
10223 * i40e_resume - PCI callback for waking up from D3
10224 * @pdev: PCI device information struct
10225 **/
10226static int i40e_resume(struct pci_dev *pdev)
10227{
10228 struct i40e_pf *pf = pci_get_drvdata(pdev);
10229 u32 err;
10230
10231 pci_set_power_state(pdev, PCI_D0);
10232 pci_restore_state(pdev);
10233 /* pci_restore_state() clears dev->state_saves, so
10234 * call pci_save_state() again to restore it.
10235 */
10236 pci_save_state(pdev);
10237
10238 err = pci_enable_device_mem(pdev);
10239 if (err) {
10240 dev_err(&pdev->dev,
10241 "%s: Cannot enable PCI device from suspend\n",
10242 __func__);
10243 return err;
10244 }
10245 pci_set_master(pdev);
10246
10247 /* no wakeup events while running */
10248 pci_wake_from_d3(pdev, false);
10249
10250 /* handling the reset will rebuild the device state */
10251 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
10252 clear_bit(__I40E_DOWN, &pf->state);
10253 rtnl_lock();
10254 i40e_reset_and_rebuild(pf, false);
10255 rtnl_unlock();
10256 }
10257
10258 return 0;
10259}
10260
10261#endif
41c445ff
JB		 10262static const struct pci_error_handlers i40e_err_handler = {
10263 .error_detected = i40e_pci_error_detected,
10264 .slot_reset = i40e_pci_error_slot_reset,
10265 .resume = i40e_pci_error_resume,
10266};
10267
10268static struct pci_driver i40e_driver = {
10269 .name = i40e_driver_name,
10270 .id_table = i40e_pci_tbl,
10271 .probe = i40e_probe,
10272 .remove = i40e_remove,
9007bccd
SN		 10273#ifdef CONFIG_PM
10274 .suspend = i40e_suspend,
10275 .resume = i40e_resume,
10276#endif
10277 .shutdown = i40e_shutdown,
41c445ff
JB		 10278 .err_handler = &i40e_err_handler,
10279 .sriov_configure = i40e_pci_sriov_configure,
10280};
10281
10282/**
10283 * i40e_init_module - Driver registration routine
10284 *
10285 * i40e_init_module is the first routine called when the driver is
10286 * loaded. All it does is register with the PCI subsystem.
10287 **/
10288static int __init i40e_init_module(void)
10289{
10290 pr_info("%s: %s - version %s\n", i40e_driver_name,
10291 i40e_driver_string, i40e_driver_version_str);
10292 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 10293
41c445ff
JB		 10294 i40e_dbg_init();
10295 return pci_register_driver(&i40e_driver);
10296}
10297module_init(i40e_init_module);
10298
10299/**
10300 * i40e_exit_module - Driver exit cleanup routine
10301 *
10302 * i40e_exit_module is called just before the driver is removed
10303 * from memory.
10304 **/
10305static void __exit i40e_exit_module(void)
10306{
10307 pci_unregister_driver(&i40e_driver);
10308 i40e_dbg_exit();
10309}
10310module_exit(i40e_exit_module);
Linux kernel - Deliverables
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