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i40e: Add new update VSI flow to accommodate FW fix with VSI Loopback mode
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
7bda87c7
CS		 41#define DRV_VERSION_MINOR 1
42#define DRV_VERSION_BUILD 23
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
9baa3c34 68static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
38e00438
VD		 273#ifdef I40E_FCOE
274void i40e_tx_timeout(struct net_device *netdev)
275#else
41c445ff 276static void i40e_tx_timeout(struct net_device *netdev)
38e00438 277#endif
41c445ff
JB		 278{
279 struct i40e_netdev_priv *np = netdev_priv(netdev);
280 struct i40e_vsi *vsi = np->vsi;
281 struct i40e_pf *pf = vsi->back;
282
283 pf->tx_timeout_count++;
284
285 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
327fe04b 286 pf->tx_timeout_recovery_level = 1;
41c445ff
JB		 287 pf->tx_timeout_last_recovery = jiffies;
288 netdev_info(netdev, "tx_timeout recovery level %d\n",
289 pf->tx_timeout_recovery_level);
290
291 switch (pf->tx_timeout_recovery_level) {
292 case 0:
293 /* disable and re-enable queues for the VSI */
294 if (in_interrupt()) {
295 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
296 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
297 } else {
298 i40e_vsi_reinit_locked(vsi);
299 }
300 break;
301 case 1:
302 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
303 break;
304 case 2:
305 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
306 break;
307 case 3:
308 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
309 break;
310 default:
311 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 312 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
313 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 314 break;
315 }
316 i40e_service_event_schedule(pf);
317 pf->tx_timeout_recovery_level++;
318}
319
320/**
321 * i40e_release_rx_desc - Store the new tail and head values
322 * @rx_ring: ring to bump
323 * @val: new head index
324 **/
325static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
326{
327 rx_ring->next_to_use = val;
328
329 /* Force memory writes to complete before letting h/w
330 * know there are new descriptors to fetch. (Only
331 * applicable for weak-ordered memory model archs,
332 * such as IA-64).
333 */
334 wmb();
335 writel(val, rx_ring->tail);
336}
337
338/**
339 * i40e_get_vsi_stats_struct - Get System Network Statistics
340 * @vsi: the VSI we care about
341 *
342 * Returns the address of the device statistics structure.
343 * The statistics are actually updated from the service task.
344 **/
345struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
346{
347 return &vsi->net_stats;
348}
349
350/**
351 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
352 * @netdev: network interface device structure
353 *
354 * Returns the address of the device statistics structure.
355 * The statistics are actually updated from the service task.
356 **/
38e00438
VD		 357#ifdef I40E_FCOE
358struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
359 struct net_device *netdev,
360 struct rtnl_link_stats64 *stats)
361#else
41c445ff
JB		 362static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
363 struct net_device *netdev,
980e9b11 364 struct rtnl_link_stats64 *stats)
38e00438 365#endif
41c445ff
JB		 366{
367 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 368 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 369 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 370 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
371 int i;
372
bc7d338f
ASJ		 373 if (test_bit(__I40E_DOWN, &vsi->state))
374 return stats;
375
3c325ced
JB		 376 if (!vsi->tx_rings)
377 return stats;
378
980e9b11
AD		 379 rcu_read_lock();
380 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 381 u64 bytes, packets;
382 unsigned int start;
383
384 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
385 if (!tx_ring)
386 continue;
387
388 do {
57a7744e 389 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 390 packets = tx_ring->stats.packets;
391 bytes = tx_ring->stats.bytes;
57a7744e 392 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 393
394 stats->tx_packets += packets;
395 stats->tx_bytes += bytes;
396 rx_ring = &tx_ring[1];
397
398 do {
57a7744e 399 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 400 packets = rx_ring->stats.packets;
401 bytes = rx_ring->stats.bytes;
57a7744e 402 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 403
980e9b11
AD		 404 stats->rx_packets += packets;
405 stats->rx_bytes += bytes;
406 }
407 rcu_read_unlock();
408
a5282f44 409 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 410 stats->multicast = vsi_stats->multicast;
411 stats->tx_errors = vsi_stats->tx_errors;
412 stats->tx_dropped = vsi_stats->tx_dropped;
413 stats->rx_errors = vsi_stats->rx_errors;
414 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
415 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 416
980e9b11 417 return stats;
41c445ff
JB		 418}
419
420/**
421 * i40e_vsi_reset_stats - Resets all stats of the given vsi
422 * @vsi: the VSI to have its stats reset
423 **/
424void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
425{
426 struct rtnl_link_stats64 *ns;
427 int i;
428
429 if (!vsi)
430 return;
431
432 ns = i40e_get_vsi_stats_struct(vsi);
433 memset(ns, 0, sizeof(*ns));
434 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
435 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
436 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 437 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 438 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 439 memset(&vsi->rx_rings[i]->stats, 0 ,
440 sizeof(vsi->rx_rings[i]->stats));
441 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
442 sizeof(vsi->rx_rings[i]->rx_stats));
443 memset(&vsi->tx_rings[i]->stats, 0 ,
444 sizeof(vsi->tx_rings[i]->stats));
445 memset(&vsi->tx_rings[i]->tx_stats, 0,
446 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 447 }
8e9dca53 448 }
41c445ff
JB		 449 vsi->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_pf_reset_stats - Reset all of the stats for the given pf
454 * @pf: the PF to be reset
455 **/
456void i40e_pf_reset_stats(struct i40e_pf *pf)
457{
e91fdf76
SN		 458 int i;
459
41c445ff
JB		 460 memset(&pf->stats, 0, sizeof(pf->stats));
461 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
462 pf->stat_offsets_loaded = false;
e91fdf76
SN		 463
464 for (i = 0; i < I40E_MAX_VEB; i++) {
465 if (pf->veb[i]) {
466 memset(&pf->veb[i]->stats, 0,
467 sizeof(pf->veb[i]->stats));
468 memset(&pf->veb[i]->stats_offsets, 0,
469 sizeof(pf->veb[i]->stats_offsets));
470 pf->veb[i]->stat_offsets_loaded = false;
471 }
472 }
41c445ff
JB		 473}
474
475/**
476 * i40e_stat_update48 - read and update a 48 bit stat from the chip
477 * @hw: ptr to the hardware info
478 * @hireg: the high 32 bit reg to read
479 * @loreg: the low 32 bit reg to read
480 * @offset_loaded: has the initial offset been loaded yet
481 * @offset: ptr to current offset value
482 * @stat: ptr to the stat
483 *
484 * Since the device stats are not reset at PFReset, they likely will not
485 * be zeroed when the driver starts. We'll save the first values read
486 * and use them as offsets to be subtracted from the raw values in order
487 * to report stats that count from zero. In the process, we also manage
488 * the potential roll-over.
489 **/
490static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
491 bool offset_loaded, u64 *offset, u64 *stat)
492{
493 u64 new_data;
494
ab60085e 495 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 496 new_data = rd32(hw, loreg);
497 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
498 } else {
499 new_data = rd64(hw, loreg);
500 }
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = new_data - *offset;
505 else
506 *stat = (new_data + ((u64)1 << 48)) - *offset;
507 *stat &= 0xFFFFFFFFFFFFULL;
508}
509
510/**
511 * i40e_stat_update32 - read and update a 32 bit stat from the chip
512 * @hw: ptr to the hardware info
513 * @reg: the hw reg to read
514 * @offset_loaded: has the initial offset been loaded yet
515 * @offset: ptr to current offset value
516 * @stat: ptr to the stat
517 **/
518static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
519 bool offset_loaded, u64 *offset, u64 *stat)
520{
521 u32 new_data;
522
523 new_data = rd32(hw, reg);
524 if (!offset_loaded)
525 *offset = new_data;
526 if (likely(new_data >= *offset))
527 *stat = (u32)(new_data - *offset);
528 else
529 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
530}
531
532/**
533 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
534 * @vsi: the VSI to be updated
535 **/
536void i40e_update_eth_stats(struct i40e_vsi *vsi)
537{
538 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
539 struct i40e_pf *pf = vsi->back;
540 struct i40e_hw *hw = &pf->hw;
541 struct i40e_eth_stats *oes;
542 struct i40e_eth_stats *es; /* device's eth stats */
543
544 es = &vsi->eth_stats;
545 oes = &vsi->eth_stats_offsets;
546
547 /* Gather up the stats that the hw collects */
548 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
549 vsi->stat_offsets_loaded,
550 &oes->tx_errors, &es->tx_errors);
551 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 554 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
555 vsi->stat_offsets_loaded,
556 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
557 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 560
561 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
562 I40E_GLV_GORCL(stat_idx),
563 vsi->stat_offsets_loaded,
564 &oes->rx_bytes, &es->rx_bytes);
565 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
566 I40E_GLV_UPRCL(stat_idx),
567 vsi->stat_offsets_loaded,
568 &oes->rx_unicast, &es->rx_unicast);
569 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
570 I40E_GLV_MPRCL(stat_idx),
571 vsi->stat_offsets_loaded,
572 &oes->rx_multicast, &es->rx_multicast);
573 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
574 I40E_GLV_BPRCL(stat_idx),
575 vsi->stat_offsets_loaded,
576 &oes->rx_broadcast, &es->rx_broadcast);
577
578 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
579 I40E_GLV_GOTCL(stat_idx),
580 vsi->stat_offsets_loaded,
581 &oes->tx_bytes, &es->tx_bytes);
582 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
583 I40E_GLV_UPTCL(stat_idx),
584 vsi->stat_offsets_loaded,
585 &oes->tx_unicast, &es->tx_unicast);
586 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
587 I40E_GLV_MPTCL(stat_idx),
588 vsi->stat_offsets_loaded,
589 &oes->tx_multicast, &es->tx_multicast);
590 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
591 I40E_GLV_BPTCL(stat_idx),
592 vsi->stat_offsets_loaded,
593 &oes->tx_broadcast, &es->tx_broadcast);
594 vsi->stat_offsets_loaded = true;
595}
596
597/**
598 * i40e_update_veb_stats - Update Switch component statistics
599 * @veb: the VEB being updated
600 **/
601static void i40e_update_veb_stats(struct i40e_veb *veb)
602{
603 struct i40e_pf *pf = veb->pf;
604 struct i40e_hw *hw = &pf->hw;
605 struct i40e_eth_stats *oes;
606 struct i40e_eth_stats *es; /* device's eth stats */
607 int idx = 0;
608
609 idx = veb->stats_idx;
610 es = &veb->stats;
611 oes = &veb->stats_offsets;
612
613 /* Gather up the stats that the hw collects */
614 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 617 if (hw->revision_id > 0)
618 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
619 veb->stat_offsets_loaded,
620 &oes->rx_unknown_protocol,
621 &es->rx_unknown_protocol);
41c445ff
JB		 622 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
623 veb->stat_offsets_loaded,
624 &oes->rx_bytes, &es->rx_bytes);
625 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
626 veb->stat_offsets_loaded,
627 &oes->rx_unicast, &es->rx_unicast);
628 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
629 veb->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
632 veb->stat_offsets_loaded,
633 &oes->rx_broadcast, &es->rx_broadcast);
634
635 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
636 veb->stat_offsets_loaded,
637 &oes->tx_bytes, &es->tx_bytes);
638 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
639 veb->stat_offsets_loaded,
640 &oes->tx_unicast, &es->tx_unicast);
641 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
642 veb->stat_offsets_loaded,
643 &oes->tx_multicast, &es->tx_multicast);
644 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
645 veb->stat_offsets_loaded,
646 &oes->tx_broadcast, &es->tx_broadcast);
647 veb->stat_offsets_loaded = true;
648}
649
38e00438
VD		 650#ifdef I40E_FCOE
651/**
652 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
653 * @vsi: the VSI that is capable of doing FCoE
654 **/
655static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
656{
657 struct i40e_pf *pf = vsi->back;
658 struct i40e_hw *hw = &pf->hw;
659 struct i40e_fcoe_stats *ofs;
660 struct i40e_fcoe_stats *fs; /* device's eth stats */
661 int idx;
662
663 if (vsi->type != I40E_VSI_FCOE)
664 return;
665
666 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
667 fs = &vsi->fcoe_stats;
668 ofs = &vsi->fcoe_stats_offsets;
669
670 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
671 vsi->fcoe_stat_offsets_loaded,
672 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
673 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
674 vsi->fcoe_stat_offsets_loaded,
675 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
676 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
677 vsi->fcoe_stat_offsets_loaded,
678 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
679 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
680 vsi->fcoe_stat_offsets_loaded,
681 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
682 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
683 vsi->fcoe_stat_offsets_loaded,
684 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
685 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
686 vsi->fcoe_stat_offsets_loaded,
687 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
688 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
689 vsi->fcoe_stat_offsets_loaded,
690 &ofs->fcoe_last_error, &fs->fcoe_last_error);
691 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
692 vsi->fcoe_stat_offsets_loaded,
693 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
694
695 vsi->fcoe_stat_offsets_loaded = true;
696}
697
698#endif
41c445ff
JB		 699/**
700 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
701 * @pf: the corresponding PF
702 *
703 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
704 **/
705static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
706{
707 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
708 struct i40e_hw_port_stats *nsd = &pf->stats;
709 struct i40e_hw *hw = &pf->hw;
710 u64 xoff = 0;
711 u16 i, v;
712
713 if ((hw->fc.current_mode != I40E_FC_FULL) &&
714 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
715 return;
716
717 xoff = nsd->link_xoff_rx;
718 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
719 pf->stat_offsets_loaded,
720 &osd->link_xoff_rx, &nsd->link_xoff_rx);
721
722 /* No new LFC xoff rx */
723 if (!(nsd->link_xoff_rx - xoff))
724 return;
725
726 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 727 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 728 struct i40e_vsi *vsi = pf->vsi[v];
729
ddfda80f 730 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 731 continue;
732
733 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 734 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 735 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
736 }
737 }
738}
739
740/**
741 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
742 * @pf: the corresponding PF
743 *
744 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
745 **/
746static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
747{
748 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
749 struct i40e_hw_port_stats *nsd = &pf->stats;
750 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
751 struct i40e_dcbx_config *dcb_cfg;
752 struct i40e_hw *hw = &pf->hw;
753 u16 i, v;
754 u8 tc;
755
756 dcb_cfg = &hw->local_dcbx_config;
757
758 /* See if DCB enabled with PFC TC */
759 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
760 !(dcb_cfg->pfc.pfcenable)) {
761 i40e_update_link_xoff_rx(pf);
762 return;
763 }
764
765 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
766 u64 prio_xoff = nsd->priority_xoff_rx[i];
767 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
768 pf->stat_offsets_loaded,
769 &osd->priority_xoff_rx[i],
770 &nsd->priority_xoff_rx[i]);
771
772 /* No new PFC xoff rx */
773 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
774 continue;
775 /* Get the TC for given priority */
776 tc = dcb_cfg->etscfg.prioritytable[i];
777 xoff[tc] = true;
778 }
779
780 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 781 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 782 struct i40e_vsi *vsi = pf->vsi[v];
783
ddfda80f 784 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 785 continue;
786
787 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 788 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 789
790 tc = ring->dcb_tc;
791 if (xoff[tc])
792 clear_bit(__I40E_HANG_CHECK_ARMED,
793 &ring->state);
794 }
795 }
796}
797
798/**
7812fddc 799 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 800 * @vsi: the VSI to be updated
801 *
802 * There are a few instances where we store the same stat in a
803 * couple of different structs. This is partly because we have
804 * the netdev stats that need to be filled out, which is slightly
805 * different from the "eth_stats" defined by the chip and used in
7812fddc 806 * VF communications. We sort it out here.
41c445ff 807 **/
7812fddc 808static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 809{
810 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 811 struct rtnl_link_stats64 *ons;
812 struct rtnl_link_stats64 *ns; /* netdev stats */
813 struct i40e_eth_stats *oes;
814 struct i40e_eth_stats *es; /* device's eth stats */
815 u32 tx_restart, tx_busy;
bf00b376 816 struct i40e_ring *p;
41c445ff 817 u32 rx_page, rx_buf;
bf00b376
AA		 818 u64 bytes, packets;
819 unsigned int start;
41c445ff
JB		 820 u64 rx_p, rx_b;
821 u64 tx_p, tx_b;
41c445ff
JB		 822 u16 q;
823
824 if (test_bit(__I40E_DOWN, &vsi->state) ||
825 test_bit(__I40E_CONFIG_BUSY, &pf->state))
826 return;
827
828 ns = i40e_get_vsi_stats_struct(vsi);
829 ons = &vsi->net_stats_offsets;
830 es = &vsi->eth_stats;
831 oes = &vsi->eth_stats_offsets;
832
833 /* Gather up the netdev and vsi stats that the driver collects
834 * on the fly during packet processing
835 */
836 rx_b = rx_p = 0;
837 tx_b = tx_p = 0;
838 tx_restart = tx_busy = 0;
839 rx_page = 0;
840 rx_buf = 0;
980e9b11 841 rcu_read_lock();
41c445ff 842 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 843 /* locate Tx ring */
844 p = ACCESS_ONCE(vsi->tx_rings[q]);
845
846 do {
57a7744e 847 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 848 packets = p->stats.packets;
849 bytes = p->stats.bytes;
57a7744e 850 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 851 tx_b += bytes;
852 tx_p += packets;
853 tx_restart += p->tx_stats.restart_queue;
854 tx_busy += p->tx_stats.tx_busy;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
871 vsi->rx_page_failed = rx_page;
872 vsi->rx_buf_failed = rx_buf;
873
874 ns->rx_packets = rx_p;
875 ns->rx_bytes = rx_b;
876 ns->tx_packets = tx_p;
877 ns->tx_bytes = tx_b;
878
41c445ff 879 /* update netdev stats from eth stats */
7812fddc 880 i40e_update_eth_stats(vsi);
41c445ff
JB		 881 ons->tx_errors = oes->tx_errors;
882 ns->tx_errors = es->tx_errors;
883 ons->multicast = oes->rx_multicast;
884 ns->multicast = es->rx_multicast;
41a9e55c
SN		 885 ons->rx_dropped = oes->rx_discards;
886 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 887 ons->tx_dropped = oes->tx_discards;
888 ns->tx_dropped = es->tx_discards;
889
7812fddc 890 /* pull in a couple PF stats if this is the main vsi */
41c445ff 891 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 892 ns->rx_crc_errors = pf->stats.crc_errors;
893 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
894 ns->rx_length_errors = pf->stats.rx_length_errors;
895 }
896}
41c445ff 897
7812fddc
SN		 898/**
899 * i40e_update_pf_stats - Update the pf statistics counters.
900 * @pf: the PF to be updated
901 **/
902static void i40e_update_pf_stats(struct i40e_pf *pf)
903{
904 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
905 struct i40e_hw_port_stats *nsd = &pf->stats;
906 struct i40e_hw *hw = &pf->hw;
907 u32 val;
908 int i;
41c445ff 909
7812fddc
SN		 910 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
911 I40E_GLPRT_GORCL(hw->port),
912 pf->stat_offsets_loaded,
913 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
914 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
915 I40E_GLPRT_GOTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
918 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_discards,
921 &nsd->eth.rx_discards);
922 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->eth.tx_discards,
925 &nsd->eth.tx_discards);
41c445ff 926
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
928 I40E_GLPRT_UPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_unicast,
931 &nsd->eth.rx_unicast);
7812fddc
SN		 932 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
933 I40E_GLPRT_MPRCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.rx_multicast,
936 &nsd->eth.rx_multicast);
532d283d
SN		 937 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
938 I40E_GLPRT_BPRCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.rx_broadcast,
941 &nsd->eth.rx_broadcast);
942 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
943 I40E_GLPRT_UPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_unicast,
946 &nsd->eth.tx_unicast);
947 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
948 I40E_GLPRT_MPTCL(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->eth.tx_multicast,
951 &nsd->eth.tx_multicast);
952 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
953 I40E_GLPRT_BPTCL(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->eth.tx_broadcast,
956 &nsd->eth.tx_broadcast);
41c445ff 957
7812fddc
SN		 958 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->tx_dropped_link_down,
961 &nsd->tx_dropped_link_down);
41c445ff 962
7812fddc
SN		 963 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->crc_errors, &nsd->crc_errors);
41c445ff 966
7812fddc
SN		 967 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 970
7812fddc
SN		 971 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->mac_local_faults,
974 &nsd->mac_local_faults);
975 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->mac_remote_faults,
978 &nsd->mac_remote_faults);
41c445ff 979
7812fddc
SN		 980 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
981 pf->stat_offsets_loaded,
982 &osd->rx_length_errors,
983 &nsd->rx_length_errors);
41c445ff 984
7812fddc
SN		 985 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_rx, &nsd->link_xon_rx);
988 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xon_tx, &nsd->link_xon_tx);
991 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
992 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
993 pf->stat_offsets_loaded,
994 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 995
7812fddc
SN		 996 for (i = 0; i < 8; i++) {
997 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_rx[i],
1000 &nsd->priority_xon_rx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xon_tx[i],
1004 &nsd->priority_xon_tx[i]);
1005 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1006 pf->stat_offsets_loaded,
7812fddc
SN		 1007 &osd->priority_xoff_tx[i],
1008 &nsd->priority_xoff_tx[i]);
1009 i40e_stat_update32(hw,
1010 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1011 pf->stat_offsets_loaded,
7812fddc
SN		 1012 &osd->priority_xon_2_xoff[i],
1013 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1014 }
1015
7812fddc
SN		 1016 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1017 I40E_GLPRT_PRC64L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_64, &nsd->rx_size_64);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1021 I40E_GLPRT_PRC127L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_127, &nsd->rx_size_127);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1025 I40E_GLPRT_PRC255L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_255, &nsd->rx_size_255);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1029 I40E_GLPRT_PRC511L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_511, &nsd->rx_size_511);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1033 I40E_GLPRT_PRC1023L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1023, &nsd->rx_size_1023);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1037 I40E_GLPRT_PRC1522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_1522, &nsd->rx_size_1522);
1040 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1041 I40E_GLPRT_PRC9522L(hw->port),
1042 pf->stat_offsets_loaded,
1043 &osd->rx_size_big, &nsd->rx_size_big);
1044
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1046 I40E_GLPRT_PTC64L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_64, &nsd->tx_size_64);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1050 I40E_GLPRT_PTC127L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_127, &nsd->tx_size_127);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1054 I40E_GLPRT_PTC255L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_255, &nsd->tx_size_255);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1058 I40E_GLPRT_PTC511L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_511, &nsd->tx_size_511);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1062 I40E_GLPRT_PTC1023L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1023, &nsd->tx_size_1023);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1066 I40E_GLPRT_PTC1522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_1522, &nsd->tx_size_1522);
1069 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1070 I40E_GLPRT_PTC9522L(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->tx_size_big, &nsd->tx_size_big);
1073
1074 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1075 pf->stat_offsets_loaded,
1076 &osd->rx_undersize, &nsd->rx_undersize);
1077 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_fragments, &nsd->rx_fragments);
1080 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_oversize, &nsd->rx_oversize);
1083 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_jabber, &nsd->rx_jabber);
1086
433c47de
ASJ		 1087 /* FDIR stats */
1088 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1089 pf->stat_offsets_loaded,
1090 &osd->fd_atr_match, &nsd->fd_atr_match);
1091 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1092 pf->stat_offsets_loaded,
1093 &osd->fd_sb_match, &nsd->fd_sb_match);
1094
7812fddc
SN		 1095 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1096 nsd->tx_lpi_status =
1097 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1098 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1099 nsd->rx_lpi_status =
1100 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1101 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1102 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1103 pf->stat_offsets_loaded,
1104 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1105 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1106 pf->stat_offsets_loaded,
1107 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1108
41c445ff
JB		 1109 pf->stat_offsets_loaded = true;
1110}
1111
7812fddc
SN		 1112/**
1113 * i40e_update_stats - Update the various statistics counters.
1114 * @vsi: the VSI to be updated
1115 *
1116 * Update the various stats for this VSI and its related entities.
1117 **/
1118void i40e_update_stats(struct i40e_vsi *vsi)
1119{
1120 struct i40e_pf *pf = vsi->back;
1121
1122 if (vsi == pf->vsi[pf->lan_vsi])
1123 i40e_update_pf_stats(pf);
1124
1125 i40e_update_vsi_stats(vsi);
38e00438
VD		 1126#ifdef I40E_FCOE
1127 i40e_update_fcoe_stats(vsi);
1128#endif
7812fddc
SN		 1129}
1130
41c445ff
JB		 1131/**
1132 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1133 * @vsi: the VSI to be searched
1134 * @macaddr: the MAC address
1135 * @vlan: the vlan
1136 * @is_vf: make sure its a vf filter, else doesn't matter
1137 * @is_netdev: make sure its a netdev filter, else doesn't matter
1138 *
1139 * Returns ptr to the filter object or NULL
1140 **/
1141static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1142 u8 *macaddr, s16 vlan,
1143 bool is_vf, bool is_netdev)
1144{
1145 struct i40e_mac_filter *f;
1146
1147 if (!vsi || !macaddr)
1148 return NULL;
1149
1150 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1151 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1152 (vlan == f->vlan) &&
1153 (!is_vf || f->is_vf) &&
1154 (!is_netdev || f->is_netdev))
1155 return f;
1156 }
1157 return NULL;
1158}
1159
1160/**
1161 * i40e_find_mac - Find a mac addr in the macvlan filters list
1162 * @vsi: the VSI to be searched
1163 * @macaddr: the MAC address we are searching for
1164 * @is_vf: make sure its a vf filter, else doesn't matter
1165 * @is_netdev: make sure its a netdev filter, else doesn't matter
1166 *
1167 * Returns the first filter with the provided MAC address or NULL if
1168 * MAC address was not found
1169 **/
1170struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1171 bool is_vf, bool is_netdev)
1172{
1173 struct i40e_mac_filter *f;
1174
1175 if (!vsi || !macaddr)
1176 return NULL;
1177
1178 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1179 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1180 (!is_vf || f->is_vf) &&
1181 (!is_netdev || f->is_netdev))
1182 return f;
1183 }
1184 return NULL;
1185}
1186
1187/**
1188 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1189 * @vsi: the VSI to be searched
1190 *
1191 * Returns true if VSI is in vlan mode or false otherwise
1192 **/
1193bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1194{
1195 struct i40e_mac_filter *f;
1196
1197 /* Only -1 for all the filters denotes not in vlan mode
1198 * so we have to go through all the list in order to make sure
1199 */
1200 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1201 if (f->vlan >= 0)
1202 return true;
1203 }
1204
1205 return false;
1206}
1207
1208/**
1209 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1210 * @vsi: the VSI to be searched
1211 * @macaddr: the mac address to be filtered
1212 * @is_vf: true if it is a vf
1213 * @is_netdev: true if it is a netdev
1214 *
1215 * Goes through all the macvlan filters and adds a
1216 * macvlan filter for each unique vlan that already exists
1217 *
1218 * Returns first filter found on success, else NULL
1219 **/
1220struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1221 bool is_vf, bool is_netdev)
1222{
1223 struct i40e_mac_filter *f;
1224
1225 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1226 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1227 is_vf, is_netdev)) {
1228 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1229 is_vf, is_netdev))
41c445ff
JB		 1230 return NULL;
1231 }
1232 }
1233
1234 return list_first_entry_or_null(&vsi->mac_filter_list,
1235 struct i40e_mac_filter, list);
1236}
1237
8c27d42e
GR		 1238/**
1239 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1240 * @vsi: the PF Main VSI - inappropriate for any other VSI
1241 * @macaddr: the MAC address
30650cc5
SN		 1242 *
1243 * Some older firmware configurations set up a default promiscuous VLAN
1244 * filter that needs to be removed.
8c27d42e 1245 **/
30650cc5 1246static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1247{
1248 struct i40e_aqc_remove_macvlan_element_data element;
1249 struct i40e_pf *pf = vsi->back;
1250 i40e_status aq_ret;
1251
1252 /* Only appropriate for the PF main VSI */
1253 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1254 return -EINVAL;
8c27d42e 1255
30650cc5 1256 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1257 ether_addr_copy(element.mac_addr, macaddr);
1258 element.vlan_tag = 0;
1259 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1260 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1261 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1262 if (aq_ret)
30650cc5
SN		 1263 return -ENOENT;
1264
1265 return 0;
8c27d42e
GR		 1266}
1267
41c445ff
JB		 1268/**
1269 * i40e_add_filter - Add a mac/vlan filter to the VSI
1270 * @vsi: the VSI to be searched
1271 * @macaddr: the MAC address
1272 * @vlan: the vlan
1273 * @is_vf: make sure its a vf filter, else doesn't matter
1274 * @is_netdev: make sure its a netdev filter, else doesn't matter
1275 *
1276 * Returns ptr to the filter object or NULL when no memory available.
1277 **/
1278struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1279 u8 *macaddr, s16 vlan,
1280 bool is_vf, bool is_netdev)
1281{
1282 struct i40e_mac_filter *f;
1283
1284 if (!vsi || !macaddr)
1285 return NULL;
1286
1287 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1288 if (!f) {
1289 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1290 if (!f)
1291 goto add_filter_out;
1292
9a173901 1293 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1294 f->vlan = vlan;
1295 f->changed = true;
1296
1297 INIT_LIST_HEAD(&f->list);
1298 list_add(&f->list, &vsi->mac_filter_list);
1299 }
1300
1301 /* increment counter and add a new flag if needed */
1302 if (is_vf) {
1303 if (!f->is_vf) {
1304 f->is_vf = true;
1305 f->counter++;
1306 }
1307 } else if (is_netdev) {
1308 if (!f->is_netdev) {
1309 f->is_netdev = true;
1310 f->counter++;
1311 }
1312 } else {
1313 f->counter++;
1314 }
1315
1316 /* changed tells sync_filters_subtask to
1317 * push the filter down to the firmware
1318 */
1319 if (f->changed) {
1320 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1321 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1322 }
1323
1324add_filter_out:
1325 return f;
1326}
1327
1328/**
1329 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1330 * @vsi: the VSI to be searched
1331 * @macaddr: the MAC address
1332 * @vlan: the vlan
1333 * @is_vf: make sure it's a vf filter, else doesn't matter
1334 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1335 **/
1336void i40e_del_filter(struct i40e_vsi *vsi,
1337 u8 *macaddr, s16 vlan,
1338 bool is_vf, bool is_netdev)
1339{
1340 struct i40e_mac_filter *f;
1341
1342 if (!vsi || !macaddr)
1343 return;
1344
1345 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1346 if (!f || f->counter == 0)
1347 return;
1348
1349 if (is_vf) {
1350 if (f->is_vf) {
1351 f->is_vf = false;
1352 f->counter--;
1353 }
1354 } else if (is_netdev) {
1355 if (f->is_netdev) {
1356 f->is_netdev = false;
1357 f->counter--;
1358 }
1359 } else {
1360 /* make sure we don't remove a filter in use by vf or netdev */
1361 int min_f = 0;
1362 min_f += (f->is_vf ? 1 : 0);
1363 min_f += (f->is_netdev ? 1 : 0);
1364
1365 if (f->counter > min_f)
1366 f->counter--;
1367 }
1368
1369 /* counter == 0 tells sync_filters_subtask to
1370 * remove the filter from the firmware's list
1371 */
1372 if (f->counter == 0) {
1373 f->changed = true;
1374 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1375 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1376 }
1377}
1378
1379/**
1380 * i40e_set_mac - NDO callback to set mac address
1381 * @netdev: network interface device structure
1382 * @p: pointer to an address structure
1383 *
1384 * Returns 0 on success, negative on failure
1385 **/
38e00438
VD		 1386#ifdef I40E_FCOE
1387int i40e_set_mac(struct net_device *netdev, void *p)
1388#else
41c445ff 1389static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1390#endif
41c445ff
JB		 1391{
1392 struct i40e_netdev_priv *np = netdev_priv(netdev);
1393 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1394 struct i40e_pf *pf = vsi->back;
1395 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1396 struct sockaddr *addr = p;
1397 struct i40e_mac_filter *f;
1398
1399 if (!is_valid_ether_addr(addr->sa_data))
1400 return -EADDRNOTAVAIL;
1401
30650cc5
SN		 1402 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1403 netdev_info(netdev, "already using mac address %pM\n",
1404 addr->sa_data);
1405 return 0;
1406 }
41c445ff 1407
80f6428f
ASJ		 1408 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1409 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1410 return -EADDRNOTAVAIL;
1411
30650cc5
SN		 1412 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1413 netdev_info(netdev, "returning to hw mac address %pM\n",
1414 hw->mac.addr);
1415 else
1416 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1417
41c445ff
JB		 1418 if (vsi->type == I40E_VSI_MAIN) {
1419 i40e_status ret;
1420 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1421 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1422 addr->sa_data, NULL);
1423 if (ret) {
1424 netdev_info(netdev,
1425 "Addr change for Main VSI failed: %d\n",
1426 ret);
1427 return -EADDRNOTAVAIL;
1428 }
41c445ff
JB		 1429 }
1430
30650cc5
SN		 1431 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1432 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1433
30650cc5
SN		 1434 memset(&element, 0, sizeof(element));
1435 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1436 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1437 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1438 } else {
6c8ad1ba
SN		 1439 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1440 false, false);
6c8ad1ba 1441 }
41c445ff 1442
30650cc5
SN		 1443 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1444 struct i40e_aqc_add_macvlan_element_data element;
1445
1446 memset(&element, 0, sizeof(element));
1447 ether_addr_copy(element.mac_addr, hw->mac.addr);
1448 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1449 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1450 } else {
1451 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1452 false, false);
1453 if (f)
1454 f->is_laa = true;
1455 }
1456
1457 i40e_sync_vsi_filters(vsi);
1458 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1459
1460 return 0;
1461}
1462
1463/**
1464 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1465 * @vsi: the VSI being setup
1466 * @ctxt: VSI context structure
1467 * @enabled_tc: Enabled TCs bitmap
1468 * @is_add: True if called before Add VSI
1469 *
1470 * Setup VSI queue mapping for enabled traffic classes.
1471 **/
38e00438
VD		 1472#ifdef I40E_FCOE
1473void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1474 struct i40e_vsi_context *ctxt,
1475 u8 enabled_tc,
1476 bool is_add)
1477#else
41c445ff
JB		 1478static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1479 struct i40e_vsi_context *ctxt,
1480 u8 enabled_tc,
1481 bool is_add)
38e00438 1482#endif
41c445ff
JB		 1483{
1484 struct i40e_pf *pf = vsi->back;
1485 u16 sections = 0;
1486 u8 netdev_tc = 0;
1487 u16 numtc = 0;
1488 u16 qcount;
1489 u8 offset;
1490 u16 qmap;
1491 int i;
4e3b35b0 1492 u16 num_tc_qps = 0;
41c445ff
JB		 1493
1494 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1495 offset = 0;
1496
1497 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1498 /* Find numtc from enabled TC bitmap */
1499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1500 if (enabled_tc & (1 << i)) /* TC is enabled */
1501 numtc++;
1502 }
1503 if (!numtc) {
1504 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1505 numtc = 1;
1506 }
1507 } else {
1508 /* At least TC0 is enabled in case of non-DCB case */
1509 numtc = 1;
1510 }
1511
1512 vsi->tc_config.numtc = numtc;
1513 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1514 /* Number of queues per enabled TC */
eb051afe 1515 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1516 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1517
1518 /* Setup queue offset/count for all TCs for given VSI */
1519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1520 /* See if the given TC is enabled for the given VSI */
1521 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1522 int pow, num_qps;
1523
41c445ff
JB		 1524 switch (vsi->type) {
1525 case I40E_VSI_MAIN:
4e3b35b0 1526 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff 1527 break;
38e00438
VD		 1528#ifdef I40E_FCOE
1529 case I40E_VSI_FCOE:
1530 qcount = num_tc_qps;
1531 break;
1532#endif
41c445ff
JB		 1533 case I40E_VSI_FDIR:
1534 case I40E_VSI_SRIOV:
1535 case I40E_VSI_VMDQ2:
1536 default:
4e3b35b0 1537 qcount = num_tc_qps;
41c445ff
JB		 1538 WARN_ON(i != 0);
1539 break;
1540 }
4e3b35b0
NP		 1541 vsi->tc_config.tc_info[i].qoffset = offset;
1542 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1543
1544 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1545 num_qps = qcount;
41c445ff 1546 pow = 0;
4e3b35b0 1547 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1548 pow++;
1549 num_qps >>= 1;
1550 }
1551
1552 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1553 qmap =
1554 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1555 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1556
4e3b35b0 1557 offset += qcount;
41c445ff
JB		 1558 } else {
1559 /* TC is not enabled so set the offset to
1560 * default queue and allocate one queue
1561 * for the given TC.
1562 */
1563 vsi->tc_config.tc_info[i].qoffset = 0;
1564 vsi->tc_config.tc_info[i].qcount = 1;
1565 vsi->tc_config.tc_info[i].netdev_tc = 0;
1566
1567 qmap = 0;
1568 }
1569 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1570 }
1571
1572 /* Set actual Tx/Rx queue pairs */
1573 vsi->num_queue_pairs = offset;
1574
1575 /* Scheduler section valid can only be set for ADD VSI */
1576 if (is_add) {
1577 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1578
1579 ctxt->info.up_enable_bits = enabled_tc;
1580 }
1581 if (vsi->type == I40E_VSI_SRIOV) {
1582 ctxt->info.mapping_flags |=
1583 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1584 for (i = 0; i < vsi->num_queue_pairs; i++)
1585 ctxt->info.queue_mapping[i] =
1586 cpu_to_le16(vsi->base_queue + i);
1587 } else {
1588 ctxt->info.mapping_flags |=
1589 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1590 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1591 }
1592 ctxt->info.valid_sections |= cpu_to_le16(sections);
1593}
1594
1595/**
1596 * i40e_set_rx_mode - NDO callback to set the netdev filters
1597 * @netdev: network interface device structure
1598 **/
38e00438
VD		 1599#ifdef I40E_FCOE
1600void i40e_set_rx_mode(struct net_device *netdev)
1601#else
41c445ff 1602static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1603#endif
41c445ff
JB		 1604{
1605 struct i40e_netdev_priv *np = netdev_priv(netdev);
1606 struct i40e_mac_filter *f, *ftmp;
1607 struct i40e_vsi *vsi = np->vsi;
1608 struct netdev_hw_addr *uca;
1609 struct netdev_hw_addr *mca;
1610 struct netdev_hw_addr *ha;
1611
1612 /* add addr if not already in the filter list */
1613 netdev_for_each_uc_addr(uca, netdev) {
1614 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1615 if (i40e_is_vsi_in_vlan(vsi))
1616 i40e_put_mac_in_vlan(vsi, uca->addr,
1617 false, true);
1618 else
1619 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1620 false, true);
1621 }
1622 }
1623
1624 netdev_for_each_mc_addr(mca, netdev) {
1625 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1626 if (i40e_is_vsi_in_vlan(vsi))
1627 i40e_put_mac_in_vlan(vsi, mca->addr,
1628 false, true);
1629 else
1630 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1631 false, true);
1632 }
1633 }
1634
1635 /* remove filter if not in netdev list */
1636 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1637 bool found = false;
1638
1639 if (!f->is_netdev)
1640 continue;
1641
1642 if (is_multicast_ether_addr(f->macaddr)) {
1643 netdev_for_each_mc_addr(mca, netdev) {
1644 if (ether_addr_equal(mca->addr, f->macaddr)) {
1645 found = true;
1646 break;
1647 }
1648 }
1649 } else {
1650 netdev_for_each_uc_addr(uca, netdev) {
1651 if (ether_addr_equal(uca->addr, f->macaddr)) {
1652 found = true;
1653 break;
1654 }
1655 }
1656
1657 for_each_dev_addr(netdev, ha) {
1658 if (ether_addr_equal(ha->addr, f->macaddr)) {
1659 found = true;
1660 break;
1661 }
1662 }
1663 }
1664 if (!found)
1665 i40e_del_filter(
1666 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1667 }
1668
1669 /* check for other flag changes */
1670 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1671 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1672 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1673 }
1674}
1675
1676/**
1677 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1678 * @vsi: ptr to the VSI
1679 *
1680 * Push any outstanding VSI filter changes through the AdminQ.
1681 *
1682 * Returns 0 or error value
1683 **/
1684int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1685{
1686 struct i40e_mac_filter *f, *ftmp;
1687 bool promisc_forced_on = false;
1688 bool add_happened = false;
1689 int filter_list_len = 0;
1690 u32 changed_flags = 0;
dcae29be 1691 i40e_status aq_ret = 0;
41c445ff
JB		 1692 struct i40e_pf *pf;
1693 int num_add = 0;
1694 int num_del = 0;
1695 u16 cmd_flags;
1696
1697 /* empty array typed pointers, kcalloc later */
1698 struct i40e_aqc_add_macvlan_element_data *add_list;
1699 struct i40e_aqc_remove_macvlan_element_data *del_list;
1700
1701 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1702 usleep_range(1000, 2000);
1703 pf = vsi->back;
1704
1705 if (vsi->netdev) {
1706 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1707 vsi->current_netdev_flags = vsi->netdev->flags;
1708 }
1709
1710 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1711 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1712
1713 filter_list_len = pf->hw.aq.asq_buf_size /
1714 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1715 del_list = kcalloc(filter_list_len,
1716 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1717 GFP_KERNEL);
1718 if (!del_list)
1719 return -ENOMEM;
1720
1721 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1722 if (!f->changed)
1723 continue;
1724
1725 if (f->counter != 0)
1726 continue;
1727 f->changed = false;
1728 cmd_flags = 0;
1729
1730 /* add to delete list */
9a173901 1731 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1732 del_list[num_del].vlan_tag =
1733 cpu_to_le16((u16)(f->vlan ==
1734 I40E_VLAN_ANY ? 0 : f->vlan));
1735
41c445ff
JB		 1736 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1737 del_list[num_del].flags = cmd_flags;
1738 num_del++;
1739
1740 /* unlink from filter list */
1741 list_del(&f->list);
1742 kfree(f);
1743
1744 /* flush a full buffer */
1745 if (num_del == filter_list_len) {
dcae29be 1746 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1747 vsi->seid, del_list, num_del,
1748 NULL);
1749 num_del = 0;
1750 memset(del_list, 0, sizeof(*del_list));
1751
fdfe9cbe
SN		 1752 if (aq_ret &&
1753 pf->hw.aq.asq_last_status !=
1754 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1755 dev_info(&pf->pdev->dev,
1756 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1757 aq_ret,
41c445ff
JB		 1758 pf->hw.aq.asq_last_status);
1759 }
1760 }
1761 if (num_del) {
dcae29be 1762 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1763 del_list, num_del, NULL);
1764 num_del = 0;
1765
fdfe9cbe
SN		 1766 if (aq_ret &&
1767 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1768 dev_info(&pf->pdev->dev,
1769 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1770 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1771 }
1772
1773 kfree(del_list);
1774 del_list = NULL;
1775
1776 /* do all the adds now */
1777 filter_list_len = pf->hw.aq.asq_buf_size /
1778 sizeof(struct i40e_aqc_add_macvlan_element_data),
1779 add_list = kcalloc(filter_list_len,
1780 sizeof(struct i40e_aqc_add_macvlan_element_data),
1781 GFP_KERNEL);
1782 if (!add_list)
1783 return -ENOMEM;
1784
1785 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1786 if (!f->changed)
1787 continue;
1788
1789 if (f->counter == 0)
1790 continue;
1791 f->changed = false;
1792 add_happened = true;
1793 cmd_flags = 0;
1794
1795 /* add to add array */
9a173901 1796 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1797 add_list[num_add].vlan_tag =
1798 cpu_to_le16(
1799 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1800 add_list[num_add].queue_number = 0;
1801
1802 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1803 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1804 num_add++;
1805
1806 /* flush a full buffer */
1807 if (num_add == filter_list_len) {
dcae29be
JB		 1808 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1809 add_list, num_add,
1810 NULL);
41c445ff
JB		 1811 num_add = 0;
1812
dcae29be 1813 if (aq_ret)
41c445ff
JB		 1814 break;
1815 memset(add_list, 0, sizeof(*add_list));
1816 }
1817 }
1818 if (num_add) {
dcae29be
JB		 1819 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1820 add_list, num_add, NULL);
41c445ff
JB		 1821 num_add = 0;
1822 }
1823 kfree(add_list);
1824 add_list = NULL;
1825
30650cc5
SN		 1826 if (add_happened && aq_ret &&
1827 pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
41c445ff
JB		 1828 dev_info(&pf->pdev->dev,
1829 "add filter failed, err %d, aq_err %d\n",
dcae29be 1830 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1831 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1832 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1833 &vsi->state)) {
1834 promisc_forced_on = true;
1835 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1836 &vsi->state);
1837 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1838 }
1839 }
1840 }
1841
1842 /* check for changes in promiscuous modes */
1843 if (changed_flags & IFF_ALLMULTI) {
1844 bool cur_multipromisc;
1845 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1846 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1847 vsi->seid,
1848 cur_multipromisc,
1849 NULL);
1850 if (aq_ret)
41c445ff
JB		 1851 dev_info(&pf->pdev->dev,
1852 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1853 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1854 }
1855 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1856 bool cur_promisc;
1857 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1858 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1859 &vsi->state));
dcae29be
JB		 1860 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1861 vsi->seid,
1862 cur_promisc, NULL);
1863 if (aq_ret)
41c445ff
JB		 1864 dev_info(&pf->pdev->dev,
1865 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1866 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1867 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1868 vsi->seid,
1869 cur_promisc, NULL);
1870 if (aq_ret)
1871 dev_info(&pf->pdev->dev,
1872 "set brdcast promisc failed, err %d, aq_err %d\n",
1873 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1874 }
1875
1876 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1877 return 0;
1878}
1879
1880/**
1881 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1882 * @pf: board private structure
1883 **/
1884static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1885{
1886 int v;
1887
1888 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1889 return;
1890 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1891
505682cd 1892 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1893 if (pf->vsi[v] &&
1894 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1895 i40e_sync_vsi_filters(pf->vsi[v]);
1896 }
1897}
1898
1899/**
1900 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1901 * @netdev: network interface device structure
1902 * @new_mtu: new value for maximum frame size
1903 *
1904 * Returns 0 on success, negative on failure
1905 **/
1906static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1907{
1908 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1909 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1910 struct i40e_vsi *vsi = np->vsi;
1911
1912 /* MTU < 68 is an error and causes problems on some kernels */
1913 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1914 return -EINVAL;
1915
1916 netdev_info(netdev, "changing MTU from %d to %d\n",
1917 netdev->mtu, new_mtu);
1918 netdev->mtu = new_mtu;
1919 if (netif_running(netdev))
1920 i40e_vsi_reinit_locked(vsi);
1921
1922 return 0;
1923}
1924
beb0dff1
JK		 1925/**
1926 * i40e_ioctl - Access the hwtstamp interface
1927 * @netdev: network interface device structure
1928 * @ifr: interface request data
1929 * @cmd: ioctl command
1930 **/
1931int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1932{
1933 struct i40e_netdev_priv *np = netdev_priv(netdev);
1934 struct i40e_pf *pf = np->vsi->back;
1935
1936 switch (cmd) {
1937 case SIOCGHWTSTAMP:
1938 return i40e_ptp_get_ts_config(pf, ifr);
1939 case SIOCSHWTSTAMP:
1940 return i40e_ptp_set_ts_config(pf, ifr);
1941 default:
1942 return -EOPNOTSUPP;
1943 }
1944}
1945
41c445ff
JB		 1946/**
1947 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1948 * @vsi: the vsi being adjusted
1949 **/
1950void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1951{
1952 struct i40e_vsi_context ctxt;
1953 i40e_status ret;
1954
1955 if ((vsi->info.valid_sections &
1956 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1957 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1958 return; /* already enabled */
1959
1960 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1961 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1962 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1963
1964 ctxt.seid = vsi->seid;
1965 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1966 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1967 if (ret) {
1968 dev_info(&vsi->back->pdev->dev,
1969 "%s: update vsi failed, aq_err=%d\n",
1970 __func__, vsi->back->hw.aq.asq_last_status);
1971 }
1972}
1973
1974/**
1975 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1976 * @vsi: the vsi being adjusted
1977 **/
1978void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1979{
1980 struct i40e_vsi_context ctxt;
1981 i40e_status ret;
1982
1983 if ((vsi->info.valid_sections &
1984 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1985 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1986 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1987 return; /* already disabled */
1988
1989 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1990 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1991 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1992
1993 ctxt.seid = vsi->seid;
1994 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1995 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1996 if (ret) {
1997 dev_info(&vsi->back->pdev->dev,
1998 "%s: update vsi failed, aq_err=%d\n",
1999 __func__, vsi->back->hw.aq.asq_last_status);
2000 }
2001}
2002
2003/**
2004 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2005 * @netdev: network interface to be adjusted
2006 * @features: netdev features to test if VLAN offload is enabled or not
2007 **/
2008static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2009{
2010 struct i40e_netdev_priv *np = netdev_priv(netdev);
2011 struct i40e_vsi *vsi = np->vsi;
2012
2013 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2014 i40e_vlan_stripping_enable(vsi);
2015 else
2016 i40e_vlan_stripping_disable(vsi);
2017}
2018
2019/**
2020 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2021 * @vsi: the vsi being configured
2022 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2023 **/
2024int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2025{
2026 struct i40e_mac_filter *f, *add_f;
2027 bool is_netdev, is_vf;
41c445ff
JB		 2028
2029 is_vf = (vsi->type == I40E_VSI_SRIOV);
2030 is_netdev = !!(vsi->netdev);
2031
2032 if (is_netdev) {
2033 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2034 is_vf, is_netdev);
2035 if (!add_f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add vlan filter %d for %pM\n",
2038 vid, vsi->netdev->dev_addr);
2039 return -ENOMEM;
2040 }
2041 }
2042
2043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2044 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2045 if (!add_f) {
2046 dev_info(&vsi->back->pdev->dev,
2047 "Could not add vlan filter %d for %pM\n",
2048 vid, f->macaddr);
2049 return -ENOMEM;
2050 }
2051 }
2052
41c445ff
JB		 2053 /* Now if we add a vlan tag, make sure to check if it is the first
2054 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2055 * with 0, so we now accept untagged and specified tagged traffic
2056 * (and not any taged and untagged)
2057 */
2058 if (vid > 0) {
2059 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2060 I40E_VLAN_ANY,
2061 is_vf, is_netdev)) {
2062 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2063 I40E_VLAN_ANY, is_vf, is_netdev);
2064 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2065 is_vf, is_netdev);
2066 if (!add_f) {
2067 dev_info(&vsi->back->pdev->dev,
2068 "Could not add filter 0 for %pM\n",
2069 vsi->netdev->dev_addr);
2070 return -ENOMEM;
2071 }
2072 }
8d82a7c5 2073 }
41c445ff 2074
8d82a7c5
GR		 2075 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2076 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 2077 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2078 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2079 is_vf, is_netdev)) {
2080 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2081 is_vf, is_netdev);
2082 add_f = i40e_add_filter(vsi, f->macaddr,
2083 0, is_vf, is_netdev);
2084 if (!add_f) {
2085 dev_info(&vsi->back->pdev->dev,
2086 "Could not add filter 0 for %pM\n",
2087 f->macaddr);
2088 return -ENOMEM;
2089 }
2090 }
2091 }
41c445ff
JB		 2092 }
2093
80f6428f
ASJ		 2094 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2095 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2096 return 0;
2097
2098 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 2099}
2100
2101/**
2102 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2103 * @vsi: the vsi being configured
2104 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2105 *
2106 * Return: 0 on success or negative otherwise
41c445ff
JB		 2107 **/
2108int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2109{
2110 struct net_device *netdev = vsi->netdev;
2111 struct i40e_mac_filter *f, *add_f;
2112 bool is_vf, is_netdev;
2113 int filter_count = 0;
41c445ff
JB		 2114
2115 is_vf = (vsi->type == I40E_VSI_SRIOV);
2116 is_netdev = !!(netdev);
2117
2118 if (is_netdev)
2119 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2120
2121 list_for_each_entry(f, &vsi->mac_filter_list, list)
2122 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2123
41c445ff
JB		 2124 /* go through all the filters for this VSI and if there is only
2125 * vid == 0 it means there are no other filters, so vid 0 must
2126 * be replaced with -1. This signifies that we should from now
2127 * on accept any traffic (with any tag present, or untagged)
2128 */
2129 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2130 if (is_netdev) {
2131 if (f->vlan &&
2132 ether_addr_equal(netdev->dev_addr, f->macaddr))
2133 filter_count++;
2134 }
2135
2136 if (f->vlan)
2137 filter_count++;
2138 }
2139
2140 if (!filter_count && is_netdev) {
2141 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2142 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2143 is_vf, is_netdev);
2144 if (!f) {
2145 dev_info(&vsi->back->pdev->dev,
2146 "Could not add filter %d for %pM\n",
2147 I40E_VLAN_ANY, netdev->dev_addr);
2148 return -ENOMEM;
2149 }
2150 }
2151
2152 if (!filter_count) {
2153 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2154 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2155 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2156 is_vf, is_netdev);
2157 if (!add_f) {
2158 dev_info(&vsi->back->pdev->dev,
2159 "Could not add filter %d for %pM\n",
2160 I40E_VLAN_ANY, f->macaddr);
2161 return -ENOMEM;
2162 }
2163 }
2164 }
2165
80f6428f
ASJ		 2166 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2167 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2168 return 0;
2169
41c445ff
JB		 2170 return i40e_sync_vsi_filters(vsi);
2171}
2172
2173/**
2174 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2175 * @netdev: network interface to be adjusted
2176 * @vid: vlan id to be added
078b5876
JB		 2177 *
2178 * net_device_ops implementation for adding vlan ids
41c445ff 2179 **/
38e00438
VD		 2180#ifdef I40E_FCOE
2181int i40e_vlan_rx_add_vid(struct net_device *netdev,
2182 __always_unused __be16 proto, u16 vid)
2183#else
41c445ff
JB		 2184static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2185 __always_unused __be16 proto, u16 vid)
38e00438 2186#endif
41c445ff
JB		 2187{
2188 struct i40e_netdev_priv *np = netdev_priv(netdev);
2189 struct i40e_vsi *vsi = np->vsi;
078b5876 2190 int ret = 0;
41c445ff
JB		 2191
2192 if (vid > 4095)
078b5876
JB		 2193 return -EINVAL;
2194
2195 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2196
6982d429
ASJ		 2197 /* If the network stack called us with vid = 0 then
2198 * it is asking to receive priority tagged packets with
2199 * vlan id 0. Our HW receives them by default when configured
2200 * to receive untagged packets so there is no need to add an
2201 * extra filter for vlan 0 tagged packets.
41c445ff 2202 */
6982d429
ASJ		 2203 if (vid)
2204 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2205
078b5876
JB		 2206 if (!ret && (vid < VLAN_N_VID))
2207 set_bit(vid, vsi->active_vlans);
41c445ff 2208
078b5876 2209 return ret;
41c445ff
JB		 2210}
2211
2212/**
2213 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2214 * @netdev: network interface to be adjusted
2215 * @vid: vlan id to be removed
078b5876 2216 *
fdfd943e 2217 * net_device_ops implementation for removing vlan ids
41c445ff 2218 **/
38e00438
VD		 2219#ifdef I40E_FCOE
2220int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2221 __always_unused __be16 proto, u16 vid)
2222#else
41c445ff
JB		 2223static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2224 __always_unused __be16 proto, u16 vid)
38e00438 2225#endif
41c445ff
JB		 2226{
2227 struct i40e_netdev_priv *np = netdev_priv(netdev);
2228 struct i40e_vsi *vsi = np->vsi;
2229
078b5876
JB		 2230 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2231
41c445ff
JB		 2232 /* return code is ignored as there is nothing a user
2233 * can do about failure to remove and a log message was
078b5876 2234 * already printed from the other function
41c445ff
JB		 2235 */
2236 i40e_vsi_kill_vlan(vsi, vid);
2237
2238 clear_bit(vid, vsi->active_vlans);
078b5876 2239
41c445ff
JB		 2240 return 0;
2241}
2242
2243/**
2244 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2245 * @vsi: the vsi being brought back up
2246 **/
2247static void i40e_restore_vlan(struct i40e_vsi *vsi)
2248{
2249 u16 vid;
2250
2251 if (!vsi->netdev)
2252 return;
2253
2254 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2255
2256 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2257 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2258 vid);
2259}
2260
2261/**
2262 * i40e_vsi_add_pvid - Add pvid for the VSI
2263 * @vsi: the vsi being adjusted
2264 * @vid: the vlan id to set as a PVID
2265 **/
dcae29be 2266int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2267{
2268 struct i40e_vsi_context ctxt;
dcae29be 2269 i40e_status aq_ret;
41c445ff
JB		 2270
2271 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2272 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2273 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2274 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2275 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2276
2277 ctxt.seid = vsi->seid;
2278 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2279 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2280 if (aq_ret) {
41c445ff
JB		 2281 dev_info(&vsi->back->pdev->dev,
2282 "%s: update vsi failed, aq_err=%d\n",
2283 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2284 return -ENOENT;
41c445ff
JB		 2285 }
2286
dcae29be 2287 return 0;
41c445ff
JB		 2288}
2289
2290/**
2291 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2292 * @vsi: the vsi being adjusted
2293 *
2294 * Just use the vlan_rx_register() service to put it back to normal
2295 **/
2296void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2297{
6c12fcbf
GR		 2298 i40e_vlan_stripping_disable(vsi);
2299
41c445ff 2300 vsi->info.pvid = 0;
41c445ff
JB		 2301}
2302
2303/**
2304 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2305 * @vsi: ptr to the VSI
2306 *
2307 * If this function returns with an error, then it's possible one or
2308 * more of the rings is populated (while the rest are not). It is the
2309 * callers duty to clean those orphaned rings.
2310 *
2311 * Return 0 on success, negative on failure
2312 **/
2313static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2314{
2315 int i, err = 0;
2316
2317 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2318 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2319
2320 return err;
2321}
2322
2323/**
2324 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2325 * @vsi: ptr to the VSI
2326 *
2327 * Free VSI's transmit software resources
2328 **/
2329static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2330{
2331 int i;
2332
8e9dca53
GR		 2333 if (!vsi->tx_rings)
2334 return;
2335
41c445ff 2336 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2337 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2338 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2339}
2340
2341/**
2342 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2343 * @vsi: ptr to the VSI
2344 *
2345 * If this function returns with an error, then it's possible one or
2346 * more of the rings is populated (while the rest are not). It is the
2347 * callers duty to clean those orphaned rings.
2348 *
2349 * Return 0 on success, negative on failure
2350 **/
2351static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2352{
2353 int i, err = 0;
2354
2355 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2356 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2357#ifdef I40E_FCOE
2358 i40e_fcoe_setup_ddp_resources(vsi);
2359#endif
41c445ff
JB		 2360 return err;
2361}
2362
2363/**
2364 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2365 * @vsi: ptr to the VSI
2366 *
2367 * Free all receive software resources
2368 **/
2369static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2370{
2371 int i;
2372
8e9dca53
GR		 2373 if (!vsi->rx_rings)
2374 return;
2375
41c445ff 2376 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2377 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2378 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2379#ifdef I40E_FCOE
2380 i40e_fcoe_free_ddp_resources(vsi);
2381#endif
41c445ff
JB		 2382}
2383
3ffa037d
NP		 2384/**
2385 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2386 * @ring: The Tx ring to configure
2387 *
2388 * This enables/disables XPS for a given Tx descriptor ring
2389 * based on the TCs enabled for the VSI that ring belongs to.
2390 **/
2391static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2392{
2393 struct i40e_vsi *vsi = ring->vsi;
2394 cpumask_var_t mask;
2395
2396 if (ring->q_vector && ring->netdev) {
2397 /* Single TC mode enable XPS */
2398 if (vsi->tc_config.numtc <= 1 &&
2399 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) {
2400 netif_set_xps_queue(ring->netdev,
2401 &ring->q_vector->affinity_mask,
2402 ring->queue_index);
2403 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2404 /* Disable XPS to allow selection based on TC */
2405 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2406 netif_set_xps_queue(ring->netdev, mask,
2407 ring->queue_index);
2408 free_cpumask_var(mask);
2409 }
2410 }
2411}
2412
41c445ff
JB		 2413/**
2414 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2415 * @ring: The Tx ring to configure
2416 *
2417 * Configure the Tx descriptor ring in the HMC context.
2418 **/
2419static int i40e_configure_tx_ring(struct i40e_ring *ring)
2420{
2421 struct i40e_vsi *vsi = ring->vsi;
2422 u16 pf_q = vsi->base_queue + ring->queue_index;
2423 struct i40e_hw *hw = &vsi->back->hw;
2424 struct i40e_hmc_obj_txq tx_ctx;
2425 i40e_status err = 0;
2426 u32 qtx_ctl = 0;
2427
2428 /* some ATR related tx ring init */
60ea5f83 2429 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2430 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2431 ring->atr_count = 0;
2432 } else {
2433 ring->atr_sample_rate = 0;
2434 }
2435
3ffa037d
NP		 2436 /* configure XPS */
2437 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2438
2439 /* clear the context structure first */
2440 memset(&tx_ctx, 0, sizeof(tx_ctx));
2441
2442 tx_ctx.new_context = 1;
2443 tx_ctx.base = (ring->dma / 128);
2444 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2445 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2446 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2447#ifdef I40E_FCOE
2448 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2449#endif
beb0dff1 2450 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2451 /* FDIR VSI tx ring can still use RS bit and writebacks */
2452 if (vsi->type != I40E_VSI_FDIR)
2453 tx_ctx.head_wb_ena = 1;
2454 tx_ctx.head_wb_addr = ring->dma +
2455 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2456
2457 /* As part of VSI creation/update, FW allocates certain
2458 * Tx arbitration queue sets for each TC enabled for
2459 * the VSI. The FW returns the handles to these queue
2460 * sets as part of the response buffer to Add VSI,
2461 * Update VSI, etc. AQ commands. It is expected that
2462 * these queue set handles be associated with the Tx
2463 * queues by the driver as part of the TX queue context
2464 * initialization. This has to be done regardless of
2465 * DCB as by default everything is mapped to TC0.
2466 */
2467 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2468 tx_ctx.rdylist_act = 0;
2469
2470 /* clear the context in the HMC */
2471 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2472 if (err) {
2473 dev_info(&vsi->back->pdev->dev,
2474 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2475 ring->queue_index, pf_q, err);
2476 return -ENOMEM;
2477 }
2478
2479 /* set the context in the HMC */
2480 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2481 if (err) {
2482 dev_info(&vsi->back->pdev->dev,
2483 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2484 ring->queue_index, pf_q, err);
2485 return -ENOMEM;
2486 }
2487
2488 /* Now associate this queue with this PCI function */
7a28d885 2489 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2490 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2491 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2492 I40E_QTX_CTL_VFVM_INDX_MASK;
2493 } else {
9d8bf547 2494 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2495 }
2496
13fd9774
SN		 2497 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2498 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2499 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2500 i40e_flush(hw);
2501
2502 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2503
2504 /* cache tail off for easier writes later */
2505 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2506
2507 return 0;
2508}
2509
2510/**
2511 * i40e_configure_rx_ring - Configure a receive ring context
2512 * @ring: The Rx ring to configure
2513 *
2514 * Configure the Rx descriptor ring in the HMC context.
2515 **/
2516static int i40e_configure_rx_ring(struct i40e_ring *ring)
2517{
2518 struct i40e_vsi *vsi = ring->vsi;
2519 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2520 u16 pf_q = vsi->base_queue + ring->queue_index;
2521 struct i40e_hw *hw = &vsi->back->hw;
2522 struct i40e_hmc_obj_rxq rx_ctx;
2523 i40e_status err = 0;
2524
2525 ring->state = 0;
2526
2527 /* clear the context structure first */
2528 memset(&rx_ctx, 0, sizeof(rx_ctx));
2529
2530 ring->rx_buf_len = vsi->rx_buf_len;
2531 ring->rx_hdr_len = vsi->rx_hdr_len;
2532
2533 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2534 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2535
2536 rx_ctx.base = (ring->dma / 128);
2537 rx_ctx.qlen = ring->count;
2538
2539 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2540 set_ring_16byte_desc_enabled(ring);
2541 rx_ctx.dsize = 0;
2542 } else {
2543 rx_ctx.dsize = 1;
2544 }
2545
2546 rx_ctx.dtype = vsi->dtype;
2547 if (vsi->dtype) {
2548 set_ring_ps_enabled(ring);
2549 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2550 I40E_RX_SPLIT_IP |
2551 I40E_RX_SPLIT_TCP_UDP |
2552 I40E_RX_SPLIT_SCTP;
2553 } else {
2554 rx_ctx.hsplit_0 = 0;
2555 }
2556
2557 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2558 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2559 if (hw->revision_id == 0)
2560 rx_ctx.lrxqthresh = 0;
2561 else
2562 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2563 rx_ctx.crcstrip = 1;
2564 rx_ctx.l2tsel = 1;
2565 rx_ctx.showiv = 1;
38e00438
VD		 2566#ifdef I40E_FCOE
2567 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2568#endif
acb3676b
CS		 2569 /* set the prefena field to 1 because the manual says to */
2570 rx_ctx.prefena = 1;
41c445ff
JB		 2571
2572 /* clear the context in the HMC */
2573 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2574 if (err) {
2575 dev_info(&vsi->back->pdev->dev,
2576 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2577 ring->queue_index, pf_q, err);
2578 return -ENOMEM;
2579 }
2580
2581 /* set the context in the HMC */
2582 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2583 if (err) {
2584 dev_info(&vsi->back->pdev->dev,
2585 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2586 ring->queue_index, pf_q, err);
2587 return -ENOMEM;
2588 }
2589
2590 /* cache tail for quicker writes, and clear the reg before use */
2591 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2592 writel(0, ring->tail);
2593
2594 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2595
2596 return 0;
2597}
2598
2599/**
2600 * i40e_vsi_configure_tx - Configure the VSI for Tx
2601 * @vsi: VSI structure describing this set of rings and resources
2602 *
2603 * Configure the Tx VSI for operation.
2604 **/
2605static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2606{
2607 int err = 0;
2608 u16 i;
2609
9f65e15b
AD		 2610 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2611 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2612
2613 return err;
2614}
2615
2616/**
2617 * i40e_vsi_configure_rx - Configure the VSI for Rx
2618 * @vsi: the VSI being configured
2619 *
2620 * Configure the Rx VSI for operation.
2621 **/
2622static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2623{
2624 int err = 0;
2625 u16 i;
2626
2627 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2628 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2629 + ETH_FCS_LEN + VLAN_HLEN;
2630 else
2631 vsi->max_frame = I40E_RXBUFFER_2048;
2632
2633 /* figure out correct receive buffer length */
2634 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2635 I40E_FLAG_RX_PS_ENABLED)) {
2636 case I40E_FLAG_RX_1BUF_ENABLED:
2637 vsi->rx_hdr_len = 0;
2638 vsi->rx_buf_len = vsi->max_frame;
2639 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2640 break;
2641 case I40E_FLAG_RX_PS_ENABLED:
2642 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2643 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2644 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2645 break;
2646 default:
2647 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2648 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2649 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2650 break;
2651 }
2652
38e00438
VD		 2653#ifdef I40E_FCOE
2654 /* setup rx buffer for FCoE */
2655 if ((vsi->type == I40E_VSI_FCOE) &&
2656 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2657 vsi->rx_hdr_len = 0;
2658 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2659 vsi->max_frame = I40E_RXBUFFER_3072;
2660 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2661 }
2662
2663#endif /* I40E_FCOE */
41c445ff
JB		 2664 /* round up for the chip's needs */
2665 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2666 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2667 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2668 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2669
2670 /* set up individual rings */
2671 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2672 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2673
2674 return err;
2675}
2676
2677/**
2678 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2679 * @vsi: ptr to the VSI
2680 **/
2681static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2682{
e7046ee1 2683 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2684 u16 qoffset, qcount;
2685 int i, n;
2686
2687 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2688 return;
2689
2690 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2691 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2692 continue;
2693
2694 qoffset = vsi->tc_config.tc_info[n].qoffset;
2695 qcount = vsi->tc_config.tc_info[n].qcount;
2696 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2697 rx_ring = vsi->rx_rings[i];
2698 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2699 rx_ring->dcb_tc = n;
2700 tx_ring->dcb_tc = n;
2701 }
2702 }
2703}
2704
2705/**
2706 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2707 * @vsi: ptr to the VSI
2708 **/
2709static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2710{
2711 if (vsi->netdev)
2712 i40e_set_rx_mode(vsi->netdev);
2713}
2714
17a73f6b
JG		 2715/**
2716 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2717 * @vsi: Pointer to the targeted VSI
2718 *
2719 * This function replays the hlist on the hw where all the SB Flow Director
2720 * filters were saved.
2721 **/
2722static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2723{
2724 struct i40e_fdir_filter *filter;
2725 struct i40e_pf *pf = vsi->back;
2726 struct hlist_node *node;
2727
55a5e60b
ASJ		 2728 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2729 return;
2730
17a73f6b
JG		 2731 hlist_for_each_entry_safe(filter, node,
2732 &pf->fdir_filter_list, fdir_node) {
2733 i40e_add_del_fdir(vsi, filter, true);
2734 }
2735}
2736
41c445ff
JB		 2737/**
2738 * i40e_vsi_configure - Set up the VSI for action
2739 * @vsi: the VSI being configured
2740 **/
2741static int i40e_vsi_configure(struct i40e_vsi *vsi)
2742{
2743 int err;
2744
2745 i40e_set_vsi_rx_mode(vsi);
2746 i40e_restore_vlan(vsi);
2747 i40e_vsi_config_dcb_rings(vsi);
2748 err = i40e_vsi_configure_tx(vsi);
2749 if (!err)
2750 err = i40e_vsi_configure_rx(vsi);
2751
2752 return err;
2753}
2754
2755/**
2756 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2757 * @vsi: the VSI being configured
2758 **/
2759static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2760{
2761 struct i40e_pf *pf = vsi->back;
2762 struct i40e_q_vector *q_vector;
2763 struct i40e_hw *hw = &pf->hw;
2764 u16 vector;
2765 int i, q;
2766 u32 val;
2767 u32 qp;
2768
2769 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2770 * and PFINT_LNKLSTn registers, e.g.:
2771 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2772 */
2773 qp = vsi->base_queue;
2774 vector = vsi->base_vector;
493fb300
AD		 2775 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2776 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2777 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2778 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2779 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2780 q_vector->rx.itr);
2781 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2782 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2783 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2784 q_vector->tx.itr);
2785
2786 /* Linked list for the queuepairs assigned to this vector */
2787 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2788 for (q = 0; q < q_vector->num_ringpairs; q++) {
2789 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2790 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2791 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2792 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2793 (I40E_QUEUE_TYPE_TX
2794 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2795
2796 wr32(hw, I40E_QINT_RQCTL(qp), val);
2797
2798 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2799 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2800 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2801 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2802 (I40E_QUEUE_TYPE_RX
2803 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2804
2805 /* Terminate the linked list */
2806 if (q == (q_vector->num_ringpairs - 1))
2807 val |= (I40E_QUEUE_END_OF_LIST
2808 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2809
2810 wr32(hw, I40E_QINT_TQCTL(qp), val);
2811 qp++;
2812 }
2813 }
2814
2815 i40e_flush(hw);
2816}
2817
2818/**
2819 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2820 * @hw: ptr to the hardware info
2821 **/
2822static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2823{
2824 u32 val;
2825
2826 /* clear things first */
2827 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2828 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2829
2830 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2831 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2832 I40E_PFINT_ICR0_ENA_GRST_MASK |
2833 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2834 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2835 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2836 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2837 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2838 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2839
2840 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2841
2842 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2843 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2844 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2845
2846 /* OTHER_ITR_IDX = 0 */
2847 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2848}
2849
2850/**
2851 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2852 * @vsi: the VSI being configured
2853 **/
2854static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2855{
493fb300 2856 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2857 struct i40e_pf *pf = vsi->back;
2858 struct i40e_hw *hw = &pf->hw;
2859 u32 val;
2860
2861 /* set the ITR configuration */
2862 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2863 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2864 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2865 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2866 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2867 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2868
2869 i40e_enable_misc_int_causes(hw);
2870
2871 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2872 wr32(hw, I40E_PFINT_LNKLST0, 0);
2873
f29eaa3d 2874 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2875 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2876 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2877 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2878
2879 wr32(hw, I40E_QINT_RQCTL(0), val);
2880
2881 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2882 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2883 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2884
2885 wr32(hw, I40E_QINT_TQCTL(0), val);
2886 i40e_flush(hw);
2887}
2888
2ef28cfb
MW		 2889/**
2890 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2891 * @pf: board private structure
2892 **/
2893void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2894{
2895 struct i40e_hw *hw = &pf->hw;
2896
2897 wr32(hw, I40E_PFINT_DYN_CTL0,
2898 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2899 i40e_flush(hw);
2900}
2901
41c445ff
JB		 2902/**
2903 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2904 * @pf: board private structure
2905 **/
116a57d4 2906void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2907{
2908 struct i40e_hw *hw = &pf->hw;
2909 u32 val;
2910
2911 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2912 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2913 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2914
2915 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2916 i40e_flush(hw);
2917}
2918
2919/**
2920 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2921 * @vsi: pointer to a vsi
2922 * @vector: enable a particular Hw Interrupt vector
2923 **/
2924void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2925{
2926 struct i40e_pf *pf = vsi->back;
2927 struct i40e_hw *hw = &pf->hw;
2928 u32 val;
2929
2930 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2931 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2932 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2933 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2934 /* skip the flush */
41c445ff
JB		 2935}
2936
5c2cebda
CW		 2937/**
2938 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
2939 * @vsi: pointer to a vsi
2940 * @vector: enable a particular Hw Interrupt vector
2941 **/
2942void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
2943{
2944 struct i40e_pf *pf = vsi->back;
2945 struct i40e_hw *hw = &pf->hw;
2946 u32 val;
2947
2948 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
2949 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
2950 i40e_flush(hw);
2951}
2952
41c445ff
JB		 2953/**
2954 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2955 * @irq: interrupt number
2956 * @data: pointer to a q_vector
2957 **/
2958static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2959{
2960 struct i40e_q_vector *q_vector = data;
2961
cd0b6fa6 2962 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2963 return IRQ_HANDLED;
2964
2965 napi_schedule(&q_vector->napi);
2966
2967 return IRQ_HANDLED;
2968}
2969
41c445ff
JB		 2970/**
2971 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2972 * @vsi: the VSI being configured
2973 * @basename: name for the vector
2974 *
2975 * Allocates MSI-X vectors and requests interrupts from the kernel.
2976 **/
2977static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2978{
2979 int q_vectors = vsi->num_q_vectors;
2980 struct i40e_pf *pf = vsi->back;
2981 int base = vsi->base_vector;
2982 int rx_int_idx = 0;
2983 int tx_int_idx = 0;
2984 int vector, err;
2985
2986 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2987 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2988
cd0b6fa6 2989 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2990 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2991 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2992 tx_int_idx++;
cd0b6fa6 2993 } else if (q_vector->rx.ring) {
41c445ff
JB		 2994 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2995 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2996 } else if (q_vector->tx.ring) {
41c445ff
JB		 2997 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2998 "%s-%s-%d", basename, "tx", tx_int_idx++);
2999 } else {
3000 /* skip this unused q_vector */
3001 continue;
3002 }
3003 err = request_irq(pf->msix_entries[base + vector].vector,
3004 vsi->irq_handler,
3005 0,
3006 q_vector->name,
3007 q_vector);
3008 if (err) {
3009 dev_info(&pf->pdev->dev,
3010 "%s: request_irq failed, error: %d\n",
3011 __func__, err);
3012 goto free_queue_irqs;
3013 }
3014 /* assign the mask for this irq */
3015 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3016 &q_vector->affinity_mask);
3017 }
3018
63741846 3019 vsi->irqs_ready = true;
41c445ff
JB		 3020 return 0;
3021
3022free_queue_irqs:
3023 while (vector) {
3024 vector--;
3025 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3026 NULL);
3027 free_irq(pf->msix_entries[base + vector].vector,
3028 &(vsi->q_vectors[vector]));
3029 }
3030 return err;
3031}
3032
3033/**
3034 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3035 * @vsi: the VSI being un-configured
3036 **/
3037static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3038{
3039 struct i40e_pf *pf = vsi->back;
3040 struct i40e_hw *hw = &pf->hw;
3041 int base = vsi->base_vector;
3042 int i;
3043
3044 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3045 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3046 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3047 }
3048
3049 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3050 for (i = vsi->base_vector;
3051 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3052 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3053
3054 i40e_flush(hw);
3055 for (i = 0; i < vsi->num_q_vectors; i++)
3056 synchronize_irq(pf->msix_entries[i + base].vector);
3057 } else {
3058 /* Legacy and MSI mode - this stops all interrupt handling */
3059 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3060 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3061 i40e_flush(hw);
3062 synchronize_irq(pf->pdev->irq);
3063 }
3064}
3065
3066/**
3067 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3068 * @vsi: the VSI being configured
3069 **/
3070static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3071{
3072 struct i40e_pf *pf = vsi->back;
3073 int i;
3074
3075 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3076 for (i = vsi->base_vector;
3077 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3078 i40e_irq_dynamic_enable(vsi, i);
3079 } else {
3080 i40e_irq_dynamic_enable_icr0(pf);
3081 }
3082
1022cb6c 3083 i40e_flush(&pf->hw);
41c445ff
JB		 3084 return 0;
3085}
3086
3087/**
3088 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3089 * @pf: board private structure
3090 **/
3091static void i40e_stop_misc_vector(struct i40e_pf *pf)
3092{
3093 /* Disable ICR 0 */
3094 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3095 i40e_flush(&pf->hw);
3096}
3097
3098/**
3099 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3100 * @irq: interrupt number
3101 * @data: pointer to a q_vector
3102 *
3103 * This is the handler used for all MSI/Legacy interrupts, and deals
3104 * with both queue and non-queue interrupts. This is also used in
3105 * MSIX mode to handle the non-queue interrupts.
3106 **/
3107static irqreturn_t i40e_intr(int irq, void *data)
3108{
3109 struct i40e_pf *pf = (struct i40e_pf *)data;
3110 struct i40e_hw *hw = &pf->hw;
5e823066 3111 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3112 u32 icr0, icr0_remaining;
3113 u32 val, ena_mask;
3114
3115 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3116 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3117
116a57d4
SN		 3118 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3119 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3120 goto enable_intr;
41c445ff 3121
cd92e72f
SN		 3122 /* if interrupt but no bits showing, must be SWINT */
3123 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3124 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3125 pf->sw_int_count++;
3126
41c445ff
JB		 3127 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3128 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3129
3130 /* temporarily disable queue cause for NAPI processing */
3131 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
3132 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3133 wr32(hw, I40E_QINT_RQCTL(0), qval);
3134
3135 qval = rd32(hw, I40E_QINT_TQCTL(0));
3136 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3137 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3138
3139 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 3140 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 3141 }
3142
3143 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3144 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3145 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3146 }
3147
3148 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3149 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3150 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3151 }
3152
3153 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3154 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3155 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3156 }
3157
3158 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3159 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3160 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3161 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3162 val = rd32(hw, I40E_GLGEN_RSTAT);
3163 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3164 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3165 if (val == I40E_RESET_CORER) {
41c445ff 3166 pf->corer_count++;
4eb3f768 3167 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3168 pf->globr_count++;
4eb3f768 3169 } else if (val == I40E_RESET_EMPR) {
41c445ff 3170 pf->empr_count++;
4eb3f768
SN		 3171 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
3172 }
41c445ff
JB		 3173 }
3174
9c010ee0
ASJ		 3175 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3176 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3177 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3178 }
3179
beb0dff1
JK		 3180 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3181 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3182
3183 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3184 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3185 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3186 }
beb0dff1
JK		 3187 }
3188
41c445ff
JB		 3189 /* If a critical error is pending we have no choice but to reset the
3190 * device.
3191 * Report and mask out any remaining unexpected interrupts.
3192 */
3193 icr0_remaining = icr0 & ena_mask;
3194 if (icr0_remaining) {
3195 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3196 icr0_remaining);
9c010ee0 3197 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3198 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3199 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3200 dev_info(&pf->pdev->dev, "device will be reset\n");
3201 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3202 i40e_service_event_schedule(pf);
41c445ff
JB		 3203 }
3204 ena_mask &= ~icr0_remaining;
3205 }
5e823066 3206 ret = IRQ_HANDLED;
41c445ff 3207
5e823066 3208enable_intr:
41c445ff
JB		 3209 /* re-enable interrupt causes */
3210 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3211 if (!test_bit(__I40E_DOWN, &pf->state)) {
3212 i40e_service_event_schedule(pf);
3213 i40e_irq_dynamic_enable_icr0(pf);
3214 }
3215
5e823066 3216 return ret;
41c445ff
JB		 3217}
3218
cbf61325
ASJ		 3219/**
3220 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3221 * @tx_ring: tx ring to clean
3222 * @budget: how many cleans we're allowed
3223 *
3224 * Returns true if there's any budget left (e.g. the clean is finished)
3225 **/
3226static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3227{
3228 struct i40e_vsi *vsi = tx_ring->vsi;
3229 u16 i = tx_ring->next_to_clean;
3230 struct i40e_tx_buffer *tx_buf;
3231 struct i40e_tx_desc *tx_desc;
3232
3233 tx_buf = &tx_ring->tx_bi[i];
3234 tx_desc = I40E_TX_DESC(tx_ring, i);
3235 i -= tx_ring->count;
3236
3237 do {
3238 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3239
3240 /* if next_to_watch is not set then there is no work pending */
3241 if (!eop_desc)
3242 break;
3243
3244 /* prevent any other reads prior to eop_desc */
3245 read_barrier_depends();
3246
3247 /* if the descriptor isn't done, no work yet to do */
3248 if (!(eop_desc->cmd_type_offset_bsz &
3249 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3250 break;
3251
3252 /* clear next_to_watch to prevent false hangs */
3253 tx_buf->next_to_watch = NULL;
3254
49d7d933
ASJ		 3255 tx_desc->buffer_addr = 0;
3256 tx_desc->cmd_type_offset_bsz = 0;
3257 /* move past filter desc */
3258 tx_buf++;
3259 tx_desc++;
3260 i++;
3261 if (unlikely(!i)) {
3262 i -= tx_ring->count;
3263 tx_buf = tx_ring->tx_bi;
3264 tx_desc = I40E_TX_DESC(tx_ring, 0);
3265 }
cbf61325
ASJ		 3266 /* unmap skb header data */
3267 dma_unmap_single(tx_ring->dev,
3268 dma_unmap_addr(tx_buf, dma),
3269 dma_unmap_len(tx_buf, len),
3270 DMA_TO_DEVICE);
49d7d933
ASJ		 3271 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3272 kfree(tx_buf->raw_buf);
cbf61325 3273
49d7d933
ASJ		 3274 tx_buf->raw_buf = NULL;
3275 tx_buf->tx_flags = 0;
3276 tx_buf->next_to_watch = NULL;
cbf61325 3277 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3278 tx_desc->buffer_addr = 0;
3279 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3280
49d7d933 3281 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3282 tx_buf++;
3283 tx_desc++;
3284 i++;
3285 if (unlikely(!i)) {
3286 i -= tx_ring->count;
3287 tx_buf = tx_ring->tx_bi;
3288 tx_desc = I40E_TX_DESC(tx_ring, 0);
3289 }
3290
3291 /* update budget accounting */
3292 budget--;
3293 } while (likely(budget));
3294
3295 i += tx_ring->count;
3296 tx_ring->next_to_clean = i;
3297
3298 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3299 i40e_irq_dynamic_enable(vsi,
3300 tx_ring->q_vector->v_idx + vsi->base_vector);
3301 }
3302 return budget > 0;
3303}
3304
3305/**
3306 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3307 * @irq: interrupt number
3308 * @data: pointer to a q_vector
3309 **/
3310static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3311{
3312 struct i40e_q_vector *q_vector = data;
3313 struct i40e_vsi *vsi;
3314
3315 if (!q_vector->tx.ring)
3316 return IRQ_HANDLED;
3317
3318 vsi = q_vector->tx.ring->vsi;
3319 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3320
3321 return IRQ_HANDLED;
3322}
3323
41c445ff 3324/**
cd0b6fa6 3325 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3326 * @vsi: the VSI being configured
3327 * @v_idx: vector index
cd0b6fa6 3328 * @qp_idx: queue pair index
41c445ff 3329 **/
cd0b6fa6 3330static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3331{
493fb300 3332 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3333 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3334 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3335
3336 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3337 tx_ring->next = q_vector->tx.ring;
3338 q_vector->tx.ring = tx_ring;
41c445ff 3339 q_vector->tx.count++;
cd0b6fa6
AD		 3340
3341 rx_ring->q_vector = q_vector;
3342 rx_ring->next = q_vector->rx.ring;
3343 q_vector->rx.ring = rx_ring;
3344 q_vector->rx.count++;
41c445ff
JB		 3345}
3346
3347/**
3348 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3349 * @vsi: the VSI being configured
3350 *
3351 * This function maps descriptor rings to the queue-specific vectors
3352 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3353 * one vector per queue pair, but on a constrained vector budget, we
3354 * group the queue pairs as "efficiently" as possible.
3355 **/
3356static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3357{
3358 int qp_remaining = vsi->num_queue_pairs;
3359 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3360 int num_ringpairs;
41c445ff
JB		 3361 int v_start = 0;
3362 int qp_idx = 0;
3363
3364 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3365 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3366 * It is also important to go through all the vectors available to be
3367 * sure that if we don't use all the vectors, that the remaining vectors
3368 * are cleared. This is especially important when decreasing the
3369 * number of queues in use.
41c445ff 3370 */
70114ec4 3371 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3372 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3373
3374 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3375
3376 q_vector->num_ringpairs = num_ringpairs;
3377
3378 q_vector->rx.count = 0;
3379 q_vector->tx.count = 0;
3380 q_vector->rx.ring = NULL;
3381 q_vector->tx.ring = NULL;
3382
3383 while (num_ringpairs--) {
3384 map_vector_to_qp(vsi, v_start, qp_idx);
3385 qp_idx++;
3386 qp_remaining--;
41c445ff
JB		 3387 }
3388 }
3389}
3390
3391/**
3392 * i40e_vsi_request_irq - Request IRQ from the OS
3393 * @vsi: the VSI being configured
3394 * @basename: name for the vector
3395 **/
3396static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3397{
3398 struct i40e_pf *pf = vsi->back;
3399 int err;
3400
3401 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3402 err = i40e_vsi_request_irq_msix(vsi, basename);
3403 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3404 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3405 pf->misc_int_name, pf);
3406 else
3407 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3408 pf->misc_int_name, pf);
3409
3410 if (err)
3411 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3412
3413 return err;
3414}
3415
3416#ifdef CONFIG_NET_POLL_CONTROLLER
3417/**
3418 * i40e_netpoll - A Polling 'interrupt'handler
3419 * @netdev: network interface device structure
3420 *
3421 * This is used by netconsole to send skbs without having to re-enable
3422 * interrupts. It's not called while the normal interrupt routine is executing.
3423 **/
38e00438
VD		 3424#ifdef I40E_FCOE
3425void i40e_netpoll(struct net_device *netdev)
3426#else
41c445ff 3427static void i40e_netpoll(struct net_device *netdev)
38e00438 3428#endif
41c445ff
JB		 3429{
3430 struct i40e_netdev_priv *np = netdev_priv(netdev);
3431 struct i40e_vsi *vsi = np->vsi;
3432 struct i40e_pf *pf = vsi->back;
3433 int i;
3434
3435 /* if interface is down do nothing */
3436 if (test_bit(__I40E_DOWN, &vsi->state))
3437 return;
3438
3439 pf->flags |= I40E_FLAG_IN_NETPOLL;
3440 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3441 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3442 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3443 } else {
3444 i40e_intr(pf->pdev->irq, netdev);
3445 }
3446 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3447}
3448#endif
3449
23527308
NP		 3450/**
3451 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3452 * @pf: the PF being configured
3453 * @pf_q: the PF queue
3454 * @enable: enable or disable state of the queue
3455 *
3456 * This routine will wait for the given Tx queue of the PF to reach the
3457 * enabled or disabled state.
3458 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3459 * multiple retries; else will return 0 in case of success.
3460 **/
3461static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3462{
3463 int i;
3464 u32 tx_reg;
3465
3466 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3467 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3468 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3469 break;
3470
f98a2006 3471 usleep_range(10, 20);
23527308
NP		 3472 }
3473 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3474 return -ETIMEDOUT;
3475
3476 return 0;
3477}
3478
41c445ff
JB		 3479/**
3480 * i40e_vsi_control_tx - Start or stop a VSI's rings
3481 * @vsi: the VSI being configured
3482 * @enable: start or stop the rings
3483 **/
3484static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3485{
3486 struct i40e_pf *pf = vsi->back;
3487 struct i40e_hw *hw = &pf->hw;
23527308 3488 int i, j, pf_q, ret = 0;
41c445ff
JB		 3489 u32 tx_reg;
3490
3491 pf_q = vsi->base_queue;
3492 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3493
3494 /* warn the TX unit of coming changes */
3495 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3496 if (!enable)
f98a2006 3497 usleep_range(10, 20);
351499ab 3498
6c5ef620 3499 for (j = 0; j < 50; j++) {
41c445ff 3500 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3501 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3502 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3503 break;
3504 usleep_range(1000, 2000);
3505 }
fda972f6 3506 /* Skip if the queue is already in the requested state */
7c122007 3507 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3508 continue;
41c445ff
JB		 3509
3510 /* turn on/off the queue */
c5c9eb9e
SN		 3511 if (enable) {
3512 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3513 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3514 } else {
41c445ff 3515 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3516 }
41c445ff
JB		 3517
3518 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3519 /* No waiting for the Tx queue to disable */
3520 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3521 continue;
41c445ff
JB		 3522
3523 /* wait for the change to finish */
23527308
NP		 3524 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3525 if (ret) {
3526 dev_info(&pf->pdev->dev,
3527 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3528 __func__, vsi->seid, pf_q,
3529 (enable ? "en" : "dis"));
3530 break;
41c445ff
JB		 3531 }
3532 }
3533
7134f9ce
JB		 3534 if (hw->revision_id == 0)
3535 mdelay(50);
23527308
NP		 3536 return ret;
3537}
3538
3539/**
3540 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3541 * @pf: the PF being configured
3542 * @pf_q: the PF queue
3543 * @enable: enable or disable state of the queue
3544 *
3545 * This routine will wait for the given Rx queue of the PF to reach the
3546 * enabled or disabled state.
3547 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3548 * multiple retries; else will return 0 in case of success.
3549 **/
3550static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3551{
3552 int i;
3553 u32 rx_reg;
3554
3555 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3556 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3557 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3558 break;
3559
f98a2006 3560 usleep_range(10, 20);
23527308
NP		 3561 }
3562 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3563 return -ETIMEDOUT;
7134f9ce 3564
41c445ff
JB		 3565 return 0;
3566}
3567
3568/**
3569 * i40e_vsi_control_rx - Start or stop a VSI's rings
3570 * @vsi: the VSI being configured
3571 * @enable: start or stop the rings
3572 **/
3573static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3574{
3575 struct i40e_pf *pf = vsi->back;
3576 struct i40e_hw *hw = &pf->hw;
23527308 3577 int i, j, pf_q, ret = 0;
41c445ff
JB		 3578 u32 rx_reg;
3579
3580 pf_q = vsi->base_queue;
3581 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3582 for (j = 0; j < 50; j++) {
41c445ff 3583 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3584 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3585 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3586 break;
3587 usleep_range(1000, 2000);
3588 }
41c445ff 3589
7c122007
CS		 3590 /* Skip if the queue is already in the requested state */
3591 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3592 continue;
41c445ff
JB		 3593
3594 /* turn on/off the queue */
3595 if (enable)
6c5ef620 3596 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3597 else
6c5ef620 3598 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3599 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3600
3601 /* wait for the change to finish */
23527308
NP		 3602 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3603 if (ret) {
3604 dev_info(&pf->pdev->dev,
3605 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3606 __func__, vsi->seid, pf_q,
3607 (enable ? "en" : "dis"));
3608 break;
41c445ff
JB		 3609 }
3610 }
3611
23527308 3612 return ret;
41c445ff
JB		 3613}
3614
3615/**
3616 * i40e_vsi_control_rings - Start or stop a VSI's rings
3617 * @vsi: the VSI being configured
3618 * @enable: start or stop the rings
3619 **/
fc18eaa0 3620int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3621{
3b867b28 3622 int ret = 0;
41c445ff
JB		 3623
3624 /* do rx first for enable and last for disable */
3625 if (request) {
3626 ret = i40e_vsi_control_rx(vsi, request);
3627 if (ret)
3628 return ret;
3629 ret = i40e_vsi_control_tx(vsi, request);
3630 } else {
3b867b28
ASJ		 3631 /* Ignore return value, we need to shutdown whatever we can */
3632 i40e_vsi_control_tx(vsi, request);
3633 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3634 }
3635
3636 return ret;
3637}
3638
3639/**
3640 * i40e_vsi_free_irq - Free the irq association with the OS
3641 * @vsi: the VSI being configured
3642 **/
3643static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3644{
3645 struct i40e_pf *pf = vsi->back;
3646 struct i40e_hw *hw = &pf->hw;
3647 int base = vsi->base_vector;
3648 u32 val, qp;
3649 int i;
3650
3651 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3652 if (!vsi->q_vectors)
3653 return;
3654
63741846
SN		 3655 if (!vsi->irqs_ready)
3656 return;
3657
3658 vsi->irqs_ready = false;
41c445ff
JB		 3659 for (i = 0; i < vsi->num_q_vectors; i++) {
3660 u16 vector = i + base;
3661
3662 /* free only the irqs that were actually requested */
78681b1f
SN		 3663 if (!vsi->q_vectors[i] ||
3664 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3665 continue;
3666
3667 /* clear the affinity_mask in the IRQ descriptor */
3668 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3669 NULL);
3670 free_irq(pf->msix_entries[vector].vector,
493fb300 3671 vsi->q_vectors[i]);
41c445ff
JB		 3672
3673 /* Tear down the interrupt queue link list
3674 *
3675 * We know that they come in pairs and always
3676 * the Rx first, then the Tx. To clear the
3677 * link list, stick the EOL value into the
3678 * next_q field of the registers.
3679 */
3680 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3681 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3682 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3683 val |= I40E_QUEUE_END_OF_LIST
3684 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3685 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3686
3687 while (qp != I40E_QUEUE_END_OF_LIST) {
3688 u32 next;
3689
3690 val = rd32(hw, I40E_QINT_RQCTL(qp));
3691
3692 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3693 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3694 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3695 I40E_QINT_RQCTL_INTEVENT_MASK);
3696
3697 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3698 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3699
3700 wr32(hw, I40E_QINT_RQCTL(qp), val);
3701
3702 val = rd32(hw, I40E_QINT_TQCTL(qp));
3703
3704 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3705 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3706
3707 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3708 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3709 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3710 I40E_QINT_TQCTL_INTEVENT_MASK);
3711
3712 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3713 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3714
3715 wr32(hw, I40E_QINT_TQCTL(qp), val);
3716 qp = next;
3717 }
3718 }
3719 } else {
3720 free_irq(pf->pdev->irq, pf);
3721
3722 val = rd32(hw, I40E_PFINT_LNKLST0);
3723 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3724 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3725 val |= I40E_QUEUE_END_OF_LIST
3726 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3727 wr32(hw, I40E_PFINT_LNKLST0, val);
3728
3729 val = rd32(hw, I40E_QINT_RQCTL(qp));
3730 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3731 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3732 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3733 I40E_QINT_RQCTL_INTEVENT_MASK);
3734
3735 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3736 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3737
3738 wr32(hw, I40E_QINT_RQCTL(qp), val);
3739
3740 val = rd32(hw, I40E_QINT_TQCTL(qp));
3741
3742 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3743 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3744 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3745 I40E_QINT_TQCTL_INTEVENT_MASK);
3746
3747 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3748 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3749
3750 wr32(hw, I40E_QINT_TQCTL(qp), val);
3751 }
3752}
3753
493fb300
AD		 3754/**
3755 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3756 * @vsi: the VSI being configured
3757 * @v_idx: Index of vector to be freed
3758 *
3759 * This function frees the memory allocated to the q_vector. In addition if
3760 * NAPI is enabled it will delete any references to the NAPI struct prior
3761 * to freeing the q_vector.
3762 **/
3763static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3764{
3765 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3766 struct i40e_ring *ring;
493fb300
AD		 3767
3768 if (!q_vector)
3769 return;
3770
3771 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3772 i40e_for_each_ring(ring, q_vector->tx)
3773 ring->q_vector = NULL;
3774
3775 i40e_for_each_ring(ring, q_vector->rx)
3776 ring->q_vector = NULL;
493fb300
AD		 3777
3778 /* only VSI w/ an associated netdev is set up w/ NAPI */
3779 if (vsi->netdev)
3780 netif_napi_del(&q_vector->napi);
3781
3782 vsi->q_vectors[v_idx] = NULL;
3783
3784 kfree_rcu(q_vector, rcu);
3785}
3786
41c445ff
JB		 3787/**
3788 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3789 * @vsi: the VSI being un-configured
3790 *
3791 * This frees the memory allocated to the q_vectors and
3792 * deletes references to the NAPI struct.
3793 **/
3794static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3795{
3796 int v_idx;
3797
493fb300
AD		 3798 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3799 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3800}
3801
3802/**
3803 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3804 * @pf: board private structure
3805 **/
3806static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3807{
3808 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3809 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3810 pci_disable_msix(pf->pdev);
3811 kfree(pf->msix_entries);
3812 pf->msix_entries = NULL;
3813 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3814 pci_disable_msi(pf->pdev);
3815 }
3816 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3817}
3818
3819/**
3820 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3821 * @pf: board private structure
3822 *
3823 * We go through and clear interrupt specific resources and reset the structure
3824 * to pre-load conditions
3825 **/
3826static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3827{
3828 int i;
3829
3830 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3831 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3832 if (pf->vsi[i])
3833 i40e_vsi_free_q_vectors(pf->vsi[i]);
3834 i40e_reset_interrupt_capability(pf);
3835}
3836
3837/**
3838 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3839 * @vsi: the VSI being configured
3840 **/
3841static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3842{
3843 int q_idx;
3844
3845 if (!vsi->netdev)
3846 return;
3847
3848 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3849 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3850}
3851
3852/**
3853 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3854 * @vsi: the VSI being configured
3855 **/
3856static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3857{
3858 int q_idx;
3859
3860 if (!vsi->netdev)
3861 return;
3862
3863 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3864 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3865}
3866
90ef8d47
SN		 3867/**
3868 * i40e_vsi_close - Shut down a VSI
3869 * @vsi: the vsi to be quelled
3870 **/
3871static void i40e_vsi_close(struct i40e_vsi *vsi)
3872{
3873 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3874 i40e_down(vsi);
3875 i40e_vsi_free_irq(vsi);
3876 i40e_vsi_free_tx_resources(vsi);
3877 i40e_vsi_free_rx_resources(vsi);
3878}
3879
41c445ff
JB		 3880/**
3881 * i40e_quiesce_vsi - Pause a given VSI
3882 * @vsi: the VSI being paused
3883 **/
3884static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3885{
3886 if (test_bit(__I40E_DOWN, &vsi->state))
3887 return;
3888
d341b7a5
NP		 3889 /* No need to disable FCoE VSI when Tx suspended */
3890 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
3891 vsi->type == I40E_VSI_FCOE) {
3892 dev_dbg(&vsi->back->pdev->dev,
3893 "%s: VSI seid %d skipping FCoE VSI disable\n",
3894 __func__, vsi->seid);
3895 return;
3896 }
3897
41c445ff
JB		 3898 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3899 if (vsi->netdev && netif_running(vsi->netdev)) {
3900 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3901 } else {
90ef8d47 3902 i40e_vsi_close(vsi);
41c445ff
JB		 3903 }
3904}
3905
3906/**
3907 * i40e_unquiesce_vsi - Resume a given VSI
3908 * @vsi: the VSI being resumed
3909 **/
3910static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3911{
3912 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3913 return;
3914
3915 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3916 if (vsi->netdev && netif_running(vsi->netdev))
3917 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3918 else
8276f757 3919 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3920}
3921
3922/**
3923 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3924 * @pf: the PF
3925 **/
3926static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3927{
3928 int v;
3929
505682cd 3930 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3931 if (pf->vsi[v])
3932 i40e_quiesce_vsi(pf->vsi[v]);
3933 }
3934}
3935
3936/**
3937 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3938 * @pf: the PF
3939 **/
3940static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3941{
3942 int v;
3943
505682cd 3944 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3945 if (pf->vsi[v])
3946 i40e_unquiesce_vsi(pf->vsi[v]);
3947 }
3948}
3949
69129dc3
NP		 3950#ifdef CONFIG_I40E_DCB
3951/**
3952 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
3953 * @vsi: the VSI being configured
3954 *
3955 * This function waits for the given VSI's Tx queues to be disabled.
3956 **/
3957static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
3958{
3959 struct i40e_pf *pf = vsi->back;
3960 int i, pf_q, ret;
3961
3962 pf_q = vsi->base_queue;
3963 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3964 /* Check and wait for the disable status of the queue */
3965 ret = i40e_pf_txq_wait(pf, pf_q, false);
3966 if (ret) {
3967 dev_info(&pf->pdev->dev,
3968 "%s: VSI seid %d Tx ring %d disable timeout\n",
3969 __func__, vsi->seid, pf_q);
3970 return ret;
3971 }
3972 }
3973
3974 return 0;
3975}
3976
3977/**
3978 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
3979 * @pf: the PF
3980 *
3981 * This function waits for the Tx queues to be in disabled state for all the
3982 * VSIs that are managed by this PF.
3983 **/
3984static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
3985{
3986 int v, ret = 0;
3987
3988 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 3989 /* No need to wait for FCoE VSI queues */
3990 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 3991 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
3992 if (ret)
3993 break;
3994 }
3995 }
3996
3997 return ret;
3998}
3999
4000#endif
41c445ff
JB		 4001/**
4002 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4003 * @dcbcfg: the corresponding DCBx configuration structure
4004 *
4005 * Return the number of TCs from given DCBx configuration
4006 **/
4007static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4008{
078b5876
JB		 4009 u8 num_tc = 0;
4010 int i;
41c445ff
JB		 4011
4012 /* Scan the ETS Config Priority Table to find
4013 * traffic class enabled for a given priority
4014 * and use the traffic class index to get the
4015 * number of traffic classes enabled
4016 */
4017 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4018 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4019 num_tc = dcbcfg->etscfg.prioritytable[i];
4020 }
4021
4022 /* Traffic class index starts from zero so
4023 * increment to return the actual count
4024 */
078b5876 4025 return num_tc + 1;
41c445ff
JB		 4026}
4027
4028/**
4029 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4030 * @dcbcfg: the corresponding DCBx configuration structure
4031 *
4032 * Query the current DCB configuration and return the number of
4033 * traffic classes enabled from the given DCBX config
4034 **/
4035static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4036{
4037 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4038 u8 enabled_tc = 1;
4039 u8 i;
4040
4041 for (i = 0; i < num_tc; i++)
4042 enabled_tc |= 1 << i;
4043
4044 return enabled_tc;
4045}
4046
4047/**
4048 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4049 * @pf: PF being queried
4050 *
4051 * Return number of traffic classes enabled for the given PF
4052 **/
4053static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4054{
4055 struct i40e_hw *hw = &pf->hw;
4056 u8 i, enabled_tc;
4057 u8 num_tc = 0;
4058 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4059
4060 /* If DCB is not enabled then always in single TC */
4061 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4062 return 1;
4063
4064 /* MFP mode return count of enabled TCs for this PF */
4065 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4066 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4067 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4068 if (enabled_tc & (1 << i))
4069 num_tc++;
4070 }
4071 return num_tc;
4072 }
4073
4074 /* SFP mode will be enabled for all TCs on port */
4075 return i40e_dcb_get_num_tc(dcbcfg);
4076}
4077
4078/**
4079 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4080 * @pf: PF being queried
4081 *
4082 * Return a bitmap for first enabled traffic class for this PF.
4083 **/
4084static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4085{
4086 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4087 u8 i = 0;
4088
4089 if (!enabled_tc)
4090 return 0x1; /* TC0 */
4091
4092 /* Find the first enabled TC */
4093 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4094 if (enabled_tc & (1 << i))
4095 break;
4096 }
4097
4098 return 1 << i;
4099}
4100
4101/**
4102 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4103 * @pf: PF being queried
4104 *
4105 * Return a bitmap for enabled traffic classes for this PF.
4106 **/
4107static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4108{
4109 /* If DCB is not enabled for this PF then just return default TC */
4110 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4111 return i40e_pf_get_default_tc(pf);
4112
4113 /* MFP mode will have enabled TCs set by FW */
4114 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4115 return pf->hw.func_caps.enabled_tcmap;
4116
4117 /* SFP mode we want PF to be enabled for all TCs */
4118 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4119}
4120
4121/**
4122 * i40e_vsi_get_bw_info - Query VSI BW Information
4123 * @vsi: the VSI being queried
4124 *
4125 * Returns 0 on success, negative value on failure
4126 **/
4127static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4128{
4129 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4130 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4131 struct i40e_pf *pf = vsi->back;
4132 struct i40e_hw *hw = &pf->hw;
dcae29be 4133 i40e_status aq_ret;
41c445ff 4134 u32 tc_bw_max;
41c445ff
JB		 4135 int i;
4136
4137 /* Get the VSI level BW configuration */
dcae29be
JB		 4138 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4139 if (aq_ret) {
41c445ff
JB		 4140 dev_info(&pf->pdev->dev,
4141 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 4142 aq_ret, pf->hw.aq.asq_last_status);
4143 return -EINVAL;
41c445ff
JB		 4144 }
4145
4146 /* Get the VSI level BW configuration per TC */
dcae29be 4147 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 4148 NULL);
dcae29be 4149 if (aq_ret) {
41c445ff
JB		 4150 dev_info(&pf->pdev->dev,
4151 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 4152 aq_ret, pf->hw.aq.asq_last_status);
4153 return -EINVAL;
41c445ff
JB		 4154 }
4155
4156 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4157 dev_info(&pf->pdev->dev,
4158 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4159 bw_config.tc_valid_bits,
4160 bw_ets_config.tc_valid_bits);
4161 /* Still continuing */
4162 }
4163
4164 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4165 vsi->bw_max_quanta = bw_config.max_bw;
4166 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4167 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4168 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4169 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4170 vsi->bw_ets_limit_credits[i] =
4171 le16_to_cpu(bw_ets_config.credits[i]);
4172 /* 3 bits out of 4 for each TC */
4173 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4174 }
078b5876 4175
dcae29be 4176 return 0;
41c445ff
JB		 4177}
4178
4179/**
4180 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4181 * @vsi: the VSI being configured
4182 * @enabled_tc: TC bitmap
4183 * @bw_credits: BW shared credits per TC
4184 *
4185 * Returns 0 on success, negative value on failure
4186 **/
dcae29be 4187static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4188 u8 *bw_share)
4189{
4190 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 4191 i40e_status aq_ret;
4192 int i;
41c445ff
JB		 4193
4194 bw_data.tc_valid_bits = enabled_tc;
4195 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4196 bw_data.tc_bw_credits[i] = bw_share[i];
4197
dcae29be
JB		 4198 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4199 NULL);
4200 if (aq_ret) {
41c445ff 4201 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4202 "AQ command Config VSI BW allocation per TC failed = %d\n",
4203 vsi->back->hw.aq.asq_last_status);
dcae29be 4204 return -EINVAL;
41c445ff
JB		 4205 }
4206
4207 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4208 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4209
dcae29be 4210 return 0;
41c445ff
JB		 4211}
4212
4213/**
4214 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4215 * @vsi: the VSI being configured
4216 * @enabled_tc: TC map to be enabled
4217 *
4218 **/
4219static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4220{
4221 struct net_device *netdev = vsi->netdev;
4222 struct i40e_pf *pf = vsi->back;
4223 struct i40e_hw *hw = &pf->hw;
4224 u8 netdev_tc = 0;
4225 int i;
4226 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4227
4228 if (!netdev)
4229 return;
4230
4231 if (!enabled_tc) {
4232 netdev_reset_tc(netdev);
4233 return;
4234 }
4235
4236 /* Set up actual enabled TCs on the VSI */
4237 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4238 return;
4239
4240 /* set per TC queues for the VSI */
4241 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4242 /* Only set TC queues for enabled tcs
4243 *
4244 * e.g. For a VSI that has TC0 and TC3 enabled the
4245 * enabled_tc bitmap would be 0x00001001; the driver
4246 * will set the numtc for netdev as 2 that will be
4247 * referenced by the netdev layer as TC 0 and 1.
4248 */
4249 if (vsi->tc_config.enabled_tc & (1 << i))
4250 netdev_set_tc_queue(netdev,
4251 vsi->tc_config.tc_info[i].netdev_tc,
4252 vsi->tc_config.tc_info[i].qcount,
4253 vsi->tc_config.tc_info[i].qoffset);
4254 }
4255
4256 /* Assign UP2TC map for the VSI */
4257 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4258 /* Get the actual TC# for the UP */
4259 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4260 /* Get the mapped netdev TC# for the UP */
4261 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4262 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4263 }
4264}
4265
4266/**
4267 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4268 * @vsi: the VSI being configured
4269 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4270 **/
4271static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4272 struct i40e_vsi_context *ctxt)
4273{
4274 /* copy just the sections touched not the entire info
4275 * since not all sections are valid as returned by
4276 * update vsi params
4277 */
4278 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4279 memcpy(&vsi->info.queue_mapping,
4280 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4281 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4282 sizeof(vsi->info.tc_mapping));
4283}
4284
4285/**
4286 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4287 * @vsi: VSI to be configured
4288 * @enabled_tc: TC bitmap
4289 *
4290 * This configures a particular VSI for TCs that are mapped to the
4291 * given TC bitmap. It uses default bandwidth share for TCs across
4292 * VSIs to configure TC for a particular VSI.
4293 *
4294 * NOTE:
4295 * It is expected that the VSI queues have been quisced before calling
4296 * this function.
4297 **/
4298static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4299{
4300 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4301 struct i40e_vsi_context ctxt;
4302 int ret = 0;
4303 int i;
4304
4305 /* Check if enabled_tc is same as existing or new TCs */
4306 if (vsi->tc_config.enabled_tc == enabled_tc)
4307 return ret;
4308
4309 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4310 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4311 if (enabled_tc & (1 << i))
4312 bw_share[i] = 1;
4313 }
4314
4315 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4316 if (ret) {
4317 dev_info(&vsi->back->pdev->dev,
4318 "Failed configuring TC map %d for VSI %d\n",
4319 enabled_tc, vsi->seid);
4320 goto out;
4321 }
4322
4323 /* Update Queue Pairs Mapping for currently enabled UPs */
4324 ctxt.seid = vsi->seid;
4325 ctxt.pf_num = vsi->back->hw.pf_id;
4326 ctxt.vf_num = 0;
4327 ctxt.uplink_seid = vsi->uplink_seid;
4328 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4329 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4330
4331 /* Update the VSI after updating the VSI queue-mapping information */
4332 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4333 if (ret) {
4334 dev_info(&vsi->back->pdev->dev,
4335 "update vsi failed, aq_err=%d\n",
4336 vsi->back->hw.aq.asq_last_status);
4337 goto out;
4338 }
4339 /* update the local VSI info with updated queue map */
4340 i40e_vsi_update_queue_map(vsi, &ctxt);
4341 vsi->info.valid_sections = 0;
4342
4343 /* Update current VSI BW information */
4344 ret = i40e_vsi_get_bw_info(vsi);
4345 if (ret) {
4346 dev_info(&vsi->back->pdev->dev,
4347 "Failed updating vsi bw info, aq_err=%d\n",
4348 vsi->back->hw.aq.asq_last_status);
4349 goto out;
4350 }
4351
4352 /* Update the netdev TC setup */
4353 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4354out:
4355 return ret;
4356}
4357
4e3b35b0
NP		 4358/**
4359 * i40e_veb_config_tc - Configure TCs for given VEB
4360 * @veb: given VEB
4361 * @enabled_tc: TC bitmap
4362 *
4363 * Configures given TC bitmap for VEB (switching) element
4364 **/
4365int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4366{
4367 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4368 struct i40e_pf *pf = veb->pf;
4369 int ret = 0;
4370 int i;
4371
4372 /* No TCs or already enabled TCs just return */
4373 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4374 return ret;
4375
4376 bw_data.tc_valid_bits = enabled_tc;
4377 /* bw_data.absolute_credits is not set (relative) */
4378
4379 /* Enable ETS TCs with equal BW Share for now */
4380 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4381 if (enabled_tc & (1 << i))
4382 bw_data.tc_bw_share_credits[i] = 1;
4383 }
4384
4385 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4386 &bw_data, NULL);
4387 if (ret) {
4388 dev_info(&pf->pdev->dev,
4389 "veb bw config failed, aq_err=%d\n",
4390 pf->hw.aq.asq_last_status);
4391 goto out;
4392 }
4393
4394 /* Update the BW information */
4395 ret = i40e_veb_get_bw_info(veb);
4396 if (ret) {
4397 dev_info(&pf->pdev->dev,
4398 "Failed getting veb bw config, aq_err=%d\n",
4399 pf->hw.aq.asq_last_status);
4400 }
4401
4402out:
4403 return ret;
4404}
4405
4406#ifdef CONFIG_I40E_DCB
4407/**
4408 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4409 * @pf: PF struct
4410 *
4411 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4412 * the caller would've quiesce all the VSIs before calling
4413 * this function
4414 **/
4415static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4416{
4417 u8 tc_map = 0;
4418 int ret;
4419 u8 v;
4420
4421 /* Enable the TCs available on PF to all VEBs */
4422 tc_map = i40e_pf_get_tc_map(pf);
4423 for (v = 0; v < I40E_MAX_VEB; v++) {
4424 if (!pf->veb[v])
4425 continue;
4426 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4427 if (ret) {
4428 dev_info(&pf->pdev->dev,
4429 "Failed configuring TC for VEB seid=%d\n",
4430 pf->veb[v]->seid);
4431 /* Will try to configure as many components */
4432 }
4433 }
4434
4435 /* Update each VSI */
505682cd 4436 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4437 if (!pf->vsi[v])
4438 continue;
4439
4440 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4441#ifdef I40E_FCOE
4442 * - For FCoE VSI only enable the TC configured
4443 * as per the APP TLV
4444#endif
4e3b35b0
NP		 4445 * - For all others keep them at TC0 for now
4446 */
4447 if (v == pf->lan_vsi)
4448 tc_map = i40e_pf_get_tc_map(pf);
4449 else
4450 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4451#ifdef I40E_FCOE
4452 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4453 tc_map = i40e_get_fcoe_tc_map(pf);
4454#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4455
4456 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4457 if (ret) {
4458 dev_info(&pf->pdev->dev,
4459 "Failed configuring TC for VSI seid=%d\n",
4460 pf->vsi[v]->seid);
4461 /* Will try to configure as many components */
4462 } else {
0672a091
NP		 4463 /* Re-configure VSI vectors based on updated TC map */
4464 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4465 if (pf->vsi[v]->netdev)
4466 i40e_dcbnl_set_all(pf->vsi[v]);
4467 }
4468 }
4469}
4470
2fd75f31
NP		 4471/**
4472 * i40e_resume_port_tx - Resume port Tx
4473 * @pf: PF struct
4474 *
4475 * Resume a port's Tx and issue a PF reset in case of failure to
4476 * resume.
4477 **/
4478static int i40e_resume_port_tx(struct i40e_pf *pf)
4479{
4480 struct i40e_hw *hw = &pf->hw;
4481 int ret;
4482
4483 ret = i40e_aq_resume_port_tx(hw, NULL);
4484 if (ret) {
4485 dev_info(&pf->pdev->dev,
4486 "AQ command Resume Port Tx failed = %d\n",
4487 pf->hw.aq.asq_last_status);
4488 /* Schedule PF reset to recover */
4489 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4490 i40e_service_event_schedule(pf);
4491 }
4492
4493 return ret;
4494}
4495
4e3b35b0
NP		 4496/**
4497 * i40e_init_pf_dcb - Initialize DCB configuration
4498 * @pf: PF being configured
4499 *
4500 * Query the current DCB configuration and cache it
4501 * in the hardware structure
4502 **/
4503static int i40e_init_pf_dcb(struct i40e_pf *pf)
4504{
4505 struct i40e_hw *hw = &pf->hw;
4506 int err = 0;
4507
4508 if (pf->hw.func_caps.npar_enable)
4509 goto out;
4510
4511 /* Get the initial DCB configuration */
4512 err = i40e_init_dcb(hw);
4513 if (!err) {
4514 /* Device/Function is not DCBX capable */
4515 if ((!hw->func_caps.dcb) ||
4516 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4517 dev_info(&pf->pdev->dev,
4518 "DCBX offload is not supported or is disabled for this PF.\n");
4519
4520 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4521 goto out;
4522
4523 } else {
4524 /* When status is not DISABLED then DCBX in FW */
4525 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4526 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4527
4528 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4529 /* Enable DCB tagging only when more than one TC */
4530 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4531 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4532 dev_dbg(&pf->pdev->dev,
4533 "DCBX offload is supported for this PF.\n");
4e3b35b0 4534 }
014269ff
NP		 4535 } else {
4536 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4537 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4538 }
4539
4540out:
4541 return err;
4542}
4543#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4544#define SPEED_SIZE 14
4545#define FC_SIZE 8
4546/**
4547 * i40e_print_link_message - print link up or down
4548 * @vsi: the VSI for which link needs a message
4549 */
4550static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4551{
4552 char speed[SPEED_SIZE] = "Unknown";
4553 char fc[FC_SIZE] = "RX/TX";
4554
4555 if (!isup) {
4556 netdev_info(vsi->netdev, "NIC Link is Down\n");
4557 return;
4558 }
4559
4560 switch (vsi->back->hw.phy.link_info.link_speed) {
4561 case I40E_LINK_SPEED_40GB:
35a7d804 4562 strlcpy(speed, "40 Gbps", SPEED_SIZE);
cf05ed08
JB		 4563 break;
4564 case I40E_LINK_SPEED_10GB:
35a7d804 4565 strlcpy(speed, "10 Gbps", SPEED_SIZE);
cf05ed08
JB		 4566 break;
4567 case I40E_LINK_SPEED_1GB:
35a7d804 4568 strlcpy(speed, "1000 Mbps", SPEED_SIZE);
cf05ed08 4569 break;
5960d33f
MW		 4570 case I40E_LINK_SPEED_100MB:
4571 strncpy(speed, "100 Mbps", SPEED_SIZE);
4572 break;
cf05ed08
JB		 4573 default:
4574 break;
4575 }
4576
4577 switch (vsi->back->hw.fc.current_mode) {
4578 case I40E_FC_FULL:
35a7d804 4579 strlcpy(fc, "RX/TX", FC_SIZE);
cf05ed08
JB		 4580 break;
4581 case I40E_FC_TX_PAUSE:
35a7d804 4582 strlcpy(fc, "TX", FC_SIZE);
cf05ed08
JB		 4583 break;
4584 case I40E_FC_RX_PAUSE:
35a7d804 4585 strlcpy(fc, "RX", FC_SIZE);
cf05ed08
JB		 4586 break;
4587 default:
35a7d804 4588 strlcpy(fc, "None", FC_SIZE);
cf05ed08
JB		 4589 break;
4590 }
4591
4592 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4593 speed, fc);
4594}
4e3b35b0 4595
41c445ff
JB		 4596/**
4597 * i40e_up_complete - Finish the last steps of bringing up a connection
4598 * @vsi: the VSI being configured
4599 **/
4600static int i40e_up_complete(struct i40e_vsi *vsi)
4601{
4602 struct i40e_pf *pf = vsi->back;
4603 int err;
4604
4605 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4606 i40e_vsi_configure_msix(vsi);
4607 else
4608 i40e_configure_msi_and_legacy(vsi);
4609
4610 /* start rings */
4611 err = i40e_vsi_control_rings(vsi, true);
4612 if (err)
4613 return err;
4614
4615 clear_bit(__I40E_DOWN, &vsi->state);
4616 i40e_napi_enable_all(vsi);
4617 i40e_vsi_enable_irq(vsi);
4618
4619 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4620 (vsi->netdev)) {
cf05ed08 4621 i40e_print_link_message(vsi, true);
41c445ff
JB		 4622 netif_tx_start_all_queues(vsi->netdev);
4623 netif_carrier_on(vsi->netdev);
6d779b41 4624 } else if (vsi->netdev) {
cf05ed08 4625 i40e_print_link_message(vsi, false);
7b592f61
CW		 4626 /* need to check for qualified module here*/
4627 if ((pf->hw.phy.link_info.link_info &
4628 I40E_AQ_MEDIA_AVAILABLE) &&
4629 (!(pf->hw.phy.link_info.an_info &
4630 I40E_AQ_QUALIFIED_MODULE)))
4631 netdev_err(vsi->netdev,
4632 "the driver failed to link because an unqualified module was detected.");
41c445ff 4633 }
ca64fa4e
ASJ		 4634
4635 /* replay FDIR SB filters */
1e1be8f6
ASJ		 4636 if (vsi->type == I40E_VSI_FDIR) {
4637 /* reset fd counters */
4638 pf->fd_add_err = pf->fd_atr_cnt = 0;
4639 if (pf->fd_tcp_rule > 0) {
4640 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4641 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
4642 pf->fd_tcp_rule = 0;
4643 }
ca64fa4e 4644 i40e_fdir_filter_restore(vsi);
1e1be8f6 4645 }
41c445ff
JB		 4646 i40e_service_event_schedule(pf);
4647
4648 return 0;
4649}
4650
4651/**
4652 * i40e_vsi_reinit_locked - Reset the VSI
4653 * @vsi: the VSI being configured
4654 *
4655 * Rebuild the ring structs after some configuration
4656 * has changed, e.g. MTU size.
4657 **/
4658static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4659{
4660 struct i40e_pf *pf = vsi->back;
4661
4662 WARN_ON(in_interrupt());
4663 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4664 usleep_range(1000, 2000);
4665 i40e_down(vsi);
4666
4667 /* Give a VF some time to respond to the reset. The
4668 * two second wait is based upon the watchdog cycle in
4669 * the VF driver.
4670 */
4671 if (vsi->type == I40E_VSI_SRIOV)
4672 msleep(2000);
4673 i40e_up(vsi);
4674 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4675}
4676
4677/**
4678 * i40e_up - Bring the connection back up after being down
4679 * @vsi: the VSI being configured
4680 **/
4681int i40e_up(struct i40e_vsi *vsi)
4682{
4683 int err;
4684
4685 err = i40e_vsi_configure(vsi);
4686 if (!err)
4687 err = i40e_up_complete(vsi);
4688
4689 return err;
4690}
4691
4692/**
4693 * i40e_down - Shutdown the connection processing
4694 * @vsi: the VSI being stopped
4695 **/
4696void i40e_down(struct i40e_vsi *vsi)
4697{
4698 int i;
4699
4700 /* It is assumed that the caller of this function
4701 * sets the vsi->state __I40E_DOWN bit.
4702 */
4703 if (vsi->netdev) {
4704 netif_carrier_off(vsi->netdev);
4705 netif_tx_disable(vsi->netdev);
4706 }
4707 i40e_vsi_disable_irq(vsi);
4708 i40e_vsi_control_rings(vsi, false);
4709 i40e_napi_disable_all(vsi);
4710
4711 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4712 i40e_clean_tx_ring(vsi->tx_rings[i]);
4713 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4714 }
4715}
4716
4717/**
4718 * i40e_setup_tc - configure multiple traffic classes
4719 * @netdev: net device to configure
4720 * @tc: number of traffic classes to enable
4721 **/
38e00438
VD		 4722#ifdef I40E_FCOE
4723int i40e_setup_tc(struct net_device *netdev, u8 tc)
4724#else
41c445ff 4725static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 4726#endif
41c445ff
JB		 4727{
4728 struct i40e_netdev_priv *np = netdev_priv(netdev);
4729 struct i40e_vsi *vsi = np->vsi;
4730 struct i40e_pf *pf = vsi->back;
4731 u8 enabled_tc = 0;
4732 int ret = -EINVAL;
4733 int i;
4734
4735 /* Check if DCB enabled to continue */
4736 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4737 netdev_info(netdev, "DCB is not enabled for adapter\n");
4738 goto exit;
4739 }
4740
4741 /* Check if MFP enabled */
4742 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4743 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4744 goto exit;
4745 }
4746
4747 /* Check whether tc count is within enabled limit */
4748 if (tc > i40e_pf_get_num_tc(pf)) {
4749 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4750 goto exit;
4751 }
4752
4753 /* Generate TC map for number of tc requested */
4754 for (i = 0; i < tc; i++)
4755 enabled_tc |= (1 << i);
4756
4757 /* Requesting same TC configuration as already enabled */
4758 if (enabled_tc == vsi->tc_config.enabled_tc)
4759 return 0;
4760
4761 /* Quiesce VSI queues */
4762 i40e_quiesce_vsi(vsi);
4763
4764 /* Configure VSI for enabled TCs */
4765 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4766 if (ret) {
4767 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4768 vsi->seid);
4769 goto exit;
4770 }
4771
4772 /* Unquiesce VSI */
4773 i40e_unquiesce_vsi(vsi);
4774
4775exit:
4776 return ret;
4777}
4778
4779/**
4780 * i40e_open - Called when a network interface is made active
4781 * @netdev: network interface device structure
4782 *
4783 * The open entry point is called when a network interface is made
4784 * active by the system (IFF_UP). At this point all resources needed
4785 * for transmit and receive operations are allocated, the interrupt
4786 * handler is registered with the OS, the netdev watchdog subtask is
4787 * enabled, and the stack is notified that the interface is ready.
4788 *
4789 * Returns 0 on success, negative value on failure
4790 **/
38e00438
VD		 4791#ifdef I40E_FCOE
4792int i40e_open(struct net_device *netdev)
4793#else
41c445ff 4794static int i40e_open(struct net_device *netdev)
38e00438 4795#endif
41c445ff
JB		 4796{
4797 struct i40e_netdev_priv *np = netdev_priv(netdev);
4798 struct i40e_vsi *vsi = np->vsi;
4799 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4800 int err;
4801
4eb3f768
SN		 4802 /* disallow open during test or if eeprom is broken */
4803 if (test_bit(__I40E_TESTING, &pf->state) ||
4804 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4805 return -EBUSY;
4806
4807 netif_carrier_off(netdev);
4808
6c167f58
EK		 4809 err = i40e_vsi_open(vsi);
4810 if (err)
4811 return err;
4812
059dab69
JB		 4813 /* configure global TSO hardware offload settings */
4814 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4815 TCP_FLAG_FIN) >> 16);
4816 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4817 TCP_FLAG_FIN |
4818 TCP_FLAG_CWR) >> 16);
4819 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4820
6c167f58
EK		 4821#ifdef CONFIG_I40E_VXLAN
4822 vxlan_get_rx_port(netdev);
4823#endif
4824
4825 return 0;
4826}
4827
4828/**
4829 * i40e_vsi_open -
4830 * @vsi: the VSI to open
4831 *
4832 * Finish initialization of the VSI.
4833 *
4834 * Returns 0 on success, negative value on failure
4835 **/
4836int i40e_vsi_open(struct i40e_vsi *vsi)
4837{
4838 struct i40e_pf *pf = vsi->back;
4839 char int_name[IFNAMSIZ];
4840 int err;
4841
41c445ff
JB		 4842 /* allocate descriptors */
4843 err = i40e_vsi_setup_tx_resources(vsi);
4844 if (err)
4845 goto err_setup_tx;
4846 err = i40e_vsi_setup_rx_resources(vsi);
4847 if (err)
4848 goto err_setup_rx;
4849
4850 err = i40e_vsi_configure(vsi);
4851 if (err)
4852 goto err_setup_rx;
4853
c22e3c6c
SN		 4854 if (vsi->netdev) {
4855 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4856 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4857 err = i40e_vsi_request_irq(vsi, int_name);
4858 if (err)
4859 goto err_setup_rx;
41c445ff 4860
c22e3c6c
SN		 4861 /* Notify the stack of the actual queue counts. */
4862 err = netif_set_real_num_tx_queues(vsi->netdev,
4863 vsi->num_queue_pairs);
4864 if (err)
4865 goto err_set_queues;
25946ddb 4866
c22e3c6c
SN		 4867 err = netif_set_real_num_rx_queues(vsi->netdev,
4868 vsi->num_queue_pairs);
4869 if (err)
4870 goto err_set_queues;
8a9eb7d3
SN		 4871
4872 } else if (vsi->type == I40E_VSI_FDIR) {
b2008cbf
CW		 4873 snprintf(int_name, sizeof(int_name) - 1, "%s-%s-fdir",
4874 dev_driver_string(&pf->pdev->dev),
4875 dev_name(&pf->pdev->dev));
8a9eb7d3 4876 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 4877
c22e3c6c 4878 } else {
ce9ccb17 4879 err = -EINVAL;
6c167f58
EK		 4880 goto err_setup_rx;
4881 }
25946ddb 4882
41c445ff
JB		 4883 err = i40e_up_complete(vsi);
4884 if (err)
4885 goto err_up_complete;
4886
41c445ff
JB		 4887 return 0;
4888
4889err_up_complete:
4890 i40e_down(vsi);
25946ddb 4891err_set_queues:
41c445ff
JB		 4892 i40e_vsi_free_irq(vsi);
4893err_setup_rx:
4894 i40e_vsi_free_rx_resources(vsi);
4895err_setup_tx:
4896 i40e_vsi_free_tx_resources(vsi);
4897 if (vsi == pf->vsi[pf->lan_vsi])
4898 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4899
4900 return err;
4901}
4902
17a73f6b
JG		 4903/**
4904 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4905 * @pf: Pointer to pf
4906 *
4907 * This function destroys the hlist where all the Flow Director
4908 * filters were saved.
4909 **/
4910static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4911{
4912 struct i40e_fdir_filter *filter;
4913 struct hlist_node *node2;
4914
4915 hlist_for_each_entry_safe(filter, node2,
4916 &pf->fdir_filter_list, fdir_node) {
4917 hlist_del(&filter->fdir_node);
4918 kfree(filter);
4919 }
4920 pf->fdir_pf_active_filters = 0;
4921}
4922
41c445ff
JB		 4923/**
4924 * i40e_close - Disables a network interface
4925 * @netdev: network interface device structure
4926 *
4927 * The close entry point is called when an interface is de-activated
4928 * by the OS. The hardware is still under the driver's control, but
4929 * this netdev interface is disabled.
4930 *
4931 * Returns 0, this is not allowed to fail
4932 **/
38e00438
VD		 4933#ifdef I40E_FCOE
4934int i40e_close(struct net_device *netdev)
4935#else
41c445ff 4936static int i40e_close(struct net_device *netdev)
38e00438 4937#endif
41c445ff
JB		 4938{
4939 struct i40e_netdev_priv *np = netdev_priv(netdev);
4940 struct i40e_vsi *vsi = np->vsi;
4941
90ef8d47 4942 i40e_vsi_close(vsi);
41c445ff
JB		 4943
4944 return 0;
4945}
4946
4947/**
4948 * i40e_do_reset - Start a PF or Core Reset sequence
4949 * @pf: board private structure
4950 * @reset_flags: which reset is requested
4951 *
4952 * The essential difference in resets is that the PF Reset
4953 * doesn't clear the packet buffers, doesn't reset the PE
4954 * firmware, and doesn't bother the other PFs on the chip.
4955 **/
4956void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4957{
4958 u32 val;
4959
4960 WARN_ON(in_interrupt());
4961
263fc48f
MW		 4962 if (i40e_check_asq_alive(&pf->hw))
4963 i40e_vc_notify_reset(pf);
4964
41c445ff
JB		 4965 /* do the biggest reset indicated */
4966 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4967
4968 /* Request a Global Reset
4969 *
4970 * This will start the chip's countdown to the actual full
4971 * chip reset event, and a warning interrupt to be sent
4972 * to all PFs, including the requestor. Our handler
4973 * for the warning interrupt will deal with the shutdown
4974 * and recovery of the switch setup.
4975 */
69bfb110 4976 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4977 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4978 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4979 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4980
4981 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4982
4983 /* Request a Core Reset
4984 *
4985 * Same as Global Reset, except does *not* include the MAC/PHY
4986 */
69bfb110 4987 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4988 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4989 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4990 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4991 i40e_flush(&pf->hw);
4992
7823fe34
SN		 4993 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4994
4995 /* Request a Firmware Reset
4996 *
4997 * Same as Global reset, plus restarting the
4998 * embedded firmware engine.
4999 */
5000 /* enable EMP Reset */
5001 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
5002 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
5003 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
5004
5005 /* force the reset */
5006 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5007 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
5008 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5009 i40e_flush(&pf->hw);
5010
41c445ff
JB		 5011 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
5012
5013 /* Request a PF Reset
5014 *
5015 * Resets only the PF-specific registers
5016 *
5017 * This goes directly to the tear-down and rebuild of
5018 * the switch, since we need to do all the recovery as
5019 * for the Core Reset.
5020 */
69bfb110 5021 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5022 i40e_handle_reset_warning(pf);
5023
5024 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
5025 int v;
5026
5027 /* Find the VSI(s) that requested a re-init */
5028 dev_info(&pf->pdev->dev,
5029 "VSI reinit requested\n");
505682cd 5030 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5031 struct i40e_vsi *vsi = pf->vsi[v];
5032 if (vsi != NULL &&
5033 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5034 i40e_vsi_reinit_locked(pf->vsi[v]);
5035 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5036 }
5037 }
5038
b5d06f05
NP		 5039 /* no further action needed, so return now */
5040 return;
5041 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
5042 int v;
5043
5044 /* Find the VSI(s) that needs to be brought down */
5045 dev_info(&pf->pdev->dev, "VSI down requested\n");
5046 for (v = 0; v < pf->num_alloc_vsi; v++) {
5047 struct i40e_vsi *vsi = pf->vsi[v];
5048 if (vsi != NULL &&
5049 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5050 set_bit(__I40E_DOWN, &vsi->state);
5051 i40e_down(vsi);
5052 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5053 }
5054 }
5055
41c445ff
JB		 5056 /* no further action needed, so return now */
5057 return;
5058 } else {
5059 dev_info(&pf->pdev->dev,
5060 "bad reset request 0x%08x\n", reset_flags);
5061 return;
5062 }
5063}
5064
4e3b35b0
NP		 5065#ifdef CONFIG_I40E_DCB
5066/**
5067 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5068 * @pf: board private structure
5069 * @old_cfg: current DCB config
5070 * @new_cfg: new DCB config
5071 **/
5072bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5073 struct i40e_dcbx_config *old_cfg,
5074 struct i40e_dcbx_config *new_cfg)
5075{
5076 bool need_reconfig = false;
5077
5078 /* Check if ETS configuration has changed */
5079 if (memcmp(&new_cfg->etscfg,
5080 &old_cfg->etscfg,
5081 sizeof(new_cfg->etscfg))) {
5082 /* If Priority Table has changed reconfig is needed */
5083 if (memcmp(&new_cfg->etscfg.prioritytable,
5084 &old_cfg->etscfg.prioritytable,
5085 sizeof(new_cfg->etscfg.prioritytable))) {
5086 need_reconfig = true;
69bfb110 5087 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5088 }
5089
5090 if (memcmp(&new_cfg->etscfg.tcbwtable,
5091 &old_cfg->etscfg.tcbwtable,
5092 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5093 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5094
5095 if (memcmp(&new_cfg->etscfg.tsatable,
5096 &old_cfg->etscfg.tsatable,
5097 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5098 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5099 }
5100
5101 /* Check if PFC configuration has changed */
5102 if (memcmp(&new_cfg->pfc,
5103 &old_cfg->pfc,
5104 sizeof(new_cfg->pfc))) {
5105 need_reconfig = true;
69bfb110 5106 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5107 }
5108
5109 /* Check if APP Table has changed */
5110 if (memcmp(&new_cfg->app,
5111 &old_cfg->app,
3d9667a9 5112 sizeof(new_cfg->app))) {
4e3b35b0 5113 need_reconfig = true;
69bfb110 5114 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5115 }
4e3b35b0 5116
9fa61dd2
NP		 5117 dev_dbg(&pf->pdev->dev, "%s: need_reconfig=%d\n", __func__,
5118 need_reconfig);
4e3b35b0
NP		 5119 return need_reconfig;
5120}
5121
5122/**
5123 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5124 * @pf: board private structure
5125 * @e: event info posted on ARQ
5126 **/
5127static int i40e_handle_lldp_event(struct i40e_pf *pf,
5128 struct i40e_arq_event_info *e)
5129{
5130 struct i40e_aqc_lldp_get_mib *mib =
5131 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5132 struct i40e_hw *hw = &pf->hw;
5133 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
5134 struct i40e_dcbx_config tmp_dcbx_cfg;
5135 bool need_reconfig = false;
5136 int ret = 0;
5137 u8 type;
5138
4d9b6043
NP		 5139 /* Not DCB capable or capability disabled */
5140 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5141 return ret;
5142
4e3b35b0
NP		 5143 /* Ignore if event is not for Nearest Bridge */
5144 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5145 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
9fa61dd2
NP		 5146 dev_dbg(&pf->pdev->dev,
5147 "%s: LLDP event mib bridge type 0x%x\n", __func__, type);
4e3b35b0
NP		 5148 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5149 return ret;
5150
5151 /* Check MIB Type and return if event for Remote MIB update */
5152 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2
NP		 5153 dev_dbg(&pf->pdev->dev,
5154 "%s: LLDP event mib type %s\n", __func__,
5155 type ? "remote" : "local");
4e3b35b0
NP		 5156 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5157 /* Update the remote cached instance and return */
5158 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5159 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5160 &hw->remote_dcbx_config);
5161 goto exit;
5162 }
5163
4e3b35b0 5164 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
9fa61dd2
NP		 5165 /* Store the old configuration */
5166 tmp_dcbx_cfg = *dcbx_cfg;
5167
5168 /* Get updated DCBX data from firmware */
5169 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5170 if (ret) {
9fa61dd2 5171 dev_info(&pf->pdev->dev, "Failed querying DCB configuration data from firmware.\n");
4e3b35b0
NP		 5172 goto exit;
5173 }
5174
5175 /* No change detected in DCBX configs */
5176 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 5177 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5178 goto exit;
5179 }
5180
9fa61dd2 5181 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, dcbx_cfg);
4e3b35b0 5182
9fa61dd2 5183 i40e_dcbnl_flush_apps(pf, dcbx_cfg);
4e3b35b0
NP		 5184
5185 if (!need_reconfig)
5186 goto exit;
5187
4d9b6043
NP		 5188 /* Enable DCB tagging only when more than one TC */
5189 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
5190 pf->flags |= I40E_FLAG_DCB_ENABLED;
5191 else
5192 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5193
69129dc3 5194 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5195 /* Reconfiguration needed quiesce all VSIs */
5196 i40e_pf_quiesce_all_vsi(pf);
5197
5198 /* Changes in configuration update VEB/VSI */
5199 i40e_dcb_reconfigure(pf);
5200
2fd75f31
NP		 5201 ret = i40e_resume_port_tx(pf);
5202
69129dc3 5203 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5204 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5205 if (ret)
5206 goto exit;
5207
5208 /* Wait for the PF's Tx queues to be disabled */
5209 ret = i40e_pf_wait_txq_disabled(pf);
2fd75f31
NP		 5210 if (!ret)
5211 i40e_pf_unquiesce_all_vsi(pf);
4e3b35b0
NP		 5212exit:
5213 return ret;
5214}
5215#endif /* CONFIG_I40E_DCB */
5216
23326186
ASJ		 5217/**
5218 * i40e_do_reset_safe - Protected reset path for userland calls.
5219 * @pf: board private structure
5220 * @reset_flags: which reset is requested
5221 *
5222 **/
5223void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5224{
5225 rtnl_lock();
5226 i40e_do_reset(pf, reset_flags);
5227 rtnl_unlock();
5228}
5229
41c445ff
JB		 5230/**
5231 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5232 * @pf: board private structure
5233 * @e: event info posted on ARQ
5234 *
5235 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5236 * and VF queues
5237 **/
5238static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5239 struct i40e_arq_event_info *e)
5240{
5241 struct i40e_aqc_lan_overflow *data =
5242 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5243 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5244 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5245 struct i40e_hw *hw = &pf->hw;
5246 struct i40e_vf *vf;
5247 u16 vf_id;
5248
69bfb110
JB		 5249 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5250 queue, qtx_ctl);
41c445ff
JB		 5251
5252 /* Queue belongs to VF, find the VF and issue VF reset */
5253 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5254 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5255 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5256 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5257 vf_id -= hw->func_caps.vf_base_id;
5258 vf = &pf->vf[vf_id];
5259 i40e_vc_notify_vf_reset(vf);
5260 /* Allow VF to process pending reset notification */
5261 msleep(20);
5262 i40e_reset_vf(vf, false);
5263 }
5264}
5265
5266/**
5267 * i40e_service_event_complete - Finish up the service event
5268 * @pf: board private structure
5269 **/
5270static void i40e_service_event_complete(struct i40e_pf *pf)
5271{
5272 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
5273
5274 /* flush memory to make sure state is correct before next watchog */
4e857c58 5275 smp_mb__before_atomic();
41c445ff
JB		 5276 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5277}
5278
55a5e60b 5279/**
12957388
ASJ		 5280 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5281 * @pf: board private structure
5282 **/
5283int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
5284{
5285 int val, fcnt_prog;
5286
5287 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5288 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5289 return fcnt_prog;
5290}
5291
5292/**
5293 * i40e_get_current_fd_count - Get the count of total FD filters programmed
55a5e60b
ASJ		 5294 * @pf: board private structure
5295 **/
5296int i40e_get_current_fd_count(struct i40e_pf *pf)
5297{
5298 int val, fcnt_prog;
5299 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5300 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5301 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5302 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5303 return fcnt_prog;
5304}
1e1be8f6 5305
55a5e60b
ASJ		 5306/**
5307 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5308 * @pf: board private structure
5309 **/
5310void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5311{
5312 u32 fcnt_prog, fcnt_avail;
5313
1e1be8f6
ASJ		 5314 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5315 return;
5316
55a5e60b
ASJ		 5317 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5318 * to re-enable
5319 */
12957388
ASJ		 5320 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
5321 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5322 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5323 (pf->fd_add_err == 0) ||
5324 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5325 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5326 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5327 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5328 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
5329 }
5330 }
5331 /* Wait for some more space to be available to turn on ATR */
5332 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5333 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5334 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5335 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5336 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
5337 }
5338 }
5339}
5340
1e1be8f6
ASJ		 5341#define I40E_MIN_FD_FLUSH_INTERVAL 10
5342/**
5343 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5344 * @pf: board private structure
5345 **/
5346static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5347{
5348 int flush_wait_retry = 50;
5349 int reg;
5350
1790ed0c
AA		 5351 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5352 return;
5353
1e1be8f6
ASJ		 5354 if (time_after(jiffies, pf->fd_flush_timestamp +
5355 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
5356 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5357 pf->fd_flush_timestamp = jiffies;
5358 pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
5359 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5360 /* flush all filters */
5361 wr32(&pf->hw, I40E_PFQF_CTL_1,
5362 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5363 i40e_flush(&pf->hw);
60793f4a 5364 pf->fd_flush_cnt++;
1e1be8f6
ASJ		 5365 pf->fd_add_err = 0;
5366 do {
5367 /* Check FD flush status every 5-6msec */
5368 usleep_range(5000, 6000);
5369 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5370 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5371 break;
5372 } while (flush_wait_retry--);
5373 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5374 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5375 } else {
5376 /* replay sideband filters */
5377 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5378
5379 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5380 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5381 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
5382 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5383 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
5384 }
5385 }
5386}
5387
5388/**
5389 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5390 * @pf: board private structure
5391 **/
5392int i40e_get_current_atr_cnt(struct i40e_pf *pf)
5393{
5394 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5395}
5396
5397/* We can see up to 256 filter programming desc in transit if the filters are
5398 * being applied really fast; before we see the first
5399 * filter miss error on Rx queue 0. Accumulating enough error messages before
5400 * reacting will make sure we don't cause flush too often.
5401 */
5402#define I40E_MAX_FD_PROGRAM_ERROR 256
5403
41c445ff
JB		 5404/**
5405 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5406 * @pf: board private structure
5407 **/
5408static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5409{
41c445ff 5410
41c445ff
JB		 5411 /* if interface is down do nothing */
5412 if (test_bit(__I40E_DOWN, &pf->state))
5413 return;
1e1be8f6 5414
1790ed0c
AA		 5415 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5416 return;
5417
1e1be8f6
ASJ		 5418 if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
5419 (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
5420 (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
5421 i40e_fdir_flush_and_replay(pf);
5422
55a5e60b
ASJ		 5423 i40e_fdir_check_and_reenable(pf);
5424
41c445ff
JB		 5425}
5426
5427/**
5428 * i40e_vsi_link_event - notify VSI of a link event
5429 * @vsi: vsi to be notified
5430 * @link_up: link up or down
5431 **/
5432static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5433{
32b5b811 5434 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5435 return;
5436
5437 switch (vsi->type) {
5438 case I40E_VSI_MAIN:
38e00438
VD		 5439#ifdef I40E_FCOE
5440 case I40E_VSI_FCOE:
5441#endif
41c445ff
JB		 5442 if (!vsi->netdev || !vsi->netdev_registered)
5443 break;
5444
5445 if (link_up) {
5446 netif_carrier_on(vsi->netdev);
5447 netif_tx_wake_all_queues(vsi->netdev);
5448 } else {
5449 netif_carrier_off(vsi->netdev);
5450 netif_tx_stop_all_queues(vsi->netdev);
5451 }
5452 break;
5453
5454 case I40E_VSI_SRIOV:
41c445ff
JB		 5455 case I40E_VSI_VMDQ2:
5456 case I40E_VSI_CTRL:
5457 case I40E_VSI_MIRROR:
5458 default:
5459 /* there is no notification for other VSIs */
5460 break;
5461 }
5462}
5463
5464/**
5465 * i40e_veb_link_event - notify elements on the veb of a link event
5466 * @veb: veb to be notified
5467 * @link_up: link up or down
5468 **/
5469static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5470{
5471 struct i40e_pf *pf;
5472 int i;
5473
5474 if (!veb || !veb->pf)
5475 return;
5476 pf = veb->pf;
5477
5478 /* depth first... */
5479 for (i = 0; i < I40E_MAX_VEB; i++)
5480 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5481 i40e_veb_link_event(pf->veb[i], link_up);
5482
5483 /* ... now the local VSIs */
505682cd 5484 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5485 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5486 i40e_vsi_link_event(pf->vsi[i], link_up);
5487}
5488
5489/**
5490 * i40e_link_event - Update netif_carrier status
5491 * @pf: board private structure
5492 **/
5493static void i40e_link_event(struct i40e_pf *pf)
5494{
5495 bool new_link, old_link;
320684cd 5496 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
41c445ff 5497
1e701e09
JB		 5498 /* set this to force the get_link_status call to refresh state */
5499 pf->hw.phy.get_link_info = true;
5500
41c445ff 5501 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
1e701e09 5502 new_link = i40e_get_link_status(&pf->hw);
41c445ff 5503
1e701e09 5504 if (new_link == old_link &&
320684cd
MW		 5505 (test_bit(__I40E_DOWN, &vsi->state) ||
5506 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 5507 return;
320684cd
MW		 5508
5509 if (!test_bit(__I40E_DOWN, &vsi->state))
5510 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 5511
5512 /* Notify the base of the switch tree connected to
5513 * the link. Floating VEBs are not notified.
5514 */
5515 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5516 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5517 else
320684cd 5518 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 5519
5520 if (pf->vf)
5521 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5522
5523 if (pf->flags & I40E_FLAG_PTP)
5524 i40e_ptp_set_increment(pf);
41c445ff
JB		 5525}
5526
5527/**
5528 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5529 * @pf: board private structure
5530 *
5531 * Set the per-queue flags to request a check for stuck queues in the irq
5532 * clean functions, then force interrupts to be sure the irq clean is called.
5533 **/
5534static void i40e_check_hang_subtask(struct i40e_pf *pf)
5535{
5536 int i, v;
5537
5538 /* If we're down or resetting, just bail */
5539 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5540 return;
5541
5542 /* for each VSI/netdev
5543 * for each Tx queue
5544 * set the check flag
5545 * for each q_vector
5546 * force an interrupt
5547 */
505682cd 5548 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5549 struct i40e_vsi *vsi = pf->vsi[v];
5550 int armed = 0;
5551
5552 if (!pf->vsi[v] ||
5553 test_bit(__I40E_DOWN, &vsi->state) ||
5554 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5555 continue;
5556
5557 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5558 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5559 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5560 &vsi->tx_rings[i]->state))
41c445ff
JB		 5561 armed++;
5562 }
5563
5564 if (armed) {
5565 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5566 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5567 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5d1ff106
SN		 5568 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
5569 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
5570 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
5571 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
41c445ff
JB		 5572 } else {
5573 u16 vec = vsi->base_vector - 1;
5574 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5d1ff106
SN		 5575 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
5576 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK |
5577 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
5578 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK);
41c445ff
JB		 5579 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5580 wr32(&vsi->back->hw,
5581 I40E_PFINT_DYN_CTLN(vec), val);
5582 }
5583 i40e_flush(&vsi->back->hw);
5584 }
5585 }
5586}
5587
5588/**
21536717 5589 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 5590 * @pf: board private structure
5591 **/
5592static void i40e_watchdog_subtask(struct i40e_pf *pf)
5593{
5594 int i;
5595
5596 /* if interface is down do nothing */
5597 if (test_bit(__I40E_DOWN, &pf->state) ||
5598 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5599 return;
5600
21536717
SN		 5601 /* make sure we don't do these things too often */
5602 if (time_before(jiffies, (pf->service_timer_previous +
5603 pf->service_timer_period)))
5604 return;
5605 pf->service_timer_previous = jiffies;
5606
5607 i40e_check_hang_subtask(pf);
5608 i40e_link_event(pf);
5609
41c445ff
JB		 5610 /* Update the stats for active netdevs so the network stack
5611 * can look at updated numbers whenever it cares to
5612 */
505682cd 5613 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5614 if (pf->vsi[i] && pf->vsi[i]->netdev)
5615 i40e_update_stats(pf->vsi[i]);
5616
5617 /* Update the stats for the active switching components */
5618 for (i = 0; i < I40E_MAX_VEB; i++)
5619 if (pf->veb[i])
5620 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5621
5622 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5623}
5624
5625/**
5626 * i40e_reset_subtask - Set up for resetting the device and driver
5627 * @pf: board private structure
5628 **/
5629static void i40e_reset_subtask(struct i40e_pf *pf)
5630{
5631 u32 reset_flags = 0;
5632
23326186 5633 rtnl_lock();
41c445ff
JB		 5634 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5635 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5636 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5637 }
5638 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5639 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5640 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5641 }
5642 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5643 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5644 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5645 }
5646 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5647 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5648 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5649 }
b5d06f05
NP		 5650 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5651 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5652 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5653 }
41c445ff
JB		 5654
5655 /* If there's a recovery already waiting, it takes
5656 * precedence before starting a new reset sequence.
5657 */
5658 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5659 i40e_handle_reset_warning(pf);
23326186 5660 goto unlock;
41c445ff
JB		 5661 }
5662
5663 /* If we're already down or resetting, just bail */
5664 if (reset_flags &&
5665 !test_bit(__I40E_DOWN, &pf->state) &&
5666 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5667 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5668
5669unlock:
5670 rtnl_unlock();
41c445ff
JB		 5671}
5672
5673/**
5674 * i40e_handle_link_event - Handle link event
5675 * @pf: board private structure
5676 * @e: event info posted on ARQ
5677 **/
5678static void i40e_handle_link_event(struct i40e_pf *pf,
5679 struct i40e_arq_event_info *e)
5680{
5681 struct i40e_hw *hw = &pf->hw;
5682 struct i40e_aqc_get_link_status *status =
5683 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5684 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5685
5686 /* save off old link status information */
5687 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5688 sizeof(pf->hw.phy.link_info_old));
5689
1e701e09
JB		 5690 /* Do a new status request to re-enable LSE reporting
5691 * and load new status information into the hw struct
5692 * This completely ignores any state information
5693 * in the ARQ event info, instead choosing to always
5694 * issue the AQ update link status command.
5695 */
5696 i40e_link_event(pf);
5697
7b592f61
CW		 5698 /* check for unqualified module, if link is down */
5699 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
5700 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
5701 (!(status->link_info & I40E_AQ_LINK_UP)))
5702 dev_err(&pf->pdev->dev,
5703 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 5704}
5705
5706/**
5707 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5708 * @pf: board private structure
5709 **/
5710static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5711{
5712 struct i40e_arq_event_info event;
5713 struct i40e_hw *hw = &pf->hw;
5714 u16 pending, i = 0;
5715 i40e_status ret;
5716 u16 opcode;
86df242b 5717 u32 oldval;
41c445ff
JB		 5718 u32 val;
5719
a316f651
ASJ		 5720 /* Do not run clean AQ when PF reset fails */
5721 if (test_bit(__I40E_RESET_FAILED, &pf->state))
5722 return;
5723
86df242b
SN		 5724 /* check for error indications */
5725 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5726 oldval = val;
5727 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5728 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5729 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5730 }
5731 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5732 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5733 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5734 }
5735 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5736 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5737 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5738 }
5739 if (oldval != val)
5740 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5741
5742 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5743 oldval = val;
5744 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5745 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5746 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5747 }
5748 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5749 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5750 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5751 }
5752 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5753 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5754 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5755 }
5756 if (oldval != val)
5757 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5758
1001dc37
MW		 5759 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
5760 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 5761 if (!event.msg_buf)
5762 return;
5763
5764 do {
5765 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 5766 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 5767 break;
56497978 5768 else if (ret) {
41c445ff
JB		 5769 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5770 break;
5771 }
5772
5773 opcode = le16_to_cpu(event.desc.opcode);
5774 switch (opcode) {
5775
5776 case i40e_aqc_opc_get_link_status:
5777 i40e_handle_link_event(pf, &event);
5778 break;
5779 case i40e_aqc_opc_send_msg_to_pf:
5780 ret = i40e_vc_process_vf_msg(pf,
5781 le16_to_cpu(event.desc.retval),
5782 le32_to_cpu(event.desc.cookie_high),
5783 le32_to_cpu(event.desc.cookie_low),
5784 event.msg_buf,
1001dc37 5785 event.msg_len);
41c445ff
JB		 5786 break;
5787 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5788 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5789#ifdef CONFIG_I40E_DCB
5790 rtnl_lock();
5791 ret = i40e_handle_lldp_event(pf, &event);
5792 rtnl_unlock();
5793#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5794 break;
5795 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5796 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5797 i40e_handle_lan_overflow_event(pf, &event);
5798 break;
0467bc91
SN		 5799 case i40e_aqc_opc_send_msg_to_peer:
5800 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5801 break;
41c445ff
JB		 5802 default:
5803 dev_info(&pf->pdev->dev,
0467bc91
SN		 5804 "ARQ Error: Unknown event 0x%04x received\n",
5805 opcode);
41c445ff
JB		 5806 break;
5807 }
5808 } while (pending && (i++ < pf->adminq_work_limit));
5809
5810 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5811 /* re-enable Admin queue interrupt cause */
5812 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5813 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5814 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5815 i40e_flush(hw);
5816
5817 kfree(event.msg_buf);
5818}
5819
4eb3f768
SN		 5820/**
5821 * i40e_verify_eeprom - make sure eeprom is good to use
5822 * @pf: board private structure
5823 **/
5824static void i40e_verify_eeprom(struct i40e_pf *pf)
5825{
5826 int err;
5827
5828 err = i40e_diag_eeprom_test(&pf->hw);
5829 if (err) {
5830 /* retry in case of garbage read */
5831 err = i40e_diag_eeprom_test(&pf->hw);
5832 if (err) {
5833 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5834 err);
5835 set_bit(__I40E_BAD_EEPROM, &pf->state);
5836 }
5837 }
5838
5839 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5840 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5841 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5842 }
5843}
5844
41c445ff
JB		 5845/**
5846 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5847 * @veb: pointer to the VEB instance
5848 *
5849 * This is a recursive function that first builds the attached VSIs then
5850 * recurses in to build the next layer of VEB. We track the connections
5851 * through our own index numbers because the seid's from the HW could
5852 * change across the reset.
5853 **/
5854static int i40e_reconstitute_veb(struct i40e_veb *veb)
5855{
5856 struct i40e_vsi *ctl_vsi = NULL;
5857 struct i40e_pf *pf = veb->pf;
5858 int v, veb_idx;
5859 int ret;
5860
5861 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5862 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5863 if (pf->vsi[v] &&
5864 pf->vsi[v]->veb_idx == veb->idx &&
5865 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5866 ctl_vsi = pf->vsi[v];
5867 break;
5868 }
5869 }
5870 if (!ctl_vsi) {
5871 dev_info(&pf->pdev->dev,
5872 "missing owner VSI for veb_idx %d\n", veb->idx);
5873 ret = -ENOENT;
5874 goto end_reconstitute;
5875 }
5876 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5877 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5878 ret = i40e_add_vsi(ctl_vsi);
5879 if (ret) {
5880 dev_info(&pf->pdev->dev,
5881 "rebuild of owner VSI failed: %d\n", ret);
5882 goto end_reconstitute;
5883 }
5884 i40e_vsi_reset_stats(ctl_vsi);
5885
5886 /* create the VEB in the switch and move the VSI onto the VEB */
5887 ret = i40e_add_veb(veb, ctl_vsi);
5888 if (ret)
5889 goto end_reconstitute;
5890
5891 /* create the remaining VSIs attached to this VEB */
505682cd 5892 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5893 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5894 continue;
5895
5896 if (pf->vsi[v]->veb_idx == veb->idx) {
5897 struct i40e_vsi *vsi = pf->vsi[v];
5898 vsi->uplink_seid = veb->seid;
5899 ret = i40e_add_vsi(vsi);
5900 if (ret) {
5901 dev_info(&pf->pdev->dev,
5902 "rebuild of vsi_idx %d failed: %d\n",
5903 v, ret);
5904 goto end_reconstitute;
5905 }
5906 i40e_vsi_reset_stats(vsi);
5907 }
5908 }
5909
5910 /* create any VEBs attached to this VEB - RECURSION */
5911 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5912 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5913 pf->veb[veb_idx]->uplink_seid = veb->seid;
5914 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5915 if (ret)
5916 break;
5917 }
5918 }
5919
5920end_reconstitute:
5921 return ret;
5922}
5923
5924/**
5925 * i40e_get_capabilities - get info about the HW
5926 * @pf: the PF struct
5927 **/
5928static int i40e_get_capabilities(struct i40e_pf *pf)
5929{
5930 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5931 u16 data_size;
5932 int buf_len;
5933 int err;
5934
5935 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5936 do {
5937 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5938 if (!cap_buf)
5939 return -ENOMEM;
5940
5941 /* this loads the data into the hw struct for us */
5942 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5943 &data_size,
5944 i40e_aqc_opc_list_func_capabilities,
5945 NULL);
5946 /* data loaded, buffer no longer needed */
5947 kfree(cap_buf);
5948
5949 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5950 /* retry with a larger buffer */
5951 buf_len = data_size;
5952 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5953 dev_info(&pf->pdev->dev,
5954 "capability discovery failed: aq=%d\n",
5955 pf->hw.aq.asq_last_status);
5956 return -ENODEV;
5957 }
5958 } while (err);
5959
ac71b7ba
ASJ		 5960 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5961 (pf->hw.aq.fw_maj_ver < 2)) {
5962 pf->hw.func_caps.num_msix_vectors++;
5963 pf->hw.func_caps.num_msix_vectors_vf++;
5964 }
5965
41c445ff
JB		 5966 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5967 dev_info(&pf->pdev->dev,
5968 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5969 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5970 pf->hw.func_caps.num_msix_vectors,
5971 pf->hw.func_caps.num_msix_vectors_vf,
5972 pf->hw.func_caps.fd_filters_guaranteed,
5973 pf->hw.func_caps.fd_filters_best_effort,
5974 pf->hw.func_caps.num_tx_qp,
5975 pf->hw.func_caps.num_vsis);
5976
7134f9ce
JB		 5977#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5978 + pf->hw.func_caps.num_vfs)
5979 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5980 dev_info(&pf->pdev->dev,
5981 "got num_vsis %d, setting num_vsis to %d\n",
5982 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5983 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5984 }
5985
41c445ff
JB		 5986 return 0;
5987}
5988
cbf61325
ASJ		 5989static int i40e_vsi_clear(struct i40e_vsi *vsi);
5990
41c445ff 5991/**
cbf61325 5992 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5993 * @pf: board private structure
5994 **/
cbf61325 5995static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5996{
5997 struct i40e_vsi *vsi;
8a9eb7d3 5998 int i;
41c445ff 5999
407e063c
JB		 6000 /* quick workaround for an NVM issue that leaves a critical register
6001 * uninitialized
6002 */
6003 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6004 static const u32 hkey[] = {
6005 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6006 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6007 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6008 0x95b3a76d};
6009
6010 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6011 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6012 }
6013
cbf61325 6014 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6015 return;
6016
cbf61325 6017 /* find existing VSI and see if it needs configuring */
41c445ff 6018 vsi = NULL;
505682cd 6019 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6020 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6021 vsi = pf->vsi[i];
cbf61325
ASJ		 6022 break;
6023 }
6024 }
6025
6026 /* create a new VSI if none exists */
41c445ff 6027 if (!vsi) {
cbf61325
ASJ		 6028 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6029 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6030 if (!vsi) {
6031 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6032 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6033 return;
41c445ff 6034 }
cbf61325 6035 }
41c445ff 6036
8a9eb7d3 6037 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6038}
6039
6040/**
6041 * i40e_fdir_teardown - release the Flow Director resources
6042 * @pf: board private structure
6043 **/
6044static void i40e_fdir_teardown(struct i40e_pf *pf)
6045{
6046 int i;
6047
17a73f6b 6048 i40e_fdir_filter_exit(pf);
505682cd 6049 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6050 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6051 i40e_vsi_release(pf->vsi[i]);
6052 break;
6053 }
6054 }
6055}
6056
6057/**
f650a38b 6058 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6059 * @pf: board private structure
6060 *
f650a38b
ASJ		 6061 * Close up the VFs and other things in prep for pf Reset.
6062 **/
23cfbe07 6063static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6064{
41c445ff 6065 struct i40e_hw *hw = &pf->hw;
60442dea 6066 i40e_status ret = 0;
41c445ff
JB		 6067 u32 v;
6068
6069 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6070 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6071 return;
41c445ff 6072
69bfb110 6073 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6074
41c445ff
JB		 6075 /* quiesce the VSIs and their queues that are not already DOWN */
6076 i40e_pf_quiesce_all_vsi(pf);
6077
505682cd 6078 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6079 if (pf->vsi[v])
6080 pf->vsi[v]->seid = 0;
6081 }
6082
6083 i40e_shutdown_adminq(&pf->hw);
6084
f650a38b 6085 /* call shutdown HMC */
60442dea
SN		 6086 if (hw->hmc.hmc_obj) {
6087 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6088 if (ret)
60442dea
SN		 6089 dev_warn(&pf->pdev->dev,
6090 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6091 }
f650a38b
ASJ		 6092}
6093
44033fac
JB		 6094/**
6095 * i40e_send_version - update firmware with driver version
6096 * @pf: PF struct
6097 */
6098static void i40e_send_version(struct i40e_pf *pf)
6099{
6100 struct i40e_driver_version dv;
6101
6102 dv.major_version = DRV_VERSION_MAJOR;
6103 dv.minor_version = DRV_VERSION_MINOR;
6104 dv.build_version = DRV_VERSION_BUILD;
6105 dv.subbuild_version = 0;
35a7d804 6106 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6107 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6108}
6109
f650a38b 6110/**
4dda12e6 6111 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6112 * @pf: board private structure
bc7d338f 6113 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6114 **/
bc7d338f 6115static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6116{
f650a38b 6117 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6118 u8 set_fc_aq_fail = 0;
f650a38b
ASJ		 6119 i40e_status ret;
6120 u32 v;
6121
41c445ff
JB		 6122 /* Now we wait for GRST to settle out.
6123 * We don't have to delete the VEBs or VSIs from the hw switch
6124 * because the reset will make them disappear.
6125 */
6126 ret = i40e_pf_reset(hw);
b5565400 6127 if (ret) {
41c445ff 6128 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6129 set_bit(__I40E_RESET_FAILED, &pf->state);
6130 goto clear_recovery;
b5565400 6131 }
41c445ff
JB		 6132 pf->pfr_count++;
6133
6134 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6135 goto clear_recovery;
69bfb110 6136 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6137
6138 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6139 ret = i40e_init_adminq(&pf->hw);
6140 if (ret) {
6141 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
a316f651 6142 goto clear_recovery;
41c445ff
JB		 6143 }
6144
4eb3f768
SN		 6145 /* re-verify the eeprom if we just had an EMP reset */
6146 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
6147 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
6148 i40e_verify_eeprom(pf);
6149 }
6150
e78ac4bf 6151 i40e_clear_pxe_mode(hw);
41c445ff
JB		 6152 ret = i40e_get_capabilities(pf);
6153 if (ret) {
6154 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
6155 ret);
6156 goto end_core_reset;
6157 }
6158
41c445ff
JB		 6159 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6160 hw->func_caps.num_rx_qp,
6161 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6162 if (ret) {
6163 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6164 goto end_core_reset;
6165 }
6166 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6167 if (ret) {
6168 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6169 goto end_core_reset;
6170 }
6171
4e3b35b0
NP		 6172#ifdef CONFIG_I40E_DCB
6173 ret = i40e_init_pf_dcb(pf);
6174 if (ret) {
6175 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
6176 goto end_core_reset;
6177 }
6178#endif /* CONFIG_I40E_DCB */
38e00438
VD		 6179#ifdef I40E_FCOE
6180 ret = i40e_init_pf_fcoe(pf);
6181 if (ret)
6182 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", ret);
4e3b35b0 6183
38e00438 6184#endif
41c445ff 6185 /* do basic switch setup */
bc7d338f 6186 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6187 if (ret)
6188 goto end_core_reset;
6189
7e2453fe
JB		 6190 /* driver is only interested in link up/down and module qualification
6191 * reports from firmware
6192 */
6193 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6194 I40E_AQ_EVENT_LINK_UPDOWN |
6195 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6196 if (ret)
6197 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", ret);
6198
cafa2ee6
ASJ		 6199 /* make sure our flow control settings are restored */
6200 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6201 if (ret)
6202 dev_info(&pf->pdev->dev, "set fc fail, aq_err %d\n", ret);
6203
41c445ff
JB		 6204 /* Rebuild the VSIs and VEBs that existed before reset.
6205 * They are still in our local switch element arrays, so only
6206 * need to rebuild the switch model in the HW.
6207 *
6208 * If there were VEBs but the reconstitution failed, we'll try
6209 * try to recover minimal use by getting the basic PF VSI working.
6210 */
6211 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6212 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6213 /* find the one VEB connected to the MAC, and find orphans */
6214 for (v = 0; v < I40E_MAX_VEB; v++) {
6215 if (!pf->veb[v])
6216 continue;
6217
6218 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6219 pf->veb[v]->uplink_seid == 0) {
6220 ret = i40e_reconstitute_veb(pf->veb[v]);
6221
6222 if (!ret)
6223 continue;
6224
6225 /* If Main VEB failed, we're in deep doodoo,
6226 * so give up rebuilding the switch and set up
6227 * for minimal rebuild of PF VSI.
6228 * If orphan failed, we'll report the error
6229 * but try to keep going.
6230 */
6231 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6232 dev_info(&pf->pdev->dev,
6233 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6234 ret);
6235 pf->vsi[pf->lan_vsi]->uplink_seid
6236 = pf->mac_seid;
6237 break;
6238 } else if (pf->veb[v]->uplink_seid == 0) {
6239 dev_info(&pf->pdev->dev,
6240 "rebuild of orphan VEB failed: %d\n",
6241 ret);
6242 }
6243 }
6244 }
6245 }
6246
6247 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6248 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6249 /* no VEB, so rebuild only the Main VSI */
6250 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6251 if (ret) {
6252 dev_info(&pf->pdev->dev,
6253 "rebuild of Main VSI failed: %d\n", ret);
6254 goto end_core_reset;
6255 }
6256 }
6257
cafa2ee6
ASJ		 6258 msleep(75);
6259 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6260 if (ret) {
6261 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
6262 pf->hw.aq.asq_last_status);
6263 }
6264
41c445ff
JB		 6265 /* reinit the misc interrupt */
6266 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6267 ret = i40e_setup_misc_vector(pf);
6268
6269 /* restart the VSIs that were rebuilt and running before the reset */
6270 i40e_pf_unquiesce_all_vsi(pf);
6271
69f64b2b
MW		 6272 if (pf->num_alloc_vfs) {
6273 for (v = 0; v < pf->num_alloc_vfs; v++)
6274 i40e_reset_vf(&pf->vf[v], true);
6275 }
6276
41c445ff 6277 /* tell the firmware that we're starting */
44033fac 6278 i40e_send_version(pf);
41c445ff
JB		 6279
6280end_core_reset:
a316f651
ASJ		 6281 clear_bit(__I40E_RESET_FAILED, &pf->state);
6282clear_recovery:
41c445ff
JB		 6283 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6284}
6285
f650a38b
ASJ		 6286/**
6287 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
6288 * @pf: board private structure
6289 *
6290 * Close up the VFs and other things in prep for a Core Reset,
6291 * then get ready to rebuild the world.
6292 **/
6293static void i40e_handle_reset_warning(struct i40e_pf *pf)
6294{
23cfbe07
SN		 6295 i40e_prep_for_reset(pf);
6296 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6297}
6298
41c445ff
JB		 6299/**
6300 * i40e_handle_mdd_event
6301 * @pf: pointer to the pf structure
6302 *
6303 * Called from the MDD irq handler to identify possibly malicious vfs
6304 **/
6305static void i40e_handle_mdd_event(struct i40e_pf *pf)
6306{
6307 struct i40e_hw *hw = &pf->hw;
6308 bool mdd_detected = false;
df430b12 6309 bool pf_mdd_detected = false;
41c445ff
JB		 6310 struct i40e_vf *vf;
6311 u32 reg;
6312 int i;
6313
6314 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6315 return;
6316
6317 /* find what triggered the MDD event */
6318 reg = rd32(hw, I40E_GL_MDET_TX);
6319 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6320 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6321 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6322 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6323 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6324 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6325 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6326 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6327 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6328 pf->hw.func_caps.base_queue;
faf32978
JB		 6329 if (netif_msg_tx_err(pf))
6330 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
6331 event, queue, pf_num, vf_num);
41c445ff
JB		 6332 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6333 mdd_detected = true;
6334 }
6335 reg = rd32(hw, I40E_GL_MDET_RX);
6336 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6337 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6338 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6339 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6340 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6341 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6342 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6343 pf->hw.func_caps.base_queue;
faf32978
JB		 6344 if (netif_msg_rx_err(pf))
6345 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6346 event, queue, func);
41c445ff
JB		 6347 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6348 mdd_detected = true;
6349 }
6350
df430b12
NP		 6351 if (mdd_detected) {
6352 reg = rd32(hw, I40E_PF_MDET_TX);
6353 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6354 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6355 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6356 pf_mdd_detected = true;
6357 }
6358 reg = rd32(hw, I40E_PF_MDET_RX);
6359 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6360 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6361 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6362 pf_mdd_detected = true;
6363 }
6364 /* Queue belongs to the PF, initiate a reset */
6365 if (pf_mdd_detected) {
6366 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6367 i40e_service_event_schedule(pf);
6368 }
6369 }
6370
41c445ff
JB		 6371 /* see if one of the VFs needs its hand slapped */
6372 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6373 vf = &(pf->vf[i]);
6374 reg = rd32(hw, I40E_VP_MDET_TX(i));
6375 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6376 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6377 vf->num_mdd_events++;
faf32978
JB		 6378 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6379 i);
41c445ff
JB		 6380 }
6381
6382 reg = rd32(hw, I40E_VP_MDET_RX(i));
6383 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6384 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6385 vf->num_mdd_events++;
faf32978
JB		 6386 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6387 i);
41c445ff
JB		 6388 }
6389
6390 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6391 dev_info(&pf->pdev->dev,
6392 "Too many MDD events on VF %d, disabled\n", i);
6393 dev_info(&pf->pdev->dev,
6394 "Use PF Control I/F to re-enable the VF\n");
6395 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6396 }
6397 }
6398
6399 /* re-enable mdd interrupt cause */
6400 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6401 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6402 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6403 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6404 i40e_flush(hw);
6405}
6406
a1c9a9d9
JK		 6407#ifdef CONFIG_I40E_VXLAN
6408/**
6409 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6410 * @pf: board private structure
6411 **/
6412static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6413{
a1c9a9d9
JK		 6414 struct i40e_hw *hw = &pf->hw;
6415 i40e_status ret;
6416 u8 filter_index;
6417 __be16 port;
6418 int i;
6419
6420 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
6421 return;
6422
6423 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
6424
6425 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6426 if (pf->pending_vxlan_bitmap & (1 << i)) {
6427 pf->pending_vxlan_bitmap &= ~(1 << i);
6428 port = pf->vxlan_ports[i];
6429 ret = port ?
6430 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 6431 I40E_AQC_TUNNEL_TYPE_VXLAN,
6432 &filter_index, NULL)
6433 : i40e_aq_del_udp_tunnel(hw, i, NULL);
6434
6435 if (ret) {
6436 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
6437 port ? "adding" : "deleting",
6438 ntohs(port), port ? i : i);
6439
6440 pf->vxlan_ports[i] = 0;
6441 } else {
6442 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
6443 port ? "Added" : "Deleted",
6444 ntohs(port), port ? i : filter_index);
6445 }
6446 }
6447 }
6448}
6449
6450#endif
41c445ff
JB		 6451/**
6452 * i40e_service_task - Run the driver's async subtasks
6453 * @work: pointer to work_struct containing our data
6454 **/
6455static void i40e_service_task(struct work_struct *work)
6456{
6457 struct i40e_pf *pf = container_of(work,
6458 struct i40e_pf,
6459 service_task);
6460 unsigned long start_time = jiffies;
6461
e57a2fea
SN		 6462 /* don't bother with service tasks if a reset is in progress */
6463 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6464 i40e_service_event_complete(pf);
6465 return;
6466 }
6467
41c445ff
JB		 6468 i40e_reset_subtask(pf);
6469 i40e_handle_mdd_event(pf);
6470 i40e_vc_process_vflr_event(pf);
6471 i40e_watchdog_subtask(pf);
6472 i40e_fdir_reinit_subtask(pf);
41c445ff 6473 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 6474#ifdef CONFIG_I40E_VXLAN
6475 i40e_sync_vxlan_filters_subtask(pf);
6476#endif
41c445ff
JB		 6477 i40e_clean_adminq_subtask(pf);
6478
6479 i40e_service_event_complete(pf);
6480
6481 /* If the tasks have taken longer than one timer cycle or there
6482 * is more work to be done, reschedule the service task now
6483 * rather than wait for the timer to tick again.
6484 */
6485 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
6486 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
6487 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
6488 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
6489 i40e_service_event_schedule(pf);
6490}
6491
6492/**
6493 * i40e_service_timer - timer callback
6494 * @data: pointer to PF struct
6495 **/
6496static void i40e_service_timer(unsigned long data)
6497{
6498 struct i40e_pf *pf = (struct i40e_pf *)data;
6499
6500 mod_timer(&pf->service_timer,
6501 round_jiffies(jiffies + pf->service_timer_period));
6502 i40e_service_event_schedule(pf);
6503}
6504
6505/**
6506 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
6507 * @vsi: the VSI being configured
6508 **/
6509static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
6510{
6511 struct i40e_pf *pf = vsi->back;
6512
6513 switch (vsi->type) {
6514 case I40E_VSI_MAIN:
6515 vsi->alloc_queue_pairs = pf->num_lan_qps;
6516 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6517 I40E_REQ_DESCRIPTOR_MULTIPLE);
6518 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6519 vsi->num_q_vectors = pf->num_lan_msix;
6520 else
6521 vsi->num_q_vectors = 1;
6522
6523 break;
6524
6525 case I40E_VSI_FDIR:
6526 vsi->alloc_queue_pairs = 1;
6527 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6528 I40E_REQ_DESCRIPTOR_MULTIPLE);
6529 vsi->num_q_vectors = 1;
6530 break;
6531
6532 case I40E_VSI_VMDQ2:
6533 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6534 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6535 I40E_REQ_DESCRIPTOR_MULTIPLE);
6536 vsi->num_q_vectors = pf->num_vmdq_msix;
6537 break;
6538
6539 case I40E_VSI_SRIOV:
6540 vsi->alloc_queue_pairs = pf->num_vf_qps;
6541 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6542 I40E_REQ_DESCRIPTOR_MULTIPLE);
6543 break;
6544
38e00438
VD		 6545#ifdef I40E_FCOE
6546 case I40E_VSI_FCOE:
6547 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
6548 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6549 I40E_REQ_DESCRIPTOR_MULTIPLE);
6550 vsi->num_q_vectors = pf->num_fcoe_msix;
6551 break;
6552
6553#endif /* I40E_FCOE */
41c445ff
JB		 6554 default:
6555 WARN_ON(1);
6556 return -ENODATA;
6557 }
6558
6559 return 0;
6560}
6561
f650a38b
ASJ		 6562/**
6563 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6564 * @type: VSI pointer
bc7d338f 6565 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6566 *
6567 * On error: returns error code (negative)
6568 * On success: returns 0
6569 **/
bc7d338f 6570static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6571{
6572 int size;
6573 int ret = 0;
6574
ac6c5e3d 6575 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6576 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6577 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6578 if (!vsi->tx_rings)
6579 return -ENOMEM;
f650a38b
ASJ		 6580 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6581
bc7d338f
ASJ		 6582 if (alloc_qvectors) {
6583 /* allocate memory for q_vector pointers */
f57e4fbd 6584 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 6585 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6586 if (!vsi->q_vectors) {
6587 ret = -ENOMEM;
6588 goto err_vectors;
6589 }
f650a38b
ASJ		 6590 }
6591 return ret;
6592
6593err_vectors:
6594 kfree(vsi->tx_rings);
6595 return ret;
6596}
6597
41c445ff
JB		 6598/**
6599 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6600 * @pf: board private structure
6601 * @type: type of VSI
6602 *
6603 * On error: returns error code (negative)
6604 * On success: returns vsi index in PF (positive)
6605 **/
6606static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6607{
6608 int ret = -ENODEV;
6609 struct i40e_vsi *vsi;
6610 int vsi_idx;
6611 int i;
6612
6613 /* Need to protect the allocation of the VSIs at the PF level */
6614 mutex_lock(&pf->switch_mutex);
6615
6616 /* VSI list may be fragmented if VSI creation/destruction has
6617 * been happening. We can afford to do a quick scan to look
6618 * for any free VSIs in the list.
6619 *
6620 * find next empty vsi slot, looping back around if necessary
6621 */
6622 i = pf->next_vsi;
505682cd 6623 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6624 i++;
505682cd 6625 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6626 i = 0;
6627 while (i < pf->next_vsi && pf->vsi[i])
6628 i++;
6629 }
6630
505682cd 6631 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6632 vsi_idx = i; /* Found one! */
6633 } else {
6634 ret = -ENODEV;
493fb300 6635 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6636 }
6637 pf->next_vsi = ++i;
6638
6639 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6640 if (!vsi) {
6641 ret = -ENOMEM;
493fb300 6642 goto unlock_pf;
41c445ff
JB		 6643 }
6644 vsi->type = type;
6645 vsi->back = pf;
6646 set_bit(__I40E_DOWN, &vsi->state);
6647 vsi->flags = 0;
6648 vsi->idx = vsi_idx;
6649 vsi->rx_itr_setting = pf->rx_itr_default;
6650 vsi->tx_itr_setting = pf->tx_itr_default;
6651 vsi->netdev_registered = false;
6652 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6653 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6654 vsi->irqs_ready = false;
41c445ff 6655
9f65e15b
AD		 6656 ret = i40e_set_num_rings_in_vsi(vsi);
6657 if (ret)
6658 goto err_rings;
6659
bc7d338f 6660 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6661 if (ret)
9f65e15b 6662 goto err_rings;
493fb300 6663
41c445ff
JB		 6664 /* Setup default MSIX irq handler for VSI */
6665 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6666
6667 pf->vsi[vsi_idx] = vsi;
6668 ret = vsi_idx;
493fb300
AD		 6669 goto unlock_pf;
6670
9f65e15b 6671err_rings:
493fb300
AD		 6672 pf->next_vsi = i - 1;
6673 kfree(vsi);
6674unlock_pf:
41c445ff
JB		 6675 mutex_unlock(&pf->switch_mutex);
6676 return ret;
6677}
6678
f650a38b
ASJ		 6679/**
6680 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6681 * @type: VSI pointer
bc7d338f 6682 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6683 *
6684 * On error: returns error code (negative)
6685 * On success: returns 0
6686 **/
bc7d338f 6687static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6688{
6689 /* free the ring and vector containers */
bc7d338f
ASJ		 6690 if (free_qvectors) {
6691 kfree(vsi->q_vectors);
6692 vsi->q_vectors = NULL;
6693 }
f650a38b
ASJ		 6694 kfree(vsi->tx_rings);
6695 vsi->tx_rings = NULL;
6696 vsi->rx_rings = NULL;
6697}
6698
41c445ff
JB		 6699/**
6700 * i40e_vsi_clear - Deallocate the VSI provided
6701 * @vsi: the VSI being un-configured
6702 **/
6703static int i40e_vsi_clear(struct i40e_vsi *vsi)
6704{
6705 struct i40e_pf *pf;
6706
6707 if (!vsi)
6708 return 0;
6709
6710 if (!vsi->back)
6711 goto free_vsi;
6712 pf = vsi->back;
6713
6714 mutex_lock(&pf->switch_mutex);
6715 if (!pf->vsi[vsi->idx]) {
6716 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6717 vsi->idx, vsi->idx, vsi, vsi->type);
6718 goto unlock_vsi;
6719 }
6720
6721 if (pf->vsi[vsi->idx] != vsi) {
6722 dev_err(&pf->pdev->dev,
6723 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6724 pf->vsi[vsi->idx]->idx,
6725 pf->vsi[vsi->idx],
6726 pf->vsi[vsi->idx]->type,
6727 vsi->idx, vsi, vsi->type);
6728 goto unlock_vsi;
6729 }
6730
6731 /* updates the pf for this cleared vsi */
6732 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6733 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6734
bc7d338f 6735 i40e_vsi_free_arrays(vsi, true);
493fb300 6736
41c445ff
JB		 6737 pf->vsi[vsi->idx] = NULL;
6738 if (vsi->idx < pf->next_vsi)
6739 pf->next_vsi = vsi->idx;
6740
6741unlock_vsi:
6742 mutex_unlock(&pf->switch_mutex);
6743free_vsi:
6744 kfree(vsi);
6745
6746 return 0;
6747}
6748
9f65e15b
AD		 6749/**
6750 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6751 * @vsi: the VSI being cleaned
6752 **/
be1d5eea 6753static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6754{
6755 int i;
6756
8e9dca53 6757 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6758 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6759 kfree_rcu(vsi->tx_rings[i], rcu);
6760 vsi->tx_rings[i] = NULL;
6761 vsi->rx_rings[i] = NULL;
6762 }
be1d5eea 6763 }
9f65e15b
AD		 6764}
6765
41c445ff
JB		 6766/**
6767 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6768 * @vsi: the VSI being configured
6769 **/
6770static int i40e_alloc_rings(struct i40e_vsi *vsi)
6771{
e7046ee1 6772 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6773 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6774 int i;
6775
41c445ff 6776 /* Set basic values in the rings to be used later during open() */
d7397644 6777 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6778 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6779 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6780 if (!tx_ring)
6781 goto err_out;
41c445ff
JB		 6782
6783 tx_ring->queue_index = i;
6784 tx_ring->reg_idx = vsi->base_queue + i;
6785 tx_ring->ring_active = false;
6786 tx_ring->vsi = vsi;
6787 tx_ring->netdev = vsi->netdev;
6788 tx_ring->dev = &pf->pdev->dev;
6789 tx_ring->count = vsi->num_desc;
6790 tx_ring->size = 0;
6791 tx_ring->dcb_tc = 0;
9f65e15b 6792 vsi->tx_rings[i] = tx_ring;
41c445ff 6793
9f65e15b 6794 rx_ring = &tx_ring[1];
41c445ff
JB		 6795 rx_ring->queue_index = i;
6796 rx_ring->reg_idx = vsi->base_queue + i;
6797 rx_ring->ring_active = false;
6798 rx_ring->vsi = vsi;
6799 rx_ring->netdev = vsi->netdev;
6800 rx_ring->dev = &pf->pdev->dev;
6801 rx_ring->count = vsi->num_desc;
6802 rx_ring->size = 0;
6803 rx_ring->dcb_tc = 0;
6804 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6805 set_ring_16byte_desc_enabled(rx_ring);
6806 else
6807 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6808 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6809 }
6810
6811 return 0;
9f65e15b
AD		 6812
6813err_out:
6814 i40e_vsi_clear_rings(vsi);
6815 return -ENOMEM;
41c445ff
JB		 6816}
6817
6818/**
6819 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6820 * @pf: board private structure
6821 * @vectors: the number of MSI-X vectors to request
6822 *
6823 * Returns the number of vectors reserved, or error
6824 **/
6825static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6826{
7b37f376
AG		 6827 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6828 I40E_MIN_MSIX, vectors);
6829 if (vectors < 0) {
41c445ff 6830 dev_info(&pf->pdev->dev,
7b37f376 6831 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6832 vectors = 0;
6833 }
6834
6835 return vectors;
6836}
6837
6838/**
6839 * i40e_init_msix - Setup the MSIX capability
6840 * @pf: board private structure
6841 *
6842 * Work with the OS to set up the MSIX vectors needed.
6843 *
6844 * Returns 0 on success, negative on failure
6845 **/
6846static int i40e_init_msix(struct i40e_pf *pf)
6847{
6848 i40e_status err = 0;
6849 struct i40e_hw *hw = &pf->hw;
c135b0de 6850 int other_vecs = 0;
41c445ff
JB		 6851 int v_budget, i;
6852 int vec;
6853
6854 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6855 return -ENODEV;
6856
6857 /* The number of vectors we'll request will be comprised of:
6858 * - Add 1 for "other" cause for Admin Queue events, etc.
6859 * - The number of LAN queue pairs
f8ff1464
ASJ		 6860 * - Queues being used for RSS.
6861 * We don't need as many as max_rss_size vectors.
6862 * use rss_size instead in the calculation since that
6863 * is governed by number of cpus in the system.
6864 * - assumes symmetric Tx/Rx pairing
41c445ff 6865 * - The number of VMDq pairs
38e00438
VD		 6866#ifdef I40E_FCOE
6867 * - The number of FCOE qps.
6868#endif
41c445ff
JB		 6869 * Once we count this up, try the request.
6870 *
6871 * If we can't get what we want, we'll simplify to nearly nothing
6872 * and try again. If that still fails, we punt.
6873 */
f8ff1464 6874 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff 6875 pf->num_vmdq_msix = pf->num_vmdq_qps;
c135b0de
SN		 6876 other_vecs = 1;
6877 other_vecs += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6878 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
c135b0de 6879 other_vecs++;
41c445ff 6880
38e00438
VD		 6881#ifdef I40E_FCOE
6882 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6883 pf->num_fcoe_msix = pf->num_fcoe_qps;
6884 v_budget += pf->num_fcoe_msix;
6885 }
6886
6887#endif
41c445ff 6888 /* Scale down if necessary, and the rings will share vectors */
c135b0de
SN		 6889 pf->num_lan_msix = min_t(int, pf->num_lan_msix,
6890 (hw->func_caps.num_msix_vectors - other_vecs));
6891 v_budget = pf->num_lan_msix + other_vecs;
41c445ff
JB		 6892
6893 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6894 GFP_KERNEL);
6895 if (!pf->msix_entries)
6896 return -ENOMEM;
6897
6898 for (i = 0; i < v_budget; i++)
6899 pf->msix_entries[i].entry = i;
6900 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6901
6902 if (vec != v_budget) {
6903 /* If we have limited resources, we will start with no vectors
6904 * for the special features and then allocate vectors to some
6905 * of these features based on the policy and at the end disable
6906 * the features that did not get any vectors.
6907 */
38e00438
VD		 6908#ifdef I40E_FCOE
6909 pf->num_fcoe_qps = 0;
6910 pf->num_fcoe_msix = 0;
6911#endif
a34977ba
ASJ		 6912 pf->num_vmdq_msix = 0;
6913 }
6914
41c445ff
JB		 6915 if (vec < I40E_MIN_MSIX) {
6916 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6917 kfree(pf->msix_entries);
6918 pf->msix_entries = NULL;
6919 return -ENODEV;
6920
6921 } else if (vec == I40E_MIN_MSIX) {
6922 /* Adjust for minimal MSIX use */
41c445ff
JB		 6923 pf->num_vmdq_vsis = 0;
6924 pf->num_vmdq_qps = 0;
41c445ff
JB		 6925 pf->num_lan_qps = 1;
6926 pf->num_lan_msix = 1;
6927
6928 } else if (vec != v_budget) {
a34977ba
ASJ		 6929 /* reserve the misc vector */
6930 vec--;
6931
41c445ff
JB		 6932 /* Scale vector usage down */
6933 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6934 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6935
6936 /* partition out the remaining vectors */
6937 switch (vec) {
6938 case 2:
41c445ff
JB		 6939 pf->num_lan_msix = 1;
6940 break;
6941 case 3:
38e00438
VD		 6942#ifdef I40E_FCOE
6943 /* give one vector to FCoE */
6944 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6945 pf->num_lan_msix = 1;
6946 pf->num_fcoe_msix = 1;
6947 }
6948#else
41c445ff 6949 pf->num_lan_msix = 2;
38e00438 6950#endif
41c445ff
JB		 6951 break;
6952 default:
38e00438
VD		 6953#ifdef I40E_FCOE
6954 /* give one vector to FCoE */
6955 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
6956 pf->num_fcoe_msix = 1;
6957 vec--;
6958 }
6959#endif
41c445ff
JB		 6960 pf->num_lan_msix = min_t(int, (vec / 2),
6961 pf->num_lan_qps);
6962 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6963 I40E_DEFAULT_NUM_VMDQ_VSI);
6964 break;
6965 }
6966 }
6967
a34977ba
ASJ		 6968 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6969 (pf->num_vmdq_msix == 0)) {
6970 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6971 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6972 }
38e00438
VD		 6973#ifdef I40E_FCOE
6974
6975 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
6976 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
6977 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
6978 }
6979#endif
41c445ff
JB		 6980 return err;
6981}
6982
493fb300 6983/**
90e04070 6984 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6985 * @vsi: the VSI being configured
6986 * @v_idx: index of the vector in the vsi struct
6987 *
6988 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6989 **/
90e04070 6990static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6991{
6992 struct i40e_q_vector *q_vector;
6993
6994 /* allocate q_vector */
6995 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6996 if (!q_vector)
6997 return -ENOMEM;
6998
6999 q_vector->vsi = vsi;
7000 q_vector->v_idx = v_idx;
7001 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7002 if (vsi->netdev)
7003 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7004 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7005
cd0b6fa6
AD		 7006 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7007 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7008
493fb300
AD		 7009 /* tie q_vector and vsi together */
7010 vsi->q_vectors[v_idx] = q_vector;
7011
7012 return 0;
7013}
7014
41c445ff 7015/**
90e04070 7016 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7017 * @vsi: the VSI being configured
7018 *
7019 * We allocate one q_vector per queue interrupt. If allocation fails we
7020 * return -ENOMEM.
7021 **/
90e04070 7022static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7023{
7024 struct i40e_pf *pf = vsi->back;
7025 int v_idx, num_q_vectors;
493fb300 7026 int err;
41c445ff
JB		 7027
7028 /* if not MSIX, give the one vector only to the LAN VSI */
7029 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7030 num_q_vectors = vsi->num_q_vectors;
7031 else if (vsi == pf->vsi[pf->lan_vsi])
7032 num_q_vectors = 1;
7033 else
7034 return -EINVAL;
7035
41c445ff 7036 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7037 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7038 if (err)
7039 goto err_out;
41c445ff
JB		 7040 }
7041
7042 return 0;
493fb300
AD		 7043
7044err_out:
7045 while (v_idx--)
7046 i40e_free_q_vector(vsi, v_idx);
7047
7048 return err;
41c445ff
JB		 7049}
7050
7051/**
7052 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7053 * @pf: board private structure to initialize
7054 **/
7055static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
7056{
7057 int err = 0;
7058
7059 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7060 err = i40e_init_msix(pf);
7061 if (err) {
60ea5f83 7062 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7063#ifdef I40E_FCOE
7064 I40E_FLAG_FCOE_ENABLED |
7065#endif
60ea5f83 7066 I40E_FLAG_RSS_ENABLED |
4d9b6043 7067 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7068 I40E_FLAG_SRIOV_ENABLED |
7069 I40E_FLAG_FD_SB_ENABLED |
7070 I40E_FLAG_FD_ATR_ENABLED |
7071 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7072
7073 /* rework the queue expectations without MSIX */
7074 i40e_determine_queue_usage(pf);
7075 }
7076 }
7077
7078 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7079 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7080 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 7081 err = pci_enable_msi(pf->pdev);
7082 if (err) {
958a3e3b 7083 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 7084 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7085 }
7086 }
7087
958a3e3b 7088 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7089 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7090
41c445ff
JB		 7091 /* track first vector for misc interrupts */
7092 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
7093}
7094
7095/**
7096 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7097 * @pf: board private structure
7098 *
7099 * This sets up the handler for MSIX 0, which is used to manage the
7100 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7101 * when in MSI or Legacy interrupt mode.
7102 **/
7103static int i40e_setup_misc_vector(struct i40e_pf *pf)
7104{
7105 struct i40e_hw *hw = &pf->hw;
7106 int err = 0;
7107
7108 /* Only request the irq if this is the first time through, and
7109 * not when we're rebuilding after a Reset
7110 */
7111 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7112 err = request_irq(pf->msix_entries[0].vector,
7113 i40e_intr, 0, pf->misc_int_name, pf);
7114 if (err) {
7115 dev_info(&pf->pdev->dev,
77fa28be
CS		 7116 "request_irq for %s failed: %d\n",
7117 pf->misc_int_name, err);
41c445ff
JB		 7118 return -EFAULT;
7119 }
7120 }
7121
7122 i40e_enable_misc_int_causes(hw);
7123
7124 /* associate no queues to the misc vector */
7125 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7126 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7127
7128 i40e_flush(hw);
7129
7130 i40e_irq_dynamic_enable_icr0(pf);
7131
7132 return err;
7133}
7134
7135/**
7136 * i40e_config_rss - Prepare for RSS if used
7137 * @pf: board private structure
7138 **/
7139static int i40e_config_rss(struct i40e_pf *pf)
7140{
22f258a1 7141 u32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];
4617e8c0
ASJ		 7142 struct i40e_hw *hw = &pf->hw;
7143 u32 lut = 0;
7144 int i, j;
7145 u64 hena;
e157ea30 7146 u32 reg_val;
41c445ff 7147
22f258a1 7148 netdev_rss_key_fill(rss_key, sizeof(rss_key));
41c445ff 7149 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
22f258a1 7150 wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);
41c445ff
JB		 7151
7152 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
7153 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
7154 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 7155 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 7156 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
7157 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
7158
e157ea30
CW		 7159 /* Check capability and Set table size and register per hw expectation*/
7160 reg_val = rd32(hw, I40E_PFQF_CTL_0);
7161 if (hw->func_caps.rss_table_size == 512) {
7162 reg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7163 pf->rss_table_size = 512;
7164 } else {
7165 pf->rss_table_size = 128;
7166 reg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;
7167 }
7168 wr32(hw, I40E_PFQF_CTL_0, reg_val);
7169
41c445ff 7170 /* Populate the LUT with max no. of queues in round robin fashion */
e157ea30 7171 for (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {
41c445ff
JB		 7172
7173 /* The assumption is that lan qp count will be the highest
7174 * qp count for any PF VSI that needs RSS.
7175 * If multiple VSIs need RSS support, all the qp counts
7176 * for those VSIs should be a power of 2 for RSS to work.
7177 * If LAN VSI is the only consumer for RSS then this requirement
7178 * is not necessary.
7179 */
7180 if (j == pf->rss_size)
7181 j = 0;
7182 /* lut = 4-byte sliding window of 4 lut entries */
7183 lut = (lut << 8) | (j &
7184 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
7185 /* On i = 3, we have 4 entries in lut; write to the register */
7186 if ((i & 3) == 3)
7187 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
7188 }
7189 i40e_flush(hw);
7190
7191 return 0;
7192}
7193
f8ff1464
ASJ		 7194/**
7195 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
7196 * @pf: board private structure
7197 * @queue_count: the requested queue count for rss.
7198 *
7199 * returns 0 if rss is not enabled, if enabled returns the final rss queue
7200 * count which may be different from the requested queue count.
7201 **/
7202int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
7203{
7204 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
7205 return 0;
7206
7207 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 7208
7209 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 7210 i40e_prep_for_reset(pf);
7211
f8ff1464
ASJ		 7212 pf->rss_size = queue_count;
7213
7214 i40e_reset_and_rebuild(pf, true);
7215 i40e_config_rss(pf);
7216 }
7217 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
7218 return pf->rss_size;
7219}
7220
41c445ff
JB		 7221/**
7222 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
7223 * @pf: board private structure to initialize
7224 *
7225 * i40e_sw_init initializes the Adapter private data structure.
7226 * Fields are initialized based on PCI device information and
7227 * OS network device settings (MTU size).
7228 **/
7229static int i40e_sw_init(struct i40e_pf *pf)
7230{
7231 int err = 0;
7232 int size;
7233
7234 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
7235 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 7236 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 7237 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
7238 if (I40E_DEBUG_USER & debug)
7239 pf->hw.debug_mask = debug;
7240 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
7241 I40E_DEFAULT_MSG_ENABLE);
7242 }
7243
7244 /* Set default capability flags */
7245 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
7246 I40E_FLAG_MSI_ENABLED |
7247 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 7248 I40E_FLAG_RX_1BUF_ENABLED;
7249
ca99eb99
MW		 7250 /* Set default ITR */
7251 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
7252 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
7253
7134f9ce
JB		 7254 /* Depending on PF configurations, it is possible that the RSS
7255 * maximum might end up larger than the available queues
7256 */
41c445ff 7257 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
ec9a7db7 7258 pf->rss_size = 1;
7134f9ce
JB		 7259 pf->rss_size_max = min_t(int, pf->rss_size_max,
7260 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 7261 if (pf->hw.func_caps.rss) {
7262 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 7263 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 7264 }
7265
2050bc65
CS		 7266 /* MFP mode enabled */
7267 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
7268 pf->flags |= I40E_FLAG_MFP_ENABLED;
7269 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
7270 }
7271
cbf61325
ASJ		 7272 /* FW/NVM is not yet fixed in this regard */
7273 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
7274 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
7275 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7276 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 7277 /* Setup a counter for fd_atr per pf */
7278 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 7279 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 7280 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 7281 /* Setup a counter for fd_sb per pf */
7282 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 7283 } else {
7284 dev_info(&pf->pdev->dev,
0b67584f 7285 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 7286 }
cbf61325
ASJ		 7287 pf->fdir_pf_filter_count =
7288 pf->hw.func_caps.fd_filters_guaranteed;
7289 pf->hw.fdir_shared_filter_count =
7290 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 7291 }
7292
7293 if (pf->hw.func_caps.vmdq) {
7294 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
7295 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
7296 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
7297 }
7298
38e00438
VD		 7299#ifdef I40E_FCOE
7300 err = i40e_init_pf_fcoe(pf);
7301 if (err)
7302 dev_info(&pf->pdev->dev, "init_pf_fcoe failed: %d\n", err);
7303
7304#endif /* I40E_FCOE */
41c445ff
JB		 7305#ifdef CONFIG_PCI_IOV
7306 if (pf->hw.func_caps.num_vfs) {
7307 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
7308 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
7309 pf->num_req_vfs = min_t(int,
7310 pf->hw.func_caps.num_vfs,
7311 I40E_MAX_VF_COUNT);
7312 }
7313#endif /* CONFIG_PCI_IOV */
7314 pf->eeprom_version = 0xDEAD;
7315 pf->lan_veb = I40E_NO_VEB;
7316 pf->lan_vsi = I40E_NO_VSI;
7317
7318 /* set up queue assignment tracking */
7319 size = sizeof(struct i40e_lump_tracking)
7320 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
7321 pf->qp_pile = kzalloc(size, GFP_KERNEL);
7322 if (!pf->qp_pile) {
7323 err = -ENOMEM;
7324 goto sw_init_done;
7325 }
7326 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
7327 pf->qp_pile->search_hint = 0;
7328
7329 /* set up vector assignment tracking */
7330 size = sizeof(struct i40e_lump_tracking)
7331 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
7332 pf->irq_pile = kzalloc(size, GFP_KERNEL);
7333 if (!pf->irq_pile) {
7334 kfree(pf->qp_pile);
7335 err = -ENOMEM;
7336 goto sw_init_done;
7337 }
7338 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
7339 pf->irq_pile->search_hint = 0;
7340
327fe04b
ASJ		 7341 pf->tx_timeout_recovery_level = 1;
7342
41c445ff
JB		 7343 mutex_init(&pf->switch_mutex);
7344
7345sw_init_done:
7346 return err;
7347}
7348
7c3c288b
ASJ		 7349/**
7350 * i40e_set_ntuple - set the ntuple feature flag and take action
7351 * @pf: board private structure to initialize
7352 * @features: the feature set that the stack is suggesting
7353 *
7354 * returns a bool to indicate if reset needs to happen
7355 **/
7356bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
7357{
7358 bool need_reset = false;
7359
7360 /* Check if Flow Director n-tuple support was enabled or disabled. If
7361 * the state changed, we need to reset.
7362 */
7363 if (features & NETIF_F_NTUPLE) {
7364 /* Enable filters and mark for reset */
7365 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
7366 need_reset = true;
7367 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7368 } else {
7369 /* turn off filters, mark for reset and clear SW filter list */
7370 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7371 need_reset = true;
7372 i40e_fdir_filter_exit(pf);
7373 }
7374 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 7375 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 7376 /* reset fd counters */
7377 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
7378 pf->fdir_pf_active_filters = 0;
7379 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
7380 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 7381 /* if ATR was auto disabled it can be re-enabled. */
7382 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
7383 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
7384 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 7385 }
7386 return need_reset;
7387}
7388
41c445ff
JB		 7389/**
7390 * i40e_set_features - set the netdev feature flags
7391 * @netdev: ptr to the netdev being adjusted
7392 * @features: the feature set that the stack is suggesting
7393 **/
7394static int i40e_set_features(struct net_device *netdev,
7395 netdev_features_t features)
7396{
7397 struct i40e_netdev_priv *np = netdev_priv(netdev);
7398 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 7399 struct i40e_pf *pf = vsi->back;
7400 bool need_reset;
41c445ff
JB		 7401
7402 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7403 i40e_vlan_stripping_enable(vsi);
7404 else
7405 i40e_vlan_stripping_disable(vsi);
7406
7c3c288b
ASJ		 7407 need_reset = i40e_set_ntuple(pf, features);
7408
7409 if (need_reset)
7410 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
7411
41c445ff
JB		 7412 return 0;
7413}
7414
a1c9a9d9
JK		 7415#ifdef CONFIG_I40E_VXLAN
7416/**
7417 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
7418 * @pf: board private structure
7419 * @port: The UDP port to look up
7420 *
7421 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
7422 **/
7423static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
7424{
7425 u8 i;
7426
7427 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7428 if (pf->vxlan_ports[i] == port)
7429 return i;
7430 }
7431
7432 return i;
7433}
7434
7435/**
7436 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
7437 * @netdev: This physical port's netdev
7438 * @sa_family: Socket Family that VXLAN is notifying us about
7439 * @port: New UDP port number that VXLAN started listening to
7440 **/
7441static void i40e_add_vxlan_port(struct net_device *netdev,
7442 sa_family_t sa_family, __be16 port)
7443{
7444 struct i40e_netdev_priv *np = netdev_priv(netdev);
7445 struct i40e_vsi *vsi = np->vsi;
7446 struct i40e_pf *pf = vsi->back;
7447 u8 next_idx;
7448 u8 idx;
7449
7450 if (sa_family == AF_INET6)
7451 return;
7452
7453 idx = i40e_get_vxlan_port_idx(pf, port);
7454
7455 /* Check if port already exists */
7456 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7457 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
7458 return;
7459 }
7460
7461 /* Now check if there is space to add the new port */
7462 next_idx = i40e_get_vxlan_port_idx(pf, 0);
7463
7464 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7465 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
7466 ntohs(port));
7467 return;
7468 }
7469
7470 /* New port: add it and mark its index in the bitmap */
7471 pf->vxlan_ports[next_idx] = port;
7472 pf->pending_vxlan_bitmap |= (1 << next_idx);
7473
7474 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7475}
7476
7477/**
7478 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
7479 * @netdev: This physical port's netdev
7480 * @sa_family: Socket Family that VXLAN is notifying us about
7481 * @port: UDP port number that VXLAN stopped listening to
7482 **/
7483static void i40e_del_vxlan_port(struct net_device *netdev,
7484 sa_family_t sa_family, __be16 port)
7485{
7486 struct i40e_netdev_priv *np = netdev_priv(netdev);
7487 struct i40e_vsi *vsi = np->vsi;
7488 struct i40e_pf *pf = vsi->back;
7489 u8 idx;
7490
7491 if (sa_family == AF_INET6)
7492 return;
7493
7494 idx = i40e_get_vxlan_port_idx(pf, port);
7495
7496 /* Check if port already exists */
7497 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
7498 /* if port exists, set it to 0 (mark for deletion)
7499 * and make it pending
7500 */
7501 pf->vxlan_ports[idx] = 0;
7502
7503 pf->pending_vxlan_bitmap |= (1 << idx);
7504
7505 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
7506 } else {
7507 netdev_warn(netdev, "Port %d was not found, not deleting\n",
7508 ntohs(port));
7509 }
7510}
7511
7512#endif
1f224ad2 7513static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 7514 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 7515{
7516 struct i40e_netdev_priv *np = netdev_priv(netdev);
7517 struct i40e_pf *pf = np->vsi->back;
7518 struct i40e_hw *hw = &pf->hw;
7519
7520 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
7521 return -EOPNOTSUPP;
7522
7523 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
7524 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
7525
7526 return 0;
7527}
7528
2f90ade6
JB		 7529/**
7530 * i40e_ndo_fdb_add - add an entry to the hardware database
7531 * @ndm: the input from the stack
7532 * @tb: pointer to array of nladdr (unused)
7533 * @dev: the net device pointer
7534 * @addr: the MAC address entry being added
7535 * @flags: instructions from stack about fdb operation
7536 */
4ba0dea5
GR		 7537static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7538 struct net_device *dev,
f6f6424b 7539 const unsigned char *addr, u16 vid,
4ba0dea5 7540 u16 flags)
4ba0dea5
GR		 7541{
7542 struct i40e_netdev_priv *np = netdev_priv(dev);
7543 struct i40e_pf *pf = np->vsi->back;
7544 int err = 0;
7545
7546 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
7547 return -EOPNOTSUPP;
7548
7549 /* Hardware does not support aging addresses so if a
7550 * ndm_state is given only allow permanent addresses
7551 */
7552 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7553 netdev_info(dev, "FDB only supports static addresses\n");
7554 return -EINVAL;
7555 }
7556
7557 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
7558 err = dev_uc_add_excl(dev, addr);
7559 else if (is_multicast_ether_addr(addr))
7560 err = dev_mc_add_excl(dev, addr);
7561 else
7562 err = -EINVAL;
7563
7564 /* Only return duplicate errors if NLM_F_EXCL is set */
7565 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7566 err = 0;
7567
7568 return err;
7569}
7570
41c445ff
JB		 7571static const struct net_device_ops i40e_netdev_ops = {
7572 .ndo_open = i40e_open,
7573 .ndo_stop = i40e_close,
7574 .ndo_start_xmit = i40e_lan_xmit_frame,
7575 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7576 .ndo_set_rx_mode = i40e_set_rx_mode,
7577 .ndo_validate_addr = eth_validate_addr,
7578 .ndo_set_mac_address = i40e_set_mac,
7579 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7580 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7581 .ndo_tx_timeout = i40e_tx_timeout,
7582 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7583 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7584#ifdef CONFIG_NET_POLL_CONTROLLER
7585 .ndo_poll_controller = i40e_netpoll,
7586#endif
7587 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 7588#ifdef I40E_FCOE
7589 .ndo_fcoe_enable = i40e_fcoe_enable,
7590 .ndo_fcoe_disable = i40e_fcoe_disable,
7591#endif
41c445ff
JB		 7592 .ndo_set_features = i40e_set_features,
7593 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7594 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7595 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7596 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7597 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 7598 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
a1c9a9d9
JK		 7599#ifdef CONFIG_I40E_VXLAN
7600 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7601 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7602#endif
1f224ad2 7603 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 7604 .ndo_fdb_add = i40e_ndo_fdb_add,
41c445ff
JB		 7605};
7606
7607/**
7608 * i40e_config_netdev - Setup the netdev flags
7609 * @vsi: the VSI being configured
7610 *
7611 * Returns 0 on success, negative value on failure
7612 **/
7613static int i40e_config_netdev(struct i40e_vsi *vsi)
7614{
1a10370a 7615 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7616 struct i40e_pf *pf = vsi->back;
7617 struct i40e_hw *hw = &pf->hw;
7618 struct i40e_netdev_priv *np;
7619 struct net_device *netdev;
7620 u8 mac_addr[ETH_ALEN];
7621 int etherdev_size;
7622
7623 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7624 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7625 if (!netdev)
7626 return -ENOMEM;
7627
7628 vsi->netdev = netdev;
7629 np = netdev_priv(netdev);
7630 np->vsi = vsi;
7631
d70e941b 7632 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7633 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7634 NETIF_F_TSO;
41c445ff
JB		 7635
7636 netdev->features = NETIF_F_SG |
7637 NETIF_F_IP_CSUM |
7638 NETIF_F_SCTP_CSUM |
7639 NETIF_F_HIGHDMA |
7640 NETIF_F_GSO_UDP_TUNNEL |
7641 NETIF_F_HW_VLAN_CTAG_TX |
7642 NETIF_F_HW_VLAN_CTAG_RX |
7643 NETIF_F_HW_VLAN_CTAG_FILTER |
7644 NETIF_F_IPV6_CSUM |
7645 NETIF_F_TSO |
059dab69 7646 NETIF_F_TSO_ECN |
41c445ff
JB		 7647 NETIF_F_TSO6 |
7648 NETIF_F_RXCSUM |
7649 NETIF_F_RXHASH |
7650 0;
7651
2e86a0b6
ASJ		 7652 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7653 netdev->features |= NETIF_F_NTUPLE;
7654
41c445ff
JB		 7655 /* copy netdev features into list of user selectable features */
7656 netdev->hw_features |= netdev->features;
7657
7658 if (vsi->type == I40E_VSI_MAIN) {
7659 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7660 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 7661 /* The following steps are necessary to prevent reception
7662 * of tagged packets - some older NVM configurations load a
7663 * default a MAC-VLAN filter that accepts any tagged packet
7664 * which must be replaced by a normal filter.
8c27d42e 7665 */
30650cc5
SN		 7666 if (!i40e_rm_default_mac_filter(vsi, mac_addr))
7667 i40e_add_filter(vsi, mac_addr,
7668 I40E_VLAN_ANY, false, true);
41c445ff
JB		 7669 } else {
7670 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7671 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7672 pf->vsi[pf->lan_vsi]->netdev->name);
7673 random_ether_addr(mac_addr);
7674 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7675 }
1a10370a 7676 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7677
9a173901
GR		 7678 ether_addr_copy(netdev->dev_addr, mac_addr);
7679 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7680 /* vlan gets same features (except vlan offload)
7681 * after any tweaks for specific VSI types
7682 */
7683 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7684 NETIF_F_HW_VLAN_CTAG_RX |
7685 NETIF_F_HW_VLAN_CTAG_FILTER);
7686 netdev->priv_flags |= IFF_UNICAST_FLT;
7687 netdev->priv_flags |= IFF_SUPP_NOFCS;
7688 /* Setup netdev TC information */
7689 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7690
7691 netdev->netdev_ops = &i40e_netdev_ops;
7692 netdev->watchdog_timeo = 5 * HZ;
7693 i40e_set_ethtool_ops(netdev);
38e00438
VD		 7694#ifdef I40E_FCOE
7695 i40e_fcoe_config_netdev(netdev, vsi);
7696#endif
41c445ff
JB		 7697
7698 return 0;
7699}
7700
7701/**
7702 * i40e_vsi_delete - Delete a VSI from the switch
7703 * @vsi: the VSI being removed
7704 *
7705 * Returns 0 on success, negative value on failure
7706 **/
7707static void i40e_vsi_delete(struct i40e_vsi *vsi)
7708{
7709 /* remove default VSI is not allowed */
7710 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7711 return;
7712
41c445ff 7713 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7714}
7715
7716/**
7717 * i40e_add_vsi - Add a VSI to the switch
7718 * @vsi: the VSI being configured
7719 *
7720 * This initializes a VSI context depending on the VSI type to be added and
7721 * passes it down to the add_vsi aq command.
7722 **/
7723static int i40e_add_vsi(struct i40e_vsi *vsi)
7724{
7725 int ret = -ENODEV;
7726 struct i40e_mac_filter *f, *ftmp;
7727 struct i40e_pf *pf = vsi->back;
7728 struct i40e_hw *hw = &pf->hw;
7729 struct i40e_vsi_context ctxt;
7730 u8 enabled_tc = 0x1; /* TC0 enabled */
7731 int f_count = 0;
7732
7733 memset(&ctxt, 0, sizeof(ctxt));
7734 switch (vsi->type) {
7735 case I40E_VSI_MAIN:
7736 /* The PF's main VSI is already setup as part of the
7737 * device initialization, so we'll not bother with
7738 * the add_vsi call, but we will retrieve the current
7739 * VSI context.
7740 */
7741 ctxt.seid = pf->main_vsi_seid;
7742 ctxt.pf_num = pf->hw.pf_id;
7743 ctxt.vf_num = 0;
7744 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7745 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7746 if (ret) {
7747 dev_info(&pf->pdev->dev,
7748 "couldn't get pf vsi config, err %d, aq_err %d\n",
7749 ret, pf->hw.aq.asq_last_status);
7750 return -ENOENT;
7751 }
7752 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7753 vsi->info.valid_sections = 0;
7754
7755 vsi->seid = ctxt.seid;
7756 vsi->id = ctxt.vsi_number;
7757
7758 enabled_tc = i40e_pf_get_tc_map(pf);
7759
7760 /* MFP mode setup queue map and update VSI */
7761 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7762 memset(&ctxt, 0, sizeof(ctxt));
7763 ctxt.seid = pf->main_vsi_seid;
7764 ctxt.pf_num = pf->hw.pf_id;
7765 ctxt.vf_num = 0;
7766 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7767 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7768 if (ret) {
7769 dev_info(&pf->pdev->dev,
7770 "update vsi failed, aq_err=%d\n",
7771 pf->hw.aq.asq_last_status);
7772 ret = -ENOENT;
7773 goto err;
7774 }
7775 /* update the local VSI info queue map */
7776 i40e_vsi_update_queue_map(vsi, &ctxt);
7777 vsi->info.valid_sections = 0;
7778 } else {
7779 /* Default/Main VSI is only enabled for TC0
7780 * reconfigure it to enable all TCs that are
7781 * available on the port in SFP mode.
7782 */
7783 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7784 if (ret) {
7785 dev_info(&pf->pdev->dev,
7786 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7787 enabled_tc, ret,
7788 pf->hw.aq.asq_last_status);
7789 ret = -ENOENT;
7790 }
7791 }
7792 break;
7793
7794 case I40E_VSI_FDIR:
cbf61325
ASJ		 7795 ctxt.pf_num = hw->pf_id;
7796 ctxt.vf_num = 0;
7797 ctxt.uplink_seid = vsi->uplink_seid;
7798 ctxt.connection_type = 0x1; /* regular data port */
7799 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
79c21a82
ASJ		 7800 ctxt.info.valid_sections |=
7801 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7802 ctxt.info.switch_id =
7803 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
41c445ff 7804 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7805 break;
7806
7807 case I40E_VSI_VMDQ2:
7808 ctxt.pf_num = hw->pf_id;
7809 ctxt.vf_num = 0;
7810 ctxt.uplink_seid = vsi->uplink_seid;
7811 ctxt.connection_type = 0x1; /* regular data port */
7812 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7813
7814 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7815
7816 /* This VSI is connected to VEB so the switch_id
7817 * should be set to zero by default.
7818 */
7819 ctxt.info.switch_id = 0;
41c445ff
JB		 7820 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7821
7822 /* Setup the VSI tx/rx queue map for TC0 only for now */
7823 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7824 break;
7825
7826 case I40E_VSI_SRIOV:
7827 ctxt.pf_num = hw->pf_id;
7828 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7829 ctxt.uplink_seid = vsi->uplink_seid;
7830 ctxt.connection_type = 0x1; /* regular data port */
7831 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7832
7833 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7834
7835 /* This VSI is connected to VEB so the switch_id
7836 * should be set to zero by default.
7837 */
7838 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7839
7840 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7841 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7842 if (pf->vf[vsi->vf_id].spoofchk) {
7843 ctxt.info.valid_sections |=
7844 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7845 ctxt.info.sec_flags |=
7846 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7847 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7848 }
41c445ff
JB		 7849 /* Setup the VSI tx/rx queue map for TC0 only for now */
7850 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7851 break;
7852
38e00438
VD		 7853#ifdef I40E_FCOE
7854 case I40E_VSI_FCOE:
7855 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
7856 if (ret) {
7857 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
7858 return ret;
7859 }
7860 break;
7861
7862#endif /* I40E_FCOE */
41c445ff
JB		 7863 default:
7864 return -ENODEV;
7865 }
7866
7867 if (vsi->type != I40E_VSI_MAIN) {
7868 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7869 if (ret) {
7870 dev_info(&vsi->back->pdev->dev,
7871 "add vsi failed, aq_err=%d\n",
7872 vsi->back->hw.aq.asq_last_status);
7873 ret = -ENOENT;
7874 goto err;
7875 }
7876 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7877 vsi->info.valid_sections = 0;
7878 vsi->seid = ctxt.seid;
7879 vsi->id = ctxt.vsi_number;
7880 }
7881
7882 /* If macvlan filters already exist, force them to get loaded */
7883 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7884 f->changed = true;
7885 f_count++;
6252c7e4
SN		 7886
7887 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
30650cc5
SN		 7888 struct i40e_aqc_remove_macvlan_element_data element;
7889
7890 memset(&element, 0, sizeof(element));
7891 ether_addr_copy(element.mac_addr, f->macaddr);
7892 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7893 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
7894 &element, 1, NULL);
7895 if (ret) {
7896 /* some older FW has a different default */
7897 element.flags |=
7898 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7899 i40e_aq_remove_macvlan(hw, vsi->seid,
7900 &element, 1, NULL);
7901 }
7902
7903 i40e_aq_mac_address_write(hw,
6252c7e4
SN		 7904 I40E_AQC_WRITE_TYPE_LAA_WOL,
7905 f->macaddr, NULL);
7906 }
41c445ff
JB		 7907 }
7908 if (f_count) {
7909 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7910 pf->flags |= I40E_FLAG_FILTER_SYNC;
7911 }
7912
7913 /* Update VSI BW information */
7914 ret = i40e_vsi_get_bw_info(vsi);
7915 if (ret) {
7916 dev_info(&pf->pdev->dev,
7917 "couldn't get vsi bw info, err %d, aq_err %d\n",
7918 ret, pf->hw.aq.asq_last_status);
7919 /* VSI is already added so not tearing that up */
7920 ret = 0;
7921 }
7922
7923err:
7924 return ret;
7925}
7926
7927/**
7928 * i40e_vsi_release - Delete a VSI and free its resources
7929 * @vsi: the VSI being removed
7930 *
7931 * Returns 0 on success or < 0 on error
7932 **/
7933int i40e_vsi_release(struct i40e_vsi *vsi)
7934{
7935 struct i40e_mac_filter *f, *ftmp;
7936 struct i40e_veb *veb = NULL;
7937 struct i40e_pf *pf;
7938 u16 uplink_seid;
7939 int i, n;
7940
7941 pf = vsi->back;
7942
7943 /* release of a VEB-owner or last VSI is not allowed */
7944 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7945 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7946 vsi->seid, vsi->uplink_seid);
7947 return -ENODEV;
7948 }
7949 if (vsi == pf->vsi[pf->lan_vsi] &&
7950 !test_bit(__I40E_DOWN, &pf->state)) {
7951 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7952 return -ENODEV;
7953 }
7954
7955 uplink_seid = vsi->uplink_seid;
7956 if (vsi->type != I40E_VSI_SRIOV) {
7957 if (vsi->netdev_registered) {
7958 vsi->netdev_registered = false;
7959 if (vsi->netdev) {
7960 /* results in a call to i40e_close() */
7961 unregister_netdev(vsi->netdev);
41c445ff
JB		 7962 }
7963 } else {
90ef8d47 7964 i40e_vsi_close(vsi);
41c445ff
JB		 7965 }
7966 i40e_vsi_disable_irq(vsi);
7967 }
7968
7969 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7970 i40e_del_filter(vsi, f->macaddr, f->vlan,
7971 f->is_vf, f->is_netdev);
7972 i40e_sync_vsi_filters(vsi);
7973
7974 i40e_vsi_delete(vsi);
7975 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7976 if (vsi->netdev) {
7977 free_netdev(vsi->netdev);
7978 vsi->netdev = NULL;
7979 }
41c445ff
JB		 7980 i40e_vsi_clear_rings(vsi);
7981 i40e_vsi_clear(vsi);
7982
7983 /* If this was the last thing on the VEB, except for the
7984 * controlling VSI, remove the VEB, which puts the controlling
7985 * VSI onto the next level down in the switch.
7986 *
7987 * Well, okay, there's one more exception here: don't remove
7988 * the orphan VEBs yet. We'll wait for an explicit remove request
7989 * from up the network stack.
7990 */
505682cd 7991 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7992 if (pf->vsi[i] &&
7993 pf->vsi[i]->uplink_seid == uplink_seid &&
7994 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7995 n++; /* count the VSIs */
7996 }
7997 }
7998 for (i = 0; i < I40E_MAX_VEB; i++) {
7999 if (!pf->veb[i])
8000 continue;
8001 if (pf->veb[i]->uplink_seid == uplink_seid)
8002 n++; /* count the VEBs */
8003 if (pf->veb[i]->seid == uplink_seid)
8004 veb = pf->veb[i];
8005 }
8006 if (n == 0 && veb && veb->uplink_seid != 0)
8007 i40e_veb_release(veb);
8008
8009 return 0;
8010}
8011
8012/**
8013 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
8014 * @vsi: ptr to the VSI
8015 *
8016 * This should only be called after i40e_vsi_mem_alloc() which allocates the
8017 * corresponding SW VSI structure and initializes num_queue_pairs for the
8018 * newly allocated VSI.
8019 *
8020 * Returns 0 on success or negative on failure
8021 **/
8022static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
8023{
8024 int ret = -ENOENT;
8025 struct i40e_pf *pf = vsi->back;
8026
493fb300 8027 if (vsi->q_vectors[0]) {
41c445ff
JB		 8028 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
8029 vsi->seid);
8030 return -EEXIST;
8031 }
8032
8033 if (vsi->base_vector) {
f29eaa3d 8034 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 8035 vsi->seid, vsi->base_vector);
8036 return -EEXIST;
8037 }
8038
90e04070 8039 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 8040 if (ret) {
8041 dev_info(&pf->pdev->dev,
8042 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
8043 vsi->num_q_vectors, vsi->seid, ret);
8044 vsi->num_q_vectors = 0;
8045 goto vector_setup_out;
8046 }
8047
958a3e3b
SN		 8048 if (vsi->num_q_vectors)
8049 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
8050 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 8051 if (vsi->base_vector < 0) {
8052 dev_info(&pf->pdev->dev,
049a2be8
SN		 8053 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
8054 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 8055 i40e_vsi_free_q_vectors(vsi);
8056 ret = -ENOENT;
8057 goto vector_setup_out;
8058 }
8059
8060vector_setup_out:
8061 return ret;
8062}
8063
bc7d338f
ASJ		 8064/**
8065 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
8066 * @vsi: pointer to the vsi.
8067 *
8068 * This re-allocates a vsi's queue resources.
8069 *
8070 * Returns pointer to the successfully allocated and configured VSI sw struct
8071 * on success, otherwise returns NULL on failure.
8072 **/
8073static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
8074{
8075 struct i40e_pf *pf = vsi->back;
8076 u8 enabled_tc;
8077 int ret;
8078
8079 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
8080 i40e_vsi_clear_rings(vsi);
8081
8082 i40e_vsi_free_arrays(vsi, false);
8083 i40e_set_num_rings_in_vsi(vsi);
8084 ret = i40e_vsi_alloc_arrays(vsi, false);
8085 if (ret)
8086 goto err_vsi;
8087
8088 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
8089 if (ret < 0) {
049a2be8
SN		 8090 dev_info(&pf->pdev->dev,
8091 "failed to get tracking for %d queues for VSI %d err=%d\n",
8092 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 8093 goto err_vsi;
8094 }
8095 vsi->base_queue = ret;
8096
8097 /* Update the FW view of the VSI. Force a reset of TC and queue
8098 * layout configurations.
8099 */
8100 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8101 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8102 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8103 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8104
8105 /* assign it some queues */
8106 ret = i40e_alloc_rings(vsi);
8107 if (ret)
8108 goto err_rings;
8109
8110 /* map all of the rings to the q_vectors */
8111 i40e_vsi_map_rings_to_vectors(vsi);
8112 return vsi;
8113
8114err_rings:
8115 i40e_vsi_free_q_vectors(vsi);
8116 if (vsi->netdev_registered) {
8117 vsi->netdev_registered = false;
8118 unregister_netdev(vsi->netdev);
8119 free_netdev(vsi->netdev);
8120 vsi->netdev = NULL;
8121 }
8122 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8123err_vsi:
8124 i40e_vsi_clear(vsi);
8125 return NULL;
8126}
8127
41c445ff
JB		 8128/**
8129 * i40e_vsi_setup - Set up a VSI by a given type
8130 * @pf: board private structure
8131 * @type: VSI type
8132 * @uplink_seid: the switch element to link to
8133 * @param1: usage depends upon VSI type. For VF types, indicates VF id
8134 *
8135 * This allocates the sw VSI structure and its queue resources, then add a VSI
8136 * to the identified VEB.
8137 *
8138 * Returns pointer to the successfully allocated and configure VSI sw struct on
8139 * success, otherwise returns NULL on failure.
8140 **/
8141struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
8142 u16 uplink_seid, u32 param1)
8143{
8144 struct i40e_vsi *vsi = NULL;
8145 struct i40e_veb *veb = NULL;
8146 int ret, i;
8147 int v_idx;
8148
8149 /* The requested uplink_seid must be either
8150 * - the PF's port seid
8151 * no VEB is needed because this is the PF
8152 * or this is a Flow Director special case VSI
8153 * - seid of an existing VEB
8154 * - seid of a VSI that owns an existing VEB
8155 * - seid of a VSI that doesn't own a VEB
8156 * a new VEB is created and the VSI becomes the owner
8157 * - seid of the PF VSI, which is what creates the first VEB
8158 * this is a special case of the previous
8159 *
8160 * Find which uplink_seid we were given and create a new VEB if needed
8161 */
8162 for (i = 0; i < I40E_MAX_VEB; i++) {
8163 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
8164 veb = pf->veb[i];
8165 break;
8166 }
8167 }
8168
8169 if (!veb && uplink_seid != pf->mac_seid) {
8170
505682cd 8171 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8172 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
8173 vsi = pf->vsi[i];
8174 break;
8175 }
8176 }
8177 if (!vsi) {
8178 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
8179 uplink_seid);
8180 return NULL;
8181 }
8182
8183 if (vsi->uplink_seid == pf->mac_seid)
8184 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
8185 vsi->tc_config.enabled_tc);
8186 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
8187 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8188 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 8189 if (veb) {
8190 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
8191 dev_info(&vsi->back->pdev->dev,
8192 "%s: New VSI creation error, uplink seid of LAN VSI expected.\n",
8193 __func__);
8194 return NULL;
8195 }
8196 i40e_enable_pf_switch_lb(pf);
8197 }
41c445ff
JB		 8198 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8199 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8200 veb = pf->veb[i];
8201 }
8202 if (!veb) {
8203 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
8204 return NULL;
8205 }
8206
8207 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8208 uplink_seid = veb->seid;
8209 }
8210
8211 /* get vsi sw struct */
8212 v_idx = i40e_vsi_mem_alloc(pf, type);
8213 if (v_idx < 0)
8214 goto err_alloc;
8215 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 8216 if (!vsi)
8217 goto err_alloc;
41c445ff
JB		 8218 vsi->type = type;
8219 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
8220
8221 if (type == I40E_VSI_MAIN)
8222 pf->lan_vsi = v_idx;
8223 else if (type == I40E_VSI_SRIOV)
8224 vsi->vf_id = param1;
8225 /* assign it some queues */
cbf61325
ASJ		 8226 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
8227 vsi->idx);
41c445ff 8228 if (ret < 0) {
049a2be8
SN		 8229 dev_info(&pf->pdev->dev,
8230 "failed to get tracking for %d queues for VSI %d err=%d\n",
8231 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 8232 goto err_vsi;
8233 }
8234 vsi->base_queue = ret;
8235
8236 /* get a VSI from the hardware */
8237 vsi->uplink_seid = uplink_seid;
8238 ret = i40e_add_vsi(vsi);
8239 if (ret)
8240 goto err_vsi;
8241
8242 switch (vsi->type) {
8243 /* setup the netdev if needed */
8244 case I40E_VSI_MAIN:
8245 case I40E_VSI_VMDQ2:
38e00438 8246 case I40E_VSI_FCOE:
41c445ff
JB		 8247 ret = i40e_config_netdev(vsi);
8248 if (ret)
8249 goto err_netdev;
8250 ret = register_netdev(vsi->netdev);
8251 if (ret)
8252 goto err_netdev;
8253 vsi->netdev_registered = true;
8254 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 8255#ifdef CONFIG_I40E_DCB
8256 /* Setup DCB netlink interface */
8257 i40e_dcbnl_setup(vsi);
8258#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8259 /* fall through */
8260
8261 case I40E_VSI_FDIR:
8262 /* set up vectors and rings if needed */
8263 ret = i40e_vsi_setup_vectors(vsi);
8264 if (ret)
8265 goto err_msix;
8266
8267 ret = i40e_alloc_rings(vsi);
8268 if (ret)
8269 goto err_rings;
8270
8271 /* map all of the rings to the q_vectors */
8272 i40e_vsi_map_rings_to_vectors(vsi);
8273
8274 i40e_vsi_reset_stats(vsi);
8275 break;
8276
8277 default:
8278 /* no netdev or rings for the other VSI types */
8279 break;
8280 }
8281
8282 return vsi;
8283
8284err_rings:
8285 i40e_vsi_free_q_vectors(vsi);
8286err_msix:
8287 if (vsi->netdev_registered) {
8288 vsi->netdev_registered = false;
8289 unregister_netdev(vsi->netdev);
8290 free_netdev(vsi->netdev);
8291 vsi->netdev = NULL;
8292 }
8293err_netdev:
8294 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
8295err_vsi:
8296 i40e_vsi_clear(vsi);
8297err_alloc:
8298 return NULL;
8299}
8300
8301/**
8302 * i40e_veb_get_bw_info - Query VEB BW information
8303 * @veb: the veb to query
8304 *
8305 * Query the Tx scheduler BW configuration data for given VEB
8306 **/
8307static int i40e_veb_get_bw_info(struct i40e_veb *veb)
8308{
8309 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
8310 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
8311 struct i40e_pf *pf = veb->pf;
8312 struct i40e_hw *hw = &pf->hw;
8313 u32 tc_bw_max;
8314 int ret = 0;
8315 int i;
8316
8317 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8318 &bw_data, NULL);
8319 if (ret) {
8320 dev_info(&pf->pdev->dev,
8321 "query veb bw config failed, aq_err=%d\n",
8322 hw->aq.asq_last_status);
8323 goto out;
8324 }
8325
8326 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8327 &ets_data, NULL);
8328 if (ret) {
8329 dev_info(&pf->pdev->dev,
8330 "query veb bw ets config failed, aq_err=%d\n",
8331 hw->aq.asq_last_status);
8332 goto out;
8333 }
8334
8335 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
8336 veb->bw_max_quanta = ets_data.tc_bw_max;
8337 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 8338 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 8339 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
8340 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
8341 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8342 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
8343 veb->bw_tc_limit_credits[i] =
8344 le16_to_cpu(bw_data.tc_bw_limits[i]);
8345 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
8346 }
8347
8348out:
8349 return ret;
8350}
8351
8352/**
8353 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
8354 * @pf: board private structure
8355 *
8356 * On error: returns error code (negative)
8357 * On success: returns vsi index in PF (positive)
8358 **/
8359static int i40e_veb_mem_alloc(struct i40e_pf *pf)
8360{
8361 int ret = -ENOENT;
8362 struct i40e_veb *veb;
8363 int i;
8364
8365 /* Need to protect the allocation of switch elements at the PF level */
8366 mutex_lock(&pf->switch_mutex);
8367
8368 /* VEB list may be fragmented if VEB creation/destruction has
8369 * been happening. We can afford to do a quick scan to look
8370 * for any free slots in the list.
8371 *
8372 * find next empty veb slot, looping back around if necessary
8373 */
8374 i = 0;
8375 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
8376 i++;
8377 if (i >= I40E_MAX_VEB) {
8378 ret = -ENOMEM;
8379 goto err_alloc_veb; /* out of VEB slots! */
8380 }
8381
8382 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
8383 if (!veb) {
8384 ret = -ENOMEM;
8385 goto err_alloc_veb;
8386 }
8387 veb->pf = pf;
8388 veb->idx = i;
8389 veb->enabled_tc = 1;
8390
8391 pf->veb[i] = veb;
8392 ret = i;
8393err_alloc_veb:
8394 mutex_unlock(&pf->switch_mutex);
8395 return ret;
8396}
8397
8398/**
8399 * i40e_switch_branch_release - Delete a branch of the switch tree
8400 * @branch: where to start deleting
8401 *
8402 * This uses recursion to find the tips of the branch to be
8403 * removed, deleting until we get back to and can delete this VEB.
8404 **/
8405static void i40e_switch_branch_release(struct i40e_veb *branch)
8406{
8407 struct i40e_pf *pf = branch->pf;
8408 u16 branch_seid = branch->seid;
8409 u16 veb_idx = branch->idx;
8410 int i;
8411
8412 /* release any VEBs on this VEB - RECURSION */
8413 for (i = 0; i < I40E_MAX_VEB; i++) {
8414 if (!pf->veb[i])
8415 continue;
8416 if (pf->veb[i]->uplink_seid == branch->seid)
8417 i40e_switch_branch_release(pf->veb[i]);
8418 }
8419
8420 /* Release the VSIs on this VEB, but not the owner VSI.
8421 *
8422 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
8423 * the VEB itself, so don't use (*branch) after this loop.
8424 */
505682cd 8425 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8426 if (!pf->vsi[i])
8427 continue;
8428 if (pf->vsi[i]->uplink_seid == branch_seid &&
8429 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
8430 i40e_vsi_release(pf->vsi[i]);
8431 }
8432 }
8433
8434 /* There's one corner case where the VEB might not have been
8435 * removed, so double check it here and remove it if needed.
8436 * This case happens if the veb was created from the debugfs
8437 * commands and no VSIs were added to it.
8438 */
8439 if (pf->veb[veb_idx])
8440 i40e_veb_release(pf->veb[veb_idx]);
8441}
8442
8443/**
8444 * i40e_veb_clear - remove veb struct
8445 * @veb: the veb to remove
8446 **/
8447static void i40e_veb_clear(struct i40e_veb *veb)
8448{
8449 if (!veb)
8450 return;
8451
8452 if (veb->pf) {
8453 struct i40e_pf *pf = veb->pf;
8454
8455 mutex_lock(&pf->switch_mutex);
8456 if (pf->veb[veb->idx] == veb)
8457 pf->veb[veb->idx] = NULL;
8458 mutex_unlock(&pf->switch_mutex);
8459 }
8460
8461 kfree(veb);
8462}
8463
8464/**
8465 * i40e_veb_release - Delete a VEB and free its resources
8466 * @veb: the VEB being removed
8467 **/
8468void i40e_veb_release(struct i40e_veb *veb)
8469{
8470 struct i40e_vsi *vsi = NULL;
8471 struct i40e_pf *pf;
8472 int i, n = 0;
8473
8474 pf = veb->pf;
8475
8476 /* find the remaining VSI and check for extras */
505682cd 8477 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8478 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
8479 n++;
8480 vsi = pf->vsi[i];
8481 }
8482 }
8483 if (n != 1) {
8484 dev_info(&pf->pdev->dev,
8485 "can't remove VEB %d with %d VSIs left\n",
8486 veb->seid, n);
8487 return;
8488 }
8489
8490 /* move the remaining VSI to uplink veb */
8491 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
8492 if (veb->uplink_seid) {
8493 vsi->uplink_seid = veb->uplink_seid;
8494 if (veb->uplink_seid == pf->mac_seid)
8495 vsi->veb_idx = I40E_NO_VEB;
8496 else
8497 vsi->veb_idx = veb->veb_idx;
8498 } else {
8499 /* floating VEB */
8500 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8501 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
8502 }
8503
8504 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
8505 i40e_veb_clear(veb);
41c445ff
JB		 8506}
8507
8508/**
8509 * i40e_add_veb - create the VEB in the switch
8510 * @veb: the VEB to be instantiated
8511 * @vsi: the controlling VSI
8512 **/
8513static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
8514{
56747264 8515 bool is_default = false;
e1c51b95 8516 bool is_cloud = false;
41c445ff
JB		 8517 int ret;
8518
8519 /* get a VEB from the hardware */
8520 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 8521 veb->enabled_tc, is_default,
8522 is_cloud, &veb->seid, NULL);
41c445ff
JB		 8523 if (ret) {
8524 dev_info(&veb->pf->pdev->dev,
8525 "couldn't add VEB, err %d, aq_err %d\n",
8526 ret, veb->pf->hw.aq.asq_last_status);
8527 return -EPERM;
8528 }
8529
8530 /* get statistics counter */
8531 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
8532 &veb->stats_idx, NULL, NULL, NULL);
8533 if (ret) {
8534 dev_info(&veb->pf->pdev->dev,
8535 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
8536 ret, veb->pf->hw.aq.asq_last_status);
8537 return -EPERM;
8538 }
8539 ret = i40e_veb_get_bw_info(veb);
8540 if (ret) {
8541 dev_info(&veb->pf->pdev->dev,
8542 "couldn't get VEB bw info, err %d, aq_err %d\n",
8543 ret, veb->pf->hw.aq.asq_last_status);
8544 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
8545 return -ENOENT;
8546 }
8547
8548 vsi->uplink_seid = veb->seid;
8549 vsi->veb_idx = veb->idx;
8550 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
8551
8552 return 0;
8553}
8554
8555/**
8556 * i40e_veb_setup - Set up a VEB
8557 * @pf: board private structure
8558 * @flags: VEB setup flags
8559 * @uplink_seid: the switch element to link to
8560 * @vsi_seid: the initial VSI seid
8561 * @enabled_tc: Enabled TC bit-map
8562 *
8563 * This allocates the sw VEB structure and links it into the switch
8564 * It is possible and legal for this to be a duplicate of an already
8565 * existing VEB. It is also possible for both uplink and vsi seids
8566 * to be zero, in order to create a floating VEB.
8567 *
8568 * Returns pointer to the successfully allocated VEB sw struct on
8569 * success, otherwise returns NULL on failure.
8570 **/
8571struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
8572 u16 uplink_seid, u16 vsi_seid,
8573 u8 enabled_tc)
8574{
8575 struct i40e_veb *veb, *uplink_veb = NULL;
8576 int vsi_idx, veb_idx;
8577 int ret;
8578
8579 /* if one seid is 0, the other must be 0 to create a floating relay */
8580 if ((uplink_seid == 0 || vsi_seid == 0) &&
8581 (uplink_seid + vsi_seid != 0)) {
8582 dev_info(&pf->pdev->dev,
8583 "one, not both seid's are 0: uplink=%d vsi=%d\n",
8584 uplink_seid, vsi_seid);
8585 return NULL;
8586 }
8587
8588 /* make sure there is such a vsi and uplink */
505682cd 8589 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 8590 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
8591 break;
505682cd 8592 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 8593 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
8594 vsi_seid);
8595 return NULL;
8596 }
8597
8598 if (uplink_seid && uplink_seid != pf->mac_seid) {
8599 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8600 if (pf->veb[veb_idx] &&
8601 pf->veb[veb_idx]->seid == uplink_seid) {
8602 uplink_veb = pf->veb[veb_idx];
8603 break;
8604 }
8605 }
8606 if (!uplink_veb) {
8607 dev_info(&pf->pdev->dev,
8608 "uplink seid %d not found\n", uplink_seid);
8609 return NULL;
8610 }
8611 }
8612
8613 /* get veb sw struct */
8614 veb_idx = i40e_veb_mem_alloc(pf);
8615 if (veb_idx < 0)
8616 goto err_alloc;
8617 veb = pf->veb[veb_idx];
8618 veb->flags = flags;
8619 veb->uplink_seid = uplink_seid;
8620 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8621 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8622
8623 /* create the VEB in the switch */
8624 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8625 if (ret)
8626 goto err_veb;
1bb8b935
SN		 8627 if (vsi_idx == pf->lan_vsi)
8628 pf->lan_veb = veb->idx;
41c445ff
JB		 8629
8630 return veb;
8631
8632err_veb:
8633 i40e_veb_clear(veb);
8634err_alloc:
8635 return NULL;
8636}
8637
8638/**
8639 * i40e_setup_pf_switch_element - set pf vars based on switch type
8640 * @pf: board private structure
8641 * @ele: element we are building info from
8642 * @num_reported: total number of elements
8643 * @printconfig: should we print the contents
8644 *
8645 * helper function to assist in extracting a few useful SEID values.
8646 **/
8647static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8648 struct i40e_aqc_switch_config_element_resp *ele,
8649 u16 num_reported, bool printconfig)
8650{
8651 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8652 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8653 u8 element_type = ele->element_type;
8654 u16 seid = le16_to_cpu(ele->seid);
8655
8656 if (printconfig)
8657 dev_info(&pf->pdev->dev,
8658 "type=%d seid=%d uplink=%d downlink=%d\n",
8659 element_type, seid, uplink_seid, downlink_seid);
8660
8661 switch (element_type) {
8662 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8663 pf->mac_seid = seid;
8664 break;
8665 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8666 /* Main VEB? */
8667 if (uplink_seid != pf->mac_seid)
8668 break;
8669 if (pf->lan_veb == I40E_NO_VEB) {
8670 int v;
8671
8672 /* find existing or else empty VEB */
8673 for (v = 0; v < I40E_MAX_VEB; v++) {
8674 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8675 pf->lan_veb = v;
8676 break;
8677 }
8678 }
8679 if (pf->lan_veb == I40E_NO_VEB) {
8680 v = i40e_veb_mem_alloc(pf);
8681 if (v < 0)
8682 break;
8683 pf->lan_veb = v;
8684 }
8685 }
8686
8687 pf->veb[pf->lan_veb]->seid = seid;
8688 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8689 pf->veb[pf->lan_veb]->pf = pf;
8690 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8691 break;
8692 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8693 if (num_reported != 1)
8694 break;
8695 /* This is immediately after a reset so we can assume this is
8696 * the PF's VSI
8697 */
8698 pf->mac_seid = uplink_seid;
8699 pf->pf_seid = downlink_seid;
8700 pf->main_vsi_seid = seid;
8701 if (printconfig)
8702 dev_info(&pf->pdev->dev,
8703 "pf_seid=%d main_vsi_seid=%d\n",
8704 pf->pf_seid, pf->main_vsi_seid);
8705 break;
8706 case I40E_SWITCH_ELEMENT_TYPE_PF:
8707 case I40E_SWITCH_ELEMENT_TYPE_VF:
8708 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8709 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8710 case I40E_SWITCH_ELEMENT_TYPE_PE:
8711 case I40E_SWITCH_ELEMENT_TYPE_PA:
8712 /* ignore these for now */
8713 break;
8714 default:
8715 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8716 element_type, seid);
8717 break;
8718 }
8719}
8720
8721/**
8722 * i40e_fetch_switch_configuration - Get switch config from firmware
8723 * @pf: board private structure
8724 * @printconfig: should we print the contents
8725 *
8726 * Get the current switch configuration from the device and
8727 * extract a few useful SEID values.
8728 **/
8729int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8730{
8731 struct i40e_aqc_get_switch_config_resp *sw_config;
8732 u16 next_seid = 0;
8733 int ret = 0;
8734 u8 *aq_buf;
8735 int i;
8736
8737 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8738 if (!aq_buf)
8739 return -ENOMEM;
8740
8741 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8742 do {
8743 u16 num_reported, num_total;
8744
8745 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8746 I40E_AQ_LARGE_BUF,
8747 &next_seid, NULL);
8748 if (ret) {
8749 dev_info(&pf->pdev->dev,
8750 "get switch config failed %d aq_err=%x\n",
8751 ret, pf->hw.aq.asq_last_status);
8752 kfree(aq_buf);
8753 return -ENOENT;
8754 }
8755
8756 num_reported = le16_to_cpu(sw_config->header.num_reported);
8757 num_total = le16_to_cpu(sw_config->header.num_total);
8758
8759 if (printconfig)
8760 dev_info(&pf->pdev->dev,
8761 "header: %d reported %d total\n",
8762 num_reported, num_total);
8763
41c445ff
JB		 8764 for (i = 0; i < num_reported; i++) {
8765 struct i40e_aqc_switch_config_element_resp *ele =
8766 &sw_config->element[i];
8767
8768 i40e_setup_pf_switch_element(pf, ele, num_reported,
8769 printconfig);
8770 }
8771 } while (next_seid != 0);
8772
8773 kfree(aq_buf);
8774 return ret;
8775}
8776
8777/**
8778 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8779 * @pf: board private structure
bc7d338f 8780 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8781 *
8782 * Returns 0 on success, negative value on failure
8783 **/
bc7d338f 8784static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 8785{
8786 int ret;
8787
8788 /* find out what's out there already */
8789 ret = i40e_fetch_switch_configuration(pf, false);
8790 if (ret) {
8791 dev_info(&pf->pdev->dev,
8792 "couldn't fetch switch config, err %d, aq_err %d\n",
8793 ret, pf->hw.aq.asq_last_status);
8794 return ret;
8795 }
8796 i40e_pf_reset_stats(pf);
8797
41c445ff 8798 /* first time setup */
bc7d338f 8799 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8800 struct i40e_vsi *vsi = NULL;
8801 u16 uplink_seid;
8802
8803 /* Set up the PF VSI associated with the PF's main VSI
8804 * that is already in the HW switch
8805 */
8806 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8807 uplink_seid = pf->veb[pf->lan_veb]->seid;
8808 else
8809 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8810 if (pf->lan_vsi == I40E_NO_VSI)
8811 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8812 else if (reinit)
8813 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8814 if (!vsi) {
8815 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8816 i40e_fdir_teardown(pf);
8817 return -EAGAIN;
8818 }
41c445ff
JB		 8819 } else {
8820 /* force a reset of TC and queue layout configurations */
8821 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8822 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8823 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8824 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8825 }
8826 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8827
cbf61325
ASJ		 8828 i40e_fdir_sb_setup(pf);
8829
41c445ff
JB		 8830 /* Setup static PF queue filter control settings */
8831 ret = i40e_setup_pf_filter_control(pf);
8832 if (ret) {
8833 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8834 ret);
8835 /* Failure here should not stop continuing other steps */
8836 }
8837
8838 /* enable RSS in the HW, even for only one queue, as the stack can use
8839 * the hash
8840 */
8841 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8842 i40e_config_rss(pf);
8843
8844 /* fill in link information and enable LSE reporting */
a34a6711
MW		 8845 i40e_update_link_info(&pf->hw, true);
8846 i40e_link_event(pf);
8847
8848 /* Initialize user-specific link properties */
8849 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8850 I40E_AQ_AN_COMPLETED) ? true : false);
8851
8852 /* fill in link information and enable LSE reporting */
8109e123 8853 i40e_update_link_info(&pf->hw, true);
41c445ff
JB		 8854 i40e_link_event(pf);
8855
d52c20b7 8856 /* Initialize user-specific link properties */
41c445ff
JB		 8857 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8858 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 8859
beb0dff1
JK		 8860 i40e_ptp_init(pf);
8861
41c445ff
JB		 8862 return ret;
8863}
8864
41c445ff
JB		 8865/**
8866 * i40e_determine_queue_usage - Work out queue distribution
8867 * @pf: board private structure
8868 **/
8869static void i40e_determine_queue_usage(struct i40e_pf *pf)
8870{
41c445ff
JB		 8871 int queues_left;
8872
8873 pf->num_lan_qps = 0;
38e00438
VD		 8874#ifdef I40E_FCOE
8875 pf->num_fcoe_qps = 0;
8876#endif
41c445ff
JB		 8877
8878 /* Find the max queues to be put into basic use. We'll always be
8879 * using TC0, whether or not DCB is running, and TC0 will get the
8880 * big RSS set.
8881 */
8882 queues_left = pf->hw.func_caps.num_tx_qp;
8883
cbf61325 8884 if ((queues_left == 1) ||
9aa7e935 8885 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8886 /* one qp for PF, no queues for anything else */
8887 queues_left = 0;
8888 pf->rss_size = pf->num_lan_qps = 1;
8889
8890 /* make sure all the fancies are disabled */
60ea5f83 8891 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8892#ifdef I40E_FCOE
8893 I40E_FLAG_FCOE_ENABLED |
8894#endif
60ea5f83
JB		 8895 I40E_FLAG_FD_SB_ENABLED |
8896 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8897 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8898 I40E_FLAG_SRIOV_ENABLED |
8899 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8900 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8901 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8902 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8903 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8904 /* one qp for PF */
8905 pf->rss_size = pf->num_lan_qps = 1;
8906 queues_left -= pf->num_lan_qps;
8907
8908 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 8909#ifdef I40E_FCOE
8910 I40E_FLAG_FCOE_ENABLED |
8911#endif
9aa7e935
FZ		 8912 I40E_FLAG_FD_SB_ENABLED |
8913 I40E_FLAG_FD_ATR_ENABLED |
8914 I40E_FLAG_DCB_ENABLED |
8915 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8916 } else {
cbf61325 8917 /* Not enough queues for all TCs */
4d9b6043 8918 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8919 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8920 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8921 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8922 }
8923 pf->num_lan_qps = pf->rss_size_max;
8924 queues_left -= pf->num_lan_qps;
8925 }
8926
38e00438
VD		 8927#ifdef I40E_FCOE
8928 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
8929 if (I40E_DEFAULT_FCOE <= queues_left) {
8930 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
8931 } else if (I40E_MINIMUM_FCOE <= queues_left) {
8932 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
8933 } else {
8934 pf->num_fcoe_qps = 0;
8935 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
8936 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
8937 }
8938
8939 queues_left -= pf->num_fcoe_qps;
8940 }
8941
8942#endif
cbf61325
ASJ		 8943 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8944 if (queues_left > 1) {
8945 queues_left -= 1; /* save 1 queue for FD */
8946 } else {
8947 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8948 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8949 }
41c445ff
JB		 8950 }
8951
8952 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8953 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8954 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8955 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8956 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8957 }
8958
8959 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8960 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8961 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8962 (queues_left / pf->num_vmdq_qps));
8963 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8964 }
8965
f8ff1464 8966 pf->queues_left = queues_left;
38e00438
VD		 8967#ifdef I40E_FCOE
8968 dev_info(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
8969#endif
41c445ff
JB		 8970}
8971
8972/**
8973 * i40e_setup_pf_filter_control - Setup PF static filter control
8974 * @pf: PF to be setup
8975 *
8976 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8977 * settings. If PE/FCoE are enabled then it will also set the per PF
8978 * based filter sizes required for them. It also enables Flow director,
8979 * ethertype and macvlan type filter settings for the pf.
8980 *
8981 * Returns 0 on success, negative on failure
8982 **/
8983static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8984{
8985 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8986
8987 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8988
8989 /* Flow Director is enabled */
60ea5f83 8990 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8991 settings->enable_fdir = true;
8992
8993 /* Ethtype and MACVLAN filters enabled for PF */
8994 settings->enable_ethtype = true;
8995 settings->enable_macvlan = true;
8996
8997 if (i40e_set_filter_control(&pf->hw, settings))
8998 return -ENOENT;
8999
9000 return 0;
9001}
9002
0c22b3dd
JB		 9003#define INFO_STRING_LEN 255
9004static void i40e_print_features(struct i40e_pf *pf)
9005{
9006 struct i40e_hw *hw = &pf->hw;
9007 char *buf, *string;
9008
9009 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
9010 if (!string) {
9011 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
9012 return;
9013 }
9014
9015 buf = string;
9016
9017 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
9018#ifdef CONFIG_PCI_IOV
9019 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
9020#endif
9021 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
9022 pf->vsi[pf->lan_vsi]->num_queue_pairs);
9023
9024 if (pf->flags & I40E_FLAG_RSS_ENABLED)
9025 buf += sprintf(buf, "RSS ");
0c22b3dd 9026 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 9027 buf += sprintf(buf, "FD_ATR ");
9028 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
9029 buf += sprintf(buf, "FD_SB ");
0c22b3dd 9030 buf += sprintf(buf, "NTUPLE ");
c6423ff1 9031 }
4d9b6043 9032 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 9033 buf += sprintf(buf, "DCB ");
9034 if (pf->flags & I40E_FLAG_PTP)
9035 buf += sprintf(buf, "PTP ");
38e00438
VD		 9036#ifdef I40E_FCOE
9037 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
9038 buf += sprintf(buf, "FCOE ");
9039#endif
0c22b3dd
JB		 9040
9041 BUG_ON(buf > (string + INFO_STRING_LEN));
9042 dev_info(&pf->pdev->dev, "%s\n", string);
9043 kfree(string);
9044}
9045
41c445ff
JB		 9046/**
9047 * i40e_probe - Device initialization routine
9048 * @pdev: PCI device information struct
9049 * @ent: entry in i40e_pci_tbl
9050 *
9051 * i40e_probe initializes a pf identified by a pci_dev structure.
9052 * The OS initialization, configuring of the pf private structure,
9053 * and a hardware reset occur.
9054 *
9055 * Returns 0 on success, negative on failure
9056 **/
9057static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9058{
41c445ff
JB		 9059 struct i40e_pf *pf;
9060 struct i40e_hw *hw;
93cd765b 9061 static u16 pfs_found;
d4dfb81a 9062 u16 link_status;
41c445ff
JB		 9063 int err = 0;
9064 u32 len;
8a9eb7d3 9065 u32 i;
41c445ff
JB		 9066
9067 err = pci_enable_device_mem(pdev);
9068 if (err)
9069 return err;
9070
9071 /* set up for high or low dma */
6494294f 9072 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 9073 if (err) {
e3e3bfdd
JS		 9074 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9075 if (err) {
9076 dev_err(&pdev->dev,
9077 "DMA configuration failed: 0x%x\n", err);
9078 goto err_dma;
9079 }
41c445ff
JB		 9080 }
9081
9082 /* set up pci connections */
9083 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9084 IORESOURCE_MEM), i40e_driver_name);
9085 if (err) {
9086 dev_info(&pdev->dev,
9087 "pci_request_selected_regions failed %d\n", err);
9088 goto err_pci_reg;
9089 }
9090
9091 pci_enable_pcie_error_reporting(pdev);
9092 pci_set_master(pdev);
9093
9094 /* Now that we have a PCI connection, we need to do the
9095 * low level device setup. This is primarily setting up
9096 * the Admin Queue structures and then querying for the
9097 * device's current profile information.
9098 */
9099 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
9100 if (!pf) {
9101 err = -ENOMEM;
9102 goto err_pf_alloc;
9103 }
9104 pf->next_vsi = 0;
9105 pf->pdev = pdev;
9106 set_bit(__I40E_DOWN, &pf->state);
9107
9108 hw = &pf->hw;
9109 hw->back = pf;
9110 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9111 pci_resource_len(pdev, 0));
9112 if (!hw->hw_addr) {
9113 err = -EIO;
9114 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
9115 (unsigned int)pci_resource_start(pdev, 0),
9116 (unsigned int)pci_resource_len(pdev, 0), err);
9117 goto err_ioremap;
9118 }
9119 hw->vendor_id = pdev->vendor;
9120 hw->device_id = pdev->device;
9121 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
9122 hw->subsystem_vendor_id = pdev->subsystem_vendor;
9123 hw->subsystem_device_id = pdev->subsystem_device;
9124 hw->bus.device = PCI_SLOT(pdev->devfn);
9125 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 9126 pf->instance = pfs_found;
41c445ff 9127
5b5faa43
SN		 9128 if (debug != -1) {
9129 pf->msg_enable = pf->hw.debug_mask;
9130 pf->msg_enable = debug;
9131 }
9132
7134f9ce
JB		 9133 /* do a special CORER for clearing PXE mode once at init */
9134 if (hw->revision_id == 0 &&
9135 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
9136 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
9137 i40e_flush(hw);
9138 msleep(200);
9139 pf->corer_count++;
9140
9141 i40e_clear_pxe_mode(hw);
9142 }
9143
41c445ff 9144 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 9145 i40e_clear_hw(hw);
41c445ff
JB		 9146 err = i40e_pf_reset(hw);
9147 if (err) {
9148 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
9149 goto err_pf_reset;
9150 }
9151 pf->pfr_count++;
9152
9153 hw->aq.num_arq_entries = I40E_AQ_LEN;
9154 hw->aq.num_asq_entries = I40E_AQ_LEN;
9155 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9156 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
9157 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 9158
41c445ff 9159 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
b2008cbf
CW		 9160 "%s-%s:misc",
9161 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 9162
9163 err = i40e_init_shared_code(hw);
9164 if (err) {
9165 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
9166 goto err_pf_reset;
9167 }
9168
d52c20b7
JB		 9169 /* set up a default setting for link flow control */
9170 pf->hw.fc.requested_mode = I40E_FC_NONE;
9171
41c445ff
JB		 9172 err = i40e_init_adminq(hw);
9173 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
9174 if (err) {
9175 dev_info(&pdev->dev,
7aa67613 9176 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
41c445ff
JB		 9177 goto err_pf_reset;
9178 }
9179
7aa67613
CS		 9180 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
9181 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 9182 dev_info(&pdev->dev,
7aa67613
CS		 9183 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
9184 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
9185 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 9186 dev_info(&pdev->dev,
7aa67613 9187 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62
SN		 9188
9189
4eb3f768
SN		 9190 i40e_verify_eeprom(pf);
9191
2c5fe33b
JB		 9192 /* Rev 0 hardware was never productized */
9193 if (hw->revision_id < 1)
9194 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
9195
6ff4ef86 9196 i40e_clear_pxe_mode(hw);
41c445ff
JB		 9197 err = i40e_get_capabilities(pf);
9198 if (err)
9199 goto err_adminq_setup;
9200
9201 err = i40e_sw_init(pf);
9202 if (err) {
9203 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
9204 goto err_sw_init;
9205 }
9206
9207 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9208 hw->func_caps.num_rx_qp,
9209 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
9210 if (err) {
9211 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
9212 goto err_init_lan_hmc;
9213 }
9214
9215 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9216 if (err) {
9217 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
9218 err = -ENOENT;
9219 goto err_configure_lan_hmc;
9220 }
9221
9222 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 9223 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 9224 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
9225 err = -EIO;
9226 goto err_mac_addr;
9227 }
9228 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 9229 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 9230 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
9231 if (is_valid_ether_addr(hw->mac.port_addr))
9232 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 9233#ifdef I40E_FCOE
9234 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
9235 if (err)
9236 dev_info(&pdev->dev,
9237 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
9238 if (!is_valid_ether_addr(hw->mac.san_addr)) {
9239 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
9240 hw->mac.san_addr);
9241 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
9242 }
9243 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
9244#endif /* I40E_FCOE */
41c445ff
JB		 9245
9246 pci_set_drvdata(pdev, pf);
9247 pci_save_state(pdev);
4e3b35b0
NP		 9248#ifdef CONFIG_I40E_DCB
9249 err = i40e_init_pf_dcb(pf);
9250 if (err) {
9251 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 9252 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 9253 /* Continue without DCB enabled */
4e3b35b0
NP		 9254 }
9255#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9256
9257 /* set up periodic task facility */
9258 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
9259 pf->service_timer_period = HZ;
9260
9261 INIT_WORK(&pf->service_task, i40e_service_task);
9262 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
9263 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
9264 pf->link_check_timeout = jiffies;
9265
8e2773ae
SN		 9266 /* WoL defaults to disabled */
9267 pf->wol_en = false;
9268 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
9269
41c445ff
JB		 9270 /* set up the main switch operations */
9271 i40e_determine_queue_usage(pf);
9272 i40e_init_interrupt_scheme(pf);
9273
505682cd
MW		 9274 /* The number of VSIs reported by the FW is the minimum guaranteed
9275 * to us; HW supports far more and we share the remaining pool with
9276 * the other PFs. We allocate space for more than the guarantee with
9277 * the understanding that we might not get them all later.
41c445ff 9278 */
505682cd
MW		 9279 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
9280 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
9281 else
9282 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
9283
9284 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
9285 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 9286 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 9287 if (!pf->vsi) {
9288 err = -ENOMEM;
41c445ff 9289 goto err_switch_setup;
ed87ac09 9290 }
41c445ff 9291
bc7d338f 9292 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 9293 if (err) {
9294 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
9295 goto err_vsis;
9296 }
8a9eb7d3 9297 /* if FDIR VSI was set up, start it now */
505682cd 9298 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 9299 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
9300 i40e_vsi_open(pf->vsi[i]);
9301 break;
9302 }
9303 }
41c445ff 9304
7e2453fe
JB		 9305 /* driver is only interested in link up/down and module qualification
9306 * reports from firmware
9307 */
9308 err = i40e_aq_set_phy_int_mask(&pf->hw,
9309 I40E_AQ_EVENT_LINK_UPDOWN |
9310 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
9311 if (err)
9312 dev_info(&pf->pdev->dev, "set phy mask fail, aq_err %d\n", err);
9313
cafa2ee6
ASJ		 9314 msleep(75);
9315 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9316 if (err) {
9317 dev_info(&pf->pdev->dev, "link restart failed, aq_err=%d\n",
9318 pf->hw.aq.asq_last_status);
9319 }
9320
41c445ff
JB		 9321 /* The main driver is (mostly) up and happy. We need to set this state
9322 * before setting up the misc vector or we get a race and the vector
9323 * ends up disabled forever.
9324 */
9325 clear_bit(__I40E_DOWN, &pf->state);
9326
9327 /* In case of MSIX we are going to setup the misc vector right here
9328 * to handle admin queue events etc. In case of legacy and MSI
9329 * the misc functionality and queue processing is combined in
9330 * the same vector and that gets setup at open.
9331 */
9332 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9333 err = i40e_setup_misc_vector(pf);
9334 if (err) {
9335 dev_info(&pdev->dev,
9336 "setup of misc vector failed: %d\n", err);
9337 goto err_vsis;
9338 }
9339 }
9340
df805f62 9341#ifdef CONFIG_PCI_IOV
41c445ff
JB		 9342 /* prep for VF support */
9343 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 9344 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
9345 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 9346 u32 val;
9347
9348 /* disable link interrupts for VFs */
9349 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
9350 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
9351 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
9352 i40e_flush(hw);
4aeec010
MW		 9353
9354 if (pci_num_vf(pdev)) {
9355 dev_info(&pdev->dev,
9356 "Active VFs found, allocating resources.\n");
9357 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
9358 if (err)
9359 dev_info(&pdev->dev,
9360 "Error %d allocating resources for existing VFs\n",
9361 err);
9362 }
41c445ff 9363 }
df805f62 9364#endif /* CONFIG_PCI_IOV */
41c445ff 9365
93cd765b
ASJ		 9366 pfs_found++;
9367
41c445ff
JB		 9368 i40e_dbg_pf_init(pf);
9369
9370 /* tell the firmware that we're starting */
44033fac 9371 i40e_send_version(pf);
41c445ff
JB		 9372
9373 /* since everything's happy, start the service_task timer */
9374 mod_timer(&pf->service_timer,
9375 round_jiffies(jiffies + pf->service_timer_period));
9376
38e00438
VD		 9377#ifdef I40E_FCOE
9378 /* create FCoE interface */
9379 i40e_fcoe_vsi_setup(pf);
9380
9381#endif
d4dfb81a
CS		 9382 /* Get the negotiated link width and speed from PCI config space */
9383 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
9384
9385 i40e_set_pci_config_data(hw, link_status);
9386
69bfb110 9387 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 9388 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
9389 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
9390 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
9391 "Unknown"),
9392 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
9393 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
9394 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
9395 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
9396 "Unknown"));
9397
9398 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
9399 hw->bus.speed < i40e_bus_speed_8000) {
9400 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
9401 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
9402 }
9403
0c22b3dd
JB		 9404 /* print a string summarizing features */
9405 i40e_print_features(pf);
9406
41c445ff
JB		 9407 return 0;
9408
9409 /* Unwind what we've done if something failed in the setup */
9410err_vsis:
9411 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 9412 i40e_clear_interrupt_scheme(pf);
9413 kfree(pf->vsi);
04b03013
SN		 9414err_switch_setup:
9415 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 9416 del_timer_sync(&pf->service_timer);
9417err_mac_addr:
9418err_configure_lan_hmc:
9419 (void)i40e_shutdown_lan_hmc(hw);
9420err_init_lan_hmc:
9421 kfree(pf->qp_pile);
9422 kfree(pf->irq_pile);
9423err_sw_init:
9424err_adminq_setup:
9425 (void)i40e_shutdown_adminq(hw);
9426err_pf_reset:
9427 iounmap(hw->hw_addr);
9428err_ioremap:
9429 kfree(pf);
9430err_pf_alloc:
9431 pci_disable_pcie_error_reporting(pdev);
9432 pci_release_selected_regions(pdev,
9433 pci_select_bars(pdev, IORESOURCE_MEM));
9434err_pci_reg:
9435err_dma:
9436 pci_disable_device(pdev);
9437 return err;
9438}
9439
9440/**
9441 * i40e_remove - Device removal routine
9442 * @pdev: PCI device information struct
9443 *
9444 * i40e_remove is called by the PCI subsystem to alert the driver
9445 * that is should release a PCI device. This could be caused by a
9446 * Hot-Plug event, or because the driver is going to be removed from
9447 * memory.
9448 **/
9449static void i40e_remove(struct pci_dev *pdev)
9450{
9451 struct i40e_pf *pf = pci_get_drvdata(pdev);
9452 i40e_status ret_code;
41c445ff
JB		 9453 int i;
9454
9455 i40e_dbg_pf_exit(pf);
9456
beb0dff1
JK		 9457 i40e_ptp_stop(pf);
9458
41c445ff
JB		 9459 /* no more scheduling of any task */
9460 set_bit(__I40E_DOWN, &pf->state);
9461 del_timer_sync(&pf->service_timer);
9462 cancel_work_sync(&pf->service_task);
9463
eb2d80bc
MW		 9464 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
9465 i40e_free_vfs(pf);
9466 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
9467 }
9468
41c445ff
JB		 9469 i40e_fdir_teardown(pf);
9470
9471 /* If there is a switch structure or any orphans, remove them.
9472 * This will leave only the PF's VSI remaining.
9473 */
9474 for (i = 0; i < I40E_MAX_VEB; i++) {
9475 if (!pf->veb[i])
9476 continue;
9477
9478 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
9479 pf->veb[i]->uplink_seid == 0)
9480 i40e_switch_branch_release(pf->veb[i]);
9481 }
9482
9483 /* Now we can shutdown the PF's VSI, just before we kill
9484 * adminq and hmc.
9485 */
9486 if (pf->vsi[pf->lan_vsi])
9487 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
9488
9489 i40e_stop_misc_vector(pf);
9490 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
9491 synchronize_irq(pf->msix_entries[0].vector);
9492 free_irq(pf->msix_entries[0].vector, pf);
9493 }
9494
9495 /* shutdown and destroy the HMC */
60442dea
SN		 9496 if (pf->hw.hmc.hmc_obj) {
9497 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
9498 if (ret_code)
9499 dev_warn(&pdev->dev,
9500 "Failed to destroy the HMC resources: %d\n",
9501 ret_code);
9502 }
41c445ff
JB		 9503
9504 /* shutdown the adminq */
41c445ff
JB		 9505 ret_code = i40e_shutdown_adminq(&pf->hw);
9506 if (ret_code)
9507 dev_warn(&pdev->dev,
9508 "Failed to destroy the Admin Queue resources: %d\n",
9509 ret_code);
9510
9511 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
9512 i40e_clear_interrupt_scheme(pf);
505682cd 9513 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9514 if (pf->vsi[i]) {
9515 i40e_vsi_clear_rings(pf->vsi[i]);
9516 i40e_vsi_clear(pf->vsi[i]);
9517 pf->vsi[i] = NULL;
9518 }
9519 }
9520
9521 for (i = 0; i < I40E_MAX_VEB; i++) {
9522 kfree(pf->veb[i]);
9523 pf->veb[i] = NULL;
9524 }
9525
9526 kfree(pf->qp_pile);
9527 kfree(pf->irq_pile);
41c445ff
JB		 9528 kfree(pf->vsi);
9529
41c445ff
JB		 9530 iounmap(pf->hw.hw_addr);
9531 kfree(pf);
9532 pci_release_selected_regions(pdev,
9533 pci_select_bars(pdev, IORESOURCE_MEM));
9534
9535 pci_disable_pcie_error_reporting(pdev);
9536 pci_disable_device(pdev);
9537}
9538
9539/**
9540 * i40e_pci_error_detected - warning that something funky happened in PCI land
9541 * @pdev: PCI device information struct
9542 *
9543 * Called to warn that something happened and the error handling steps
9544 * are in progress. Allows the driver to quiesce things, be ready for
9545 * remediation.
9546 **/
9547static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
9548 enum pci_channel_state error)
9549{
9550 struct i40e_pf *pf = pci_get_drvdata(pdev);
9551
9552 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
9553
9554 /* shutdown all operations */
9007bccd
SN		 9555 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
9556 rtnl_lock();
9557 i40e_prep_for_reset(pf);
9558 rtnl_unlock();
9559 }
41c445ff
JB		 9560
9561 /* Request a slot reset */
9562 return PCI_ERS_RESULT_NEED_RESET;
9563}
9564
9565/**
9566 * i40e_pci_error_slot_reset - a PCI slot reset just happened
9567 * @pdev: PCI device information struct
9568 *
9569 * Called to find if the driver can work with the device now that
9570 * the pci slot has been reset. If a basic connection seems good
9571 * (registers are readable and have sane content) then return a
9572 * happy little PCI_ERS_RESULT_xxx.
9573 **/
9574static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
9575{
9576 struct i40e_pf *pf = pci_get_drvdata(pdev);
9577 pci_ers_result_t result;
9578 int err;
9579 u32 reg;
9580
9581 dev_info(&pdev->dev, "%s\n", __func__);
9582 if (pci_enable_device_mem(pdev)) {
9583 dev_info(&pdev->dev,
9584 "Cannot re-enable PCI device after reset.\n");
9585 result = PCI_ERS_RESULT_DISCONNECT;
9586 } else {
9587 pci_set_master(pdev);
9588 pci_restore_state(pdev);
9589 pci_save_state(pdev);
9590 pci_wake_from_d3(pdev, false);
9591
9592 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
9593 if (reg == 0)
9594 result = PCI_ERS_RESULT_RECOVERED;
9595 else
9596 result = PCI_ERS_RESULT_DISCONNECT;
9597 }
9598
9599 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9600 if (err) {
9601 dev_info(&pdev->dev,
9602 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9603 err);
9604 /* non-fatal, continue */
9605 }
9606
9607 return result;
9608}
9609
9610/**
9611 * i40e_pci_error_resume - restart operations after PCI error recovery
9612 * @pdev: PCI device information struct
9613 *
9614 * Called to allow the driver to bring things back up after PCI error
9615 * and/or reset recovery has finished.
9616 **/
9617static void i40e_pci_error_resume(struct pci_dev *pdev)
9618{
9619 struct i40e_pf *pf = pci_get_drvdata(pdev);
9620
9621 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 9622 if (test_bit(__I40E_SUSPENDED, &pf->state))
9623 return;
9624
9625 rtnl_lock();
41c445ff 9626 i40e_handle_reset_warning(pf);
9007bccd
SN		 9627 rtnl_lock();
9628}
9629
9630/**
9631 * i40e_shutdown - PCI callback for shutting down
9632 * @pdev: PCI device information struct
9633 **/
9634static void i40e_shutdown(struct pci_dev *pdev)
9635{
9636 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9637 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9638
9639 set_bit(__I40E_SUSPENDED, &pf->state);
9640 set_bit(__I40E_DOWN, &pf->state);
9641 rtnl_lock();
9642 i40e_prep_for_reset(pf);
9643 rtnl_unlock();
9644
8e2773ae
SN		 9645 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9646 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9647
9007bccd 9648 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9649 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9650 pci_set_power_state(pdev, PCI_D3hot);
9651 }
9652}
9653
9654#ifdef CONFIG_PM
9655/**
9656 * i40e_suspend - PCI callback for moving to D3
9657 * @pdev: PCI device information struct
9658 **/
9659static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9660{
9661 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9662 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9663
9664 set_bit(__I40E_SUSPENDED, &pf->state);
9665 set_bit(__I40E_DOWN, &pf->state);
9666 rtnl_lock();
9667 i40e_prep_for_reset(pf);
9668 rtnl_unlock();
9669
8e2773ae
SN		 9670 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9671 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9672
9673 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9674 pci_set_power_state(pdev, PCI_D3hot);
9675
9676 return 0;
41c445ff
JB		 9677}
9678
9007bccd
SN		 9679/**
9680 * i40e_resume - PCI callback for waking up from D3
9681 * @pdev: PCI device information struct
9682 **/
9683static int i40e_resume(struct pci_dev *pdev)
9684{
9685 struct i40e_pf *pf = pci_get_drvdata(pdev);
9686 u32 err;
9687
9688 pci_set_power_state(pdev, PCI_D0);
9689 pci_restore_state(pdev);
9690 /* pci_restore_state() clears dev->state_saves, so
9691 * call pci_save_state() again to restore it.
9692 */
9693 pci_save_state(pdev);
9694
9695 err = pci_enable_device_mem(pdev);
9696 if (err) {
9697 dev_err(&pdev->dev,
9698 "%s: Cannot enable PCI device from suspend\n",
9699 __func__);
9700 return err;
9701 }
9702 pci_set_master(pdev);
9703
9704 /* no wakeup events while running */
9705 pci_wake_from_d3(pdev, false);
9706
9707 /* handling the reset will rebuild the device state */
9708 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9709 clear_bit(__I40E_DOWN, &pf->state);
9710 rtnl_lock();
9711 i40e_reset_and_rebuild(pf, false);
9712 rtnl_unlock();
9713 }
9714
9715 return 0;
9716}
9717
9718#endif
41c445ff
JB		 9719static const struct pci_error_handlers i40e_err_handler = {
9720 .error_detected = i40e_pci_error_detected,
9721 .slot_reset = i40e_pci_error_slot_reset,
9722 .resume = i40e_pci_error_resume,
9723};
9724
9725static struct pci_driver i40e_driver = {
9726 .name = i40e_driver_name,
9727 .id_table = i40e_pci_tbl,
9728 .probe = i40e_probe,
9729 .remove = i40e_remove,
9007bccd
SN		 9730#ifdef CONFIG_PM
9731 .suspend = i40e_suspend,
9732 .resume = i40e_resume,
9733#endif
9734 .shutdown = i40e_shutdown,
41c445ff
JB		 9735 .err_handler = &i40e_err_handler,
9736 .sriov_configure = i40e_pci_sriov_configure,
9737};
9738
9739/**
9740 * i40e_init_module - Driver registration routine
9741 *
9742 * i40e_init_module is the first routine called when the driver is
9743 * loaded. All it does is register with the PCI subsystem.
9744 **/
9745static int __init i40e_init_module(void)
9746{
9747 pr_info("%s: %s - version %s\n", i40e_driver_name,
9748 i40e_driver_string, i40e_driver_version_str);
9749 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9750 i40e_dbg_init();
9751 return pci_register_driver(&i40e_driver);
9752}
9753module_init(i40e_init_module);
9754
9755/**
9756 * i40e_exit_module - Driver exit cleanup routine
9757 *
9758 * i40e_exit_module is called just before the driver is removed
9759 * from memory.
9760 **/
9761static void __exit i40e_exit_module(void)
9762{
9763 pci_unregister_driver(&i40e_driver);
9764 i40e_dbg_exit();
9765}
9766module_exit(i40e_exit_module);
Linux kernel - Deliverables
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