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i40e: count timeout events
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
acbc3eb5 41#define DRV_VERSION_BUILD 32
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 46static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 57static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 58static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 59
60/* i40e_pci_tbl - PCI Device ID Table
61 *
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 68 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 78 /* required last entry */
79 {0, }
80};
81MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
82
83#define I40E_MAX_VF_COUNT 128
84static int debug = -1;
85module_param(debug, int, 0);
86MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
87
88MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
89MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
90MODULE_LICENSE("GPL");
91MODULE_VERSION(DRV_VERSION);
92
93/**
94 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
95 * @hw: pointer to the HW structure
96 * @mem: ptr to mem struct to fill out
97 * @size: size of memory requested
98 * @alignment: what to align the allocation to
99 **/
100int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
101 u64 size, u32 alignment)
102{
103 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
104
105 mem->size = ALIGN(size, alignment);
106 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
107 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 108 if (!mem->va)
109 return -ENOMEM;
41c445ff 110
93bc73b8 111 return 0;
41c445ff
JB		 112}
113
114/**
115 * i40e_free_dma_mem_d - OS specific memory free for shared code
116 * @hw: pointer to the HW structure
117 * @mem: ptr to mem struct to free
118 **/
119int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
120{
121 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
122
123 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
124 mem->va = NULL;
125 mem->pa = 0;
126 mem->size = 0;
127
128 return 0;
129}
130
131/**
132 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
133 * @hw: pointer to the HW structure
134 * @mem: ptr to mem struct to fill out
135 * @size: size of memory requested
136 **/
137int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
138 u32 size)
139{
140 mem->size = size;
141 mem->va = kzalloc(size, GFP_KERNEL);
142
93bc73b8
JB		 143 if (!mem->va)
144 return -ENOMEM;
41c445ff 145
93bc73b8 146 return 0;
41c445ff
JB		 147}
148
149/**
150 * i40e_free_virt_mem_d - OS specific memory free for shared code
151 * @hw: pointer to the HW structure
152 * @mem: ptr to mem struct to free
153 **/
154int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
155{
156 /* it's ok to kfree a NULL pointer */
157 kfree(mem->va);
158 mem->va = NULL;
159 mem->size = 0;
160
161 return 0;
162}
163
164/**
165 * i40e_get_lump - find a lump of free generic resource
166 * @pf: board private structure
167 * @pile: the pile of resource to search
168 * @needed: the number of items needed
169 * @id: an owner id to stick on the items assigned
170 *
171 * Returns the base item index of the lump, or negative for error
172 *
173 * The search_hint trick and lack of advanced fit-finding only work
174 * because we're highly likely to have all the same size lump requests.
175 * Linear search time and any fragmentation should be minimal.
176 **/
177static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
178 u16 needed, u16 id)
179{
180 int ret = -ENOMEM;
ddf434ac 181 int i, j;
41c445ff
JB		 182
183 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
184 dev_info(&pf->pdev->dev,
185 "param err: pile=%p needed=%d id=0x%04x\n",
186 pile, needed, id);
187 return -EINVAL;
188 }
189
190 /* start the linear search with an imperfect hint */
191 i = pile->search_hint;
ddf434ac 192 while (i < pile->num_entries) {
41c445ff
JB		 193 /* skip already allocated entries */
194 if (pile->list[i] & I40E_PILE_VALID_BIT) {
195 i++;
196 continue;
197 }
198
199 /* do we have enough in this lump? */
200 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
201 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
202 break;
203 }
204
205 if (j == needed) {
206 /* there was enough, so assign it to the requestor */
207 for (j = 0; j < needed; j++)
208 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
209 ret = i;
210 pile->search_hint = i + j;
ddf434ac 211 break;
41c445ff
JB		 212 } else {
213 /* not enough, so skip over it and continue looking */
214 i += j;
215 }
216 }
217
218 return ret;
219}
220
221/**
222 * i40e_put_lump - return a lump of generic resource
223 * @pile: the pile of resource to search
224 * @index: the base item index
225 * @id: the owner id of the items assigned
226 *
227 * Returns the count of items in the lump
228 **/
229static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
230{
231 int valid_id = (id | I40E_PILE_VALID_BIT);
232 int count = 0;
233 int i;
234
235 if (!pile || index >= pile->num_entries)
236 return -EINVAL;
237
238 for (i = index;
239 i < pile->num_entries && pile->list[i] == valid_id;
240 i++) {
241 pile->list[i] = 0;
242 count++;
243 }
244
245 if (count && index < pile->search_hint)
246 pile->search_hint = index;
247
248 return count;
249}
250
251/**
252 * i40e_service_event_schedule - Schedule the service task to wake up
253 * @pf: board private structure
254 *
255 * If not already scheduled, this puts the task into the work queue
256 **/
257static void i40e_service_event_schedule(struct i40e_pf *pf)
258{
259 if (!test_bit(__I40E_DOWN, &pf->state) &&
260 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
261 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
262 schedule_work(&pf->service_task);
263}
264
265/**
266 * i40e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 *
269 * If any port has noticed a Tx timeout, it is likely that the whole
270 * device is munged, not just the one netdev port, so go for the full
271 * reset.
272 **/
273static void i40e_tx_timeout(struct net_device *netdev)
274{
275 struct i40e_netdev_priv *np = netdev_priv(netdev);
276 struct i40e_vsi *vsi = np->vsi;
277 struct i40e_pf *pf = vsi->back;
278
279 pf->tx_timeout_count++;
280
281 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
282 pf->tx_timeout_recovery_level = 0;
283 pf->tx_timeout_last_recovery = jiffies;
284 netdev_info(netdev, "tx_timeout recovery level %d\n",
285 pf->tx_timeout_recovery_level);
286
287 switch (pf->tx_timeout_recovery_level) {
288 case 0:
289 /* disable and re-enable queues for the VSI */
290 if (in_interrupt()) {
291 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
292 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
293 } else {
294 i40e_vsi_reinit_locked(vsi);
295 }
296 break;
297 case 1:
298 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
299 break;
300 case 2:
301 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
302 break;
303 case 3:
304 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
305 break;
306 default:
307 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 308 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 309 i40e_down(vsi);
310 break;
311 }
312 i40e_service_event_schedule(pf);
313 pf->tx_timeout_recovery_level++;
314}
315
316/**
317 * i40e_release_rx_desc - Store the new tail and head values
318 * @rx_ring: ring to bump
319 * @val: new head index
320 **/
321static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
322{
323 rx_ring->next_to_use = val;
324
325 /* Force memory writes to complete before letting h/w
326 * know there are new descriptors to fetch. (Only
327 * applicable for weak-ordered memory model archs,
328 * such as IA-64).
329 */
330 wmb();
331 writel(val, rx_ring->tail);
332}
333
334/**
335 * i40e_get_vsi_stats_struct - Get System Network Statistics
336 * @vsi: the VSI we care about
337 *
338 * Returns the address of the device statistics structure.
339 * The statistics are actually updated from the service task.
340 **/
341struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
342{
343 return &vsi->net_stats;
344}
345
346/**
347 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
348 * @netdev: network interface device structure
349 *
350 * Returns the address of the device statistics structure.
351 * The statistics are actually updated from the service task.
352 **/
353static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
354 struct net_device *netdev,
980e9b11 355 struct rtnl_link_stats64 *stats)
41c445ff
JB		 356{
357 struct i40e_netdev_priv *np = netdev_priv(netdev);
358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
370 struct i40e_ring *tx_ring, *rx_ring;
371 u64 bytes, packets;
372 unsigned int start;
373
374 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
375 if (!tx_ring)
376 continue;
377
378 do {
379 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
380 packets = tx_ring->stats.packets;
381 bytes = tx_ring->stats.bytes;
382 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
383
384 stats->tx_packets += packets;
385 stats->tx_bytes += bytes;
386 rx_ring = &tx_ring[1];
387
388 do {
389 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
390 packets = rx_ring->stats.packets;
391 bytes = rx_ring->stats.bytes;
392 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 393
980e9b11
AD		 394 stats->rx_packets += packets;
395 stats->rx_bytes += bytes;
396 }
397 rcu_read_unlock();
398
399 /* following stats updated by ixgbe_watchdog_task() */
400 stats->multicast = vsi_stats->multicast;
401 stats->tx_errors = vsi_stats->tx_errors;
402 stats->tx_dropped = vsi_stats->tx_dropped;
403 stats->rx_errors = vsi_stats->rx_errors;
404 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
405 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 406
980e9b11 407 return stats;
41c445ff
JB		 408}
409
410/**
411 * i40e_vsi_reset_stats - Resets all stats of the given vsi
412 * @vsi: the VSI to have its stats reset
413 **/
414void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
415{
416 struct rtnl_link_stats64 *ns;
417 int i;
418
419 if (!vsi)
420 return;
421
422 ns = i40e_get_vsi_stats_struct(vsi);
423 memset(ns, 0, sizeof(*ns));
424 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
425 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
426 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 427 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 428 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 429 memset(&vsi->rx_rings[i]->stats, 0 ,
430 sizeof(vsi->rx_rings[i]->stats));
431 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
432 sizeof(vsi->rx_rings[i]->rx_stats));
433 memset(&vsi->tx_rings[i]->stats, 0 ,
434 sizeof(vsi->tx_rings[i]->stats));
435 memset(&vsi->tx_rings[i]->tx_stats, 0,
436 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 437 }
8e9dca53 438 }
41c445ff
JB		 439 vsi->stat_offsets_loaded = false;
440}
441
442/**
443 * i40e_pf_reset_stats - Reset all of the stats for the given pf
444 * @pf: the PF to be reset
445 **/
446void i40e_pf_reset_stats(struct i40e_pf *pf)
447{
448 memset(&pf->stats, 0, sizeof(pf->stats));
449 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
450 pf->stat_offsets_loaded = false;
451}
452
453/**
454 * i40e_stat_update48 - read and update a 48 bit stat from the chip
455 * @hw: ptr to the hardware info
456 * @hireg: the high 32 bit reg to read
457 * @loreg: the low 32 bit reg to read
458 * @offset_loaded: has the initial offset been loaded yet
459 * @offset: ptr to current offset value
460 * @stat: ptr to the stat
461 *
462 * Since the device stats are not reset at PFReset, they likely will not
463 * be zeroed when the driver starts. We'll save the first values read
464 * and use them as offsets to be subtracted from the raw values in order
465 * to report stats that count from zero. In the process, we also manage
466 * the potential roll-over.
467 **/
468static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
469 bool offset_loaded, u64 *offset, u64 *stat)
470{
471 u64 new_data;
472
ab60085e 473 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 474 new_data = rd32(hw, loreg);
475 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
476 } else {
477 new_data = rd64(hw, loreg);
478 }
479 if (!offset_loaded)
480 *offset = new_data;
481 if (likely(new_data >= *offset))
482 *stat = new_data - *offset;
483 else
484 *stat = (new_data + ((u64)1 << 48)) - *offset;
485 *stat &= 0xFFFFFFFFFFFFULL;
486}
487
488/**
489 * i40e_stat_update32 - read and update a 32 bit stat from the chip
490 * @hw: ptr to the hardware info
491 * @reg: the hw reg to read
492 * @offset_loaded: has the initial offset been loaded yet
493 * @offset: ptr to current offset value
494 * @stat: ptr to the stat
495 **/
496static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
497 bool offset_loaded, u64 *offset, u64 *stat)
498{
499 u32 new_data;
500
501 new_data = rd32(hw, reg);
502 if (!offset_loaded)
503 *offset = new_data;
504 if (likely(new_data >= *offset))
505 *stat = (u32)(new_data - *offset);
506 else
507 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
508}
509
510/**
511 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
512 * @vsi: the VSI to be updated
513 **/
514void i40e_update_eth_stats(struct i40e_vsi *vsi)
515{
516 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
517 struct i40e_pf *pf = vsi->back;
518 struct i40e_hw *hw = &pf->hw;
519 struct i40e_eth_stats *oes;
520 struct i40e_eth_stats *es; /* device's eth stats */
521
522 es = &vsi->eth_stats;
523 oes = &vsi->eth_stats_offsets;
524
525 /* Gather up the stats that the hw collects */
526 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
527 vsi->stat_offsets_loaded,
528 &oes->tx_errors, &es->tx_errors);
529 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
530 vsi->stat_offsets_loaded,
531 &oes->rx_discards, &es->rx_discards);
532
533 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
534 I40E_GLV_GORCL(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->rx_bytes, &es->rx_bytes);
537 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
538 I40E_GLV_UPRCL(stat_idx),
539 vsi->stat_offsets_loaded,
540 &oes->rx_unicast, &es->rx_unicast);
541 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
542 I40E_GLV_MPRCL(stat_idx),
543 vsi->stat_offsets_loaded,
544 &oes->rx_multicast, &es->rx_multicast);
545 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
546 I40E_GLV_BPRCL(stat_idx),
547 vsi->stat_offsets_loaded,
548 &oes->rx_broadcast, &es->rx_broadcast);
549
550 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
551 I40E_GLV_GOTCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->tx_bytes, &es->tx_bytes);
554 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
555 I40E_GLV_UPTCL(stat_idx),
556 vsi->stat_offsets_loaded,
557 &oes->tx_unicast, &es->tx_unicast);
558 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
559 I40E_GLV_MPTCL(stat_idx),
560 vsi->stat_offsets_loaded,
561 &oes->tx_multicast, &es->tx_multicast);
562 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
563 I40E_GLV_BPTCL(stat_idx),
564 vsi->stat_offsets_loaded,
565 &oes->tx_broadcast, &es->tx_broadcast);
566 vsi->stat_offsets_loaded = true;
567}
568
569/**
570 * i40e_update_veb_stats - Update Switch component statistics
571 * @veb: the VEB being updated
572 **/
573static void i40e_update_veb_stats(struct i40e_veb *veb)
574{
575 struct i40e_pf *pf = veb->pf;
576 struct i40e_hw *hw = &pf->hw;
577 struct i40e_eth_stats *oes;
578 struct i40e_eth_stats *es; /* device's eth stats */
579 int idx = 0;
580
581 idx = veb->stats_idx;
582 es = &veb->stats;
583 oes = &veb->stats_offsets;
584
585 /* Gather up the stats that the hw collects */
586 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
587 veb->stat_offsets_loaded,
588 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 589 if (hw->revision_id > 0)
590 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
591 veb->stat_offsets_loaded,
592 &oes->rx_unknown_protocol,
593 &es->rx_unknown_protocol);
41c445ff
JB		 594 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
595 veb->stat_offsets_loaded,
596 &oes->rx_bytes, &es->rx_bytes);
597 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
598 veb->stat_offsets_loaded,
599 &oes->rx_unicast, &es->rx_unicast);
600 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
601 veb->stat_offsets_loaded,
602 &oes->rx_multicast, &es->rx_multicast);
603 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
604 veb->stat_offsets_loaded,
605 &oes->rx_broadcast, &es->rx_broadcast);
606
607 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
608 veb->stat_offsets_loaded,
609 &oes->tx_bytes, &es->tx_bytes);
610 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
611 veb->stat_offsets_loaded,
612 &oes->tx_unicast, &es->tx_unicast);
613 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
614 veb->stat_offsets_loaded,
615 &oes->tx_multicast, &es->tx_multicast);
616 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
617 veb->stat_offsets_loaded,
618 &oes->tx_broadcast, &es->tx_broadcast);
619 veb->stat_offsets_loaded = true;
620}
621
622/**
623 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
624 * @pf: the corresponding PF
625 *
626 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
627 **/
628static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
629{
630 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
631 struct i40e_hw_port_stats *nsd = &pf->stats;
632 struct i40e_hw *hw = &pf->hw;
633 u64 xoff = 0;
634 u16 i, v;
635
636 if ((hw->fc.current_mode != I40E_FC_FULL) &&
637 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
638 return;
639
640 xoff = nsd->link_xoff_rx;
641 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
642 pf->stat_offsets_loaded,
643 &osd->link_xoff_rx, &nsd->link_xoff_rx);
644
645 /* No new LFC xoff rx */
646 if (!(nsd->link_xoff_rx - xoff))
647 return;
648
649 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
650 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
651 struct i40e_vsi *vsi = pf->vsi[v];
652
653 if (!vsi)
654 continue;
655
656 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 657 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 658 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
659 }
660 }
661}
662
663/**
664 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
665 * @pf: the corresponding PF
666 *
667 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
668 **/
669static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
670{
671 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
672 struct i40e_hw_port_stats *nsd = &pf->stats;
673 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
674 struct i40e_dcbx_config *dcb_cfg;
675 struct i40e_hw *hw = &pf->hw;
676 u16 i, v;
677 u8 tc;
678
679 dcb_cfg = &hw->local_dcbx_config;
680
681 /* See if DCB enabled with PFC TC */
682 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
683 !(dcb_cfg->pfc.pfcenable)) {
684 i40e_update_link_xoff_rx(pf);
685 return;
686 }
687
688 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
689 u64 prio_xoff = nsd->priority_xoff_rx[i];
690 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
691 pf->stat_offsets_loaded,
692 &osd->priority_xoff_rx[i],
693 &nsd->priority_xoff_rx[i]);
694
695 /* No new PFC xoff rx */
696 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
697 continue;
698 /* Get the TC for given priority */
699 tc = dcb_cfg->etscfg.prioritytable[i];
700 xoff[tc] = true;
701 }
702
703 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
704 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
705 struct i40e_vsi *vsi = pf->vsi[v];
706
707 if (!vsi)
708 continue;
709
710 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 711 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 712
713 tc = ring->dcb_tc;
714 if (xoff[tc])
715 clear_bit(__I40E_HANG_CHECK_ARMED,
716 &ring->state);
717 }
718 }
719}
720
721/**
722 * i40e_update_stats - Update the board statistics counters.
723 * @vsi: the VSI to be updated
724 *
725 * There are a few instances where we store the same stat in a
726 * couple of different structs. This is partly because we have
727 * the netdev stats that need to be filled out, which is slightly
728 * different from the "eth_stats" defined by the chip and used in
729 * VF communications. We sort it all out here in a central place.
730 **/
731void i40e_update_stats(struct i40e_vsi *vsi)
732{
733 struct i40e_pf *pf = vsi->back;
734 struct i40e_hw *hw = &pf->hw;
735 struct rtnl_link_stats64 *ons;
736 struct rtnl_link_stats64 *ns; /* netdev stats */
737 struct i40e_eth_stats *oes;
738 struct i40e_eth_stats *es; /* device's eth stats */
739 u32 tx_restart, tx_busy;
740 u32 rx_page, rx_buf;
741 u64 rx_p, rx_b;
742 u64 tx_p, tx_b;
743 int i;
744 u16 q;
745
746 if (test_bit(__I40E_DOWN, &vsi->state) ||
747 test_bit(__I40E_CONFIG_BUSY, &pf->state))
748 return;
749
750 ns = i40e_get_vsi_stats_struct(vsi);
751 ons = &vsi->net_stats_offsets;
752 es = &vsi->eth_stats;
753 oes = &vsi->eth_stats_offsets;
754
755 /* Gather up the netdev and vsi stats that the driver collects
756 * on the fly during packet processing
757 */
758 rx_b = rx_p = 0;
759 tx_b = tx_p = 0;
760 tx_restart = tx_busy = 0;
761 rx_page = 0;
762 rx_buf = 0;
980e9b11 763 rcu_read_lock();
41c445ff
JB		 764 for (q = 0; q < vsi->num_queue_pairs; q++) {
765 struct i40e_ring *p;
980e9b11
AD		 766 u64 bytes, packets;
767 unsigned int start;
768
769 /* locate Tx ring */
770 p = ACCESS_ONCE(vsi->tx_rings[q]);
771
772 do {
773 start = u64_stats_fetch_begin_bh(&p->syncp);
774 packets = p->stats.packets;
775 bytes = p->stats.bytes;
776 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
777 tx_b += bytes;
778 tx_p += packets;
779 tx_restart += p->tx_stats.restart_queue;
780 tx_busy += p->tx_stats.tx_busy;
41c445ff 781
980e9b11
AD		 782 /* Rx queue is part of the same block as Tx queue */
783 p = &p[1];
784 do {
785 start = u64_stats_fetch_begin_bh(&p->syncp);
786 packets = p->stats.packets;
787 bytes = p->stats.bytes;
788 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
789 rx_b += bytes;
790 rx_p += packets;
420136cc
MW		 791 rx_buf += p->rx_stats.alloc_buff_failed;
792 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 793 }
980e9b11 794 rcu_read_unlock();
41c445ff
JB		 795 vsi->tx_restart = tx_restart;
796 vsi->tx_busy = tx_busy;
797 vsi->rx_page_failed = rx_page;
798 vsi->rx_buf_failed = rx_buf;
799
800 ns->rx_packets = rx_p;
801 ns->rx_bytes = rx_b;
802 ns->tx_packets = tx_p;
803 ns->tx_bytes = tx_b;
804
805 i40e_update_eth_stats(vsi);
806 /* update netdev stats from eth stats */
807 ons->rx_errors = oes->rx_errors;
808 ns->rx_errors = es->rx_errors;
809 ons->tx_errors = oes->tx_errors;
810 ns->tx_errors = es->tx_errors;
811 ons->multicast = oes->rx_multicast;
812 ns->multicast = es->rx_multicast;
813 ons->tx_dropped = oes->tx_discards;
814 ns->tx_dropped = es->tx_discards;
815
816 /* Get the port data only if this is the main PF VSI */
817 if (vsi == pf->vsi[pf->lan_vsi]) {
818 struct i40e_hw_port_stats *nsd = &pf->stats;
819 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
820
821 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
822 I40E_GLPRT_GORCL(hw->port),
823 pf->stat_offsets_loaded,
824 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
825 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
826 I40E_GLPRT_GOTCL(hw->port),
827 pf->stat_offsets_loaded,
828 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
829 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
830 pf->stat_offsets_loaded,
831 &osd->eth.rx_discards,
832 &nsd->eth.rx_discards);
833 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
834 pf->stat_offsets_loaded,
835 &osd->eth.tx_discards,
836 &nsd->eth.tx_discards);
837 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
838 I40E_GLPRT_MPRCL(hw->port),
839 pf->stat_offsets_loaded,
840 &osd->eth.rx_multicast,
841 &nsd->eth.rx_multicast);
842
843 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
844 pf->stat_offsets_loaded,
845 &osd->tx_dropped_link_down,
846 &nsd->tx_dropped_link_down);
847
848 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
849 pf->stat_offsets_loaded,
850 &osd->crc_errors, &nsd->crc_errors);
851 ns->rx_crc_errors = nsd->crc_errors;
852
853 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
854 pf->stat_offsets_loaded,
855 &osd->illegal_bytes, &nsd->illegal_bytes);
856 ns->rx_errors = nsd->crc_errors
857 + nsd->illegal_bytes;
858
859 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
860 pf->stat_offsets_loaded,
861 &osd->mac_local_faults,
862 &nsd->mac_local_faults);
863 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
864 pf->stat_offsets_loaded,
865 &osd->mac_remote_faults,
866 &nsd->mac_remote_faults);
867
868 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
869 pf->stat_offsets_loaded,
870 &osd->rx_length_errors,
871 &nsd->rx_length_errors);
872 ns->rx_length_errors = nsd->rx_length_errors;
873
874 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
875 pf->stat_offsets_loaded,
876 &osd->link_xon_rx, &nsd->link_xon_rx);
877 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
878 pf->stat_offsets_loaded,
879 &osd->link_xon_tx, &nsd->link_xon_tx);
880 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
881 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
882 pf->stat_offsets_loaded,
883 &osd->link_xoff_tx, &nsd->link_xoff_tx);
884
885 for (i = 0; i < 8; i++) {
886 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
887 pf->stat_offsets_loaded,
888 &osd->priority_xon_rx[i],
889 &nsd->priority_xon_rx[i]);
890 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
891 pf->stat_offsets_loaded,
892 &osd->priority_xon_tx[i],
893 &nsd->priority_xon_tx[i]);
894 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
895 pf->stat_offsets_loaded,
896 &osd->priority_xoff_tx[i],
897 &nsd->priority_xoff_tx[i]);
898 i40e_stat_update32(hw,
899 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
900 pf->stat_offsets_loaded,
901 &osd->priority_xon_2_xoff[i],
902 &nsd->priority_xon_2_xoff[i]);
903 }
904
905 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
906 I40E_GLPRT_PRC64L(hw->port),
907 pf->stat_offsets_loaded,
908 &osd->rx_size_64, &nsd->rx_size_64);
909 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
910 I40E_GLPRT_PRC127L(hw->port),
911 pf->stat_offsets_loaded,
912 &osd->rx_size_127, &nsd->rx_size_127);
913 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
914 I40E_GLPRT_PRC255L(hw->port),
915 pf->stat_offsets_loaded,
916 &osd->rx_size_255, &nsd->rx_size_255);
917 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
918 I40E_GLPRT_PRC511L(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->rx_size_511, &nsd->rx_size_511);
921 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
922 I40E_GLPRT_PRC1023L(hw->port),
923 pf->stat_offsets_loaded,
924 &osd->rx_size_1023, &nsd->rx_size_1023);
925 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
926 I40E_GLPRT_PRC1522L(hw->port),
927 pf->stat_offsets_loaded,
928 &osd->rx_size_1522, &nsd->rx_size_1522);
929 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
930 I40E_GLPRT_PRC9522L(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->rx_size_big, &nsd->rx_size_big);
933
934 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
935 I40E_GLPRT_PTC64L(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->tx_size_64, &nsd->tx_size_64);
938 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
939 I40E_GLPRT_PTC127L(hw->port),
940 pf->stat_offsets_loaded,
941 &osd->tx_size_127, &nsd->tx_size_127);
942 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
943 I40E_GLPRT_PTC255L(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->tx_size_255, &nsd->tx_size_255);
946 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
947 I40E_GLPRT_PTC511L(hw->port),
948 pf->stat_offsets_loaded,
949 &osd->tx_size_511, &nsd->tx_size_511);
950 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
951 I40E_GLPRT_PTC1023L(hw->port),
952 pf->stat_offsets_loaded,
953 &osd->tx_size_1023, &nsd->tx_size_1023);
954 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
955 I40E_GLPRT_PTC1522L(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->tx_size_1522, &nsd->tx_size_1522);
958 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
959 I40E_GLPRT_PTC9522L(hw->port),
960 pf->stat_offsets_loaded,
961 &osd->tx_size_big, &nsd->tx_size_big);
962
963 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
964 pf->stat_offsets_loaded,
965 &osd->rx_undersize, &nsd->rx_undersize);
966 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_fragments, &nsd->rx_fragments);
969 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
970 pf->stat_offsets_loaded,
971 &osd->rx_oversize, &nsd->rx_oversize);
972 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->rx_jabber, &nsd->rx_jabber);
975 }
976
977 pf->stat_offsets_loaded = true;
978}
979
980/**
981 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
982 * @vsi: the VSI to be searched
983 * @macaddr: the MAC address
984 * @vlan: the vlan
985 * @is_vf: make sure its a vf filter, else doesn't matter
986 * @is_netdev: make sure its a netdev filter, else doesn't matter
987 *
988 * Returns ptr to the filter object or NULL
989 **/
990static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
991 u8 *macaddr, s16 vlan,
992 bool is_vf, bool is_netdev)
993{
994 struct i40e_mac_filter *f;
995
996 if (!vsi || !macaddr)
997 return NULL;
998
999 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1000 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1001 (vlan == f->vlan) &&
1002 (!is_vf || f->is_vf) &&
1003 (!is_netdev || f->is_netdev))
1004 return f;
1005 }
1006 return NULL;
1007}
1008
1009/**
1010 * i40e_find_mac - Find a mac addr in the macvlan filters list
1011 * @vsi: the VSI to be searched
1012 * @macaddr: the MAC address we are searching for
1013 * @is_vf: make sure its a vf filter, else doesn't matter
1014 * @is_netdev: make sure its a netdev filter, else doesn't matter
1015 *
1016 * Returns the first filter with the provided MAC address or NULL if
1017 * MAC address was not found
1018 **/
1019struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1020 bool is_vf, bool is_netdev)
1021{
1022 struct i40e_mac_filter *f;
1023
1024 if (!vsi || !macaddr)
1025 return NULL;
1026
1027 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1028 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1029 (!is_vf || f->is_vf) &&
1030 (!is_netdev || f->is_netdev))
1031 return f;
1032 }
1033 return NULL;
1034}
1035
1036/**
1037 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1038 * @vsi: the VSI to be searched
1039 *
1040 * Returns true if VSI is in vlan mode or false otherwise
1041 **/
1042bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1043{
1044 struct i40e_mac_filter *f;
1045
1046 /* Only -1 for all the filters denotes not in vlan mode
1047 * so we have to go through all the list in order to make sure
1048 */
1049 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1050 if (f->vlan >= 0)
1051 return true;
1052 }
1053
1054 return false;
1055}
1056
1057/**
1058 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1059 * @vsi: the VSI to be searched
1060 * @macaddr: the mac address to be filtered
1061 * @is_vf: true if it is a vf
1062 * @is_netdev: true if it is a netdev
1063 *
1064 * Goes through all the macvlan filters and adds a
1065 * macvlan filter for each unique vlan that already exists
1066 *
1067 * Returns first filter found on success, else NULL
1068 **/
1069struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1070 bool is_vf, bool is_netdev)
1071{
1072 struct i40e_mac_filter *f;
1073
1074 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1075 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev)) {
1077 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1078 is_vf, is_netdev))
41c445ff
JB		 1079 return NULL;
1080 }
1081 }
1082
1083 return list_first_entry_or_null(&vsi->mac_filter_list,
1084 struct i40e_mac_filter, list);
1085}
1086
1087/**
1088 * i40e_add_filter - Add a mac/vlan filter to the VSI
1089 * @vsi: the VSI to be searched
1090 * @macaddr: the MAC address
1091 * @vlan: the vlan
1092 * @is_vf: make sure its a vf filter, else doesn't matter
1093 * @is_netdev: make sure its a netdev filter, else doesn't matter
1094 *
1095 * Returns ptr to the filter object or NULL when no memory available.
1096 **/
1097struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1098 u8 *macaddr, s16 vlan,
1099 bool is_vf, bool is_netdev)
1100{
1101 struct i40e_mac_filter *f;
1102
1103 if (!vsi || !macaddr)
1104 return NULL;
1105
1106 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1107 if (!f) {
1108 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1109 if (!f)
1110 goto add_filter_out;
1111
1112 memcpy(f->macaddr, macaddr, ETH_ALEN);
1113 f->vlan = vlan;
1114 f->changed = true;
1115
1116 INIT_LIST_HEAD(&f->list);
1117 list_add(&f->list, &vsi->mac_filter_list);
1118 }
1119
1120 /* increment counter and add a new flag if needed */
1121 if (is_vf) {
1122 if (!f->is_vf) {
1123 f->is_vf = true;
1124 f->counter++;
1125 }
1126 } else if (is_netdev) {
1127 if (!f->is_netdev) {
1128 f->is_netdev = true;
1129 f->counter++;
1130 }
1131 } else {
1132 f->counter++;
1133 }
1134
1135 /* changed tells sync_filters_subtask to
1136 * push the filter down to the firmware
1137 */
1138 if (f->changed) {
1139 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1140 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1141 }
1142
1143add_filter_out:
1144 return f;
1145}
1146
1147/**
1148 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1149 * @vsi: the VSI to be searched
1150 * @macaddr: the MAC address
1151 * @vlan: the vlan
1152 * @is_vf: make sure it's a vf filter, else doesn't matter
1153 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1154 **/
1155void i40e_del_filter(struct i40e_vsi *vsi,
1156 u8 *macaddr, s16 vlan,
1157 bool is_vf, bool is_netdev)
1158{
1159 struct i40e_mac_filter *f;
1160
1161 if (!vsi || !macaddr)
1162 return;
1163
1164 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1165 if (!f || f->counter == 0)
1166 return;
1167
1168 if (is_vf) {
1169 if (f->is_vf) {
1170 f->is_vf = false;
1171 f->counter--;
1172 }
1173 } else if (is_netdev) {
1174 if (f->is_netdev) {
1175 f->is_netdev = false;
1176 f->counter--;
1177 }
1178 } else {
1179 /* make sure we don't remove a filter in use by vf or netdev */
1180 int min_f = 0;
1181 min_f += (f->is_vf ? 1 : 0);
1182 min_f += (f->is_netdev ? 1 : 0);
1183
1184 if (f->counter > min_f)
1185 f->counter--;
1186 }
1187
1188 /* counter == 0 tells sync_filters_subtask to
1189 * remove the filter from the firmware's list
1190 */
1191 if (f->counter == 0) {
1192 f->changed = true;
1193 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1194 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1195 }
1196}
1197
1198/**
1199 * i40e_set_mac - NDO callback to set mac address
1200 * @netdev: network interface device structure
1201 * @p: pointer to an address structure
1202 *
1203 * Returns 0 on success, negative on failure
1204 **/
1205static int i40e_set_mac(struct net_device *netdev, void *p)
1206{
1207 struct i40e_netdev_priv *np = netdev_priv(netdev);
1208 struct i40e_vsi *vsi = np->vsi;
1209 struct sockaddr *addr = p;
1210 struct i40e_mac_filter *f;
1211
1212 if (!is_valid_ether_addr(addr->sa_data))
1213 return -EADDRNOTAVAIL;
1214
1215 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1216
1217 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1218 return 0;
1219
80f6428f
ASJ		 1220 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1221 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1222 return -EADDRNOTAVAIL;
1223
41c445ff
JB		 1224 if (vsi->type == I40E_VSI_MAIN) {
1225 i40e_status ret;
1226 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1227 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1228 addr->sa_data, NULL);
1229 if (ret) {
1230 netdev_info(netdev,
1231 "Addr change for Main VSI failed: %d\n",
1232 ret);
1233 return -EADDRNOTAVAIL;
1234 }
1235
1236 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1237 }
1238
1239 /* In order to be sure to not drop any packets, add the new address
1240 * then delete the old one.
1241 */
1242 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1243 if (!f)
1244 return -ENOMEM;
1245
1246 i40e_sync_vsi_filters(vsi);
1247 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1248 i40e_sync_vsi_filters(vsi);
1249
1250 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1251
1252 return 0;
1253}
1254
1255/**
1256 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1257 * @vsi: the VSI being setup
1258 * @ctxt: VSI context structure
1259 * @enabled_tc: Enabled TCs bitmap
1260 * @is_add: True if called before Add VSI
1261 *
1262 * Setup VSI queue mapping for enabled traffic classes.
1263 **/
1264static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1265 struct i40e_vsi_context *ctxt,
1266 u8 enabled_tc,
1267 bool is_add)
1268{
1269 struct i40e_pf *pf = vsi->back;
1270 u16 sections = 0;
1271 u8 netdev_tc = 0;
1272 u16 numtc = 0;
1273 u16 qcount;
1274 u8 offset;
1275 u16 qmap;
1276 int i;
4e3b35b0 1277 u16 num_tc_qps = 0;
41c445ff
JB		 1278
1279 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1280 offset = 0;
1281
1282 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1283 /* Find numtc from enabled TC bitmap */
1284 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1285 if (enabled_tc & (1 << i)) /* TC is enabled */
1286 numtc++;
1287 }
1288 if (!numtc) {
1289 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1290 numtc = 1;
1291 }
1292 } else {
1293 /* At least TC0 is enabled in case of non-DCB case */
1294 numtc = 1;
1295 }
1296
1297 vsi->tc_config.numtc = numtc;
1298 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1299 /* Number of queues per enabled TC */
1300 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1301 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1302
1303 /* Setup queue offset/count for all TCs for given VSI */
1304 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1305 /* See if the given TC is enabled for the given VSI */
1306 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1307 int pow, num_qps;
1308
41c445ff
JB		 1309 switch (vsi->type) {
1310 case I40E_VSI_MAIN:
4e3b35b0 1311 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1312 break;
1313 case I40E_VSI_FDIR:
1314 case I40E_VSI_SRIOV:
1315 case I40E_VSI_VMDQ2:
1316 default:
4e3b35b0 1317 qcount = num_tc_qps;
41c445ff
JB		 1318 WARN_ON(i != 0);
1319 break;
1320 }
4e3b35b0
NP		 1321 vsi->tc_config.tc_info[i].qoffset = offset;
1322 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1323
1324 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1325 num_qps = qcount;
41c445ff 1326 pow = 0;
4e3b35b0 1327 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1328 pow++;
1329 num_qps >>= 1;
1330 }
1331
1332 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1333 qmap =
1334 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1335 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1336
4e3b35b0 1337 offset += qcount;
41c445ff
JB		 1338 } else {
1339 /* TC is not enabled so set the offset to
1340 * default queue and allocate one queue
1341 * for the given TC.
1342 */
1343 vsi->tc_config.tc_info[i].qoffset = 0;
1344 vsi->tc_config.tc_info[i].qcount = 1;
1345 vsi->tc_config.tc_info[i].netdev_tc = 0;
1346
1347 qmap = 0;
1348 }
1349 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1350 }
1351
1352 /* Set actual Tx/Rx queue pairs */
1353 vsi->num_queue_pairs = offset;
1354
1355 /* Scheduler section valid can only be set for ADD VSI */
1356 if (is_add) {
1357 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1358
1359 ctxt->info.up_enable_bits = enabled_tc;
1360 }
1361 if (vsi->type == I40E_VSI_SRIOV) {
1362 ctxt->info.mapping_flags |=
1363 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1364 for (i = 0; i < vsi->num_queue_pairs; i++)
1365 ctxt->info.queue_mapping[i] =
1366 cpu_to_le16(vsi->base_queue + i);
1367 } else {
1368 ctxt->info.mapping_flags |=
1369 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1370 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1371 }
1372 ctxt->info.valid_sections |= cpu_to_le16(sections);
1373}
1374
1375/**
1376 * i40e_set_rx_mode - NDO callback to set the netdev filters
1377 * @netdev: network interface device structure
1378 **/
1379static void i40e_set_rx_mode(struct net_device *netdev)
1380{
1381 struct i40e_netdev_priv *np = netdev_priv(netdev);
1382 struct i40e_mac_filter *f, *ftmp;
1383 struct i40e_vsi *vsi = np->vsi;
1384 struct netdev_hw_addr *uca;
1385 struct netdev_hw_addr *mca;
1386 struct netdev_hw_addr *ha;
1387
1388 /* add addr if not already in the filter list */
1389 netdev_for_each_uc_addr(uca, netdev) {
1390 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1391 if (i40e_is_vsi_in_vlan(vsi))
1392 i40e_put_mac_in_vlan(vsi, uca->addr,
1393 false, true);
1394 else
1395 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1396 false, true);
1397 }
1398 }
1399
1400 netdev_for_each_mc_addr(mca, netdev) {
1401 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1402 if (i40e_is_vsi_in_vlan(vsi))
1403 i40e_put_mac_in_vlan(vsi, mca->addr,
1404 false, true);
1405 else
1406 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1407 false, true);
1408 }
1409 }
1410
1411 /* remove filter if not in netdev list */
1412 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1413 bool found = false;
1414
1415 if (!f->is_netdev)
1416 continue;
1417
1418 if (is_multicast_ether_addr(f->macaddr)) {
1419 netdev_for_each_mc_addr(mca, netdev) {
1420 if (ether_addr_equal(mca->addr, f->macaddr)) {
1421 found = true;
1422 break;
1423 }
1424 }
1425 } else {
1426 netdev_for_each_uc_addr(uca, netdev) {
1427 if (ether_addr_equal(uca->addr, f->macaddr)) {
1428 found = true;
1429 break;
1430 }
1431 }
1432
1433 for_each_dev_addr(netdev, ha) {
1434 if (ether_addr_equal(ha->addr, f->macaddr)) {
1435 found = true;
1436 break;
1437 }
1438 }
1439 }
1440 if (!found)
1441 i40e_del_filter(
1442 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1443 }
1444
1445 /* check for other flag changes */
1446 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1447 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1448 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1449 }
1450}
1451
1452/**
1453 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1454 * @vsi: ptr to the VSI
1455 *
1456 * Push any outstanding VSI filter changes through the AdminQ.
1457 *
1458 * Returns 0 or error value
1459 **/
1460int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1461{
1462 struct i40e_mac_filter *f, *ftmp;
1463 bool promisc_forced_on = false;
1464 bool add_happened = false;
1465 int filter_list_len = 0;
1466 u32 changed_flags = 0;
dcae29be 1467 i40e_status aq_ret = 0;
41c445ff
JB		 1468 struct i40e_pf *pf;
1469 int num_add = 0;
1470 int num_del = 0;
1471 u16 cmd_flags;
1472
1473 /* empty array typed pointers, kcalloc later */
1474 struct i40e_aqc_add_macvlan_element_data *add_list;
1475 struct i40e_aqc_remove_macvlan_element_data *del_list;
1476
1477 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1478 usleep_range(1000, 2000);
1479 pf = vsi->back;
1480
1481 if (vsi->netdev) {
1482 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1483 vsi->current_netdev_flags = vsi->netdev->flags;
1484 }
1485
1486 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1487 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1488
1489 filter_list_len = pf->hw.aq.asq_buf_size /
1490 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1491 del_list = kcalloc(filter_list_len,
1492 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1493 GFP_KERNEL);
1494 if (!del_list)
1495 return -ENOMEM;
1496
1497 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1498 if (!f->changed)
1499 continue;
1500
1501 if (f->counter != 0)
1502 continue;
1503 f->changed = false;
1504 cmd_flags = 0;
1505
1506 /* add to delete list */
1507 memcpy(del_list[num_del].mac_addr,
1508 f->macaddr, ETH_ALEN);
1509 del_list[num_del].vlan_tag =
1510 cpu_to_le16((u16)(f->vlan ==
1511 I40E_VLAN_ANY ? 0 : f->vlan));
1512
41c445ff
JB		 1513 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1514 del_list[num_del].flags = cmd_flags;
1515 num_del++;
1516
1517 /* unlink from filter list */
1518 list_del(&f->list);
1519 kfree(f);
1520
1521 /* flush a full buffer */
1522 if (num_del == filter_list_len) {
dcae29be 1523 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1524 vsi->seid, del_list, num_del,
1525 NULL);
1526 num_del = 0;
1527 memset(del_list, 0, sizeof(*del_list));
1528
dcae29be 1529 if (aq_ret)
41c445ff
JB		 1530 dev_info(&pf->pdev->dev,
1531 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1532 aq_ret,
41c445ff
JB		 1533 pf->hw.aq.asq_last_status);
1534 }
1535 }
1536 if (num_del) {
dcae29be 1537 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1538 del_list, num_del, NULL);
1539 num_del = 0;
1540
dcae29be 1541 if (aq_ret)
41c445ff
JB		 1542 dev_info(&pf->pdev->dev,
1543 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1544 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1545 }
1546
1547 kfree(del_list);
1548 del_list = NULL;
1549
1550 /* do all the adds now */
1551 filter_list_len = pf->hw.aq.asq_buf_size /
1552 sizeof(struct i40e_aqc_add_macvlan_element_data),
1553 add_list = kcalloc(filter_list_len,
1554 sizeof(struct i40e_aqc_add_macvlan_element_data),
1555 GFP_KERNEL);
1556 if (!add_list)
1557 return -ENOMEM;
1558
1559 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1560 if (!f->changed)
1561 continue;
1562
1563 if (f->counter == 0)
1564 continue;
1565 f->changed = false;
1566 add_happened = true;
1567 cmd_flags = 0;
1568
1569 /* add to add array */
1570 memcpy(add_list[num_add].mac_addr,
1571 f->macaddr, ETH_ALEN);
1572 add_list[num_add].vlan_tag =
1573 cpu_to_le16(
1574 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1575 add_list[num_add].queue_number = 0;
1576
1577 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1578 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1579 num_add++;
1580
1581 /* flush a full buffer */
1582 if (num_add == filter_list_len) {
dcae29be
JB		 1583 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1584 add_list, num_add,
1585 NULL);
41c445ff
JB		 1586 num_add = 0;
1587
dcae29be 1588 if (aq_ret)
41c445ff
JB		 1589 break;
1590 memset(add_list, 0, sizeof(*add_list));
1591 }
1592 }
1593 if (num_add) {
dcae29be
JB		 1594 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1595 add_list, num_add, NULL);
41c445ff
JB		 1596 num_add = 0;
1597 }
1598 kfree(add_list);
1599 add_list = NULL;
1600
dcae29be 1601 if (add_happened && (!aq_ret)) {
41c445ff 1602 /* do nothing */;
dcae29be 1603 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1604 dev_info(&pf->pdev->dev,
1605 "add filter failed, err %d, aq_err %d\n",
dcae29be 1606 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1607 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1608 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1609 &vsi->state)) {
1610 promisc_forced_on = true;
1611 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1612 &vsi->state);
1613 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1614 }
1615 }
1616 }
1617
1618 /* check for changes in promiscuous modes */
1619 if (changed_flags & IFF_ALLMULTI) {
1620 bool cur_multipromisc;
1621 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1622 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1623 vsi->seid,
1624 cur_multipromisc,
1625 NULL);
1626 if (aq_ret)
41c445ff
JB		 1627 dev_info(&pf->pdev->dev,
1628 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1629 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1630 }
1631 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1632 bool cur_promisc;
1633 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1634 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1635 &vsi->state));
dcae29be
JB		 1636 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1637 vsi->seid,
1638 cur_promisc, NULL);
1639 if (aq_ret)
41c445ff
JB		 1640 dev_info(&pf->pdev->dev,
1641 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1642 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1643 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1644 vsi->seid,
1645 cur_promisc, NULL);
1646 if (aq_ret)
1647 dev_info(&pf->pdev->dev,
1648 "set brdcast promisc failed, err %d, aq_err %d\n",
1649 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1650 }
1651
1652 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1653 return 0;
1654}
1655
1656/**
1657 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1658 * @pf: board private structure
1659 **/
1660static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1661{
1662 int v;
1663
1664 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1665 return;
1666 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1667
1668 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1669 if (pf->vsi[v] &&
1670 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1671 i40e_sync_vsi_filters(pf->vsi[v]);
1672 }
1673}
1674
1675/**
1676 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1677 * @netdev: network interface device structure
1678 * @new_mtu: new value for maximum frame size
1679 *
1680 * Returns 0 on success, negative on failure
1681 **/
1682static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1683{
1684 struct i40e_netdev_priv *np = netdev_priv(netdev);
1685 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1686 struct i40e_vsi *vsi = np->vsi;
1687
1688 /* MTU < 68 is an error and causes problems on some kernels */
1689 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1690 return -EINVAL;
1691
1692 netdev_info(netdev, "changing MTU from %d to %d\n",
1693 netdev->mtu, new_mtu);
1694 netdev->mtu = new_mtu;
1695 if (netif_running(netdev))
1696 i40e_vsi_reinit_locked(vsi);
1697
1698 return 0;
1699}
1700
beb0dff1
JK		 1701/**
1702 * i40e_ioctl - Access the hwtstamp interface
1703 * @netdev: network interface device structure
1704 * @ifr: interface request data
1705 * @cmd: ioctl command
1706 **/
1707int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1708{
1709 struct i40e_netdev_priv *np = netdev_priv(netdev);
1710 struct i40e_pf *pf = np->vsi->back;
1711
1712 switch (cmd) {
1713 case SIOCGHWTSTAMP:
1714 return i40e_ptp_get_ts_config(pf, ifr);
1715 case SIOCSHWTSTAMP:
1716 return i40e_ptp_set_ts_config(pf, ifr);
1717 default:
1718 return -EOPNOTSUPP;
1719 }
1720}
1721
41c445ff
JB		 1722/**
1723 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1724 * @vsi: the vsi being adjusted
1725 **/
1726void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1727{
1728 struct i40e_vsi_context ctxt;
1729 i40e_status ret;
1730
1731 if ((vsi->info.valid_sections &
1732 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1733 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1734 return; /* already enabled */
1735
1736 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1737 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1738 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1739
1740 ctxt.seid = vsi->seid;
1741 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1742 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1743 if (ret) {
1744 dev_info(&vsi->back->pdev->dev,
1745 "%s: update vsi failed, aq_err=%d\n",
1746 __func__, vsi->back->hw.aq.asq_last_status);
1747 }
1748}
1749
1750/**
1751 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1752 * @vsi: the vsi being adjusted
1753 **/
1754void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1755{
1756 struct i40e_vsi_context ctxt;
1757 i40e_status ret;
1758
1759 if ((vsi->info.valid_sections &
1760 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1761 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1762 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1763 return; /* already disabled */
1764
1765 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1766 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1767 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1768
1769 ctxt.seid = vsi->seid;
1770 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1771 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1772 if (ret) {
1773 dev_info(&vsi->back->pdev->dev,
1774 "%s: update vsi failed, aq_err=%d\n",
1775 __func__, vsi->back->hw.aq.asq_last_status);
1776 }
1777}
1778
1779/**
1780 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1781 * @netdev: network interface to be adjusted
1782 * @features: netdev features to test if VLAN offload is enabled or not
1783 **/
1784static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1785{
1786 struct i40e_netdev_priv *np = netdev_priv(netdev);
1787 struct i40e_vsi *vsi = np->vsi;
1788
1789 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1790 i40e_vlan_stripping_enable(vsi);
1791 else
1792 i40e_vlan_stripping_disable(vsi);
1793}
1794
1795/**
1796 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1797 * @vsi: the vsi being configured
1798 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1799 **/
1800int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1801{
1802 struct i40e_mac_filter *f, *add_f;
1803 bool is_netdev, is_vf;
41c445ff
JB		 1804
1805 is_vf = (vsi->type == I40E_VSI_SRIOV);
1806 is_netdev = !!(vsi->netdev);
1807
1808 if (is_netdev) {
1809 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1810 is_vf, is_netdev);
1811 if (!add_f) {
1812 dev_info(&vsi->back->pdev->dev,
1813 "Could not add vlan filter %d for %pM\n",
1814 vid, vsi->netdev->dev_addr);
1815 return -ENOMEM;
1816 }
1817 }
1818
1819 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1820 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1821 if (!add_f) {
1822 dev_info(&vsi->back->pdev->dev,
1823 "Could not add vlan filter %d for %pM\n",
1824 vid, f->macaddr);
1825 return -ENOMEM;
1826 }
1827 }
1828
41c445ff
JB		 1829 /* Now if we add a vlan tag, make sure to check if it is the first
1830 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1831 * with 0, so we now accept untagged and specified tagged traffic
1832 * (and not any taged and untagged)
1833 */
1834 if (vid > 0) {
1835 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1836 I40E_VLAN_ANY,
1837 is_vf, is_netdev)) {
1838 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1839 I40E_VLAN_ANY, is_vf, is_netdev);
1840 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1841 is_vf, is_netdev);
1842 if (!add_f) {
1843 dev_info(&vsi->back->pdev->dev,
1844 "Could not add filter 0 for %pM\n",
1845 vsi->netdev->dev_addr);
1846 return -ENOMEM;
1847 }
1848 }
8d82a7c5 1849 }
41c445ff 1850
8d82a7c5
GR		 1851 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1852 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1853 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1854 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1855 is_vf, is_netdev)) {
1856 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1857 is_vf, is_netdev);
1858 add_f = i40e_add_filter(vsi, f->macaddr,
1859 0, is_vf, is_netdev);
1860 if (!add_f) {
1861 dev_info(&vsi->back->pdev->dev,
1862 "Could not add filter 0 for %pM\n",
1863 f->macaddr);
1864 return -ENOMEM;
1865 }
1866 }
1867 }
41c445ff
JB		 1868 }
1869
80f6428f
ASJ		 1870 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1871 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1872 return 0;
1873
1874 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1875}
1876
1877/**
1878 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1879 * @vsi: the vsi being configured
1880 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1881 *
1882 * Return: 0 on success or negative otherwise
41c445ff
JB		 1883 **/
1884int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1885{
1886 struct net_device *netdev = vsi->netdev;
1887 struct i40e_mac_filter *f, *add_f;
1888 bool is_vf, is_netdev;
1889 int filter_count = 0;
41c445ff
JB		 1890
1891 is_vf = (vsi->type == I40E_VSI_SRIOV);
1892 is_netdev = !!(netdev);
1893
1894 if (is_netdev)
1895 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1896
1897 list_for_each_entry(f, &vsi->mac_filter_list, list)
1898 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1899
41c445ff
JB		 1900 /* go through all the filters for this VSI and if there is only
1901 * vid == 0 it means there are no other filters, so vid 0 must
1902 * be replaced with -1. This signifies that we should from now
1903 * on accept any traffic (with any tag present, or untagged)
1904 */
1905 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1906 if (is_netdev) {
1907 if (f->vlan &&
1908 ether_addr_equal(netdev->dev_addr, f->macaddr))
1909 filter_count++;
1910 }
1911
1912 if (f->vlan)
1913 filter_count++;
1914 }
1915
1916 if (!filter_count && is_netdev) {
1917 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1918 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1919 is_vf, is_netdev);
1920 if (!f) {
1921 dev_info(&vsi->back->pdev->dev,
1922 "Could not add filter %d for %pM\n",
1923 I40E_VLAN_ANY, netdev->dev_addr);
1924 return -ENOMEM;
1925 }
1926 }
1927
1928 if (!filter_count) {
1929 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1930 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1931 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1932 is_vf, is_netdev);
1933 if (!add_f) {
1934 dev_info(&vsi->back->pdev->dev,
1935 "Could not add filter %d for %pM\n",
1936 I40E_VLAN_ANY, f->macaddr);
1937 return -ENOMEM;
1938 }
1939 }
1940 }
1941
80f6428f
ASJ		 1942 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1943 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1944 return 0;
1945
41c445ff
JB		 1946 return i40e_sync_vsi_filters(vsi);
1947}
1948
1949/**
1950 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1951 * @netdev: network interface to be adjusted
1952 * @vid: vlan id to be added
078b5876
JB		 1953 *
1954 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1955 **/
1956static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1957 __always_unused __be16 proto, u16 vid)
1958{
1959 struct i40e_netdev_priv *np = netdev_priv(netdev);
1960 struct i40e_vsi *vsi = np->vsi;
078b5876 1961 int ret = 0;
41c445ff
JB		 1962
1963 if (vid > 4095)
078b5876
JB		 1964 return -EINVAL;
1965
1966 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1967
41c445ff
JB		 1968 /* If the network stack called us with vid = 0, we should
1969 * indicate to i40e_vsi_add_vlan() that we want to receive
1970 * any traffic (i.e. with any vlan tag, or untagged)
1971 */
1972 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1973
078b5876
JB		 1974 if (!ret && (vid < VLAN_N_VID))
1975 set_bit(vid, vsi->active_vlans);
41c445ff 1976
078b5876 1977 return ret;
41c445ff
JB		 1978}
1979
1980/**
1981 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1982 * @netdev: network interface to be adjusted
1983 * @vid: vlan id to be removed
078b5876
JB		 1984 *
1985 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1986 **/
1987static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1988 __always_unused __be16 proto, u16 vid)
1989{
1990 struct i40e_netdev_priv *np = netdev_priv(netdev);
1991 struct i40e_vsi *vsi = np->vsi;
1992
078b5876
JB		 1993 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1994
41c445ff
JB		 1995 /* return code is ignored as there is nothing a user
1996 * can do about failure to remove and a log message was
078b5876 1997 * already printed from the other function
41c445ff
JB		 1998 */
1999 i40e_vsi_kill_vlan(vsi, vid);
2000
2001 clear_bit(vid, vsi->active_vlans);
078b5876 2002
41c445ff
JB		 2003 return 0;
2004}
2005
2006/**
2007 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2008 * @vsi: the vsi being brought back up
2009 **/
2010static void i40e_restore_vlan(struct i40e_vsi *vsi)
2011{
2012 u16 vid;
2013
2014 if (!vsi->netdev)
2015 return;
2016
2017 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2018
2019 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2020 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2021 vid);
2022}
2023
2024/**
2025 * i40e_vsi_add_pvid - Add pvid for the VSI
2026 * @vsi: the vsi being adjusted
2027 * @vid: the vlan id to set as a PVID
2028 **/
dcae29be 2029int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2030{
2031 struct i40e_vsi_context ctxt;
dcae29be 2032 i40e_status aq_ret;
41c445ff
JB		 2033
2034 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2035 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2036 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2037 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2038 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2039
2040 ctxt.seid = vsi->seid;
2041 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2042 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2043 if (aq_ret) {
41c445ff
JB		 2044 dev_info(&vsi->back->pdev->dev,
2045 "%s: update vsi failed, aq_err=%d\n",
2046 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2047 return -ENOENT;
41c445ff
JB		 2048 }
2049
dcae29be 2050 return 0;
41c445ff
JB		 2051}
2052
2053/**
2054 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2055 * @vsi: the vsi being adjusted
2056 *
2057 * Just use the vlan_rx_register() service to put it back to normal
2058 **/
2059void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2060{
6c12fcbf
GR		 2061 i40e_vlan_stripping_disable(vsi);
2062
41c445ff 2063 vsi->info.pvid = 0;
41c445ff
JB		 2064}
2065
2066/**
2067 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2068 * @vsi: ptr to the VSI
2069 *
2070 * If this function returns with an error, then it's possible one or
2071 * more of the rings is populated (while the rest are not). It is the
2072 * callers duty to clean those orphaned rings.
2073 *
2074 * Return 0 on success, negative on failure
2075 **/
2076static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2077{
2078 int i, err = 0;
2079
2080 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2081 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2082
2083 return err;
2084}
2085
2086/**
2087 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2088 * @vsi: ptr to the VSI
2089 *
2090 * Free VSI's transmit software resources
2091 **/
2092static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2093{
2094 int i;
2095
8e9dca53
GR		 2096 if (!vsi->tx_rings)
2097 return;
2098
41c445ff 2099 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2100 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2101 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2102}
2103
2104/**
2105 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2106 * @vsi: ptr to the VSI
2107 *
2108 * If this function returns with an error, then it's possible one or
2109 * more of the rings is populated (while the rest are not). It is the
2110 * callers duty to clean those orphaned rings.
2111 *
2112 * Return 0 on success, negative on failure
2113 **/
2114static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2115{
2116 int i, err = 0;
2117
2118 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2119 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2120 return err;
2121}
2122
2123/**
2124 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2125 * @vsi: ptr to the VSI
2126 *
2127 * Free all receive software resources
2128 **/
2129static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2130{
2131 int i;
2132
8e9dca53
GR		 2133 if (!vsi->rx_rings)
2134 return;
2135
41c445ff 2136 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2137 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2138 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2139}
2140
2141/**
2142 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2143 * @ring: The Tx ring to configure
2144 *
2145 * Configure the Tx descriptor ring in the HMC context.
2146 **/
2147static int i40e_configure_tx_ring(struct i40e_ring *ring)
2148{
2149 struct i40e_vsi *vsi = ring->vsi;
2150 u16 pf_q = vsi->base_queue + ring->queue_index;
2151 struct i40e_hw *hw = &vsi->back->hw;
2152 struct i40e_hmc_obj_txq tx_ctx;
2153 i40e_status err = 0;
2154 u32 qtx_ctl = 0;
2155
2156 /* some ATR related tx ring init */
60ea5f83 2157 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2158 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2159 ring->atr_count = 0;
2160 } else {
2161 ring->atr_sample_rate = 0;
2162 }
2163
2164 /* initialize XPS */
2165 if (ring->q_vector && ring->netdev &&
4e3b35b0 2166 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2167 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2168 netif_set_xps_queue(ring->netdev,
2169 &ring->q_vector->affinity_mask,
2170 ring->queue_index);
2171
2172 /* clear the context structure first */
2173 memset(&tx_ctx, 0, sizeof(tx_ctx));
2174
2175 tx_ctx.new_context = 1;
2176 tx_ctx.base = (ring->dma / 128);
2177 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2178 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2179 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2180 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
41c445ff
JB		 2181
2182 /* As part of VSI creation/update, FW allocates certain
2183 * Tx arbitration queue sets for each TC enabled for
2184 * the VSI. The FW returns the handles to these queue
2185 * sets as part of the response buffer to Add VSI,
2186 * Update VSI, etc. AQ commands. It is expected that
2187 * these queue set handles be associated with the Tx
2188 * queues by the driver as part of the TX queue context
2189 * initialization. This has to be done regardless of
2190 * DCB as by default everything is mapped to TC0.
2191 */
2192 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2193 tx_ctx.rdylist_act = 0;
2194
2195 /* clear the context in the HMC */
2196 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2197 if (err) {
2198 dev_info(&vsi->back->pdev->dev,
2199 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2200 ring->queue_index, pf_q, err);
2201 return -ENOMEM;
2202 }
2203
2204 /* set the context in the HMC */
2205 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2206 if (err) {
2207 dev_info(&vsi->back->pdev->dev,
2208 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2209 ring->queue_index, pf_q, err);
2210 return -ENOMEM;
2211 }
2212
2213 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2214 if (vsi->type == I40E_VSI_VMDQ2)
2215 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2216 else
2217 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2218 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2219 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2220 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2221 i40e_flush(hw);
2222
2223 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2224
2225 /* cache tail off for easier writes later */
2226 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2227
2228 return 0;
2229}
2230
2231/**
2232 * i40e_configure_rx_ring - Configure a receive ring context
2233 * @ring: The Rx ring to configure
2234 *
2235 * Configure the Rx descriptor ring in the HMC context.
2236 **/
2237static int i40e_configure_rx_ring(struct i40e_ring *ring)
2238{
2239 struct i40e_vsi *vsi = ring->vsi;
2240 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2241 u16 pf_q = vsi->base_queue + ring->queue_index;
2242 struct i40e_hw *hw = &vsi->back->hw;
2243 struct i40e_hmc_obj_rxq rx_ctx;
2244 i40e_status err = 0;
2245
2246 ring->state = 0;
2247
2248 /* clear the context structure first */
2249 memset(&rx_ctx, 0, sizeof(rx_ctx));
2250
2251 ring->rx_buf_len = vsi->rx_buf_len;
2252 ring->rx_hdr_len = vsi->rx_hdr_len;
2253
2254 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2255 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2256
2257 rx_ctx.base = (ring->dma / 128);
2258 rx_ctx.qlen = ring->count;
2259
2260 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2261 set_ring_16byte_desc_enabled(ring);
2262 rx_ctx.dsize = 0;
2263 } else {
2264 rx_ctx.dsize = 1;
2265 }
2266
2267 rx_ctx.dtype = vsi->dtype;
2268 if (vsi->dtype) {
2269 set_ring_ps_enabled(ring);
2270 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2271 I40E_RX_SPLIT_IP |
2272 I40E_RX_SPLIT_TCP_UDP |
2273 I40E_RX_SPLIT_SCTP;
2274 } else {
2275 rx_ctx.hsplit_0 = 0;
2276 }
2277
2278 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2279 (chain_len * ring->rx_buf_len));
2280 rx_ctx.tphrdesc_ena = 1;
2281 rx_ctx.tphwdesc_ena = 1;
2282 rx_ctx.tphdata_ena = 1;
2283 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2284 if (hw->revision_id == 0)
2285 rx_ctx.lrxqthresh = 0;
2286 else
2287 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2288 rx_ctx.crcstrip = 1;
2289 rx_ctx.l2tsel = 1;
2290 rx_ctx.showiv = 1;
2291
2292 /* clear the context in the HMC */
2293 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2294 if (err) {
2295 dev_info(&vsi->back->pdev->dev,
2296 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2297 ring->queue_index, pf_q, err);
2298 return -ENOMEM;
2299 }
2300
2301 /* set the context in the HMC */
2302 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2303 if (err) {
2304 dev_info(&vsi->back->pdev->dev,
2305 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2306 ring->queue_index, pf_q, err);
2307 return -ENOMEM;
2308 }
2309
2310 /* cache tail for quicker writes, and clear the reg before use */
2311 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2312 writel(0, ring->tail);
2313
2314 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2315
2316 return 0;
2317}
2318
2319/**
2320 * i40e_vsi_configure_tx - Configure the VSI for Tx
2321 * @vsi: VSI structure describing this set of rings and resources
2322 *
2323 * Configure the Tx VSI for operation.
2324 **/
2325static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2326{
2327 int err = 0;
2328 u16 i;
2329
9f65e15b
AD		 2330 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2331 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2332
2333 return err;
2334}
2335
2336/**
2337 * i40e_vsi_configure_rx - Configure the VSI for Rx
2338 * @vsi: the VSI being configured
2339 *
2340 * Configure the Rx VSI for operation.
2341 **/
2342static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2343{
2344 int err = 0;
2345 u16 i;
2346
2347 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2348 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2349 + ETH_FCS_LEN + VLAN_HLEN;
2350 else
2351 vsi->max_frame = I40E_RXBUFFER_2048;
2352
2353 /* figure out correct receive buffer length */
2354 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2355 I40E_FLAG_RX_PS_ENABLED)) {
2356 case I40E_FLAG_RX_1BUF_ENABLED:
2357 vsi->rx_hdr_len = 0;
2358 vsi->rx_buf_len = vsi->max_frame;
2359 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2360 break;
2361 case I40E_FLAG_RX_PS_ENABLED:
2362 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2363 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2364 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2365 break;
2366 default:
2367 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2368 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2369 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2370 break;
2371 }
2372
2373 /* round up for the chip's needs */
2374 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2375 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2376 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2377 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2378
2379 /* set up individual rings */
2380 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2381 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2382
2383 return err;
2384}
2385
2386/**
2387 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2388 * @vsi: ptr to the VSI
2389 **/
2390static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2391{
2392 u16 qoffset, qcount;
2393 int i, n;
2394
2395 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2396 return;
2397
2398 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2399 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2400 continue;
2401
2402 qoffset = vsi->tc_config.tc_info[n].qoffset;
2403 qcount = vsi->tc_config.tc_info[n].qcount;
2404 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2405 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2406 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2407 rx_ring->dcb_tc = n;
2408 tx_ring->dcb_tc = n;
2409 }
2410 }
2411}
2412
2413/**
2414 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2415 * @vsi: ptr to the VSI
2416 **/
2417static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2418{
2419 if (vsi->netdev)
2420 i40e_set_rx_mode(vsi->netdev);
2421}
2422
17a73f6b
JG		 2423/**
2424 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2425 * @vsi: Pointer to the targeted VSI
2426 *
2427 * This function replays the hlist on the hw where all the SB Flow Director
2428 * filters were saved.
2429 **/
2430static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2431{
2432 struct i40e_fdir_filter *filter;
2433 struct i40e_pf *pf = vsi->back;
2434 struct hlist_node *node;
2435
2436 hlist_for_each_entry_safe(filter, node,
2437 &pf->fdir_filter_list, fdir_node) {
2438 i40e_add_del_fdir(vsi, filter, true);
2439 }
2440}
2441
41c445ff
JB		 2442/**
2443 * i40e_vsi_configure - Set up the VSI for action
2444 * @vsi: the VSI being configured
2445 **/
2446static int i40e_vsi_configure(struct i40e_vsi *vsi)
2447{
2448 int err;
2449
2450 i40e_set_vsi_rx_mode(vsi);
2451 i40e_restore_vlan(vsi);
2452 i40e_vsi_config_dcb_rings(vsi);
17a73f6b
JG		 2453 if (vsi->type == I40E_VSI_FDIR)
2454 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 2455 err = i40e_vsi_configure_tx(vsi);
2456 if (!err)
2457 err = i40e_vsi_configure_rx(vsi);
2458
2459 return err;
2460}
2461
2462/**
2463 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2464 * @vsi: the VSI being configured
2465 **/
2466static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2467{
2468 struct i40e_pf *pf = vsi->back;
2469 struct i40e_q_vector *q_vector;
2470 struct i40e_hw *hw = &pf->hw;
2471 u16 vector;
2472 int i, q;
2473 u32 val;
2474 u32 qp;
2475
2476 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2477 * and PFINT_LNKLSTn registers, e.g.:
2478 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2479 */
2480 qp = vsi->base_queue;
2481 vector = vsi->base_vector;
493fb300
AD		 2482 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2483 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2484 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2485 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2486 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2487 q_vector->rx.itr);
2488 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2489 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2490 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2491 q_vector->tx.itr);
2492
2493 /* Linked list for the queuepairs assigned to this vector */
2494 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2495 for (q = 0; q < q_vector->num_ringpairs; q++) {
2496 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2497 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2498 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2499 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2500 (I40E_QUEUE_TYPE_TX
2501 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2502
2503 wr32(hw, I40E_QINT_RQCTL(qp), val);
2504
2505 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2506 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2507 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2508 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2509 (I40E_QUEUE_TYPE_RX
2510 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2511
2512 /* Terminate the linked list */
2513 if (q == (q_vector->num_ringpairs - 1))
2514 val |= (I40E_QUEUE_END_OF_LIST
2515 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2516
2517 wr32(hw, I40E_QINT_TQCTL(qp), val);
2518 qp++;
2519 }
2520 }
2521
2522 i40e_flush(hw);
2523}
2524
2525/**
2526 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2527 * @hw: ptr to the hardware info
2528 **/
2529static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2530{
2531 u32 val;
2532
2533 /* clear things first */
2534 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2535 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2536
2537 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2538 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2539 I40E_PFINT_ICR0_ENA_GRST_MASK |
2540 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2541 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2542 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2543 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2544 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2545 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2546 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2547
2548 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2549
2550 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2551 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2552 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2553
2554 /* OTHER_ITR_IDX = 0 */
2555 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2556}
2557
2558/**
2559 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2560 * @vsi: the VSI being configured
2561 **/
2562static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2563{
493fb300 2564 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2565 struct i40e_pf *pf = vsi->back;
2566 struct i40e_hw *hw = &pf->hw;
2567 u32 val;
2568
2569 /* set the ITR configuration */
2570 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2571 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2572 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2573 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2574 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2575 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2576
2577 i40e_enable_misc_int_causes(hw);
2578
2579 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2580 wr32(hw, I40E_PFINT_LNKLST0, 0);
2581
2582 /* Associate the queue pair to the vector and enable the q int */
2583 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2584 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2585 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2586
2587 wr32(hw, I40E_QINT_RQCTL(0), val);
2588
2589 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2590 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2591 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2592
2593 wr32(hw, I40E_QINT_TQCTL(0), val);
2594 i40e_flush(hw);
2595}
2596
2ef28cfb
MW		 2597/**
2598 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2599 * @pf: board private structure
2600 **/
2601void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2602{
2603 struct i40e_hw *hw = &pf->hw;
2604
2605 wr32(hw, I40E_PFINT_DYN_CTL0,
2606 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2607 i40e_flush(hw);
2608}
2609
41c445ff
JB		 2610/**
2611 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2612 * @pf: board private structure
2613 **/
116a57d4 2614void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2615{
2616 struct i40e_hw *hw = &pf->hw;
2617 u32 val;
2618
2619 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2620 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2621 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2622
2623 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2624 i40e_flush(hw);
2625}
2626
2627/**
2628 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2629 * @vsi: pointer to a vsi
2630 * @vector: enable a particular Hw Interrupt vector
2631 **/
2632void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2633{
2634 struct i40e_pf *pf = vsi->back;
2635 struct i40e_hw *hw = &pf->hw;
2636 u32 val;
2637
2638 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2639 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2640 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2641 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2642 /* skip the flush */
41c445ff
JB		 2643}
2644
2645/**
2646 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2647 * @irq: interrupt number
2648 * @data: pointer to a q_vector
2649 **/
2650static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2651{
2652 struct i40e_q_vector *q_vector = data;
2653
cd0b6fa6 2654 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2655 return IRQ_HANDLED;
2656
2657 napi_schedule(&q_vector->napi);
2658
2659 return IRQ_HANDLED;
2660}
2661
41c445ff
JB		 2662/**
2663 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2664 * @vsi: the VSI being configured
2665 * @basename: name for the vector
2666 *
2667 * Allocates MSI-X vectors and requests interrupts from the kernel.
2668 **/
2669static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2670{
2671 int q_vectors = vsi->num_q_vectors;
2672 struct i40e_pf *pf = vsi->back;
2673 int base = vsi->base_vector;
2674 int rx_int_idx = 0;
2675 int tx_int_idx = 0;
2676 int vector, err;
2677
2678 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2679 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2680
cd0b6fa6 2681 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2682 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2683 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2684 tx_int_idx++;
cd0b6fa6 2685 } else if (q_vector->rx.ring) {
41c445ff
JB		 2686 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2687 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2688 } else if (q_vector->tx.ring) {
41c445ff
JB		 2689 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2690 "%s-%s-%d", basename, "tx", tx_int_idx++);
2691 } else {
2692 /* skip this unused q_vector */
2693 continue;
2694 }
2695 err = request_irq(pf->msix_entries[base + vector].vector,
2696 vsi->irq_handler,
2697 0,
2698 q_vector->name,
2699 q_vector);
2700 if (err) {
2701 dev_info(&pf->pdev->dev,
2702 "%s: request_irq failed, error: %d\n",
2703 __func__, err);
2704 goto free_queue_irqs;
2705 }
2706 /* assign the mask for this irq */
2707 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2708 &q_vector->affinity_mask);
2709 }
2710
2711 return 0;
2712
2713free_queue_irqs:
2714 while (vector) {
2715 vector--;
2716 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2717 NULL);
2718 free_irq(pf->msix_entries[base + vector].vector,
2719 &(vsi->q_vectors[vector]));
2720 }
2721 return err;
2722}
2723
2724/**
2725 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2726 * @vsi: the VSI being un-configured
2727 **/
2728static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2729{
2730 struct i40e_pf *pf = vsi->back;
2731 struct i40e_hw *hw = &pf->hw;
2732 int base = vsi->base_vector;
2733 int i;
2734
2735 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2736 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2737 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2738 }
2739
2740 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2741 for (i = vsi->base_vector;
2742 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2743 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2744
2745 i40e_flush(hw);
2746 for (i = 0; i < vsi->num_q_vectors; i++)
2747 synchronize_irq(pf->msix_entries[i + base].vector);
2748 } else {
2749 /* Legacy and MSI mode - this stops all interrupt handling */
2750 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2751 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2752 i40e_flush(hw);
2753 synchronize_irq(pf->pdev->irq);
2754 }
2755}
2756
2757/**
2758 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2759 * @vsi: the VSI being configured
2760 **/
2761static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2762{
2763 struct i40e_pf *pf = vsi->back;
2764 int i;
2765
2766 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2767 for (i = vsi->base_vector;
2768 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2769 i40e_irq_dynamic_enable(vsi, i);
2770 } else {
2771 i40e_irq_dynamic_enable_icr0(pf);
2772 }
2773
1022cb6c 2774 i40e_flush(&pf->hw);
41c445ff
JB		 2775 return 0;
2776}
2777
2778/**
2779 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2780 * @pf: board private structure
2781 **/
2782static void i40e_stop_misc_vector(struct i40e_pf *pf)
2783{
2784 /* Disable ICR 0 */
2785 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2786 i40e_flush(&pf->hw);
2787}
2788
2789/**
2790 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2791 * @irq: interrupt number
2792 * @data: pointer to a q_vector
2793 *
2794 * This is the handler used for all MSI/Legacy interrupts, and deals
2795 * with both queue and non-queue interrupts. This is also used in
2796 * MSIX mode to handle the non-queue interrupts.
2797 **/
2798static irqreturn_t i40e_intr(int irq, void *data)
2799{
2800 struct i40e_pf *pf = (struct i40e_pf *)data;
2801 struct i40e_hw *hw = &pf->hw;
5e823066 2802 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2803 u32 icr0, icr0_remaining;
2804 u32 val, ena_mask;
2805
2806 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2807 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2808
116a57d4
SN		 2809 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2810 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2811 goto enable_intr;
41c445ff 2812
cd92e72f
SN		 2813 /* if interrupt but no bits showing, must be SWINT */
2814 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2815 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2816 pf->sw_int_count++;
2817
41c445ff
JB		 2818 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2819 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2820
2821 /* temporarily disable queue cause for NAPI processing */
2822 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2823 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2824 wr32(hw, I40E_QINT_RQCTL(0), qval);
2825
2826 qval = rd32(hw, I40E_QINT_TQCTL(0));
2827 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2828 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2829
2830 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2831 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2832 }
2833
2834 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2835 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2836 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2837 }
2838
2839 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2840 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2841 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2842 }
2843
2844 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2845 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2846 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2847 }
2848
2849 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2850 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2851 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2852 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2853 val = rd32(hw, I40E_GLGEN_RSTAT);
2854 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2855 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2856 if (val == I40E_RESET_CORER)
41c445ff 2857 pf->corer_count++;
d52cf0a9 2858 else if (val == I40E_RESET_GLOBR)
41c445ff 2859 pf->globr_count++;
d52cf0a9 2860 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2861 pf->empr_count++;
2862 }
2863
9c010ee0
ASJ		 2864 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2865 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2866 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2867 }
2868
beb0dff1
JK		 2869 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2870 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2871
2872 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2873 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2874 i40e_ptp_tx_hwtstamp(pf);
2875 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2876 }
2877
2878 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2879 }
2880
41c445ff
JB		 2881 /* If a critical error is pending we have no choice but to reset the
2882 * device.
2883 * Report and mask out any remaining unexpected interrupts.
2884 */
2885 icr0_remaining = icr0 & ena_mask;
2886 if (icr0_remaining) {
2887 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2888 icr0_remaining);
9c010ee0 2889 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2890 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2891 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2892 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2893 dev_info(&pf->pdev->dev, "device will be reset\n");
2894 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2895 i40e_service_event_schedule(pf);
41c445ff
JB		 2896 }
2897 ena_mask &= ~icr0_remaining;
2898 }
5e823066 2899 ret = IRQ_HANDLED;
41c445ff 2900
5e823066 2901enable_intr:
41c445ff
JB		 2902 /* re-enable interrupt causes */
2903 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2904 if (!test_bit(__I40E_DOWN, &pf->state)) {
2905 i40e_service_event_schedule(pf);
2906 i40e_irq_dynamic_enable_icr0(pf);
2907 }
2908
5e823066 2909 return ret;
41c445ff
JB		 2910}
2911
cbf61325
ASJ		 2912/**
2913 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2914 * @tx_ring: tx ring to clean
2915 * @budget: how many cleans we're allowed
2916 *
2917 * Returns true if there's any budget left (e.g. the clean is finished)
2918 **/
2919static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2920{
2921 struct i40e_vsi *vsi = tx_ring->vsi;
2922 u16 i = tx_ring->next_to_clean;
2923 struct i40e_tx_buffer *tx_buf;
2924 struct i40e_tx_desc *tx_desc;
2925
2926 tx_buf = &tx_ring->tx_bi[i];
2927 tx_desc = I40E_TX_DESC(tx_ring, i);
2928 i -= tx_ring->count;
2929
2930 do {
2931 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2932
2933 /* if next_to_watch is not set then there is no work pending */
2934 if (!eop_desc)
2935 break;
2936
2937 /* prevent any other reads prior to eop_desc */
2938 read_barrier_depends();
2939
2940 /* if the descriptor isn't done, no work yet to do */
2941 if (!(eop_desc->cmd_type_offset_bsz &
2942 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2943 break;
2944
2945 /* clear next_to_watch to prevent false hangs */
2946 tx_buf->next_to_watch = NULL;
2947
2948 /* unmap skb header data */
2949 dma_unmap_single(tx_ring->dev,
2950 dma_unmap_addr(tx_buf, dma),
2951 dma_unmap_len(tx_buf, len),
2952 DMA_TO_DEVICE);
2953
2954 dma_unmap_len_set(tx_buf, len, 0);
2955
2956
2957 /* move to the next desc and buffer to clean */
2958 tx_buf++;
2959 tx_desc++;
2960 i++;
2961 if (unlikely(!i)) {
2962 i -= tx_ring->count;
2963 tx_buf = tx_ring->tx_bi;
2964 tx_desc = I40E_TX_DESC(tx_ring, 0);
2965 }
2966
2967 /* update budget accounting */
2968 budget--;
2969 } while (likely(budget));
2970
2971 i += tx_ring->count;
2972 tx_ring->next_to_clean = i;
2973
2974 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
2975 i40e_irq_dynamic_enable(vsi,
2976 tx_ring->q_vector->v_idx + vsi->base_vector);
2977 }
2978 return budget > 0;
2979}
2980
2981/**
2982 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
2983 * @irq: interrupt number
2984 * @data: pointer to a q_vector
2985 **/
2986static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
2987{
2988 struct i40e_q_vector *q_vector = data;
2989 struct i40e_vsi *vsi;
2990
2991 if (!q_vector->tx.ring)
2992 return IRQ_HANDLED;
2993
2994 vsi = q_vector->tx.ring->vsi;
2995 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
2996
2997 return IRQ_HANDLED;
2998}
2999
41c445ff 3000/**
cd0b6fa6 3001 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3002 * @vsi: the VSI being configured
3003 * @v_idx: vector index
cd0b6fa6 3004 * @qp_idx: queue pair index
41c445ff 3005 **/
cd0b6fa6 3006static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3007{
493fb300 3008 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3009 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3010 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3011
3012 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3013 tx_ring->next = q_vector->tx.ring;
3014 q_vector->tx.ring = tx_ring;
41c445ff 3015 q_vector->tx.count++;
cd0b6fa6
AD		 3016
3017 rx_ring->q_vector = q_vector;
3018 rx_ring->next = q_vector->rx.ring;
3019 q_vector->rx.ring = rx_ring;
3020 q_vector->rx.count++;
41c445ff
JB		 3021}
3022
3023/**
3024 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3025 * @vsi: the VSI being configured
3026 *
3027 * This function maps descriptor rings to the queue-specific vectors
3028 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3029 * one vector per queue pair, but on a constrained vector budget, we
3030 * group the queue pairs as "efficiently" as possible.
3031 **/
3032static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3033{
3034 int qp_remaining = vsi->num_queue_pairs;
3035 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3036 int num_ringpairs;
41c445ff
JB		 3037 int v_start = 0;
3038 int qp_idx = 0;
3039
3040 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3041 * group them so there are multiple queues per vector.
3042 */
3043 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3044 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3045
3046 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3047
3048 q_vector->num_ringpairs = num_ringpairs;
3049
3050 q_vector->rx.count = 0;
3051 q_vector->tx.count = 0;
3052 q_vector->rx.ring = NULL;
3053 q_vector->tx.ring = NULL;
3054
3055 while (num_ringpairs--) {
3056 map_vector_to_qp(vsi, v_start, qp_idx);
3057 qp_idx++;
3058 qp_remaining--;
41c445ff
JB		 3059 }
3060 }
3061}
3062
3063/**
3064 * i40e_vsi_request_irq - Request IRQ from the OS
3065 * @vsi: the VSI being configured
3066 * @basename: name for the vector
3067 **/
3068static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3069{
3070 struct i40e_pf *pf = vsi->back;
3071 int err;
3072
3073 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3074 err = i40e_vsi_request_irq_msix(vsi, basename);
3075 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3076 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3077 pf->misc_int_name, pf);
3078 else
3079 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3080 pf->misc_int_name, pf);
3081
3082 if (err)
3083 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3084
3085 return err;
3086}
3087
3088#ifdef CONFIG_NET_POLL_CONTROLLER
3089/**
3090 * i40e_netpoll - A Polling 'interrupt'handler
3091 * @netdev: network interface device structure
3092 *
3093 * This is used by netconsole to send skbs without having to re-enable
3094 * interrupts. It's not called while the normal interrupt routine is executing.
3095 **/
3096static void i40e_netpoll(struct net_device *netdev)
3097{
3098 struct i40e_netdev_priv *np = netdev_priv(netdev);
3099 struct i40e_vsi *vsi = np->vsi;
3100 struct i40e_pf *pf = vsi->back;
3101 int i;
3102
3103 /* if interface is down do nothing */
3104 if (test_bit(__I40E_DOWN, &vsi->state))
3105 return;
3106
3107 pf->flags |= I40E_FLAG_IN_NETPOLL;
3108 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3109 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3110 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3111 } else {
3112 i40e_intr(pf->pdev->irq, netdev);
3113 }
3114 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3115}
3116#endif
3117
3118/**
3119 * i40e_vsi_control_tx - Start or stop a VSI's rings
3120 * @vsi: the VSI being configured
3121 * @enable: start or stop the rings
3122 **/
3123static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3124{
3125 struct i40e_pf *pf = vsi->back;
3126 struct i40e_hw *hw = &pf->hw;
3127 int i, j, pf_q;
3128 u32 tx_reg;
3129
3130 pf_q = vsi->base_queue;
3131 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3132 for (j = 0; j < 50; j++) {
41c445ff 3133 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3134 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3135 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3136 break;
3137 usleep_range(1000, 2000);
3138 }
fda972f6
MW		 3139 /* Skip if the queue is already in the requested state */
3140 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3141 continue;
3142 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3143 continue;
41c445ff
JB		 3144
3145 /* turn on/off the queue */
c5c9eb9e
SN		 3146 if (enable) {
3147 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3148 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3149 } else {
41c445ff 3150 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3151 }
41c445ff
JB		 3152
3153 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3154
3155 /* wait for the change to finish */
3156 for (j = 0; j < 10; j++) {
3157 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3158 if (enable) {
3159 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3160 break;
3161 } else {
3162 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3163 break;
3164 }
3165
3166 udelay(10);
3167 }
3168 if (j >= 10) {
3169 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3170 pf_q, (enable ? "en" : "dis"));
3171 return -ETIMEDOUT;
3172 }
3173 }
3174
7134f9ce
JB		 3175 if (hw->revision_id == 0)
3176 mdelay(50);
3177
41c445ff
JB		 3178 return 0;
3179}
3180
3181/**
3182 * i40e_vsi_control_rx - Start or stop a VSI's rings
3183 * @vsi: the VSI being configured
3184 * @enable: start or stop the rings
3185 **/
3186static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3187{
3188 struct i40e_pf *pf = vsi->back;
3189 struct i40e_hw *hw = &pf->hw;
3190 int i, j, pf_q;
3191 u32 rx_reg;
3192
3193 pf_q = vsi->base_queue;
3194 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3195 for (j = 0; j < 50; j++) {
41c445ff 3196 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3197 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3198 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3199 break;
3200 usleep_range(1000, 2000);
3201 }
41c445ff
JB		 3202
3203 if (enable) {
3204 /* is STAT set ? */
3205 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3206 continue;
3207 } else {
3208 /* is !STAT set ? */
3209 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3210 continue;
3211 }
3212
3213 /* turn on/off the queue */
3214 if (enable)
6c5ef620 3215 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3216 else
6c5ef620 3217 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3218 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3219
3220 /* wait for the change to finish */
3221 for (j = 0; j < 10; j++) {
3222 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3223
3224 if (enable) {
3225 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3226 break;
3227 } else {
3228 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3229 break;
3230 }
3231
3232 udelay(10);
3233 }
3234 if (j >= 10) {
3235 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3236 pf_q, (enable ? "en" : "dis"));
3237 return -ETIMEDOUT;
3238 }
3239 }
3240
3241 return 0;
3242}
3243
3244/**
3245 * i40e_vsi_control_rings - Start or stop a VSI's rings
3246 * @vsi: the VSI being configured
3247 * @enable: start or stop the rings
3248 **/
fc18eaa0 3249int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3250{
3b867b28 3251 int ret = 0;
41c445ff
JB		 3252
3253 /* do rx first for enable and last for disable */
3254 if (request) {
3255 ret = i40e_vsi_control_rx(vsi, request);
3256 if (ret)
3257 return ret;
3258 ret = i40e_vsi_control_tx(vsi, request);
3259 } else {
3b867b28
ASJ		 3260 /* Ignore return value, we need to shutdown whatever we can */
3261 i40e_vsi_control_tx(vsi, request);
3262 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3263 }
3264
3265 return ret;
3266}
3267
3268/**
3269 * i40e_vsi_free_irq - Free the irq association with the OS
3270 * @vsi: the VSI being configured
3271 **/
3272static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3273{
3274 struct i40e_pf *pf = vsi->back;
3275 struct i40e_hw *hw = &pf->hw;
3276 int base = vsi->base_vector;
3277 u32 val, qp;
3278 int i;
3279
3280 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3281 if (!vsi->q_vectors)
3282 return;
3283
3284 for (i = 0; i < vsi->num_q_vectors; i++) {
3285 u16 vector = i + base;
3286
3287 /* free only the irqs that were actually requested */
78681b1f
SN		 3288 if (!vsi->q_vectors[i] ||
3289 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3290 continue;
3291
3292 /* clear the affinity_mask in the IRQ descriptor */
3293 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3294 NULL);
3295 free_irq(pf->msix_entries[vector].vector,
493fb300 3296 vsi->q_vectors[i]);
41c445ff
JB		 3297
3298 /* Tear down the interrupt queue link list
3299 *
3300 * We know that they come in pairs and always
3301 * the Rx first, then the Tx. To clear the
3302 * link list, stick the EOL value into the
3303 * next_q field of the registers.
3304 */
3305 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3306 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3307 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3308 val |= I40E_QUEUE_END_OF_LIST
3309 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3310 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3311
3312 while (qp != I40E_QUEUE_END_OF_LIST) {
3313 u32 next;
3314
3315 val = rd32(hw, I40E_QINT_RQCTL(qp));
3316
3317 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3318 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3319 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3320 I40E_QINT_RQCTL_INTEVENT_MASK);
3321
3322 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3323 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3324
3325 wr32(hw, I40E_QINT_RQCTL(qp), val);
3326
3327 val = rd32(hw, I40E_QINT_TQCTL(qp));
3328
3329 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3330 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3331
3332 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3333 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3334 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3335 I40E_QINT_TQCTL_INTEVENT_MASK);
3336
3337 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3338 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3339
3340 wr32(hw, I40E_QINT_TQCTL(qp), val);
3341 qp = next;
3342 }
3343 }
3344 } else {
3345 free_irq(pf->pdev->irq, pf);
3346
3347 val = rd32(hw, I40E_PFINT_LNKLST0);
3348 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3349 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3350 val |= I40E_QUEUE_END_OF_LIST
3351 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3352 wr32(hw, I40E_PFINT_LNKLST0, val);
3353
3354 val = rd32(hw, I40E_QINT_RQCTL(qp));
3355 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3356 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3357 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3358 I40E_QINT_RQCTL_INTEVENT_MASK);
3359
3360 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3361 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3362
3363 wr32(hw, I40E_QINT_RQCTL(qp), val);
3364
3365 val = rd32(hw, I40E_QINT_TQCTL(qp));
3366
3367 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3368 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3369 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3370 I40E_QINT_TQCTL_INTEVENT_MASK);
3371
3372 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3373 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3374
3375 wr32(hw, I40E_QINT_TQCTL(qp), val);
3376 }
3377}
3378
493fb300
AD		 3379/**
3380 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3381 * @vsi: the VSI being configured
3382 * @v_idx: Index of vector to be freed
3383 *
3384 * This function frees the memory allocated to the q_vector. In addition if
3385 * NAPI is enabled it will delete any references to the NAPI struct prior
3386 * to freeing the q_vector.
3387 **/
3388static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3389{
3390 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3391 struct i40e_ring *ring;
493fb300
AD		 3392
3393 if (!q_vector)
3394 return;
3395
3396 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3397 i40e_for_each_ring(ring, q_vector->tx)
3398 ring->q_vector = NULL;
3399
3400 i40e_for_each_ring(ring, q_vector->rx)
3401 ring->q_vector = NULL;
493fb300
AD		 3402
3403 /* only VSI w/ an associated netdev is set up w/ NAPI */
3404 if (vsi->netdev)
3405 netif_napi_del(&q_vector->napi);
3406
3407 vsi->q_vectors[v_idx] = NULL;
3408
3409 kfree_rcu(q_vector, rcu);
3410}
3411
41c445ff
JB		 3412/**
3413 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3414 * @vsi: the VSI being un-configured
3415 *
3416 * This frees the memory allocated to the q_vectors and
3417 * deletes references to the NAPI struct.
3418 **/
3419static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3420{
3421 int v_idx;
3422
493fb300
AD		 3423 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3424 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3425}
3426
3427/**
3428 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3429 * @pf: board private structure
3430 **/
3431static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3432{
3433 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3434 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3435 pci_disable_msix(pf->pdev);
3436 kfree(pf->msix_entries);
3437 pf->msix_entries = NULL;
3438 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3439 pci_disable_msi(pf->pdev);
3440 }
3441 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3442}
3443
3444/**
3445 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3446 * @pf: board private structure
3447 *
3448 * We go through and clear interrupt specific resources and reset the structure
3449 * to pre-load conditions
3450 **/
3451static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3452{
3453 int i;
3454
3455 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3456 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3457 if (pf->vsi[i])
3458 i40e_vsi_free_q_vectors(pf->vsi[i]);
3459 i40e_reset_interrupt_capability(pf);
3460}
3461
3462/**
3463 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3464 * @vsi: the VSI being configured
3465 **/
3466static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3467{
3468 int q_idx;
3469
3470 if (!vsi->netdev)
3471 return;
3472
3473 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3474 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3475}
3476
3477/**
3478 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3479 * @vsi: the VSI being configured
3480 **/
3481static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3482{
3483 int q_idx;
3484
3485 if (!vsi->netdev)
3486 return;
3487
3488 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3489 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3490}
3491
3492/**
3493 * i40e_quiesce_vsi - Pause a given VSI
3494 * @vsi: the VSI being paused
3495 **/
3496static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3497{
3498 if (test_bit(__I40E_DOWN, &vsi->state))
3499 return;
3500
3501 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3502 if (vsi->netdev && netif_running(vsi->netdev)) {
3503 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3504 } else {
3505 set_bit(__I40E_DOWN, &vsi->state);
3506 i40e_down(vsi);
3507 }
3508}
3509
3510/**
3511 * i40e_unquiesce_vsi - Resume a given VSI
3512 * @vsi: the VSI being resumed
3513 **/
3514static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3515{
3516 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3517 return;
3518
3519 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3520 if (vsi->netdev && netif_running(vsi->netdev))
3521 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3522 else
3523 i40e_up(vsi); /* this clears the DOWN bit */
3524}
3525
3526/**
3527 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3528 * @pf: the PF
3529 **/
3530static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3531{
3532 int v;
3533
3534 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3535 if (pf->vsi[v])
3536 i40e_quiesce_vsi(pf->vsi[v]);
3537 }
3538}
3539
3540/**
3541 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3542 * @pf: the PF
3543 **/
3544static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3545{
3546 int v;
3547
3548 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3549 if (pf->vsi[v])
3550 i40e_unquiesce_vsi(pf->vsi[v]);
3551 }
3552}
3553
3554/**
3555 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3556 * @dcbcfg: the corresponding DCBx configuration structure
3557 *
3558 * Return the number of TCs from given DCBx configuration
3559 **/
3560static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3561{
078b5876
JB		 3562 u8 num_tc = 0;
3563 int i;
41c445ff
JB		 3564
3565 /* Scan the ETS Config Priority Table to find
3566 * traffic class enabled for a given priority
3567 * and use the traffic class index to get the
3568 * number of traffic classes enabled
3569 */
3570 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3571 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3572 num_tc = dcbcfg->etscfg.prioritytable[i];
3573 }
3574
3575 /* Traffic class index starts from zero so
3576 * increment to return the actual count
3577 */
078b5876 3578 return num_tc + 1;
41c445ff
JB		 3579}
3580
3581/**
3582 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3583 * @dcbcfg: the corresponding DCBx configuration structure
3584 *
3585 * Query the current DCB configuration and return the number of
3586 * traffic classes enabled from the given DCBX config
3587 **/
3588static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3589{
3590 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3591 u8 enabled_tc = 1;
3592 u8 i;
3593
3594 for (i = 0; i < num_tc; i++)
3595 enabled_tc |= 1 << i;
3596
3597 return enabled_tc;
3598}
3599
3600/**
3601 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3602 * @pf: PF being queried
3603 *
3604 * Return number of traffic classes enabled for the given PF
3605 **/
3606static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3607{
3608 struct i40e_hw *hw = &pf->hw;
3609 u8 i, enabled_tc;
3610 u8 num_tc = 0;
3611 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3612
3613 /* If DCB is not enabled then always in single TC */
3614 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3615 return 1;
3616
3617 /* MFP mode return count of enabled TCs for this PF */
3618 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3619 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3620 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3621 if (enabled_tc & (1 << i))
3622 num_tc++;
3623 }
3624 return num_tc;
3625 }
3626
3627 /* SFP mode will be enabled for all TCs on port */
3628 return i40e_dcb_get_num_tc(dcbcfg);
3629}
3630
3631/**
3632 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3633 * @pf: PF being queried
3634 *
3635 * Return a bitmap for first enabled traffic class for this PF.
3636 **/
3637static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3638{
3639 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3640 u8 i = 0;
3641
3642 if (!enabled_tc)
3643 return 0x1; /* TC0 */
3644
3645 /* Find the first enabled TC */
3646 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3647 if (enabled_tc & (1 << i))
3648 break;
3649 }
3650
3651 return 1 << i;
3652}
3653
3654/**
3655 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3656 * @pf: PF being queried
3657 *
3658 * Return a bitmap for enabled traffic classes for this PF.
3659 **/
3660static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3661{
3662 /* If DCB is not enabled for this PF then just return default TC */
3663 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3664 return i40e_pf_get_default_tc(pf);
3665
3666 /* MFP mode will have enabled TCs set by FW */
3667 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3668 return pf->hw.func_caps.enabled_tcmap;
3669
3670 /* SFP mode we want PF to be enabled for all TCs */
3671 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3672}
3673
3674/**
3675 * i40e_vsi_get_bw_info - Query VSI BW Information
3676 * @vsi: the VSI being queried
3677 *
3678 * Returns 0 on success, negative value on failure
3679 **/
3680static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3681{
3682 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3683 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3684 struct i40e_pf *pf = vsi->back;
3685 struct i40e_hw *hw = &pf->hw;
dcae29be 3686 i40e_status aq_ret;
41c445ff 3687 u32 tc_bw_max;
41c445ff
JB		 3688 int i;
3689
3690 /* Get the VSI level BW configuration */
dcae29be
JB		 3691 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3692 if (aq_ret) {
41c445ff
JB		 3693 dev_info(&pf->pdev->dev,
3694 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3695 aq_ret, pf->hw.aq.asq_last_status);
3696 return -EINVAL;
41c445ff
JB		 3697 }
3698
3699 /* Get the VSI level BW configuration per TC */
dcae29be 3700 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3701 NULL);
dcae29be 3702 if (aq_ret) {
41c445ff
JB		 3703 dev_info(&pf->pdev->dev,
3704 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3705 aq_ret, pf->hw.aq.asq_last_status);
3706 return -EINVAL;
41c445ff
JB		 3707 }
3708
3709 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3710 dev_info(&pf->pdev->dev,
3711 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3712 bw_config.tc_valid_bits,
3713 bw_ets_config.tc_valid_bits);
3714 /* Still continuing */
3715 }
3716
3717 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3718 vsi->bw_max_quanta = bw_config.max_bw;
3719 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3720 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3721 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3722 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3723 vsi->bw_ets_limit_credits[i] =
3724 le16_to_cpu(bw_ets_config.credits[i]);
3725 /* 3 bits out of 4 for each TC */
3726 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3727 }
078b5876 3728
dcae29be 3729 return 0;
41c445ff
JB		 3730}
3731
3732/**
3733 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3734 * @vsi: the VSI being configured
3735 * @enabled_tc: TC bitmap
3736 * @bw_credits: BW shared credits per TC
3737 *
3738 * Returns 0 on success, negative value on failure
3739 **/
dcae29be 3740static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3741 u8 *bw_share)
3742{
3743 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3744 i40e_status aq_ret;
3745 int i;
41c445ff
JB		 3746
3747 bw_data.tc_valid_bits = enabled_tc;
3748 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3749 bw_data.tc_bw_credits[i] = bw_share[i];
3750
dcae29be
JB		 3751 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3752 NULL);
3753 if (aq_ret) {
41c445ff
JB		 3754 dev_info(&vsi->back->pdev->dev,
3755 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3756 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3757 return -EINVAL;
41c445ff
JB		 3758 }
3759
3760 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3761 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3762
dcae29be 3763 return 0;
41c445ff
JB		 3764}
3765
3766/**
3767 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3768 * @vsi: the VSI being configured
3769 * @enabled_tc: TC map to be enabled
3770 *
3771 **/
3772static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3773{
3774 struct net_device *netdev = vsi->netdev;
3775 struct i40e_pf *pf = vsi->back;
3776 struct i40e_hw *hw = &pf->hw;
3777 u8 netdev_tc = 0;
3778 int i;
3779 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3780
3781 if (!netdev)
3782 return;
3783
3784 if (!enabled_tc) {
3785 netdev_reset_tc(netdev);
3786 return;
3787 }
3788
3789 /* Set up actual enabled TCs on the VSI */
3790 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3791 return;
3792
3793 /* set per TC queues for the VSI */
3794 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3795 /* Only set TC queues for enabled tcs
3796 *
3797 * e.g. For a VSI that has TC0 and TC3 enabled the
3798 * enabled_tc bitmap would be 0x00001001; the driver
3799 * will set the numtc for netdev as 2 that will be
3800 * referenced by the netdev layer as TC 0 and 1.
3801 */
3802 if (vsi->tc_config.enabled_tc & (1 << i))
3803 netdev_set_tc_queue(netdev,
3804 vsi->tc_config.tc_info[i].netdev_tc,
3805 vsi->tc_config.tc_info[i].qcount,
3806 vsi->tc_config.tc_info[i].qoffset);
3807 }
3808
3809 /* Assign UP2TC map for the VSI */
3810 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3811 /* Get the actual TC# for the UP */
3812 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3813 /* Get the mapped netdev TC# for the UP */
3814 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3815 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3816 }
3817}
3818
3819/**
3820 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3821 * @vsi: the VSI being configured
3822 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3823 **/
3824static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3825 struct i40e_vsi_context *ctxt)
3826{
3827 /* copy just the sections touched not the entire info
3828 * since not all sections are valid as returned by
3829 * update vsi params
3830 */
3831 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3832 memcpy(&vsi->info.queue_mapping,
3833 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3834 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3835 sizeof(vsi->info.tc_mapping));
3836}
3837
3838/**
3839 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3840 * @vsi: VSI to be configured
3841 * @enabled_tc: TC bitmap
3842 *
3843 * This configures a particular VSI for TCs that are mapped to the
3844 * given TC bitmap. It uses default bandwidth share for TCs across
3845 * VSIs to configure TC for a particular VSI.
3846 *
3847 * NOTE:
3848 * It is expected that the VSI queues have been quisced before calling
3849 * this function.
3850 **/
3851static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3852{
3853 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3854 struct i40e_vsi_context ctxt;
3855 int ret = 0;
3856 int i;
3857
3858 /* Check if enabled_tc is same as existing or new TCs */
3859 if (vsi->tc_config.enabled_tc == enabled_tc)
3860 return ret;
3861
3862 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3863 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3864 if (enabled_tc & (1 << i))
3865 bw_share[i] = 1;
3866 }
3867
3868 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3869 if (ret) {
3870 dev_info(&vsi->back->pdev->dev,
3871 "Failed configuring TC map %d for VSI %d\n",
3872 enabled_tc, vsi->seid);
3873 goto out;
3874 }
3875
3876 /* Update Queue Pairs Mapping for currently enabled UPs */
3877 ctxt.seid = vsi->seid;
3878 ctxt.pf_num = vsi->back->hw.pf_id;
3879 ctxt.vf_num = 0;
3880 ctxt.uplink_seid = vsi->uplink_seid;
3881 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3882 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3883
3884 /* Update the VSI after updating the VSI queue-mapping information */
3885 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3886 if (ret) {
3887 dev_info(&vsi->back->pdev->dev,
3888 "update vsi failed, aq_err=%d\n",
3889 vsi->back->hw.aq.asq_last_status);
3890 goto out;
3891 }
3892 /* update the local VSI info with updated queue map */
3893 i40e_vsi_update_queue_map(vsi, &ctxt);
3894 vsi->info.valid_sections = 0;
3895
3896 /* Update current VSI BW information */
3897 ret = i40e_vsi_get_bw_info(vsi);
3898 if (ret) {
3899 dev_info(&vsi->back->pdev->dev,
3900 "Failed updating vsi bw info, aq_err=%d\n",
3901 vsi->back->hw.aq.asq_last_status);
3902 goto out;
3903 }
3904
3905 /* Update the netdev TC setup */
3906 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3907out:
3908 return ret;
3909}
3910
4e3b35b0
NP		 3911/**
3912 * i40e_veb_config_tc - Configure TCs for given VEB
3913 * @veb: given VEB
3914 * @enabled_tc: TC bitmap
3915 *
3916 * Configures given TC bitmap for VEB (switching) element
3917 **/
3918int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3919{
3920 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3921 struct i40e_pf *pf = veb->pf;
3922 int ret = 0;
3923 int i;
3924
3925 /* No TCs or already enabled TCs just return */
3926 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3927 return ret;
3928
3929 bw_data.tc_valid_bits = enabled_tc;
3930 /* bw_data.absolute_credits is not set (relative) */
3931
3932 /* Enable ETS TCs with equal BW Share for now */
3933 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3934 if (enabled_tc & (1 << i))
3935 bw_data.tc_bw_share_credits[i] = 1;
3936 }
3937
3938 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3939 &bw_data, NULL);
3940 if (ret) {
3941 dev_info(&pf->pdev->dev,
3942 "veb bw config failed, aq_err=%d\n",
3943 pf->hw.aq.asq_last_status);
3944 goto out;
3945 }
3946
3947 /* Update the BW information */
3948 ret = i40e_veb_get_bw_info(veb);
3949 if (ret) {
3950 dev_info(&pf->pdev->dev,
3951 "Failed getting veb bw config, aq_err=%d\n",
3952 pf->hw.aq.asq_last_status);
3953 }
3954
3955out:
3956 return ret;
3957}
3958
3959#ifdef CONFIG_I40E_DCB
3960/**
3961 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3962 * @pf: PF struct
3963 *
3964 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3965 * the caller would've quiesce all the VSIs before calling
3966 * this function
3967 **/
3968static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3969{
3970 u8 tc_map = 0;
3971 int ret;
3972 u8 v;
3973
3974 /* Enable the TCs available on PF to all VEBs */
3975 tc_map = i40e_pf_get_tc_map(pf);
3976 for (v = 0; v < I40E_MAX_VEB; v++) {
3977 if (!pf->veb[v])
3978 continue;
3979 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
3980 if (ret) {
3981 dev_info(&pf->pdev->dev,
3982 "Failed configuring TC for VEB seid=%d\n",
3983 pf->veb[v]->seid);
3984 /* Will try to configure as many components */
3985 }
3986 }
3987
3988 /* Update each VSI */
3989 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3990 if (!pf->vsi[v])
3991 continue;
3992
3993 /* - Enable all TCs for the LAN VSI
3994 * - For all others keep them at TC0 for now
3995 */
3996 if (v == pf->lan_vsi)
3997 tc_map = i40e_pf_get_tc_map(pf);
3998 else
3999 tc_map = i40e_pf_get_default_tc(pf);
4000
4001 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4002 if (ret) {
4003 dev_info(&pf->pdev->dev,
4004 "Failed configuring TC for VSI seid=%d\n",
4005 pf->vsi[v]->seid);
4006 /* Will try to configure as many components */
4007 } else {
4008 if (pf->vsi[v]->netdev)
4009 i40e_dcbnl_set_all(pf->vsi[v]);
4010 }
4011 }
4012}
4013
4014/**
4015 * i40e_init_pf_dcb - Initialize DCB configuration
4016 * @pf: PF being configured
4017 *
4018 * Query the current DCB configuration and cache it
4019 * in the hardware structure
4020 **/
4021static int i40e_init_pf_dcb(struct i40e_pf *pf)
4022{
4023 struct i40e_hw *hw = &pf->hw;
4024 int err = 0;
4025
4026 if (pf->hw.func_caps.npar_enable)
4027 goto out;
4028
4029 /* Get the initial DCB configuration */
4030 err = i40e_init_dcb(hw);
4031 if (!err) {
4032 /* Device/Function is not DCBX capable */
4033 if ((!hw->func_caps.dcb) ||
4034 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4035 dev_info(&pf->pdev->dev,
4036 "DCBX offload is not supported or is disabled for this PF.\n");
4037
4038 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4039 goto out;
4040
4041 } else {
4042 /* When status is not DISABLED then DCBX in FW */
4043 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4044 DCB_CAP_DCBX_VER_IEEE;
4045 pf->flags |= I40E_FLAG_DCB_ENABLED;
4046 }
4047 }
4048
4049out:
4050 return err;
4051}
4052#endif /* CONFIG_I40E_DCB */
4053
41c445ff
JB		 4054/**
4055 * i40e_up_complete - Finish the last steps of bringing up a connection
4056 * @vsi: the VSI being configured
4057 **/
4058static int i40e_up_complete(struct i40e_vsi *vsi)
4059{
4060 struct i40e_pf *pf = vsi->back;
4061 int err;
4062
4063 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4064 i40e_vsi_configure_msix(vsi);
4065 else
4066 i40e_configure_msi_and_legacy(vsi);
4067
4068 /* start rings */
4069 err = i40e_vsi_control_rings(vsi, true);
4070 if (err)
4071 return err;
4072
4073 clear_bit(__I40E_DOWN, &vsi->state);
4074 i40e_napi_enable_all(vsi);
4075 i40e_vsi_enable_irq(vsi);
4076
4077 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4078 (vsi->netdev)) {
6d779b41 4079 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4080 netif_tx_start_all_queues(vsi->netdev);
4081 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4082 } else if (vsi->netdev) {
4083 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 4084 }
4085 i40e_service_event_schedule(pf);
4086
4087 return 0;
4088}
4089
4090/**
4091 * i40e_vsi_reinit_locked - Reset the VSI
4092 * @vsi: the VSI being configured
4093 *
4094 * Rebuild the ring structs after some configuration
4095 * has changed, e.g. MTU size.
4096 **/
4097static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4098{
4099 struct i40e_pf *pf = vsi->back;
4100
4101 WARN_ON(in_interrupt());
4102 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4103 usleep_range(1000, 2000);
4104 i40e_down(vsi);
4105
4106 /* Give a VF some time to respond to the reset. The
4107 * two second wait is based upon the watchdog cycle in
4108 * the VF driver.
4109 */
4110 if (vsi->type == I40E_VSI_SRIOV)
4111 msleep(2000);
4112 i40e_up(vsi);
4113 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4114}
4115
4116/**
4117 * i40e_up - Bring the connection back up after being down
4118 * @vsi: the VSI being configured
4119 **/
4120int i40e_up(struct i40e_vsi *vsi)
4121{
4122 int err;
4123
4124 err = i40e_vsi_configure(vsi);
4125 if (!err)
4126 err = i40e_up_complete(vsi);
4127
4128 return err;
4129}
4130
4131/**
4132 * i40e_down - Shutdown the connection processing
4133 * @vsi: the VSI being stopped
4134 **/
4135void i40e_down(struct i40e_vsi *vsi)
4136{
4137 int i;
4138
4139 /* It is assumed that the caller of this function
4140 * sets the vsi->state __I40E_DOWN bit.
4141 */
4142 if (vsi->netdev) {
4143 netif_carrier_off(vsi->netdev);
4144 netif_tx_disable(vsi->netdev);
4145 }
4146 i40e_vsi_disable_irq(vsi);
4147 i40e_vsi_control_rings(vsi, false);
4148 i40e_napi_disable_all(vsi);
4149
4150 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4151 i40e_clean_tx_ring(vsi->tx_rings[i]);
4152 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4153 }
4154}
4155
4156/**
4157 * i40e_setup_tc - configure multiple traffic classes
4158 * @netdev: net device to configure
4159 * @tc: number of traffic classes to enable
4160 **/
4161static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4162{
4163 struct i40e_netdev_priv *np = netdev_priv(netdev);
4164 struct i40e_vsi *vsi = np->vsi;
4165 struct i40e_pf *pf = vsi->back;
4166 u8 enabled_tc = 0;
4167 int ret = -EINVAL;
4168 int i;
4169
4170 /* Check if DCB enabled to continue */
4171 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4172 netdev_info(netdev, "DCB is not enabled for adapter\n");
4173 goto exit;
4174 }
4175
4176 /* Check if MFP enabled */
4177 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4178 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4179 goto exit;
4180 }
4181
4182 /* Check whether tc count is within enabled limit */
4183 if (tc > i40e_pf_get_num_tc(pf)) {
4184 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4185 goto exit;
4186 }
4187
4188 /* Generate TC map for number of tc requested */
4189 for (i = 0; i < tc; i++)
4190 enabled_tc |= (1 << i);
4191
4192 /* Requesting same TC configuration as already enabled */
4193 if (enabled_tc == vsi->tc_config.enabled_tc)
4194 return 0;
4195
4196 /* Quiesce VSI queues */
4197 i40e_quiesce_vsi(vsi);
4198
4199 /* Configure VSI for enabled TCs */
4200 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4201 if (ret) {
4202 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4203 vsi->seid);
4204 goto exit;
4205 }
4206
4207 /* Unquiesce VSI */
4208 i40e_unquiesce_vsi(vsi);
4209
4210exit:
4211 return ret;
4212}
4213
4214/**
4215 * i40e_open - Called when a network interface is made active
4216 * @netdev: network interface device structure
4217 *
4218 * The open entry point is called when a network interface is made
4219 * active by the system (IFF_UP). At this point all resources needed
4220 * for transmit and receive operations are allocated, the interrupt
4221 * handler is registered with the OS, the netdev watchdog subtask is
4222 * enabled, and the stack is notified that the interface is ready.
4223 *
4224 * Returns 0 on success, negative value on failure
4225 **/
4226static int i40e_open(struct net_device *netdev)
4227{
4228 struct i40e_netdev_priv *np = netdev_priv(netdev);
4229 struct i40e_vsi *vsi = np->vsi;
4230 struct i40e_pf *pf = vsi->back;
4231 char int_name[IFNAMSIZ];
4232 int err;
4233
4234 /* disallow open during test */
4235 if (test_bit(__I40E_TESTING, &pf->state))
4236 return -EBUSY;
4237
4238 netif_carrier_off(netdev);
4239
4240 /* allocate descriptors */
4241 err = i40e_vsi_setup_tx_resources(vsi);
4242 if (err)
4243 goto err_setup_tx;
4244 err = i40e_vsi_setup_rx_resources(vsi);
4245 if (err)
4246 goto err_setup_rx;
4247
4248 err = i40e_vsi_configure(vsi);
4249 if (err)
4250 goto err_setup_rx;
4251
4252 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4253 dev_driver_string(&pf->pdev->dev), netdev->name);
4254 err = i40e_vsi_request_irq(vsi, int_name);
4255 if (err)
4256 goto err_setup_rx;
4257
25946ddb 4258 /* Notify the stack of the actual queue counts. */
d7397644 4259 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4260 if (err)
4261 goto err_set_queues;
4262
d7397644 4263 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4264 if (err)
4265 goto err_set_queues;
4266
41c445ff
JB		 4267 err = i40e_up_complete(vsi);
4268 if (err)
4269 goto err_up_complete;
4270
a1c9a9d9
JK		 4271#ifdef CONFIG_I40E_VXLAN
4272 vxlan_get_rx_port(netdev);
4273#endif
41c445ff
JB		 4274
4275 return 0;
4276
4277err_up_complete:
4278 i40e_down(vsi);
25946ddb 4279err_set_queues:
41c445ff
JB		 4280 i40e_vsi_free_irq(vsi);
4281err_setup_rx:
4282 i40e_vsi_free_rx_resources(vsi);
4283err_setup_tx:
4284 i40e_vsi_free_tx_resources(vsi);
4285 if (vsi == pf->vsi[pf->lan_vsi])
4286 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4287
4288 return err;
4289}
4290
17a73f6b
JG		 4291/**
4292 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4293 * @pf: Pointer to pf
4294 *
4295 * This function destroys the hlist where all the Flow Director
4296 * filters were saved.
4297 **/
4298static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4299{
4300 struct i40e_fdir_filter *filter;
4301 struct hlist_node *node2;
4302
4303 hlist_for_each_entry_safe(filter, node2,
4304 &pf->fdir_filter_list, fdir_node) {
4305 hlist_del(&filter->fdir_node);
4306 kfree(filter);
4307 }
4308 pf->fdir_pf_active_filters = 0;
4309}
4310
41c445ff
JB		 4311/**
4312 * i40e_close - Disables a network interface
4313 * @netdev: network interface device structure
4314 *
4315 * The close entry point is called when an interface is de-activated
4316 * by the OS. The hardware is still under the driver's control, but
4317 * this netdev interface is disabled.
4318 *
4319 * Returns 0, this is not allowed to fail
4320 **/
4321static int i40e_close(struct net_device *netdev)
4322{
4323 struct i40e_netdev_priv *np = netdev_priv(netdev);
4324 struct i40e_vsi *vsi = np->vsi;
4325
4326 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4327 return 0;
4328
4329 i40e_down(vsi);
4330 i40e_vsi_free_irq(vsi);
4331
4332 i40e_vsi_free_tx_resources(vsi);
4333 i40e_vsi_free_rx_resources(vsi);
4334
4335 return 0;
4336}
4337
4338/**
4339 * i40e_do_reset - Start a PF or Core Reset sequence
4340 * @pf: board private structure
4341 * @reset_flags: which reset is requested
4342 *
4343 * The essential difference in resets is that the PF Reset
4344 * doesn't clear the packet buffers, doesn't reset the PE
4345 * firmware, and doesn't bother the other PFs on the chip.
4346 **/
4347void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4348{
4349 u32 val;
4350
4351 WARN_ON(in_interrupt());
4352
4353 /* do the biggest reset indicated */
4354 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4355
4356 /* Request a Global Reset
4357 *
4358 * This will start the chip's countdown to the actual full
4359 * chip reset event, and a warning interrupt to be sent
4360 * to all PFs, including the requestor. Our handler
4361 * for the warning interrupt will deal with the shutdown
4362 * and recovery of the switch setup.
4363 */
4364 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4365 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4366 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4367 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4368
4369 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4370
4371 /* Request a Core Reset
4372 *
4373 * Same as Global Reset, except does *not* include the MAC/PHY
4374 */
4375 dev_info(&pf->pdev->dev, "CoreR requested\n");
4376 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4377 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4378 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4379 i40e_flush(&pf->hw);
4380
7823fe34
SN		 4381 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4382
4383 /* Request a Firmware Reset
4384 *
4385 * Same as Global reset, plus restarting the
4386 * embedded firmware engine.
4387 */
4388 /* enable EMP Reset */
4389 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4390 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4391 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4392
4393 /* force the reset */
4394 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4395 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4396 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4397 i40e_flush(&pf->hw);
4398
41c445ff
JB		 4399 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4400
4401 /* Request a PF Reset
4402 *
4403 * Resets only the PF-specific registers
4404 *
4405 * This goes directly to the tear-down and rebuild of
4406 * the switch, since we need to do all the recovery as
4407 * for the Core Reset.
4408 */
4409 dev_info(&pf->pdev->dev, "PFR requested\n");
4410 i40e_handle_reset_warning(pf);
4411
4412 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4413 int v;
4414
4415 /* Find the VSI(s) that requested a re-init */
4416 dev_info(&pf->pdev->dev,
4417 "VSI reinit requested\n");
4418 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4419 struct i40e_vsi *vsi = pf->vsi[v];
4420 if (vsi != NULL &&
4421 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4422 i40e_vsi_reinit_locked(pf->vsi[v]);
4423 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4424 }
4425 }
4426
4427 /* no further action needed, so return now */
4428 return;
4429 } else {
4430 dev_info(&pf->pdev->dev,
4431 "bad reset request 0x%08x\n", reset_flags);
4432 return;
4433 }
4434}
4435
4e3b35b0
NP		 4436#ifdef CONFIG_I40E_DCB
4437/**
4438 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4439 * @pf: board private structure
4440 * @old_cfg: current DCB config
4441 * @new_cfg: new DCB config
4442 **/
4443bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4444 struct i40e_dcbx_config *old_cfg,
4445 struct i40e_dcbx_config *new_cfg)
4446{
4447 bool need_reconfig = false;
4448
4449 /* Check if ETS configuration has changed */
4450 if (memcmp(&new_cfg->etscfg,
4451 &old_cfg->etscfg,
4452 sizeof(new_cfg->etscfg))) {
4453 /* If Priority Table has changed reconfig is needed */
4454 if (memcmp(&new_cfg->etscfg.prioritytable,
4455 &old_cfg->etscfg.prioritytable,
4456 sizeof(new_cfg->etscfg.prioritytable))) {
4457 need_reconfig = true;
4458 dev_info(&pf->pdev->dev, "ETS UP2TC changed.\n");
4459 }
4460
4461 if (memcmp(&new_cfg->etscfg.tcbwtable,
4462 &old_cfg->etscfg.tcbwtable,
4463 sizeof(new_cfg->etscfg.tcbwtable)))
4464 dev_info(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4465
4466 if (memcmp(&new_cfg->etscfg.tsatable,
4467 &old_cfg->etscfg.tsatable,
4468 sizeof(new_cfg->etscfg.tsatable)))
4469 dev_info(&pf->pdev->dev, "ETS TSA Table changed.\n");
4470 }
4471
4472 /* Check if PFC configuration has changed */
4473 if (memcmp(&new_cfg->pfc,
4474 &old_cfg->pfc,
4475 sizeof(new_cfg->pfc))) {
4476 need_reconfig = true;
4477 dev_info(&pf->pdev->dev, "PFC config change detected.\n");
4478 }
4479
4480 /* Check if APP Table has changed */
4481 if (memcmp(&new_cfg->app,
4482 &old_cfg->app,
3d9667a9 4483 sizeof(new_cfg->app))) {
4e3b35b0
NP		 4484 need_reconfig = true;
4485 dev_info(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4486 }
4e3b35b0
NP		 4487
4488 return need_reconfig;
4489}
4490
4491/**
4492 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4493 * @pf: board private structure
4494 * @e: event info posted on ARQ
4495 **/
4496static int i40e_handle_lldp_event(struct i40e_pf *pf,
4497 struct i40e_arq_event_info *e)
4498{
4499 struct i40e_aqc_lldp_get_mib *mib =
4500 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4501 struct i40e_hw *hw = &pf->hw;
4502 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4503 struct i40e_dcbx_config tmp_dcbx_cfg;
4504 bool need_reconfig = false;
4505 int ret = 0;
4506 u8 type;
4507
4508 /* Ignore if event is not for Nearest Bridge */
4509 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4510 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4511 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4512 return ret;
4513
4514 /* Check MIB Type and return if event for Remote MIB update */
4515 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4516 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4517 /* Update the remote cached instance and return */
4518 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4519 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4520 &hw->remote_dcbx_config);
4521 goto exit;
4522 }
4523
4524 /* Convert/store the DCBX data from LLDPDU temporarily */
4525 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4526 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4527 if (ret) {
4528 /* Error in LLDPDU parsing return */
4529 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4530 goto exit;
4531 }
4532
4533 /* No change detected in DCBX configs */
4534 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
4535 dev_info(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4536 goto exit;
4537 }
4538
4539 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4540
4541 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4542
4543 /* Overwrite the new configuration */
4544 *dcbx_cfg = tmp_dcbx_cfg;
4545
4546 if (!need_reconfig)
4547 goto exit;
4548
4549 /* Reconfiguration needed quiesce all VSIs */
4550 i40e_pf_quiesce_all_vsi(pf);
4551
4552 /* Changes in configuration update VEB/VSI */
4553 i40e_dcb_reconfigure(pf);
4554
4555 i40e_pf_unquiesce_all_vsi(pf);
4556exit:
4557 return ret;
4558}
4559#endif /* CONFIG_I40E_DCB */
4560
23326186
ASJ		 4561/**
4562 * i40e_do_reset_safe - Protected reset path for userland calls.
4563 * @pf: board private structure
4564 * @reset_flags: which reset is requested
4565 *
4566 **/
4567void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4568{
4569 rtnl_lock();
4570 i40e_do_reset(pf, reset_flags);
4571 rtnl_unlock();
4572}
4573
41c445ff
JB		 4574/**
4575 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4576 * @pf: board private structure
4577 * @e: event info posted on ARQ
4578 *
4579 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4580 * and VF queues
4581 **/
4582static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4583 struct i40e_arq_event_info *e)
4584{
4585 struct i40e_aqc_lan_overflow *data =
4586 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4587 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4588 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4589 struct i40e_hw *hw = &pf->hw;
4590 struct i40e_vf *vf;
4591 u16 vf_id;
4592
4593 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4594 __func__, queue, qtx_ctl);
4595
4596 /* Queue belongs to VF, find the VF and issue VF reset */
4597 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4598 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4599 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4600 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4601 vf_id -= hw->func_caps.vf_base_id;
4602 vf = &pf->vf[vf_id];
4603 i40e_vc_notify_vf_reset(vf);
4604 /* Allow VF to process pending reset notification */
4605 msleep(20);
4606 i40e_reset_vf(vf, false);
4607 }
4608}
4609
4610/**
4611 * i40e_service_event_complete - Finish up the service event
4612 * @pf: board private structure
4613 **/
4614static void i40e_service_event_complete(struct i40e_pf *pf)
4615{
4616 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4617
4618 /* flush memory to make sure state is correct before next watchog */
4619 smp_mb__before_clear_bit();
4620 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4621}
4622
4623/**
4624 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4625 * @pf: board private structure
4626 **/
4627static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4628{
4629 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4630 return;
4631
4632 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4633
4634 /* if interface is down do nothing */
4635 if (test_bit(__I40E_DOWN, &pf->state))
4636 return;
4637}
4638
4639/**
4640 * i40e_vsi_link_event - notify VSI of a link event
4641 * @vsi: vsi to be notified
4642 * @link_up: link up or down
4643 **/
4644static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4645{
4646 if (!vsi)
4647 return;
4648
4649 switch (vsi->type) {
4650 case I40E_VSI_MAIN:
4651 if (!vsi->netdev || !vsi->netdev_registered)
4652 break;
4653
4654 if (link_up) {
4655 netif_carrier_on(vsi->netdev);
4656 netif_tx_wake_all_queues(vsi->netdev);
4657 } else {
4658 netif_carrier_off(vsi->netdev);
4659 netif_tx_stop_all_queues(vsi->netdev);
4660 }
4661 break;
4662
4663 case I40E_VSI_SRIOV:
4664 break;
4665
4666 case I40E_VSI_VMDQ2:
4667 case I40E_VSI_CTRL:
4668 case I40E_VSI_MIRROR:
4669 default:
4670 /* there is no notification for other VSIs */
4671 break;
4672 }
4673}
4674
4675/**
4676 * i40e_veb_link_event - notify elements on the veb of a link event
4677 * @veb: veb to be notified
4678 * @link_up: link up or down
4679 **/
4680static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4681{
4682 struct i40e_pf *pf;
4683 int i;
4684
4685 if (!veb || !veb->pf)
4686 return;
4687 pf = veb->pf;
4688
4689 /* depth first... */
4690 for (i = 0; i < I40E_MAX_VEB; i++)
4691 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4692 i40e_veb_link_event(pf->veb[i], link_up);
4693
4694 /* ... now the local VSIs */
4695 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4696 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4697 i40e_vsi_link_event(pf->vsi[i], link_up);
4698}
4699
4700/**
4701 * i40e_link_event - Update netif_carrier status
4702 * @pf: board private structure
4703 **/
4704static void i40e_link_event(struct i40e_pf *pf)
4705{
4706 bool new_link, old_link;
4707
4708 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4709 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4710
4711 if (new_link == old_link)
4712 return;
4713
6d779b41
AS		 4714 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4715 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4716 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4717
4718 /* Notify the base of the switch tree connected to
4719 * the link. Floating VEBs are not notified.
4720 */
4721 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4722 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4723 else
4724 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4725
4726 if (pf->vf)
4727 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4728
4729 if (pf->flags & I40E_FLAG_PTP)
4730 i40e_ptp_set_increment(pf);
41c445ff
JB		 4731}
4732
4733/**
4734 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4735 * @pf: board private structure
4736 *
4737 * Set the per-queue flags to request a check for stuck queues in the irq
4738 * clean functions, then force interrupts to be sure the irq clean is called.
4739 **/
4740static void i40e_check_hang_subtask(struct i40e_pf *pf)
4741{
4742 int i, v;
4743
4744 /* If we're down or resetting, just bail */
4745 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4746 return;
4747
4748 /* for each VSI/netdev
4749 * for each Tx queue
4750 * set the check flag
4751 * for each q_vector
4752 * force an interrupt
4753 */
4754 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4755 struct i40e_vsi *vsi = pf->vsi[v];
4756 int armed = 0;
4757
4758 if (!pf->vsi[v] ||
4759 test_bit(__I40E_DOWN, &vsi->state) ||
4760 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4761 continue;
4762
4763 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4764 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4765 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4766 &vsi->tx_rings[i]->state))
41c445ff
JB		 4767 armed++;
4768 }
4769
4770 if (armed) {
4771 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4772 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4773 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4774 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4775 } else {
4776 u16 vec = vsi->base_vector - 1;
4777 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4778 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4779 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4780 wr32(&vsi->back->hw,
4781 I40E_PFINT_DYN_CTLN(vec), val);
4782 }
4783 i40e_flush(&vsi->back->hw);
4784 }
4785 }
4786}
4787
4788/**
4789 * i40e_watchdog_subtask - Check and bring link up
4790 * @pf: board private structure
4791 **/
4792static void i40e_watchdog_subtask(struct i40e_pf *pf)
4793{
4794 int i;
4795
4796 /* if interface is down do nothing */
4797 if (test_bit(__I40E_DOWN, &pf->state) ||
4798 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4799 return;
4800
4801 /* Update the stats for active netdevs so the network stack
4802 * can look at updated numbers whenever it cares to
4803 */
4804 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4805 if (pf->vsi[i] && pf->vsi[i]->netdev)
4806 i40e_update_stats(pf->vsi[i]);
4807
4808 /* Update the stats for the active switching components */
4809 for (i = 0; i < I40E_MAX_VEB; i++)
4810 if (pf->veb[i])
4811 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4812
4813 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4814}
4815
4816/**
4817 * i40e_reset_subtask - Set up for resetting the device and driver
4818 * @pf: board private structure
4819 **/
4820static void i40e_reset_subtask(struct i40e_pf *pf)
4821{
4822 u32 reset_flags = 0;
4823
23326186 4824 rtnl_lock();
41c445ff
JB		 4825 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4826 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4827 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4828 }
4829 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4830 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4831 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4832 }
4833 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4834 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4835 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4836 }
4837 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4838 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4839 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4840 }
4841
4842 /* If there's a recovery already waiting, it takes
4843 * precedence before starting a new reset sequence.
4844 */
4845 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4846 i40e_handle_reset_warning(pf);
23326186 4847 goto unlock;
41c445ff
JB		 4848 }
4849
4850 /* If we're already down or resetting, just bail */
4851 if (reset_flags &&
4852 !test_bit(__I40E_DOWN, &pf->state) &&
4853 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4854 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4855
4856unlock:
4857 rtnl_unlock();
41c445ff
JB		 4858}
4859
4860/**
4861 * i40e_handle_link_event - Handle link event
4862 * @pf: board private structure
4863 * @e: event info posted on ARQ
4864 **/
4865static void i40e_handle_link_event(struct i40e_pf *pf,
4866 struct i40e_arq_event_info *e)
4867{
4868 struct i40e_hw *hw = &pf->hw;
4869 struct i40e_aqc_get_link_status *status =
4870 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4871 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4872
4873 /* save off old link status information */
4874 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4875 sizeof(pf->hw.phy.link_info_old));
4876
4877 /* update link status */
4878 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4879 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4880 hw_link_info->link_info = status->link_info;
4881 hw_link_info->an_info = status->an_info;
4882 hw_link_info->ext_info = status->ext_info;
4883 hw_link_info->lse_enable =
4884 le16_to_cpu(status->command_flags) &
4885 I40E_AQ_LSE_ENABLE;
4886
4887 /* process the event */
4888 i40e_link_event(pf);
4889
4890 /* Do a new status request to re-enable LSE reporting
4891 * and load new status information into the hw struct,
4892 * then see if the status changed while processing the
4893 * initial event.
4894 */
4895 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4896 i40e_link_event(pf);
4897}
4898
4899/**
4900 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4901 * @pf: board private structure
4902 **/
4903static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4904{
4905 struct i40e_arq_event_info event;
4906 struct i40e_hw *hw = &pf->hw;
4907 u16 pending, i = 0;
4908 i40e_status ret;
4909 u16 opcode;
4910 u32 val;
4911
4912 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4913 return;
4914
3197ce22 4915 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4916 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4917 if (!event.msg_buf)
4918 return;
4919
4920 do {
2f019123 4921 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4922 ret = i40e_clean_arq_element(hw, &event, &pending);
4923 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4924 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4925 break;
4926 } else if (ret) {
4927 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4928 break;
4929 }
4930
4931 opcode = le16_to_cpu(event.desc.opcode);
4932 switch (opcode) {
4933
4934 case i40e_aqc_opc_get_link_status:
4935 i40e_handle_link_event(pf, &event);
4936 break;
4937 case i40e_aqc_opc_send_msg_to_pf:
4938 ret = i40e_vc_process_vf_msg(pf,
4939 le16_to_cpu(event.desc.retval),
4940 le32_to_cpu(event.desc.cookie_high),
4941 le32_to_cpu(event.desc.cookie_low),
4942 event.msg_buf,
4943 event.msg_size);
4944 break;
4945 case i40e_aqc_opc_lldp_update_mib:
4946 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 4947#ifdef CONFIG_I40E_DCB
4948 rtnl_lock();
4949 ret = i40e_handle_lldp_event(pf, &event);
4950 rtnl_unlock();
4951#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 4952 break;
4953 case i40e_aqc_opc_event_lan_overflow:
4954 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4955 i40e_handle_lan_overflow_event(pf, &event);
4956 break;
0467bc91
SN		 4957 case i40e_aqc_opc_send_msg_to_peer:
4958 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
4959 break;
41c445ff
JB		 4960 default:
4961 dev_info(&pf->pdev->dev,
0467bc91
SN		 4962 "ARQ Error: Unknown event 0x%04x received\n",
4963 opcode);
41c445ff
JB		 4964 break;
4965 }
4966 } while (pending && (i++ < pf->adminq_work_limit));
4967
4968 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4969 /* re-enable Admin queue interrupt cause */
4970 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4971 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4972 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4973 i40e_flush(hw);
4974
4975 kfree(event.msg_buf);
4976}
4977
4978/**
4979 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4980 * @veb: pointer to the VEB instance
4981 *
4982 * This is a recursive function that first builds the attached VSIs then
4983 * recurses in to build the next layer of VEB. We track the connections
4984 * through our own index numbers because the seid's from the HW could
4985 * change across the reset.
4986 **/
4987static int i40e_reconstitute_veb(struct i40e_veb *veb)
4988{
4989 struct i40e_vsi *ctl_vsi = NULL;
4990 struct i40e_pf *pf = veb->pf;
4991 int v, veb_idx;
4992 int ret;
4993
4994 /* build VSI that owns this VEB, temporarily attached to base VEB */
4995 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4996 if (pf->vsi[v] &&
4997 pf->vsi[v]->veb_idx == veb->idx &&
4998 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4999 ctl_vsi = pf->vsi[v];
5000 break;
5001 }
5002 }
5003 if (!ctl_vsi) {
5004 dev_info(&pf->pdev->dev,
5005 "missing owner VSI for veb_idx %d\n", veb->idx);
5006 ret = -ENOENT;
5007 goto end_reconstitute;
5008 }
5009 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5010 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5011 ret = i40e_add_vsi(ctl_vsi);
5012 if (ret) {
5013 dev_info(&pf->pdev->dev,
5014 "rebuild of owner VSI failed: %d\n", ret);
5015 goto end_reconstitute;
5016 }
5017 i40e_vsi_reset_stats(ctl_vsi);
5018
5019 /* create the VEB in the switch and move the VSI onto the VEB */
5020 ret = i40e_add_veb(veb, ctl_vsi);
5021 if (ret)
5022 goto end_reconstitute;
5023
5024 /* create the remaining VSIs attached to this VEB */
5025 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5026 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5027 continue;
5028
5029 if (pf->vsi[v]->veb_idx == veb->idx) {
5030 struct i40e_vsi *vsi = pf->vsi[v];
5031 vsi->uplink_seid = veb->seid;
5032 ret = i40e_add_vsi(vsi);
5033 if (ret) {
5034 dev_info(&pf->pdev->dev,
5035 "rebuild of vsi_idx %d failed: %d\n",
5036 v, ret);
5037 goto end_reconstitute;
5038 }
5039 i40e_vsi_reset_stats(vsi);
5040 }
5041 }
5042
5043 /* create any VEBs attached to this VEB - RECURSION */
5044 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5045 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5046 pf->veb[veb_idx]->uplink_seid = veb->seid;
5047 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5048 if (ret)
5049 break;
5050 }
5051 }
5052
5053end_reconstitute:
5054 return ret;
5055}
5056
5057/**
5058 * i40e_get_capabilities - get info about the HW
5059 * @pf: the PF struct
5060 **/
5061static int i40e_get_capabilities(struct i40e_pf *pf)
5062{
5063 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5064 u16 data_size;
5065 int buf_len;
5066 int err;
5067
5068 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5069 do {
5070 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5071 if (!cap_buf)
5072 return -ENOMEM;
5073
5074 /* this loads the data into the hw struct for us */
5075 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5076 &data_size,
5077 i40e_aqc_opc_list_func_capabilities,
5078 NULL);
5079 /* data loaded, buffer no longer needed */
5080 kfree(cap_buf);
5081
5082 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5083 /* retry with a larger buffer */
5084 buf_len = data_size;
5085 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5086 dev_info(&pf->pdev->dev,
5087 "capability discovery failed: aq=%d\n",
5088 pf->hw.aq.asq_last_status);
5089 return -ENODEV;
5090 }
5091 } while (err);
5092
d0b10249
JB		 5093 /* increment MSI-X count because current FW skips one */
5094 pf->hw.func_caps.num_msix_vectors++;
7134f9ce 5095
ac71b7ba
ASJ		 5096 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5097 (pf->hw.aq.fw_maj_ver < 2)) {
5098 pf->hw.func_caps.num_msix_vectors++;
5099 pf->hw.func_caps.num_msix_vectors_vf++;
5100 }
5101
41c445ff
JB		 5102 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5103 dev_info(&pf->pdev->dev,
5104 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5105 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5106 pf->hw.func_caps.num_msix_vectors,
5107 pf->hw.func_caps.num_msix_vectors_vf,
5108 pf->hw.func_caps.fd_filters_guaranteed,
5109 pf->hw.func_caps.fd_filters_best_effort,
5110 pf->hw.func_caps.num_tx_qp,
5111 pf->hw.func_caps.num_vsis);
5112
7134f9ce
JB		 5113#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5114 + pf->hw.func_caps.num_vfs)
5115 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5116 dev_info(&pf->pdev->dev,
5117 "got num_vsis %d, setting num_vsis to %d\n",
5118 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5119 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5120 }
5121
41c445ff
JB		 5122 return 0;
5123}
5124
cbf61325
ASJ		 5125static int i40e_vsi_clear(struct i40e_vsi *vsi);
5126
41c445ff 5127/**
cbf61325 5128 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5129 * @pf: board private structure
5130 **/
cbf61325 5131static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5132{
5133 struct i40e_vsi *vsi;
5134 bool new_vsi = false;
5135 int err, i;
5136
cbf61325 5137 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5138 return;
5139
cbf61325 5140 /* find existing VSI and see if it needs configuring */
41c445ff 5141 vsi = NULL;
cbf61325
ASJ		 5142 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5143 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5144 vsi = pf->vsi[i];
cbf61325
ASJ		 5145 break;
5146 }
5147 }
5148
5149 /* create a new VSI if none exists */
41c445ff 5150 if (!vsi) {
cbf61325
ASJ		 5151 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5152 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5153 if (!vsi) {
5154 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
cbf61325 5155 goto err_vsi;
41c445ff
JB		 5156 }
5157 new_vsi = true;
5158 }
cbf61325 5159 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5160
5161 err = i40e_vsi_setup_tx_resources(vsi);
cbf61325
ASJ		 5162 if (err)
5163 goto err_setup_tx;
5164 err = i40e_vsi_setup_rx_resources(vsi);
5165 if (err)
5166 goto err_setup_rx;
5167
5168 if (new_vsi) {
41c445ff 5169 char int_name[IFNAMSIZ + 9];
cbf61325
ASJ		 5170 err = i40e_vsi_configure(vsi);
5171 if (err)
5172 goto err_setup_rx;
41c445ff
JB		 5173 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
5174 dev_driver_string(&pf->pdev->dev));
5175 err = i40e_vsi_request_irq(vsi, int_name);
cbf61325
ASJ		 5176 if (err)
5177 goto err_setup_rx;
41c445ff 5178 err = i40e_up_complete(vsi);
cbf61325
ASJ		 5179 if (err)
5180 goto err_up_complete;
17a73f6b 5181 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
cbf61325 5182 }
41c445ff 5183
cbf61325
ASJ		 5184 return;
5185
5186err_up_complete:
5187 i40e_down(vsi);
5188 i40e_vsi_free_irq(vsi);
5189err_setup_rx:
5190 i40e_vsi_free_rx_resources(vsi);
5191err_setup_tx:
5192 i40e_vsi_free_tx_resources(vsi);
5193err_vsi:
5194 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5195 i40e_vsi_clear(vsi);
41c445ff
JB		 5196}
5197
5198/**
5199 * i40e_fdir_teardown - release the Flow Director resources
5200 * @pf: board private structure
5201 **/
5202static void i40e_fdir_teardown(struct i40e_pf *pf)
5203{
5204 int i;
5205
17a73f6b 5206 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5207 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5208 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5209 i40e_vsi_release(pf->vsi[i]);
5210 break;
5211 }
5212 }
5213}
5214
5215/**
f650a38b 5216 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5217 * @pf: board private structure
5218 *
f650a38b
ASJ		 5219 * Close up the VFs and other things in prep for pf Reset.
5220 **/
5221static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5222{
41c445ff
JB		 5223 struct i40e_hw *hw = &pf->hw;
5224 i40e_status ret;
5225 u32 v;
5226
5227 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5228 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5229 return 0;
41c445ff
JB		 5230
5231 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
5232
37f0be6d
ASJ		 5233 if (i40e_check_asq_alive(hw))
5234 i40e_vc_notify_reset(pf);
41c445ff
JB		 5235
5236 /* quiesce the VSIs and their queues that are not already DOWN */
5237 i40e_pf_quiesce_all_vsi(pf);
5238
5239 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5240 if (pf->vsi[v])
5241 pf->vsi[v]->seid = 0;
5242 }
5243
5244 i40e_shutdown_adminq(&pf->hw);
5245
f650a38b
ASJ		 5246 /* call shutdown HMC */
5247 ret = i40e_shutdown_lan_hmc(hw);
5248 if (ret) {
5249 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5250 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5251 }
5252 return ret;
5253}
5254
5255/**
4dda12e6 5256 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5257 * @pf: board private structure
bc7d338f 5258 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5259 **/
bc7d338f 5260static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5261{
5262 struct i40e_driver_version dv;
5263 struct i40e_hw *hw = &pf->hw;
5264 i40e_status ret;
5265 u32 v;
5266
41c445ff
JB		 5267 /* Now we wait for GRST to settle out.
5268 * We don't have to delete the VEBs or VSIs from the hw switch
5269 * because the reset will make them disappear.
5270 */
5271 ret = i40e_pf_reset(hw);
5272 if (ret)
5273 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5274 pf->pfr_count++;
5275
5276 if (test_bit(__I40E_DOWN, &pf->state))
5277 goto end_core_reset;
5278 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
5279
5280 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5281 ret = i40e_init_adminq(&pf->hw);
5282 if (ret) {
5283 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5284 goto end_core_reset;
5285 }
5286
5287 ret = i40e_get_capabilities(pf);
5288 if (ret) {
5289 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5290 ret);
5291 goto end_core_reset;
5292 }
5293
41c445ff
JB		 5294 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5295 hw->func_caps.num_rx_qp,
5296 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5297 if (ret) {
5298 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5299 goto end_core_reset;
5300 }
5301 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5302 if (ret) {
5303 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5304 goto end_core_reset;
5305 }
5306
4e3b35b0
NP		 5307#ifdef CONFIG_I40E_DCB
5308 ret = i40e_init_pf_dcb(pf);
5309 if (ret) {
5310 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5311 goto end_core_reset;
5312 }
5313#endif /* CONFIG_I40E_DCB */
5314
41c445ff 5315 /* do basic switch setup */
bc7d338f 5316 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5317 if (ret)
5318 goto end_core_reset;
5319
5320 /* Rebuild the VSIs and VEBs that existed before reset.
5321 * They are still in our local switch element arrays, so only
5322 * need to rebuild the switch model in the HW.
5323 *
5324 * If there were VEBs but the reconstitution failed, we'll try
5325 * try to recover minimal use by getting the basic PF VSI working.
5326 */
5327 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
5328 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
5329 /* find the one VEB connected to the MAC, and find orphans */
5330 for (v = 0; v < I40E_MAX_VEB; v++) {
5331 if (!pf->veb[v])
5332 continue;
5333
5334 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5335 pf->veb[v]->uplink_seid == 0) {
5336 ret = i40e_reconstitute_veb(pf->veb[v]);
5337
5338 if (!ret)
5339 continue;
5340
5341 /* If Main VEB failed, we're in deep doodoo,
5342 * so give up rebuilding the switch and set up
5343 * for minimal rebuild of PF VSI.
5344 * If orphan failed, we'll report the error
5345 * but try to keep going.
5346 */
5347 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5348 dev_info(&pf->pdev->dev,
5349 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5350 ret);
5351 pf->vsi[pf->lan_vsi]->uplink_seid
5352 = pf->mac_seid;
5353 break;
5354 } else if (pf->veb[v]->uplink_seid == 0) {
5355 dev_info(&pf->pdev->dev,
5356 "rebuild of orphan VEB failed: %d\n",
5357 ret);
5358 }
5359 }
5360 }
5361 }
5362
5363 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5364 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5365 /* no VEB, so rebuild only the Main VSI */
5366 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5367 if (ret) {
5368 dev_info(&pf->pdev->dev,
5369 "rebuild of Main VSI failed: %d\n", ret);
5370 goto end_core_reset;
5371 }
5372 }
5373
5374 /* reinit the misc interrupt */
5375 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5376 ret = i40e_setup_misc_vector(pf);
5377
5378 /* restart the VSIs that were rebuilt and running before the reset */
5379 i40e_pf_unquiesce_all_vsi(pf);
5380
69f64b2b
MW		 5381 if (pf->num_alloc_vfs) {
5382 for (v = 0; v < pf->num_alloc_vfs; v++)
5383 i40e_reset_vf(&pf->vf[v], true);
5384 }
5385
41c445ff
JB		 5386 /* tell the firmware that we're starting */
5387 dv.major_version = DRV_VERSION_MAJOR;
5388 dv.minor_version = DRV_VERSION_MINOR;
5389 dv.build_version = DRV_VERSION_BUILD;
5390 dv.subbuild_version = 0;
5391 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5392
5393 dev_info(&pf->pdev->dev, "PF reset done\n");
5394
5395end_core_reset:
5396 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5397}
5398
f650a38b
ASJ		 5399/**
5400 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5401 * @pf: board private structure
5402 *
5403 * Close up the VFs and other things in prep for a Core Reset,
5404 * then get ready to rebuild the world.
5405 **/
5406static void i40e_handle_reset_warning(struct i40e_pf *pf)
5407{
5408 i40e_status ret;
5409
5410 ret = i40e_prep_for_reset(pf);
5411 if (!ret)
bc7d338f 5412 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5413}
5414
41c445ff
JB		 5415/**
5416 * i40e_handle_mdd_event
5417 * @pf: pointer to the pf structure
5418 *
5419 * Called from the MDD irq handler to identify possibly malicious vfs
5420 **/
5421static void i40e_handle_mdd_event(struct i40e_pf *pf)
5422{
5423 struct i40e_hw *hw = &pf->hw;
5424 bool mdd_detected = false;
5425 struct i40e_vf *vf;
5426 u32 reg;
5427 int i;
5428
5429 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5430 return;
5431
5432 /* find what triggered the MDD event */
5433 reg = rd32(hw, I40E_GL_MDET_TX);
5434 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5435 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5436 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5437 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5438 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5439 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5440 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5441 dev_info(&pf->pdev->dev,
5442 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
5443 event, queue, func);
5444 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5445 mdd_detected = true;
5446 }
5447 reg = rd32(hw, I40E_GL_MDET_RX);
5448 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5449 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5450 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5451 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5452 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5453 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5454 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5455 dev_info(&pf->pdev->dev,
5456 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
5457 event, queue, func);
5458 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5459 mdd_detected = true;
5460 }
5461
5462 /* see if one of the VFs needs its hand slapped */
5463 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5464 vf = &(pf->vf[i]);
5465 reg = rd32(hw, I40E_VP_MDET_TX(i));
5466 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5467 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5468 vf->num_mdd_events++;
5469 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5470 }
5471
5472 reg = rd32(hw, I40E_VP_MDET_RX(i));
5473 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5474 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5475 vf->num_mdd_events++;
5476 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5477 }
5478
5479 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5480 dev_info(&pf->pdev->dev,
5481 "Too many MDD events on VF %d, disabled\n", i);
5482 dev_info(&pf->pdev->dev,
5483 "Use PF Control I/F to re-enable the VF\n");
5484 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5485 }
5486 }
5487
5488 /* re-enable mdd interrupt cause */
5489 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5490 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5491 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5492 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5493 i40e_flush(hw);
5494}
5495
a1c9a9d9
JK		 5496#ifdef CONFIG_I40E_VXLAN
5497/**
5498 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5499 * @pf: board private structure
5500 **/
5501static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5502{
5503 const int vxlan_hdr_qwords = 4;
5504 struct i40e_hw *hw = &pf->hw;
5505 i40e_status ret;
5506 u8 filter_index;
5507 __be16 port;
5508 int i;
5509
5510 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5511 return;
5512
5513 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5514
5515 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5516 if (pf->pending_vxlan_bitmap & (1 << i)) {
5517 pf->pending_vxlan_bitmap &= ~(1 << i);
5518 port = pf->vxlan_ports[i];
5519 ret = port ?
5520 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5521 vxlan_hdr_qwords,
5522 I40E_AQC_TUNNEL_TYPE_VXLAN,
5523 &filter_index, NULL)
5524 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5525
5526 if (ret) {
5527 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5528 port ? "adding" : "deleting",
5529 ntohs(port), port ? i : i);
5530
5531 pf->vxlan_ports[i] = 0;
5532 } else {
5533 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5534 port ? "Added" : "Deleted",
5535 ntohs(port), port ? i : filter_index);
5536 }
5537 }
5538 }
5539}
5540
5541#endif
41c445ff
JB		 5542/**
5543 * i40e_service_task - Run the driver's async subtasks
5544 * @work: pointer to work_struct containing our data
5545 **/
5546static void i40e_service_task(struct work_struct *work)
5547{
5548 struct i40e_pf *pf = container_of(work,
5549 struct i40e_pf,
5550 service_task);
5551 unsigned long start_time = jiffies;
5552
5553 i40e_reset_subtask(pf);
5554 i40e_handle_mdd_event(pf);
5555 i40e_vc_process_vflr_event(pf);
5556 i40e_watchdog_subtask(pf);
5557 i40e_fdir_reinit_subtask(pf);
5558 i40e_check_hang_subtask(pf);
5559 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5560#ifdef CONFIG_I40E_VXLAN
5561 i40e_sync_vxlan_filters_subtask(pf);
5562#endif
41c445ff
JB		 5563 i40e_clean_adminq_subtask(pf);
5564
5565 i40e_service_event_complete(pf);
5566
5567 /* If the tasks have taken longer than one timer cycle or there
5568 * is more work to be done, reschedule the service task now
5569 * rather than wait for the timer to tick again.
5570 */
5571 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5572 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5573 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5574 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5575 i40e_service_event_schedule(pf);
5576}
5577
5578/**
5579 * i40e_service_timer - timer callback
5580 * @data: pointer to PF struct
5581 **/
5582static void i40e_service_timer(unsigned long data)
5583{
5584 struct i40e_pf *pf = (struct i40e_pf *)data;
5585
5586 mod_timer(&pf->service_timer,
5587 round_jiffies(jiffies + pf->service_timer_period));
5588 i40e_service_event_schedule(pf);
5589}
5590
5591/**
5592 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5593 * @vsi: the VSI being configured
5594 **/
5595static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5596{
5597 struct i40e_pf *pf = vsi->back;
5598
5599 switch (vsi->type) {
5600 case I40E_VSI_MAIN:
5601 vsi->alloc_queue_pairs = pf->num_lan_qps;
5602 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5603 I40E_REQ_DESCRIPTOR_MULTIPLE);
5604 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5605 vsi->num_q_vectors = pf->num_lan_msix;
5606 else
5607 vsi->num_q_vectors = 1;
5608
5609 break;
5610
5611 case I40E_VSI_FDIR:
5612 vsi->alloc_queue_pairs = 1;
5613 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5614 I40E_REQ_DESCRIPTOR_MULTIPLE);
5615 vsi->num_q_vectors = 1;
5616 break;
5617
5618 case I40E_VSI_VMDQ2:
5619 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5620 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5621 I40E_REQ_DESCRIPTOR_MULTIPLE);
5622 vsi->num_q_vectors = pf->num_vmdq_msix;
5623 break;
5624
5625 case I40E_VSI_SRIOV:
5626 vsi->alloc_queue_pairs = pf->num_vf_qps;
5627 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5628 I40E_REQ_DESCRIPTOR_MULTIPLE);
5629 break;
5630
5631 default:
5632 WARN_ON(1);
5633 return -ENODATA;
5634 }
5635
5636 return 0;
5637}
5638
f650a38b
ASJ		 5639/**
5640 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5641 * @type: VSI pointer
bc7d338f 5642 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5643 *
5644 * On error: returns error code (negative)
5645 * On success: returns 0
5646 **/
bc7d338f 5647static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5648{
5649 int size;
5650 int ret = 0;
5651
ac6c5e3d 5652 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5653 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5654 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5655 if (!vsi->tx_rings)
5656 return -ENOMEM;
f650a38b
ASJ		 5657 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5658
bc7d338f
ASJ		 5659 if (alloc_qvectors) {
5660 /* allocate memory for q_vector pointers */
5661 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5662 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5663 if (!vsi->q_vectors) {
5664 ret = -ENOMEM;
5665 goto err_vectors;
5666 }
f650a38b
ASJ		 5667 }
5668 return ret;
5669
5670err_vectors:
5671 kfree(vsi->tx_rings);
5672 return ret;
5673}
5674
41c445ff
JB		 5675/**
5676 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5677 * @pf: board private structure
5678 * @type: type of VSI
5679 *
5680 * On error: returns error code (negative)
5681 * On success: returns vsi index in PF (positive)
5682 **/
5683static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5684{
5685 int ret = -ENODEV;
5686 struct i40e_vsi *vsi;
5687 int vsi_idx;
5688 int i;
5689
5690 /* Need to protect the allocation of the VSIs at the PF level */
5691 mutex_lock(&pf->switch_mutex);
5692
5693 /* VSI list may be fragmented if VSI creation/destruction has
5694 * been happening. We can afford to do a quick scan to look
5695 * for any free VSIs in the list.
5696 *
5697 * find next empty vsi slot, looping back around if necessary
5698 */
5699 i = pf->next_vsi;
5700 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5701 i++;
5702 if (i >= pf->hw.func_caps.num_vsis) {
5703 i = 0;
5704 while (i < pf->next_vsi && pf->vsi[i])
5705 i++;
5706 }
5707
5708 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5709 vsi_idx = i; /* Found one! */
5710 } else {
5711 ret = -ENODEV;
493fb300 5712 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5713 }
5714 pf->next_vsi = ++i;
5715
5716 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5717 if (!vsi) {
5718 ret = -ENOMEM;
493fb300 5719 goto unlock_pf;
41c445ff
JB		 5720 }
5721 vsi->type = type;
5722 vsi->back = pf;
5723 set_bit(__I40E_DOWN, &vsi->state);
5724 vsi->flags = 0;
5725 vsi->idx = vsi_idx;
5726 vsi->rx_itr_setting = pf->rx_itr_default;
5727 vsi->tx_itr_setting = pf->tx_itr_default;
5728 vsi->netdev_registered = false;
5729 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5730 INIT_LIST_HEAD(&vsi->mac_filter_list);
5731
9f65e15b
AD		 5732 ret = i40e_set_num_rings_in_vsi(vsi);
5733 if (ret)
5734 goto err_rings;
5735
bc7d338f 5736 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5737 if (ret)
9f65e15b 5738 goto err_rings;
493fb300 5739
41c445ff
JB		 5740 /* Setup default MSIX irq handler for VSI */
5741 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5742
5743 pf->vsi[vsi_idx] = vsi;
5744 ret = vsi_idx;
493fb300
AD		 5745 goto unlock_pf;
5746
9f65e15b 5747err_rings:
493fb300
AD		 5748 pf->next_vsi = i - 1;
5749 kfree(vsi);
5750unlock_pf:
41c445ff
JB		 5751 mutex_unlock(&pf->switch_mutex);
5752 return ret;
5753}
5754
f650a38b
ASJ		 5755/**
5756 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5757 * @type: VSI pointer
bc7d338f 5758 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5759 *
5760 * On error: returns error code (negative)
5761 * On success: returns 0
5762 **/
bc7d338f 5763static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5764{
5765 /* free the ring and vector containers */
bc7d338f
ASJ		 5766 if (free_qvectors) {
5767 kfree(vsi->q_vectors);
5768 vsi->q_vectors = NULL;
5769 }
f650a38b
ASJ		 5770 kfree(vsi->tx_rings);
5771 vsi->tx_rings = NULL;
5772 vsi->rx_rings = NULL;
5773}
5774
41c445ff
JB		 5775/**
5776 * i40e_vsi_clear - Deallocate the VSI provided
5777 * @vsi: the VSI being un-configured
5778 **/
5779static int i40e_vsi_clear(struct i40e_vsi *vsi)
5780{
5781 struct i40e_pf *pf;
5782
5783 if (!vsi)
5784 return 0;
5785
5786 if (!vsi->back)
5787 goto free_vsi;
5788 pf = vsi->back;
5789
5790 mutex_lock(&pf->switch_mutex);
5791 if (!pf->vsi[vsi->idx]) {
5792 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5793 vsi->idx, vsi->idx, vsi, vsi->type);
5794 goto unlock_vsi;
5795 }
5796
5797 if (pf->vsi[vsi->idx] != vsi) {
5798 dev_err(&pf->pdev->dev,
5799 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5800 pf->vsi[vsi->idx]->idx,
5801 pf->vsi[vsi->idx],
5802 pf->vsi[vsi->idx]->type,
5803 vsi->idx, vsi, vsi->type);
5804 goto unlock_vsi;
5805 }
5806
5807 /* updates the pf for this cleared vsi */
5808 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5809 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5810
bc7d338f 5811 i40e_vsi_free_arrays(vsi, true);
493fb300 5812
41c445ff
JB		 5813 pf->vsi[vsi->idx] = NULL;
5814 if (vsi->idx < pf->next_vsi)
5815 pf->next_vsi = vsi->idx;
5816
5817unlock_vsi:
5818 mutex_unlock(&pf->switch_mutex);
5819free_vsi:
5820 kfree(vsi);
5821
5822 return 0;
5823}
5824
9f65e15b
AD		 5825/**
5826 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5827 * @vsi: the VSI being cleaned
5828 **/
be1d5eea 5829static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5830{
5831 int i;
5832
8e9dca53 5833 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5834 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5835 kfree_rcu(vsi->tx_rings[i], rcu);
5836 vsi->tx_rings[i] = NULL;
5837 vsi->rx_rings[i] = NULL;
5838 }
be1d5eea 5839 }
9f65e15b
AD		 5840}
5841
41c445ff
JB		 5842/**
5843 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5844 * @vsi: the VSI being configured
5845 **/
5846static int i40e_alloc_rings(struct i40e_vsi *vsi)
5847{
5848 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5849 int i;
5850
41c445ff 5851 /* Set basic values in the rings to be used later during open() */
d7397644 5852 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5853 struct i40e_ring *tx_ring;
5854 struct i40e_ring *rx_ring;
5855
ac6c5e3d 5856 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5857 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5858 if (!tx_ring)
5859 goto err_out;
41c445ff
JB		 5860
5861 tx_ring->queue_index = i;
5862 tx_ring->reg_idx = vsi->base_queue + i;
5863 tx_ring->ring_active = false;
5864 tx_ring->vsi = vsi;
5865 tx_ring->netdev = vsi->netdev;
5866 tx_ring->dev = &pf->pdev->dev;
5867 tx_ring->count = vsi->num_desc;
5868 tx_ring->size = 0;
5869 tx_ring->dcb_tc = 0;
9f65e15b 5870 vsi->tx_rings[i] = tx_ring;
41c445ff 5871
9f65e15b 5872 rx_ring = &tx_ring[1];
41c445ff
JB		 5873 rx_ring->queue_index = i;
5874 rx_ring->reg_idx = vsi->base_queue + i;
5875 rx_ring->ring_active = false;
5876 rx_ring->vsi = vsi;
5877 rx_ring->netdev = vsi->netdev;
5878 rx_ring->dev = &pf->pdev->dev;
5879 rx_ring->count = vsi->num_desc;
5880 rx_ring->size = 0;
5881 rx_ring->dcb_tc = 0;
5882 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5883 set_ring_16byte_desc_enabled(rx_ring);
5884 else
5885 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5886 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5887 }
5888
5889 return 0;
9f65e15b
AD		 5890
5891err_out:
5892 i40e_vsi_clear_rings(vsi);
5893 return -ENOMEM;
41c445ff
JB		 5894}
5895
5896/**
5897 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5898 * @pf: board private structure
5899 * @vectors: the number of MSI-X vectors to request
5900 *
5901 * Returns the number of vectors reserved, or error
5902 **/
5903static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5904{
7b37f376
AG		 5905 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
5906 I40E_MIN_MSIX, vectors);
5907 if (vectors < 0) {
41c445ff 5908 dev_info(&pf->pdev->dev,
7b37f376 5909 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 5910 vectors = 0;
5911 }
5912
7b37f376
AG		 5913 pf->num_msix_entries = vectors;
5914
41c445ff
JB		 5915 return vectors;
5916}
5917
5918/**
5919 * i40e_init_msix - Setup the MSIX capability
5920 * @pf: board private structure
5921 *
5922 * Work with the OS to set up the MSIX vectors needed.
5923 *
5924 * Returns 0 on success, negative on failure
5925 **/
5926static int i40e_init_msix(struct i40e_pf *pf)
5927{
5928 i40e_status err = 0;
5929 struct i40e_hw *hw = &pf->hw;
5930 int v_budget, i;
5931 int vec;
5932
5933 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5934 return -ENODEV;
5935
5936 /* The number of vectors we'll request will be comprised of:
5937 * - Add 1 for "other" cause for Admin Queue events, etc.
5938 * - The number of LAN queue pairs
f8ff1464
ASJ		 5939 * - Queues being used for RSS.
5940 * We don't need as many as max_rss_size vectors.
5941 * use rss_size instead in the calculation since that
5942 * is governed by number of cpus in the system.
5943 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5944 * - The number of VMDq pairs
5945 * Once we count this up, try the request.
5946 *
5947 * If we can't get what we want, we'll simplify to nearly nothing
5948 * and try again. If that still fails, we punt.
5949 */
f8ff1464 5950 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5951 pf->num_vmdq_msix = pf->num_vmdq_qps;
5952 v_budget = 1 + pf->num_lan_msix;
5953 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 5954 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 5955 v_budget++;
5956
5957 /* Scale down if necessary, and the rings will share vectors */
5958 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5959
5960 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5961 GFP_KERNEL);
5962 if (!pf->msix_entries)
5963 return -ENOMEM;
5964
5965 for (i = 0; i < v_budget; i++)
5966 pf->msix_entries[i].entry = i;
5967 vec = i40e_reserve_msix_vectors(pf, v_budget);
5968 if (vec < I40E_MIN_MSIX) {
5969 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5970 kfree(pf->msix_entries);
5971 pf->msix_entries = NULL;
5972 return -ENODEV;
5973
5974 } else if (vec == I40E_MIN_MSIX) {
5975 /* Adjust for minimal MSIX use */
77fa28be 5976 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 5977 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5978 pf->num_vmdq_vsis = 0;
5979 pf->num_vmdq_qps = 0;
5980 pf->num_vmdq_msix = 0;
5981 pf->num_lan_qps = 1;
5982 pf->num_lan_msix = 1;
5983
5984 } else if (vec != v_budget) {
5985 /* Scale vector usage down */
5986 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5987 vec--; /* reserve the misc vector */
5988
5989 /* partition out the remaining vectors */
5990 switch (vec) {
5991 case 2:
5992 pf->num_vmdq_vsis = 1;
5993 pf->num_lan_msix = 1;
5994 break;
5995 case 3:
5996 pf->num_vmdq_vsis = 1;
5997 pf->num_lan_msix = 2;
5998 break;
5999 default:
6000 pf->num_lan_msix = min_t(int, (vec / 2),
6001 pf->num_lan_qps);
6002 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6003 I40E_DEFAULT_NUM_VMDQ_VSI);
6004 break;
6005 }
6006 }
6007
6008 return err;
6009}
6010
493fb300
AD		 6011/**
6012 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
6013 * @vsi: the VSI being configured
6014 * @v_idx: index of the vector in the vsi struct
6015 *
6016 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6017 **/
6018static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
6019{
6020 struct i40e_q_vector *q_vector;
6021
6022 /* allocate q_vector */
6023 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6024 if (!q_vector)
6025 return -ENOMEM;
6026
6027 q_vector->vsi = vsi;
6028 q_vector->v_idx = v_idx;
6029 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6030 if (vsi->netdev)
6031 netif_napi_add(vsi->netdev, &q_vector->napi,
6032 i40e_napi_poll, vsi->work_limit);
6033
cd0b6fa6
AD		 6034 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6035 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6036
493fb300
AD		 6037 /* tie q_vector and vsi together */
6038 vsi->q_vectors[v_idx] = q_vector;
6039
6040 return 0;
6041}
6042
41c445ff
JB		 6043/**
6044 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
6045 * @vsi: the VSI being configured
6046 *
6047 * We allocate one q_vector per queue interrupt. If allocation fails we
6048 * return -ENOMEM.
6049 **/
6050static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
6051{
6052 struct i40e_pf *pf = vsi->back;
6053 int v_idx, num_q_vectors;
493fb300 6054 int err;
41c445ff
JB		 6055
6056 /* if not MSIX, give the one vector only to the LAN VSI */
6057 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6058 num_q_vectors = vsi->num_q_vectors;
6059 else if (vsi == pf->vsi[pf->lan_vsi])
6060 num_q_vectors = 1;
6061 else
6062 return -EINVAL;
6063
41c445ff 6064 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 6065 err = i40e_alloc_q_vector(vsi, v_idx);
6066 if (err)
6067 goto err_out;
41c445ff
JB		 6068 }
6069
6070 return 0;
493fb300
AD		 6071
6072err_out:
6073 while (v_idx--)
6074 i40e_free_q_vector(vsi, v_idx);
6075
6076 return err;
41c445ff
JB		 6077}
6078
6079/**
6080 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6081 * @pf: board private structure to initialize
6082 **/
6083static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6084{
6085 int err = 0;
6086
6087 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6088 err = i40e_init_msix(pf);
6089 if (err) {
60ea5f83
JB		 6090 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6091 I40E_FLAG_RSS_ENABLED |
6092 I40E_FLAG_DCB_ENABLED |
6093 I40E_FLAG_SRIOV_ENABLED |
6094 I40E_FLAG_FD_SB_ENABLED |
6095 I40E_FLAG_FD_ATR_ENABLED |
6096 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6097
6098 /* rework the queue expectations without MSIX */
6099 i40e_determine_queue_usage(pf);
6100 }
6101 }
6102
6103 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6104 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6105 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6106 err = pci_enable_msi(pf->pdev);
6107 if (err) {
958a3e3b 6108 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6109 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6110 }
6111 }
6112
958a3e3b 6113 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6114 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6115
41c445ff
JB		 6116 /* track first vector for misc interrupts */
6117 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6118}
6119
6120/**
6121 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6122 * @pf: board private structure
6123 *
6124 * This sets up the handler for MSIX 0, which is used to manage the
6125 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6126 * when in MSI or Legacy interrupt mode.
6127 **/
6128static int i40e_setup_misc_vector(struct i40e_pf *pf)
6129{
6130 struct i40e_hw *hw = &pf->hw;
6131 int err = 0;
6132
6133 /* Only request the irq if this is the first time through, and
6134 * not when we're rebuilding after a Reset
6135 */
6136 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6137 err = request_irq(pf->msix_entries[0].vector,
6138 i40e_intr, 0, pf->misc_int_name, pf);
6139 if (err) {
6140 dev_info(&pf->pdev->dev,
77fa28be
CS		 6141 "request_irq for %s failed: %d\n",
6142 pf->misc_int_name, err);
41c445ff
JB		 6143 return -EFAULT;
6144 }
6145 }
6146
6147 i40e_enable_misc_int_causes(hw);
6148
6149 /* associate no queues to the misc vector */
6150 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6151 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6152
6153 i40e_flush(hw);
6154
6155 i40e_irq_dynamic_enable_icr0(pf);
6156
6157 return err;
6158}
6159
6160/**
6161 * i40e_config_rss - Prepare for RSS if used
6162 * @pf: board private structure
6163 **/
6164static int i40e_config_rss(struct i40e_pf *pf)
6165{
41c445ff
JB		 6166 /* Set of random keys generated using kernel random number generator */
6167 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6168 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6169 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6170 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6171 struct i40e_hw *hw = &pf->hw;
6172 u32 lut = 0;
6173 int i, j;
6174 u64 hena;
41c445ff
JB		 6175
6176 /* Fill out hash function seed */
6177 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6178 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6179
6180 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6181 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6182 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6183 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6184 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6185 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6186
6187 /* Populate the LUT with max no. of queues in round robin fashion */
6188 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6189
6190 /* The assumption is that lan qp count will be the highest
6191 * qp count for any PF VSI that needs RSS.
6192 * If multiple VSIs need RSS support, all the qp counts
6193 * for those VSIs should be a power of 2 for RSS to work.
6194 * If LAN VSI is the only consumer for RSS then this requirement
6195 * is not necessary.
6196 */
6197 if (j == pf->rss_size)
6198 j = 0;
6199 /* lut = 4-byte sliding window of 4 lut entries */
6200 lut = (lut << 8) | (j &
6201 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6202 /* On i = 3, we have 4 entries in lut; write to the register */
6203 if ((i & 3) == 3)
6204 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6205 }
6206 i40e_flush(hw);
6207
6208 return 0;
6209}
6210
f8ff1464
ASJ		 6211/**
6212 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6213 * @pf: board private structure
6214 * @queue_count: the requested queue count for rss.
6215 *
6216 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6217 * count which may be different from the requested queue count.
6218 **/
6219int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6220{
6221 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6222 return 0;
6223
6224 queue_count = min_t(int, queue_count, pf->rss_size_max);
6225 queue_count = rounddown_pow_of_two(queue_count);
6226
6227 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6228 i40e_prep_for_reset(pf);
6229
f8ff1464
ASJ		 6230 pf->rss_size = queue_count;
6231
6232 i40e_reset_and_rebuild(pf, true);
6233 i40e_config_rss(pf);
6234 }
6235 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6236 return pf->rss_size;
6237}
6238
41c445ff
JB		 6239/**
6240 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6241 * @pf: board private structure to initialize
6242 *
6243 * i40e_sw_init initializes the Adapter private data structure.
6244 * Fields are initialized based on PCI device information and
6245 * OS network device settings (MTU size).
6246 **/
6247static int i40e_sw_init(struct i40e_pf *pf)
6248{
6249 int err = 0;
6250 int size;
6251
6252 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6253 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6254 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6255 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6256 if (I40E_DEBUG_USER & debug)
6257 pf->hw.debug_mask = debug;
6258 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6259 I40E_DEFAULT_MSG_ENABLE);
6260 }
6261
6262 /* Set default capability flags */
6263 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6264 I40E_FLAG_MSI_ENABLED |
6265 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6266 I40E_FLAG_RX_1BUF_ENABLED;
6267
7134f9ce
JB		 6268 /* Depending on PF configurations, it is possible that the RSS
6269 * maximum might end up larger than the available queues
6270 */
41c445ff 6271 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6272 pf->rss_size_max = min_t(int, pf->rss_size_max,
6273 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6274 if (pf->hw.func_caps.rss) {
6275 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6276 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6277 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6278 } else {
6279 pf->rss_size = 1;
6280 }
6281
2050bc65
CS		 6282 /* MFP mode enabled */
6283 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6284 pf->flags |= I40E_FLAG_MFP_ENABLED;
6285 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6286 }
6287
cbf61325
ASJ		 6288 /* FW/NVM is not yet fixed in this regard */
6289 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6290 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6291 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6292 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6293 dev_info(&pf->pdev->dev,
6294 "Flow Director ATR mode Enabled\n");
6295 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6296 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 6297 dev_info(&pf->pdev->dev,
6298 "Flow Director Side Band mode Enabled\n");
cbf61325
ASJ		 6299 } else {
6300 dev_info(&pf->pdev->dev,
6301 "Flow Director Side Band mode Disabled in MFP mode\n");
41c445ff 6302 }
cbf61325
ASJ		 6303 pf->fdir_pf_filter_count =
6304 pf->hw.func_caps.fd_filters_guaranteed;
6305 pf->hw.fdir_shared_filter_count =
6306 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6307 }
6308
6309 if (pf->hw.func_caps.vmdq) {
6310 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6311 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6312 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6313 }
6314
41c445ff
JB		 6315#ifdef CONFIG_PCI_IOV
6316 if (pf->hw.func_caps.num_vfs) {
6317 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6318 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6319 pf->num_req_vfs = min_t(int,
6320 pf->hw.func_caps.num_vfs,
6321 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 6322 dev_info(&pf->pdev->dev,
6323 "Number of VFs being requested for PF[%d] = %d\n",
6324 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 6325 }
6326#endif /* CONFIG_PCI_IOV */
6327 pf->eeprom_version = 0xDEAD;
6328 pf->lan_veb = I40E_NO_VEB;
6329 pf->lan_vsi = I40E_NO_VSI;
6330
6331 /* set up queue assignment tracking */
6332 size = sizeof(struct i40e_lump_tracking)
6333 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6334 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6335 if (!pf->qp_pile) {
6336 err = -ENOMEM;
6337 goto sw_init_done;
6338 }
6339 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6340 pf->qp_pile->search_hint = 0;
6341
6342 /* set up vector assignment tracking */
6343 size = sizeof(struct i40e_lump_tracking)
6344 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6345 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6346 if (!pf->irq_pile) {
6347 kfree(pf->qp_pile);
6348 err = -ENOMEM;
6349 goto sw_init_done;
6350 }
6351 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6352 pf->irq_pile->search_hint = 0;
6353
6354 mutex_init(&pf->switch_mutex);
6355
6356sw_init_done:
6357 return err;
6358}
6359
6360/**
6361 * i40e_set_features - set the netdev feature flags
6362 * @netdev: ptr to the netdev being adjusted
6363 * @features: the feature set that the stack is suggesting
6364 **/
6365static int i40e_set_features(struct net_device *netdev,
6366 netdev_features_t features)
6367{
6368 struct i40e_netdev_priv *np = netdev_priv(netdev);
6369 struct i40e_vsi *vsi = np->vsi;
6370
6371 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6372 i40e_vlan_stripping_enable(vsi);
6373 else
6374 i40e_vlan_stripping_disable(vsi);
6375
6376 return 0;
6377}
6378
a1c9a9d9
JK		 6379#ifdef CONFIG_I40E_VXLAN
6380/**
6381 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6382 * @pf: board private structure
6383 * @port: The UDP port to look up
6384 *
6385 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6386 **/
6387static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6388{
6389 u8 i;
6390
6391 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6392 if (pf->vxlan_ports[i] == port)
6393 return i;
6394 }
6395
6396 return i;
6397}
6398
6399/**
6400 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6401 * @netdev: This physical port's netdev
6402 * @sa_family: Socket Family that VXLAN is notifying us about
6403 * @port: New UDP port number that VXLAN started listening to
6404 **/
6405static void i40e_add_vxlan_port(struct net_device *netdev,
6406 sa_family_t sa_family, __be16 port)
6407{
6408 struct i40e_netdev_priv *np = netdev_priv(netdev);
6409 struct i40e_vsi *vsi = np->vsi;
6410 struct i40e_pf *pf = vsi->back;
6411 u8 next_idx;
6412 u8 idx;
6413
6414 if (sa_family == AF_INET6)
6415 return;
6416
6417 idx = i40e_get_vxlan_port_idx(pf, port);
6418
6419 /* Check if port already exists */
6420 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6421 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6422 return;
6423 }
6424
6425 /* Now check if there is space to add the new port */
6426 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6427
6428 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6429 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6430 ntohs(port));
6431 return;
6432 }
6433
6434 /* New port: add it and mark its index in the bitmap */
6435 pf->vxlan_ports[next_idx] = port;
6436 pf->pending_vxlan_bitmap |= (1 << next_idx);
6437
6438 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6439}
6440
6441/**
6442 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6443 * @netdev: This physical port's netdev
6444 * @sa_family: Socket Family that VXLAN is notifying us about
6445 * @port: UDP port number that VXLAN stopped listening to
6446 **/
6447static void i40e_del_vxlan_port(struct net_device *netdev,
6448 sa_family_t sa_family, __be16 port)
6449{
6450 struct i40e_netdev_priv *np = netdev_priv(netdev);
6451 struct i40e_vsi *vsi = np->vsi;
6452 struct i40e_pf *pf = vsi->back;
6453 u8 idx;
6454
6455 if (sa_family == AF_INET6)
6456 return;
6457
6458 idx = i40e_get_vxlan_port_idx(pf, port);
6459
6460 /* Check if port already exists */
6461 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6462 /* if port exists, set it to 0 (mark for deletion)
6463 * and make it pending
6464 */
6465 pf->vxlan_ports[idx] = 0;
6466
6467 pf->pending_vxlan_bitmap |= (1 << idx);
6468
6469 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6470 } else {
6471 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6472 ntohs(port));
6473 }
6474}
6475
6476#endif
41c445ff
JB		 6477static const struct net_device_ops i40e_netdev_ops = {
6478 .ndo_open = i40e_open,
6479 .ndo_stop = i40e_close,
6480 .ndo_start_xmit = i40e_lan_xmit_frame,
6481 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6482 .ndo_set_rx_mode = i40e_set_rx_mode,
6483 .ndo_validate_addr = eth_validate_addr,
6484 .ndo_set_mac_address = i40e_set_mac,
6485 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6486 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6487 .ndo_tx_timeout = i40e_tx_timeout,
6488 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6489 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6490#ifdef CONFIG_NET_POLL_CONTROLLER
6491 .ndo_poll_controller = i40e_netpoll,
6492#endif
6493 .ndo_setup_tc = i40e_setup_tc,
6494 .ndo_set_features = i40e_set_features,
6495 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6496 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6497 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6498 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6499#ifdef CONFIG_I40E_VXLAN
6500 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6501 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6502#endif
41c445ff
JB		 6503};
6504
6505/**
6506 * i40e_config_netdev - Setup the netdev flags
6507 * @vsi: the VSI being configured
6508 *
6509 * Returns 0 on success, negative value on failure
6510 **/
6511static int i40e_config_netdev(struct i40e_vsi *vsi)
6512{
1a10370a 6513 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6514 struct i40e_pf *pf = vsi->back;
6515 struct i40e_hw *hw = &pf->hw;
6516 struct i40e_netdev_priv *np;
6517 struct net_device *netdev;
6518 u8 mac_addr[ETH_ALEN];
6519 int etherdev_size;
6520
6521 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6522 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6523 if (!netdev)
6524 return -ENOMEM;
6525
6526 vsi->netdev = netdev;
6527 np = netdev_priv(netdev);
6528 np->vsi = vsi;
6529
6530 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6531 NETIF_F_GSO_UDP_TUNNEL |
6532 NETIF_F_TSO |
6533 NETIF_F_SG;
6534
6535 netdev->features = NETIF_F_SG |
6536 NETIF_F_IP_CSUM |
6537 NETIF_F_SCTP_CSUM |
6538 NETIF_F_HIGHDMA |
6539 NETIF_F_GSO_UDP_TUNNEL |
6540 NETIF_F_HW_VLAN_CTAG_TX |
6541 NETIF_F_HW_VLAN_CTAG_RX |
6542 NETIF_F_HW_VLAN_CTAG_FILTER |
6543 NETIF_F_IPV6_CSUM |
6544 NETIF_F_TSO |
6545 NETIF_F_TSO6 |
6546 NETIF_F_RXCSUM |
6547 NETIF_F_RXHASH |
6548 0;
6549
6550 /* copy netdev features into list of user selectable features */
6551 netdev->hw_features |= netdev->features;
6552
6553 if (vsi->type == I40E_VSI_MAIN) {
6554 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6555 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6556 } else {
6557 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6558 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6559 pf->vsi[pf->lan_vsi]->netdev->name);
6560 random_ether_addr(mac_addr);
6561 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6562 }
1a10370a 6563 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6564
6565 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6566 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6567 /* vlan gets same features (except vlan offload)
6568 * after any tweaks for specific VSI types
6569 */
6570 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6571 NETIF_F_HW_VLAN_CTAG_RX |
6572 NETIF_F_HW_VLAN_CTAG_FILTER);
6573 netdev->priv_flags |= IFF_UNICAST_FLT;
6574 netdev->priv_flags |= IFF_SUPP_NOFCS;
6575 /* Setup netdev TC information */
6576 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6577
6578 netdev->netdev_ops = &i40e_netdev_ops;
6579 netdev->watchdog_timeo = 5 * HZ;
6580 i40e_set_ethtool_ops(netdev);
6581
6582 return 0;
6583}
6584
6585/**
6586 * i40e_vsi_delete - Delete a VSI from the switch
6587 * @vsi: the VSI being removed
6588 *
6589 * Returns 0 on success, negative value on failure
6590 **/
6591static void i40e_vsi_delete(struct i40e_vsi *vsi)
6592{
6593 /* remove default VSI is not allowed */
6594 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6595 return;
6596
41c445ff
JB		 6597 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6598 return;
6599}
6600
6601/**
6602 * i40e_add_vsi - Add a VSI to the switch
6603 * @vsi: the VSI being configured
6604 *
6605 * This initializes a VSI context depending on the VSI type to be added and
6606 * passes it down to the add_vsi aq command.
6607 **/
6608static int i40e_add_vsi(struct i40e_vsi *vsi)
6609{
6610 int ret = -ENODEV;
6611 struct i40e_mac_filter *f, *ftmp;
6612 struct i40e_pf *pf = vsi->back;
6613 struct i40e_hw *hw = &pf->hw;
6614 struct i40e_vsi_context ctxt;
6615 u8 enabled_tc = 0x1; /* TC0 enabled */
6616 int f_count = 0;
6617
6618 memset(&ctxt, 0, sizeof(ctxt));
6619 switch (vsi->type) {
6620 case I40E_VSI_MAIN:
6621 /* The PF's main VSI is already setup as part of the
6622 * device initialization, so we'll not bother with
6623 * the add_vsi call, but we will retrieve the current
6624 * VSI context.
6625 */
6626 ctxt.seid = pf->main_vsi_seid;
6627 ctxt.pf_num = pf->hw.pf_id;
6628 ctxt.vf_num = 0;
6629 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6630 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6631 if (ret) {
6632 dev_info(&pf->pdev->dev,
6633 "couldn't get pf vsi config, err %d, aq_err %d\n",
6634 ret, pf->hw.aq.asq_last_status);
6635 return -ENOENT;
6636 }
6637 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6638 vsi->info.valid_sections = 0;
6639
6640 vsi->seid = ctxt.seid;
6641 vsi->id = ctxt.vsi_number;
6642
6643 enabled_tc = i40e_pf_get_tc_map(pf);
6644
6645 /* MFP mode setup queue map and update VSI */
6646 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6647 memset(&ctxt, 0, sizeof(ctxt));
6648 ctxt.seid = pf->main_vsi_seid;
6649 ctxt.pf_num = pf->hw.pf_id;
6650 ctxt.vf_num = 0;
6651 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6652 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6653 if (ret) {
6654 dev_info(&pf->pdev->dev,
6655 "update vsi failed, aq_err=%d\n",
6656 pf->hw.aq.asq_last_status);
6657 ret = -ENOENT;
6658 goto err;
6659 }
6660 /* update the local VSI info queue map */
6661 i40e_vsi_update_queue_map(vsi, &ctxt);
6662 vsi->info.valid_sections = 0;
6663 } else {
6664 /* Default/Main VSI is only enabled for TC0
6665 * reconfigure it to enable all TCs that are
6666 * available on the port in SFP mode.
6667 */
6668 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6669 if (ret) {
6670 dev_info(&pf->pdev->dev,
6671 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6672 enabled_tc, ret,
6673 pf->hw.aq.asq_last_status);
6674 ret = -ENOENT;
6675 }
6676 }
6677 break;
6678
6679 case I40E_VSI_FDIR:
cbf61325
ASJ		 6680 ctxt.pf_num = hw->pf_id;
6681 ctxt.vf_num = 0;
6682 ctxt.uplink_seid = vsi->uplink_seid;
6683 ctxt.connection_type = 0x1; /* regular data port */
6684 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6685 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6686 break;
6687
6688 case I40E_VSI_VMDQ2:
6689 ctxt.pf_num = hw->pf_id;
6690 ctxt.vf_num = 0;
6691 ctxt.uplink_seid = vsi->uplink_seid;
6692 ctxt.connection_type = 0x1; /* regular data port */
6693 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6694
6695 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6696
6697 /* This VSI is connected to VEB so the switch_id
6698 * should be set to zero by default.
6699 */
6700 ctxt.info.switch_id = 0;
6701 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6702 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6703
6704 /* Setup the VSI tx/rx queue map for TC0 only for now */
6705 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6706 break;
6707
6708 case I40E_VSI_SRIOV:
6709 ctxt.pf_num = hw->pf_id;
6710 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6711 ctxt.uplink_seid = vsi->uplink_seid;
6712 ctxt.connection_type = 0x1; /* regular data port */
6713 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6714
6715 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6716
6717 /* This VSI is connected to VEB so the switch_id
6718 * should be set to zero by default.
6719 */
6720 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6721
6722 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6723 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6724 /* Setup the VSI tx/rx queue map for TC0 only for now */
6725 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6726 break;
6727
6728 default:
6729 return -ENODEV;
6730 }
6731
6732 if (vsi->type != I40E_VSI_MAIN) {
6733 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6734 if (ret) {
6735 dev_info(&vsi->back->pdev->dev,
6736 "add vsi failed, aq_err=%d\n",
6737 vsi->back->hw.aq.asq_last_status);
6738 ret = -ENOENT;
6739 goto err;
6740 }
6741 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6742 vsi->info.valid_sections = 0;
6743 vsi->seid = ctxt.seid;
6744 vsi->id = ctxt.vsi_number;
6745 }
6746
6747 /* If macvlan filters already exist, force them to get loaded */
6748 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6749 f->changed = true;
6750 f_count++;
6751 }
6752 if (f_count) {
6753 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6754 pf->flags |= I40E_FLAG_FILTER_SYNC;
6755 }
6756
6757 /* Update VSI BW information */
6758 ret = i40e_vsi_get_bw_info(vsi);
6759 if (ret) {
6760 dev_info(&pf->pdev->dev,
6761 "couldn't get vsi bw info, err %d, aq_err %d\n",
6762 ret, pf->hw.aq.asq_last_status);
6763 /* VSI is already added so not tearing that up */
6764 ret = 0;
6765 }
6766
6767err:
6768 return ret;
6769}
6770
6771/**
6772 * i40e_vsi_release - Delete a VSI and free its resources
6773 * @vsi: the VSI being removed
6774 *
6775 * Returns 0 on success or < 0 on error
6776 **/
6777int i40e_vsi_release(struct i40e_vsi *vsi)
6778{
6779 struct i40e_mac_filter *f, *ftmp;
6780 struct i40e_veb *veb = NULL;
6781 struct i40e_pf *pf;
6782 u16 uplink_seid;
6783 int i, n;
6784
6785 pf = vsi->back;
6786
6787 /* release of a VEB-owner or last VSI is not allowed */
6788 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6789 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6790 vsi->seid, vsi->uplink_seid);
6791 return -ENODEV;
6792 }
6793 if (vsi == pf->vsi[pf->lan_vsi] &&
6794 !test_bit(__I40E_DOWN, &pf->state)) {
6795 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6796 return -ENODEV;
6797 }
6798
6799 uplink_seid = vsi->uplink_seid;
6800 if (vsi->type != I40E_VSI_SRIOV) {
6801 if (vsi->netdev_registered) {
6802 vsi->netdev_registered = false;
6803 if (vsi->netdev) {
6804 /* results in a call to i40e_close() */
6805 unregister_netdev(vsi->netdev);
6806 free_netdev(vsi->netdev);
6807 vsi->netdev = NULL;
6808 }
6809 } else {
6810 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6811 i40e_down(vsi);
6812 i40e_vsi_free_irq(vsi);
6813 i40e_vsi_free_tx_resources(vsi);
6814 i40e_vsi_free_rx_resources(vsi);
6815 }
6816 i40e_vsi_disable_irq(vsi);
6817 }
6818
6819 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6820 i40e_del_filter(vsi, f->macaddr, f->vlan,
6821 f->is_vf, f->is_netdev);
6822 i40e_sync_vsi_filters(vsi);
6823
6824 i40e_vsi_delete(vsi);
6825 i40e_vsi_free_q_vectors(vsi);
6826 i40e_vsi_clear_rings(vsi);
6827 i40e_vsi_clear(vsi);
6828
6829 /* If this was the last thing on the VEB, except for the
6830 * controlling VSI, remove the VEB, which puts the controlling
6831 * VSI onto the next level down in the switch.
6832 *
6833 * Well, okay, there's one more exception here: don't remove
6834 * the orphan VEBs yet. We'll wait for an explicit remove request
6835 * from up the network stack.
6836 */
6837 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6838 if (pf->vsi[i] &&
6839 pf->vsi[i]->uplink_seid == uplink_seid &&
6840 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6841 n++; /* count the VSIs */
6842 }
6843 }
6844 for (i = 0; i < I40E_MAX_VEB; i++) {
6845 if (!pf->veb[i])
6846 continue;
6847 if (pf->veb[i]->uplink_seid == uplink_seid)
6848 n++; /* count the VEBs */
6849 if (pf->veb[i]->seid == uplink_seid)
6850 veb = pf->veb[i];
6851 }
6852 if (n == 0 && veb && veb->uplink_seid != 0)
6853 i40e_veb_release(veb);
6854
6855 return 0;
6856}
6857
6858/**
6859 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6860 * @vsi: ptr to the VSI
6861 *
6862 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6863 * corresponding SW VSI structure and initializes num_queue_pairs for the
6864 * newly allocated VSI.
6865 *
6866 * Returns 0 on success or negative on failure
6867 **/
6868static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6869{
6870 int ret = -ENOENT;
6871 struct i40e_pf *pf = vsi->back;
6872
493fb300 6873 if (vsi->q_vectors[0]) {
41c445ff
JB		 6874 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6875 vsi->seid);
6876 return -EEXIST;
6877 }
6878
6879 if (vsi->base_vector) {
6880 dev_info(&pf->pdev->dev,
6881 "VSI %d has non-zero base vector %d\n",
6882 vsi->seid, vsi->base_vector);
6883 return -EEXIST;
6884 }
6885
6886 ret = i40e_alloc_q_vectors(vsi);
6887 if (ret) {
6888 dev_info(&pf->pdev->dev,
6889 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6890 vsi->num_q_vectors, vsi->seid, ret);
6891 vsi->num_q_vectors = 0;
6892 goto vector_setup_out;
6893 }
6894
958a3e3b
SN		 6895 if (vsi->num_q_vectors)
6896 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6897 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6898 if (vsi->base_vector < 0) {
6899 dev_info(&pf->pdev->dev,
6900 "failed to get q tracking for VSI %d, err=%d\n",
6901 vsi->seid, vsi->base_vector);
6902 i40e_vsi_free_q_vectors(vsi);
6903 ret = -ENOENT;
6904 goto vector_setup_out;
6905 }
6906
6907vector_setup_out:
6908 return ret;
6909}
6910
bc7d338f
ASJ		 6911/**
6912 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6913 * @vsi: pointer to the vsi.
6914 *
6915 * This re-allocates a vsi's queue resources.
6916 *
6917 * Returns pointer to the successfully allocated and configured VSI sw struct
6918 * on success, otherwise returns NULL on failure.
6919 **/
6920static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6921{
6922 struct i40e_pf *pf = vsi->back;
6923 u8 enabled_tc;
6924 int ret;
6925
6926 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6927 i40e_vsi_clear_rings(vsi);
6928
6929 i40e_vsi_free_arrays(vsi, false);
6930 i40e_set_num_rings_in_vsi(vsi);
6931 ret = i40e_vsi_alloc_arrays(vsi, false);
6932 if (ret)
6933 goto err_vsi;
6934
6935 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6936 if (ret < 0) {
6937 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6938 vsi->seid, ret);
6939 goto err_vsi;
6940 }
6941 vsi->base_queue = ret;
6942
6943 /* Update the FW view of the VSI. Force a reset of TC and queue
6944 * layout configurations.
6945 */
6946 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6947 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6948 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6949 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6950
6951 /* assign it some queues */
6952 ret = i40e_alloc_rings(vsi);
6953 if (ret)
6954 goto err_rings;
6955
6956 /* map all of the rings to the q_vectors */
6957 i40e_vsi_map_rings_to_vectors(vsi);
6958 return vsi;
6959
6960err_rings:
6961 i40e_vsi_free_q_vectors(vsi);
6962 if (vsi->netdev_registered) {
6963 vsi->netdev_registered = false;
6964 unregister_netdev(vsi->netdev);
6965 free_netdev(vsi->netdev);
6966 vsi->netdev = NULL;
6967 }
6968 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6969err_vsi:
6970 i40e_vsi_clear(vsi);
6971 return NULL;
6972}
6973
41c445ff
JB		 6974/**
6975 * i40e_vsi_setup - Set up a VSI by a given type
6976 * @pf: board private structure
6977 * @type: VSI type
6978 * @uplink_seid: the switch element to link to
6979 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6980 *
6981 * This allocates the sw VSI structure and its queue resources, then add a VSI
6982 * to the identified VEB.
6983 *
6984 * Returns pointer to the successfully allocated and configure VSI sw struct on
6985 * success, otherwise returns NULL on failure.
6986 **/
6987struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6988 u16 uplink_seid, u32 param1)
6989{
6990 struct i40e_vsi *vsi = NULL;
6991 struct i40e_veb *veb = NULL;
6992 int ret, i;
6993 int v_idx;
6994
6995 /* The requested uplink_seid must be either
6996 * - the PF's port seid
6997 * no VEB is needed because this is the PF
6998 * or this is a Flow Director special case VSI
6999 * - seid of an existing VEB
7000 * - seid of a VSI that owns an existing VEB
7001 * - seid of a VSI that doesn't own a VEB
7002 * a new VEB is created and the VSI becomes the owner
7003 * - seid of the PF VSI, which is what creates the first VEB
7004 * this is a special case of the previous
7005 *
7006 * Find which uplink_seid we were given and create a new VEB if needed
7007 */
7008 for (i = 0; i < I40E_MAX_VEB; i++) {
7009 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7010 veb = pf->veb[i];
7011 break;
7012 }
7013 }
7014
7015 if (!veb && uplink_seid != pf->mac_seid) {
7016
7017 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7018 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7019 vsi = pf->vsi[i];
7020 break;
7021 }
7022 }
7023 if (!vsi) {
7024 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7025 uplink_seid);
7026 return NULL;
7027 }
7028
7029 if (vsi->uplink_seid == pf->mac_seid)
7030 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7031 vsi->tc_config.enabled_tc);
7032 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7033 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7034 vsi->tc_config.enabled_tc);
7035
7036 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7037 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7038 veb = pf->veb[i];
7039 }
7040 if (!veb) {
7041 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7042 return NULL;
7043 }
7044
7045 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7046 uplink_seid = veb->seid;
7047 }
7048
7049 /* get vsi sw struct */
7050 v_idx = i40e_vsi_mem_alloc(pf, type);
7051 if (v_idx < 0)
7052 goto err_alloc;
7053 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7054 if (!vsi)
7055 goto err_alloc;
41c445ff
JB		 7056 vsi->type = type;
7057 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7058
7059 if (type == I40E_VSI_MAIN)
7060 pf->lan_vsi = v_idx;
7061 else if (type == I40E_VSI_SRIOV)
7062 vsi->vf_id = param1;
7063 /* assign it some queues */
cbf61325
ASJ		 7064 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7065 vsi->idx);
41c445ff
JB		 7066 if (ret < 0) {
7067 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7068 vsi->seid, ret);
7069 goto err_vsi;
7070 }
7071 vsi->base_queue = ret;
7072
7073 /* get a VSI from the hardware */
7074 vsi->uplink_seid = uplink_seid;
7075 ret = i40e_add_vsi(vsi);
7076 if (ret)
7077 goto err_vsi;
7078
7079 switch (vsi->type) {
7080 /* setup the netdev if needed */
7081 case I40E_VSI_MAIN:
7082 case I40E_VSI_VMDQ2:
7083 ret = i40e_config_netdev(vsi);
7084 if (ret)
7085 goto err_netdev;
7086 ret = register_netdev(vsi->netdev);
7087 if (ret)
7088 goto err_netdev;
7089 vsi->netdev_registered = true;
7090 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7091#ifdef CONFIG_I40E_DCB
7092 /* Setup DCB netlink interface */
7093 i40e_dcbnl_setup(vsi);
7094#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7095 /* fall through */
7096
7097 case I40E_VSI_FDIR:
7098 /* set up vectors and rings if needed */
7099 ret = i40e_vsi_setup_vectors(vsi);
7100 if (ret)
7101 goto err_msix;
7102
7103 ret = i40e_alloc_rings(vsi);
7104 if (ret)
7105 goto err_rings;
7106
7107 /* map all of the rings to the q_vectors */
7108 i40e_vsi_map_rings_to_vectors(vsi);
7109
7110 i40e_vsi_reset_stats(vsi);
7111 break;
7112
7113 default:
7114 /* no netdev or rings for the other VSI types */
7115 break;
7116 }
7117
7118 return vsi;
7119
7120err_rings:
7121 i40e_vsi_free_q_vectors(vsi);
7122err_msix:
7123 if (vsi->netdev_registered) {
7124 vsi->netdev_registered = false;
7125 unregister_netdev(vsi->netdev);
7126 free_netdev(vsi->netdev);
7127 vsi->netdev = NULL;
7128 }
7129err_netdev:
7130 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7131err_vsi:
7132 i40e_vsi_clear(vsi);
7133err_alloc:
7134 return NULL;
7135}
7136
7137/**
7138 * i40e_veb_get_bw_info - Query VEB BW information
7139 * @veb: the veb to query
7140 *
7141 * Query the Tx scheduler BW configuration data for given VEB
7142 **/
7143static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7144{
7145 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7146 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7147 struct i40e_pf *pf = veb->pf;
7148 struct i40e_hw *hw = &pf->hw;
7149 u32 tc_bw_max;
7150 int ret = 0;
7151 int i;
7152
7153 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7154 &bw_data, NULL);
7155 if (ret) {
7156 dev_info(&pf->pdev->dev,
7157 "query veb bw config failed, aq_err=%d\n",
7158 hw->aq.asq_last_status);
7159 goto out;
7160 }
7161
7162 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7163 &ets_data, NULL);
7164 if (ret) {
7165 dev_info(&pf->pdev->dev,
7166 "query veb bw ets config failed, aq_err=%d\n",
7167 hw->aq.asq_last_status);
7168 goto out;
7169 }
7170
7171 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7172 veb->bw_max_quanta = ets_data.tc_bw_max;
7173 veb->is_abs_credits = bw_data.absolute_credits_enable;
7174 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7175 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7176 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7177 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7178 veb->bw_tc_limit_credits[i] =
7179 le16_to_cpu(bw_data.tc_bw_limits[i]);
7180 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7181 }
7182
7183out:
7184 return ret;
7185}
7186
7187/**
7188 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7189 * @pf: board private structure
7190 *
7191 * On error: returns error code (negative)
7192 * On success: returns vsi index in PF (positive)
7193 **/
7194static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7195{
7196 int ret = -ENOENT;
7197 struct i40e_veb *veb;
7198 int i;
7199
7200 /* Need to protect the allocation of switch elements at the PF level */
7201 mutex_lock(&pf->switch_mutex);
7202
7203 /* VEB list may be fragmented if VEB creation/destruction has
7204 * been happening. We can afford to do a quick scan to look
7205 * for any free slots in the list.
7206 *
7207 * find next empty veb slot, looping back around if necessary
7208 */
7209 i = 0;
7210 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7211 i++;
7212 if (i >= I40E_MAX_VEB) {
7213 ret = -ENOMEM;
7214 goto err_alloc_veb; /* out of VEB slots! */
7215 }
7216
7217 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7218 if (!veb) {
7219 ret = -ENOMEM;
7220 goto err_alloc_veb;
7221 }
7222 veb->pf = pf;
7223 veb->idx = i;
7224 veb->enabled_tc = 1;
7225
7226 pf->veb[i] = veb;
7227 ret = i;
7228err_alloc_veb:
7229 mutex_unlock(&pf->switch_mutex);
7230 return ret;
7231}
7232
7233/**
7234 * i40e_switch_branch_release - Delete a branch of the switch tree
7235 * @branch: where to start deleting
7236 *
7237 * This uses recursion to find the tips of the branch to be
7238 * removed, deleting until we get back to and can delete this VEB.
7239 **/
7240static void i40e_switch_branch_release(struct i40e_veb *branch)
7241{
7242 struct i40e_pf *pf = branch->pf;
7243 u16 branch_seid = branch->seid;
7244 u16 veb_idx = branch->idx;
7245 int i;
7246
7247 /* release any VEBs on this VEB - RECURSION */
7248 for (i = 0; i < I40E_MAX_VEB; i++) {
7249 if (!pf->veb[i])
7250 continue;
7251 if (pf->veb[i]->uplink_seid == branch->seid)
7252 i40e_switch_branch_release(pf->veb[i]);
7253 }
7254
7255 /* Release the VSIs on this VEB, but not the owner VSI.
7256 *
7257 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7258 * the VEB itself, so don't use (*branch) after this loop.
7259 */
7260 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7261 if (!pf->vsi[i])
7262 continue;
7263 if (pf->vsi[i]->uplink_seid == branch_seid &&
7264 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7265 i40e_vsi_release(pf->vsi[i]);
7266 }
7267 }
7268
7269 /* There's one corner case where the VEB might not have been
7270 * removed, so double check it here and remove it if needed.
7271 * This case happens if the veb was created from the debugfs
7272 * commands and no VSIs were added to it.
7273 */
7274 if (pf->veb[veb_idx])
7275 i40e_veb_release(pf->veb[veb_idx]);
7276}
7277
7278/**
7279 * i40e_veb_clear - remove veb struct
7280 * @veb: the veb to remove
7281 **/
7282static void i40e_veb_clear(struct i40e_veb *veb)
7283{
7284 if (!veb)
7285 return;
7286
7287 if (veb->pf) {
7288 struct i40e_pf *pf = veb->pf;
7289
7290 mutex_lock(&pf->switch_mutex);
7291 if (pf->veb[veb->idx] == veb)
7292 pf->veb[veb->idx] = NULL;
7293 mutex_unlock(&pf->switch_mutex);
7294 }
7295
7296 kfree(veb);
7297}
7298
7299/**
7300 * i40e_veb_release - Delete a VEB and free its resources
7301 * @veb: the VEB being removed
7302 **/
7303void i40e_veb_release(struct i40e_veb *veb)
7304{
7305 struct i40e_vsi *vsi = NULL;
7306 struct i40e_pf *pf;
7307 int i, n = 0;
7308
7309 pf = veb->pf;
7310
7311 /* find the remaining VSI and check for extras */
7312 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7313 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7314 n++;
7315 vsi = pf->vsi[i];
7316 }
7317 }
7318 if (n != 1) {
7319 dev_info(&pf->pdev->dev,
7320 "can't remove VEB %d with %d VSIs left\n",
7321 veb->seid, n);
7322 return;
7323 }
7324
7325 /* move the remaining VSI to uplink veb */
7326 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7327 if (veb->uplink_seid) {
7328 vsi->uplink_seid = veb->uplink_seid;
7329 if (veb->uplink_seid == pf->mac_seid)
7330 vsi->veb_idx = I40E_NO_VEB;
7331 else
7332 vsi->veb_idx = veb->veb_idx;
7333 } else {
7334 /* floating VEB */
7335 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7336 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7337 }
7338
7339 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7340 i40e_veb_clear(veb);
7341
7342 return;
7343}
7344
7345/**
7346 * i40e_add_veb - create the VEB in the switch
7347 * @veb: the VEB to be instantiated
7348 * @vsi: the controlling VSI
7349 **/
7350static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7351{
56747264 7352 bool is_default = false;
e1c51b95 7353 bool is_cloud = false;
41c445ff
JB		 7354 int ret;
7355
7356 /* get a VEB from the hardware */
7357 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7358 veb->enabled_tc, is_default,
7359 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7360 if (ret) {
7361 dev_info(&veb->pf->pdev->dev,
7362 "couldn't add VEB, err %d, aq_err %d\n",
7363 ret, veb->pf->hw.aq.asq_last_status);
7364 return -EPERM;
7365 }
7366
7367 /* get statistics counter */
7368 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7369 &veb->stats_idx, NULL, NULL, NULL);
7370 if (ret) {
7371 dev_info(&veb->pf->pdev->dev,
7372 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7373 ret, veb->pf->hw.aq.asq_last_status);
7374 return -EPERM;
7375 }
7376 ret = i40e_veb_get_bw_info(veb);
7377 if (ret) {
7378 dev_info(&veb->pf->pdev->dev,
7379 "couldn't get VEB bw info, err %d, aq_err %d\n",
7380 ret, veb->pf->hw.aq.asq_last_status);
7381 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7382 return -ENOENT;
7383 }
7384
7385 vsi->uplink_seid = veb->seid;
7386 vsi->veb_idx = veb->idx;
7387 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7388
7389 return 0;
7390}
7391
7392/**
7393 * i40e_veb_setup - Set up a VEB
7394 * @pf: board private structure
7395 * @flags: VEB setup flags
7396 * @uplink_seid: the switch element to link to
7397 * @vsi_seid: the initial VSI seid
7398 * @enabled_tc: Enabled TC bit-map
7399 *
7400 * This allocates the sw VEB structure and links it into the switch
7401 * It is possible and legal for this to be a duplicate of an already
7402 * existing VEB. It is also possible for both uplink and vsi seids
7403 * to be zero, in order to create a floating VEB.
7404 *
7405 * Returns pointer to the successfully allocated VEB sw struct on
7406 * success, otherwise returns NULL on failure.
7407 **/
7408struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7409 u16 uplink_seid, u16 vsi_seid,
7410 u8 enabled_tc)
7411{
7412 struct i40e_veb *veb, *uplink_veb = NULL;
7413 int vsi_idx, veb_idx;
7414 int ret;
7415
7416 /* if one seid is 0, the other must be 0 to create a floating relay */
7417 if ((uplink_seid == 0 || vsi_seid == 0) &&
7418 (uplink_seid + vsi_seid != 0)) {
7419 dev_info(&pf->pdev->dev,
7420 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7421 uplink_seid, vsi_seid);
7422 return NULL;
7423 }
7424
7425 /* make sure there is such a vsi and uplink */
7426 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7427 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7428 break;
7429 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7430 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7431 vsi_seid);
7432 return NULL;
7433 }
7434
7435 if (uplink_seid && uplink_seid != pf->mac_seid) {
7436 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7437 if (pf->veb[veb_idx] &&
7438 pf->veb[veb_idx]->seid == uplink_seid) {
7439 uplink_veb = pf->veb[veb_idx];
7440 break;
7441 }
7442 }
7443 if (!uplink_veb) {
7444 dev_info(&pf->pdev->dev,
7445 "uplink seid %d not found\n", uplink_seid);
7446 return NULL;
7447 }
7448 }
7449
7450 /* get veb sw struct */
7451 veb_idx = i40e_veb_mem_alloc(pf);
7452 if (veb_idx < 0)
7453 goto err_alloc;
7454 veb = pf->veb[veb_idx];
7455 veb->flags = flags;
7456 veb->uplink_seid = uplink_seid;
7457 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7458 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7459
7460 /* create the VEB in the switch */
7461 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7462 if (ret)
7463 goto err_veb;
7464
7465 return veb;
7466
7467err_veb:
7468 i40e_veb_clear(veb);
7469err_alloc:
7470 return NULL;
7471}
7472
7473/**
7474 * i40e_setup_pf_switch_element - set pf vars based on switch type
7475 * @pf: board private structure
7476 * @ele: element we are building info from
7477 * @num_reported: total number of elements
7478 * @printconfig: should we print the contents
7479 *
7480 * helper function to assist in extracting a few useful SEID values.
7481 **/
7482static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7483 struct i40e_aqc_switch_config_element_resp *ele,
7484 u16 num_reported, bool printconfig)
7485{
7486 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7487 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7488 u8 element_type = ele->element_type;
7489 u16 seid = le16_to_cpu(ele->seid);
7490
7491 if (printconfig)
7492 dev_info(&pf->pdev->dev,
7493 "type=%d seid=%d uplink=%d downlink=%d\n",
7494 element_type, seid, uplink_seid, downlink_seid);
7495
7496 switch (element_type) {
7497 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7498 pf->mac_seid = seid;
7499 break;
7500 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7501 /* Main VEB? */
7502 if (uplink_seid != pf->mac_seid)
7503 break;
7504 if (pf->lan_veb == I40E_NO_VEB) {
7505 int v;
7506
7507 /* find existing or else empty VEB */
7508 for (v = 0; v < I40E_MAX_VEB; v++) {
7509 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7510 pf->lan_veb = v;
7511 break;
7512 }
7513 }
7514 if (pf->lan_veb == I40E_NO_VEB) {
7515 v = i40e_veb_mem_alloc(pf);
7516 if (v < 0)
7517 break;
7518 pf->lan_veb = v;
7519 }
7520 }
7521
7522 pf->veb[pf->lan_veb]->seid = seid;
7523 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7524 pf->veb[pf->lan_veb]->pf = pf;
7525 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7526 break;
7527 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7528 if (num_reported != 1)
7529 break;
7530 /* This is immediately after a reset so we can assume this is
7531 * the PF's VSI
7532 */
7533 pf->mac_seid = uplink_seid;
7534 pf->pf_seid = downlink_seid;
7535 pf->main_vsi_seid = seid;
7536 if (printconfig)
7537 dev_info(&pf->pdev->dev,
7538 "pf_seid=%d main_vsi_seid=%d\n",
7539 pf->pf_seid, pf->main_vsi_seid);
7540 break;
7541 case I40E_SWITCH_ELEMENT_TYPE_PF:
7542 case I40E_SWITCH_ELEMENT_TYPE_VF:
7543 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7544 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7545 case I40E_SWITCH_ELEMENT_TYPE_PE:
7546 case I40E_SWITCH_ELEMENT_TYPE_PA:
7547 /* ignore these for now */
7548 break;
7549 default:
7550 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7551 element_type, seid);
7552 break;
7553 }
7554}
7555
7556/**
7557 * i40e_fetch_switch_configuration - Get switch config from firmware
7558 * @pf: board private structure
7559 * @printconfig: should we print the contents
7560 *
7561 * Get the current switch configuration from the device and
7562 * extract a few useful SEID values.
7563 **/
7564int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7565{
7566 struct i40e_aqc_get_switch_config_resp *sw_config;
7567 u16 next_seid = 0;
7568 int ret = 0;
7569 u8 *aq_buf;
7570 int i;
7571
7572 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7573 if (!aq_buf)
7574 return -ENOMEM;
7575
7576 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7577 do {
7578 u16 num_reported, num_total;
7579
7580 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7581 I40E_AQ_LARGE_BUF,
7582 &next_seid, NULL);
7583 if (ret) {
7584 dev_info(&pf->pdev->dev,
7585 "get switch config failed %d aq_err=%x\n",
7586 ret, pf->hw.aq.asq_last_status);
7587 kfree(aq_buf);
7588 return -ENOENT;
7589 }
7590
7591 num_reported = le16_to_cpu(sw_config->header.num_reported);
7592 num_total = le16_to_cpu(sw_config->header.num_total);
7593
7594 if (printconfig)
7595 dev_info(&pf->pdev->dev,
7596 "header: %d reported %d total\n",
7597 num_reported, num_total);
7598
7599 if (num_reported) {
7600 int sz = sizeof(*sw_config) * num_reported;
7601
7602 kfree(pf->sw_config);
7603 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7604 if (pf->sw_config)
7605 memcpy(pf->sw_config, sw_config, sz);
7606 }
7607
7608 for (i = 0; i < num_reported; i++) {
7609 struct i40e_aqc_switch_config_element_resp *ele =
7610 &sw_config->element[i];
7611
7612 i40e_setup_pf_switch_element(pf, ele, num_reported,
7613 printconfig);
7614 }
7615 } while (next_seid != 0);
7616
7617 kfree(aq_buf);
7618 return ret;
7619}
7620
7621/**
7622 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7623 * @pf: board private structure
bc7d338f 7624 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7625 *
7626 * Returns 0 on success, negative value on failure
7627 **/
bc7d338f 7628static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7629{
895106a5 7630 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7631 int ret;
7632
7633 /* find out what's out there already */
7634 ret = i40e_fetch_switch_configuration(pf, false);
7635 if (ret) {
7636 dev_info(&pf->pdev->dev,
7637 "couldn't fetch switch config, err %d, aq_err %d\n",
7638 ret, pf->hw.aq.asq_last_status);
7639 return ret;
7640 }
7641 i40e_pf_reset_stats(pf);
7642
41c445ff 7643 /* first time setup */
bc7d338f 7644 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7645 struct i40e_vsi *vsi = NULL;
7646 u16 uplink_seid;
7647
7648 /* Set up the PF VSI associated with the PF's main VSI
7649 * that is already in the HW switch
7650 */
7651 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7652 uplink_seid = pf->veb[pf->lan_veb]->seid;
7653 else
7654 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7655 if (pf->lan_vsi == I40E_NO_VSI)
7656 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7657 else if (reinit)
7658 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7659 if (!vsi) {
7660 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7661 i40e_fdir_teardown(pf);
7662 return -EAGAIN;
7663 }
41c445ff
JB		 7664 } else {
7665 /* force a reset of TC and queue layout configurations */
7666 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7667 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7668 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7669 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7670 }
7671 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7672
cbf61325
ASJ		 7673 i40e_fdir_sb_setup(pf);
7674
41c445ff
JB		 7675 /* Setup static PF queue filter control settings */
7676 ret = i40e_setup_pf_filter_control(pf);
7677 if (ret) {
7678 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7679 ret);
7680 /* Failure here should not stop continuing other steps */
7681 }
7682
7683 /* enable RSS in the HW, even for only one queue, as the stack can use
7684 * the hash
7685 */
7686 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7687 i40e_config_rss(pf);
7688
7689 /* fill in link information and enable LSE reporting */
7690 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7691 i40e_link_event(pf);
7692
d52c20b7 7693 /* Initialize user-specific link properties */
41c445ff
JB		 7694 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7695 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7696 /* requested_mode is set in probe or by ethtool */
7697 if (!pf->fc_autoneg_status)
7698 goto no_autoneg;
7699
7700 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7701 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7702 pf->hw.fc.current_mode = I40E_FC_FULL;
7703 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7704 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7705 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7706 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7707 else
d52c20b7
JB		 7708 pf->hw.fc.current_mode = I40E_FC_NONE;
7709
7710 /* sync the flow control settings with the auto-neg values */
7711 switch (pf->hw.fc.current_mode) {
7712 case I40E_FC_FULL:
7713 txfc = 1;
7714 rxfc = 1;
7715 break;
7716 case I40E_FC_TX_PAUSE:
7717 txfc = 1;
7718 rxfc = 0;
7719 break;
7720 case I40E_FC_RX_PAUSE:
7721 txfc = 0;
7722 rxfc = 1;
7723 break;
7724 case I40E_FC_NONE:
7725 case I40E_FC_DEFAULT:
7726 txfc = 0;
7727 rxfc = 0;
7728 break;
7729 case I40E_FC_PFC:
7730 /* TBD */
7731 break;
7732 /* no default case, we have to handle all possibilities here */
7733 }
7734
7735 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7736
7737 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7738 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7739 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7740
7741 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7742
d52c20b7
JB		 7743 goto fc_complete;
7744
7745no_autoneg:
7746 /* disable L2 flow control, user can turn it on if they wish */
7747 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7748 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7749 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7750
7751fc_complete:
beb0dff1
JK		 7752 i40e_ptp_init(pf);
7753
41c445ff
JB		 7754 return ret;
7755}
7756
41c445ff
JB		 7757/**
7758 * i40e_determine_queue_usage - Work out queue distribution
7759 * @pf: board private structure
7760 **/
7761static void i40e_determine_queue_usage(struct i40e_pf *pf)
7762{
41c445ff
JB		 7763 int queues_left;
7764
7765 pf->num_lan_qps = 0;
41c445ff
JB		 7766
7767 /* Find the max queues to be put into basic use. We'll always be
7768 * using TC0, whether or not DCB is running, and TC0 will get the
7769 * big RSS set.
7770 */
7771 queues_left = pf->hw.func_caps.num_tx_qp;
7772
cbf61325
ASJ		 7773 if ((queues_left == 1) ||
7774 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
7775 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
7776 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 7777 /* one qp for PF, no queues for anything else */
7778 queues_left = 0;
7779 pf->rss_size = pf->num_lan_qps = 1;
7780
7781 /* make sure all the fancies are disabled */
60ea5f83
JB		 7782 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
7783 I40E_FLAG_FD_SB_ENABLED |
7784 I40E_FLAG_FD_ATR_ENABLED |
7785 I40E_FLAG_DCB_ENABLED |
7786 I40E_FLAG_SRIOV_ENABLED |
7787 I40E_FLAG_VMDQ_ENABLED);
41c445ff 7788 } else {
cbf61325
ASJ		 7789 /* Not enough queues for all TCs */
7790 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
7791 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
7792 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
7793 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
7794 }
7795 pf->num_lan_qps = pf->rss_size_max;
7796 queues_left -= pf->num_lan_qps;
7797 }
7798
7799 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7800 if (queues_left > 1) {
7801 queues_left -= 1; /* save 1 queue for FD */
7802 } else {
7803 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7804 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
7805 }
41c445ff
JB		 7806 }
7807
7808 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7809 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 7810 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
7811 (queues_left / pf->num_vf_qps));
41c445ff
JB		 7812 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7813 }
7814
7815 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7816 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7817 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7818 (queues_left / pf->num_vmdq_qps));
7819 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7820 }
7821
f8ff1464 7822 pf->queues_left = queues_left;
41c445ff
JB		 7823 return;
7824}
7825
7826/**
7827 * i40e_setup_pf_filter_control - Setup PF static filter control
7828 * @pf: PF to be setup
7829 *
7830 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7831 * settings. If PE/FCoE are enabled then it will also set the per PF
7832 * based filter sizes required for them. It also enables Flow director,
7833 * ethertype and macvlan type filter settings for the pf.
7834 *
7835 * Returns 0 on success, negative on failure
7836 **/
7837static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7838{
7839 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7840
7841 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7842
7843 /* Flow Director is enabled */
60ea5f83 7844 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 7845 settings->enable_fdir = true;
7846
7847 /* Ethtype and MACVLAN filters enabled for PF */
7848 settings->enable_ethtype = true;
7849 settings->enable_macvlan = true;
7850
7851 if (i40e_set_filter_control(&pf->hw, settings))
7852 return -ENOENT;
7853
7854 return 0;
7855}
7856
7857/**
7858 * i40e_probe - Device initialization routine
7859 * @pdev: PCI device information struct
7860 * @ent: entry in i40e_pci_tbl
7861 *
7862 * i40e_probe initializes a pf identified by a pci_dev structure.
7863 * The OS initialization, configuring of the pf private structure,
7864 * and a hardware reset occur.
7865 *
7866 * Returns 0 on success, negative on failure
7867 **/
7868static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7869{
7870 struct i40e_driver_version dv;
7871 struct i40e_pf *pf;
7872 struct i40e_hw *hw;
93cd765b 7873 static u16 pfs_found;
d4dfb81a 7874 u16 link_status;
41c445ff
JB		 7875 int err = 0;
7876 u32 len;
7877
7878 err = pci_enable_device_mem(pdev);
7879 if (err)
7880 return err;
7881
7882 /* set up for high or low dma */
7883 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7884 /* coherent mask for the same size will always succeed if
7885 * dma_set_mask does
7886 */
7887 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7888 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7889 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7890 } else {
7891 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7892 err = -EIO;
7893 goto err_dma;
7894 }
7895
7896 /* set up pci connections */
7897 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7898 IORESOURCE_MEM), i40e_driver_name);
7899 if (err) {
7900 dev_info(&pdev->dev,
7901 "pci_request_selected_regions failed %d\n", err);
7902 goto err_pci_reg;
7903 }
7904
7905 pci_enable_pcie_error_reporting(pdev);
7906 pci_set_master(pdev);
7907
7908 /* Now that we have a PCI connection, we need to do the
7909 * low level device setup. This is primarily setting up
7910 * the Admin Queue structures and then querying for the
7911 * device's current profile information.
7912 */
7913 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7914 if (!pf) {
7915 err = -ENOMEM;
7916 goto err_pf_alloc;
7917 }
7918 pf->next_vsi = 0;
7919 pf->pdev = pdev;
7920 set_bit(__I40E_DOWN, &pf->state);
7921
7922 hw = &pf->hw;
7923 hw->back = pf;
7924 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7925 pci_resource_len(pdev, 0));
7926 if (!hw->hw_addr) {
7927 err = -EIO;
7928 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7929 (unsigned int)pci_resource_start(pdev, 0),
7930 (unsigned int)pci_resource_len(pdev, 0), err);
7931 goto err_ioremap;
7932 }
7933 hw->vendor_id = pdev->vendor;
7934 hw->device_id = pdev->device;
7935 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7936 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7937 hw->subsystem_device_id = pdev->subsystem_device;
7938 hw->bus.device = PCI_SLOT(pdev->devfn);
7939 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7940 pf->instance = pfs_found;
41c445ff 7941
7134f9ce
JB		 7942 /* do a special CORER for clearing PXE mode once at init */
7943 if (hw->revision_id == 0 &&
7944 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7945 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7946 i40e_flush(hw);
7947 msleep(200);
7948 pf->corer_count++;
7949
7950 i40e_clear_pxe_mode(hw);
7951 }
7952
41c445ff
JB		 7953 /* Reset here to make sure all is clean and to define PF 'n' */
7954 err = i40e_pf_reset(hw);
7955 if (err) {
7956 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7957 goto err_pf_reset;
7958 }
7959 pf->pfr_count++;
7960
7961 hw->aq.num_arq_entries = I40E_AQ_LEN;
7962 hw->aq.num_asq_entries = I40E_AQ_LEN;
7963 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7964 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7965 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7966 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7967 "%s-pf%d:misc",
7968 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7969
7970 err = i40e_init_shared_code(hw);
7971 if (err) {
7972 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7973 goto err_pf_reset;
7974 }
7975
d52c20b7
JB		 7976 /* set up a default setting for link flow control */
7977 pf->hw.fc.requested_mode = I40E_FC_NONE;
7978
41c445ff
JB		 7979 err = i40e_init_adminq(hw);
7980 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7981 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7982 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7983 dev_info(&pdev->dev,
7984 "warning: NVM version not supported, supported version: %02x.%02x\n",
7985 I40E_CURRENT_NVM_VERSION_HI,
7986 I40E_CURRENT_NVM_VERSION_LO);
7987 }
41c445ff
JB		 7988 if (err) {
7989 dev_info(&pdev->dev,
7990 "init_adminq failed: %d expecting API %02x.%02x\n",
7991 err,
7992 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7993 goto err_pf_reset;
7994 }
7995
6ff4ef86 7996 i40e_clear_pxe_mode(hw);
41c445ff
JB		 7997 err = i40e_get_capabilities(pf);
7998 if (err)
7999 goto err_adminq_setup;
8000
8001 err = i40e_sw_init(pf);
8002 if (err) {
8003 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8004 goto err_sw_init;
8005 }
8006
8007 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8008 hw->func_caps.num_rx_qp,
8009 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8010 if (err) {
8011 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8012 goto err_init_lan_hmc;
8013 }
8014
8015 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8016 if (err) {
8017 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8018 err = -ENOENT;
8019 goto err_configure_lan_hmc;
8020 }
8021
8022 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8023 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8024 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8025 err = -EIO;
8026 goto err_mac_addr;
8027 }
8028 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8029 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8030
8031 pci_set_drvdata(pdev, pf);
8032 pci_save_state(pdev);
4e3b35b0
NP		 8033#ifdef CONFIG_I40E_DCB
8034 err = i40e_init_pf_dcb(pf);
8035 if (err) {
8036 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8037 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8038 goto err_init_dcb;
8039 }
8040#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8041
8042 /* set up periodic task facility */
8043 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8044 pf->service_timer_period = HZ;
8045
8046 INIT_WORK(&pf->service_task, i40e_service_task);
8047 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8048 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8049 pf->link_check_timeout = jiffies;
8050
8e2773ae
SN		 8051 /* WoL defaults to disabled */
8052 pf->wol_en = false;
8053 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8054
41c445ff
JB		 8055 /* set up the main switch operations */
8056 i40e_determine_queue_usage(pf);
8057 i40e_init_interrupt_scheme(pf);
8058
8059 /* Set up the *vsi struct based on the number of VSIs in the HW,
8060 * and set up our local tracking of the MAIN PF vsi.
8061 */
8062 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8063 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8064 if (!pf->vsi) {
8065 err = -ENOMEM;
41c445ff 8066 goto err_switch_setup;
ed87ac09 8067 }
41c445ff 8068
bc7d338f 8069 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8070 if (err) {
8071 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8072 goto err_vsis;
8073 }
8074
8075 /* The main driver is (mostly) up and happy. We need to set this state
8076 * before setting up the misc vector or we get a race and the vector
8077 * ends up disabled forever.
8078 */
8079 clear_bit(__I40E_DOWN, &pf->state);
8080
8081 /* In case of MSIX we are going to setup the misc vector right here
8082 * to handle admin queue events etc. In case of legacy and MSI
8083 * the misc functionality and queue processing is combined in
8084 * the same vector and that gets setup at open.
8085 */
8086 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8087 err = i40e_setup_misc_vector(pf);
8088 if (err) {
8089 dev_info(&pdev->dev,
8090 "setup of misc vector failed: %d\n", err);
8091 goto err_vsis;
8092 }
8093 }
8094
8095 /* prep for VF support */
8096 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8097 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
8098 u32 val;
8099
8100 /* disable link interrupts for VFs */
8101 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8102 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8103 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8104 i40e_flush(hw);
4aeec010
MW		 8105
8106 if (pci_num_vf(pdev)) {
8107 dev_info(&pdev->dev,
8108 "Active VFs found, allocating resources.\n");
8109 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8110 if (err)
8111 dev_info(&pdev->dev,
8112 "Error %d allocating resources for existing VFs\n",
8113 err);
8114 }
41c445ff
JB		 8115 }
8116
93cd765b
ASJ		 8117 pfs_found++;
8118
41c445ff
JB		 8119 i40e_dbg_pf_init(pf);
8120
8121 /* tell the firmware that we're starting */
8122 dv.major_version = DRV_VERSION_MAJOR;
8123 dv.minor_version = DRV_VERSION_MINOR;
8124 dv.build_version = DRV_VERSION_BUILD;
8125 dv.subbuild_version = 0;
8126 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8127
8128 /* since everything's happy, start the service_task timer */
8129 mod_timer(&pf->service_timer,
8130 round_jiffies(jiffies + pf->service_timer_period));
8131
d4dfb81a
CS		 8132 /* Get the negotiated link width and speed from PCI config space */
8133 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8134
8135 i40e_set_pci_config_data(hw, link_status);
8136
8137 dev_info(&pdev->dev, "PCI Express: %s %s\n",
8138 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8139 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8140 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8141 "Unknown"),
8142 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8143 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8144 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8145 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8146 "Unknown"));
8147
8148 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8149 hw->bus.speed < i40e_bus_speed_8000) {
8150 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8151 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8152 }
8153
41c445ff
JB		 8154 return 0;
8155
8156 /* Unwind what we've done if something failed in the setup */
8157err_vsis:
8158 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8159 i40e_clear_interrupt_scheme(pf);
8160 kfree(pf->vsi);
04b03013
SN		 8161err_switch_setup:
8162 i40e_reset_interrupt_capability(pf);
41c445ff 8163 del_timer_sync(&pf->service_timer);
4e3b35b0
NP		 8164#ifdef CONFIG_I40E_DCB
8165err_init_dcb:
8166#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8167err_mac_addr:
8168err_configure_lan_hmc:
8169 (void)i40e_shutdown_lan_hmc(hw);
8170err_init_lan_hmc:
8171 kfree(pf->qp_pile);
8172 kfree(pf->irq_pile);
8173err_sw_init:
8174err_adminq_setup:
8175 (void)i40e_shutdown_adminq(hw);
8176err_pf_reset:
8177 iounmap(hw->hw_addr);
8178err_ioremap:
8179 kfree(pf);
8180err_pf_alloc:
8181 pci_disable_pcie_error_reporting(pdev);
8182 pci_release_selected_regions(pdev,
8183 pci_select_bars(pdev, IORESOURCE_MEM));
8184err_pci_reg:
8185err_dma:
8186 pci_disable_device(pdev);
8187 return err;
8188}
8189
8190/**
8191 * i40e_remove - Device removal routine
8192 * @pdev: PCI device information struct
8193 *
8194 * i40e_remove is called by the PCI subsystem to alert the driver
8195 * that is should release a PCI device. This could be caused by a
8196 * Hot-Plug event, or because the driver is going to be removed from
8197 * memory.
8198 **/
8199static void i40e_remove(struct pci_dev *pdev)
8200{
8201 struct i40e_pf *pf = pci_get_drvdata(pdev);
8202 i40e_status ret_code;
8203 u32 reg;
8204 int i;
8205
8206 i40e_dbg_pf_exit(pf);
8207
beb0dff1
JK		 8208 i40e_ptp_stop(pf);
8209
41c445ff
JB		 8210 /* no more scheduling of any task */
8211 set_bit(__I40E_DOWN, &pf->state);
8212 del_timer_sync(&pf->service_timer);
8213 cancel_work_sync(&pf->service_task);
8214
eb2d80bc
MW		 8215 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8216 i40e_free_vfs(pf);
8217 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8218 }
8219
41c445ff
JB		 8220 i40e_fdir_teardown(pf);
8221
8222 /* If there is a switch structure or any orphans, remove them.
8223 * This will leave only the PF's VSI remaining.
8224 */
8225 for (i = 0; i < I40E_MAX_VEB; i++) {
8226 if (!pf->veb[i])
8227 continue;
8228
8229 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8230 pf->veb[i]->uplink_seid == 0)
8231 i40e_switch_branch_release(pf->veb[i]);
8232 }
8233
8234 /* Now we can shutdown the PF's VSI, just before we kill
8235 * adminq and hmc.
8236 */
8237 if (pf->vsi[pf->lan_vsi])
8238 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8239
8240 i40e_stop_misc_vector(pf);
8241 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8242 synchronize_irq(pf->msix_entries[0].vector);
8243 free_irq(pf->msix_entries[0].vector, pf);
8244 }
8245
8246 /* shutdown and destroy the HMC */
8247 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8248 if (ret_code)
8249 dev_warn(&pdev->dev,
8250 "Failed to destroy the HMC resources: %d\n", ret_code);
8251
8252 /* shutdown the adminq */
41c445ff
JB		 8253 ret_code = i40e_shutdown_adminq(&pf->hw);
8254 if (ret_code)
8255 dev_warn(&pdev->dev,
8256 "Failed to destroy the Admin Queue resources: %d\n",
8257 ret_code);
8258
8259 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8260 i40e_clear_interrupt_scheme(pf);
8261 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8262 if (pf->vsi[i]) {
8263 i40e_vsi_clear_rings(pf->vsi[i]);
8264 i40e_vsi_clear(pf->vsi[i]);
8265 pf->vsi[i] = NULL;
8266 }
8267 }
8268
8269 for (i = 0; i < I40E_MAX_VEB; i++) {
8270 kfree(pf->veb[i]);
8271 pf->veb[i] = NULL;
8272 }
8273
8274 kfree(pf->qp_pile);
8275 kfree(pf->irq_pile);
8276 kfree(pf->sw_config);
8277 kfree(pf->vsi);
8278
8279 /* force a PF reset to clean anything leftover */
8280 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8281 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8282 i40e_flush(&pf->hw);
8283
8284 iounmap(pf->hw.hw_addr);
8285 kfree(pf);
8286 pci_release_selected_regions(pdev,
8287 pci_select_bars(pdev, IORESOURCE_MEM));
8288
8289 pci_disable_pcie_error_reporting(pdev);
8290 pci_disable_device(pdev);
8291}
8292
8293/**
8294 * i40e_pci_error_detected - warning that something funky happened in PCI land
8295 * @pdev: PCI device information struct
8296 *
8297 * Called to warn that something happened and the error handling steps
8298 * are in progress. Allows the driver to quiesce things, be ready for
8299 * remediation.
8300 **/
8301static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8302 enum pci_channel_state error)
8303{
8304 struct i40e_pf *pf = pci_get_drvdata(pdev);
8305
8306 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8307
8308 /* shutdown all operations */
9007bccd
SN		 8309 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8310 rtnl_lock();
8311 i40e_prep_for_reset(pf);
8312 rtnl_unlock();
8313 }
41c445ff
JB		 8314
8315 /* Request a slot reset */
8316 return PCI_ERS_RESULT_NEED_RESET;
8317}
8318
8319/**
8320 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8321 * @pdev: PCI device information struct
8322 *
8323 * Called to find if the driver can work with the device now that
8324 * the pci slot has been reset. If a basic connection seems good
8325 * (registers are readable and have sane content) then return a
8326 * happy little PCI_ERS_RESULT_xxx.
8327 **/
8328static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8329{
8330 struct i40e_pf *pf = pci_get_drvdata(pdev);
8331 pci_ers_result_t result;
8332 int err;
8333 u32 reg;
8334
8335 dev_info(&pdev->dev, "%s\n", __func__);
8336 if (pci_enable_device_mem(pdev)) {
8337 dev_info(&pdev->dev,
8338 "Cannot re-enable PCI device after reset.\n");
8339 result = PCI_ERS_RESULT_DISCONNECT;
8340 } else {
8341 pci_set_master(pdev);
8342 pci_restore_state(pdev);
8343 pci_save_state(pdev);
8344 pci_wake_from_d3(pdev, false);
8345
8346 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8347 if (reg == 0)
8348 result = PCI_ERS_RESULT_RECOVERED;
8349 else
8350 result = PCI_ERS_RESULT_DISCONNECT;
8351 }
8352
8353 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8354 if (err) {
8355 dev_info(&pdev->dev,
8356 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8357 err);
8358 /* non-fatal, continue */
8359 }
8360
8361 return result;
8362}
8363
8364/**
8365 * i40e_pci_error_resume - restart operations after PCI error recovery
8366 * @pdev: PCI device information struct
8367 *
8368 * Called to allow the driver to bring things back up after PCI error
8369 * and/or reset recovery has finished.
8370 **/
8371static void i40e_pci_error_resume(struct pci_dev *pdev)
8372{
8373 struct i40e_pf *pf = pci_get_drvdata(pdev);
8374
8375 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8376 if (test_bit(__I40E_SUSPENDED, &pf->state))
8377 return;
8378
8379 rtnl_lock();
41c445ff 8380 i40e_handle_reset_warning(pf);
9007bccd
SN		 8381 rtnl_lock();
8382}
8383
8384/**
8385 * i40e_shutdown - PCI callback for shutting down
8386 * @pdev: PCI device information struct
8387 **/
8388static void i40e_shutdown(struct pci_dev *pdev)
8389{
8390 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8391 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8392
8393 set_bit(__I40E_SUSPENDED, &pf->state);
8394 set_bit(__I40E_DOWN, &pf->state);
8395 rtnl_lock();
8396 i40e_prep_for_reset(pf);
8397 rtnl_unlock();
8398
8e2773ae
SN		 8399 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8400 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8401
9007bccd 8402 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8403 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8404 pci_set_power_state(pdev, PCI_D3hot);
8405 }
8406}
8407
8408#ifdef CONFIG_PM
8409/**
8410 * i40e_suspend - PCI callback for moving to D3
8411 * @pdev: PCI device information struct
8412 **/
8413static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8414{
8415 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8416 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8417
8418 set_bit(__I40E_SUSPENDED, &pf->state);
8419 set_bit(__I40E_DOWN, &pf->state);
8420 rtnl_lock();
8421 i40e_prep_for_reset(pf);
8422 rtnl_unlock();
8423
8e2773ae
SN		 8424 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8425 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8426
8427 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8428 pci_set_power_state(pdev, PCI_D3hot);
8429
8430 return 0;
41c445ff
JB		 8431}
8432
9007bccd
SN		 8433/**
8434 * i40e_resume - PCI callback for waking up from D3
8435 * @pdev: PCI device information struct
8436 **/
8437static int i40e_resume(struct pci_dev *pdev)
8438{
8439 struct i40e_pf *pf = pci_get_drvdata(pdev);
8440 u32 err;
8441
8442 pci_set_power_state(pdev, PCI_D0);
8443 pci_restore_state(pdev);
8444 /* pci_restore_state() clears dev->state_saves, so
8445 * call pci_save_state() again to restore it.
8446 */
8447 pci_save_state(pdev);
8448
8449 err = pci_enable_device_mem(pdev);
8450 if (err) {
8451 dev_err(&pdev->dev,
8452 "%s: Cannot enable PCI device from suspend\n",
8453 __func__);
8454 return err;
8455 }
8456 pci_set_master(pdev);
8457
8458 /* no wakeup events while running */
8459 pci_wake_from_d3(pdev, false);
8460
8461 /* handling the reset will rebuild the device state */
8462 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8463 clear_bit(__I40E_DOWN, &pf->state);
8464 rtnl_lock();
8465 i40e_reset_and_rebuild(pf, false);
8466 rtnl_unlock();
8467 }
8468
8469 return 0;
8470}
8471
8472#endif
41c445ff
JB		 8473static const struct pci_error_handlers i40e_err_handler = {
8474 .error_detected = i40e_pci_error_detected,
8475 .slot_reset = i40e_pci_error_slot_reset,
8476 .resume = i40e_pci_error_resume,
8477};
8478
8479static struct pci_driver i40e_driver = {
8480 .name = i40e_driver_name,
8481 .id_table = i40e_pci_tbl,
8482 .probe = i40e_probe,
8483 .remove = i40e_remove,
9007bccd
SN		 8484#ifdef CONFIG_PM
8485 .suspend = i40e_suspend,
8486 .resume = i40e_resume,
8487#endif
8488 .shutdown = i40e_shutdown,
41c445ff
JB		 8489 .err_handler = &i40e_err_handler,
8490 .sriov_configure = i40e_pci_sriov_configure,
8491};
8492
8493/**
8494 * i40e_init_module - Driver registration routine
8495 *
8496 * i40e_init_module is the first routine called when the driver is
8497 * loaded. All it does is register with the PCI subsystem.
8498 **/
8499static int __init i40e_init_module(void)
8500{
8501 pr_info("%s: %s - version %s\n", i40e_driver_name,
8502 i40e_driver_string, i40e_driver_version_str);
8503 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8504 i40e_dbg_init();
8505 return pci_register_driver(&i40e_driver);
8506}
8507module_init(i40e_init_module);
8508
8509/**
8510 * i40e_exit_module - Driver exit cleanup routine
8511 *
8512 * i40e_exit_module is called just before the driver is removed
8513 * from memory.
8514 **/
8515static void __exit i40e_exit_module(void)
8516{
8517 pci_unregister_driver(&i40e_driver);
8518 i40e_dbg_exit();
8519}
8520module_exit(i40e_exit_module);
Linux kernel - Deliverables
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