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i40e: Fix scheduling while atomic bug during NAPI
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
e454d6bf 41#define DRV_VERSION_MINOR 4
f8320902 42#define DRV_VERSION_BUILD 10
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
b5d06f05
NP		 307 set_bit(__I40E_DOWN_REQUESTED, &pf->state);
308 set_bit(__I40E_DOWN_REQUESTED, &vsi->state);
41c445ff
JB		 309 break;
310 }
311 i40e_service_event_schedule(pf);
312 pf->tx_timeout_recovery_level++;
313}
314
315/**
316 * i40e_release_rx_desc - Store the new tail and head values
317 * @rx_ring: ring to bump
318 * @val: new head index
319 **/
320static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
321{
322 rx_ring->next_to_use = val;
323
324 /* Force memory writes to complete before letting h/w
325 * know there are new descriptors to fetch. (Only
326 * applicable for weak-ordered memory model archs,
327 * such as IA-64).
328 */
329 wmb();
330 writel(val, rx_ring->tail);
331}
332
333/**
334 * i40e_get_vsi_stats_struct - Get System Network Statistics
335 * @vsi: the VSI we care about
336 *
337 * Returns the address of the device statistics structure.
338 * The statistics are actually updated from the service task.
339 **/
340struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
341{
342 return &vsi->net_stats;
343}
344
345/**
346 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
347 * @netdev: network interface device structure
348 *
349 * Returns the address of the device statistics structure.
350 * The statistics are actually updated from the service task.
351 **/
352static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
353 struct net_device *netdev,
980e9b11 354 struct rtnl_link_stats64 *stats)
41c445ff
JB		 355{
356 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 357 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
57a7744e 378 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
57a7744e 381 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
a5282f44 398 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 426 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 436 }
8e9dca53 437 }
41c445ff
JB		 438 vsi->stat_offsets_loaded = false;
439}
440
441/**
442 * i40e_pf_reset_stats - Reset all of the stats for the given pf
443 * @pf: the PF to be reset
444 **/
445void i40e_pf_reset_stats(struct i40e_pf *pf)
446{
447 memset(&pf->stats, 0, sizeof(pf->stats));
448 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
449 pf->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_stat_update48 - read and update a 48 bit stat from the chip
454 * @hw: ptr to the hardware info
455 * @hireg: the high 32 bit reg to read
456 * @loreg: the low 32 bit reg to read
457 * @offset_loaded: has the initial offset been loaded yet
458 * @offset: ptr to current offset value
459 * @stat: ptr to the stat
460 *
461 * Since the device stats are not reset at PFReset, they likely will not
462 * be zeroed when the driver starts. We'll save the first values read
463 * and use them as offsets to be subtracted from the raw values in order
464 * to report stats that count from zero. In the process, we also manage
465 * the potential roll-over.
466 **/
467static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
468 bool offset_loaded, u64 *offset, u64 *stat)
469{
470 u64 new_data;
471
ab60085e 472 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 473 new_data = rd32(hw, loreg);
474 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
475 } else {
476 new_data = rd64(hw, loreg);
477 }
478 if (!offset_loaded)
479 *offset = new_data;
480 if (likely(new_data >= *offset))
481 *stat = new_data - *offset;
482 else
483 *stat = (new_data + ((u64)1 << 48)) - *offset;
484 *stat &= 0xFFFFFFFFFFFFULL;
485}
486
487/**
488 * i40e_stat_update32 - read and update a 32 bit stat from the chip
489 * @hw: ptr to the hardware info
490 * @reg: the hw reg to read
491 * @offset_loaded: has the initial offset been loaded yet
492 * @offset: ptr to current offset value
493 * @stat: ptr to the stat
494 **/
495static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
496 bool offset_loaded, u64 *offset, u64 *stat)
497{
498 u32 new_data;
499
500 new_data = rd32(hw, reg);
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = (u32)(new_data - *offset);
505 else
506 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
507}
508
509/**
510 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
511 * @vsi: the VSI to be updated
512 **/
513void i40e_update_eth_stats(struct i40e_vsi *vsi)
514{
515 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
516 struct i40e_pf *pf = vsi->back;
517 struct i40e_hw *hw = &pf->hw;
518 struct i40e_eth_stats *oes;
519 struct i40e_eth_stats *es; /* device's eth stats */
520
521 es = &vsi->eth_stats;
522 oes = &vsi->eth_stats_offsets;
523
524 /* Gather up the stats that the hw collects */
525 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
526 vsi->stat_offsets_loaded,
527 &oes->tx_errors, &es->tx_errors);
528 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
529 vsi->stat_offsets_loaded,
530 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 531 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
532 vsi->stat_offsets_loaded,
533 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
534 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 537
538 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
539 I40E_GLV_GORCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_bytes, &es->rx_bytes);
542 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
543 I40E_GLV_UPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_unicast, &es->rx_unicast);
546 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
547 I40E_GLV_MPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_multicast, &es->rx_multicast);
550 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
551 I40E_GLV_BPRCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_broadcast, &es->rx_broadcast);
554
555 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
556 I40E_GLV_GOTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_bytes, &es->tx_bytes);
559 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
560 I40E_GLV_UPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_unicast, &es->tx_unicast);
563 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
564 I40E_GLV_MPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_multicast, &es->tx_multicast);
567 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
568 I40E_GLV_BPTCL(stat_idx),
569 vsi->stat_offsets_loaded,
570 &oes->tx_broadcast, &es->tx_broadcast);
571 vsi->stat_offsets_loaded = true;
572}
573
574/**
575 * i40e_update_veb_stats - Update Switch component statistics
576 * @veb: the VEB being updated
577 **/
578static void i40e_update_veb_stats(struct i40e_veb *veb)
579{
580 struct i40e_pf *pf = veb->pf;
581 struct i40e_hw *hw = &pf->hw;
582 struct i40e_eth_stats *oes;
583 struct i40e_eth_stats *es; /* device's eth stats */
584 int idx = 0;
585
586 idx = veb->stats_idx;
587 es = &veb->stats;
588 oes = &veb->stats_offsets;
589
590 /* Gather up the stats that the hw collects */
591 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
592 veb->stat_offsets_loaded,
593 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 594 if (hw->revision_id > 0)
595 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unknown_protocol,
598 &es->rx_unknown_protocol);
41c445ff
JB		 599 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
600 veb->stat_offsets_loaded,
601 &oes->rx_bytes, &es->rx_bytes);
602 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
603 veb->stat_offsets_loaded,
604 &oes->rx_unicast, &es->rx_unicast);
605 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->rx_multicast, &es->rx_multicast);
608 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->rx_broadcast, &es->rx_broadcast);
611
612 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
613 veb->stat_offsets_loaded,
614 &oes->tx_bytes, &es->tx_bytes);
615 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
616 veb->stat_offsets_loaded,
617 &oes->tx_unicast, &es->tx_unicast);
618 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
619 veb->stat_offsets_loaded,
620 &oes->tx_multicast, &es->tx_multicast);
621 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
622 veb->stat_offsets_loaded,
623 &oes->tx_broadcast, &es->tx_broadcast);
624 veb->stat_offsets_loaded = true;
625}
626
627/**
628 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
629 * @pf: the corresponding PF
630 *
631 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
632 **/
633static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
634{
635 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
636 struct i40e_hw_port_stats *nsd = &pf->stats;
637 struct i40e_hw *hw = &pf->hw;
638 u64 xoff = 0;
639 u16 i, v;
640
641 if ((hw->fc.current_mode != I40E_FC_FULL) &&
642 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
643 return;
644
645 xoff = nsd->link_xoff_rx;
646 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
647 pf->stat_offsets_loaded,
648 &osd->link_xoff_rx, &nsd->link_xoff_rx);
649
650 /* No new LFC xoff rx */
651 if (!(nsd->link_xoff_rx - xoff))
652 return;
653
654 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 655 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 656 struct i40e_vsi *vsi = pf->vsi[v];
657
ddfda80f 658 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 659 continue;
660
661 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 662 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 663 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
664 }
665 }
666}
667
668/**
669 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
670 * @pf: the corresponding PF
671 *
672 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
673 **/
674static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
675{
676 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
677 struct i40e_hw_port_stats *nsd = &pf->stats;
678 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
679 struct i40e_dcbx_config *dcb_cfg;
680 struct i40e_hw *hw = &pf->hw;
681 u16 i, v;
682 u8 tc;
683
684 dcb_cfg = &hw->local_dcbx_config;
685
686 /* See if DCB enabled with PFC TC */
687 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
688 !(dcb_cfg->pfc.pfcenable)) {
689 i40e_update_link_xoff_rx(pf);
690 return;
691 }
692
693 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
694 u64 prio_xoff = nsd->priority_xoff_rx[i];
695 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
696 pf->stat_offsets_loaded,
697 &osd->priority_xoff_rx[i],
698 &nsd->priority_xoff_rx[i]);
699
700 /* No new PFC xoff rx */
701 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
702 continue;
703 /* Get the TC for given priority */
704 tc = dcb_cfg->etscfg.prioritytable[i];
705 xoff[tc] = true;
706 }
707
708 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 709 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 710 struct i40e_vsi *vsi = pf->vsi[v];
711
ddfda80f 712 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 713 continue;
714
715 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 716 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 717
718 tc = ring->dcb_tc;
719 if (xoff[tc])
720 clear_bit(__I40E_HANG_CHECK_ARMED,
721 &ring->state);
722 }
723 }
724}
725
726/**
7812fddc 727 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 728 * @vsi: the VSI to be updated
729 *
730 * There are a few instances where we store the same stat in a
731 * couple of different structs. This is partly because we have
732 * the netdev stats that need to be filled out, which is slightly
733 * different from the "eth_stats" defined by the chip and used in
7812fddc 734 * VF communications. We sort it out here.
41c445ff 735 **/
7812fddc 736static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 737{
738 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 739 struct rtnl_link_stats64 *ons;
740 struct rtnl_link_stats64 *ns; /* netdev stats */
741 struct i40e_eth_stats *oes;
742 struct i40e_eth_stats *es; /* device's eth stats */
743 u32 tx_restart, tx_busy;
744 u32 rx_page, rx_buf;
745 u64 rx_p, rx_b;
746 u64 tx_p, tx_b;
41c445ff
JB		 747 u16 q;
748
749 if (test_bit(__I40E_DOWN, &vsi->state) ||
750 test_bit(__I40E_CONFIG_BUSY, &pf->state))
751 return;
752
753 ns = i40e_get_vsi_stats_struct(vsi);
754 ons = &vsi->net_stats_offsets;
755 es = &vsi->eth_stats;
756 oes = &vsi->eth_stats_offsets;
757
758 /* Gather up the netdev and vsi stats that the driver collects
759 * on the fly during packet processing
760 */
761 rx_b = rx_p = 0;
762 tx_b = tx_p = 0;
763 tx_restart = tx_busy = 0;
764 rx_page = 0;
765 rx_buf = 0;
980e9b11 766 rcu_read_lock();
41c445ff
JB		 767 for (q = 0; q < vsi->num_queue_pairs; q++) {
768 struct i40e_ring *p;
980e9b11
AD		 769 u64 bytes, packets;
770 unsigned int start;
771
772 /* locate Tx ring */
773 p = ACCESS_ONCE(vsi->tx_rings[q]);
774
775 do {
57a7744e 776 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 777 packets = p->stats.packets;
778 bytes = p->stats.bytes;
57a7744e 779 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 780 tx_b += bytes;
781 tx_p += packets;
782 tx_restart += p->tx_stats.restart_queue;
783 tx_busy += p->tx_stats.tx_busy;
41c445ff 784
980e9b11
AD		 785 /* Rx queue is part of the same block as Tx queue */
786 p = &p[1];
787 do {
57a7744e 788 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 789 packets = p->stats.packets;
790 bytes = p->stats.bytes;
57a7744e 791 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 792 rx_b += bytes;
793 rx_p += packets;
420136cc
MW		 794 rx_buf += p->rx_stats.alloc_buff_failed;
795 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 796 }
980e9b11 797 rcu_read_unlock();
41c445ff
JB		 798 vsi->tx_restart = tx_restart;
799 vsi->tx_busy = tx_busy;
800 vsi->rx_page_failed = rx_page;
801 vsi->rx_buf_failed = rx_buf;
802
803 ns->rx_packets = rx_p;
804 ns->rx_bytes = rx_b;
805 ns->tx_packets = tx_p;
806 ns->tx_bytes = tx_b;
807
41c445ff 808 /* update netdev stats from eth stats */
7812fddc 809 i40e_update_eth_stats(vsi);
41c445ff
JB		 810 ons->tx_errors = oes->tx_errors;
811 ns->tx_errors = es->tx_errors;
812 ons->multicast = oes->rx_multicast;
813 ns->multicast = es->rx_multicast;
41a9e55c
SN		 814 ons->rx_dropped = oes->rx_discards;
815 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 816 ons->tx_dropped = oes->tx_discards;
817 ns->tx_dropped = es->tx_discards;
818
7812fddc 819 /* pull in a couple PF stats if this is the main vsi */
41c445ff 820 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 821 ns->rx_crc_errors = pf->stats.crc_errors;
822 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
823 ns->rx_length_errors = pf->stats.rx_length_errors;
824 }
825}
41c445ff 826
7812fddc
SN		 827/**
828 * i40e_update_pf_stats - Update the pf statistics counters.
829 * @pf: the PF to be updated
830 **/
831static void i40e_update_pf_stats(struct i40e_pf *pf)
832{
833 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
834 struct i40e_hw_port_stats *nsd = &pf->stats;
835 struct i40e_hw *hw = &pf->hw;
836 u32 val;
837 int i;
41c445ff 838
7812fddc
SN		 839 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
840 I40E_GLPRT_GORCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
843 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
844 I40E_GLPRT_GOTCL(hw->port),
845 pf->stat_offsets_loaded,
846 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
847 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
848 pf->stat_offsets_loaded,
849 &osd->eth.rx_discards,
850 &nsd->eth.rx_discards);
851 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->eth.tx_discards,
854 &nsd->eth.tx_discards);
41c445ff 855
532d283d
SN		 856 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
857 I40E_GLPRT_UPRCL(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->eth.rx_unicast,
860 &nsd->eth.rx_unicast);
7812fddc
SN		 861 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
862 I40E_GLPRT_MPRCL(hw->port),
863 pf->stat_offsets_loaded,
864 &osd->eth.rx_multicast,
865 &nsd->eth.rx_multicast);
532d283d
SN		 866 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
867 I40E_GLPRT_BPRCL(hw->port),
868 pf->stat_offsets_loaded,
869 &osd->eth.rx_broadcast,
870 &nsd->eth.rx_broadcast);
871 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
872 I40E_GLPRT_UPTCL(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->eth.tx_unicast,
875 &nsd->eth.tx_unicast);
876 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
877 I40E_GLPRT_MPTCL(hw->port),
878 pf->stat_offsets_loaded,
879 &osd->eth.tx_multicast,
880 &nsd->eth.tx_multicast);
881 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
882 I40E_GLPRT_BPTCL(hw->port),
883 pf->stat_offsets_loaded,
884 &osd->eth.tx_broadcast,
885 &nsd->eth.tx_broadcast);
41c445ff 886
7812fddc
SN		 887 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
888 pf->stat_offsets_loaded,
889 &osd->tx_dropped_link_down,
890 &nsd->tx_dropped_link_down);
41c445ff 891
7812fddc
SN		 892 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
893 pf->stat_offsets_loaded,
894 &osd->crc_errors, &nsd->crc_errors);
41c445ff 895
7812fddc
SN		 896 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
897 pf->stat_offsets_loaded,
898 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 899
7812fddc
SN		 900 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
901 pf->stat_offsets_loaded,
902 &osd->mac_local_faults,
903 &nsd->mac_local_faults);
904 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->mac_remote_faults,
907 &nsd->mac_remote_faults);
41c445ff 908
7812fddc
SN		 909 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
910 pf->stat_offsets_loaded,
911 &osd->rx_length_errors,
912 &nsd->rx_length_errors);
41c445ff 913
7812fddc
SN		 914 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
915 pf->stat_offsets_loaded,
916 &osd->link_xon_rx, &nsd->link_xon_rx);
917 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->link_xon_tx, &nsd->link_xon_tx);
920 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
921 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
922 pf->stat_offsets_loaded,
923 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 924
7812fddc
SN		 925 for (i = 0; i < 8; i++) {
926 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 927 pf->stat_offsets_loaded,
7812fddc
SN		 928 &osd->priority_xon_rx[i],
929 &nsd->priority_xon_rx[i]);
930 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 931 pf->stat_offsets_loaded,
7812fddc
SN		 932 &osd->priority_xon_tx[i],
933 &nsd->priority_xon_tx[i]);
934 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 935 pf->stat_offsets_loaded,
7812fddc
SN		 936 &osd->priority_xoff_tx[i],
937 &nsd->priority_xoff_tx[i]);
938 i40e_stat_update32(hw,
939 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 940 pf->stat_offsets_loaded,
7812fddc
SN		 941 &osd->priority_xon_2_xoff[i],
942 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 943 }
944
7812fddc
SN		 945 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
946 I40E_GLPRT_PRC64L(hw->port),
947 pf->stat_offsets_loaded,
948 &osd->rx_size_64, &nsd->rx_size_64);
949 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
950 I40E_GLPRT_PRC127L(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->rx_size_127, &nsd->rx_size_127);
953 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
954 I40E_GLPRT_PRC255L(hw->port),
955 pf->stat_offsets_loaded,
956 &osd->rx_size_255, &nsd->rx_size_255);
957 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
958 I40E_GLPRT_PRC511L(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->rx_size_511, &nsd->rx_size_511);
961 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
962 I40E_GLPRT_PRC1023L(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->rx_size_1023, &nsd->rx_size_1023);
965 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
966 I40E_GLPRT_PRC1522L(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_size_1522, &nsd->rx_size_1522);
969 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
970 I40E_GLPRT_PRC9522L(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_size_big, &nsd->rx_size_big);
973
974 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
975 I40E_GLPRT_PTC64L(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->tx_size_64, &nsd->tx_size_64);
978 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
979 I40E_GLPRT_PTC127L(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->tx_size_127, &nsd->tx_size_127);
982 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
983 I40E_GLPRT_PTC255L(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->tx_size_255, &nsd->tx_size_255);
986 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
987 I40E_GLPRT_PTC511L(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->tx_size_511, &nsd->tx_size_511);
990 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
991 I40E_GLPRT_PTC1023L(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->tx_size_1023, &nsd->tx_size_1023);
994 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
995 I40E_GLPRT_PTC1522L(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->tx_size_1522, &nsd->tx_size_1522);
998 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
999 I40E_GLPRT_PTC9522L(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->tx_size_big, &nsd->tx_size_big);
1002
1003 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->rx_undersize, &nsd->rx_undersize);
1006 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->rx_fragments, &nsd->rx_fragments);
1009 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->rx_oversize, &nsd->rx_oversize);
1012 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_jabber, &nsd->rx_jabber);
1015
433c47de
ASJ		 1016 /* FDIR stats */
1017 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_atr_cnt_idx),
1018 pf->stat_offsets_loaded,
1019 &osd->fd_atr_match, &nsd->fd_atr_match);
1020 i40e_stat_update32(hw, I40E_GLQF_PCNT(pf->fd_sb_cnt_idx),
1021 pf->stat_offsets_loaded,
1022 &osd->fd_sb_match, &nsd->fd_sb_match);
1023
7812fddc
SN		 1024 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1025 nsd->tx_lpi_status =
1026 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1027 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1028 nsd->rx_lpi_status =
1029 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1030 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1031 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1032 pf->stat_offsets_loaded,
1033 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1034 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1035 pf->stat_offsets_loaded,
1036 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1037
41c445ff
JB		 1038 pf->stat_offsets_loaded = true;
1039}
1040
7812fddc
SN		 1041/**
1042 * i40e_update_stats - Update the various statistics counters.
1043 * @vsi: the VSI to be updated
1044 *
1045 * Update the various stats for this VSI and its related entities.
1046 **/
1047void i40e_update_stats(struct i40e_vsi *vsi)
1048{
1049 struct i40e_pf *pf = vsi->back;
1050
1051 if (vsi == pf->vsi[pf->lan_vsi])
1052 i40e_update_pf_stats(pf);
1053
1054 i40e_update_vsi_stats(vsi);
1055}
1056
41c445ff
JB		 1057/**
1058 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1059 * @vsi: the VSI to be searched
1060 * @macaddr: the MAC address
1061 * @vlan: the vlan
1062 * @is_vf: make sure its a vf filter, else doesn't matter
1063 * @is_netdev: make sure its a netdev filter, else doesn't matter
1064 *
1065 * Returns ptr to the filter object or NULL
1066 **/
1067static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1068 u8 *macaddr, s16 vlan,
1069 bool is_vf, bool is_netdev)
1070{
1071 struct i40e_mac_filter *f;
1072
1073 if (!vsi || !macaddr)
1074 return NULL;
1075
1076 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1077 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1078 (vlan == f->vlan) &&
1079 (!is_vf || f->is_vf) &&
1080 (!is_netdev || f->is_netdev))
1081 return f;
1082 }
1083 return NULL;
1084}
1085
1086/**
1087 * i40e_find_mac - Find a mac addr in the macvlan filters list
1088 * @vsi: the VSI to be searched
1089 * @macaddr: the MAC address we are searching for
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns the first filter with the provided MAC address or NULL if
1094 * MAC address was not found
1095 **/
1096struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1105 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1106 (!is_vf || f->is_vf) &&
1107 (!is_netdev || f->is_netdev))
1108 return f;
1109 }
1110 return NULL;
1111}
1112
1113/**
1114 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1115 * @vsi: the VSI to be searched
1116 *
1117 * Returns true if VSI is in vlan mode or false otherwise
1118 **/
1119bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1120{
1121 struct i40e_mac_filter *f;
1122
1123 /* Only -1 for all the filters denotes not in vlan mode
1124 * so we have to go through all the list in order to make sure
1125 */
1126 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1127 if (f->vlan >= 0)
1128 return true;
1129 }
1130
1131 return false;
1132}
1133
1134/**
1135 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1136 * @vsi: the VSI to be searched
1137 * @macaddr: the mac address to be filtered
1138 * @is_vf: true if it is a vf
1139 * @is_netdev: true if it is a netdev
1140 *
1141 * Goes through all the macvlan filters and adds a
1142 * macvlan filter for each unique vlan that already exists
1143 *
1144 * Returns first filter found on success, else NULL
1145 **/
1146struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1147 bool is_vf, bool is_netdev)
1148{
1149 struct i40e_mac_filter *f;
1150
1151 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1152 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1153 is_vf, is_netdev)) {
1154 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1155 is_vf, is_netdev))
41c445ff
JB		 1156 return NULL;
1157 }
1158 }
1159
1160 return list_first_entry_or_null(&vsi->mac_filter_list,
1161 struct i40e_mac_filter, list);
1162}
1163
8c27d42e
GR		 1164/**
1165 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1166 * @vsi: the PF Main VSI - inappropriate for any other VSI
1167 * @macaddr: the MAC address
1168 **/
1169static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
1170{
1171 struct i40e_aqc_remove_macvlan_element_data element;
1172 struct i40e_pf *pf = vsi->back;
1173 i40e_status aq_ret;
1174
1175 /* Only appropriate for the PF main VSI */
1176 if (vsi->type != I40E_VSI_MAIN)
1177 return;
1178
1179 ether_addr_copy(element.mac_addr, macaddr);
1180 element.vlan_tag = 0;
1181 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1182 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1183 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1184 if (aq_ret)
1185 dev_err(&pf->pdev->dev, "Could not remove default MAC-VLAN\n");
1186}
1187
41c445ff
JB		 1188/**
1189 * i40e_add_filter - Add a mac/vlan filter to the VSI
1190 * @vsi: the VSI to be searched
1191 * @macaddr: the MAC address
1192 * @vlan: the vlan
1193 * @is_vf: make sure its a vf filter, else doesn't matter
1194 * @is_netdev: make sure its a netdev filter, else doesn't matter
1195 *
1196 * Returns ptr to the filter object or NULL when no memory available.
1197 **/
1198struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1199 u8 *macaddr, s16 vlan,
1200 bool is_vf, bool is_netdev)
1201{
1202 struct i40e_mac_filter *f;
1203
1204 if (!vsi || !macaddr)
1205 return NULL;
1206
1207 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1208 if (!f) {
1209 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1210 if (!f)
1211 goto add_filter_out;
1212
9a173901 1213 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1214 f->vlan = vlan;
1215 f->changed = true;
1216
1217 INIT_LIST_HEAD(&f->list);
1218 list_add(&f->list, &vsi->mac_filter_list);
1219 }
1220
1221 /* increment counter and add a new flag if needed */
1222 if (is_vf) {
1223 if (!f->is_vf) {
1224 f->is_vf = true;
1225 f->counter++;
1226 }
1227 } else if (is_netdev) {
1228 if (!f->is_netdev) {
1229 f->is_netdev = true;
1230 f->counter++;
1231 }
1232 } else {
1233 f->counter++;
1234 }
1235
1236 /* changed tells sync_filters_subtask to
1237 * push the filter down to the firmware
1238 */
1239 if (f->changed) {
1240 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1241 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1242 }
1243
1244add_filter_out:
1245 return f;
1246}
1247
1248/**
1249 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1250 * @vsi: the VSI to be searched
1251 * @macaddr: the MAC address
1252 * @vlan: the vlan
1253 * @is_vf: make sure it's a vf filter, else doesn't matter
1254 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1255 **/
1256void i40e_del_filter(struct i40e_vsi *vsi,
1257 u8 *macaddr, s16 vlan,
1258 bool is_vf, bool is_netdev)
1259{
1260 struct i40e_mac_filter *f;
1261
1262 if (!vsi || !macaddr)
1263 return;
1264
1265 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1266 if (!f || f->counter == 0)
1267 return;
1268
1269 if (is_vf) {
1270 if (f->is_vf) {
1271 f->is_vf = false;
1272 f->counter--;
1273 }
1274 } else if (is_netdev) {
1275 if (f->is_netdev) {
1276 f->is_netdev = false;
1277 f->counter--;
1278 }
1279 } else {
1280 /* make sure we don't remove a filter in use by vf or netdev */
1281 int min_f = 0;
1282 min_f += (f->is_vf ? 1 : 0);
1283 min_f += (f->is_netdev ? 1 : 0);
1284
1285 if (f->counter > min_f)
1286 f->counter--;
1287 }
1288
1289 /* counter == 0 tells sync_filters_subtask to
1290 * remove the filter from the firmware's list
1291 */
1292 if (f->counter == 0) {
1293 f->changed = true;
1294 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1295 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1296 }
1297}
1298
1299/**
1300 * i40e_set_mac - NDO callback to set mac address
1301 * @netdev: network interface device structure
1302 * @p: pointer to an address structure
1303 *
1304 * Returns 0 on success, negative on failure
1305 **/
1306static int i40e_set_mac(struct net_device *netdev, void *p)
1307{
1308 struct i40e_netdev_priv *np = netdev_priv(netdev);
1309 struct i40e_vsi *vsi = np->vsi;
1310 struct sockaddr *addr = p;
1311 struct i40e_mac_filter *f;
1312
1313 if (!is_valid_ether_addr(addr->sa_data))
1314 return -EADDRNOTAVAIL;
1315
1316 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1317
1318 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1319 return 0;
1320
80f6428f
ASJ		 1321 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1322 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1323 return -EADDRNOTAVAIL;
1324
41c445ff
JB		 1325 if (vsi->type == I40E_VSI_MAIN) {
1326 i40e_status ret;
1327 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1328 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1329 addr->sa_data, NULL);
1330 if (ret) {
1331 netdev_info(netdev,
1332 "Addr change for Main VSI failed: %d\n",
1333 ret);
1334 return -EADDRNOTAVAIL;
1335 }
1336
9a173901 1337 ether_addr_copy(vsi->back->hw.mac.addr, addr->sa_data);
41c445ff
JB		 1338 }
1339
1340 /* In order to be sure to not drop any packets, add the new address
1341 * then delete the old one.
1342 */
1343 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1344 if (!f)
1345 return -ENOMEM;
1346
1347 i40e_sync_vsi_filters(vsi);
1348 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1349 i40e_sync_vsi_filters(vsi);
1350
9a173901 1351 ether_addr_copy(netdev->dev_addr, addr->sa_data);
41c445ff
JB		 1352
1353 return 0;
1354}
1355
1356/**
1357 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1358 * @vsi: the VSI being setup
1359 * @ctxt: VSI context structure
1360 * @enabled_tc: Enabled TCs bitmap
1361 * @is_add: True if called before Add VSI
1362 *
1363 * Setup VSI queue mapping for enabled traffic classes.
1364 **/
1365static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1366 struct i40e_vsi_context *ctxt,
1367 u8 enabled_tc,
1368 bool is_add)
1369{
1370 struct i40e_pf *pf = vsi->back;
1371 u16 sections = 0;
1372 u8 netdev_tc = 0;
1373 u16 numtc = 0;
1374 u16 qcount;
1375 u8 offset;
1376 u16 qmap;
1377 int i;
4e3b35b0 1378 u16 num_tc_qps = 0;
41c445ff
JB		 1379
1380 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1381 offset = 0;
1382
1383 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1384 /* Find numtc from enabled TC bitmap */
1385 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1386 if (enabled_tc & (1 << i)) /* TC is enabled */
1387 numtc++;
1388 }
1389 if (!numtc) {
1390 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1391 numtc = 1;
1392 }
1393 } else {
1394 /* At least TC0 is enabled in case of non-DCB case */
1395 numtc = 1;
1396 }
1397
1398 vsi->tc_config.numtc = numtc;
1399 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1400 /* Number of queues per enabled TC */
eb051afe 1401 num_tc_qps = vsi->alloc_queue_pairs/numtc;
4e3b35b0 1402 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1403
1404 /* Setup queue offset/count for all TCs for given VSI */
1405 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1406 /* See if the given TC is enabled for the given VSI */
1407 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1408 int pow, num_qps;
1409
41c445ff
JB		 1410 switch (vsi->type) {
1411 case I40E_VSI_MAIN:
4e3b35b0 1412 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1413 break;
1414 case I40E_VSI_FDIR:
1415 case I40E_VSI_SRIOV:
1416 case I40E_VSI_VMDQ2:
1417 default:
4e3b35b0 1418 qcount = num_tc_qps;
41c445ff
JB		 1419 WARN_ON(i != 0);
1420 break;
1421 }
4e3b35b0
NP		 1422 vsi->tc_config.tc_info[i].qoffset = offset;
1423 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1424
1425 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1426 num_qps = qcount;
41c445ff 1427 pow = 0;
4e3b35b0 1428 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1429 pow++;
1430 num_qps >>= 1;
1431 }
1432
1433 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1434 qmap =
1435 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1436 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1437
4e3b35b0 1438 offset += qcount;
41c445ff
JB		 1439 } else {
1440 /* TC is not enabled so set the offset to
1441 * default queue and allocate one queue
1442 * for the given TC.
1443 */
1444 vsi->tc_config.tc_info[i].qoffset = 0;
1445 vsi->tc_config.tc_info[i].qcount = 1;
1446 vsi->tc_config.tc_info[i].netdev_tc = 0;
1447
1448 qmap = 0;
1449 }
1450 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1451 }
1452
1453 /* Set actual Tx/Rx queue pairs */
1454 vsi->num_queue_pairs = offset;
1455
1456 /* Scheduler section valid can only be set for ADD VSI */
1457 if (is_add) {
1458 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1459
1460 ctxt->info.up_enable_bits = enabled_tc;
1461 }
1462 if (vsi->type == I40E_VSI_SRIOV) {
1463 ctxt->info.mapping_flags |=
1464 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1465 for (i = 0; i < vsi->num_queue_pairs; i++)
1466 ctxt->info.queue_mapping[i] =
1467 cpu_to_le16(vsi->base_queue + i);
1468 } else {
1469 ctxt->info.mapping_flags |=
1470 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1471 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1472 }
1473 ctxt->info.valid_sections |= cpu_to_le16(sections);
1474}
1475
1476/**
1477 * i40e_set_rx_mode - NDO callback to set the netdev filters
1478 * @netdev: network interface device structure
1479 **/
1480static void i40e_set_rx_mode(struct net_device *netdev)
1481{
1482 struct i40e_netdev_priv *np = netdev_priv(netdev);
1483 struct i40e_mac_filter *f, *ftmp;
1484 struct i40e_vsi *vsi = np->vsi;
1485 struct netdev_hw_addr *uca;
1486 struct netdev_hw_addr *mca;
1487 struct netdev_hw_addr *ha;
1488
1489 /* add addr if not already in the filter list */
1490 netdev_for_each_uc_addr(uca, netdev) {
1491 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1492 if (i40e_is_vsi_in_vlan(vsi))
1493 i40e_put_mac_in_vlan(vsi, uca->addr,
1494 false, true);
1495 else
1496 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1497 false, true);
1498 }
1499 }
1500
1501 netdev_for_each_mc_addr(mca, netdev) {
1502 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1503 if (i40e_is_vsi_in_vlan(vsi))
1504 i40e_put_mac_in_vlan(vsi, mca->addr,
1505 false, true);
1506 else
1507 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1508 false, true);
1509 }
1510 }
1511
1512 /* remove filter if not in netdev list */
1513 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1514 bool found = false;
1515
1516 if (!f->is_netdev)
1517 continue;
1518
1519 if (is_multicast_ether_addr(f->macaddr)) {
1520 netdev_for_each_mc_addr(mca, netdev) {
1521 if (ether_addr_equal(mca->addr, f->macaddr)) {
1522 found = true;
1523 break;
1524 }
1525 }
1526 } else {
1527 netdev_for_each_uc_addr(uca, netdev) {
1528 if (ether_addr_equal(uca->addr, f->macaddr)) {
1529 found = true;
1530 break;
1531 }
1532 }
1533
1534 for_each_dev_addr(netdev, ha) {
1535 if (ether_addr_equal(ha->addr, f->macaddr)) {
1536 found = true;
1537 break;
1538 }
1539 }
1540 }
1541 if (!found)
1542 i40e_del_filter(
1543 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1544 }
1545
1546 /* check for other flag changes */
1547 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1548 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1549 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1550 }
1551}
1552
1553/**
1554 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1555 * @vsi: ptr to the VSI
1556 *
1557 * Push any outstanding VSI filter changes through the AdminQ.
1558 *
1559 * Returns 0 or error value
1560 **/
1561int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1562{
1563 struct i40e_mac_filter *f, *ftmp;
1564 bool promisc_forced_on = false;
1565 bool add_happened = false;
1566 int filter_list_len = 0;
1567 u32 changed_flags = 0;
dcae29be 1568 i40e_status aq_ret = 0;
41c445ff
JB		 1569 struct i40e_pf *pf;
1570 int num_add = 0;
1571 int num_del = 0;
1572 u16 cmd_flags;
1573
1574 /* empty array typed pointers, kcalloc later */
1575 struct i40e_aqc_add_macvlan_element_data *add_list;
1576 struct i40e_aqc_remove_macvlan_element_data *del_list;
1577
1578 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1579 usleep_range(1000, 2000);
1580 pf = vsi->back;
1581
1582 if (vsi->netdev) {
1583 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1584 vsi->current_netdev_flags = vsi->netdev->flags;
1585 }
1586
1587 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1588 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1589
1590 filter_list_len = pf->hw.aq.asq_buf_size /
1591 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1592 del_list = kcalloc(filter_list_len,
1593 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1594 GFP_KERNEL);
1595 if (!del_list)
1596 return -ENOMEM;
1597
1598 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1599 if (!f->changed)
1600 continue;
1601
1602 if (f->counter != 0)
1603 continue;
1604 f->changed = false;
1605 cmd_flags = 0;
1606
1607 /* add to delete list */
9a173901 1608 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1609 del_list[num_del].vlan_tag =
1610 cpu_to_le16((u16)(f->vlan ==
1611 I40E_VLAN_ANY ? 0 : f->vlan));
1612
41c445ff
JB		 1613 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1614 del_list[num_del].flags = cmd_flags;
1615 num_del++;
1616
1617 /* unlink from filter list */
1618 list_del(&f->list);
1619 kfree(f);
1620
1621 /* flush a full buffer */
1622 if (num_del == filter_list_len) {
dcae29be 1623 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1624 vsi->seid, del_list, num_del,
1625 NULL);
1626 num_del = 0;
1627 memset(del_list, 0, sizeof(*del_list));
1628
fdfe9cbe
SN		 1629 if (aq_ret &&
1630 pf->hw.aq.asq_last_status !=
1631 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1632 dev_info(&pf->pdev->dev,
1633 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1634 aq_ret,
41c445ff
JB		 1635 pf->hw.aq.asq_last_status);
1636 }
1637 }
1638 if (num_del) {
dcae29be 1639 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1640 del_list, num_del, NULL);
1641 num_del = 0;
1642
fdfe9cbe
SN		 1643 if (aq_ret &&
1644 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1645 dev_info(&pf->pdev->dev,
1646 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1647 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1648 }
1649
1650 kfree(del_list);
1651 del_list = NULL;
1652
1653 /* do all the adds now */
1654 filter_list_len = pf->hw.aq.asq_buf_size /
1655 sizeof(struct i40e_aqc_add_macvlan_element_data),
1656 add_list = kcalloc(filter_list_len,
1657 sizeof(struct i40e_aqc_add_macvlan_element_data),
1658 GFP_KERNEL);
1659 if (!add_list)
1660 return -ENOMEM;
1661
1662 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1663 if (!f->changed)
1664 continue;
1665
1666 if (f->counter == 0)
1667 continue;
1668 f->changed = false;
1669 add_happened = true;
1670 cmd_flags = 0;
1671
1672 /* add to add array */
9a173901 1673 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1674 add_list[num_add].vlan_tag =
1675 cpu_to_le16(
1676 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1677 add_list[num_add].queue_number = 0;
1678
1679 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1680 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1681 num_add++;
1682
1683 /* flush a full buffer */
1684 if (num_add == filter_list_len) {
dcae29be
JB		 1685 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1686 add_list, num_add,
1687 NULL);
41c445ff
JB		 1688 num_add = 0;
1689
dcae29be 1690 if (aq_ret)
41c445ff
JB		 1691 break;
1692 memset(add_list, 0, sizeof(*add_list));
1693 }
1694 }
1695 if (num_add) {
dcae29be
JB		 1696 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1697 add_list, num_add, NULL);
41c445ff
JB		 1698 num_add = 0;
1699 }
1700 kfree(add_list);
1701 add_list = NULL;
1702
dcae29be 1703 if (add_happened && (!aq_ret)) {
41c445ff 1704 /* do nothing */;
dcae29be 1705 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1706 dev_info(&pf->pdev->dev,
1707 "add filter failed, err %d, aq_err %d\n",
dcae29be 1708 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1709 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1710 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1711 &vsi->state)) {
1712 promisc_forced_on = true;
1713 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1714 &vsi->state);
1715 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1716 }
1717 }
1718 }
1719
1720 /* check for changes in promiscuous modes */
1721 if (changed_flags & IFF_ALLMULTI) {
1722 bool cur_multipromisc;
1723 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1724 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1725 vsi->seid,
1726 cur_multipromisc,
1727 NULL);
1728 if (aq_ret)
41c445ff
JB		 1729 dev_info(&pf->pdev->dev,
1730 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1731 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1732 }
1733 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1734 bool cur_promisc;
1735 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1736 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1737 &vsi->state));
dcae29be
JB		 1738 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1739 vsi->seid,
1740 cur_promisc, NULL);
1741 if (aq_ret)
41c445ff
JB		 1742 dev_info(&pf->pdev->dev,
1743 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1744 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1745 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1746 vsi->seid,
1747 cur_promisc, NULL);
1748 if (aq_ret)
1749 dev_info(&pf->pdev->dev,
1750 "set brdcast promisc failed, err %d, aq_err %d\n",
1751 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1752 }
1753
1754 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1755 return 0;
1756}
1757
1758/**
1759 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1760 * @pf: board private structure
1761 **/
1762static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1763{
1764 int v;
1765
1766 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1767 return;
1768 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1769
505682cd 1770 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1771 if (pf->vsi[v] &&
1772 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1773 i40e_sync_vsi_filters(pf->vsi[v]);
1774 }
1775}
1776
1777/**
1778 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1779 * @netdev: network interface device structure
1780 * @new_mtu: new value for maximum frame size
1781 *
1782 * Returns 0 on success, negative on failure
1783 **/
1784static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1785{
1786 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1787 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1788 struct i40e_vsi *vsi = np->vsi;
1789
1790 /* MTU < 68 is an error and causes problems on some kernels */
1791 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1792 return -EINVAL;
1793
1794 netdev_info(netdev, "changing MTU from %d to %d\n",
1795 netdev->mtu, new_mtu);
1796 netdev->mtu = new_mtu;
1797 if (netif_running(netdev))
1798 i40e_vsi_reinit_locked(vsi);
1799
1800 return 0;
1801}
1802
beb0dff1
JK		 1803/**
1804 * i40e_ioctl - Access the hwtstamp interface
1805 * @netdev: network interface device structure
1806 * @ifr: interface request data
1807 * @cmd: ioctl command
1808 **/
1809int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1810{
1811 struct i40e_netdev_priv *np = netdev_priv(netdev);
1812 struct i40e_pf *pf = np->vsi->back;
1813
1814 switch (cmd) {
1815 case SIOCGHWTSTAMP:
1816 return i40e_ptp_get_ts_config(pf, ifr);
1817 case SIOCSHWTSTAMP:
1818 return i40e_ptp_set_ts_config(pf, ifr);
1819 default:
1820 return -EOPNOTSUPP;
1821 }
1822}
1823
41c445ff
JB		 1824/**
1825 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1826 * @vsi: the vsi being adjusted
1827 **/
1828void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1829{
1830 struct i40e_vsi_context ctxt;
1831 i40e_status ret;
1832
1833 if ((vsi->info.valid_sections &
1834 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1835 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1836 return; /* already enabled */
1837
1838 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1839 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1840 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1841
1842 ctxt.seid = vsi->seid;
1843 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1844 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1845 if (ret) {
1846 dev_info(&vsi->back->pdev->dev,
1847 "%s: update vsi failed, aq_err=%d\n",
1848 __func__, vsi->back->hw.aq.asq_last_status);
1849 }
1850}
1851
1852/**
1853 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1854 * @vsi: the vsi being adjusted
1855 **/
1856void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1857{
1858 struct i40e_vsi_context ctxt;
1859 i40e_status ret;
1860
1861 if ((vsi->info.valid_sections &
1862 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1863 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1864 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1865 return; /* already disabled */
1866
1867 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1868 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1869 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1870
1871 ctxt.seid = vsi->seid;
1872 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1873 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1874 if (ret) {
1875 dev_info(&vsi->back->pdev->dev,
1876 "%s: update vsi failed, aq_err=%d\n",
1877 __func__, vsi->back->hw.aq.asq_last_status);
1878 }
1879}
1880
1881/**
1882 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1883 * @netdev: network interface to be adjusted
1884 * @features: netdev features to test if VLAN offload is enabled or not
1885 **/
1886static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1887{
1888 struct i40e_netdev_priv *np = netdev_priv(netdev);
1889 struct i40e_vsi *vsi = np->vsi;
1890
1891 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1892 i40e_vlan_stripping_enable(vsi);
1893 else
1894 i40e_vlan_stripping_disable(vsi);
1895}
1896
1897/**
1898 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1899 * @vsi: the vsi being configured
1900 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1901 **/
1902int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1903{
1904 struct i40e_mac_filter *f, *add_f;
1905 bool is_netdev, is_vf;
41c445ff
JB		 1906
1907 is_vf = (vsi->type == I40E_VSI_SRIOV);
1908 is_netdev = !!(vsi->netdev);
1909
1910 if (is_netdev) {
1911 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1912 is_vf, is_netdev);
1913 if (!add_f) {
1914 dev_info(&vsi->back->pdev->dev,
1915 "Could not add vlan filter %d for %pM\n",
1916 vid, vsi->netdev->dev_addr);
1917 return -ENOMEM;
1918 }
1919 }
1920
1921 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1922 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1923 if (!add_f) {
1924 dev_info(&vsi->back->pdev->dev,
1925 "Could not add vlan filter %d for %pM\n",
1926 vid, f->macaddr);
1927 return -ENOMEM;
1928 }
1929 }
1930
41c445ff
JB		 1931 /* Now if we add a vlan tag, make sure to check if it is the first
1932 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1933 * with 0, so we now accept untagged and specified tagged traffic
1934 * (and not any taged and untagged)
1935 */
1936 if (vid > 0) {
1937 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1938 I40E_VLAN_ANY,
1939 is_vf, is_netdev)) {
1940 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1941 I40E_VLAN_ANY, is_vf, is_netdev);
1942 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1943 is_vf, is_netdev);
1944 if (!add_f) {
1945 dev_info(&vsi->back->pdev->dev,
1946 "Could not add filter 0 for %pM\n",
1947 vsi->netdev->dev_addr);
1948 return -ENOMEM;
1949 }
1950 }
8d82a7c5 1951 }
41c445ff 1952
8d82a7c5
GR		 1953 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1954 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1955 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1956 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1957 is_vf, is_netdev)) {
1958 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1959 is_vf, is_netdev);
1960 add_f = i40e_add_filter(vsi, f->macaddr,
1961 0, is_vf, is_netdev);
1962 if (!add_f) {
1963 dev_info(&vsi->back->pdev->dev,
1964 "Could not add filter 0 for %pM\n",
1965 f->macaddr);
1966 return -ENOMEM;
1967 }
1968 }
1969 }
41c445ff
JB		 1970 }
1971
80f6428f
ASJ		 1972 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1973 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1974 return 0;
1975
1976 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1977}
1978
1979/**
1980 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1981 * @vsi: the vsi being configured
1982 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1983 *
1984 * Return: 0 on success or negative otherwise
41c445ff
JB		 1985 **/
1986int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1987{
1988 struct net_device *netdev = vsi->netdev;
1989 struct i40e_mac_filter *f, *add_f;
1990 bool is_vf, is_netdev;
1991 int filter_count = 0;
41c445ff
JB		 1992
1993 is_vf = (vsi->type == I40E_VSI_SRIOV);
1994 is_netdev = !!(netdev);
1995
1996 if (is_netdev)
1997 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1998
1999 list_for_each_entry(f, &vsi->mac_filter_list, list)
2000 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2001
41c445ff
JB		 2002 /* go through all the filters for this VSI and if there is only
2003 * vid == 0 it means there are no other filters, so vid 0 must
2004 * be replaced with -1. This signifies that we should from now
2005 * on accept any traffic (with any tag present, or untagged)
2006 */
2007 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2008 if (is_netdev) {
2009 if (f->vlan &&
2010 ether_addr_equal(netdev->dev_addr, f->macaddr))
2011 filter_count++;
2012 }
2013
2014 if (f->vlan)
2015 filter_count++;
2016 }
2017
2018 if (!filter_count && is_netdev) {
2019 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2020 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2021 is_vf, is_netdev);
2022 if (!f) {
2023 dev_info(&vsi->back->pdev->dev,
2024 "Could not add filter %d for %pM\n",
2025 I40E_VLAN_ANY, netdev->dev_addr);
2026 return -ENOMEM;
2027 }
2028 }
2029
2030 if (!filter_count) {
2031 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2032 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2033 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2034 is_vf, is_netdev);
2035 if (!add_f) {
2036 dev_info(&vsi->back->pdev->dev,
2037 "Could not add filter %d for %pM\n",
2038 I40E_VLAN_ANY, f->macaddr);
2039 return -ENOMEM;
2040 }
2041 }
2042 }
2043
80f6428f
ASJ		 2044 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2045 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2046 return 0;
2047
41c445ff
JB		 2048 return i40e_sync_vsi_filters(vsi);
2049}
2050
2051/**
2052 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2053 * @netdev: network interface to be adjusted
2054 * @vid: vlan id to be added
078b5876
JB		 2055 *
2056 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 2057 **/
2058static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2059 __always_unused __be16 proto, u16 vid)
2060{
2061 struct i40e_netdev_priv *np = netdev_priv(netdev);
2062 struct i40e_vsi *vsi = np->vsi;
078b5876 2063 int ret = 0;
41c445ff
JB		 2064
2065 if (vid > 4095)
078b5876
JB		 2066 return -EINVAL;
2067
2068 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2069
6982d429
ASJ		 2070 /* If the network stack called us with vid = 0 then
2071 * it is asking to receive priority tagged packets with
2072 * vlan id 0. Our HW receives them by default when configured
2073 * to receive untagged packets so there is no need to add an
2074 * extra filter for vlan 0 tagged packets.
41c445ff 2075 */
6982d429
ASJ		 2076 if (vid)
2077 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2078
078b5876
JB		 2079 if (!ret && (vid < VLAN_N_VID))
2080 set_bit(vid, vsi->active_vlans);
41c445ff 2081
078b5876 2082 return ret;
41c445ff
JB		 2083}
2084
2085/**
2086 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2087 * @netdev: network interface to be adjusted
2088 * @vid: vlan id to be removed
078b5876 2089 *
fdfd943e 2090 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2091 **/
2092static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2093 __always_unused __be16 proto, u16 vid)
2094{
2095 struct i40e_netdev_priv *np = netdev_priv(netdev);
2096 struct i40e_vsi *vsi = np->vsi;
2097
078b5876
JB		 2098 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2099
41c445ff
JB		 2100 /* return code is ignored as there is nothing a user
2101 * can do about failure to remove and a log message was
078b5876 2102 * already printed from the other function
41c445ff
JB		 2103 */
2104 i40e_vsi_kill_vlan(vsi, vid);
2105
2106 clear_bit(vid, vsi->active_vlans);
078b5876 2107
41c445ff
JB		 2108 return 0;
2109}
2110
2111/**
2112 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2113 * @vsi: the vsi being brought back up
2114 **/
2115static void i40e_restore_vlan(struct i40e_vsi *vsi)
2116{
2117 u16 vid;
2118
2119 if (!vsi->netdev)
2120 return;
2121
2122 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2123
2124 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2125 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2126 vid);
2127}
2128
2129/**
2130 * i40e_vsi_add_pvid - Add pvid for the VSI
2131 * @vsi: the vsi being adjusted
2132 * @vid: the vlan id to set as a PVID
2133 **/
dcae29be 2134int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2135{
2136 struct i40e_vsi_context ctxt;
dcae29be 2137 i40e_status aq_ret;
41c445ff
JB		 2138
2139 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2140 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2141 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2142 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2143 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2144
2145 ctxt.seid = vsi->seid;
2146 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2147 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2148 if (aq_ret) {
41c445ff
JB		 2149 dev_info(&vsi->back->pdev->dev,
2150 "%s: update vsi failed, aq_err=%d\n",
2151 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2152 return -ENOENT;
41c445ff
JB		 2153 }
2154
dcae29be 2155 return 0;
41c445ff
JB		 2156}
2157
2158/**
2159 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2160 * @vsi: the vsi being adjusted
2161 *
2162 * Just use the vlan_rx_register() service to put it back to normal
2163 **/
2164void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2165{
6c12fcbf
GR		 2166 i40e_vlan_stripping_disable(vsi);
2167
41c445ff 2168 vsi->info.pvid = 0;
41c445ff
JB		 2169}
2170
2171/**
2172 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2173 * @vsi: ptr to the VSI
2174 *
2175 * If this function returns with an error, then it's possible one or
2176 * more of the rings is populated (while the rest are not). It is the
2177 * callers duty to clean those orphaned rings.
2178 *
2179 * Return 0 on success, negative on failure
2180 **/
2181static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2182{
2183 int i, err = 0;
2184
2185 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2186 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2187
2188 return err;
2189}
2190
2191/**
2192 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2193 * @vsi: ptr to the VSI
2194 *
2195 * Free VSI's transmit software resources
2196 **/
2197static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2198{
2199 int i;
2200
8e9dca53
GR		 2201 if (!vsi->tx_rings)
2202 return;
2203
41c445ff 2204 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2205 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2206 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2207}
2208
2209/**
2210 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2211 * @vsi: ptr to the VSI
2212 *
2213 * If this function returns with an error, then it's possible one or
2214 * more of the rings is populated (while the rest are not). It is the
2215 * callers duty to clean those orphaned rings.
2216 *
2217 * Return 0 on success, negative on failure
2218 **/
2219static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2220{
2221 int i, err = 0;
2222
2223 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2224 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2225 return err;
2226}
2227
2228/**
2229 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2230 * @vsi: ptr to the VSI
2231 *
2232 * Free all receive software resources
2233 **/
2234static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2235{
2236 int i;
2237
8e9dca53
GR		 2238 if (!vsi->rx_rings)
2239 return;
2240
41c445ff 2241 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2242 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2243 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2244}
2245
2246/**
2247 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2248 * @ring: The Tx ring to configure
2249 *
2250 * Configure the Tx descriptor ring in the HMC context.
2251 **/
2252static int i40e_configure_tx_ring(struct i40e_ring *ring)
2253{
2254 struct i40e_vsi *vsi = ring->vsi;
2255 u16 pf_q = vsi->base_queue + ring->queue_index;
2256 struct i40e_hw *hw = &vsi->back->hw;
2257 struct i40e_hmc_obj_txq tx_ctx;
2258 i40e_status err = 0;
2259 u32 qtx_ctl = 0;
2260
2261 /* some ATR related tx ring init */
60ea5f83 2262 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2263 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2264 ring->atr_count = 0;
2265 } else {
2266 ring->atr_sample_rate = 0;
2267 }
2268
2269 /* initialize XPS */
2270 if (ring->q_vector && ring->netdev &&
4e3b35b0 2271 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2272 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2273 netif_set_xps_queue(ring->netdev,
2274 &ring->q_vector->affinity_mask,
2275 ring->queue_index);
2276
2277 /* clear the context structure first */
2278 memset(&tx_ctx, 0, sizeof(tx_ctx));
2279
2280 tx_ctx.new_context = 1;
2281 tx_ctx.base = (ring->dma / 128);
2282 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2283 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2284 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2285 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2286 /* FDIR VSI tx ring can still use RS bit and writebacks */
2287 if (vsi->type != I40E_VSI_FDIR)
2288 tx_ctx.head_wb_ena = 1;
2289 tx_ctx.head_wb_addr = ring->dma +
2290 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2291
2292 /* As part of VSI creation/update, FW allocates certain
2293 * Tx arbitration queue sets for each TC enabled for
2294 * the VSI. The FW returns the handles to these queue
2295 * sets as part of the response buffer to Add VSI,
2296 * Update VSI, etc. AQ commands. It is expected that
2297 * these queue set handles be associated with the Tx
2298 * queues by the driver as part of the TX queue context
2299 * initialization. This has to be done regardless of
2300 * DCB as by default everything is mapped to TC0.
2301 */
2302 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2303 tx_ctx.rdylist_act = 0;
2304
2305 /* clear the context in the HMC */
2306 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2307 if (err) {
2308 dev_info(&vsi->back->pdev->dev,
2309 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2310 ring->queue_index, pf_q, err);
2311 return -ENOMEM;
2312 }
2313
2314 /* set the context in the HMC */
2315 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2316 if (err) {
2317 dev_info(&vsi->back->pdev->dev,
2318 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2319 ring->queue_index, pf_q, err);
2320 return -ENOMEM;
2321 }
2322
2323 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2324 if (vsi->type == I40E_VSI_VMDQ2)
2325 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2326 else
2327 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2328 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2329 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2330 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2331 i40e_flush(hw);
2332
2333 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2334
2335 /* cache tail off for easier writes later */
2336 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2337
2338 return 0;
2339}
2340
2341/**
2342 * i40e_configure_rx_ring - Configure a receive ring context
2343 * @ring: The Rx ring to configure
2344 *
2345 * Configure the Rx descriptor ring in the HMC context.
2346 **/
2347static int i40e_configure_rx_ring(struct i40e_ring *ring)
2348{
2349 struct i40e_vsi *vsi = ring->vsi;
2350 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2351 u16 pf_q = vsi->base_queue + ring->queue_index;
2352 struct i40e_hw *hw = &vsi->back->hw;
2353 struct i40e_hmc_obj_rxq rx_ctx;
2354 i40e_status err = 0;
2355
2356 ring->state = 0;
2357
2358 /* clear the context structure first */
2359 memset(&rx_ctx, 0, sizeof(rx_ctx));
2360
2361 ring->rx_buf_len = vsi->rx_buf_len;
2362 ring->rx_hdr_len = vsi->rx_hdr_len;
2363
2364 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2365 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2366
2367 rx_ctx.base = (ring->dma / 128);
2368 rx_ctx.qlen = ring->count;
2369
2370 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2371 set_ring_16byte_desc_enabled(ring);
2372 rx_ctx.dsize = 0;
2373 } else {
2374 rx_ctx.dsize = 1;
2375 }
2376
2377 rx_ctx.dtype = vsi->dtype;
2378 if (vsi->dtype) {
2379 set_ring_ps_enabled(ring);
2380 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2381 I40E_RX_SPLIT_IP |
2382 I40E_RX_SPLIT_TCP_UDP |
2383 I40E_RX_SPLIT_SCTP;
2384 } else {
2385 rx_ctx.hsplit_0 = 0;
2386 }
2387
2388 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2389 (chain_len * ring->rx_buf_len));
2390 rx_ctx.tphrdesc_ena = 1;
2391 rx_ctx.tphwdesc_ena = 1;
2392 rx_ctx.tphdata_ena = 1;
2393 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2394 if (hw->revision_id == 0)
2395 rx_ctx.lrxqthresh = 0;
2396 else
2397 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2398 rx_ctx.crcstrip = 1;
2399 rx_ctx.l2tsel = 1;
2400 rx_ctx.showiv = 1;
acb3676b
CS		 2401 /* set the prefena field to 1 because the manual says to */
2402 rx_ctx.prefena = 1;
41c445ff
JB		 2403
2404 /* clear the context in the HMC */
2405 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2406 if (err) {
2407 dev_info(&vsi->back->pdev->dev,
2408 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2409 ring->queue_index, pf_q, err);
2410 return -ENOMEM;
2411 }
2412
2413 /* set the context in the HMC */
2414 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2415 if (err) {
2416 dev_info(&vsi->back->pdev->dev,
2417 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2418 ring->queue_index, pf_q, err);
2419 return -ENOMEM;
2420 }
2421
2422 /* cache tail for quicker writes, and clear the reg before use */
2423 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2424 writel(0, ring->tail);
2425
2426 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2427
2428 return 0;
2429}
2430
2431/**
2432 * i40e_vsi_configure_tx - Configure the VSI for Tx
2433 * @vsi: VSI structure describing this set of rings and resources
2434 *
2435 * Configure the Tx VSI for operation.
2436 **/
2437static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2438{
2439 int err = 0;
2440 u16 i;
2441
9f65e15b
AD		 2442 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2443 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2444
2445 return err;
2446}
2447
2448/**
2449 * i40e_vsi_configure_rx - Configure the VSI for Rx
2450 * @vsi: the VSI being configured
2451 *
2452 * Configure the Rx VSI for operation.
2453 **/
2454static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2455{
2456 int err = 0;
2457 u16 i;
2458
2459 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2460 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2461 + ETH_FCS_LEN + VLAN_HLEN;
2462 else
2463 vsi->max_frame = I40E_RXBUFFER_2048;
2464
2465 /* figure out correct receive buffer length */
2466 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2467 I40E_FLAG_RX_PS_ENABLED)) {
2468 case I40E_FLAG_RX_1BUF_ENABLED:
2469 vsi->rx_hdr_len = 0;
2470 vsi->rx_buf_len = vsi->max_frame;
2471 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2472 break;
2473 case I40E_FLAG_RX_PS_ENABLED:
2474 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2475 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2476 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2477 break;
2478 default:
2479 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2480 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2481 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2482 break;
2483 }
2484
2485 /* round up for the chip's needs */
2486 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2487 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2488 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2489 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2490
2491 /* set up individual rings */
2492 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2493 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2494
2495 return err;
2496}
2497
2498/**
2499 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2500 * @vsi: ptr to the VSI
2501 **/
2502static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2503{
e7046ee1 2504 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2505 u16 qoffset, qcount;
2506 int i, n;
2507
2508 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2509 return;
2510
2511 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2512 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2513 continue;
2514
2515 qoffset = vsi->tc_config.tc_info[n].qoffset;
2516 qcount = vsi->tc_config.tc_info[n].qcount;
2517 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2518 rx_ring = vsi->rx_rings[i];
2519 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2520 rx_ring->dcb_tc = n;
2521 tx_ring->dcb_tc = n;
2522 }
2523 }
2524}
2525
2526/**
2527 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2528 * @vsi: ptr to the VSI
2529 **/
2530static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2531{
2532 if (vsi->netdev)
2533 i40e_set_rx_mode(vsi->netdev);
2534}
2535
17a73f6b
JG		 2536/**
2537 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2538 * @vsi: Pointer to the targeted VSI
2539 *
2540 * This function replays the hlist on the hw where all the SB Flow Director
2541 * filters were saved.
2542 **/
2543static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2544{
2545 struct i40e_fdir_filter *filter;
2546 struct i40e_pf *pf = vsi->back;
2547 struct hlist_node *node;
2548
55a5e60b
ASJ		 2549 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2550 return;
2551
17a73f6b
JG		 2552 hlist_for_each_entry_safe(filter, node,
2553 &pf->fdir_filter_list, fdir_node) {
2554 i40e_add_del_fdir(vsi, filter, true);
2555 }
2556}
2557
41c445ff
JB		 2558/**
2559 * i40e_vsi_configure - Set up the VSI for action
2560 * @vsi: the VSI being configured
2561 **/
2562static int i40e_vsi_configure(struct i40e_vsi *vsi)
2563{
2564 int err;
2565
2566 i40e_set_vsi_rx_mode(vsi);
2567 i40e_restore_vlan(vsi);
2568 i40e_vsi_config_dcb_rings(vsi);
2569 err = i40e_vsi_configure_tx(vsi);
2570 if (!err)
2571 err = i40e_vsi_configure_rx(vsi);
2572
2573 return err;
2574}
2575
2576/**
2577 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2578 * @vsi: the VSI being configured
2579 **/
2580static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2581{
2582 struct i40e_pf *pf = vsi->back;
2583 struct i40e_q_vector *q_vector;
2584 struct i40e_hw *hw = &pf->hw;
2585 u16 vector;
2586 int i, q;
2587 u32 val;
2588 u32 qp;
2589
2590 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2591 * and PFINT_LNKLSTn registers, e.g.:
2592 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2593 */
2594 qp = vsi->base_queue;
2595 vector = vsi->base_vector;
493fb300
AD		 2596 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2597 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2598 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2599 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2600 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2601 q_vector->rx.itr);
2602 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2603 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2604 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2605 q_vector->tx.itr);
2606
2607 /* Linked list for the queuepairs assigned to this vector */
2608 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2609 for (q = 0; q < q_vector->num_ringpairs; q++) {
2610 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2611 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2612 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2613 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2614 (I40E_QUEUE_TYPE_TX
2615 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2616
2617 wr32(hw, I40E_QINT_RQCTL(qp), val);
2618
2619 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2620 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2621 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2622 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2623 (I40E_QUEUE_TYPE_RX
2624 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2625
2626 /* Terminate the linked list */
2627 if (q == (q_vector->num_ringpairs - 1))
2628 val |= (I40E_QUEUE_END_OF_LIST
2629 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2630
2631 wr32(hw, I40E_QINT_TQCTL(qp), val);
2632 qp++;
2633 }
2634 }
2635
2636 i40e_flush(hw);
2637}
2638
2639/**
2640 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2641 * @hw: ptr to the hardware info
2642 **/
2643static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2644{
2645 u32 val;
2646
2647 /* clear things first */
2648 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2649 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2650
2651 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2652 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2653 I40E_PFINT_ICR0_ENA_GRST_MASK |
2654 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2655 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2656 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2657 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2658 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2659 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2660
2661 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2662
2663 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2664 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2665 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2666
2667 /* OTHER_ITR_IDX = 0 */
2668 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2669}
2670
2671/**
2672 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2673 * @vsi: the VSI being configured
2674 **/
2675static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2676{
493fb300 2677 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2678 struct i40e_pf *pf = vsi->back;
2679 struct i40e_hw *hw = &pf->hw;
2680 u32 val;
2681
2682 /* set the ITR configuration */
2683 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2684 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2685 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2686 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2687 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2688 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2689
2690 i40e_enable_misc_int_causes(hw);
2691
2692 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2693 wr32(hw, I40E_PFINT_LNKLST0, 0);
2694
f29eaa3d 2695 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2696 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2697 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2698 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2699
2700 wr32(hw, I40E_QINT_RQCTL(0), val);
2701
2702 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2703 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2704 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2705
2706 wr32(hw, I40E_QINT_TQCTL(0), val);
2707 i40e_flush(hw);
2708}
2709
2ef28cfb
MW		 2710/**
2711 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2712 * @pf: board private structure
2713 **/
2714void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2715{
2716 struct i40e_hw *hw = &pf->hw;
2717
2718 wr32(hw, I40E_PFINT_DYN_CTL0,
2719 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2720 i40e_flush(hw);
2721}
2722
41c445ff
JB		 2723/**
2724 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2725 * @pf: board private structure
2726 **/
116a57d4 2727void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2728{
2729 struct i40e_hw *hw = &pf->hw;
2730 u32 val;
2731
2732 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2733 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2734 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2735
2736 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2737 i40e_flush(hw);
2738}
2739
2740/**
2741 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2742 * @vsi: pointer to a vsi
2743 * @vector: enable a particular Hw Interrupt vector
2744 **/
2745void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2746{
2747 struct i40e_pf *pf = vsi->back;
2748 struct i40e_hw *hw = &pf->hw;
2749 u32 val;
2750
2751 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2752 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2753 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2754 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2755 /* skip the flush */
41c445ff
JB		 2756}
2757
2758/**
2759 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2760 * @irq: interrupt number
2761 * @data: pointer to a q_vector
2762 **/
2763static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2764{
2765 struct i40e_q_vector *q_vector = data;
2766
cd0b6fa6 2767 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2768 return IRQ_HANDLED;
2769
2770 napi_schedule(&q_vector->napi);
2771
2772 return IRQ_HANDLED;
2773}
2774
41c445ff
JB		 2775/**
2776 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2777 * @vsi: the VSI being configured
2778 * @basename: name for the vector
2779 *
2780 * Allocates MSI-X vectors and requests interrupts from the kernel.
2781 **/
2782static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2783{
2784 int q_vectors = vsi->num_q_vectors;
2785 struct i40e_pf *pf = vsi->back;
2786 int base = vsi->base_vector;
2787 int rx_int_idx = 0;
2788 int tx_int_idx = 0;
2789 int vector, err;
2790
2791 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2792 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2793
cd0b6fa6 2794 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2795 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2796 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2797 tx_int_idx++;
cd0b6fa6 2798 } else if (q_vector->rx.ring) {
41c445ff
JB		 2799 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2800 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2801 } else if (q_vector->tx.ring) {
41c445ff
JB		 2802 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2803 "%s-%s-%d", basename, "tx", tx_int_idx++);
2804 } else {
2805 /* skip this unused q_vector */
2806 continue;
2807 }
2808 err = request_irq(pf->msix_entries[base + vector].vector,
2809 vsi->irq_handler,
2810 0,
2811 q_vector->name,
2812 q_vector);
2813 if (err) {
2814 dev_info(&pf->pdev->dev,
2815 "%s: request_irq failed, error: %d\n",
2816 __func__, err);
2817 goto free_queue_irqs;
2818 }
2819 /* assign the mask for this irq */
2820 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2821 &q_vector->affinity_mask);
2822 }
2823
63741846 2824 vsi->irqs_ready = true;
41c445ff
JB		 2825 return 0;
2826
2827free_queue_irqs:
2828 while (vector) {
2829 vector--;
2830 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2831 NULL);
2832 free_irq(pf->msix_entries[base + vector].vector,
2833 &(vsi->q_vectors[vector]));
2834 }
2835 return err;
2836}
2837
2838/**
2839 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2840 * @vsi: the VSI being un-configured
2841 **/
2842static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2843{
2844 struct i40e_pf *pf = vsi->back;
2845 struct i40e_hw *hw = &pf->hw;
2846 int base = vsi->base_vector;
2847 int i;
2848
2849 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2850 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2851 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2852 }
2853
2854 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2855 for (i = vsi->base_vector;
2856 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2857 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2858
2859 i40e_flush(hw);
2860 for (i = 0; i < vsi->num_q_vectors; i++)
2861 synchronize_irq(pf->msix_entries[i + base].vector);
2862 } else {
2863 /* Legacy and MSI mode - this stops all interrupt handling */
2864 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2865 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2866 i40e_flush(hw);
2867 synchronize_irq(pf->pdev->irq);
2868 }
2869}
2870
2871/**
2872 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2873 * @vsi: the VSI being configured
2874 **/
2875static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2876{
2877 struct i40e_pf *pf = vsi->back;
2878 int i;
2879
2880 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2881 for (i = vsi->base_vector;
2882 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2883 i40e_irq_dynamic_enable(vsi, i);
2884 } else {
2885 i40e_irq_dynamic_enable_icr0(pf);
2886 }
2887
1022cb6c 2888 i40e_flush(&pf->hw);
41c445ff
JB		 2889 return 0;
2890}
2891
2892/**
2893 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2894 * @pf: board private structure
2895 **/
2896static void i40e_stop_misc_vector(struct i40e_pf *pf)
2897{
2898 /* Disable ICR 0 */
2899 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2900 i40e_flush(&pf->hw);
2901}
2902
2903/**
2904 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2905 * @irq: interrupt number
2906 * @data: pointer to a q_vector
2907 *
2908 * This is the handler used for all MSI/Legacy interrupts, and deals
2909 * with both queue and non-queue interrupts. This is also used in
2910 * MSIX mode to handle the non-queue interrupts.
2911 **/
2912static irqreturn_t i40e_intr(int irq, void *data)
2913{
2914 struct i40e_pf *pf = (struct i40e_pf *)data;
2915 struct i40e_hw *hw = &pf->hw;
5e823066 2916 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2917 u32 icr0, icr0_remaining;
2918 u32 val, ena_mask;
2919
2920 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2921 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2922
116a57d4
SN		 2923 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2924 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2925 goto enable_intr;
41c445ff 2926
cd92e72f
SN		 2927 /* if interrupt but no bits showing, must be SWINT */
2928 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2929 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2930 pf->sw_int_count++;
2931
41c445ff
JB		 2932 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2933 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2934
2935 /* temporarily disable queue cause for NAPI processing */
2936 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2937 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2938 wr32(hw, I40E_QINT_RQCTL(0), qval);
2939
2940 qval = rd32(hw, I40E_QINT_TQCTL(0));
2941 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2942 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2943
2944 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2945 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2946 }
2947
2948 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2949 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2950 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2951 }
2952
2953 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2954 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2955 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2956 }
2957
2958 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2959 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2960 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2961 }
2962
2963 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2964 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2965 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2966 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2967 val = rd32(hw, I40E_GLGEN_RSTAT);
2968 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2969 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2970 if (val == I40E_RESET_CORER) {
41c445ff 2971 pf->corer_count++;
4eb3f768 2972 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2973 pf->globr_count++;
4eb3f768 2974 } else if (val == I40E_RESET_EMPR) {
41c445ff 2975 pf->empr_count++;
4eb3f768
SN		 2976 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2977 }
41c445ff
JB		 2978 }
2979
9c010ee0
ASJ		 2980 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2981 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2982 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2983 }
2984
beb0dff1
JK		 2985 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2986 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2987
2988 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 2989 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 2990 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 2991 }
beb0dff1
JK		 2992 }
2993
41c445ff
JB		 2994 /* If a critical error is pending we have no choice but to reset the
2995 * device.
2996 * Report and mask out any remaining unexpected interrupts.
2997 */
2998 icr0_remaining = icr0 & ena_mask;
2999 if (icr0_remaining) {
3000 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3001 icr0_remaining);
9c010ee0 3002 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3003 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3004 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3005 dev_info(&pf->pdev->dev, "device will be reset\n");
3006 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3007 i40e_service_event_schedule(pf);
41c445ff
JB		 3008 }
3009 ena_mask &= ~icr0_remaining;
3010 }
5e823066 3011 ret = IRQ_HANDLED;
41c445ff 3012
5e823066 3013enable_intr:
41c445ff
JB		 3014 /* re-enable interrupt causes */
3015 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3016 if (!test_bit(__I40E_DOWN, &pf->state)) {
3017 i40e_service_event_schedule(pf);
3018 i40e_irq_dynamic_enable_icr0(pf);
3019 }
3020
5e823066 3021 return ret;
41c445ff
JB		 3022}
3023
cbf61325
ASJ		 3024/**
3025 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3026 * @tx_ring: tx ring to clean
3027 * @budget: how many cleans we're allowed
3028 *
3029 * Returns true if there's any budget left (e.g. the clean is finished)
3030 **/
3031static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3032{
3033 struct i40e_vsi *vsi = tx_ring->vsi;
3034 u16 i = tx_ring->next_to_clean;
3035 struct i40e_tx_buffer *tx_buf;
3036 struct i40e_tx_desc *tx_desc;
3037
3038 tx_buf = &tx_ring->tx_bi[i];
3039 tx_desc = I40E_TX_DESC(tx_ring, i);
3040 i -= tx_ring->count;
3041
3042 do {
3043 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3044
3045 /* if next_to_watch is not set then there is no work pending */
3046 if (!eop_desc)
3047 break;
3048
3049 /* prevent any other reads prior to eop_desc */
3050 read_barrier_depends();
3051
3052 /* if the descriptor isn't done, no work yet to do */
3053 if (!(eop_desc->cmd_type_offset_bsz &
3054 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3055 break;
3056
3057 /* clear next_to_watch to prevent false hangs */
3058 tx_buf->next_to_watch = NULL;
3059
3060 /* unmap skb header data */
3061 dma_unmap_single(tx_ring->dev,
3062 dma_unmap_addr(tx_buf, dma),
3063 dma_unmap_len(tx_buf, len),
3064 DMA_TO_DEVICE);
3065
3066 dma_unmap_len_set(tx_buf, len, 0);
3067
3068
3069 /* move to the next desc and buffer to clean */
3070 tx_buf++;
3071 tx_desc++;
3072 i++;
3073 if (unlikely(!i)) {
3074 i -= tx_ring->count;
3075 tx_buf = tx_ring->tx_bi;
3076 tx_desc = I40E_TX_DESC(tx_ring, 0);
3077 }
3078
3079 /* update budget accounting */
3080 budget--;
3081 } while (likely(budget));
3082
3083 i += tx_ring->count;
3084 tx_ring->next_to_clean = i;
3085
3086 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3087 i40e_irq_dynamic_enable(vsi,
3088 tx_ring->q_vector->v_idx + vsi->base_vector);
3089 }
3090 return budget > 0;
3091}
3092
3093/**
3094 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3095 * @irq: interrupt number
3096 * @data: pointer to a q_vector
3097 **/
3098static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3099{
3100 struct i40e_q_vector *q_vector = data;
3101 struct i40e_vsi *vsi;
3102
3103 if (!q_vector->tx.ring)
3104 return IRQ_HANDLED;
3105
3106 vsi = q_vector->tx.ring->vsi;
3107 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3108
3109 return IRQ_HANDLED;
3110}
3111
41c445ff 3112/**
cd0b6fa6 3113 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3114 * @vsi: the VSI being configured
3115 * @v_idx: vector index
cd0b6fa6 3116 * @qp_idx: queue pair index
41c445ff 3117 **/
cd0b6fa6 3118static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3119{
493fb300 3120 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3121 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3122 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3123
3124 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3125 tx_ring->next = q_vector->tx.ring;
3126 q_vector->tx.ring = tx_ring;
41c445ff 3127 q_vector->tx.count++;
cd0b6fa6
AD		 3128
3129 rx_ring->q_vector = q_vector;
3130 rx_ring->next = q_vector->rx.ring;
3131 q_vector->rx.ring = rx_ring;
3132 q_vector->rx.count++;
41c445ff
JB		 3133}
3134
3135/**
3136 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3137 * @vsi: the VSI being configured
3138 *
3139 * This function maps descriptor rings to the queue-specific vectors
3140 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3141 * one vector per queue pair, but on a constrained vector budget, we
3142 * group the queue pairs as "efficiently" as possible.
3143 **/
3144static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3145{
3146 int qp_remaining = vsi->num_queue_pairs;
3147 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3148 int num_ringpairs;
41c445ff
JB		 3149 int v_start = 0;
3150 int qp_idx = 0;
3151
3152 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3153 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3154 * It is also important to go through all the vectors available to be
3155 * sure that if we don't use all the vectors, that the remaining vectors
3156 * are cleared. This is especially important when decreasing the
3157 * number of queues in use.
41c445ff 3158 */
70114ec4 3159 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3160 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3161
3162 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3163
3164 q_vector->num_ringpairs = num_ringpairs;
3165
3166 q_vector->rx.count = 0;
3167 q_vector->tx.count = 0;
3168 q_vector->rx.ring = NULL;
3169 q_vector->tx.ring = NULL;
3170
3171 while (num_ringpairs--) {
3172 map_vector_to_qp(vsi, v_start, qp_idx);
3173 qp_idx++;
3174 qp_remaining--;
41c445ff
JB		 3175 }
3176 }
3177}
3178
3179/**
3180 * i40e_vsi_request_irq - Request IRQ from the OS
3181 * @vsi: the VSI being configured
3182 * @basename: name for the vector
3183 **/
3184static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3185{
3186 struct i40e_pf *pf = vsi->back;
3187 int err;
3188
3189 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3190 err = i40e_vsi_request_irq_msix(vsi, basename);
3191 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3192 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3193 pf->misc_int_name, pf);
3194 else
3195 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3196 pf->misc_int_name, pf);
3197
3198 if (err)
3199 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3200
3201 return err;
3202}
3203
3204#ifdef CONFIG_NET_POLL_CONTROLLER
3205/**
3206 * i40e_netpoll - A Polling 'interrupt'handler
3207 * @netdev: network interface device structure
3208 *
3209 * This is used by netconsole to send skbs without having to re-enable
3210 * interrupts. It's not called while the normal interrupt routine is executing.
3211 **/
3212static void i40e_netpoll(struct net_device *netdev)
3213{
3214 struct i40e_netdev_priv *np = netdev_priv(netdev);
3215 struct i40e_vsi *vsi = np->vsi;
3216 struct i40e_pf *pf = vsi->back;
3217 int i;
3218
3219 /* if interface is down do nothing */
3220 if (test_bit(__I40E_DOWN, &vsi->state))
3221 return;
3222
3223 pf->flags |= I40E_FLAG_IN_NETPOLL;
3224 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3225 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3226 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3227 } else {
3228 i40e_intr(pf->pdev->irq, netdev);
3229 }
3230 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3231}
3232#endif
3233
23527308
NP		 3234/**
3235 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3236 * @pf: the PF being configured
3237 * @pf_q: the PF queue
3238 * @enable: enable or disable state of the queue
3239 *
3240 * This routine will wait for the given Tx queue of the PF to reach the
3241 * enabled or disabled state.
3242 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3243 * multiple retries; else will return 0 in case of success.
3244 **/
3245static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3246{
3247 int i;
3248 u32 tx_reg;
3249
3250 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3251 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3252 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3253 break;
3254
3255 udelay(10);
3256 }
3257 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3258 return -ETIMEDOUT;
3259
3260 return 0;
3261}
3262
41c445ff
JB		 3263/**
3264 * i40e_vsi_control_tx - Start or stop a VSI's rings
3265 * @vsi: the VSI being configured
3266 * @enable: start or stop the rings
3267 **/
3268static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3269{
3270 struct i40e_pf *pf = vsi->back;
3271 struct i40e_hw *hw = &pf->hw;
23527308 3272 int i, j, pf_q, ret = 0;
41c445ff
JB		 3273 u32 tx_reg;
3274
3275 pf_q = vsi->base_queue;
3276 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3277
3278 /* warn the TX unit of coming changes */
3279 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3280 if (!enable)
3281 udelay(10);
3282
6c5ef620 3283 for (j = 0; j < 50; j++) {
41c445ff 3284 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3285 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3286 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3287 break;
3288 usleep_range(1000, 2000);
3289 }
fda972f6 3290 /* Skip if the queue is already in the requested state */
7c122007 3291 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3292 continue;
41c445ff
JB		 3293
3294 /* turn on/off the queue */
c5c9eb9e
SN		 3295 if (enable) {
3296 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3297 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3298 } else {
41c445ff 3299 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3300 }
41c445ff
JB		 3301
3302 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3303
3304 /* wait for the change to finish */
23527308
NP		 3305 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3306 if (ret) {
3307 dev_info(&pf->pdev->dev,
3308 "%s: VSI seid %d Tx ring %d %sable timeout\n",
3309 __func__, vsi->seid, pf_q,
3310 (enable ? "en" : "dis"));
3311 break;
41c445ff
JB		 3312 }
3313 }
3314
7134f9ce
JB		 3315 if (hw->revision_id == 0)
3316 mdelay(50);
23527308
NP		 3317 return ret;
3318}
3319
3320/**
3321 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3322 * @pf: the PF being configured
3323 * @pf_q: the PF queue
3324 * @enable: enable or disable state of the queue
3325 *
3326 * This routine will wait for the given Rx queue of the PF to reach the
3327 * enabled or disabled state.
3328 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3329 * multiple retries; else will return 0 in case of success.
3330 **/
3331static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3332{
3333 int i;
3334 u32 rx_reg;
3335
3336 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3337 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3338 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3339 break;
3340
3341 udelay(10);
3342 }
3343 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3344 return -ETIMEDOUT;
7134f9ce 3345
41c445ff
JB		 3346 return 0;
3347}
3348
3349/**
3350 * i40e_vsi_control_rx - Start or stop a VSI's rings
3351 * @vsi: the VSI being configured
3352 * @enable: start or stop the rings
3353 **/
3354static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3355{
3356 struct i40e_pf *pf = vsi->back;
3357 struct i40e_hw *hw = &pf->hw;
23527308 3358 int i, j, pf_q, ret = 0;
41c445ff
JB		 3359 u32 rx_reg;
3360
3361 pf_q = vsi->base_queue;
3362 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3363 for (j = 0; j < 50; j++) {
41c445ff 3364 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3365 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3366 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3367 break;
3368 usleep_range(1000, 2000);
3369 }
41c445ff 3370
7c122007
CS		 3371 /* Skip if the queue is already in the requested state */
3372 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3373 continue;
41c445ff
JB		 3374
3375 /* turn on/off the queue */
3376 if (enable)
6c5ef620 3377 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3378 else
6c5ef620 3379 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3380 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3381
3382 /* wait for the change to finish */
23527308
NP		 3383 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3384 if (ret) {
3385 dev_info(&pf->pdev->dev,
3386 "%s: VSI seid %d Rx ring %d %sable timeout\n",
3387 __func__, vsi->seid, pf_q,
3388 (enable ? "en" : "dis"));
3389 break;
41c445ff
JB		 3390 }
3391 }
3392
23527308 3393 return ret;
41c445ff
JB		 3394}
3395
3396/**
3397 * i40e_vsi_control_rings - Start or stop a VSI's rings
3398 * @vsi: the VSI being configured
3399 * @enable: start or stop the rings
3400 **/
fc18eaa0 3401int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3402{
3b867b28 3403 int ret = 0;
41c445ff
JB		 3404
3405 /* do rx first for enable and last for disable */
3406 if (request) {
3407 ret = i40e_vsi_control_rx(vsi, request);
3408 if (ret)
3409 return ret;
3410 ret = i40e_vsi_control_tx(vsi, request);
3411 } else {
3b867b28
ASJ		 3412 /* Ignore return value, we need to shutdown whatever we can */
3413 i40e_vsi_control_tx(vsi, request);
3414 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3415 }
3416
3417 return ret;
3418}
3419
3420/**
3421 * i40e_vsi_free_irq - Free the irq association with the OS
3422 * @vsi: the VSI being configured
3423 **/
3424static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3425{
3426 struct i40e_pf *pf = vsi->back;
3427 struct i40e_hw *hw = &pf->hw;
3428 int base = vsi->base_vector;
3429 u32 val, qp;
3430 int i;
3431
3432 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3433 if (!vsi->q_vectors)
3434 return;
3435
63741846
SN		 3436 if (!vsi->irqs_ready)
3437 return;
3438
3439 vsi->irqs_ready = false;
41c445ff
JB		 3440 for (i = 0; i < vsi->num_q_vectors; i++) {
3441 u16 vector = i + base;
3442
3443 /* free only the irqs that were actually requested */
78681b1f
SN		 3444 if (!vsi->q_vectors[i] ||
3445 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3446 continue;
3447
3448 /* clear the affinity_mask in the IRQ descriptor */
3449 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3450 NULL);
3451 free_irq(pf->msix_entries[vector].vector,
493fb300 3452 vsi->q_vectors[i]);
41c445ff
JB		 3453
3454 /* Tear down the interrupt queue link list
3455 *
3456 * We know that they come in pairs and always
3457 * the Rx first, then the Tx. To clear the
3458 * link list, stick the EOL value into the
3459 * next_q field of the registers.
3460 */
3461 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3462 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3463 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3464 val |= I40E_QUEUE_END_OF_LIST
3465 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3466 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3467
3468 while (qp != I40E_QUEUE_END_OF_LIST) {
3469 u32 next;
3470
3471 val = rd32(hw, I40E_QINT_RQCTL(qp));
3472
3473 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3474 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3475 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3476 I40E_QINT_RQCTL_INTEVENT_MASK);
3477
3478 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3479 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3480
3481 wr32(hw, I40E_QINT_RQCTL(qp), val);
3482
3483 val = rd32(hw, I40E_QINT_TQCTL(qp));
3484
3485 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3486 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3487
3488 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3489 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3490 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3491 I40E_QINT_TQCTL_INTEVENT_MASK);
3492
3493 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3494 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3495
3496 wr32(hw, I40E_QINT_TQCTL(qp), val);
3497 qp = next;
3498 }
3499 }
3500 } else {
3501 free_irq(pf->pdev->irq, pf);
3502
3503 val = rd32(hw, I40E_PFINT_LNKLST0);
3504 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3505 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3506 val |= I40E_QUEUE_END_OF_LIST
3507 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3508 wr32(hw, I40E_PFINT_LNKLST0, val);
3509
3510 val = rd32(hw, I40E_QINT_RQCTL(qp));
3511 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3512 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3513 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3514 I40E_QINT_RQCTL_INTEVENT_MASK);
3515
3516 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3517 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3518
3519 wr32(hw, I40E_QINT_RQCTL(qp), val);
3520
3521 val = rd32(hw, I40E_QINT_TQCTL(qp));
3522
3523 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3524 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3525 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3526 I40E_QINT_TQCTL_INTEVENT_MASK);
3527
3528 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3529 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3530
3531 wr32(hw, I40E_QINT_TQCTL(qp), val);
3532 }
3533}
3534
493fb300
AD		 3535/**
3536 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3537 * @vsi: the VSI being configured
3538 * @v_idx: Index of vector to be freed
3539 *
3540 * This function frees the memory allocated to the q_vector. In addition if
3541 * NAPI is enabled it will delete any references to the NAPI struct prior
3542 * to freeing the q_vector.
3543 **/
3544static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3545{
3546 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3547 struct i40e_ring *ring;
493fb300
AD		 3548
3549 if (!q_vector)
3550 return;
3551
3552 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3553 i40e_for_each_ring(ring, q_vector->tx)
3554 ring->q_vector = NULL;
3555
3556 i40e_for_each_ring(ring, q_vector->rx)
3557 ring->q_vector = NULL;
493fb300
AD		 3558
3559 /* only VSI w/ an associated netdev is set up w/ NAPI */
3560 if (vsi->netdev)
3561 netif_napi_del(&q_vector->napi);
3562
3563 vsi->q_vectors[v_idx] = NULL;
3564
3565 kfree_rcu(q_vector, rcu);
3566}
3567
41c445ff
JB		 3568/**
3569 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3570 * @vsi: the VSI being un-configured
3571 *
3572 * This frees the memory allocated to the q_vectors and
3573 * deletes references to the NAPI struct.
3574 **/
3575static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3576{
3577 int v_idx;
3578
493fb300
AD		 3579 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3580 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3581}
3582
3583/**
3584 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3585 * @pf: board private structure
3586 **/
3587static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3588{
3589 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3590 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3591 pci_disable_msix(pf->pdev);
3592 kfree(pf->msix_entries);
3593 pf->msix_entries = NULL;
3594 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3595 pci_disable_msi(pf->pdev);
3596 }
3597 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3598}
3599
3600/**
3601 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3602 * @pf: board private structure
3603 *
3604 * We go through and clear interrupt specific resources and reset the structure
3605 * to pre-load conditions
3606 **/
3607static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3608{
3609 int i;
3610
3611 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3612 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3613 if (pf->vsi[i])
3614 i40e_vsi_free_q_vectors(pf->vsi[i]);
3615 i40e_reset_interrupt_capability(pf);
3616}
3617
3618/**
3619 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3620 * @vsi: the VSI being configured
3621 **/
3622static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3623{
3624 int q_idx;
3625
3626 if (!vsi->netdev)
3627 return;
3628
3629 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3630 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3631}
3632
3633/**
3634 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3635 * @vsi: the VSI being configured
3636 **/
3637static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3638{
3639 int q_idx;
3640
3641 if (!vsi->netdev)
3642 return;
3643
3644 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3645 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3646}
3647
90ef8d47
SN		 3648/**
3649 * i40e_vsi_close - Shut down a VSI
3650 * @vsi: the vsi to be quelled
3651 **/
3652static void i40e_vsi_close(struct i40e_vsi *vsi)
3653{
3654 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3655 i40e_down(vsi);
3656 i40e_vsi_free_irq(vsi);
3657 i40e_vsi_free_tx_resources(vsi);
3658 i40e_vsi_free_rx_resources(vsi);
3659}
3660
41c445ff
JB		 3661/**
3662 * i40e_quiesce_vsi - Pause a given VSI
3663 * @vsi: the VSI being paused
3664 **/
3665static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3666{
3667 if (test_bit(__I40E_DOWN, &vsi->state))
3668 return;
3669
3670 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3671 if (vsi->netdev && netif_running(vsi->netdev)) {
3672 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3673 } else {
90ef8d47 3674 i40e_vsi_close(vsi);
41c445ff
JB		 3675 }
3676}
3677
3678/**
3679 * i40e_unquiesce_vsi - Resume a given VSI
3680 * @vsi: the VSI being resumed
3681 **/
3682static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3683{
3684 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3685 return;
3686
3687 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3688 if (vsi->netdev && netif_running(vsi->netdev))
3689 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3690 else
8276f757 3691 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3692}
3693
3694/**
3695 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3696 * @pf: the PF
3697 **/
3698static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3699{
3700 int v;
3701
505682cd 3702 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3703 if (pf->vsi[v])
3704 i40e_quiesce_vsi(pf->vsi[v]);
3705 }
3706}
3707
3708/**
3709 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3710 * @pf: the PF
3711 **/
3712static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3713{
3714 int v;
3715
505682cd 3716 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3717 if (pf->vsi[v])
3718 i40e_unquiesce_vsi(pf->vsi[v]);
3719 }
3720}
3721
3722/**
3723 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3724 * @dcbcfg: the corresponding DCBx configuration structure
3725 *
3726 * Return the number of TCs from given DCBx configuration
3727 **/
3728static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3729{
078b5876
JB		 3730 u8 num_tc = 0;
3731 int i;
41c445ff
JB		 3732
3733 /* Scan the ETS Config Priority Table to find
3734 * traffic class enabled for a given priority
3735 * and use the traffic class index to get the
3736 * number of traffic classes enabled
3737 */
3738 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3739 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3740 num_tc = dcbcfg->etscfg.prioritytable[i];
3741 }
3742
3743 /* Traffic class index starts from zero so
3744 * increment to return the actual count
3745 */
078b5876 3746 return num_tc + 1;
41c445ff
JB		 3747}
3748
3749/**
3750 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3751 * @dcbcfg: the corresponding DCBx configuration structure
3752 *
3753 * Query the current DCB configuration and return the number of
3754 * traffic classes enabled from the given DCBX config
3755 **/
3756static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3757{
3758 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3759 u8 enabled_tc = 1;
3760 u8 i;
3761
3762 for (i = 0; i < num_tc; i++)
3763 enabled_tc |= 1 << i;
3764
3765 return enabled_tc;
3766}
3767
3768/**
3769 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3770 * @pf: PF being queried
3771 *
3772 * Return number of traffic classes enabled for the given PF
3773 **/
3774static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3775{
3776 struct i40e_hw *hw = &pf->hw;
3777 u8 i, enabled_tc;
3778 u8 num_tc = 0;
3779 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3780
3781 /* If DCB is not enabled then always in single TC */
3782 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3783 return 1;
3784
3785 /* MFP mode return count of enabled TCs for this PF */
3786 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3787 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3788 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3789 if (enabled_tc & (1 << i))
3790 num_tc++;
3791 }
3792 return num_tc;
3793 }
3794
3795 /* SFP mode will be enabled for all TCs on port */
3796 return i40e_dcb_get_num_tc(dcbcfg);
3797}
3798
3799/**
3800 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3801 * @pf: PF being queried
3802 *
3803 * Return a bitmap for first enabled traffic class for this PF.
3804 **/
3805static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3806{
3807 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3808 u8 i = 0;
3809
3810 if (!enabled_tc)
3811 return 0x1; /* TC0 */
3812
3813 /* Find the first enabled TC */
3814 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3815 if (enabled_tc & (1 << i))
3816 break;
3817 }
3818
3819 return 1 << i;
3820}
3821
3822/**
3823 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3824 * @pf: PF being queried
3825 *
3826 * Return a bitmap for enabled traffic classes for this PF.
3827 **/
3828static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3829{
3830 /* If DCB is not enabled for this PF then just return default TC */
3831 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3832 return i40e_pf_get_default_tc(pf);
3833
3834 /* MFP mode will have enabled TCs set by FW */
3835 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3836 return pf->hw.func_caps.enabled_tcmap;
3837
3838 /* SFP mode we want PF to be enabled for all TCs */
3839 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3840}
3841
3842/**
3843 * i40e_vsi_get_bw_info - Query VSI BW Information
3844 * @vsi: the VSI being queried
3845 *
3846 * Returns 0 on success, negative value on failure
3847 **/
3848static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3849{
3850 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3851 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3852 struct i40e_pf *pf = vsi->back;
3853 struct i40e_hw *hw = &pf->hw;
dcae29be 3854 i40e_status aq_ret;
41c445ff 3855 u32 tc_bw_max;
41c445ff
JB		 3856 int i;
3857
3858 /* Get the VSI level BW configuration */
dcae29be
JB		 3859 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3860 if (aq_ret) {
41c445ff
JB		 3861 dev_info(&pf->pdev->dev,
3862 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3863 aq_ret, pf->hw.aq.asq_last_status);
3864 return -EINVAL;
41c445ff
JB		 3865 }
3866
3867 /* Get the VSI level BW configuration per TC */
dcae29be 3868 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3869 NULL);
dcae29be 3870 if (aq_ret) {
41c445ff
JB		 3871 dev_info(&pf->pdev->dev,
3872 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3873 aq_ret, pf->hw.aq.asq_last_status);
3874 return -EINVAL;
41c445ff
JB		 3875 }
3876
3877 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3878 dev_info(&pf->pdev->dev,
3879 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3880 bw_config.tc_valid_bits,
3881 bw_ets_config.tc_valid_bits);
3882 /* Still continuing */
3883 }
3884
3885 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3886 vsi->bw_max_quanta = bw_config.max_bw;
3887 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3888 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3889 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3890 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3891 vsi->bw_ets_limit_credits[i] =
3892 le16_to_cpu(bw_ets_config.credits[i]);
3893 /* 3 bits out of 4 for each TC */
3894 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3895 }
078b5876 3896
dcae29be 3897 return 0;
41c445ff
JB		 3898}
3899
3900/**
3901 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3902 * @vsi: the VSI being configured
3903 * @enabled_tc: TC bitmap
3904 * @bw_credits: BW shared credits per TC
3905 *
3906 * Returns 0 on success, negative value on failure
3907 **/
dcae29be 3908static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3909 u8 *bw_share)
3910{
3911 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3912 i40e_status aq_ret;
3913 int i;
41c445ff
JB		 3914
3915 bw_data.tc_valid_bits = enabled_tc;
3916 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3917 bw_data.tc_bw_credits[i] = bw_share[i];
3918
dcae29be
JB		 3919 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3920 NULL);
3921 if (aq_ret) {
41c445ff 3922 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3923 "AQ command Config VSI BW allocation per TC failed = %d\n",
3924 vsi->back->hw.aq.asq_last_status);
dcae29be 3925 return -EINVAL;
41c445ff
JB		 3926 }
3927
3928 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3929 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3930
dcae29be 3931 return 0;
41c445ff
JB		 3932}
3933
3934/**
3935 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3936 * @vsi: the VSI being configured
3937 * @enabled_tc: TC map to be enabled
3938 *
3939 **/
3940static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3941{
3942 struct net_device *netdev = vsi->netdev;
3943 struct i40e_pf *pf = vsi->back;
3944 struct i40e_hw *hw = &pf->hw;
3945 u8 netdev_tc = 0;
3946 int i;
3947 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3948
3949 if (!netdev)
3950 return;
3951
3952 if (!enabled_tc) {
3953 netdev_reset_tc(netdev);
3954 return;
3955 }
3956
3957 /* Set up actual enabled TCs on the VSI */
3958 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3959 return;
3960
3961 /* set per TC queues for the VSI */
3962 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3963 /* Only set TC queues for enabled tcs
3964 *
3965 * e.g. For a VSI that has TC0 and TC3 enabled the
3966 * enabled_tc bitmap would be 0x00001001; the driver
3967 * will set the numtc for netdev as 2 that will be
3968 * referenced by the netdev layer as TC 0 and 1.
3969 */
3970 if (vsi->tc_config.enabled_tc & (1 << i))
3971 netdev_set_tc_queue(netdev,
3972 vsi->tc_config.tc_info[i].netdev_tc,
3973 vsi->tc_config.tc_info[i].qcount,
3974 vsi->tc_config.tc_info[i].qoffset);
3975 }
3976
3977 /* Assign UP2TC map for the VSI */
3978 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3979 /* Get the actual TC# for the UP */
3980 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3981 /* Get the mapped netdev TC# for the UP */
3982 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3983 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3984 }
3985}
3986
3987/**
3988 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3989 * @vsi: the VSI being configured
3990 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3991 **/
3992static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3993 struct i40e_vsi_context *ctxt)
3994{
3995 /* copy just the sections touched not the entire info
3996 * since not all sections are valid as returned by
3997 * update vsi params
3998 */
3999 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4000 memcpy(&vsi->info.queue_mapping,
4001 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4002 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4003 sizeof(vsi->info.tc_mapping));
4004}
4005
4006/**
4007 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4008 * @vsi: VSI to be configured
4009 * @enabled_tc: TC bitmap
4010 *
4011 * This configures a particular VSI for TCs that are mapped to the
4012 * given TC bitmap. It uses default bandwidth share for TCs across
4013 * VSIs to configure TC for a particular VSI.
4014 *
4015 * NOTE:
4016 * It is expected that the VSI queues have been quisced before calling
4017 * this function.
4018 **/
4019static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4020{
4021 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4022 struct i40e_vsi_context ctxt;
4023 int ret = 0;
4024 int i;
4025
4026 /* Check if enabled_tc is same as existing or new TCs */
4027 if (vsi->tc_config.enabled_tc == enabled_tc)
4028 return ret;
4029
4030 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4031 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4032 if (enabled_tc & (1 << i))
4033 bw_share[i] = 1;
4034 }
4035
4036 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4037 if (ret) {
4038 dev_info(&vsi->back->pdev->dev,
4039 "Failed configuring TC map %d for VSI %d\n",
4040 enabled_tc, vsi->seid);
4041 goto out;
4042 }
4043
4044 /* Update Queue Pairs Mapping for currently enabled UPs */
4045 ctxt.seid = vsi->seid;
4046 ctxt.pf_num = vsi->back->hw.pf_id;
4047 ctxt.vf_num = 0;
4048 ctxt.uplink_seid = vsi->uplink_seid;
4049 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4050 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4051
4052 /* Update the VSI after updating the VSI queue-mapping information */
4053 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4054 if (ret) {
4055 dev_info(&vsi->back->pdev->dev,
4056 "update vsi failed, aq_err=%d\n",
4057 vsi->back->hw.aq.asq_last_status);
4058 goto out;
4059 }
4060 /* update the local VSI info with updated queue map */
4061 i40e_vsi_update_queue_map(vsi, &ctxt);
4062 vsi->info.valid_sections = 0;
4063
4064 /* Update current VSI BW information */
4065 ret = i40e_vsi_get_bw_info(vsi);
4066 if (ret) {
4067 dev_info(&vsi->back->pdev->dev,
4068 "Failed updating vsi bw info, aq_err=%d\n",
4069 vsi->back->hw.aq.asq_last_status);
4070 goto out;
4071 }
4072
4073 /* Update the netdev TC setup */
4074 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4075out:
4076 return ret;
4077}
4078
4e3b35b0
NP		 4079/**
4080 * i40e_veb_config_tc - Configure TCs for given VEB
4081 * @veb: given VEB
4082 * @enabled_tc: TC bitmap
4083 *
4084 * Configures given TC bitmap for VEB (switching) element
4085 **/
4086int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4087{
4088 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4089 struct i40e_pf *pf = veb->pf;
4090 int ret = 0;
4091 int i;
4092
4093 /* No TCs or already enabled TCs just return */
4094 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4095 return ret;
4096
4097 bw_data.tc_valid_bits = enabled_tc;
4098 /* bw_data.absolute_credits is not set (relative) */
4099
4100 /* Enable ETS TCs with equal BW Share for now */
4101 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4102 if (enabled_tc & (1 << i))
4103 bw_data.tc_bw_share_credits[i] = 1;
4104 }
4105
4106 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4107 &bw_data, NULL);
4108 if (ret) {
4109 dev_info(&pf->pdev->dev,
4110 "veb bw config failed, aq_err=%d\n",
4111 pf->hw.aq.asq_last_status);
4112 goto out;
4113 }
4114
4115 /* Update the BW information */
4116 ret = i40e_veb_get_bw_info(veb);
4117 if (ret) {
4118 dev_info(&pf->pdev->dev,
4119 "Failed getting veb bw config, aq_err=%d\n",
4120 pf->hw.aq.asq_last_status);
4121 }
4122
4123out:
4124 return ret;
4125}
4126
4127#ifdef CONFIG_I40E_DCB
4128/**
4129 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4130 * @pf: PF struct
4131 *
4132 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4133 * the caller would've quiesce all the VSIs before calling
4134 * this function
4135 **/
4136static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4137{
4138 u8 tc_map = 0;
4139 int ret;
4140 u8 v;
4141
4142 /* Enable the TCs available on PF to all VEBs */
4143 tc_map = i40e_pf_get_tc_map(pf);
4144 for (v = 0; v < I40E_MAX_VEB; v++) {
4145 if (!pf->veb[v])
4146 continue;
4147 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4148 if (ret) {
4149 dev_info(&pf->pdev->dev,
4150 "Failed configuring TC for VEB seid=%d\n",
4151 pf->veb[v]->seid);
4152 /* Will try to configure as many components */
4153 }
4154 }
4155
4156 /* Update each VSI */
505682cd 4157 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4158 if (!pf->vsi[v])
4159 continue;
4160
4161 /* - Enable all TCs for the LAN VSI
4162 * - For all others keep them at TC0 for now
4163 */
4164 if (v == pf->lan_vsi)
4165 tc_map = i40e_pf_get_tc_map(pf);
4166 else
4167 tc_map = i40e_pf_get_default_tc(pf);
4168
4169 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4170 if (ret) {
4171 dev_info(&pf->pdev->dev,
4172 "Failed configuring TC for VSI seid=%d\n",
4173 pf->vsi[v]->seid);
4174 /* Will try to configure as many components */
4175 } else {
0672a091
NP		 4176 /* Re-configure VSI vectors based on updated TC map */
4177 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4178 if (pf->vsi[v]->netdev)
4179 i40e_dcbnl_set_all(pf->vsi[v]);
4180 }
4181 }
4182}
4183
4184/**
4185 * i40e_init_pf_dcb - Initialize DCB configuration
4186 * @pf: PF being configured
4187 *
4188 * Query the current DCB configuration and cache it
4189 * in the hardware structure
4190 **/
4191static int i40e_init_pf_dcb(struct i40e_pf *pf)
4192{
4193 struct i40e_hw *hw = &pf->hw;
4194 int err = 0;
4195
4196 if (pf->hw.func_caps.npar_enable)
4197 goto out;
4198
4199 /* Get the initial DCB configuration */
4200 err = i40e_init_dcb(hw);
4201 if (!err) {
4202 /* Device/Function is not DCBX capable */
4203 if ((!hw->func_caps.dcb) ||
4204 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4205 dev_info(&pf->pdev->dev,
4206 "DCBX offload is not supported or is disabled for this PF.\n");
4207
4208 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4209 goto out;
4210
4211 } else {
4212 /* When status is not DISABLED then DCBX in FW */
4213 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4214 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4215
4216 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4217 /* Enable DCB tagging only when more than one TC */
4218 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4219 pf->flags |= I40E_FLAG_DCB_ENABLED;
4e3b35b0 4220 }
014269ff
NP		 4221 } else {
4222 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4223 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4224 }
4225
4226out:
4227 return err;
4228}
4229#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4230#define SPEED_SIZE 14
4231#define FC_SIZE 8
4232/**
4233 * i40e_print_link_message - print link up or down
4234 * @vsi: the VSI for which link needs a message
4235 */
4236static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4237{
4238 char speed[SPEED_SIZE] = "Unknown";
4239 char fc[FC_SIZE] = "RX/TX";
4240
4241 if (!isup) {
4242 netdev_info(vsi->netdev, "NIC Link is Down\n");
4243 return;
4244 }
4245
4246 switch (vsi->back->hw.phy.link_info.link_speed) {
4247 case I40E_LINK_SPEED_40GB:
4248 strncpy(speed, "40 Gbps", SPEED_SIZE);
4249 break;
4250 case I40E_LINK_SPEED_10GB:
4251 strncpy(speed, "10 Gbps", SPEED_SIZE);
4252 break;
4253 case I40E_LINK_SPEED_1GB:
4254 strncpy(speed, "1000 Mbps", SPEED_SIZE);
4255 break;
4256 default:
4257 break;
4258 }
4259
4260 switch (vsi->back->hw.fc.current_mode) {
4261 case I40E_FC_FULL:
4262 strncpy(fc, "RX/TX", FC_SIZE);
4263 break;
4264 case I40E_FC_TX_PAUSE:
4265 strncpy(fc, "TX", FC_SIZE);
4266 break;
4267 case I40E_FC_RX_PAUSE:
4268 strncpy(fc, "RX", FC_SIZE);
4269 break;
4270 default:
4271 strncpy(fc, "None", FC_SIZE);
4272 break;
4273 }
4274
4275 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4276 speed, fc);
4277}
4e3b35b0 4278
41c445ff
JB		 4279/**
4280 * i40e_up_complete - Finish the last steps of bringing up a connection
4281 * @vsi: the VSI being configured
4282 **/
4283static int i40e_up_complete(struct i40e_vsi *vsi)
4284{
4285 struct i40e_pf *pf = vsi->back;
4286 int err;
4287
4288 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4289 i40e_vsi_configure_msix(vsi);
4290 else
4291 i40e_configure_msi_and_legacy(vsi);
4292
4293 /* start rings */
4294 err = i40e_vsi_control_rings(vsi, true);
4295 if (err)
4296 return err;
4297
4298 clear_bit(__I40E_DOWN, &vsi->state);
4299 i40e_napi_enable_all(vsi);
4300 i40e_vsi_enable_irq(vsi);
4301
4302 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4303 (vsi->netdev)) {
cf05ed08 4304 i40e_print_link_message(vsi, true);
41c445ff
JB		 4305 netif_tx_start_all_queues(vsi->netdev);
4306 netif_carrier_on(vsi->netdev);
6d779b41 4307 } else if (vsi->netdev) {
cf05ed08 4308 i40e_print_link_message(vsi, false);
41c445ff 4309 }
ca64fa4e
ASJ		 4310
4311 /* replay FDIR SB filters */
4312 if (vsi->type == I40E_VSI_FDIR)
4313 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4314 i40e_service_event_schedule(pf);
4315
4316 return 0;
4317}
4318
4319/**
4320 * i40e_vsi_reinit_locked - Reset the VSI
4321 * @vsi: the VSI being configured
4322 *
4323 * Rebuild the ring structs after some configuration
4324 * has changed, e.g. MTU size.
4325 **/
4326static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4327{
4328 struct i40e_pf *pf = vsi->back;
4329
4330 WARN_ON(in_interrupt());
4331 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4332 usleep_range(1000, 2000);
4333 i40e_down(vsi);
4334
4335 /* Give a VF some time to respond to the reset. The
4336 * two second wait is based upon the watchdog cycle in
4337 * the VF driver.
4338 */
4339 if (vsi->type == I40E_VSI_SRIOV)
4340 msleep(2000);
4341 i40e_up(vsi);
4342 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4343}
4344
4345/**
4346 * i40e_up - Bring the connection back up after being down
4347 * @vsi: the VSI being configured
4348 **/
4349int i40e_up(struct i40e_vsi *vsi)
4350{
4351 int err;
4352
4353 err = i40e_vsi_configure(vsi);
4354 if (!err)
4355 err = i40e_up_complete(vsi);
4356
4357 return err;
4358}
4359
4360/**
4361 * i40e_down - Shutdown the connection processing
4362 * @vsi: the VSI being stopped
4363 **/
4364void i40e_down(struct i40e_vsi *vsi)
4365{
4366 int i;
4367
4368 /* It is assumed that the caller of this function
4369 * sets the vsi->state __I40E_DOWN bit.
4370 */
4371 if (vsi->netdev) {
4372 netif_carrier_off(vsi->netdev);
4373 netif_tx_disable(vsi->netdev);
4374 }
4375 i40e_vsi_disable_irq(vsi);
4376 i40e_vsi_control_rings(vsi, false);
4377 i40e_napi_disable_all(vsi);
4378
4379 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4380 i40e_clean_tx_ring(vsi->tx_rings[i]);
4381 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4382 }
4383}
4384
4385/**
4386 * i40e_setup_tc - configure multiple traffic classes
4387 * @netdev: net device to configure
4388 * @tc: number of traffic classes to enable
4389 **/
4390static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4391{
4392 struct i40e_netdev_priv *np = netdev_priv(netdev);
4393 struct i40e_vsi *vsi = np->vsi;
4394 struct i40e_pf *pf = vsi->back;
4395 u8 enabled_tc = 0;
4396 int ret = -EINVAL;
4397 int i;
4398
4399 /* Check if DCB enabled to continue */
4400 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4401 netdev_info(netdev, "DCB is not enabled for adapter\n");
4402 goto exit;
4403 }
4404
4405 /* Check if MFP enabled */
4406 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4407 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4408 goto exit;
4409 }
4410
4411 /* Check whether tc count is within enabled limit */
4412 if (tc > i40e_pf_get_num_tc(pf)) {
4413 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4414 goto exit;
4415 }
4416
4417 /* Generate TC map for number of tc requested */
4418 for (i = 0; i < tc; i++)
4419 enabled_tc |= (1 << i);
4420
4421 /* Requesting same TC configuration as already enabled */
4422 if (enabled_tc == vsi->tc_config.enabled_tc)
4423 return 0;
4424
4425 /* Quiesce VSI queues */
4426 i40e_quiesce_vsi(vsi);
4427
4428 /* Configure VSI for enabled TCs */
4429 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4430 if (ret) {
4431 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4432 vsi->seid);
4433 goto exit;
4434 }
4435
4436 /* Unquiesce VSI */
4437 i40e_unquiesce_vsi(vsi);
4438
4439exit:
4440 return ret;
4441}
4442
4443/**
4444 * i40e_open - Called when a network interface is made active
4445 * @netdev: network interface device structure
4446 *
4447 * The open entry point is called when a network interface is made
4448 * active by the system (IFF_UP). At this point all resources needed
4449 * for transmit and receive operations are allocated, the interrupt
4450 * handler is registered with the OS, the netdev watchdog subtask is
4451 * enabled, and the stack is notified that the interface is ready.
4452 *
4453 * Returns 0 on success, negative value on failure
4454 **/
4455static int i40e_open(struct net_device *netdev)
4456{
4457 struct i40e_netdev_priv *np = netdev_priv(netdev);
4458 struct i40e_vsi *vsi = np->vsi;
4459 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4460 int err;
4461
4eb3f768
SN		 4462 /* disallow open during test or if eeprom is broken */
4463 if (test_bit(__I40E_TESTING, &pf->state) ||
4464 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4465 return -EBUSY;
4466
4467 netif_carrier_off(netdev);
4468
6c167f58
EK		 4469 err = i40e_vsi_open(vsi);
4470 if (err)
4471 return err;
4472
059dab69
JB		 4473 /* configure global TSO hardware offload settings */
4474 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4475 TCP_FLAG_FIN) >> 16);
4476 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4477 TCP_FLAG_FIN |
4478 TCP_FLAG_CWR) >> 16);
4479 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4480
6c167f58
EK		 4481#ifdef CONFIG_I40E_VXLAN
4482 vxlan_get_rx_port(netdev);
4483#endif
4484
4485 return 0;
4486}
4487
4488/**
4489 * i40e_vsi_open -
4490 * @vsi: the VSI to open
4491 *
4492 * Finish initialization of the VSI.
4493 *
4494 * Returns 0 on success, negative value on failure
4495 **/
4496int i40e_vsi_open(struct i40e_vsi *vsi)
4497{
4498 struct i40e_pf *pf = vsi->back;
4499 char int_name[IFNAMSIZ];
4500 int err;
4501
41c445ff
JB		 4502 /* allocate descriptors */
4503 err = i40e_vsi_setup_tx_resources(vsi);
4504 if (err)
4505 goto err_setup_tx;
4506 err = i40e_vsi_setup_rx_resources(vsi);
4507 if (err)
4508 goto err_setup_rx;
4509
4510 err = i40e_vsi_configure(vsi);
4511 if (err)
4512 goto err_setup_rx;
4513
c22e3c6c
SN		 4514 if (vsi->netdev) {
4515 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4516 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4517 err = i40e_vsi_request_irq(vsi, int_name);
4518 if (err)
4519 goto err_setup_rx;
41c445ff 4520
c22e3c6c
SN		 4521 /* Notify the stack of the actual queue counts. */
4522 err = netif_set_real_num_tx_queues(vsi->netdev,
4523 vsi->num_queue_pairs);
4524 if (err)
4525 goto err_set_queues;
25946ddb 4526
c22e3c6c
SN		 4527 err = netif_set_real_num_rx_queues(vsi->netdev,
4528 vsi->num_queue_pairs);
4529 if (err)
4530 goto err_set_queues;
8a9eb7d3
SN		 4531
4532 } else if (vsi->type == I40E_VSI_FDIR) {
4533 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4534 dev_driver_string(&pf->pdev->dev));
4535 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4536 } else {
ce9ccb17 4537 err = -EINVAL;
6c167f58
EK		 4538 goto err_setup_rx;
4539 }
25946ddb 4540
41c445ff
JB		 4541 err = i40e_up_complete(vsi);
4542 if (err)
4543 goto err_up_complete;
4544
41c445ff
JB		 4545 return 0;
4546
4547err_up_complete:
4548 i40e_down(vsi);
25946ddb 4549err_set_queues:
41c445ff
JB		 4550 i40e_vsi_free_irq(vsi);
4551err_setup_rx:
4552 i40e_vsi_free_rx_resources(vsi);
4553err_setup_tx:
4554 i40e_vsi_free_tx_resources(vsi);
4555 if (vsi == pf->vsi[pf->lan_vsi])
4556 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4557
4558 return err;
4559}
4560
17a73f6b
JG		 4561/**
4562 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4563 * @pf: Pointer to pf
4564 *
4565 * This function destroys the hlist where all the Flow Director
4566 * filters were saved.
4567 **/
4568static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4569{
4570 struct i40e_fdir_filter *filter;
4571 struct hlist_node *node2;
4572
4573 hlist_for_each_entry_safe(filter, node2,
4574 &pf->fdir_filter_list, fdir_node) {
4575 hlist_del(&filter->fdir_node);
4576 kfree(filter);
4577 }
4578 pf->fdir_pf_active_filters = 0;
4579}
4580
41c445ff
JB		 4581/**
4582 * i40e_close - Disables a network interface
4583 * @netdev: network interface device structure
4584 *
4585 * The close entry point is called when an interface is de-activated
4586 * by the OS. The hardware is still under the driver's control, but
4587 * this netdev interface is disabled.
4588 *
4589 * Returns 0, this is not allowed to fail
4590 **/
4591static int i40e_close(struct net_device *netdev)
4592{
4593 struct i40e_netdev_priv *np = netdev_priv(netdev);
4594 struct i40e_vsi *vsi = np->vsi;
4595
90ef8d47 4596 i40e_vsi_close(vsi);
41c445ff
JB		 4597
4598 return 0;
4599}
4600
4601/**
4602 * i40e_do_reset - Start a PF or Core Reset sequence
4603 * @pf: board private structure
4604 * @reset_flags: which reset is requested
4605 *
4606 * The essential difference in resets is that the PF Reset
4607 * doesn't clear the packet buffers, doesn't reset the PE
4608 * firmware, and doesn't bother the other PFs on the chip.
4609 **/
4610void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4611{
4612 u32 val;
4613
4614 WARN_ON(in_interrupt());
4615
263fc48f
MW		 4616 if (i40e_check_asq_alive(&pf->hw))
4617 i40e_vc_notify_reset(pf);
4618
41c445ff
JB		 4619 /* do the biggest reset indicated */
4620 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4621
4622 /* Request a Global Reset
4623 *
4624 * This will start the chip's countdown to the actual full
4625 * chip reset event, and a warning interrupt to be sent
4626 * to all PFs, including the requestor. Our handler
4627 * for the warning interrupt will deal with the shutdown
4628 * and recovery of the switch setup.
4629 */
69bfb110 4630 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4631 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4632 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4633 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4634
4635 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4636
4637 /* Request a Core Reset
4638 *
4639 * Same as Global Reset, except does *not* include the MAC/PHY
4640 */
69bfb110 4641 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4642 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4643 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4644 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4645 i40e_flush(&pf->hw);
4646
7823fe34
SN		 4647 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4648
4649 /* Request a Firmware Reset
4650 *
4651 * Same as Global reset, plus restarting the
4652 * embedded firmware engine.
4653 */
4654 /* enable EMP Reset */
4655 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4656 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4657 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4658
4659 /* force the reset */
4660 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4661 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4662 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4663 i40e_flush(&pf->hw);
4664
41c445ff
JB		 4665 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4666
4667 /* Request a PF Reset
4668 *
4669 * Resets only the PF-specific registers
4670 *
4671 * This goes directly to the tear-down and rebuild of
4672 * the switch, since we need to do all the recovery as
4673 * for the Core Reset.
4674 */
69bfb110 4675 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4676 i40e_handle_reset_warning(pf);
4677
4678 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4679 int v;
4680
4681 /* Find the VSI(s) that requested a re-init */
4682 dev_info(&pf->pdev->dev,
4683 "VSI reinit requested\n");
505682cd 4684 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4685 struct i40e_vsi *vsi = pf->vsi[v];
4686 if (vsi != NULL &&
4687 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4688 i40e_vsi_reinit_locked(pf->vsi[v]);
4689 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4690 }
4691 }
4692
b5d06f05
NP		 4693 /* no further action needed, so return now */
4694 return;
4695 } else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {
4696 int v;
4697
4698 /* Find the VSI(s) that needs to be brought down */
4699 dev_info(&pf->pdev->dev, "VSI down requested\n");
4700 for (v = 0; v < pf->num_alloc_vsi; v++) {
4701 struct i40e_vsi *vsi = pf->vsi[v];
4702 if (vsi != NULL &&
4703 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
4704 set_bit(__I40E_DOWN, &vsi->state);
4705 i40e_down(vsi);
4706 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
4707 }
4708 }
4709
41c445ff
JB		 4710 /* no further action needed, so return now */
4711 return;
4712 } else {
4713 dev_info(&pf->pdev->dev,
4714 "bad reset request 0x%08x\n", reset_flags);
4715 return;
4716 }
4717}
4718
4e3b35b0
NP		 4719#ifdef CONFIG_I40E_DCB
4720/**
4721 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4722 * @pf: board private structure
4723 * @old_cfg: current DCB config
4724 * @new_cfg: new DCB config
4725 **/
4726bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4727 struct i40e_dcbx_config *old_cfg,
4728 struct i40e_dcbx_config *new_cfg)
4729{
4730 bool need_reconfig = false;
4731
4732 /* Check if ETS configuration has changed */
4733 if (memcmp(&new_cfg->etscfg,
4734 &old_cfg->etscfg,
4735 sizeof(new_cfg->etscfg))) {
4736 /* If Priority Table has changed reconfig is needed */
4737 if (memcmp(&new_cfg->etscfg.prioritytable,
4738 &old_cfg->etscfg.prioritytable,
4739 sizeof(new_cfg->etscfg.prioritytable))) {
4740 need_reconfig = true;
69bfb110 4741 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4742 }
4743
4744 if (memcmp(&new_cfg->etscfg.tcbwtable,
4745 &old_cfg->etscfg.tcbwtable,
4746 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4747 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4748
4749 if (memcmp(&new_cfg->etscfg.tsatable,
4750 &old_cfg->etscfg.tsatable,
4751 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4752 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4753 }
4754
4755 /* Check if PFC configuration has changed */
4756 if (memcmp(&new_cfg->pfc,
4757 &old_cfg->pfc,
4758 sizeof(new_cfg->pfc))) {
4759 need_reconfig = true;
69bfb110 4760 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4761 }
4762
4763 /* Check if APP Table has changed */
4764 if (memcmp(&new_cfg->app,
4765 &old_cfg->app,
3d9667a9 4766 sizeof(new_cfg->app))) {
4e3b35b0 4767 need_reconfig = true;
69bfb110 4768 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4769 }
4e3b35b0
NP		 4770
4771 return need_reconfig;
4772}
4773
4774/**
4775 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4776 * @pf: board private structure
4777 * @e: event info posted on ARQ
4778 **/
4779static int i40e_handle_lldp_event(struct i40e_pf *pf,
4780 struct i40e_arq_event_info *e)
4781{
4782 struct i40e_aqc_lldp_get_mib *mib =
4783 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4784 struct i40e_hw *hw = &pf->hw;
4785 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4786 struct i40e_dcbx_config tmp_dcbx_cfg;
4787 bool need_reconfig = false;
4788 int ret = 0;
4789 u8 type;
4790
4d9b6043
NP		 4791 /* Not DCB capable or capability disabled */
4792 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
4793 return ret;
4794
4e3b35b0
NP		 4795 /* Ignore if event is not for Nearest Bridge */
4796 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4797 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4798 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4799 return ret;
4800
4801 /* Check MIB Type and return if event for Remote MIB update */
4802 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4803 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4804 /* Update the remote cached instance and return */
4805 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4806 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4807 &hw->remote_dcbx_config);
4808 goto exit;
4809 }
4810
4811 /* Convert/store the DCBX data from LLDPDU temporarily */
4812 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4813 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4814 if (ret) {
4815 /* Error in LLDPDU parsing return */
4816 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4817 goto exit;
4818 }
4819
4820 /* No change detected in DCBX configs */
4821 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4822 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4823 goto exit;
4824 }
4825
4826 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4827
4828 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4829
4830 /* Overwrite the new configuration */
4831 *dcbx_cfg = tmp_dcbx_cfg;
4832
4833 if (!need_reconfig)
4834 goto exit;
4835
4d9b6043
NP		 4836 /* Enable DCB tagging only when more than one TC */
4837 if (i40e_dcb_get_num_tc(dcbx_cfg) > 1)
4838 pf->flags |= I40E_FLAG_DCB_ENABLED;
4839 else
4840 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
4841
4e3b35b0
NP		 4842 /* Reconfiguration needed quiesce all VSIs */
4843 i40e_pf_quiesce_all_vsi(pf);
4844
4845 /* Changes in configuration update VEB/VSI */
4846 i40e_dcb_reconfigure(pf);
4847
4848 i40e_pf_unquiesce_all_vsi(pf);
4849exit:
4850 return ret;
4851}
4852#endif /* CONFIG_I40E_DCB */
4853
23326186
ASJ		 4854/**
4855 * i40e_do_reset_safe - Protected reset path for userland calls.
4856 * @pf: board private structure
4857 * @reset_flags: which reset is requested
4858 *
4859 **/
4860void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4861{
4862 rtnl_lock();
4863 i40e_do_reset(pf, reset_flags);
4864 rtnl_unlock();
4865}
4866
41c445ff
JB		 4867/**
4868 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4869 * @pf: board private structure
4870 * @e: event info posted on ARQ
4871 *
4872 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4873 * and VF queues
4874 **/
4875static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4876 struct i40e_arq_event_info *e)
4877{
4878 struct i40e_aqc_lan_overflow *data =
4879 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4880 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4881 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4882 struct i40e_hw *hw = &pf->hw;
4883 struct i40e_vf *vf;
4884 u16 vf_id;
4885
69bfb110
JB		 4886 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4887 queue, qtx_ctl);
41c445ff
JB		 4888
4889 /* Queue belongs to VF, find the VF and issue VF reset */
4890 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4891 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4892 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4893 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4894 vf_id -= hw->func_caps.vf_base_id;
4895 vf = &pf->vf[vf_id];
4896 i40e_vc_notify_vf_reset(vf);
4897 /* Allow VF to process pending reset notification */
4898 msleep(20);
4899 i40e_reset_vf(vf, false);
4900 }
4901}
4902
4903/**
4904 * i40e_service_event_complete - Finish up the service event
4905 * @pf: board private structure
4906 **/
4907static void i40e_service_event_complete(struct i40e_pf *pf)
4908{
4909 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4910
4911 /* flush memory to make sure state is correct before next watchog */
4e857c58 4912 smp_mb__before_atomic();
41c445ff
JB		 4913 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4914}
4915
55a5e60b
ASJ		 4916/**
4917 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4918 * @pf: board private structure
4919 **/
4920int i40e_get_current_fd_count(struct i40e_pf *pf)
4921{
4922 int val, fcnt_prog;
4923 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4924 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4925 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4926 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4927 return fcnt_prog;
4928}
4929
4930/**
4931 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4932 * @pf: board private structure
4933 **/
4934void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4935{
4936 u32 fcnt_prog, fcnt_avail;
4937
4938 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4939 * to re-enable
4940 */
4941 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4942 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4943 return;
4944 fcnt_prog = i40e_get_current_fd_count(pf);
89132783 4945 fcnt_avail = i40e_get_fd_cnt_all(pf);
55a5e60b
ASJ		 4946 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4947 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4948 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4949 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4950 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4951 }
4952 }
4953 /* Wait for some more space to be available to turn on ATR */
4954 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4955 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4956 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4957 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4958 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4959 }
4960 }
4961}
4962
41c445ff
JB		 4963/**
4964 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4965 * @pf: board private structure
4966 **/
4967static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4968{
4969 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4970 return;
4971
41c445ff
JB		 4972 /* if interface is down do nothing */
4973 if (test_bit(__I40E_DOWN, &pf->state))
4974 return;
55a5e60b
ASJ		 4975 i40e_fdir_check_and_reenable(pf);
4976
4977 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4978 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4979 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4980}
4981
4982/**
4983 * i40e_vsi_link_event - notify VSI of a link event
4984 * @vsi: vsi to be notified
4985 * @link_up: link up or down
4986 **/
4987static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4988{
4989 if (!vsi)
4990 return;
4991
4992 switch (vsi->type) {
4993 case I40E_VSI_MAIN:
4994 if (!vsi->netdev || !vsi->netdev_registered)
4995 break;
4996
4997 if (link_up) {
4998 netif_carrier_on(vsi->netdev);
4999 netif_tx_wake_all_queues(vsi->netdev);
5000 } else {
5001 netif_carrier_off(vsi->netdev);
5002 netif_tx_stop_all_queues(vsi->netdev);
5003 }
5004 break;
5005
5006 case I40E_VSI_SRIOV:
5007 break;
5008
5009 case I40E_VSI_VMDQ2:
5010 case I40E_VSI_CTRL:
5011 case I40E_VSI_MIRROR:
5012 default:
5013 /* there is no notification for other VSIs */
5014 break;
5015 }
5016}
5017
5018/**
5019 * i40e_veb_link_event - notify elements on the veb of a link event
5020 * @veb: veb to be notified
5021 * @link_up: link up or down
5022 **/
5023static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5024{
5025 struct i40e_pf *pf;
5026 int i;
5027
5028 if (!veb || !veb->pf)
5029 return;
5030 pf = veb->pf;
5031
5032 /* depth first... */
5033 for (i = 0; i < I40E_MAX_VEB; i++)
5034 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5035 i40e_veb_link_event(pf->veb[i], link_up);
5036
5037 /* ... now the local VSIs */
505682cd 5038 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5039 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5040 i40e_vsi_link_event(pf->vsi[i], link_up);
5041}
5042
5043/**
5044 * i40e_link_event - Update netif_carrier status
5045 * @pf: board private structure
5046 **/
5047static void i40e_link_event(struct i40e_pf *pf)
5048{
5049 bool new_link, old_link;
5050
5051 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
5052 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
5053
5054 if (new_link == old_link)
5055 return;
6d779b41 5056 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 5057 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 5058
5059 /* Notify the base of the switch tree connected to
5060 * the link. Floating VEBs are not notified.
5061 */
5062 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
5063 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
5064 else
5065 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
5066
5067 if (pf->vf)
5068 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 5069
5070 if (pf->flags & I40E_FLAG_PTP)
5071 i40e_ptp_set_increment(pf);
41c445ff
JB		 5072}
5073
5074/**
5075 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
5076 * @pf: board private structure
5077 *
5078 * Set the per-queue flags to request a check for stuck queues in the irq
5079 * clean functions, then force interrupts to be sure the irq clean is called.
5080 **/
5081static void i40e_check_hang_subtask(struct i40e_pf *pf)
5082{
5083 int i, v;
5084
5085 /* If we're down or resetting, just bail */
5086 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
5087 return;
5088
5089 /* for each VSI/netdev
5090 * for each Tx queue
5091 * set the check flag
5092 * for each q_vector
5093 * force an interrupt
5094 */
505682cd 5095 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5096 struct i40e_vsi *vsi = pf->vsi[v];
5097 int armed = 0;
5098
5099 if (!pf->vsi[v] ||
5100 test_bit(__I40E_DOWN, &vsi->state) ||
5101 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
5102 continue;
5103
5104 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 5105 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 5106 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 5107 &vsi->tx_rings[i]->state))
41c445ff
JB		 5108 armed++;
5109 }
5110
5111 if (armed) {
5112 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5113 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5114 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5115 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5116 } else {
5117 u16 vec = vsi->base_vector - 1;
5118 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5119 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5120 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5121 wr32(&vsi->back->hw,
5122 I40E_PFINT_DYN_CTLN(vec), val);
5123 }
5124 i40e_flush(&vsi->back->hw);
5125 }
5126 }
5127}
5128
5129/**
5130 * i40e_watchdog_subtask - Check and bring link up
5131 * @pf: board private structure
5132 **/
5133static void i40e_watchdog_subtask(struct i40e_pf *pf)
5134{
5135 int i;
5136
5137 /* if interface is down do nothing */
5138 if (test_bit(__I40E_DOWN, &pf->state) ||
5139 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5140 return;
5141
5142 /* Update the stats for active netdevs so the network stack
5143 * can look at updated numbers whenever it cares to
5144 */
505682cd 5145 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5146 if (pf->vsi[i] && pf->vsi[i]->netdev)
5147 i40e_update_stats(pf->vsi[i]);
5148
5149 /* Update the stats for the active switching components */
5150 for (i = 0; i < I40E_MAX_VEB; i++)
5151 if (pf->veb[i])
5152 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5153
5154 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5155}
5156
5157/**
5158 * i40e_reset_subtask - Set up for resetting the device and driver
5159 * @pf: board private structure
5160 **/
5161static void i40e_reset_subtask(struct i40e_pf *pf)
5162{
5163 u32 reset_flags = 0;
5164
23326186 5165 rtnl_lock();
41c445ff
JB		 5166 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5167 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5168 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5169 }
5170 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5171 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5172 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5173 }
5174 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5175 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5176 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5177 }
5178 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5179 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5180 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5181 }
b5d06f05
NP		 5182 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
5183 reset_flags |= (1 << __I40E_DOWN_REQUESTED);
5184 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
5185 }
41c445ff
JB		 5186
5187 /* If there's a recovery already waiting, it takes
5188 * precedence before starting a new reset sequence.
5189 */
5190 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5191 i40e_handle_reset_warning(pf);
23326186 5192 goto unlock;
41c445ff
JB		 5193 }
5194
5195 /* If we're already down or resetting, just bail */
5196 if (reset_flags &&
5197 !test_bit(__I40E_DOWN, &pf->state) &&
5198 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5199 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5200
5201unlock:
5202 rtnl_unlock();
41c445ff
JB		 5203}
5204
5205/**
5206 * i40e_handle_link_event - Handle link event
5207 * @pf: board private structure
5208 * @e: event info posted on ARQ
5209 **/
5210static void i40e_handle_link_event(struct i40e_pf *pf,
5211 struct i40e_arq_event_info *e)
5212{
5213 struct i40e_hw *hw = &pf->hw;
5214 struct i40e_aqc_get_link_status *status =
5215 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5216 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5217
5218 /* save off old link status information */
5219 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5220 sizeof(pf->hw.phy.link_info_old));
5221
5222 /* update link status */
5223 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5224 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5225 hw_link_info->link_info = status->link_info;
5226 hw_link_info->an_info = status->an_info;
5227 hw_link_info->ext_info = status->ext_info;
5228 hw_link_info->lse_enable =
5229 le16_to_cpu(status->command_flags) &
5230 I40E_AQ_LSE_ENABLE;
5231
5232 /* process the event */
5233 i40e_link_event(pf);
5234
5235 /* Do a new status request to re-enable LSE reporting
5236 * and load new status information into the hw struct,
5237 * then see if the status changed while processing the
5238 * initial event.
5239 */
5240 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5241 i40e_link_event(pf);
5242}
5243
5244/**
5245 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5246 * @pf: board private structure
5247 **/
5248static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5249{
5250 struct i40e_arq_event_info event;
5251 struct i40e_hw *hw = &pf->hw;
5252 u16 pending, i = 0;
5253 i40e_status ret;
5254 u16 opcode;
86df242b 5255 u32 oldval;
41c445ff
JB		 5256 u32 val;
5257
5258 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5259 return;
5260
86df242b
SN		 5261 /* check for error indications */
5262 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5263 oldval = val;
5264 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5265 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5266 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5267 }
5268 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5269 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5270 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5271 }
5272 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5273 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5274 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5275 }
5276 if (oldval != val)
5277 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5278
5279 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5280 oldval = val;
5281 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5282 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5283 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5284 }
5285 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5286 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5287 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5288 }
5289 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5290 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5291 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5292 }
5293 if (oldval != val)
5294 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5295
3197ce22 5296 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5297 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5298 if (!event.msg_buf)
5299 return;
5300
5301 do {
2f019123 5302 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5303 ret = i40e_clean_arq_element(hw, &event, &pending);
5304 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5305 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5306 break;
5307 } else if (ret) {
5308 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5309 break;
5310 }
5311
5312 opcode = le16_to_cpu(event.desc.opcode);
5313 switch (opcode) {
5314
5315 case i40e_aqc_opc_get_link_status:
5316 i40e_handle_link_event(pf, &event);
5317 break;
5318 case i40e_aqc_opc_send_msg_to_pf:
5319 ret = i40e_vc_process_vf_msg(pf,
5320 le16_to_cpu(event.desc.retval),
5321 le32_to_cpu(event.desc.cookie_high),
5322 le32_to_cpu(event.desc.cookie_low),
5323 event.msg_buf,
5324 event.msg_size);
5325 break;
5326 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5327 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5328#ifdef CONFIG_I40E_DCB
5329 rtnl_lock();
5330 ret = i40e_handle_lldp_event(pf, &event);
5331 rtnl_unlock();
5332#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5333 break;
5334 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5335 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5336 i40e_handle_lan_overflow_event(pf, &event);
5337 break;
0467bc91
SN		 5338 case i40e_aqc_opc_send_msg_to_peer:
5339 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5340 break;
41c445ff
JB		 5341 default:
5342 dev_info(&pf->pdev->dev,
0467bc91
SN		 5343 "ARQ Error: Unknown event 0x%04x received\n",
5344 opcode);
41c445ff
JB		 5345 break;
5346 }
5347 } while (pending && (i++ < pf->adminq_work_limit));
5348
5349 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5350 /* re-enable Admin queue interrupt cause */
5351 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5352 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5353 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5354 i40e_flush(hw);
5355
5356 kfree(event.msg_buf);
5357}
5358
4eb3f768
SN		 5359/**
5360 * i40e_verify_eeprom - make sure eeprom is good to use
5361 * @pf: board private structure
5362 **/
5363static void i40e_verify_eeprom(struct i40e_pf *pf)
5364{
5365 int err;
5366
5367 err = i40e_diag_eeprom_test(&pf->hw);
5368 if (err) {
5369 /* retry in case of garbage read */
5370 err = i40e_diag_eeprom_test(&pf->hw);
5371 if (err) {
5372 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5373 err);
5374 set_bit(__I40E_BAD_EEPROM, &pf->state);
5375 }
5376 }
5377
5378 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5379 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5380 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5381 }
5382}
5383
41c445ff
JB		 5384/**
5385 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5386 * @veb: pointer to the VEB instance
5387 *
5388 * This is a recursive function that first builds the attached VSIs then
5389 * recurses in to build the next layer of VEB. We track the connections
5390 * through our own index numbers because the seid's from the HW could
5391 * change across the reset.
5392 **/
5393static int i40e_reconstitute_veb(struct i40e_veb *veb)
5394{
5395 struct i40e_vsi *ctl_vsi = NULL;
5396 struct i40e_pf *pf = veb->pf;
5397 int v, veb_idx;
5398 int ret;
5399
5400 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5401 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5402 if (pf->vsi[v] &&
5403 pf->vsi[v]->veb_idx == veb->idx &&
5404 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5405 ctl_vsi = pf->vsi[v];
5406 break;
5407 }
5408 }
5409 if (!ctl_vsi) {
5410 dev_info(&pf->pdev->dev,
5411 "missing owner VSI for veb_idx %d\n", veb->idx);
5412 ret = -ENOENT;
5413 goto end_reconstitute;
5414 }
5415 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5416 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5417 ret = i40e_add_vsi(ctl_vsi);
5418 if (ret) {
5419 dev_info(&pf->pdev->dev,
5420 "rebuild of owner VSI failed: %d\n", ret);
5421 goto end_reconstitute;
5422 }
5423 i40e_vsi_reset_stats(ctl_vsi);
5424
5425 /* create the VEB in the switch and move the VSI onto the VEB */
5426 ret = i40e_add_veb(veb, ctl_vsi);
5427 if (ret)
5428 goto end_reconstitute;
5429
5430 /* create the remaining VSIs attached to this VEB */
505682cd 5431 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5432 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5433 continue;
5434
5435 if (pf->vsi[v]->veb_idx == veb->idx) {
5436 struct i40e_vsi *vsi = pf->vsi[v];
5437 vsi->uplink_seid = veb->seid;
5438 ret = i40e_add_vsi(vsi);
5439 if (ret) {
5440 dev_info(&pf->pdev->dev,
5441 "rebuild of vsi_idx %d failed: %d\n",
5442 v, ret);
5443 goto end_reconstitute;
5444 }
5445 i40e_vsi_reset_stats(vsi);
5446 }
5447 }
5448
5449 /* create any VEBs attached to this VEB - RECURSION */
5450 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5451 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5452 pf->veb[veb_idx]->uplink_seid = veb->seid;
5453 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5454 if (ret)
5455 break;
5456 }
5457 }
5458
5459end_reconstitute:
5460 return ret;
5461}
5462
5463/**
5464 * i40e_get_capabilities - get info about the HW
5465 * @pf: the PF struct
5466 **/
5467static int i40e_get_capabilities(struct i40e_pf *pf)
5468{
5469 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5470 u16 data_size;
5471 int buf_len;
5472 int err;
5473
5474 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5475 do {
5476 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5477 if (!cap_buf)
5478 return -ENOMEM;
5479
5480 /* this loads the data into the hw struct for us */
5481 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5482 &data_size,
5483 i40e_aqc_opc_list_func_capabilities,
5484 NULL);
5485 /* data loaded, buffer no longer needed */
5486 kfree(cap_buf);
5487
5488 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5489 /* retry with a larger buffer */
5490 buf_len = data_size;
5491 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5492 dev_info(&pf->pdev->dev,
5493 "capability discovery failed: aq=%d\n",
5494 pf->hw.aq.asq_last_status);
5495 return -ENODEV;
5496 }
5497 } while (err);
5498
ac71b7ba
ASJ		 5499 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5500 (pf->hw.aq.fw_maj_ver < 2)) {
5501 pf->hw.func_caps.num_msix_vectors++;
5502 pf->hw.func_caps.num_msix_vectors_vf++;
5503 }
5504
41c445ff
JB		 5505 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5506 dev_info(&pf->pdev->dev,
5507 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5508 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5509 pf->hw.func_caps.num_msix_vectors,
5510 pf->hw.func_caps.num_msix_vectors_vf,
5511 pf->hw.func_caps.fd_filters_guaranteed,
5512 pf->hw.func_caps.fd_filters_best_effort,
5513 pf->hw.func_caps.num_tx_qp,
5514 pf->hw.func_caps.num_vsis);
5515
7134f9ce
JB		 5516#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5517 + pf->hw.func_caps.num_vfs)
5518 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5519 dev_info(&pf->pdev->dev,
5520 "got num_vsis %d, setting num_vsis to %d\n",
5521 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5522 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5523 }
5524
41c445ff
JB		 5525 return 0;
5526}
5527
cbf61325
ASJ		 5528static int i40e_vsi_clear(struct i40e_vsi *vsi);
5529
41c445ff 5530/**
cbf61325 5531 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5532 * @pf: board private structure
5533 **/
cbf61325 5534static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5535{
5536 struct i40e_vsi *vsi;
8a9eb7d3 5537 int i;
41c445ff 5538
407e063c
JB		 5539 /* quick workaround for an NVM issue that leaves a critical register
5540 * uninitialized
5541 */
5542 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
5543 static const u32 hkey[] = {
5544 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
5545 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
5546 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
5547 0x95b3a76d};
5548
5549 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
5550 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
5551 }
5552
cbf61325 5553 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5554 return;
5555
cbf61325 5556 /* find existing VSI and see if it needs configuring */
41c445ff 5557 vsi = NULL;
505682cd 5558 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5559 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5560 vsi = pf->vsi[i];
cbf61325
ASJ		 5561 break;
5562 }
5563 }
5564
5565 /* create a new VSI if none exists */
41c445ff 5566 if (!vsi) {
cbf61325
ASJ		 5567 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5568 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5569 if (!vsi) {
5570 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5571 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5572 return;
41c445ff 5573 }
cbf61325 5574 }
41c445ff 5575
8a9eb7d3 5576 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5577}
5578
5579/**
5580 * i40e_fdir_teardown - release the Flow Director resources
5581 * @pf: board private structure
5582 **/
5583static void i40e_fdir_teardown(struct i40e_pf *pf)
5584{
5585 int i;
5586
17a73f6b 5587 i40e_fdir_filter_exit(pf);
505682cd 5588 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5589 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5590 i40e_vsi_release(pf->vsi[i]);
5591 break;
5592 }
5593 }
5594}
5595
5596/**
f650a38b 5597 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5598 * @pf: board private structure
5599 *
f650a38b
ASJ		 5600 * Close up the VFs and other things in prep for pf Reset.
5601 **/
5602static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5603{
41c445ff 5604 struct i40e_hw *hw = &pf->hw;
60442dea 5605 i40e_status ret = 0;
41c445ff
JB		 5606 u32 v;
5607
5608 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5609 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5610 return 0;
41c445ff 5611
69bfb110 5612 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5613
41c445ff
JB		 5614 /* quiesce the VSIs and their queues that are not already DOWN */
5615 i40e_pf_quiesce_all_vsi(pf);
5616
505682cd 5617 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5618 if (pf->vsi[v])
5619 pf->vsi[v]->seid = 0;
5620 }
5621
5622 i40e_shutdown_adminq(&pf->hw);
5623
f650a38b 5624 /* call shutdown HMC */
60442dea
SN		 5625 if (hw->hmc.hmc_obj) {
5626 ret = i40e_shutdown_lan_hmc(hw);
5627 if (ret) {
5628 dev_warn(&pf->pdev->dev,
5629 "shutdown_lan_hmc failed: %d\n", ret);
5630 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5631 }
f650a38b
ASJ		 5632 }
5633 return ret;
5634}
5635
44033fac
JB		 5636/**
5637 * i40e_send_version - update firmware with driver version
5638 * @pf: PF struct
5639 */
5640static void i40e_send_version(struct i40e_pf *pf)
5641{
5642 struct i40e_driver_version dv;
5643
5644 dv.major_version = DRV_VERSION_MAJOR;
5645 dv.minor_version = DRV_VERSION_MINOR;
5646 dv.build_version = DRV_VERSION_BUILD;
5647 dv.subbuild_version = 0;
5648 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5649 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5650}
5651
f650a38b 5652/**
4dda12e6 5653 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5654 * @pf: board private structure
bc7d338f 5655 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5656 **/
bc7d338f 5657static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5658{
f650a38b
ASJ		 5659 struct i40e_hw *hw = &pf->hw;
5660 i40e_status ret;
5661 u32 v;
5662
41c445ff
JB		 5663 /* Now we wait for GRST to settle out.
5664 * We don't have to delete the VEBs or VSIs from the hw switch
5665 * because the reset will make them disappear.
5666 */
5667 ret = i40e_pf_reset(hw);
b5565400 5668 if (ret) {
41c445ff 5669 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5670 goto end_core_reset;
5671 }
41c445ff
JB		 5672 pf->pfr_count++;
5673
5674 if (test_bit(__I40E_DOWN, &pf->state))
5675 goto end_core_reset;
69bfb110 5676 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5677
5678 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5679 ret = i40e_init_adminq(&pf->hw);
5680 if (ret) {
5681 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5682 goto end_core_reset;
5683 }
5684
4eb3f768
SN		 5685 /* re-verify the eeprom if we just had an EMP reset */
5686 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5687 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5688 i40e_verify_eeprom(pf);
5689 }
5690
e78ac4bf 5691 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5692 ret = i40e_get_capabilities(pf);
5693 if (ret) {
5694 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5695 ret);
5696 goto end_core_reset;
5697 }
5698
41c445ff
JB		 5699 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5700 hw->func_caps.num_rx_qp,
5701 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5702 if (ret) {
5703 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5704 goto end_core_reset;
5705 }
5706 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5707 if (ret) {
5708 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5709 goto end_core_reset;
5710 }
5711
4e3b35b0
NP		 5712#ifdef CONFIG_I40E_DCB
5713 ret = i40e_init_pf_dcb(pf);
5714 if (ret) {
5715 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5716 goto end_core_reset;
5717 }
5718#endif /* CONFIG_I40E_DCB */
5719
41c445ff 5720 /* do basic switch setup */
bc7d338f 5721 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5722 if (ret)
5723 goto end_core_reset;
5724
5725 /* Rebuild the VSIs and VEBs that existed before reset.
5726 * They are still in our local switch element arrays, so only
5727 * need to rebuild the switch model in the HW.
5728 *
5729 * If there were VEBs but the reconstitution failed, we'll try
5730 * try to recover minimal use by getting the basic PF VSI working.
5731 */
5732 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5733 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5734 /* find the one VEB connected to the MAC, and find orphans */
5735 for (v = 0; v < I40E_MAX_VEB; v++) {
5736 if (!pf->veb[v])
5737 continue;
5738
5739 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5740 pf->veb[v]->uplink_seid == 0) {
5741 ret = i40e_reconstitute_veb(pf->veb[v]);
5742
5743 if (!ret)
5744 continue;
5745
5746 /* If Main VEB failed, we're in deep doodoo,
5747 * so give up rebuilding the switch and set up
5748 * for minimal rebuild of PF VSI.
5749 * If orphan failed, we'll report the error
5750 * but try to keep going.
5751 */
5752 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5753 dev_info(&pf->pdev->dev,
5754 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5755 ret);
5756 pf->vsi[pf->lan_vsi]->uplink_seid
5757 = pf->mac_seid;
5758 break;
5759 } else if (pf->veb[v]->uplink_seid == 0) {
5760 dev_info(&pf->pdev->dev,
5761 "rebuild of orphan VEB failed: %d\n",
5762 ret);
5763 }
5764 }
5765 }
5766 }
5767
5768 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5769 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5770 /* no VEB, so rebuild only the Main VSI */
5771 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5772 if (ret) {
5773 dev_info(&pf->pdev->dev,
5774 "rebuild of Main VSI failed: %d\n", ret);
5775 goto end_core_reset;
5776 }
5777 }
5778
5779 /* reinit the misc interrupt */
5780 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5781 ret = i40e_setup_misc_vector(pf);
5782
5783 /* restart the VSIs that were rebuilt and running before the reset */
5784 i40e_pf_unquiesce_all_vsi(pf);
5785
69f64b2b
MW		 5786 if (pf->num_alloc_vfs) {
5787 for (v = 0; v < pf->num_alloc_vfs; v++)
5788 i40e_reset_vf(&pf->vf[v], true);
5789 }
5790
41c445ff 5791 /* tell the firmware that we're starting */
44033fac 5792 i40e_send_version(pf);
41c445ff
JB		 5793
5794end_core_reset:
5795 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5796}
5797
f650a38b
ASJ		 5798/**
5799 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5800 * @pf: board private structure
5801 *
5802 * Close up the VFs and other things in prep for a Core Reset,
5803 * then get ready to rebuild the world.
5804 **/
5805static void i40e_handle_reset_warning(struct i40e_pf *pf)
5806{
5807 i40e_status ret;
5808
5809 ret = i40e_prep_for_reset(pf);
5810 if (!ret)
bc7d338f 5811 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5812}
5813
41c445ff
JB		 5814/**
5815 * i40e_handle_mdd_event
5816 * @pf: pointer to the pf structure
5817 *
5818 * Called from the MDD irq handler to identify possibly malicious vfs
5819 **/
5820static void i40e_handle_mdd_event(struct i40e_pf *pf)
5821{
5822 struct i40e_hw *hw = &pf->hw;
5823 bool mdd_detected = false;
5824 struct i40e_vf *vf;
5825 u32 reg;
5826 int i;
5827
5828 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5829 return;
5830
5831 /* find what triggered the MDD event */
5832 reg = rd32(hw, I40E_GL_MDET_TX);
5833 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 5834 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
5835 I40E_GL_MDET_TX_PF_NUM_SHIFT;
5836 u8 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
5837 I40E_GL_MDET_TX_VF_NUM_SHIFT;
5838 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT) >>
5839 I40E_GL_MDET_TX_EVENT_SHIFT;
5840 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
5841 I40E_GL_MDET_TX_QUEUE_SHIFT;
41c445ff 5842 dev_info(&pf->pdev->dev,
4c33f83a
ASJ		 5843 "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
5844 event, queue, pf_num, vf_num);
41c445ff
JB		 5845 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5846 mdd_detected = true;
5847 }
5848 reg = rd32(hw, I40E_GL_MDET_RX);
5849 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 5850 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
5851 I40E_GL_MDET_RX_FUNCTION_SHIFT;
5852 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT) >>
5853 I40E_GL_MDET_RX_EVENT_SHIFT;
5854 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
5855 I40E_GL_MDET_RX_QUEUE_SHIFT;
41c445ff 5856 dev_info(&pf->pdev->dev,
f29eaa3d 5857 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5858 event, queue, func);
5859 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5860 mdd_detected = true;
5861 }
5862
5863 /* see if one of the VFs needs its hand slapped */
5864 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5865 vf = &(pf->vf[i]);
5866 reg = rd32(hw, I40E_VP_MDET_TX(i));
5867 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5868 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5869 vf->num_mdd_events++;
5870 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5871 }
5872
5873 reg = rd32(hw, I40E_VP_MDET_RX(i));
5874 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5875 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5876 vf->num_mdd_events++;
5877 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5878 }
5879
5880 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5881 dev_info(&pf->pdev->dev,
5882 "Too many MDD events on VF %d, disabled\n", i);
5883 dev_info(&pf->pdev->dev,
5884 "Use PF Control I/F to re-enable the VF\n");
5885 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5886 }
5887 }
5888
5889 /* re-enable mdd interrupt cause */
5890 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5891 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5892 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5893 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5894 i40e_flush(hw);
5895}
5896
a1c9a9d9
JK		 5897#ifdef CONFIG_I40E_VXLAN
5898/**
5899 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5900 * @pf: board private structure
5901 **/
5902static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5903{
a1c9a9d9
JK		 5904 struct i40e_hw *hw = &pf->hw;
5905 i40e_status ret;
5906 u8 filter_index;
5907 __be16 port;
5908 int i;
5909
5910 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5911 return;
5912
5913 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5914
5915 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5916 if (pf->pending_vxlan_bitmap & (1 << i)) {
5917 pf->pending_vxlan_bitmap &= ~(1 << i);
5918 port = pf->vxlan_ports[i];
5919 ret = port ?
5920 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5921 I40E_AQC_TUNNEL_TYPE_VXLAN,
5922 &filter_index, NULL)
5923 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5924
5925 if (ret) {
5926 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5927 port ? "adding" : "deleting",
5928 ntohs(port), port ? i : i);
5929
5930 pf->vxlan_ports[i] = 0;
5931 } else {
5932 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5933 port ? "Added" : "Deleted",
5934 ntohs(port), port ? i : filter_index);
5935 }
5936 }
5937 }
5938}
5939
5940#endif
41c445ff
JB		 5941/**
5942 * i40e_service_task - Run the driver's async subtasks
5943 * @work: pointer to work_struct containing our data
5944 **/
5945static void i40e_service_task(struct work_struct *work)
5946{
5947 struct i40e_pf *pf = container_of(work,
5948 struct i40e_pf,
5949 service_task);
5950 unsigned long start_time = jiffies;
5951
5952 i40e_reset_subtask(pf);
5953 i40e_handle_mdd_event(pf);
5954 i40e_vc_process_vflr_event(pf);
5955 i40e_watchdog_subtask(pf);
5956 i40e_fdir_reinit_subtask(pf);
5957 i40e_check_hang_subtask(pf);
5958 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5959#ifdef CONFIG_I40E_VXLAN
5960 i40e_sync_vxlan_filters_subtask(pf);
5961#endif
41c445ff
JB		 5962 i40e_clean_adminq_subtask(pf);
5963
5964 i40e_service_event_complete(pf);
5965
5966 /* If the tasks have taken longer than one timer cycle or there
5967 * is more work to be done, reschedule the service task now
5968 * rather than wait for the timer to tick again.
5969 */
5970 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5971 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5972 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5973 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5974 i40e_service_event_schedule(pf);
5975}
5976
5977/**
5978 * i40e_service_timer - timer callback
5979 * @data: pointer to PF struct
5980 **/
5981static void i40e_service_timer(unsigned long data)
5982{
5983 struct i40e_pf *pf = (struct i40e_pf *)data;
5984
5985 mod_timer(&pf->service_timer,
5986 round_jiffies(jiffies + pf->service_timer_period));
5987 i40e_service_event_schedule(pf);
5988}
5989
5990/**
5991 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5992 * @vsi: the VSI being configured
5993 **/
5994static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5995{
5996 struct i40e_pf *pf = vsi->back;
5997
5998 switch (vsi->type) {
5999 case I40E_VSI_MAIN:
6000 vsi->alloc_queue_pairs = pf->num_lan_qps;
6001 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6002 I40E_REQ_DESCRIPTOR_MULTIPLE);
6003 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6004 vsi->num_q_vectors = pf->num_lan_msix;
6005 else
6006 vsi->num_q_vectors = 1;
6007
6008 break;
6009
6010 case I40E_VSI_FDIR:
6011 vsi->alloc_queue_pairs = 1;
6012 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
6013 I40E_REQ_DESCRIPTOR_MULTIPLE);
6014 vsi->num_q_vectors = 1;
6015 break;
6016
6017 case I40E_VSI_VMDQ2:
6018 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
6019 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6020 I40E_REQ_DESCRIPTOR_MULTIPLE);
6021 vsi->num_q_vectors = pf->num_vmdq_msix;
6022 break;
6023
6024 case I40E_VSI_SRIOV:
6025 vsi->alloc_queue_pairs = pf->num_vf_qps;
6026 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
6027 I40E_REQ_DESCRIPTOR_MULTIPLE);
6028 break;
6029
6030 default:
6031 WARN_ON(1);
6032 return -ENODATA;
6033 }
6034
6035 return 0;
6036}
6037
f650a38b
ASJ		 6038/**
6039 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
6040 * @type: VSI pointer
bc7d338f 6041 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 6042 *
6043 * On error: returns error code (negative)
6044 * On success: returns 0
6045 **/
bc7d338f 6046static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 6047{
6048 int size;
6049 int ret = 0;
6050
ac6c5e3d 6051 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 6052 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
6053 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
6054 if (!vsi->tx_rings)
6055 return -ENOMEM;
f650a38b
ASJ		 6056 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
6057
bc7d338f
ASJ		 6058 if (alloc_qvectors) {
6059 /* allocate memory for q_vector pointers */
6060 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
6061 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
6062 if (!vsi->q_vectors) {
6063 ret = -ENOMEM;
6064 goto err_vectors;
6065 }
f650a38b
ASJ		 6066 }
6067 return ret;
6068
6069err_vectors:
6070 kfree(vsi->tx_rings);
6071 return ret;
6072}
6073
41c445ff
JB		 6074/**
6075 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
6076 * @pf: board private structure
6077 * @type: type of VSI
6078 *
6079 * On error: returns error code (negative)
6080 * On success: returns vsi index in PF (positive)
6081 **/
6082static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
6083{
6084 int ret = -ENODEV;
6085 struct i40e_vsi *vsi;
6086 int vsi_idx;
6087 int i;
6088
6089 /* Need to protect the allocation of the VSIs at the PF level */
6090 mutex_lock(&pf->switch_mutex);
6091
6092 /* VSI list may be fragmented if VSI creation/destruction has
6093 * been happening. We can afford to do a quick scan to look
6094 * for any free VSIs in the list.
6095 *
6096 * find next empty vsi slot, looping back around if necessary
6097 */
6098 i = pf->next_vsi;
505682cd 6099 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 6100 i++;
505682cd 6101 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 6102 i = 0;
6103 while (i < pf->next_vsi && pf->vsi[i])
6104 i++;
6105 }
6106
505682cd 6107 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 6108 vsi_idx = i; /* Found one! */
6109 } else {
6110 ret = -ENODEV;
493fb300 6111 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 6112 }
6113 pf->next_vsi = ++i;
6114
6115 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
6116 if (!vsi) {
6117 ret = -ENOMEM;
493fb300 6118 goto unlock_pf;
41c445ff
JB		 6119 }
6120 vsi->type = type;
6121 vsi->back = pf;
6122 set_bit(__I40E_DOWN, &vsi->state);
6123 vsi->flags = 0;
6124 vsi->idx = vsi_idx;
6125 vsi->rx_itr_setting = pf->rx_itr_default;
6126 vsi->tx_itr_setting = pf->tx_itr_default;
6127 vsi->netdev_registered = false;
6128 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
6129 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 6130 vsi->irqs_ready = false;
41c445ff 6131
9f65e15b
AD		 6132 ret = i40e_set_num_rings_in_vsi(vsi);
6133 if (ret)
6134 goto err_rings;
6135
bc7d338f 6136 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6137 if (ret)
9f65e15b 6138 goto err_rings;
493fb300 6139
41c445ff
JB		 6140 /* Setup default MSIX irq handler for VSI */
6141 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6142
6143 pf->vsi[vsi_idx] = vsi;
6144 ret = vsi_idx;
493fb300
AD		 6145 goto unlock_pf;
6146
9f65e15b 6147err_rings:
493fb300
AD		 6148 pf->next_vsi = i - 1;
6149 kfree(vsi);
6150unlock_pf:
41c445ff
JB		 6151 mutex_unlock(&pf->switch_mutex);
6152 return ret;
6153}
6154
f650a38b
ASJ		 6155/**
6156 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6157 * @type: VSI pointer
bc7d338f 6158 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6159 *
6160 * On error: returns error code (negative)
6161 * On success: returns 0
6162 **/
bc7d338f 6163static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6164{
6165 /* free the ring and vector containers */
bc7d338f
ASJ		 6166 if (free_qvectors) {
6167 kfree(vsi->q_vectors);
6168 vsi->q_vectors = NULL;
6169 }
f650a38b
ASJ		 6170 kfree(vsi->tx_rings);
6171 vsi->tx_rings = NULL;
6172 vsi->rx_rings = NULL;
6173}
6174
41c445ff
JB		 6175/**
6176 * i40e_vsi_clear - Deallocate the VSI provided
6177 * @vsi: the VSI being un-configured
6178 **/
6179static int i40e_vsi_clear(struct i40e_vsi *vsi)
6180{
6181 struct i40e_pf *pf;
6182
6183 if (!vsi)
6184 return 0;
6185
6186 if (!vsi->back)
6187 goto free_vsi;
6188 pf = vsi->back;
6189
6190 mutex_lock(&pf->switch_mutex);
6191 if (!pf->vsi[vsi->idx]) {
6192 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6193 vsi->idx, vsi->idx, vsi, vsi->type);
6194 goto unlock_vsi;
6195 }
6196
6197 if (pf->vsi[vsi->idx] != vsi) {
6198 dev_err(&pf->pdev->dev,
6199 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6200 pf->vsi[vsi->idx]->idx,
6201 pf->vsi[vsi->idx],
6202 pf->vsi[vsi->idx]->type,
6203 vsi->idx, vsi, vsi->type);
6204 goto unlock_vsi;
6205 }
6206
6207 /* updates the pf for this cleared vsi */
6208 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6209 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6210
bc7d338f 6211 i40e_vsi_free_arrays(vsi, true);
493fb300 6212
41c445ff
JB		 6213 pf->vsi[vsi->idx] = NULL;
6214 if (vsi->idx < pf->next_vsi)
6215 pf->next_vsi = vsi->idx;
6216
6217unlock_vsi:
6218 mutex_unlock(&pf->switch_mutex);
6219free_vsi:
6220 kfree(vsi);
6221
6222 return 0;
6223}
6224
9f65e15b
AD		 6225/**
6226 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6227 * @vsi: the VSI being cleaned
6228 **/
be1d5eea 6229static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6230{
6231 int i;
6232
8e9dca53 6233 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6234 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6235 kfree_rcu(vsi->tx_rings[i], rcu);
6236 vsi->tx_rings[i] = NULL;
6237 vsi->rx_rings[i] = NULL;
6238 }
be1d5eea 6239 }
9f65e15b
AD		 6240}
6241
41c445ff
JB		 6242/**
6243 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6244 * @vsi: the VSI being configured
6245 **/
6246static int i40e_alloc_rings(struct i40e_vsi *vsi)
6247{
e7046ee1 6248 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6249 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6250 int i;
6251
41c445ff 6252 /* Set basic values in the rings to be used later during open() */
d7397644 6253 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6254 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6255 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6256 if (!tx_ring)
6257 goto err_out;
41c445ff
JB		 6258
6259 tx_ring->queue_index = i;
6260 tx_ring->reg_idx = vsi->base_queue + i;
6261 tx_ring->ring_active = false;
6262 tx_ring->vsi = vsi;
6263 tx_ring->netdev = vsi->netdev;
6264 tx_ring->dev = &pf->pdev->dev;
6265 tx_ring->count = vsi->num_desc;
6266 tx_ring->size = 0;
6267 tx_ring->dcb_tc = 0;
9f65e15b 6268 vsi->tx_rings[i] = tx_ring;
41c445ff 6269
9f65e15b 6270 rx_ring = &tx_ring[1];
41c445ff
JB		 6271 rx_ring->queue_index = i;
6272 rx_ring->reg_idx = vsi->base_queue + i;
6273 rx_ring->ring_active = false;
6274 rx_ring->vsi = vsi;
6275 rx_ring->netdev = vsi->netdev;
6276 rx_ring->dev = &pf->pdev->dev;
6277 rx_ring->count = vsi->num_desc;
6278 rx_ring->size = 0;
6279 rx_ring->dcb_tc = 0;
6280 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6281 set_ring_16byte_desc_enabled(rx_ring);
6282 else
6283 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6284 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6285 }
6286
6287 return 0;
9f65e15b
AD		 6288
6289err_out:
6290 i40e_vsi_clear_rings(vsi);
6291 return -ENOMEM;
41c445ff
JB		 6292}
6293
6294/**
6295 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6296 * @pf: board private structure
6297 * @vectors: the number of MSI-X vectors to request
6298 *
6299 * Returns the number of vectors reserved, or error
6300 **/
6301static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6302{
7b37f376
AG		 6303 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6304 I40E_MIN_MSIX, vectors);
6305 if (vectors < 0) {
41c445ff 6306 dev_info(&pf->pdev->dev,
7b37f376 6307 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6308 vectors = 0;
6309 }
6310
6311 return vectors;
6312}
6313
6314/**
6315 * i40e_init_msix - Setup the MSIX capability
6316 * @pf: board private structure
6317 *
6318 * Work with the OS to set up the MSIX vectors needed.
6319 *
6320 * Returns 0 on success, negative on failure
6321 **/
6322static int i40e_init_msix(struct i40e_pf *pf)
6323{
6324 i40e_status err = 0;
6325 struct i40e_hw *hw = &pf->hw;
6326 int v_budget, i;
6327 int vec;
6328
6329 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6330 return -ENODEV;
6331
6332 /* The number of vectors we'll request will be comprised of:
6333 * - Add 1 for "other" cause for Admin Queue events, etc.
6334 * - The number of LAN queue pairs
f8ff1464
ASJ		 6335 * - Queues being used for RSS.
6336 * We don't need as many as max_rss_size vectors.
6337 * use rss_size instead in the calculation since that
6338 * is governed by number of cpus in the system.
6339 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6340 * - The number of VMDq pairs
6341 * Once we count this up, try the request.
6342 *
6343 * If we can't get what we want, we'll simplify to nearly nothing
6344 * and try again. If that still fails, we punt.
6345 */
f8ff1464 6346 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6347 pf->num_vmdq_msix = pf->num_vmdq_qps;
6348 v_budget = 1 + pf->num_lan_msix;
6349 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6350 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6351 v_budget++;
6352
6353 /* Scale down if necessary, and the rings will share vectors */
6354 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6355
6356 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6357 GFP_KERNEL);
6358 if (!pf->msix_entries)
6359 return -ENOMEM;
6360
6361 for (i = 0; i < v_budget; i++)
6362 pf->msix_entries[i].entry = i;
6363 vec = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba
ASJ		 6364
6365 if (vec != v_budget) {
6366 /* If we have limited resources, we will start with no vectors
6367 * for the special features and then allocate vectors to some
6368 * of these features based on the policy and at the end disable
6369 * the features that did not get any vectors.
6370 */
6371 pf->num_vmdq_msix = 0;
6372 }
6373
41c445ff
JB		 6374 if (vec < I40E_MIN_MSIX) {
6375 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6376 kfree(pf->msix_entries);
6377 pf->msix_entries = NULL;
6378 return -ENODEV;
6379
6380 } else if (vec == I40E_MIN_MSIX) {
6381 /* Adjust for minimal MSIX use */
41c445ff
JB		 6382 pf->num_vmdq_vsis = 0;
6383 pf->num_vmdq_qps = 0;
41c445ff
JB		 6384 pf->num_lan_qps = 1;
6385 pf->num_lan_msix = 1;
6386
6387 } else if (vec != v_budget) {
a34977ba
ASJ		 6388 /* reserve the misc vector */
6389 vec--;
6390
41c445ff
JB		 6391 /* Scale vector usage down */
6392 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 6393 pf->num_vmdq_vsis = 1;
41c445ff
JB		 6394
6395 /* partition out the remaining vectors */
6396 switch (vec) {
6397 case 2:
41c445ff
JB		 6398 pf->num_lan_msix = 1;
6399 break;
6400 case 3:
41c445ff
JB		 6401 pf->num_lan_msix = 2;
6402 break;
6403 default:
6404 pf->num_lan_msix = min_t(int, (vec / 2),
6405 pf->num_lan_qps);
6406 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6407 I40E_DEFAULT_NUM_VMDQ_VSI);
6408 break;
6409 }
6410 }
6411
a34977ba
ASJ		 6412 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
6413 (pf->num_vmdq_msix == 0)) {
6414 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
6415 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6416 }
41c445ff
JB		 6417 return err;
6418}
6419
493fb300 6420/**
90e04070 6421 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6422 * @vsi: the VSI being configured
6423 * @v_idx: index of the vector in the vsi struct
6424 *
6425 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6426 **/
90e04070 6427static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6428{
6429 struct i40e_q_vector *q_vector;
6430
6431 /* allocate q_vector */
6432 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6433 if (!q_vector)
6434 return -ENOMEM;
6435
6436 q_vector->vsi = vsi;
6437 q_vector->v_idx = v_idx;
6438 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6439 if (vsi->netdev)
6440 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6441 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6442
cd0b6fa6
AD		 6443 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6444 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6445
493fb300
AD		 6446 /* tie q_vector and vsi together */
6447 vsi->q_vectors[v_idx] = q_vector;
6448
6449 return 0;
6450}
6451
41c445ff 6452/**
90e04070 6453 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6454 * @vsi: the VSI being configured
6455 *
6456 * We allocate one q_vector per queue interrupt. If allocation fails we
6457 * return -ENOMEM.
6458 **/
90e04070 6459static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6460{
6461 struct i40e_pf *pf = vsi->back;
6462 int v_idx, num_q_vectors;
493fb300 6463 int err;
41c445ff
JB		 6464
6465 /* if not MSIX, give the one vector only to the LAN VSI */
6466 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6467 num_q_vectors = vsi->num_q_vectors;
6468 else if (vsi == pf->vsi[pf->lan_vsi])
6469 num_q_vectors = 1;
6470 else
6471 return -EINVAL;
6472
41c445ff 6473 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6474 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6475 if (err)
6476 goto err_out;
41c445ff
JB		 6477 }
6478
6479 return 0;
493fb300
AD		 6480
6481err_out:
6482 while (v_idx--)
6483 i40e_free_q_vector(vsi, v_idx);
6484
6485 return err;
41c445ff
JB		 6486}
6487
6488/**
6489 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6490 * @pf: board private structure to initialize
6491 **/
6492static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6493{
6494 int err = 0;
6495
6496 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6497 err = i40e_init_msix(pf);
6498 if (err) {
60ea5f83
JB		 6499 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6500 I40E_FLAG_RSS_ENABLED |
4d9b6043 6501 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 6502 I40E_FLAG_SRIOV_ENABLED |
6503 I40E_FLAG_FD_SB_ENABLED |
6504 I40E_FLAG_FD_ATR_ENABLED |
6505 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6506
6507 /* rework the queue expectations without MSIX */
6508 i40e_determine_queue_usage(pf);
6509 }
6510 }
6511
6512 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6513 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6514 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6515 err = pci_enable_msi(pf->pdev);
6516 if (err) {
958a3e3b 6517 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6518 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6519 }
6520 }
6521
958a3e3b 6522 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6523 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6524
41c445ff
JB		 6525 /* track first vector for misc interrupts */
6526 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6527}
6528
6529/**
6530 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6531 * @pf: board private structure
6532 *
6533 * This sets up the handler for MSIX 0, which is used to manage the
6534 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6535 * when in MSI or Legacy interrupt mode.
6536 **/
6537static int i40e_setup_misc_vector(struct i40e_pf *pf)
6538{
6539 struct i40e_hw *hw = &pf->hw;
6540 int err = 0;
6541
6542 /* Only request the irq if this is the first time through, and
6543 * not when we're rebuilding after a Reset
6544 */
6545 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6546 err = request_irq(pf->msix_entries[0].vector,
6547 i40e_intr, 0, pf->misc_int_name, pf);
6548 if (err) {
6549 dev_info(&pf->pdev->dev,
77fa28be
CS		 6550 "request_irq for %s failed: %d\n",
6551 pf->misc_int_name, err);
41c445ff
JB		 6552 return -EFAULT;
6553 }
6554 }
6555
6556 i40e_enable_misc_int_causes(hw);
6557
6558 /* associate no queues to the misc vector */
6559 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6560 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6561
6562 i40e_flush(hw);
6563
6564 i40e_irq_dynamic_enable_icr0(pf);
6565
6566 return err;
6567}
6568
6569/**
6570 * i40e_config_rss - Prepare for RSS if used
6571 * @pf: board private structure
6572 **/
6573static int i40e_config_rss(struct i40e_pf *pf)
6574{
41c445ff
JB		 6575 /* Set of random keys generated using kernel random number generator */
6576 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6577 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6578 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6579 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6580 struct i40e_hw *hw = &pf->hw;
6581 u32 lut = 0;
6582 int i, j;
6583 u64 hena;
41c445ff
JB		 6584
6585 /* Fill out hash function seed */
6586 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6587 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6588
6589 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6590 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6591 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6592 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6593 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6594 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6595
6596 /* Populate the LUT with max no. of queues in round robin fashion */
6597 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6598
6599 /* The assumption is that lan qp count will be the highest
6600 * qp count for any PF VSI that needs RSS.
6601 * If multiple VSIs need RSS support, all the qp counts
6602 * for those VSIs should be a power of 2 for RSS to work.
6603 * If LAN VSI is the only consumer for RSS then this requirement
6604 * is not necessary.
6605 */
6606 if (j == pf->rss_size)
6607 j = 0;
6608 /* lut = 4-byte sliding window of 4 lut entries */
6609 lut = (lut << 8) | (j &
6610 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6611 /* On i = 3, we have 4 entries in lut; write to the register */
6612 if ((i & 3) == 3)
6613 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6614 }
6615 i40e_flush(hw);
6616
6617 return 0;
6618}
6619
f8ff1464
ASJ		 6620/**
6621 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6622 * @pf: board private structure
6623 * @queue_count: the requested queue count for rss.
6624 *
6625 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6626 * count which may be different from the requested queue count.
6627 **/
6628int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6629{
6630 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6631 return 0;
6632
6633 queue_count = min_t(int, queue_count, pf->rss_size_max);
f8ff1464
ASJ		 6634
6635 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6636 i40e_prep_for_reset(pf);
6637
f8ff1464
ASJ		 6638 pf->rss_size = queue_count;
6639
6640 i40e_reset_and_rebuild(pf, true);
6641 i40e_config_rss(pf);
6642 }
6643 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6644 return pf->rss_size;
6645}
6646
41c445ff
JB		 6647/**
6648 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6649 * @pf: board private structure to initialize
6650 *
6651 * i40e_sw_init initializes the Adapter private data structure.
6652 * Fields are initialized based on PCI device information and
6653 * OS network device settings (MTU size).
6654 **/
6655static int i40e_sw_init(struct i40e_pf *pf)
6656{
6657 int err = 0;
6658 int size;
6659
6660 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6661 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6662 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6663 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6664 if (I40E_DEBUG_USER & debug)
6665 pf->hw.debug_mask = debug;
6666 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6667 I40E_DEFAULT_MSG_ENABLE);
6668 }
6669
6670 /* Set default capability flags */
6671 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6672 I40E_FLAG_MSI_ENABLED |
6673 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6674 I40E_FLAG_RX_1BUF_ENABLED;
6675
ca99eb99
MW		 6676 /* Set default ITR */
6677 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6678 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6679
7134f9ce
JB		 6680 /* Depending on PF configurations, it is possible that the RSS
6681 * maximum might end up larger than the available queues
6682 */
41c445ff 6683 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6684 pf->rss_size_max = min_t(int, pf->rss_size_max,
6685 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6686 if (pf->hw.func_caps.rss) {
6687 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6688 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 6689 } else {
6690 pf->rss_size = 1;
6691 }
6692
2050bc65
CS		 6693 /* MFP mode enabled */
6694 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6695 pf->flags |= I40E_FLAG_MFP_ENABLED;
6696 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6697 }
6698
cbf61325
ASJ		 6699 /* FW/NVM is not yet fixed in this regard */
6700 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6701 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6702 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6703 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
433c47de
ASJ		 6704 /* Setup a counter for fd_atr per pf */
6705 pf->fd_atr_cnt_idx = I40E_FD_ATR_STAT_IDX(pf->hw.pf_id);
cbf61325 6706 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6707 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
433c47de
ASJ		 6708 /* Setup a counter for fd_sb per pf */
6709 pf->fd_sb_cnt_idx = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
cbf61325
ASJ		 6710 } else {
6711 dev_info(&pf->pdev->dev,
0b67584f 6712 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6713 }
cbf61325
ASJ		 6714 pf->fdir_pf_filter_count =
6715 pf->hw.func_caps.fd_filters_guaranteed;
6716 pf->hw.fdir_shared_filter_count =
6717 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6718 }
6719
6720 if (pf->hw.func_caps.vmdq) {
6721 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6722 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6723 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6724 }
6725
41c445ff
JB		 6726#ifdef CONFIG_PCI_IOV
6727 if (pf->hw.func_caps.num_vfs) {
6728 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6729 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6730 pf->num_req_vfs = min_t(int,
6731 pf->hw.func_caps.num_vfs,
6732 I40E_MAX_VF_COUNT);
6733 }
6734#endif /* CONFIG_PCI_IOV */
6735 pf->eeprom_version = 0xDEAD;
6736 pf->lan_veb = I40E_NO_VEB;
6737 pf->lan_vsi = I40E_NO_VSI;
6738
6739 /* set up queue assignment tracking */
6740 size = sizeof(struct i40e_lump_tracking)
6741 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6742 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6743 if (!pf->qp_pile) {
6744 err = -ENOMEM;
6745 goto sw_init_done;
6746 }
6747 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6748 pf->qp_pile->search_hint = 0;
6749
6750 /* set up vector assignment tracking */
6751 size = sizeof(struct i40e_lump_tracking)
6752 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6753 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6754 if (!pf->irq_pile) {
6755 kfree(pf->qp_pile);
6756 err = -ENOMEM;
6757 goto sw_init_done;
6758 }
6759 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6760 pf->irq_pile->search_hint = 0;
6761
6762 mutex_init(&pf->switch_mutex);
6763
6764sw_init_done:
6765 return err;
6766}
6767
7c3c288b
ASJ		 6768/**
6769 * i40e_set_ntuple - set the ntuple feature flag and take action
6770 * @pf: board private structure to initialize
6771 * @features: the feature set that the stack is suggesting
6772 *
6773 * returns a bool to indicate if reset needs to happen
6774 **/
6775bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6776{
6777 bool need_reset = false;
6778
6779 /* Check if Flow Director n-tuple support was enabled or disabled. If
6780 * the state changed, we need to reset.
6781 */
6782 if (features & NETIF_F_NTUPLE) {
6783 /* Enable filters and mark for reset */
6784 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6785 need_reset = true;
6786 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6787 } else {
6788 /* turn off filters, mark for reset and clear SW filter list */
6789 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6790 need_reset = true;
6791 i40e_fdir_filter_exit(pf);
6792 }
6793 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6794 /* if ATR was disabled it can be re-enabled. */
6795 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6796 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6797 }
6798 return need_reset;
6799}
6800
41c445ff
JB		 6801/**
6802 * i40e_set_features - set the netdev feature flags
6803 * @netdev: ptr to the netdev being adjusted
6804 * @features: the feature set that the stack is suggesting
6805 **/
6806static int i40e_set_features(struct net_device *netdev,
6807 netdev_features_t features)
6808{
6809 struct i40e_netdev_priv *np = netdev_priv(netdev);
6810 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6811 struct i40e_pf *pf = vsi->back;
6812 bool need_reset;
41c445ff
JB		 6813
6814 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6815 i40e_vlan_stripping_enable(vsi);
6816 else
6817 i40e_vlan_stripping_disable(vsi);
6818
7c3c288b
ASJ		 6819 need_reset = i40e_set_ntuple(pf, features);
6820
6821 if (need_reset)
6822 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6823
41c445ff
JB		 6824 return 0;
6825}
6826
a1c9a9d9
JK		 6827#ifdef CONFIG_I40E_VXLAN
6828/**
6829 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6830 * @pf: board private structure
6831 * @port: The UDP port to look up
6832 *
6833 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6834 **/
6835static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6836{
6837 u8 i;
6838
6839 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6840 if (pf->vxlan_ports[i] == port)
6841 return i;
6842 }
6843
6844 return i;
6845}
6846
6847/**
6848 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6849 * @netdev: This physical port's netdev
6850 * @sa_family: Socket Family that VXLAN is notifying us about
6851 * @port: New UDP port number that VXLAN started listening to
6852 **/
6853static void i40e_add_vxlan_port(struct net_device *netdev,
6854 sa_family_t sa_family, __be16 port)
6855{
6856 struct i40e_netdev_priv *np = netdev_priv(netdev);
6857 struct i40e_vsi *vsi = np->vsi;
6858 struct i40e_pf *pf = vsi->back;
6859 u8 next_idx;
6860 u8 idx;
6861
6862 if (sa_family == AF_INET6)
6863 return;
6864
6865 idx = i40e_get_vxlan_port_idx(pf, port);
6866
6867 /* Check if port already exists */
6868 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6869 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6870 return;
6871 }
6872
6873 /* Now check if there is space to add the new port */
6874 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6875
6876 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6877 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6878 ntohs(port));
6879 return;
6880 }
6881
6882 /* New port: add it and mark its index in the bitmap */
6883 pf->vxlan_ports[next_idx] = port;
6884 pf->pending_vxlan_bitmap |= (1 << next_idx);
6885
6886 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6887}
6888
6889/**
6890 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6891 * @netdev: This physical port's netdev
6892 * @sa_family: Socket Family that VXLAN is notifying us about
6893 * @port: UDP port number that VXLAN stopped listening to
6894 **/
6895static void i40e_del_vxlan_port(struct net_device *netdev,
6896 sa_family_t sa_family, __be16 port)
6897{
6898 struct i40e_netdev_priv *np = netdev_priv(netdev);
6899 struct i40e_vsi *vsi = np->vsi;
6900 struct i40e_pf *pf = vsi->back;
6901 u8 idx;
6902
6903 if (sa_family == AF_INET6)
6904 return;
6905
6906 idx = i40e_get_vxlan_port_idx(pf, port);
6907
6908 /* Check if port already exists */
6909 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6910 /* if port exists, set it to 0 (mark for deletion)
6911 * and make it pending
6912 */
6913 pf->vxlan_ports[idx] = 0;
6914
6915 pf->pending_vxlan_bitmap |= (1 << idx);
6916
6917 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6918 } else {
6919 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6920 ntohs(port));
6921 }
6922}
6923
6924#endif
4ba0dea5
GR		 6925#ifdef HAVE_FDB_OPS
6926#ifdef USE_CONST_DEV_UC_CHAR
6927static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6928 struct net_device *dev,
6929 const unsigned char *addr,
6930 u16 flags)
6931#else
6932static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6933 struct net_device *dev,
6934 unsigned char *addr,
6935 u16 flags)
6936#endif
6937{
6938 struct i40e_netdev_priv *np = netdev_priv(dev);
6939 struct i40e_pf *pf = np->vsi->back;
6940 int err = 0;
6941
6942 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6943 return -EOPNOTSUPP;
6944
6945 /* Hardware does not support aging addresses so if a
6946 * ndm_state is given only allow permanent addresses
6947 */
6948 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6949 netdev_info(dev, "FDB only supports static addresses\n");
6950 return -EINVAL;
6951 }
6952
6953 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6954 err = dev_uc_add_excl(dev, addr);
6955 else if (is_multicast_ether_addr(addr))
6956 err = dev_mc_add_excl(dev, addr);
6957 else
6958 err = -EINVAL;
6959
6960 /* Only return duplicate errors if NLM_F_EXCL is set */
6961 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6962 err = 0;
6963
6964 return err;
6965}
6966
6967#ifndef USE_DEFAULT_FDB_DEL_DUMP
6968#ifdef USE_CONST_DEV_UC_CHAR
6969static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6970 struct net_device *dev,
6971 const unsigned char *addr)
6972#else
6973static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6974 struct net_device *dev,
6975 unsigned char *addr)
6976#endif
6977{
6978 struct i40e_netdev_priv *np = netdev_priv(dev);
6979 struct i40e_pf *pf = np->vsi->back;
6980 int err = -EOPNOTSUPP;
6981
6982 if (ndm->ndm_state & NUD_PERMANENT) {
6983 netdev_info(dev, "FDB only supports static addresses\n");
6984 return -EINVAL;
6985 }
6986
6987 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6988 if (is_unicast_ether_addr(addr))
6989 err = dev_uc_del(dev, addr);
6990 else if (is_multicast_ether_addr(addr))
6991 err = dev_mc_del(dev, addr);
6992 else
6993 err = -EINVAL;
6994 }
6995
6996 return err;
6997}
6998
6999static int i40e_ndo_fdb_dump(struct sk_buff *skb,
7000 struct netlink_callback *cb,
7001 struct net_device *dev,
7002 int idx)
7003{
7004 struct i40e_netdev_priv *np = netdev_priv(dev);
7005 struct i40e_pf *pf = np->vsi->back;
7006
7007 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
7008 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7009
7010 return idx;
7011}
7012
7013#endif /* USE_DEFAULT_FDB_DEL_DUMP */
7014#endif /* HAVE_FDB_OPS */
41c445ff
JB		 7015static const struct net_device_ops i40e_netdev_ops = {
7016 .ndo_open = i40e_open,
7017 .ndo_stop = i40e_close,
7018 .ndo_start_xmit = i40e_lan_xmit_frame,
7019 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
7020 .ndo_set_rx_mode = i40e_set_rx_mode,
7021 .ndo_validate_addr = eth_validate_addr,
7022 .ndo_set_mac_address = i40e_set_mac,
7023 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 7024 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 7025 .ndo_tx_timeout = i40e_tx_timeout,
7026 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
7027 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
7028#ifdef CONFIG_NET_POLL_CONTROLLER
7029 .ndo_poll_controller = i40e_netpoll,
7030#endif
7031 .ndo_setup_tc = i40e_setup_tc,
7032 .ndo_set_features = i40e_set_features,
7033 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
7034 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 7035 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 7036 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 7037 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
c674d125 7038 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofck,
a1c9a9d9
JK		 7039#ifdef CONFIG_I40E_VXLAN
7040 .ndo_add_vxlan_port = i40e_add_vxlan_port,
7041 .ndo_del_vxlan_port = i40e_del_vxlan_port,
7042#endif
4ba0dea5
GR		 7043#ifdef HAVE_FDB_OPS
7044 .ndo_fdb_add = i40e_ndo_fdb_add,
7045#ifndef USE_DEFAULT_FDB_DEL_DUMP
7046 .ndo_fdb_del = i40e_ndo_fdb_del,
7047 .ndo_fdb_dump = i40e_ndo_fdb_dump,
7048#endif
7049#endif
41c445ff
JB		 7050};
7051
7052/**
7053 * i40e_config_netdev - Setup the netdev flags
7054 * @vsi: the VSI being configured
7055 *
7056 * Returns 0 on success, negative value on failure
7057 **/
7058static int i40e_config_netdev(struct i40e_vsi *vsi)
7059{
1a10370a 7060 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 7061 struct i40e_pf *pf = vsi->back;
7062 struct i40e_hw *hw = &pf->hw;
7063 struct i40e_netdev_priv *np;
7064 struct net_device *netdev;
7065 u8 mac_addr[ETH_ALEN];
7066 int etherdev_size;
7067
7068 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 7069 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 7070 if (!netdev)
7071 return -ENOMEM;
7072
7073 vsi->netdev = netdev;
7074 np = netdev_priv(netdev);
7075 np->vsi = vsi;
7076
d70e941b 7077 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 7078 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 7079 NETIF_F_TSO;
41c445ff
JB		 7080
7081 netdev->features = NETIF_F_SG |
7082 NETIF_F_IP_CSUM |
7083 NETIF_F_SCTP_CSUM |
7084 NETIF_F_HIGHDMA |
7085 NETIF_F_GSO_UDP_TUNNEL |
7086 NETIF_F_HW_VLAN_CTAG_TX |
7087 NETIF_F_HW_VLAN_CTAG_RX |
7088 NETIF_F_HW_VLAN_CTAG_FILTER |
7089 NETIF_F_IPV6_CSUM |
7090 NETIF_F_TSO |
059dab69 7091 NETIF_F_TSO_ECN |
41c445ff
JB		 7092 NETIF_F_TSO6 |
7093 NETIF_F_RXCSUM |
7094 NETIF_F_RXHASH |
7095 0;
7096
2e86a0b6
ASJ		 7097 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
7098 netdev->features |= NETIF_F_NTUPLE;
7099
41c445ff
JB		 7100 /* copy netdev features into list of user selectable features */
7101 netdev->hw_features |= netdev->features;
7102
7103 if (vsi->type == I40E_VSI_MAIN) {
7104 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 7105 ether_addr_copy(mac_addr, hw->mac.perm_addr);
8c27d42e
GR		 7106 /* The following two steps are necessary to prevent reception
7107 * of tagged packets - by default the NVM loads a MAC-VLAN
7108 * filter that will accept any tagged packet. This is to
7109 * prevent that during normal operations until a specific
7110 * VLAN tag filter has been set.
7111 */
7112 i40e_rm_default_mac_filter(vsi, mac_addr);
7113 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true);
41c445ff
JB		 7114 } else {
7115 /* relate the VSI_VMDQ name to the VSI_MAIN name */
7116 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
7117 pf->vsi[pf->lan_vsi]->netdev->name);
7118 random_ether_addr(mac_addr);
7119 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
7120 }
1a10370a 7121 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff 7122
9a173901
GR		 7123 ether_addr_copy(netdev->dev_addr, mac_addr);
7124 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 7125 /* vlan gets same features (except vlan offload)
7126 * after any tweaks for specific VSI types
7127 */
7128 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
7129 NETIF_F_HW_VLAN_CTAG_RX |
7130 NETIF_F_HW_VLAN_CTAG_FILTER);
7131 netdev->priv_flags |= IFF_UNICAST_FLT;
7132 netdev->priv_flags |= IFF_SUPP_NOFCS;
7133 /* Setup netdev TC information */
7134 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
7135
7136 netdev->netdev_ops = &i40e_netdev_ops;
7137 netdev->watchdog_timeo = 5 * HZ;
7138 i40e_set_ethtool_ops(netdev);
7139
7140 return 0;
7141}
7142
7143/**
7144 * i40e_vsi_delete - Delete a VSI from the switch
7145 * @vsi: the VSI being removed
7146 *
7147 * Returns 0 on success, negative value on failure
7148 **/
7149static void i40e_vsi_delete(struct i40e_vsi *vsi)
7150{
7151 /* remove default VSI is not allowed */
7152 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
7153 return;
7154
41c445ff 7155 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 7156}
7157
7158/**
7159 * i40e_add_vsi - Add a VSI to the switch
7160 * @vsi: the VSI being configured
7161 *
7162 * This initializes a VSI context depending on the VSI type to be added and
7163 * passes it down to the add_vsi aq command.
7164 **/
7165static int i40e_add_vsi(struct i40e_vsi *vsi)
7166{
7167 int ret = -ENODEV;
7168 struct i40e_mac_filter *f, *ftmp;
7169 struct i40e_pf *pf = vsi->back;
7170 struct i40e_hw *hw = &pf->hw;
7171 struct i40e_vsi_context ctxt;
7172 u8 enabled_tc = 0x1; /* TC0 enabled */
7173 int f_count = 0;
7174
7175 memset(&ctxt, 0, sizeof(ctxt));
7176 switch (vsi->type) {
7177 case I40E_VSI_MAIN:
7178 /* The PF's main VSI is already setup as part of the
7179 * device initialization, so we'll not bother with
7180 * the add_vsi call, but we will retrieve the current
7181 * VSI context.
7182 */
7183 ctxt.seid = pf->main_vsi_seid;
7184 ctxt.pf_num = pf->hw.pf_id;
7185 ctxt.vf_num = 0;
7186 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7187 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7188 if (ret) {
7189 dev_info(&pf->pdev->dev,
7190 "couldn't get pf vsi config, err %d, aq_err %d\n",
7191 ret, pf->hw.aq.asq_last_status);
7192 return -ENOENT;
7193 }
7194 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7195 vsi->info.valid_sections = 0;
7196
7197 vsi->seid = ctxt.seid;
7198 vsi->id = ctxt.vsi_number;
7199
7200 enabled_tc = i40e_pf_get_tc_map(pf);
7201
7202 /* MFP mode setup queue map and update VSI */
7203 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7204 memset(&ctxt, 0, sizeof(ctxt));
7205 ctxt.seid = pf->main_vsi_seid;
7206 ctxt.pf_num = pf->hw.pf_id;
7207 ctxt.vf_num = 0;
7208 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7209 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7210 if (ret) {
7211 dev_info(&pf->pdev->dev,
7212 "update vsi failed, aq_err=%d\n",
7213 pf->hw.aq.asq_last_status);
7214 ret = -ENOENT;
7215 goto err;
7216 }
7217 /* update the local VSI info queue map */
7218 i40e_vsi_update_queue_map(vsi, &ctxt);
7219 vsi->info.valid_sections = 0;
7220 } else {
7221 /* Default/Main VSI is only enabled for TC0
7222 * reconfigure it to enable all TCs that are
7223 * available on the port in SFP mode.
7224 */
7225 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7226 if (ret) {
7227 dev_info(&pf->pdev->dev,
7228 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7229 enabled_tc, ret,
7230 pf->hw.aq.asq_last_status);
7231 ret = -ENOENT;
7232 }
7233 }
7234 break;
7235
7236 case I40E_VSI_FDIR:
cbf61325
ASJ		 7237 ctxt.pf_num = hw->pf_id;
7238 ctxt.vf_num = 0;
7239 ctxt.uplink_seid = vsi->uplink_seid;
7240 ctxt.connection_type = 0x1; /* regular data port */
7241 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7242 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7243 break;
7244
7245 case I40E_VSI_VMDQ2:
7246 ctxt.pf_num = hw->pf_id;
7247 ctxt.vf_num = 0;
7248 ctxt.uplink_seid = vsi->uplink_seid;
7249 ctxt.connection_type = 0x1; /* regular data port */
7250 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7251
7252 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7253
7254 /* This VSI is connected to VEB so the switch_id
7255 * should be set to zero by default.
7256 */
7257 ctxt.info.switch_id = 0;
7258 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
7259 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7260
7261 /* Setup the VSI tx/rx queue map for TC0 only for now */
7262 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7263 break;
7264
7265 case I40E_VSI_SRIOV:
7266 ctxt.pf_num = hw->pf_id;
7267 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7268 ctxt.uplink_seid = vsi->uplink_seid;
7269 ctxt.connection_type = 0x1; /* regular data port */
7270 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7271
7272 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7273
7274 /* This VSI is connected to VEB so the switch_id
7275 * should be set to zero by default.
7276 */
7277 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7278
7279 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7280 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 7281 if (pf->vf[vsi->vf_id].spoofchk) {
7282 ctxt.info.valid_sections |=
7283 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
7284 ctxt.info.sec_flags |=
7285 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
7286 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
7287 }
41c445ff
JB		 7288 /* Setup the VSI tx/rx queue map for TC0 only for now */
7289 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7290 break;
7291
7292 default:
7293 return -ENODEV;
7294 }
7295
7296 if (vsi->type != I40E_VSI_MAIN) {
7297 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7298 if (ret) {
7299 dev_info(&vsi->back->pdev->dev,
7300 "add vsi failed, aq_err=%d\n",
7301 vsi->back->hw.aq.asq_last_status);
7302 ret = -ENOENT;
7303 goto err;
7304 }
7305 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7306 vsi->info.valid_sections = 0;
7307 vsi->seid = ctxt.seid;
7308 vsi->id = ctxt.vsi_number;
7309 }
7310
7311 /* If macvlan filters already exist, force them to get loaded */
7312 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7313 f->changed = true;
7314 f_count++;
7315 }
7316 if (f_count) {
7317 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7318 pf->flags |= I40E_FLAG_FILTER_SYNC;
7319 }
7320
7321 /* Update VSI BW information */
7322 ret = i40e_vsi_get_bw_info(vsi);
7323 if (ret) {
7324 dev_info(&pf->pdev->dev,
7325 "couldn't get vsi bw info, err %d, aq_err %d\n",
7326 ret, pf->hw.aq.asq_last_status);
7327 /* VSI is already added so not tearing that up */
7328 ret = 0;
7329 }
7330
7331err:
7332 return ret;
7333}
7334
7335/**
7336 * i40e_vsi_release - Delete a VSI and free its resources
7337 * @vsi: the VSI being removed
7338 *
7339 * Returns 0 on success or < 0 on error
7340 **/
7341int i40e_vsi_release(struct i40e_vsi *vsi)
7342{
7343 struct i40e_mac_filter *f, *ftmp;
7344 struct i40e_veb *veb = NULL;
7345 struct i40e_pf *pf;
7346 u16 uplink_seid;
7347 int i, n;
7348
7349 pf = vsi->back;
7350
7351 /* release of a VEB-owner or last VSI is not allowed */
7352 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7353 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7354 vsi->seid, vsi->uplink_seid);
7355 return -ENODEV;
7356 }
7357 if (vsi == pf->vsi[pf->lan_vsi] &&
7358 !test_bit(__I40E_DOWN, &pf->state)) {
7359 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7360 return -ENODEV;
7361 }
7362
7363 uplink_seid = vsi->uplink_seid;
7364 if (vsi->type != I40E_VSI_SRIOV) {
7365 if (vsi->netdev_registered) {
7366 vsi->netdev_registered = false;
7367 if (vsi->netdev) {
7368 /* results in a call to i40e_close() */
7369 unregister_netdev(vsi->netdev);
41c445ff
JB		 7370 }
7371 } else {
90ef8d47 7372 i40e_vsi_close(vsi);
41c445ff
JB		 7373 }
7374 i40e_vsi_disable_irq(vsi);
7375 }
7376
7377 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7378 i40e_del_filter(vsi, f->macaddr, f->vlan,
7379 f->is_vf, f->is_netdev);
7380 i40e_sync_vsi_filters(vsi);
7381
7382 i40e_vsi_delete(vsi);
7383 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7384 if (vsi->netdev) {
7385 free_netdev(vsi->netdev);
7386 vsi->netdev = NULL;
7387 }
41c445ff
JB		 7388 i40e_vsi_clear_rings(vsi);
7389 i40e_vsi_clear(vsi);
7390
7391 /* If this was the last thing on the VEB, except for the
7392 * controlling VSI, remove the VEB, which puts the controlling
7393 * VSI onto the next level down in the switch.
7394 *
7395 * Well, okay, there's one more exception here: don't remove
7396 * the orphan VEBs yet. We'll wait for an explicit remove request
7397 * from up the network stack.
7398 */
505682cd 7399 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7400 if (pf->vsi[i] &&
7401 pf->vsi[i]->uplink_seid == uplink_seid &&
7402 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7403 n++; /* count the VSIs */
7404 }
7405 }
7406 for (i = 0; i < I40E_MAX_VEB; i++) {
7407 if (!pf->veb[i])
7408 continue;
7409 if (pf->veb[i]->uplink_seid == uplink_seid)
7410 n++; /* count the VEBs */
7411 if (pf->veb[i]->seid == uplink_seid)
7412 veb = pf->veb[i];
7413 }
7414 if (n == 0 && veb && veb->uplink_seid != 0)
7415 i40e_veb_release(veb);
7416
7417 return 0;
7418}
7419
7420/**
7421 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7422 * @vsi: ptr to the VSI
7423 *
7424 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7425 * corresponding SW VSI structure and initializes num_queue_pairs for the
7426 * newly allocated VSI.
7427 *
7428 * Returns 0 on success or negative on failure
7429 **/
7430static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7431{
7432 int ret = -ENOENT;
7433 struct i40e_pf *pf = vsi->back;
7434
493fb300 7435 if (vsi->q_vectors[0]) {
41c445ff
JB		 7436 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7437 vsi->seid);
7438 return -EEXIST;
7439 }
7440
7441 if (vsi->base_vector) {
f29eaa3d 7442 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7443 vsi->seid, vsi->base_vector);
7444 return -EEXIST;
7445 }
7446
90e04070 7447 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7448 if (ret) {
7449 dev_info(&pf->pdev->dev,
7450 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7451 vsi->num_q_vectors, vsi->seid, ret);
7452 vsi->num_q_vectors = 0;
7453 goto vector_setup_out;
7454 }
7455
958a3e3b
SN		 7456 if (vsi->num_q_vectors)
7457 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7458 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7459 if (vsi->base_vector < 0) {
7460 dev_info(&pf->pdev->dev,
f29eaa3d 7461 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7462 vsi->seid, vsi->base_vector);
7463 i40e_vsi_free_q_vectors(vsi);
7464 ret = -ENOENT;
7465 goto vector_setup_out;
7466 }
7467
7468vector_setup_out:
7469 return ret;
7470}
7471
bc7d338f
ASJ		 7472/**
7473 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7474 * @vsi: pointer to the vsi.
7475 *
7476 * This re-allocates a vsi's queue resources.
7477 *
7478 * Returns pointer to the successfully allocated and configured VSI sw struct
7479 * on success, otherwise returns NULL on failure.
7480 **/
7481static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7482{
7483 struct i40e_pf *pf = vsi->back;
7484 u8 enabled_tc;
7485 int ret;
7486
7487 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7488 i40e_vsi_clear_rings(vsi);
7489
7490 i40e_vsi_free_arrays(vsi, false);
7491 i40e_set_num_rings_in_vsi(vsi);
7492 ret = i40e_vsi_alloc_arrays(vsi, false);
7493 if (ret)
7494 goto err_vsi;
7495
7496 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7497 if (ret < 0) {
7498 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7499 vsi->seid, ret);
7500 goto err_vsi;
7501 }
7502 vsi->base_queue = ret;
7503
7504 /* Update the FW view of the VSI. Force a reset of TC and queue
7505 * layout configurations.
7506 */
7507 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7508 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7509 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7510 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7511
7512 /* assign it some queues */
7513 ret = i40e_alloc_rings(vsi);
7514 if (ret)
7515 goto err_rings;
7516
7517 /* map all of the rings to the q_vectors */
7518 i40e_vsi_map_rings_to_vectors(vsi);
7519 return vsi;
7520
7521err_rings:
7522 i40e_vsi_free_q_vectors(vsi);
7523 if (vsi->netdev_registered) {
7524 vsi->netdev_registered = false;
7525 unregister_netdev(vsi->netdev);
7526 free_netdev(vsi->netdev);
7527 vsi->netdev = NULL;
7528 }
7529 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7530err_vsi:
7531 i40e_vsi_clear(vsi);
7532 return NULL;
7533}
7534
41c445ff
JB		 7535/**
7536 * i40e_vsi_setup - Set up a VSI by a given type
7537 * @pf: board private structure
7538 * @type: VSI type
7539 * @uplink_seid: the switch element to link to
7540 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7541 *
7542 * This allocates the sw VSI structure and its queue resources, then add a VSI
7543 * to the identified VEB.
7544 *
7545 * Returns pointer to the successfully allocated and configure VSI sw struct on
7546 * success, otherwise returns NULL on failure.
7547 **/
7548struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7549 u16 uplink_seid, u32 param1)
7550{
7551 struct i40e_vsi *vsi = NULL;
7552 struct i40e_veb *veb = NULL;
7553 int ret, i;
7554 int v_idx;
7555
7556 /* The requested uplink_seid must be either
7557 * - the PF's port seid
7558 * no VEB is needed because this is the PF
7559 * or this is a Flow Director special case VSI
7560 * - seid of an existing VEB
7561 * - seid of a VSI that owns an existing VEB
7562 * - seid of a VSI that doesn't own a VEB
7563 * a new VEB is created and the VSI becomes the owner
7564 * - seid of the PF VSI, which is what creates the first VEB
7565 * this is a special case of the previous
7566 *
7567 * Find which uplink_seid we were given and create a new VEB if needed
7568 */
7569 for (i = 0; i < I40E_MAX_VEB; i++) {
7570 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7571 veb = pf->veb[i];
7572 break;
7573 }
7574 }
7575
7576 if (!veb && uplink_seid != pf->mac_seid) {
7577
505682cd 7578 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7579 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7580 vsi = pf->vsi[i];
7581 break;
7582 }
7583 }
7584 if (!vsi) {
7585 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7586 uplink_seid);
7587 return NULL;
7588 }
7589
7590 if (vsi->uplink_seid == pf->mac_seid)
7591 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7592 vsi->tc_config.enabled_tc);
7593 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7594 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7595 vsi->tc_config.enabled_tc);
7596
7597 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7598 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7599 veb = pf->veb[i];
7600 }
7601 if (!veb) {
7602 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7603 return NULL;
7604 }
7605
7606 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7607 uplink_seid = veb->seid;
7608 }
7609
7610 /* get vsi sw struct */
7611 v_idx = i40e_vsi_mem_alloc(pf, type);
7612 if (v_idx < 0)
7613 goto err_alloc;
7614 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7615 if (!vsi)
7616 goto err_alloc;
41c445ff
JB		 7617 vsi->type = type;
7618 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7619
7620 if (type == I40E_VSI_MAIN)
7621 pf->lan_vsi = v_idx;
7622 else if (type == I40E_VSI_SRIOV)
7623 vsi->vf_id = param1;
7624 /* assign it some queues */
cbf61325
ASJ		 7625 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7626 vsi->idx);
41c445ff
JB		 7627 if (ret < 0) {
7628 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7629 vsi->seid, ret);
7630 goto err_vsi;
7631 }
7632 vsi->base_queue = ret;
7633
7634 /* get a VSI from the hardware */
7635 vsi->uplink_seid = uplink_seid;
7636 ret = i40e_add_vsi(vsi);
7637 if (ret)
7638 goto err_vsi;
7639
7640 switch (vsi->type) {
7641 /* setup the netdev if needed */
7642 case I40E_VSI_MAIN:
7643 case I40E_VSI_VMDQ2:
7644 ret = i40e_config_netdev(vsi);
7645 if (ret)
7646 goto err_netdev;
7647 ret = register_netdev(vsi->netdev);
7648 if (ret)
7649 goto err_netdev;
7650 vsi->netdev_registered = true;
7651 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7652#ifdef CONFIG_I40E_DCB
7653 /* Setup DCB netlink interface */
7654 i40e_dcbnl_setup(vsi);
7655#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7656 /* fall through */
7657
7658 case I40E_VSI_FDIR:
7659 /* set up vectors and rings if needed */
7660 ret = i40e_vsi_setup_vectors(vsi);
7661 if (ret)
7662 goto err_msix;
7663
7664 ret = i40e_alloc_rings(vsi);
7665 if (ret)
7666 goto err_rings;
7667
7668 /* map all of the rings to the q_vectors */
7669 i40e_vsi_map_rings_to_vectors(vsi);
7670
7671 i40e_vsi_reset_stats(vsi);
7672 break;
7673
7674 default:
7675 /* no netdev or rings for the other VSI types */
7676 break;
7677 }
7678
7679 return vsi;
7680
7681err_rings:
7682 i40e_vsi_free_q_vectors(vsi);
7683err_msix:
7684 if (vsi->netdev_registered) {
7685 vsi->netdev_registered = false;
7686 unregister_netdev(vsi->netdev);
7687 free_netdev(vsi->netdev);
7688 vsi->netdev = NULL;
7689 }
7690err_netdev:
7691 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7692err_vsi:
7693 i40e_vsi_clear(vsi);
7694err_alloc:
7695 return NULL;
7696}
7697
7698/**
7699 * i40e_veb_get_bw_info - Query VEB BW information
7700 * @veb: the veb to query
7701 *
7702 * Query the Tx scheduler BW configuration data for given VEB
7703 **/
7704static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7705{
7706 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7707 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7708 struct i40e_pf *pf = veb->pf;
7709 struct i40e_hw *hw = &pf->hw;
7710 u32 tc_bw_max;
7711 int ret = 0;
7712 int i;
7713
7714 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7715 &bw_data, NULL);
7716 if (ret) {
7717 dev_info(&pf->pdev->dev,
7718 "query veb bw config failed, aq_err=%d\n",
7719 hw->aq.asq_last_status);
7720 goto out;
7721 }
7722
7723 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7724 &ets_data, NULL);
7725 if (ret) {
7726 dev_info(&pf->pdev->dev,
7727 "query veb bw ets config failed, aq_err=%d\n",
7728 hw->aq.asq_last_status);
7729 goto out;
7730 }
7731
7732 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7733 veb->bw_max_quanta = ets_data.tc_bw_max;
7734 veb->is_abs_credits = bw_data.absolute_credits_enable;
7735 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7736 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7737 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7738 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7739 veb->bw_tc_limit_credits[i] =
7740 le16_to_cpu(bw_data.tc_bw_limits[i]);
7741 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7742 }
7743
7744out:
7745 return ret;
7746}
7747
7748/**
7749 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7750 * @pf: board private structure
7751 *
7752 * On error: returns error code (negative)
7753 * On success: returns vsi index in PF (positive)
7754 **/
7755static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7756{
7757 int ret = -ENOENT;
7758 struct i40e_veb *veb;
7759 int i;
7760
7761 /* Need to protect the allocation of switch elements at the PF level */
7762 mutex_lock(&pf->switch_mutex);
7763
7764 /* VEB list may be fragmented if VEB creation/destruction has
7765 * been happening. We can afford to do a quick scan to look
7766 * for any free slots in the list.
7767 *
7768 * find next empty veb slot, looping back around if necessary
7769 */
7770 i = 0;
7771 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7772 i++;
7773 if (i >= I40E_MAX_VEB) {
7774 ret = -ENOMEM;
7775 goto err_alloc_veb; /* out of VEB slots! */
7776 }
7777
7778 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7779 if (!veb) {
7780 ret = -ENOMEM;
7781 goto err_alloc_veb;
7782 }
7783 veb->pf = pf;
7784 veb->idx = i;
7785 veb->enabled_tc = 1;
7786
7787 pf->veb[i] = veb;
7788 ret = i;
7789err_alloc_veb:
7790 mutex_unlock(&pf->switch_mutex);
7791 return ret;
7792}
7793
7794/**
7795 * i40e_switch_branch_release - Delete a branch of the switch tree
7796 * @branch: where to start deleting
7797 *
7798 * This uses recursion to find the tips of the branch to be
7799 * removed, deleting until we get back to and can delete this VEB.
7800 **/
7801static void i40e_switch_branch_release(struct i40e_veb *branch)
7802{
7803 struct i40e_pf *pf = branch->pf;
7804 u16 branch_seid = branch->seid;
7805 u16 veb_idx = branch->idx;
7806 int i;
7807
7808 /* release any VEBs on this VEB - RECURSION */
7809 for (i = 0; i < I40E_MAX_VEB; i++) {
7810 if (!pf->veb[i])
7811 continue;
7812 if (pf->veb[i]->uplink_seid == branch->seid)
7813 i40e_switch_branch_release(pf->veb[i]);
7814 }
7815
7816 /* Release the VSIs on this VEB, but not the owner VSI.
7817 *
7818 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7819 * the VEB itself, so don't use (*branch) after this loop.
7820 */
505682cd 7821 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7822 if (!pf->vsi[i])
7823 continue;
7824 if (pf->vsi[i]->uplink_seid == branch_seid &&
7825 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7826 i40e_vsi_release(pf->vsi[i]);
7827 }
7828 }
7829
7830 /* There's one corner case where the VEB might not have been
7831 * removed, so double check it here and remove it if needed.
7832 * This case happens if the veb was created from the debugfs
7833 * commands and no VSIs were added to it.
7834 */
7835 if (pf->veb[veb_idx])
7836 i40e_veb_release(pf->veb[veb_idx]);
7837}
7838
7839/**
7840 * i40e_veb_clear - remove veb struct
7841 * @veb: the veb to remove
7842 **/
7843static void i40e_veb_clear(struct i40e_veb *veb)
7844{
7845 if (!veb)
7846 return;
7847
7848 if (veb->pf) {
7849 struct i40e_pf *pf = veb->pf;
7850
7851 mutex_lock(&pf->switch_mutex);
7852 if (pf->veb[veb->idx] == veb)
7853 pf->veb[veb->idx] = NULL;
7854 mutex_unlock(&pf->switch_mutex);
7855 }
7856
7857 kfree(veb);
7858}
7859
7860/**
7861 * i40e_veb_release - Delete a VEB and free its resources
7862 * @veb: the VEB being removed
7863 **/
7864void i40e_veb_release(struct i40e_veb *veb)
7865{
7866 struct i40e_vsi *vsi = NULL;
7867 struct i40e_pf *pf;
7868 int i, n = 0;
7869
7870 pf = veb->pf;
7871
7872 /* find the remaining VSI and check for extras */
505682cd 7873 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7874 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7875 n++;
7876 vsi = pf->vsi[i];
7877 }
7878 }
7879 if (n != 1) {
7880 dev_info(&pf->pdev->dev,
7881 "can't remove VEB %d with %d VSIs left\n",
7882 veb->seid, n);
7883 return;
7884 }
7885
7886 /* move the remaining VSI to uplink veb */
7887 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7888 if (veb->uplink_seid) {
7889 vsi->uplink_seid = veb->uplink_seid;
7890 if (veb->uplink_seid == pf->mac_seid)
7891 vsi->veb_idx = I40E_NO_VEB;
7892 else
7893 vsi->veb_idx = veb->veb_idx;
7894 } else {
7895 /* floating VEB */
7896 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7897 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7898 }
7899
7900 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7901 i40e_veb_clear(veb);
41c445ff
JB		 7902}
7903
7904/**
7905 * i40e_add_veb - create the VEB in the switch
7906 * @veb: the VEB to be instantiated
7907 * @vsi: the controlling VSI
7908 **/
7909static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7910{
56747264 7911 bool is_default = false;
e1c51b95 7912 bool is_cloud = false;
41c445ff
JB		 7913 int ret;
7914
7915 /* get a VEB from the hardware */
7916 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7917 veb->enabled_tc, is_default,
7918 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7919 if (ret) {
7920 dev_info(&veb->pf->pdev->dev,
7921 "couldn't add VEB, err %d, aq_err %d\n",
7922 ret, veb->pf->hw.aq.asq_last_status);
7923 return -EPERM;
7924 }
7925
7926 /* get statistics counter */
7927 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7928 &veb->stats_idx, NULL, NULL, NULL);
7929 if (ret) {
7930 dev_info(&veb->pf->pdev->dev,
7931 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7932 ret, veb->pf->hw.aq.asq_last_status);
7933 return -EPERM;
7934 }
7935 ret = i40e_veb_get_bw_info(veb);
7936 if (ret) {
7937 dev_info(&veb->pf->pdev->dev,
7938 "couldn't get VEB bw info, err %d, aq_err %d\n",
7939 ret, veb->pf->hw.aq.asq_last_status);
7940 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7941 return -ENOENT;
7942 }
7943
7944 vsi->uplink_seid = veb->seid;
7945 vsi->veb_idx = veb->idx;
7946 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7947
7948 return 0;
7949}
7950
7951/**
7952 * i40e_veb_setup - Set up a VEB
7953 * @pf: board private structure
7954 * @flags: VEB setup flags
7955 * @uplink_seid: the switch element to link to
7956 * @vsi_seid: the initial VSI seid
7957 * @enabled_tc: Enabled TC bit-map
7958 *
7959 * This allocates the sw VEB structure and links it into the switch
7960 * It is possible and legal for this to be a duplicate of an already
7961 * existing VEB. It is also possible for both uplink and vsi seids
7962 * to be zero, in order to create a floating VEB.
7963 *
7964 * Returns pointer to the successfully allocated VEB sw struct on
7965 * success, otherwise returns NULL on failure.
7966 **/
7967struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7968 u16 uplink_seid, u16 vsi_seid,
7969 u8 enabled_tc)
7970{
7971 struct i40e_veb *veb, *uplink_veb = NULL;
7972 int vsi_idx, veb_idx;
7973 int ret;
7974
7975 /* if one seid is 0, the other must be 0 to create a floating relay */
7976 if ((uplink_seid == 0 || vsi_seid == 0) &&
7977 (uplink_seid + vsi_seid != 0)) {
7978 dev_info(&pf->pdev->dev,
7979 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7980 uplink_seid, vsi_seid);
7981 return NULL;
7982 }
7983
7984 /* make sure there is such a vsi and uplink */
505682cd 7985 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 7986 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7987 break;
505682cd 7988 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 7989 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7990 vsi_seid);
7991 return NULL;
7992 }
7993
7994 if (uplink_seid && uplink_seid != pf->mac_seid) {
7995 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7996 if (pf->veb[veb_idx] &&
7997 pf->veb[veb_idx]->seid == uplink_seid) {
7998 uplink_veb = pf->veb[veb_idx];
7999 break;
8000 }
8001 }
8002 if (!uplink_veb) {
8003 dev_info(&pf->pdev->dev,
8004 "uplink seid %d not found\n", uplink_seid);
8005 return NULL;
8006 }
8007 }
8008
8009 /* get veb sw struct */
8010 veb_idx = i40e_veb_mem_alloc(pf);
8011 if (veb_idx < 0)
8012 goto err_alloc;
8013 veb = pf->veb[veb_idx];
8014 veb->flags = flags;
8015 veb->uplink_seid = uplink_seid;
8016 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
8017 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
8018
8019 /* create the VEB in the switch */
8020 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
8021 if (ret)
8022 goto err_veb;
1bb8b935
SN		 8023 if (vsi_idx == pf->lan_vsi)
8024 pf->lan_veb = veb->idx;
41c445ff
JB		 8025
8026 return veb;
8027
8028err_veb:
8029 i40e_veb_clear(veb);
8030err_alloc:
8031 return NULL;
8032}
8033
8034/**
8035 * i40e_setup_pf_switch_element - set pf vars based on switch type
8036 * @pf: board private structure
8037 * @ele: element we are building info from
8038 * @num_reported: total number of elements
8039 * @printconfig: should we print the contents
8040 *
8041 * helper function to assist in extracting a few useful SEID values.
8042 **/
8043static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
8044 struct i40e_aqc_switch_config_element_resp *ele,
8045 u16 num_reported, bool printconfig)
8046{
8047 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
8048 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
8049 u8 element_type = ele->element_type;
8050 u16 seid = le16_to_cpu(ele->seid);
8051
8052 if (printconfig)
8053 dev_info(&pf->pdev->dev,
8054 "type=%d seid=%d uplink=%d downlink=%d\n",
8055 element_type, seid, uplink_seid, downlink_seid);
8056
8057 switch (element_type) {
8058 case I40E_SWITCH_ELEMENT_TYPE_MAC:
8059 pf->mac_seid = seid;
8060 break;
8061 case I40E_SWITCH_ELEMENT_TYPE_VEB:
8062 /* Main VEB? */
8063 if (uplink_seid != pf->mac_seid)
8064 break;
8065 if (pf->lan_veb == I40E_NO_VEB) {
8066 int v;
8067
8068 /* find existing or else empty VEB */
8069 for (v = 0; v < I40E_MAX_VEB; v++) {
8070 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
8071 pf->lan_veb = v;
8072 break;
8073 }
8074 }
8075 if (pf->lan_veb == I40E_NO_VEB) {
8076 v = i40e_veb_mem_alloc(pf);
8077 if (v < 0)
8078 break;
8079 pf->lan_veb = v;
8080 }
8081 }
8082
8083 pf->veb[pf->lan_veb]->seid = seid;
8084 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
8085 pf->veb[pf->lan_veb]->pf = pf;
8086 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
8087 break;
8088 case I40E_SWITCH_ELEMENT_TYPE_VSI:
8089 if (num_reported != 1)
8090 break;
8091 /* This is immediately after a reset so we can assume this is
8092 * the PF's VSI
8093 */
8094 pf->mac_seid = uplink_seid;
8095 pf->pf_seid = downlink_seid;
8096 pf->main_vsi_seid = seid;
8097 if (printconfig)
8098 dev_info(&pf->pdev->dev,
8099 "pf_seid=%d main_vsi_seid=%d\n",
8100 pf->pf_seid, pf->main_vsi_seid);
8101 break;
8102 case I40E_SWITCH_ELEMENT_TYPE_PF:
8103 case I40E_SWITCH_ELEMENT_TYPE_VF:
8104 case I40E_SWITCH_ELEMENT_TYPE_EMP:
8105 case I40E_SWITCH_ELEMENT_TYPE_BMC:
8106 case I40E_SWITCH_ELEMENT_TYPE_PE:
8107 case I40E_SWITCH_ELEMENT_TYPE_PA:
8108 /* ignore these for now */
8109 break;
8110 default:
8111 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
8112 element_type, seid);
8113 break;
8114 }
8115}
8116
8117/**
8118 * i40e_fetch_switch_configuration - Get switch config from firmware
8119 * @pf: board private structure
8120 * @printconfig: should we print the contents
8121 *
8122 * Get the current switch configuration from the device and
8123 * extract a few useful SEID values.
8124 **/
8125int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
8126{
8127 struct i40e_aqc_get_switch_config_resp *sw_config;
8128 u16 next_seid = 0;
8129 int ret = 0;
8130 u8 *aq_buf;
8131 int i;
8132
8133 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
8134 if (!aq_buf)
8135 return -ENOMEM;
8136
8137 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
8138 do {
8139 u16 num_reported, num_total;
8140
8141 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
8142 I40E_AQ_LARGE_BUF,
8143 &next_seid, NULL);
8144 if (ret) {
8145 dev_info(&pf->pdev->dev,
8146 "get switch config failed %d aq_err=%x\n",
8147 ret, pf->hw.aq.asq_last_status);
8148 kfree(aq_buf);
8149 return -ENOENT;
8150 }
8151
8152 num_reported = le16_to_cpu(sw_config->header.num_reported);
8153 num_total = le16_to_cpu(sw_config->header.num_total);
8154
8155 if (printconfig)
8156 dev_info(&pf->pdev->dev,
8157 "header: %d reported %d total\n",
8158 num_reported, num_total);
8159
41c445ff
JB		 8160 for (i = 0; i < num_reported; i++) {
8161 struct i40e_aqc_switch_config_element_resp *ele =
8162 &sw_config->element[i];
8163
8164 i40e_setup_pf_switch_element(pf, ele, num_reported,
8165 printconfig);
8166 }
8167 } while (next_seid != 0);
8168
8169 kfree(aq_buf);
8170 return ret;
8171}
8172
8173/**
8174 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8175 * @pf: board private structure
bc7d338f 8176 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8177 *
8178 * Returns 0 on success, negative value on failure
8179 **/
bc7d338f 8180static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 8181{
895106a5 8182 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 8183 int ret;
8184
8185 /* find out what's out there already */
8186 ret = i40e_fetch_switch_configuration(pf, false);
8187 if (ret) {
8188 dev_info(&pf->pdev->dev,
8189 "couldn't fetch switch config, err %d, aq_err %d\n",
8190 ret, pf->hw.aq.asq_last_status);
8191 return ret;
8192 }
8193 i40e_pf_reset_stats(pf);
8194
41c445ff 8195 /* first time setup */
bc7d338f 8196 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8197 struct i40e_vsi *vsi = NULL;
8198 u16 uplink_seid;
8199
8200 /* Set up the PF VSI associated with the PF's main VSI
8201 * that is already in the HW switch
8202 */
8203 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8204 uplink_seid = pf->veb[pf->lan_veb]->seid;
8205 else
8206 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8207 if (pf->lan_vsi == I40E_NO_VSI)
8208 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8209 else if (reinit)
8210 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8211 if (!vsi) {
8212 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8213 i40e_fdir_teardown(pf);
8214 return -EAGAIN;
8215 }
41c445ff
JB		 8216 } else {
8217 /* force a reset of TC and queue layout configurations */
8218 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8219 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8220 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8221 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8222 }
8223 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8224
cbf61325
ASJ		 8225 i40e_fdir_sb_setup(pf);
8226
41c445ff
JB		 8227 /* Setup static PF queue filter control settings */
8228 ret = i40e_setup_pf_filter_control(pf);
8229 if (ret) {
8230 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8231 ret);
8232 /* Failure here should not stop continuing other steps */
8233 }
8234
8235 /* enable RSS in the HW, even for only one queue, as the stack can use
8236 * the hash
8237 */
8238 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8239 i40e_config_rss(pf);
8240
8241 /* fill in link information and enable LSE reporting */
8242 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
8243 i40e_link_event(pf);
8244
d52c20b7 8245 /* Initialize user-specific link properties */
41c445ff
JB		 8246 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8247 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 8248 /* requested_mode is set in probe or by ethtool */
8249 if (!pf->fc_autoneg_status)
8250 goto no_autoneg;
8251
8252 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
8253 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 8254 pf->hw.fc.current_mode = I40E_FC_FULL;
8255 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
8256 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
8257 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
8258 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
8259 else
d52c20b7
JB		 8260 pf->hw.fc.current_mode = I40E_FC_NONE;
8261
8262 /* sync the flow control settings with the auto-neg values */
8263 switch (pf->hw.fc.current_mode) {
8264 case I40E_FC_FULL:
8265 txfc = 1;
8266 rxfc = 1;
8267 break;
8268 case I40E_FC_TX_PAUSE:
8269 txfc = 1;
8270 rxfc = 0;
8271 break;
8272 case I40E_FC_RX_PAUSE:
8273 txfc = 0;
8274 rxfc = 1;
8275 break;
8276 case I40E_FC_NONE:
8277 case I40E_FC_DEFAULT:
8278 txfc = 0;
8279 rxfc = 0;
8280 break;
8281 case I40E_FC_PFC:
8282 /* TBD */
8283 break;
8284 /* no default case, we have to handle all possibilities here */
8285 }
8286
8287 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8288
8289 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8290 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8291 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8292
8293 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8294
d52c20b7
JB		 8295 goto fc_complete;
8296
8297no_autoneg:
8298 /* disable L2 flow control, user can turn it on if they wish */
8299 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8300 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8301 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8302
8303fc_complete:
beb0dff1
JK		 8304 i40e_ptp_init(pf);
8305
41c445ff
JB		 8306 return ret;
8307}
8308
41c445ff
JB		 8309/**
8310 * i40e_determine_queue_usage - Work out queue distribution
8311 * @pf: board private structure
8312 **/
8313static void i40e_determine_queue_usage(struct i40e_pf *pf)
8314{
41c445ff
JB		 8315 int queues_left;
8316
8317 pf->num_lan_qps = 0;
41c445ff
JB		 8318
8319 /* Find the max queues to be put into basic use. We'll always be
8320 * using TC0, whether or not DCB is running, and TC0 will get the
8321 * big RSS set.
8322 */
8323 queues_left = pf->hw.func_caps.num_tx_qp;
8324
cbf61325 8325 if ((queues_left == 1) ||
9aa7e935 8326 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 8327 /* one qp for PF, no queues for anything else */
8328 queues_left = 0;
8329 pf->rss_size = pf->num_lan_qps = 1;
8330
8331 /* make sure all the fancies are disabled */
60ea5f83
JB		 8332 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8333 I40E_FLAG_FD_SB_ENABLED |
8334 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8335 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 8336 I40E_FLAG_SRIOV_ENABLED |
8337 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 8338 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
8339 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 8340 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 8341 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935
FZ		 8342 /* one qp for PF */
8343 pf->rss_size = pf->num_lan_qps = 1;
8344 queues_left -= pf->num_lan_qps;
8345
8346 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8347 I40E_FLAG_FD_SB_ENABLED |
8348 I40E_FLAG_FD_ATR_ENABLED |
8349 I40E_FLAG_DCB_ENABLED |
8350 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8351 } else {
cbf61325 8352 /* Not enough queues for all TCs */
4d9b6043 8353 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 8354 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 8355 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 8356 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8357 }
8358 pf->num_lan_qps = pf->rss_size_max;
8359 queues_left -= pf->num_lan_qps;
8360 }
8361
8362 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8363 if (queues_left > 1) {
8364 queues_left -= 1; /* save 1 queue for FD */
8365 } else {
8366 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8367 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8368 }
41c445ff
JB		 8369 }
8370
8371 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8372 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8373 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8374 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8375 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8376 }
8377
8378 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8379 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8380 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8381 (queues_left / pf->num_vmdq_qps));
8382 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8383 }
8384
f8ff1464 8385 pf->queues_left = queues_left;
41c445ff
JB		 8386}
8387
8388/**
8389 * i40e_setup_pf_filter_control - Setup PF static filter control
8390 * @pf: PF to be setup
8391 *
8392 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8393 * settings. If PE/FCoE are enabled then it will also set the per PF
8394 * based filter sizes required for them. It also enables Flow director,
8395 * ethertype and macvlan type filter settings for the pf.
8396 *
8397 * Returns 0 on success, negative on failure
8398 **/
8399static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8400{
8401 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8402
8403 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8404
8405 /* Flow Director is enabled */
60ea5f83 8406 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8407 settings->enable_fdir = true;
8408
8409 /* Ethtype and MACVLAN filters enabled for PF */
8410 settings->enable_ethtype = true;
8411 settings->enable_macvlan = true;
8412
8413 if (i40e_set_filter_control(&pf->hw, settings))
8414 return -ENOENT;
8415
8416 return 0;
8417}
8418
0c22b3dd
JB		 8419#define INFO_STRING_LEN 255
8420static void i40e_print_features(struct i40e_pf *pf)
8421{
8422 struct i40e_hw *hw = &pf->hw;
8423 char *buf, *string;
8424
8425 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8426 if (!string) {
8427 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8428 return;
8429 }
8430
8431 buf = string;
8432
8433 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8434#ifdef CONFIG_PCI_IOV
8435 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8436#endif
8437 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8438 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8439
8440 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8441 buf += sprintf(buf, "RSS ");
0c22b3dd 8442 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8443 buf += sprintf(buf, "FD_ATR ");
8444 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8445 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8446 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8447 }
4d9b6043 8448 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
0c22b3dd
JB		 8449 buf += sprintf(buf, "DCB ");
8450 if (pf->flags & I40E_FLAG_PTP)
8451 buf += sprintf(buf, "PTP ");
8452
8453 BUG_ON(buf > (string + INFO_STRING_LEN));
8454 dev_info(&pf->pdev->dev, "%s\n", string);
8455 kfree(string);
8456}
8457
41c445ff
JB		 8458/**
8459 * i40e_probe - Device initialization routine
8460 * @pdev: PCI device information struct
8461 * @ent: entry in i40e_pci_tbl
8462 *
8463 * i40e_probe initializes a pf identified by a pci_dev structure.
8464 * The OS initialization, configuring of the pf private structure,
8465 * and a hardware reset occur.
8466 *
8467 * Returns 0 on success, negative on failure
8468 **/
8469static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8470{
41c445ff
JB		 8471 struct i40e_pf *pf;
8472 struct i40e_hw *hw;
93cd765b 8473 static u16 pfs_found;
d4dfb81a 8474 u16 link_status;
41c445ff
JB		 8475 int err = 0;
8476 u32 len;
8a9eb7d3 8477 u32 i;
41c445ff
JB		 8478
8479 err = pci_enable_device_mem(pdev);
8480 if (err)
8481 return err;
8482
8483 /* set up for high or low dma */
6494294f 8484 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8485 if (err) {
e3e3bfdd
JS		 8486 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8487 if (err) {
8488 dev_err(&pdev->dev,
8489 "DMA configuration failed: 0x%x\n", err);
8490 goto err_dma;
8491 }
41c445ff
JB		 8492 }
8493
8494 /* set up pci connections */
8495 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8496 IORESOURCE_MEM), i40e_driver_name);
8497 if (err) {
8498 dev_info(&pdev->dev,
8499 "pci_request_selected_regions failed %d\n", err);
8500 goto err_pci_reg;
8501 }
8502
8503 pci_enable_pcie_error_reporting(pdev);
8504 pci_set_master(pdev);
8505
8506 /* Now that we have a PCI connection, we need to do the
8507 * low level device setup. This is primarily setting up
8508 * the Admin Queue structures and then querying for the
8509 * device's current profile information.
8510 */
8511 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8512 if (!pf) {
8513 err = -ENOMEM;
8514 goto err_pf_alloc;
8515 }
8516 pf->next_vsi = 0;
8517 pf->pdev = pdev;
8518 set_bit(__I40E_DOWN, &pf->state);
8519
8520 hw = &pf->hw;
8521 hw->back = pf;
8522 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8523 pci_resource_len(pdev, 0));
8524 if (!hw->hw_addr) {
8525 err = -EIO;
8526 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8527 (unsigned int)pci_resource_start(pdev, 0),
8528 (unsigned int)pci_resource_len(pdev, 0), err);
8529 goto err_ioremap;
8530 }
8531 hw->vendor_id = pdev->vendor;
8532 hw->device_id = pdev->device;
8533 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8534 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8535 hw->subsystem_device_id = pdev->subsystem_device;
8536 hw->bus.device = PCI_SLOT(pdev->devfn);
8537 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8538 pf->instance = pfs_found;
41c445ff 8539
7134f9ce
JB		 8540 /* do a special CORER for clearing PXE mode once at init */
8541 if (hw->revision_id == 0 &&
8542 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8543 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8544 i40e_flush(hw);
8545 msleep(200);
8546 pf->corer_count++;
8547
8548 i40e_clear_pxe_mode(hw);
8549 }
8550
41c445ff
JB		 8551 /* Reset here to make sure all is clean and to define PF 'n' */
8552 err = i40e_pf_reset(hw);
8553 if (err) {
8554 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8555 goto err_pf_reset;
8556 }
8557 pf->pfr_count++;
8558
8559 hw->aq.num_arq_entries = I40E_AQ_LEN;
8560 hw->aq.num_asq_entries = I40E_AQ_LEN;
8561 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8562 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8563 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8564 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8565 "%s-pf%d:misc",
8566 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8567
8568 err = i40e_init_shared_code(hw);
8569 if (err) {
8570 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8571 goto err_pf_reset;
8572 }
8573
d52c20b7
JB		 8574 /* set up a default setting for link flow control */
8575 pf->hw.fc.requested_mode = I40E_FC_NONE;
8576
41c445ff
JB		 8577 err = i40e_init_adminq(hw);
8578 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8579 if (err) {
8580 dev_info(&pdev->dev,
8581 "init_adminq failed: %d expecting API %02x.%02x\n",
8582 err,
8583 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8584 goto err_pf_reset;
8585 }
8586
4eb3f768
SN		 8587 i40e_verify_eeprom(pf);
8588
2c5fe33b
JB		 8589 /* Rev 0 hardware was never productized */
8590 if (hw->revision_id < 1)
8591 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8592
6ff4ef86 8593 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8594 err = i40e_get_capabilities(pf);
8595 if (err)
8596 goto err_adminq_setup;
8597
8598 err = i40e_sw_init(pf);
8599 if (err) {
8600 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8601 goto err_sw_init;
8602 }
8603
8604 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8605 hw->func_caps.num_rx_qp,
8606 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8607 if (err) {
8608 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8609 goto err_init_lan_hmc;
8610 }
8611
8612 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8613 if (err) {
8614 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8615 err = -ENOENT;
8616 goto err_configure_lan_hmc;
8617 }
8618
8619 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8620 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8621 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8622 err = -EIO;
8623 goto err_mac_addr;
8624 }
8625 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 8626 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
41c445ff
JB		 8627
8628 pci_set_drvdata(pdev, pf);
8629 pci_save_state(pdev);
4e3b35b0
NP		 8630#ifdef CONFIG_I40E_DCB
8631 err = i40e_init_pf_dcb(pf);
8632 if (err) {
8633 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
4d9b6043 8634 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 8635 /* Continue without DCB enabled */
4e3b35b0
NP		 8636 }
8637#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8638
8639 /* set up periodic task facility */
8640 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8641 pf->service_timer_period = HZ;
8642
8643 INIT_WORK(&pf->service_task, i40e_service_task);
8644 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8645 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8646 pf->link_check_timeout = jiffies;
8647
8e2773ae
SN		 8648 /* WoL defaults to disabled */
8649 pf->wol_en = false;
8650 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8651
41c445ff
JB		 8652 /* set up the main switch operations */
8653 i40e_determine_queue_usage(pf);
8654 i40e_init_interrupt_scheme(pf);
8655
505682cd
MW		 8656 /* The number of VSIs reported by the FW is the minimum guaranteed
8657 * to us; HW supports far more and we share the remaining pool with
8658 * the other PFs. We allocate space for more than the guarantee with
8659 * the understanding that we might not get them all later.
41c445ff 8660 */
505682cd
MW		 8661 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
8662 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
8663 else
8664 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
8665
8666 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
8667 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 8668 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8669 if (!pf->vsi) {
8670 err = -ENOMEM;
41c445ff 8671 goto err_switch_setup;
ed87ac09 8672 }
41c445ff 8673
bc7d338f 8674 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8675 if (err) {
8676 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8677 goto err_vsis;
8678 }
8a9eb7d3 8679 /* if FDIR VSI was set up, start it now */
505682cd 8680 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 8681 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8682 i40e_vsi_open(pf->vsi[i]);
8683 break;
8684 }
8685 }
41c445ff
JB		 8686
8687 /* The main driver is (mostly) up and happy. We need to set this state
8688 * before setting up the misc vector or we get a race and the vector
8689 * ends up disabled forever.
8690 */
8691 clear_bit(__I40E_DOWN, &pf->state);
8692
8693 /* In case of MSIX we are going to setup the misc vector right here
8694 * to handle admin queue events etc. In case of legacy and MSI
8695 * the misc functionality and queue processing is combined in
8696 * the same vector and that gets setup at open.
8697 */
8698 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8699 err = i40e_setup_misc_vector(pf);
8700 if (err) {
8701 dev_info(&pdev->dev,
8702 "setup of misc vector failed: %d\n", err);
8703 goto err_vsis;
8704 }
8705 }
8706
df805f62 8707#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8708 /* prep for VF support */
8709 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8710 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8711 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8712 u32 val;
8713
8714 /* disable link interrupts for VFs */
8715 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8716 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8717 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8718 i40e_flush(hw);
4aeec010
MW		 8719
8720 if (pci_num_vf(pdev)) {
8721 dev_info(&pdev->dev,
8722 "Active VFs found, allocating resources.\n");
8723 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8724 if (err)
8725 dev_info(&pdev->dev,
8726 "Error %d allocating resources for existing VFs\n",
8727 err);
8728 }
41c445ff 8729 }
df805f62 8730#endif /* CONFIG_PCI_IOV */
41c445ff 8731
93cd765b
ASJ		 8732 pfs_found++;
8733
41c445ff
JB		 8734 i40e_dbg_pf_init(pf);
8735
8736 /* tell the firmware that we're starting */
44033fac 8737 i40e_send_version(pf);
41c445ff
JB		 8738
8739 /* since everything's happy, start the service_task timer */
8740 mod_timer(&pf->service_timer,
8741 round_jiffies(jiffies + pf->service_timer_period));
8742
d4dfb81a
CS		 8743 /* Get the negotiated link width and speed from PCI config space */
8744 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8745
8746 i40e_set_pci_config_data(hw, link_status);
8747
69bfb110 8748 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8749 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8750 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8751 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8752 "Unknown"),
8753 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8754 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8755 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8756 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8757 "Unknown"));
8758
8759 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8760 hw->bus.speed < i40e_bus_speed_8000) {
8761 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8762 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8763 }
8764
0c22b3dd
JB		 8765 /* print a string summarizing features */
8766 i40e_print_features(pf);
8767
41c445ff
JB		 8768 return 0;
8769
8770 /* Unwind what we've done if something failed in the setup */
8771err_vsis:
8772 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8773 i40e_clear_interrupt_scheme(pf);
8774 kfree(pf->vsi);
04b03013
SN		 8775err_switch_setup:
8776 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8777 del_timer_sync(&pf->service_timer);
8778err_mac_addr:
8779err_configure_lan_hmc:
8780 (void)i40e_shutdown_lan_hmc(hw);
8781err_init_lan_hmc:
8782 kfree(pf->qp_pile);
8783 kfree(pf->irq_pile);
8784err_sw_init:
8785err_adminq_setup:
8786 (void)i40e_shutdown_adminq(hw);
8787err_pf_reset:
8788 iounmap(hw->hw_addr);
8789err_ioremap:
8790 kfree(pf);
8791err_pf_alloc:
8792 pci_disable_pcie_error_reporting(pdev);
8793 pci_release_selected_regions(pdev,
8794 pci_select_bars(pdev, IORESOURCE_MEM));
8795err_pci_reg:
8796err_dma:
8797 pci_disable_device(pdev);
8798 return err;
8799}
8800
8801/**
8802 * i40e_remove - Device removal routine
8803 * @pdev: PCI device information struct
8804 *
8805 * i40e_remove is called by the PCI subsystem to alert the driver
8806 * that is should release a PCI device. This could be caused by a
8807 * Hot-Plug event, or because the driver is going to be removed from
8808 * memory.
8809 **/
8810static void i40e_remove(struct pci_dev *pdev)
8811{
8812 struct i40e_pf *pf = pci_get_drvdata(pdev);
8813 i40e_status ret_code;
8814 u32 reg;
8815 int i;
8816
8817 i40e_dbg_pf_exit(pf);
8818
beb0dff1
JK		 8819 i40e_ptp_stop(pf);
8820
41c445ff
JB		 8821 /* no more scheduling of any task */
8822 set_bit(__I40E_DOWN, &pf->state);
8823 del_timer_sync(&pf->service_timer);
8824 cancel_work_sync(&pf->service_task);
8825
eb2d80bc
MW		 8826 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8827 i40e_free_vfs(pf);
8828 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8829 }
8830
41c445ff
JB		 8831 i40e_fdir_teardown(pf);
8832
8833 /* If there is a switch structure or any orphans, remove them.
8834 * This will leave only the PF's VSI remaining.
8835 */
8836 for (i = 0; i < I40E_MAX_VEB; i++) {
8837 if (!pf->veb[i])
8838 continue;
8839
8840 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8841 pf->veb[i]->uplink_seid == 0)
8842 i40e_switch_branch_release(pf->veb[i]);
8843 }
8844
8845 /* Now we can shutdown the PF's VSI, just before we kill
8846 * adminq and hmc.
8847 */
8848 if (pf->vsi[pf->lan_vsi])
8849 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8850
8851 i40e_stop_misc_vector(pf);
8852 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8853 synchronize_irq(pf->msix_entries[0].vector);
8854 free_irq(pf->msix_entries[0].vector, pf);
8855 }
8856
8857 /* shutdown and destroy the HMC */
60442dea
SN		 8858 if (pf->hw.hmc.hmc_obj) {
8859 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8860 if (ret_code)
8861 dev_warn(&pdev->dev,
8862 "Failed to destroy the HMC resources: %d\n",
8863 ret_code);
8864 }
41c445ff
JB		 8865
8866 /* shutdown the adminq */
41c445ff
JB		 8867 ret_code = i40e_shutdown_adminq(&pf->hw);
8868 if (ret_code)
8869 dev_warn(&pdev->dev,
8870 "Failed to destroy the Admin Queue resources: %d\n",
8871 ret_code);
8872
8873 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8874 i40e_clear_interrupt_scheme(pf);
505682cd 8875 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8876 if (pf->vsi[i]) {
8877 i40e_vsi_clear_rings(pf->vsi[i]);
8878 i40e_vsi_clear(pf->vsi[i]);
8879 pf->vsi[i] = NULL;
8880 }
8881 }
8882
8883 for (i = 0; i < I40E_MAX_VEB; i++) {
8884 kfree(pf->veb[i]);
8885 pf->veb[i] = NULL;
8886 }
8887
8888 kfree(pf->qp_pile);
8889 kfree(pf->irq_pile);
41c445ff
JB		 8890 kfree(pf->vsi);
8891
8892 /* force a PF reset to clean anything leftover */
8893 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8894 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8895 i40e_flush(&pf->hw);
8896
8897 iounmap(pf->hw.hw_addr);
8898 kfree(pf);
8899 pci_release_selected_regions(pdev,
8900 pci_select_bars(pdev, IORESOURCE_MEM));
8901
8902 pci_disable_pcie_error_reporting(pdev);
8903 pci_disable_device(pdev);
8904}
8905
8906/**
8907 * i40e_pci_error_detected - warning that something funky happened in PCI land
8908 * @pdev: PCI device information struct
8909 *
8910 * Called to warn that something happened and the error handling steps
8911 * are in progress. Allows the driver to quiesce things, be ready for
8912 * remediation.
8913 **/
8914static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8915 enum pci_channel_state error)
8916{
8917 struct i40e_pf *pf = pci_get_drvdata(pdev);
8918
8919 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8920
8921 /* shutdown all operations */
9007bccd
SN		 8922 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8923 rtnl_lock();
8924 i40e_prep_for_reset(pf);
8925 rtnl_unlock();
8926 }
41c445ff
JB		 8927
8928 /* Request a slot reset */
8929 return PCI_ERS_RESULT_NEED_RESET;
8930}
8931
8932/**
8933 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8934 * @pdev: PCI device information struct
8935 *
8936 * Called to find if the driver can work with the device now that
8937 * the pci slot has been reset. If a basic connection seems good
8938 * (registers are readable and have sane content) then return a
8939 * happy little PCI_ERS_RESULT_xxx.
8940 **/
8941static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8942{
8943 struct i40e_pf *pf = pci_get_drvdata(pdev);
8944 pci_ers_result_t result;
8945 int err;
8946 u32 reg;
8947
8948 dev_info(&pdev->dev, "%s\n", __func__);
8949 if (pci_enable_device_mem(pdev)) {
8950 dev_info(&pdev->dev,
8951 "Cannot re-enable PCI device after reset.\n");
8952 result = PCI_ERS_RESULT_DISCONNECT;
8953 } else {
8954 pci_set_master(pdev);
8955 pci_restore_state(pdev);
8956 pci_save_state(pdev);
8957 pci_wake_from_d3(pdev, false);
8958
8959 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8960 if (reg == 0)
8961 result = PCI_ERS_RESULT_RECOVERED;
8962 else
8963 result = PCI_ERS_RESULT_DISCONNECT;
8964 }
8965
8966 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8967 if (err) {
8968 dev_info(&pdev->dev,
8969 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8970 err);
8971 /* non-fatal, continue */
8972 }
8973
8974 return result;
8975}
8976
8977/**
8978 * i40e_pci_error_resume - restart operations after PCI error recovery
8979 * @pdev: PCI device information struct
8980 *
8981 * Called to allow the driver to bring things back up after PCI error
8982 * and/or reset recovery has finished.
8983 **/
8984static void i40e_pci_error_resume(struct pci_dev *pdev)
8985{
8986 struct i40e_pf *pf = pci_get_drvdata(pdev);
8987
8988 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8989 if (test_bit(__I40E_SUSPENDED, &pf->state))
8990 return;
8991
8992 rtnl_lock();
41c445ff 8993 i40e_handle_reset_warning(pf);
9007bccd
SN		 8994 rtnl_lock();
8995}
8996
8997/**
8998 * i40e_shutdown - PCI callback for shutting down
8999 * @pdev: PCI device information struct
9000 **/
9001static void i40e_shutdown(struct pci_dev *pdev)
9002{
9003 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9004 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9005
9006 set_bit(__I40E_SUSPENDED, &pf->state);
9007 set_bit(__I40E_DOWN, &pf->state);
9008 rtnl_lock();
9009 i40e_prep_for_reset(pf);
9010 rtnl_unlock();
9011
8e2773ae
SN		 9012 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9013 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9014
9007bccd 9015 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 9016 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9017 pci_set_power_state(pdev, PCI_D3hot);
9018 }
9019}
9020
9021#ifdef CONFIG_PM
9022/**
9023 * i40e_suspend - PCI callback for moving to D3
9024 * @pdev: PCI device information struct
9025 **/
9026static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
9027{
9028 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 9029 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 9030
9031 set_bit(__I40E_SUSPENDED, &pf->state);
9032 set_bit(__I40E_DOWN, &pf->state);
9033 rtnl_lock();
9034 i40e_prep_for_reset(pf);
9035 rtnl_unlock();
9036
8e2773ae
SN		 9037 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
9038 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
9039
9040 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 9041 pci_set_power_state(pdev, PCI_D3hot);
9042
9043 return 0;
41c445ff
JB		 9044}
9045
9007bccd
SN		 9046/**
9047 * i40e_resume - PCI callback for waking up from D3
9048 * @pdev: PCI device information struct
9049 **/
9050static int i40e_resume(struct pci_dev *pdev)
9051{
9052 struct i40e_pf *pf = pci_get_drvdata(pdev);
9053 u32 err;
9054
9055 pci_set_power_state(pdev, PCI_D0);
9056 pci_restore_state(pdev);
9057 /* pci_restore_state() clears dev->state_saves, so
9058 * call pci_save_state() again to restore it.
9059 */
9060 pci_save_state(pdev);
9061
9062 err = pci_enable_device_mem(pdev);
9063 if (err) {
9064 dev_err(&pdev->dev,
9065 "%s: Cannot enable PCI device from suspend\n",
9066 __func__);
9067 return err;
9068 }
9069 pci_set_master(pdev);
9070
9071 /* no wakeup events while running */
9072 pci_wake_from_d3(pdev, false);
9073
9074 /* handling the reset will rebuild the device state */
9075 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
9076 clear_bit(__I40E_DOWN, &pf->state);
9077 rtnl_lock();
9078 i40e_reset_and_rebuild(pf, false);
9079 rtnl_unlock();
9080 }
9081
9082 return 0;
9083}
9084
9085#endif
41c445ff
JB		 9086static const struct pci_error_handlers i40e_err_handler = {
9087 .error_detected = i40e_pci_error_detected,
9088 .slot_reset = i40e_pci_error_slot_reset,
9089 .resume = i40e_pci_error_resume,
9090};
9091
9092static struct pci_driver i40e_driver = {
9093 .name = i40e_driver_name,
9094 .id_table = i40e_pci_tbl,
9095 .probe = i40e_probe,
9096 .remove = i40e_remove,
9007bccd
SN		 9097#ifdef CONFIG_PM
9098 .suspend = i40e_suspend,
9099 .resume = i40e_resume,
9100#endif
9101 .shutdown = i40e_shutdown,
41c445ff
JB		 9102 .err_handler = &i40e_err_handler,
9103 .sriov_configure = i40e_pci_sriov_configure,
9104};
9105
9106/**
9107 * i40e_init_module - Driver registration routine
9108 *
9109 * i40e_init_module is the first routine called when the driver is
9110 * loaded. All it does is register with the PCI subsystem.
9111 **/
9112static int __init i40e_init_module(void)
9113{
9114 pr_info("%s: %s - version %s\n", i40e_driver_name,
9115 i40e_driver_string, i40e_driver_version_str);
9116 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
9117 i40e_dbg_init();
9118 return pci_register_driver(&i40e_driver);
9119}
9120module_init(i40e_init_module);
9121
9122/**
9123 * i40e_exit_module - Driver exit cleanup routine
9124 *
9125 * i40e_exit_module is called just before the driver is removed
9126 * from memory.
9127 **/
9128static void __exit i40e_exit_module(void)
9129{
9130 pci_unregister_driver(&i40e_driver);
9131 i40e_dbg_exit();
9132}
9133module_exit(i40e_exit_module);
Linux kernel - Deliverables
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