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i40e: remove Tx work for ptp
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
ded7b9a3 42#define DRV_VERSION_BUILD 46
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e
SN		 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X710), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_D), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
83
84#define I40E_MAX_VF_COUNT 128
85static int debug = -1;
86module_param(debug, int, 0);
87MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
88
89MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
90MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/**
95 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
96 * @hw: pointer to the HW structure
97 * @mem: ptr to mem struct to fill out
98 * @size: size of memory requested
99 * @alignment: what to align the allocation to
100 **/
101int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
102 u64 size, u32 alignment)
103{
104 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
105
106 mem->size = ALIGN(size, alignment);
107 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
108 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 109 if (!mem->va)
110 return -ENOMEM;
41c445ff 111
93bc73b8 112 return 0;
41c445ff
JB		 113}
114
115/**
116 * i40e_free_dma_mem_d - OS specific memory free for shared code
117 * @hw: pointer to the HW structure
118 * @mem: ptr to mem struct to free
119 **/
120int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
121{
122 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
123
124 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
125 mem->va = NULL;
126 mem->pa = 0;
127 mem->size = 0;
128
129 return 0;
130}
131
132/**
133 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
134 * @hw: pointer to the HW structure
135 * @mem: ptr to mem struct to fill out
136 * @size: size of memory requested
137 **/
138int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
139 u32 size)
140{
141 mem->size = size;
142 mem->va = kzalloc(size, GFP_KERNEL);
143
93bc73b8
JB		 144 if (!mem->va)
145 return -ENOMEM;
41c445ff 146
93bc73b8 147 return 0;
41c445ff
JB		 148}
149
150/**
151 * i40e_free_virt_mem_d - OS specific memory free for shared code
152 * @hw: pointer to the HW structure
153 * @mem: ptr to mem struct to free
154 **/
155int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
156{
157 /* it's ok to kfree a NULL pointer */
158 kfree(mem->va);
159 mem->va = NULL;
160 mem->size = 0;
161
162 return 0;
163}
164
165/**
166 * i40e_get_lump - find a lump of free generic resource
167 * @pf: board private structure
168 * @pile: the pile of resource to search
169 * @needed: the number of items needed
170 * @id: an owner id to stick on the items assigned
171 *
172 * Returns the base item index of the lump, or negative for error
173 *
174 * The search_hint trick and lack of advanced fit-finding only work
175 * because we're highly likely to have all the same size lump requests.
176 * Linear search time and any fragmentation should be minimal.
177 **/
178static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
179 u16 needed, u16 id)
180{
181 int ret = -ENOMEM;
ddf434ac 182 int i, j;
41c445ff
JB		 183
184 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
185 dev_info(&pf->pdev->dev,
186 "param err: pile=%p needed=%d id=0x%04x\n",
187 pile, needed, id);
188 return -EINVAL;
189 }
190
191 /* start the linear search with an imperfect hint */
192 i = pile->search_hint;
ddf434ac 193 while (i < pile->num_entries) {
41c445ff
JB		 194 /* skip already allocated entries */
195 if (pile->list[i] & I40E_PILE_VALID_BIT) {
196 i++;
197 continue;
198 }
199
200 /* do we have enough in this lump? */
201 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
202 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
203 break;
204 }
205
206 if (j == needed) {
207 /* there was enough, so assign it to the requestor */
208 for (j = 0; j < needed; j++)
209 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
210 ret = i;
211 pile->search_hint = i + j;
ddf434ac 212 break;
41c445ff
JB		 213 } else {
214 /* not enough, so skip over it and continue looking */
215 i += j;
216 }
217 }
218
219 return ret;
220}
221
222/**
223 * i40e_put_lump - return a lump of generic resource
224 * @pile: the pile of resource to search
225 * @index: the base item index
226 * @id: the owner id of the items assigned
227 *
228 * Returns the count of items in the lump
229 **/
230static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
231{
232 int valid_id = (id | I40E_PILE_VALID_BIT);
233 int count = 0;
234 int i;
235
236 if (!pile || index >= pile->num_entries)
237 return -EINVAL;
238
239 for (i = index;
240 i < pile->num_entries && pile->list[i] == valid_id;
241 i++) {
242 pile->list[i] = 0;
243 count++;
244 }
245
246 if (count && index < pile->search_hint)
247 pile->search_hint = index;
248
249 return count;
250}
251
252/**
253 * i40e_service_event_schedule - Schedule the service task to wake up
254 * @pf: board private structure
255 *
256 * If not already scheduled, this puts the task into the work queue
257 **/
258static void i40e_service_event_schedule(struct i40e_pf *pf)
259{
260 if (!test_bit(__I40E_DOWN, &pf->state) &&
261 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
262 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
263 schedule_work(&pf->service_task);
264}
265
266/**
267 * i40e_tx_timeout - Respond to a Tx Hang
268 * @netdev: network interface device structure
269 *
270 * If any port has noticed a Tx timeout, it is likely that the whole
271 * device is munged, not just the one netdev port, so go for the full
272 * reset.
273 **/
274static void i40e_tx_timeout(struct net_device *netdev)
275{
276 struct i40e_netdev_priv *np = netdev_priv(netdev);
277 struct i40e_vsi *vsi = np->vsi;
278 struct i40e_pf *pf = vsi->back;
279
280 pf->tx_timeout_count++;
281
282 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
283 pf->tx_timeout_recovery_level = 0;
284 pf->tx_timeout_last_recovery = jiffies;
285 netdev_info(netdev, "tx_timeout recovery level %d\n",
286 pf->tx_timeout_recovery_level);
287
288 switch (pf->tx_timeout_recovery_level) {
289 case 0:
290 /* disable and re-enable queues for the VSI */
291 if (in_interrupt()) {
292 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
293 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
294 } else {
295 i40e_vsi_reinit_locked(vsi);
296 }
297 break;
298 case 1:
299 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
300 break;
301 case 2:
302 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
303 break;
304 case 3:
305 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
306 break;
307 default:
308 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 309 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 310 i40e_down(vsi);
311 break;
312 }
313 i40e_service_event_schedule(pf);
314 pf->tx_timeout_recovery_level++;
315}
316
317/**
318 * i40e_release_rx_desc - Store the new tail and head values
319 * @rx_ring: ring to bump
320 * @val: new head index
321 **/
322static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
323{
324 rx_ring->next_to_use = val;
325
326 /* Force memory writes to complete before letting h/w
327 * know there are new descriptors to fetch. (Only
328 * applicable for weak-ordered memory model archs,
329 * such as IA-64).
330 */
331 wmb();
332 writel(val, rx_ring->tail);
333}
334
335/**
336 * i40e_get_vsi_stats_struct - Get System Network Statistics
337 * @vsi: the VSI we care about
338 *
339 * Returns the address of the device statistics structure.
340 * The statistics are actually updated from the service task.
341 **/
342struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
343{
344 return &vsi->net_stats;
345}
346
347/**
348 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
349 * @netdev: network interface device structure
350 *
351 * Returns the address of the device statistics structure.
352 * The statistics are actually updated from the service task.
353 **/
354static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
355 struct net_device *netdev,
980e9b11 356 struct rtnl_link_stats64 *stats)
41c445ff
JB		 357{
358 struct i40e_netdev_priv *np = netdev_priv(netdev);
359 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 360 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
361 int i;
362
bc7d338f
ASJ		 363 if (test_bit(__I40E_DOWN, &vsi->state))
364 return stats;
365
3c325ced
JB		 366 if (!vsi->tx_rings)
367 return stats;
368
980e9b11
AD		 369 rcu_read_lock();
370 for (i = 0; i < vsi->num_queue_pairs; i++) {
371 struct i40e_ring *tx_ring, *rx_ring;
372 u64 bytes, packets;
373 unsigned int start;
374
375 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
376 if (!tx_ring)
377 continue;
378
379 do {
57a7744e 380 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 381 packets = tx_ring->stats.packets;
382 bytes = tx_ring->stats.bytes;
57a7744e 383 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 384
385 stats->tx_packets += packets;
386 stats->tx_bytes += bytes;
387 rx_ring = &tx_ring[1];
388
389 do {
57a7744e 390 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 391 packets = rx_ring->stats.packets;
392 bytes = rx_ring->stats.bytes;
57a7744e 393 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 394
980e9b11
AD		 395 stats->rx_packets += packets;
396 stats->rx_bytes += bytes;
397 }
398 rcu_read_unlock();
399
400 /* following stats updated by ixgbe_watchdog_task() */
401 stats->multicast = vsi_stats->multicast;
402 stats->tx_errors = vsi_stats->tx_errors;
403 stats->tx_dropped = vsi_stats->tx_dropped;
404 stats->rx_errors = vsi_stats->rx_errors;
405 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
406 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 407
980e9b11 408 return stats;
41c445ff
JB		 409}
410
411/**
412 * i40e_vsi_reset_stats - Resets all stats of the given vsi
413 * @vsi: the VSI to have its stats reset
414 **/
415void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
416{
417 struct rtnl_link_stats64 *ns;
418 int i;
419
420 if (!vsi)
421 return;
422
423 ns = i40e_get_vsi_stats_struct(vsi);
424 memset(ns, 0, sizeof(*ns));
425 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
426 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
427 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 428 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 429 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 430 memset(&vsi->rx_rings[i]->stats, 0 ,
431 sizeof(vsi->rx_rings[i]->stats));
432 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
433 sizeof(vsi->rx_rings[i]->rx_stats));
434 memset(&vsi->tx_rings[i]->stats, 0 ,
435 sizeof(vsi->tx_rings[i]->stats));
436 memset(&vsi->tx_rings[i]->tx_stats, 0,
437 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 438 }
8e9dca53 439 }
41c445ff
JB		 440 vsi->stat_offsets_loaded = false;
441}
442
443/**
444 * i40e_pf_reset_stats - Reset all of the stats for the given pf
445 * @pf: the PF to be reset
446 **/
447void i40e_pf_reset_stats(struct i40e_pf *pf)
448{
449 memset(&pf->stats, 0, sizeof(pf->stats));
450 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
451 pf->stat_offsets_loaded = false;
452}
453
454/**
455 * i40e_stat_update48 - read and update a 48 bit stat from the chip
456 * @hw: ptr to the hardware info
457 * @hireg: the high 32 bit reg to read
458 * @loreg: the low 32 bit reg to read
459 * @offset_loaded: has the initial offset been loaded yet
460 * @offset: ptr to current offset value
461 * @stat: ptr to the stat
462 *
463 * Since the device stats are not reset at PFReset, they likely will not
464 * be zeroed when the driver starts. We'll save the first values read
465 * and use them as offsets to be subtracted from the raw values in order
466 * to report stats that count from zero. In the process, we also manage
467 * the potential roll-over.
468 **/
469static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
470 bool offset_loaded, u64 *offset, u64 *stat)
471{
472 u64 new_data;
473
ab60085e 474 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 475 new_data = rd32(hw, loreg);
476 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
477 } else {
478 new_data = rd64(hw, loreg);
479 }
480 if (!offset_loaded)
481 *offset = new_data;
482 if (likely(new_data >= *offset))
483 *stat = new_data - *offset;
484 else
485 *stat = (new_data + ((u64)1 << 48)) - *offset;
486 *stat &= 0xFFFFFFFFFFFFULL;
487}
488
489/**
490 * i40e_stat_update32 - read and update a 32 bit stat from the chip
491 * @hw: ptr to the hardware info
492 * @reg: the hw reg to read
493 * @offset_loaded: has the initial offset been loaded yet
494 * @offset: ptr to current offset value
495 * @stat: ptr to the stat
496 **/
497static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
498 bool offset_loaded, u64 *offset, u64 *stat)
499{
500 u32 new_data;
501
502 new_data = rd32(hw, reg);
503 if (!offset_loaded)
504 *offset = new_data;
505 if (likely(new_data >= *offset))
506 *stat = (u32)(new_data - *offset);
507 else
508 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
509}
510
511/**
512 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
513 * @vsi: the VSI to be updated
514 **/
515void i40e_update_eth_stats(struct i40e_vsi *vsi)
516{
517 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
518 struct i40e_pf *pf = vsi->back;
519 struct i40e_hw *hw = &pf->hw;
520 struct i40e_eth_stats *oes;
521 struct i40e_eth_stats *es; /* device's eth stats */
522
523 es = &vsi->eth_stats;
524 oes = &vsi->eth_stats_offsets;
525
526 /* Gather up the stats that the hw collects */
527 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->tx_errors, &es->tx_errors);
530 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
531 vsi->stat_offsets_loaded,
532 &oes->rx_discards, &es->rx_discards);
533
534 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
535 I40E_GLV_GORCL(stat_idx),
536 vsi->stat_offsets_loaded,
537 &oes->rx_bytes, &es->rx_bytes);
538 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
539 I40E_GLV_UPRCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_unicast, &es->rx_unicast);
542 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
543 I40E_GLV_MPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_multicast, &es->rx_multicast);
546 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
547 I40E_GLV_BPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_broadcast, &es->rx_broadcast);
550
551 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
552 I40E_GLV_GOTCL(stat_idx),
553 vsi->stat_offsets_loaded,
554 &oes->tx_bytes, &es->tx_bytes);
555 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
556 I40E_GLV_UPTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_unicast, &es->tx_unicast);
559 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
560 I40E_GLV_MPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_multicast, &es->tx_multicast);
563 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
564 I40E_GLV_BPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_broadcast, &es->tx_broadcast);
567 vsi->stat_offsets_loaded = true;
568}
569
570/**
571 * i40e_update_veb_stats - Update Switch component statistics
572 * @veb: the VEB being updated
573 **/
574static void i40e_update_veb_stats(struct i40e_veb *veb)
575{
576 struct i40e_pf *pf = veb->pf;
577 struct i40e_hw *hw = &pf->hw;
578 struct i40e_eth_stats *oes;
579 struct i40e_eth_stats *es; /* device's eth stats */
580 int idx = 0;
581
582 idx = veb->stats_idx;
583 es = &veb->stats;
584 oes = &veb->stats_offsets;
585
586 /* Gather up the stats that the hw collects */
587 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
588 veb->stat_offsets_loaded,
589 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 590 if (hw->revision_id > 0)
591 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
592 veb->stat_offsets_loaded,
593 &oes->rx_unknown_protocol,
594 &es->rx_unknown_protocol);
41c445ff
JB		 595 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_bytes, &es->rx_bytes);
598 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_unicast, &es->rx_unicast);
601 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_multicast, &es->rx_multicast);
604 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
605 veb->stat_offsets_loaded,
606 &oes->rx_broadcast, &es->rx_broadcast);
607
608 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_bytes, &es->tx_bytes);
611 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_unicast, &es->tx_unicast);
614 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_multicast, &es->tx_multicast);
617 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
618 veb->stat_offsets_loaded,
619 &oes->tx_broadcast, &es->tx_broadcast);
620 veb->stat_offsets_loaded = true;
621}
622
623/**
624 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
625 * @pf: the corresponding PF
626 *
627 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
628 **/
629static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
630{
631 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
632 struct i40e_hw_port_stats *nsd = &pf->stats;
633 struct i40e_hw *hw = &pf->hw;
634 u64 xoff = 0;
635 u16 i, v;
636
637 if ((hw->fc.current_mode != I40E_FC_FULL) &&
638 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
639 return;
640
641 xoff = nsd->link_xoff_rx;
642 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
643 pf->stat_offsets_loaded,
644 &osd->link_xoff_rx, &nsd->link_xoff_rx);
645
646 /* No new LFC xoff rx */
647 if (!(nsd->link_xoff_rx - xoff))
648 return;
649
650 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
651 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
652 struct i40e_vsi *vsi = pf->vsi[v];
653
654 if (!vsi)
655 continue;
656
657 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 658 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 659 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
660 }
661 }
662}
663
664/**
665 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
666 * @pf: the corresponding PF
667 *
668 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
669 **/
670static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
671{
672 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
673 struct i40e_hw_port_stats *nsd = &pf->stats;
674 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
675 struct i40e_dcbx_config *dcb_cfg;
676 struct i40e_hw *hw = &pf->hw;
677 u16 i, v;
678 u8 tc;
679
680 dcb_cfg = &hw->local_dcbx_config;
681
682 /* See if DCB enabled with PFC TC */
683 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
684 !(dcb_cfg->pfc.pfcenable)) {
685 i40e_update_link_xoff_rx(pf);
686 return;
687 }
688
689 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
690 u64 prio_xoff = nsd->priority_xoff_rx[i];
691 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
692 pf->stat_offsets_loaded,
693 &osd->priority_xoff_rx[i],
694 &nsd->priority_xoff_rx[i]);
695
696 /* No new PFC xoff rx */
697 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
698 continue;
699 /* Get the TC for given priority */
700 tc = dcb_cfg->etscfg.prioritytable[i];
701 xoff[tc] = true;
702 }
703
704 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
705 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
706 struct i40e_vsi *vsi = pf->vsi[v];
707
708 if (!vsi)
709 continue;
710
711 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 712 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 713
714 tc = ring->dcb_tc;
715 if (xoff[tc])
716 clear_bit(__I40E_HANG_CHECK_ARMED,
717 &ring->state);
718 }
719 }
720}
721
722/**
723 * i40e_update_stats - Update the board statistics counters.
724 * @vsi: the VSI to be updated
725 *
726 * There are a few instances where we store the same stat in a
727 * couple of different structs. This is partly because we have
728 * the netdev stats that need to be filled out, which is slightly
729 * different from the "eth_stats" defined by the chip and used in
730 * VF communications. We sort it all out here in a central place.
731 **/
732void i40e_update_stats(struct i40e_vsi *vsi)
733{
734 struct i40e_pf *pf = vsi->back;
735 struct i40e_hw *hw = &pf->hw;
736 struct rtnl_link_stats64 *ons;
737 struct rtnl_link_stats64 *ns; /* netdev stats */
738 struct i40e_eth_stats *oes;
739 struct i40e_eth_stats *es; /* device's eth stats */
740 u32 tx_restart, tx_busy;
741 u32 rx_page, rx_buf;
742 u64 rx_p, rx_b;
743 u64 tx_p, tx_b;
bee5af7e 744 u32 val;
41c445ff
JB		 745 int i;
746 u16 q;
747
748 if (test_bit(__I40E_DOWN, &vsi->state) ||
749 test_bit(__I40E_CONFIG_BUSY, &pf->state))
750 return;
751
752 ns = i40e_get_vsi_stats_struct(vsi);
753 ons = &vsi->net_stats_offsets;
754 es = &vsi->eth_stats;
755 oes = &vsi->eth_stats_offsets;
756
757 /* Gather up the netdev and vsi stats that the driver collects
758 * on the fly during packet processing
759 */
760 rx_b = rx_p = 0;
761 tx_b = tx_p = 0;
762 tx_restart = tx_busy = 0;
763 rx_page = 0;
764 rx_buf = 0;
980e9b11 765 rcu_read_lock();
41c445ff
JB		 766 for (q = 0; q < vsi->num_queue_pairs; q++) {
767 struct i40e_ring *p;
980e9b11
AD		 768 u64 bytes, packets;
769 unsigned int start;
770
771 /* locate Tx ring */
772 p = ACCESS_ONCE(vsi->tx_rings[q]);
773
774 do {
57a7744e 775 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 776 packets = p->stats.packets;
777 bytes = p->stats.bytes;
57a7744e 778 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 779 tx_b += bytes;
780 tx_p += packets;
781 tx_restart += p->tx_stats.restart_queue;
782 tx_busy += p->tx_stats.tx_busy;
41c445ff 783
980e9b11
AD		 784 /* Rx queue is part of the same block as Tx queue */
785 p = &p[1];
786 do {
57a7744e 787 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 788 packets = p->stats.packets;
789 bytes = p->stats.bytes;
57a7744e 790 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 791 rx_b += bytes;
792 rx_p += packets;
420136cc
MW		 793 rx_buf += p->rx_stats.alloc_buff_failed;
794 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 795 }
980e9b11 796 rcu_read_unlock();
41c445ff
JB		 797 vsi->tx_restart = tx_restart;
798 vsi->tx_busy = tx_busy;
799 vsi->rx_page_failed = rx_page;
800 vsi->rx_buf_failed = rx_buf;
801
802 ns->rx_packets = rx_p;
803 ns->rx_bytes = rx_b;
804 ns->tx_packets = tx_p;
805 ns->tx_bytes = tx_b;
806
807 i40e_update_eth_stats(vsi);
808 /* update netdev stats from eth stats */
809 ons->rx_errors = oes->rx_errors;
810 ns->rx_errors = es->rx_errors;
811 ons->tx_errors = oes->tx_errors;
812 ns->tx_errors = es->tx_errors;
813 ons->multicast = oes->rx_multicast;
814 ns->multicast = es->rx_multicast;
815 ons->tx_dropped = oes->tx_discards;
816 ns->tx_dropped = es->tx_discards;
817
818 /* Get the port data only if this is the main PF VSI */
819 if (vsi == pf->vsi[pf->lan_vsi]) {
820 struct i40e_hw_port_stats *nsd = &pf->stats;
821 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
822
823 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
824 I40E_GLPRT_GORCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
827 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
828 I40E_GLPRT_GOTCL(hw->port),
829 pf->stat_offsets_loaded,
830 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
831 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.rx_discards,
834 &nsd->eth.rx_discards);
835 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
836 pf->stat_offsets_loaded,
837 &osd->eth.tx_discards,
838 &nsd->eth.tx_discards);
839 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
840 I40E_GLPRT_MPRCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_multicast,
843 &nsd->eth.rx_multicast);
844
845 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
846 pf->stat_offsets_loaded,
847 &osd->tx_dropped_link_down,
848 &nsd->tx_dropped_link_down);
849
850 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
851 pf->stat_offsets_loaded,
852 &osd->crc_errors, &nsd->crc_errors);
853 ns->rx_crc_errors = nsd->crc_errors;
854
855 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
856 pf->stat_offsets_loaded,
857 &osd->illegal_bytes, &nsd->illegal_bytes);
858 ns->rx_errors = nsd->crc_errors
859 + nsd->illegal_bytes;
860
861 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_local_faults,
864 &nsd->mac_local_faults);
865 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
866 pf->stat_offsets_loaded,
867 &osd->mac_remote_faults,
868 &nsd->mac_remote_faults);
869
870 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
871 pf->stat_offsets_loaded,
872 &osd->rx_length_errors,
873 &nsd->rx_length_errors);
874 ns->rx_length_errors = nsd->rx_length_errors;
875
876 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
877 pf->stat_offsets_loaded,
878 &osd->link_xon_rx, &nsd->link_xon_rx);
879 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xon_tx, &nsd->link_xon_tx);
882 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
883 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
884 pf->stat_offsets_loaded,
885 &osd->link_xoff_tx, &nsd->link_xoff_tx);
886
887 for (i = 0; i < 8; i++) {
888 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_rx[i],
891 &nsd->priority_xon_rx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xon_tx[i],
895 &nsd->priority_xon_tx[i]);
896 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
897 pf->stat_offsets_loaded,
898 &osd->priority_xoff_tx[i],
899 &nsd->priority_xoff_tx[i]);
900 i40e_stat_update32(hw,
901 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
902 pf->stat_offsets_loaded,
903 &osd->priority_xon_2_xoff[i],
904 &nsd->priority_xon_2_xoff[i]);
905 }
906
907 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
908 I40E_GLPRT_PRC64L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_64, &nsd->rx_size_64);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
912 I40E_GLPRT_PRC127L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_127, &nsd->rx_size_127);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
916 I40E_GLPRT_PRC255L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_255, &nsd->rx_size_255);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
920 I40E_GLPRT_PRC511L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_511, &nsd->rx_size_511);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
924 I40E_GLPRT_PRC1023L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1023, &nsd->rx_size_1023);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
928 I40E_GLPRT_PRC1522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_1522, &nsd->rx_size_1522);
931 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
932 I40E_GLPRT_PRC9522L(hw->port),
933 pf->stat_offsets_loaded,
934 &osd->rx_size_big, &nsd->rx_size_big);
935
936 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
937 I40E_GLPRT_PTC64L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_64, &nsd->tx_size_64);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
941 I40E_GLPRT_PTC127L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_127, &nsd->tx_size_127);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
945 I40E_GLPRT_PTC255L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_255, &nsd->tx_size_255);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
949 I40E_GLPRT_PTC511L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_511, &nsd->tx_size_511);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
953 I40E_GLPRT_PTC1023L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1023, &nsd->tx_size_1023);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
957 I40E_GLPRT_PTC1522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_1522, &nsd->tx_size_1522);
960 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
961 I40E_GLPRT_PTC9522L(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->tx_size_big, &nsd->tx_size_big);
964
965 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->rx_undersize, &nsd->rx_undersize);
968 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->rx_fragments, &nsd->rx_fragments);
971 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
972 pf->stat_offsets_loaded,
973 &osd->rx_oversize, &nsd->rx_oversize);
974 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
975 pf->stat_offsets_loaded,
976 &osd->rx_jabber, &nsd->rx_jabber);
bee5af7e
ASJ		 977
978 val = rd32(hw, I40E_PRTPM_EEE_STAT);
979 nsd->tx_lpi_status =
980 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
981 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
982 nsd->rx_lpi_status =
983 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
984 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
985 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
986 pf->stat_offsets_loaded,
987 &osd->tx_lpi_count, &nsd->tx_lpi_count);
988 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
989 pf->stat_offsets_loaded,
990 &osd->rx_lpi_count, &nsd->rx_lpi_count);
41c445ff
JB		 991 }
992
993 pf->stat_offsets_loaded = true;
994}
995
996/**
997 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
998 * @vsi: the VSI to be searched
999 * @macaddr: the MAC address
1000 * @vlan: the vlan
1001 * @is_vf: make sure its a vf filter, else doesn't matter
1002 * @is_netdev: make sure its a netdev filter, else doesn't matter
1003 *
1004 * Returns ptr to the filter object or NULL
1005 **/
1006static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1007 u8 *macaddr, s16 vlan,
1008 bool is_vf, bool is_netdev)
1009{
1010 struct i40e_mac_filter *f;
1011
1012 if (!vsi || !macaddr)
1013 return NULL;
1014
1015 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1016 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1017 (vlan == f->vlan) &&
1018 (!is_vf || f->is_vf) &&
1019 (!is_netdev || f->is_netdev))
1020 return f;
1021 }
1022 return NULL;
1023}
1024
1025/**
1026 * i40e_find_mac - Find a mac addr in the macvlan filters list
1027 * @vsi: the VSI to be searched
1028 * @macaddr: the MAC address we are searching for
1029 * @is_vf: make sure its a vf filter, else doesn't matter
1030 * @is_netdev: make sure its a netdev filter, else doesn't matter
1031 *
1032 * Returns the first filter with the provided MAC address or NULL if
1033 * MAC address was not found
1034 **/
1035struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1036 bool is_vf, bool is_netdev)
1037{
1038 struct i40e_mac_filter *f;
1039
1040 if (!vsi || !macaddr)
1041 return NULL;
1042
1043 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1044 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1045 (!is_vf || f->is_vf) &&
1046 (!is_netdev || f->is_netdev))
1047 return f;
1048 }
1049 return NULL;
1050}
1051
1052/**
1053 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1054 * @vsi: the VSI to be searched
1055 *
1056 * Returns true if VSI is in vlan mode or false otherwise
1057 **/
1058bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1059{
1060 struct i40e_mac_filter *f;
1061
1062 /* Only -1 for all the filters denotes not in vlan mode
1063 * so we have to go through all the list in order to make sure
1064 */
1065 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1066 if (f->vlan >= 0)
1067 return true;
1068 }
1069
1070 return false;
1071}
1072
1073/**
1074 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1075 * @vsi: the VSI to be searched
1076 * @macaddr: the mac address to be filtered
1077 * @is_vf: true if it is a vf
1078 * @is_netdev: true if it is a netdev
1079 *
1080 * Goes through all the macvlan filters and adds a
1081 * macvlan filter for each unique vlan that already exists
1082 *
1083 * Returns first filter found on success, else NULL
1084 **/
1085struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1086 bool is_vf, bool is_netdev)
1087{
1088 struct i40e_mac_filter *f;
1089
1090 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1091 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1092 is_vf, is_netdev)) {
1093 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1094 is_vf, is_netdev))
41c445ff
JB		 1095 return NULL;
1096 }
1097 }
1098
1099 return list_first_entry_or_null(&vsi->mac_filter_list,
1100 struct i40e_mac_filter, list);
1101}
1102
1103/**
1104 * i40e_add_filter - Add a mac/vlan filter to the VSI
1105 * @vsi: the VSI to be searched
1106 * @macaddr: the MAC address
1107 * @vlan: the vlan
1108 * @is_vf: make sure its a vf filter, else doesn't matter
1109 * @is_netdev: make sure its a netdev filter, else doesn't matter
1110 *
1111 * Returns ptr to the filter object or NULL when no memory available.
1112 **/
1113struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1114 u8 *macaddr, s16 vlan,
1115 bool is_vf, bool is_netdev)
1116{
1117 struct i40e_mac_filter *f;
1118
1119 if (!vsi || !macaddr)
1120 return NULL;
1121
1122 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1123 if (!f) {
1124 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1125 if (!f)
1126 goto add_filter_out;
1127
1128 memcpy(f->macaddr, macaddr, ETH_ALEN);
1129 f->vlan = vlan;
1130 f->changed = true;
1131
1132 INIT_LIST_HEAD(&f->list);
1133 list_add(&f->list, &vsi->mac_filter_list);
1134 }
1135
1136 /* increment counter and add a new flag if needed */
1137 if (is_vf) {
1138 if (!f->is_vf) {
1139 f->is_vf = true;
1140 f->counter++;
1141 }
1142 } else if (is_netdev) {
1143 if (!f->is_netdev) {
1144 f->is_netdev = true;
1145 f->counter++;
1146 }
1147 } else {
1148 f->counter++;
1149 }
1150
1151 /* changed tells sync_filters_subtask to
1152 * push the filter down to the firmware
1153 */
1154 if (f->changed) {
1155 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1156 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1157 }
1158
1159add_filter_out:
1160 return f;
1161}
1162
1163/**
1164 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1165 * @vsi: the VSI to be searched
1166 * @macaddr: the MAC address
1167 * @vlan: the vlan
1168 * @is_vf: make sure it's a vf filter, else doesn't matter
1169 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1170 **/
1171void i40e_del_filter(struct i40e_vsi *vsi,
1172 u8 *macaddr, s16 vlan,
1173 bool is_vf, bool is_netdev)
1174{
1175 struct i40e_mac_filter *f;
1176
1177 if (!vsi || !macaddr)
1178 return;
1179
1180 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1181 if (!f || f->counter == 0)
1182 return;
1183
1184 if (is_vf) {
1185 if (f->is_vf) {
1186 f->is_vf = false;
1187 f->counter--;
1188 }
1189 } else if (is_netdev) {
1190 if (f->is_netdev) {
1191 f->is_netdev = false;
1192 f->counter--;
1193 }
1194 } else {
1195 /* make sure we don't remove a filter in use by vf or netdev */
1196 int min_f = 0;
1197 min_f += (f->is_vf ? 1 : 0);
1198 min_f += (f->is_netdev ? 1 : 0);
1199
1200 if (f->counter > min_f)
1201 f->counter--;
1202 }
1203
1204 /* counter == 0 tells sync_filters_subtask to
1205 * remove the filter from the firmware's list
1206 */
1207 if (f->counter == 0) {
1208 f->changed = true;
1209 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1210 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1211 }
1212}
1213
1214/**
1215 * i40e_set_mac - NDO callback to set mac address
1216 * @netdev: network interface device structure
1217 * @p: pointer to an address structure
1218 *
1219 * Returns 0 on success, negative on failure
1220 **/
1221static int i40e_set_mac(struct net_device *netdev, void *p)
1222{
1223 struct i40e_netdev_priv *np = netdev_priv(netdev);
1224 struct i40e_vsi *vsi = np->vsi;
1225 struct sockaddr *addr = p;
1226 struct i40e_mac_filter *f;
1227
1228 if (!is_valid_ether_addr(addr->sa_data))
1229 return -EADDRNOTAVAIL;
1230
1231 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1232
1233 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1234 return 0;
1235
80f6428f
ASJ		 1236 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1237 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1238 return -EADDRNOTAVAIL;
1239
41c445ff
JB		 1240 if (vsi->type == I40E_VSI_MAIN) {
1241 i40e_status ret;
1242 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1243 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1244 addr->sa_data, NULL);
1245 if (ret) {
1246 netdev_info(netdev,
1247 "Addr change for Main VSI failed: %d\n",
1248 ret);
1249 return -EADDRNOTAVAIL;
1250 }
1251
1252 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1253 }
1254
1255 /* In order to be sure to not drop any packets, add the new address
1256 * then delete the old one.
1257 */
1258 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1259 if (!f)
1260 return -ENOMEM;
1261
1262 i40e_sync_vsi_filters(vsi);
1263 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1264 i40e_sync_vsi_filters(vsi);
1265
1266 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1267
1268 return 0;
1269}
1270
1271/**
1272 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1273 * @vsi: the VSI being setup
1274 * @ctxt: VSI context structure
1275 * @enabled_tc: Enabled TCs bitmap
1276 * @is_add: True if called before Add VSI
1277 *
1278 * Setup VSI queue mapping for enabled traffic classes.
1279 **/
1280static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1281 struct i40e_vsi_context *ctxt,
1282 u8 enabled_tc,
1283 bool is_add)
1284{
1285 struct i40e_pf *pf = vsi->back;
1286 u16 sections = 0;
1287 u8 netdev_tc = 0;
1288 u16 numtc = 0;
1289 u16 qcount;
1290 u8 offset;
1291 u16 qmap;
1292 int i;
4e3b35b0 1293 u16 num_tc_qps = 0;
41c445ff
JB		 1294
1295 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1296 offset = 0;
1297
1298 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1299 /* Find numtc from enabled TC bitmap */
1300 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1301 if (enabled_tc & (1 << i)) /* TC is enabled */
1302 numtc++;
1303 }
1304 if (!numtc) {
1305 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1306 numtc = 1;
1307 }
1308 } else {
1309 /* At least TC0 is enabled in case of non-DCB case */
1310 numtc = 1;
1311 }
1312
1313 vsi->tc_config.numtc = numtc;
1314 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1315 /* Number of queues per enabled TC */
1316 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1317 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1318
1319 /* Setup queue offset/count for all TCs for given VSI */
1320 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1321 /* See if the given TC is enabled for the given VSI */
1322 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1323 int pow, num_qps;
1324
41c445ff
JB		 1325 switch (vsi->type) {
1326 case I40E_VSI_MAIN:
4e3b35b0 1327 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1328 break;
1329 case I40E_VSI_FDIR:
1330 case I40E_VSI_SRIOV:
1331 case I40E_VSI_VMDQ2:
1332 default:
4e3b35b0 1333 qcount = num_tc_qps;
41c445ff
JB		 1334 WARN_ON(i != 0);
1335 break;
1336 }
4e3b35b0
NP		 1337 vsi->tc_config.tc_info[i].qoffset = offset;
1338 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1339
1340 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1341 num_qps = qcount;
41c445ff 1342 pow = 0;
4e3b35b0 1343 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1344 pow++;
1345 num_qps >>= 1;
1346 }
1347
1348 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1349 qmap =
1350 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1351 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1352
4e3b35b0 1353 offset += qcount;
41c445ff
JB		 1354 } else {
1355 /* TC is not enabled so set the offset to
1356 * default queue and allocate one queue
1357 * for the given TC.
1358 */
1359 vsi->tc_config.tc_info[i].qoffset = 0;
1360 vsi->tc_config.tc_info[i].qcount = 1;
1361 vsi->tc_config.tc_info[i].netdev_tc = 0;
1362
1363 qmap = 0;
1364 }
1365 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1366 }
1367
1368 /* Set actual Tx/Rx queue pairs */
1369 vsi->num_queue_pairs = offset;
1370
1371 /* Scheduler section valid can only be set for ADD VSI */
1372 if (is_add) {
1373 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1374
1375 ctxt->info.up_enable_bits = enabled_tc;
1376 }
1377 if (vsi->type == I40E_VSI_SRIOV) {
1378 ctxt->info.mapping_flags |=
1379 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1380 for (i = 0; i < vsi->num_queue_pairs; i++)
1381 ctxt->info.queue_mapping[i] =
1382 cpu_to_le16(vsi->base_queue + i);
1383 } else {
1384 ctxt->info.mapping_flags |=
1385 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1386 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1387 }
1388 ctxt->info.valid_sections |= cpu_to_le16(sections);
1389}
1390
1391/**
1392 * i40e_set_rx_mode - NDO callback to set the netdev filters
1393 * @netdev: network interface device structure
1394 **/
1395static void i40e_set_rx_mode(struct net_device *netdev)
1396{
1397 struct i40e_netdev_priv *np = netdev_priv(netdev);
1398 struct i40e_mac_filter *f, *ftmp;
1399 struct i40e_vsi *vsi = np->vsi;
1400 struct netdev_hw_addr *uca;
1401 struct netdev_hw_addr *mca;
1402 struct netdev_hw_addr *ha;
1403
1404 /* add addr if not already in the filter list */
1405 netdev_for_each_uc_addr(uca, netdev) {
1406 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1407 if (i40e_is_vsi_in_vlan(vsi))
1408 i40e_put_mac_in_vlan(vsi, uca->addr,
1409 false, true);
1410 else
1411 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1412 false, true);
1413 }
1414 }
1415
1416 netdev_for_each_mc_addr(mca, netdev) {
1417 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1418 if (i40e_is_vsi_in_vlan(vsi))
1419 i40e_put_mac_in_vlan(vsi, mca->addr,
1420 false, true);
1421 else
1422 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1423 false, true);
1424 }
1425 }
1426
1427 /* remove filter if not in netdev list */
1428 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1429 bool found = false;
1430
1431 if (!f->is_netdev)
1432 continue;
1433
1434 if (is_multicast_ether_addr(f->macaddr)) {
1435 netdev_for_each_mc_addr(mca, netdev) {
1436 if (ether_addr_equal(mca->addr, f->macaddr)) {
1437 found = true;
1438 break;
1439 }
1440 }
1441 } else {
1442 netdev_for_each_uc_addr(uca, netdev) {
1443 if (ether_addr_equal(uca->addr, f->macaddr)) {
1444 found = true;
1445 break;
1446 }
1447 }
1448
1449 for_each_dev_addr(netdev, ha) {
1450 if (ether_addr_equal(ha->addr, f->macaddr)) {
1451 found = true;
1452 break;
1453 }
1454 }
1455 }
1456 if (!found)
1457 i40e_del_filter(
1458 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1459 }
1460
1461 /* check for other flag changes */
1462 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1463 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1464 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1465 }
1466}
1467
1468/**
1469 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1470 * @vsi: ptr to the VSI
1471 *
1472 * Push any outstanding VSI filter changes through the AdminQ.
1473 *
1474 * Returns 0 or error value
1475 **/
1476int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1477{
1478 struct i40e_mac_filter *f, *ftmp;
1479 bool promisc_forced_on = false;
1480 bool add_happened = false;
1481 int filter_list_len = 0;
1482 u32 changed_flags = 0;
dcae29be 1483 i40e_status aq_ret = 0;
41c445ff
JB		 1484 struct i40e_pf *pf;
1485 int num_add = 0;
1486 int num_del = 0;
1487 u16 cmd_flags;
1488
1489 /* empty array typed pointers, kcalloc later */
1490 struct i40e_aqc_add_macvlan_element_data *add_list;
1491 struct i40e_aqc_remove_macvlan_element_data *del_list;
1492
1493 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1494 usleep_range(1000, 2000);
1495 pf = vsi->back;
1496
1497 if (vsi->netdev) {
1498 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1499 vsi->current_netdev_flags = vsi->netdev->flags;
1500 }
1501
1502 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1503 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1504
1505 filter_list_len = pf->hw.aq.asq_buf_size /
1506 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1507 del_list = kcalloc(filter_list_len,
1508 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1509 GFP_KERNEL);
1510 if (!del_list)
1511 return -ENOMEM;
1512
1513 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1514 if (!f->changed)
1515 continue;
1516
1517 if (f->counter != 0)
1518 continue;
1519 f->changed = false;
1520 cmd_flags = 0;
1521
1522 /* add to delete list */
1523 memcpy(del_list[num_del].mac_addr,
1524 f->macaddr, ETH_ALEN);
1525 del_list[num_del].vlan_tag =
1526 cpu_to_le16((u16)(f->vlan ==
1527 I40E_VLAN_ANY ? 0 : f->vlan));
1528
41c445ff
JB		 1529 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1530 del_list[num_del].flags = cmd_flags;
1531 num_del++;
1532
1533 /* unlink from filter list */
1534 list_del(&f->list);
1535 kfree(f);
1536
1537 /* flush a full buffer */
1538 if (num_del == filter_list_len) {
dcae29be 1539 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1540 vsi->seid, del_list, num_del,
1541 NULL);
1542 num_del = 0;
1543 memset(del_list, 0, sizeof(*del_list));
1544
dcae29be 1545 if (aq_ret)
41c445ff
JB		 1546 dev_info(&pf->pdev->dev,
1547 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1548 aq_ret,
41c445ff
JB		 1549 pf->hw.aq.asq_last_status);
1550 }
1551 }
1552 if (num_del) {
dcae29be 1553 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1554 del_list, num_del, NULL);
1555 num_del = 0;
1556
dcae29be 1557 if (aq_ret)
41c445ff
JB		 1558 dev_info(&pf->pdev->dev,
1559 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1560 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1561 }
1562
1563 kfree(del_list);
1564 del_list = NULL;
1565
1566 /* do all the adds now */
1567 filter_list_len = pf->hw.aq.asq_buf_size /
1568 sizeof(struct i40e_aqc_add_macvlan_element_data),
1569 add_list = kcalloc(filter_list_len,
1570 sizeof(struct i40e_aqc_add_macvlan_element_data),
1571 GFP_KERNEL);
1572 if (!add_list)
1573 return -ENOMEM;
1574
1575 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1576 if (!f->changed)
1577 continue;
1578
1579 if (f->counter == 0)
1580 continue;
1581 f->changed = false;
1582 add_happened = true;
1583 cmd_flags = 0;
1584
1585 /* add to add array */
1586 memcpy(add_list[num_add].mac_addr,
1587 f->macaddr, ETH_ALEN);
1588 add_list[num_add].vlan_tag =
1589 cpu_to_le16(
1590 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1591 add_list[num_add].queue_number = 0;
1592
1593 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1594 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1595 num_add++;
1596
1597 /* flush a full buffer */
1598 if (num_add == filter_list_len) {
dcae29be
JB		 1599 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1600 add_list, num_add,
1601 NULL);
41c445ff
JB		 1602 num_add = 0;
1603
dcae29be 1604 if (aq_ret)
41c445ff
JB		 1605 break;
1606 memset(add_list, 0, sizeof(*add_list));
1607 }
1608 }
1609 if (num_add) {
dcae29be
JB		 1610 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1611 add_list, num_add, NULL);
41c445ff
JB		 1612 num_add = 0;
1613 }
1614 kfree(add_list);
1615 add_list = NULL;
1616
dcae29be 1617 if (add_happened && (!aq_ret)) {
41c445ff 1618 /* do nothing */;
dcae29be 1619 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1620 dev_info(&pf->pdev->dev,
1621 "add filter failed, err %d, aq_err %d\n",
dcae29be 1622 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1623 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1624 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1625 &vsi->state)) {
1626 promisc_forced_on = true;
1627 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1628 &vsi->state);
1629 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1630 }
1631 }
1632 }
1633
1634 /* check for changes in promiscuous modes */
1635 if (changed_flags & IFF_ALLMULTI) {
1636 bool cur_multipromisc;
1637 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1638 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1639 vsi->seid,
1640 cur_multipromisc,
1641 NULL);
1642 if (aq_ret)
41c445ff
JB		 1643 dev_info(&pf->pdev->dev,
1644 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1645 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1646 }
1647 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1648 bool cur_promisc;
1649 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1650 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1651 &vsi->state));
dcae29be
JB		 1652 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1653 vsi->seid,
1654 cur_promisc, NULL);
1655 if (aq_ret)
41c445ff
JB		 1656 dev_info(&pf->pdev->dev,
1657 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1658 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1659 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1660 vsi->seid,
1661 cur_promisc, NULL);
1662 if (aq_ret)
1663 dev_info(&pf->pdev->dev,
1664 "set brdcast promisc failed, err %d, aq_err %d\n",
1665 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1666 }
1667
1668 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1669 return 0;
1670}
1671
1672/**
1673 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1674 * @pf: board private structure
1675 **/
1676static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1677{
1678 int v;
1679
1680 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1681 return;
1682 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1683
1684 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1685 if (pf->vsi[v] &&
1686 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1687 i40e_sync_vsi_filters(pf->vsi[v]);
1688 }
1689}
1690
1691/**
1692 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1693 * @netdev: network interface device structure
1694 * @new_mtu: new value for maximum frame size
1695 *
1696 * Returns 0 on success, negative on failure
1697 **/
1698static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1699{
1700 struct i40e_netdev_priv *np = netdev_priv(netdev);
1701 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1702 struct i40e_vsi *vsi = np->vsi;
1703
1704 /* MTU < 68 is an error and causes problems on some kernels */
1705 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1706 return -EINVAL;
1707
1708 netdev_info(netdev, "changing MTU from %d to %d\n",
1709 netdev->mtu, new_mtu);
1710 netdev->mtu = new_mtu;
1711 if (netif_running(netdev))
1712 i40e_vsi_reinit_locked(vsi);
1713
1714 return 0;
1715}
1716
beb0dff1
JK		 1717/**
1718 * i40e_ioctl - Access the hwtstamp interface
1719 * @netdev: network interface device structure
1720 * @ifr: interface request data
1721 * @cmd: ioctl command
1722 **/
1723int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1724{
1725 struct i40e_netdev_priv *np = netdev_priv(netdev);
1726 struct i40e_pf *pf = np->vsi->back;
1727
1728 switch (cmd) {
1729 case SIOCGHWTSTAMP:
1730 return i40e_ptp_get_ts_config(pf, ifr);
1731 case SIOCSHWTSTAMP:
1732 return i40e_ptp_set_ts_config(pf, ifr);
1733 default:
1734 return -EOPNOTSUPP;
1735 }
1736}
1737
41c445ff
JB		 1738/**
1739 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1740 * @vsi: the vsi being adjusted
1741 **/
1742void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1743{
1744 struct i40e_vsi_context ctxt;
1745 i40e_status ret;
1746
1747 if ((vsi->info.valid_sections &
1748 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1749 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1750 return; /* already enabled */
1751
1752 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1753 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1754 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1755
1756 ctxt.seid = vsi->seid;
1757 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1758 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1759 if (ret) {
1760 dev_info(&vsi->back->pdev->dev,
1761 "%s: update vsi failed, aq_err=%d\n",
1762 __func__, vsi->back->hw.aq.asq_last_status);
1763 }
1764}
1765
1766/**
1767 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1768 * @vsi: the vsi being adjusted
1769 **/
1770void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1771{
1772 struct i40e_vsi_context ctxt;
1773 i40e_status ret;
1774
1775 if ((vsi->info.valid_sections &
1776 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1777 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1778 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1779 return; /* already disabled */
1780
1781 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1782 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1783 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1784
1785 ctxt.seid = vsi->seid;
1786 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1787 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1788 if (ret) {
1789 dev_info(&vsi->back->pdev->dev,
1790 "%s: update vsi failed, aq_err=%d\n",
1791 __func__, vsi->back->hw.aq.asq_last_status);
1792 }
1793}
1794
1795/**
1796 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1797 * @netdev: network interface to be adjusted
1798 * @features: netdev features to test if VLAN offload is enabled or not
1799 **/
1800static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1801{
1802 struct i40e_netdev_priv *np = netdev_priv(netdev);
1803 struct i40e_vsi *vsi = np->vsi;
1804
1805 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1806 i40e_vlan_stripping_enable(vsi);
1807 else
1808 i40e_vlan_stripping_disable(vsi);
1809}
1810
1811/**
1812 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1813 * @vsi: the vsi being configured
1814 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1815 **/
1816int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1817{
1818 struct i40e_mac_filter *f, *add_f;
1819 bool is_netdev, is_vf;
41c445ff
JB		 1820
1821 is_vf = (vsi->type == I40E_VSI_SRIOV);
1822 is_netdev = !!(vsi->netdev);
1823
1824 if (is_netdev) {
1825 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1826 is_vf, is_netdev);
1827 if (!add_f) {
1828 dev_info(&vsi->back->pdev->dev,
1829 "Could not add vlan filter %d for %pM\n",
1830 vid, vsi->netdev->dev_addr);
1831 return -ENOMEM;
1832 }
1833 }
1834
1835 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1836 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1837 if (!add_f) {
1838 dev_info(&vsi->back->pdev->dev,
1839 "Could not add vlan filter %d for %pM\n",
1840 vid, f->macaddr);
1841 return -ENOMEM;
1842 }
1843 }
1844
41c445ff
JB		 1845 /* Now if we add a vlan tag, make sure to check if it is the first
1846 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1847 * with 0, so we now accept untagged and specified tagged traffic
1848 * (and not any taged and untagged)
1849 */
1850 if (vid > 0) {
1851 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1852 I40E_VLAN_ANY,
1853 is_vf, is_netdev)) {
1854 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1855 I40E_VLAN_ANY, is_vf, is_netdev);
1856 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1857 is_vf, is_netdev);
1858 if (!add_f) {
1859 dev_info(&vsi->back->pdev->dev,
1860 "Could not add filter 0 for %pM\n",
1861 vsi->netdev->dev_addr);
1862 return -ENOMEM;
1863 }
1864 }
8d82a7c5 1865 }
41c445ff 1866
8d82a7c5
GR		 1867 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1868 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1869 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1870 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1871 is_vf, is_netdev)) {
1872 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1873 is_vf, is_netdev);
1874 add_f = i40e_add_filter(vsi, f->macaddr,
1875 0, is_vf, is_netdev);
1876 if (!add_f) {
1877 dev_info(&vsi->back->pdev->dev,
1878 "Could not add filter 0 for %pM\n",
1879 f->macaddr);
1880 return -ENOMEM;
1881 }
1882 }
1883 }
41c445ff
JB		 1884 }
1885
80f6428f
ASJ		 1886 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1887 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1888 return 0;
1889
1890 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1891}
1892
1893/**
1894 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1895 * @vsi: the vsi being configured
1896 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1897 *
1898 * Return: 0 on success or negative otherwise
41c445ff
JB		 1899 **/
1900int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1901{
1902 struct net_device *netdev = vsi->netdev;
1903 struct i40e_mac_filter *f, *add_f;
1904 bool is_vf, is_netdev;
1905 int filter_count = 0;
41c445ff
JB		 1906
1907 is_vf = (vsi->type == I40E_VSI_SRIOV);
1908 is_netdev = !!(netdev);
1909
1910 if (is_netdev)
1911 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1912
1913 list_for_each_entry(f, &vsi->mac_filter_list, list)
1914 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1915
41c445ff
JB		 1916 /* go through all the filters for this VSI and if there is only
1917 * vid == 0 it means there are no other filters, so vid 0 must
1918 * be replaced with -1. This signifies that we should from now
1919 * on accept any traffic (with any tag present, or untagged)
1920 */
1921 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1922 if (is_netdev) {
1923 if (f->vlan &&
1924 ether_addr_equal(netdev->dev_addr, f->macaddr))
1925 filter_count++;
1926 }
1927
1928 if (f->vlan)
1929 filter_count++;
1930 }
1931
1932 if (!filter_count && is_netdev) {
1933 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1934 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1935 is_vf, is_netdev);
1936 if (!f) {
1937 dev_info(&vsi->back->pdev->dev,
1938 "Could not add filter %d for %pM\n",
1939 I40E_VLAN_ANY, netdev->dev_addr);
1940 return -ENOMEM;
1941 }
1942 }
1943
1944 if (!filter_count) {
1945 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1946 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1947 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1948 is_vf, is_netdev);
1949 if (!add_f) {
1950 dev_info(&vsi->back->pdev->dev,
1951 "Could not add filter %d for %pM\n",
1952 I40E_VLAN_ANY, f->macaddr);
1953 return -ENOMEM;
1954 }
1955 }
1956 }
1957
80f6428f
ASJ		 1958 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1959 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1960 return 0;
1961
41c445ff
JB		 1962 return i40e_sync_vsi_filters(vsi);
1963}
1964
1965/**
1966 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1967 * @netdev: network interface to be adjusted
1968 * @vid: vlan id to be added
078b5876
JB		 1969 *
1970 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1971 **/
1972static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1973 __always_unused __be16 proto, u16 vid)
1974{
1975 struct i40e_netdev_priv *np = netdev_priv(netdev);
1976 struct i40e_vsi *vsi = np->vsi;
078b5876 1977 int ret = 0;
41c445ff
JB		 1978
1979 if (vid > 4095)
078b5876
JB		 1980 return -EINVAL;
1981
1982 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1983
6982d429
ASJ		 1984 /* If the network stack called us with vid = 0 then
1985 * it is asking to receive priority tagged packets with
1986 * vlan id 0. Our HW receives them by default when configured
1987 * to receive untagged packets so there is no need to add an
1988 * extra filter for vlan 0 tagged packets.
41c445ff 1989 */
6982d429
ASJ		 1990 if (vid)
1991 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 1992
078b5876
JB		 1993 if (!ret && (vid < VLAN_N_VID))
1994 set_bit(vid, vsi->active_vlans);
41c445ff 1995
078b5876 1996 return ret;
41c445ff
JB		 1997}
1998
1999/**
2000 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2001 * @netdev: network interface to be adjusted
2002 * @vid: vlan id to be removed
078b5876 2003 *
fdfd943e 2004 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2005 **/
2006static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2007 __always_unused __be16 proto, u16 vid)
2008{
2009 struct i40e_netdev_priv *np = netdev_priv(netdev);
2010 struct i40e_vsi *vsi = np->vsi;
2011
078b5876
JB		 2012 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2013
41c445ff
JB		 2014 /* return code is ignored as there is nothing a user
2015 * can do about failure to remove and a log message was
078b5876 2016 * already printed from the other function
41c445ff
JB		 2017 */
2018 i40e_vsi_kill_vlan(vsi, vid);
2019
2020 clear_bit(vid, vsi->active_vlans);
078b5876 2021
41c445ff
JB		 2022 return 0;
2023}
2024
2025/**
2026 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2027 * @vsi: the vsi being brought back up
2028 **/
2029static void i40e_restore_vlan(struct i40e_vsi *vsi)
2030{
2031 u16 vid;
2032
2033 if (!vsi->netdev)
2034 return;
2035
2036 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2037
2038 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2039 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2040 vid);
2041}
2042
2043/**
2044 * i40e_vsi_add_pvid - Add pvid for the VSI
2045 * @vsi: the vsi being adjusted
2046 * @vid: the vlan id to set as a PVID
2047 **/
dcae29be 2048int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2049{
2050 struct i40e_vsi_context ctxt;
dcae29be 2051 i40e_status aq_ret;
41c445ff
JB		 2052
2053 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2054 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2055 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2056 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2057 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2058
2059 ctxt.seid = vsi->seid;
2060 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2061 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2062 if (aq_ret) {
41c445ff
JB		 2063 dev_info(&vsi->back->pdev->dev,
2064 "%s: update vsi failed, aq_err=%d\n",
2065 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2066 return -ENOENT;
41c445ff
JB		 2067 }
2068
dcae29be 2069 return 0;
41c445ff
JB		 2070}
2071
2072/**
2073 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2074 * @vsi: the vsi being adjusted
2075 *
2076 * Just use the vlan_rx_register() service to put it back to normal
2077 **/
2078void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2079{
6c12fcbf
GR		 2080 i40e_vlan_stripping_disable(vsi);
2081
41c445ff 2082 vsi->info.pvid = 0;
41c445ff
JB		 2083}
2084
2085/**
2086 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2087 * @vsi: ptr to the VSI
2088 *
2089 * If this function returns with an error, then it's possible one or
2090 * more of the rings is populated (while the rest are not). It is the
2091 * callers duty to clean those orphaned rings.
2092 *
2093 * Return 0 on success, negative on failure
2094 **/
2095static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2096{
2097 int i, err = 0;
2098
2099 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2100 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2101
2102 return err;
2103}
2104
2105/**
2106 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2107 * @vsi: ptr to the VSI
2108 *
2109 * Free VSI's transmit software resources
2110 **/
2111static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2112{
2113 int i;
2114
8e9dca53
GR		 2115 if (!vsi->tx_rings)
2116 return;
2117
41c445ff 2118 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2119 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2120 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2121}
2122
2123/**
2124 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2125 * @vsi: ptr to the VSI
2126 *
2127 * If this function returns with an error, then it's possible one or
2128 * more of the rings is populated (while the rest are not). It is the
2129 * callers duty to clean those orphaned rings.
2130 *
2131 * Return 0 on success, negative on failure
2132 **/
2133static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2134{
2135 int i, err = 0;
2136
2137 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2138 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2139 return err;
2140}
2141
2142/**
2143 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2144 * @vsi: ptr to the VSI
2145 *
2146 * Free all receive software resources
2147 **/
2148static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2149{
2150 int i;
2151
8e9dca53
GR		 2152 if (!vsi->rx_rings)
2153 return;
2154
41c445ff 2155 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2156 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2157 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2158}
2159
2160/**
2161 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2162 * @ring: The Tx ring to configure
2163 *
2164 * Configure the Tx descriptor ring in the HMC context.
2165 **/
2166static int i40e_configure_tx_ring(struct i40e_ring *ring)
2167{
2168 struct i40e_vsi *vsi = ring->vsi;
2169 u16 pf_q = vsi->base_queue + ring->queue_index;
2170 struct i40e_hw *hw = &vsi->back->hw;
2171 struct i40e_hmc_obj_txq tx_ctx;
2172 i40e_status err = 0;
2173 u32 qtx_ctl = 0;
2174
2175 /* some ATR related tx ring init */
60ea5f83 2176 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2177 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2178 ring->atr_count = 0;
2179 } else {
2180 ring->atr_sample_rate = 0;
2181 }
2182
2183 /* initialize XPS */
2184 if (ring->q_vector && ring->netdev &&
4e3b35b0 2185 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2186 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2187 netif_set_xps_queue(ring->netdev,
2188 &ring->q_vector->affinity_mask,
2189 ring->queue_index);
2190
2191 /* clear the context structure first */
2192 memset(&tx_ctx, 0, sizeof(tx_ctx));
2193
2194 tx_ctx.new_context = 1;
2195 tx_ctx.base = (ring->dma / 128);
2196 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2197 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2198 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2199 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2200 /* FDIR VSI tx ring can still use RS bit and writebacks */
2201 if (vsi->type != I40E_VSI_FDIR)
2202 tx_ctx.head_wb_ena = 1;
2203 tx_ctx.head_wb_addr = ring->dma +
2204 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2205
2206 /* As part of VSI creation/update, FW allocates certain
2207 * Tx arbitration queue sets for each TC enabled for
2208 * the VSI. The FW returns the handles to these queue
2209 * sets as part of the response buffer to Add VSI,
2210 * Update VSI, etc. AQ commands. It is expected that
2211 * these queue set handles be associated with the Tx
2212 * queues by the driver as part of the TX queue context
2213 * initialization. This has to be done regardless of
2214 * DCB as by default everything is mapped to TC0.
2215 */
2216 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2217 tx_ctx.rdylist_act = 0;
2218
2219 /* clear the context in the HMC */
2220 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2221 if (err) {
2222 dev_info(&vsi->back->pdev->dev,
2223 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2224 ring->queue_index, pf_q, err);
2225 return -ENOMEM;
2226 }
2227
2228 /* set the context in the HMC */
2229 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2230 if (err) {
2231 dev_info(&vsi->back->pdev->dev,
2232 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2233 ring->queue_index, pf_q, err);
2234 return -ENOMEM;
2235 }
2236
2237 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2238 if (vsi->type == I40E_VSI_VMDQ2)
2239 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2240 else
2241 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2242 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2243 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2244 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2245 i40e_flush(hw);
2246
2247 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2248
2249 /* cache tail off for easier writes later */
2250 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2251
2252 return 0;
2253}
2254
2255/**
2256 * i40e_configure_rx_ring - Configure a receive ring context
2257 * @ring: The Rx ring to configure
2258 *
2259 * Configure the Rx descriptor ring in the HMC context.
2260 **/
2261static int i40e_configure_rx_ring(struct i40e_ring *ring)
2262{
2263 struct i40e_vsi *vsi = ring->vsi;
2264 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2265 u16 pf_q = vsi->base_queue + ring->queue_index;
2266 struct i40e_hw *hw = &vsi->back->hw;
2267 struct i40e_hmc_obj_rxq rx_ctx;
2268 i40e_status err = 0;
2269
2270 ring->state = 0;
2271
2272 /* clear the context structure first */
2273 memset(&rx_ctx, 0, sizeof(rx_ctx));
2274
2275 ring->rx_buf_len = vsi->rx_buf_len;
2276 ring->rx_hdr_len = vsi->rx_hdr_len;
2277
2278 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2279 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2280
2281 rx_ctx.base = (ring->dma / 128);
2282 rx_ctx.qlen = ring->count;
2283
2284 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2285 set_ring_16byte_desc_enabled(ring);
2286 rx_ctx.dsize = 0;
2287 } else {
2288 rx_ctx.dsize = 1;
2289 }
2290
2291 rx_ctx.dtype = vsi->dtype;
2292 if (vsi->dtype) {
2293 set_ring_ps_enabled(ring);
2294 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2295 I40E_RX_SPLIT_IP |
2296 I40E_RX_SPLIT_TCP_UDP |
2297 I40E_RX_SPLIT_SCTP;
2298 } else {
2299 rx_ctx.hsplit_0 = 0;
2300 }
2301
2302 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2303 (chain_len * ring->rx_buf_len));
2304 rx_ctx.tphrdesc_ena = 1;
2305 rx_ctx.tphwdesc_ena = 1;
2306 rx_ctx.tphdata_ena = 1;
2307 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2308 if (hw->revision_id == 0)
2309 rx_ctx.lrxqthresh = 0;
2310 else
2311 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2312 rx_ctx.crcstrip = 1;
2313 rx_ctx.l2tsel = 1;
2314 rx_ctx.showiv = 1;
acb3676b
CS		 2315 /* set the prefena field to 1 because the manual says to */
2316 rx_ctx.prefena = 1;
41c445ff
JB		 2317
2318 /* clear the context in the HMC */
2319 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2320 if (err) {
2321 dev_info(&vsi->back->pdev->dev,
2322 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2323 ring->queue_index, pf_q, err);
2324 return -ENOMEM;
2325 }
2326
2327 /* set the context in the HMC */
2328 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2329 if (err) {
2330 dev_info(&vsi->back->pdev->dev,
2331 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2332 ring->queue_index, pf_q, err);
2333 return -ENOMEM;
2334 }
2335
2336 /* cache tail for quicker writes, and clear the reg before use */
2337 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2338 writel(0, ring->tail);
2339
2340 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2341
2342 return 0;
2343}
2344
2345/**
2346 * i40e_vsi_configure_tx - Configure the VSI for Tx
2347 * @vsi: VSI structure describing this set of rings and resources
2348 *
2349 * Configure the Tx VSI for operation.
2350 **/
2351static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2352{
2353 int err = 0;
2354 u16 i;
2355
9f65e15b
AD		 2356 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2357 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2358
2359 return err;
2360}
2361
2362/**
2363 * i40e_vsi_configure_rx - Configure the VSI for Rx
2364 * @vsi: the VSI being configured
2365 *
2366 * Configure the Rx VSI for operation.
2367 **/
2368static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2369{
2370 int err = 0;
2371 u16 i;
2372
2373 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2374 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2375 + ETH_FCS_LEN + VLAN_HLEN;
2376 else
2377 vsi->max_frame = I40E_RXBUFFER_2048;
2378
2379 /* figure out correct receive buffer length */
2380 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2381 I40E_FLAG_RX_PS_ENABLED)) {
2382 case I40E_FLAG_RX_1BUF_ENABLED:
2383 vsi->rx_hdr_len = 0;
2384 vsi->rx_buf_len = vsi->max_frame;
2385 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2386 break;
2387 case I40E_FLAG_RX_PS_ENABLED:
2388 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2389 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2390 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2391 break;
2392 default:
2393 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2394 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2395 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2396 break;
2397 }
2398
2399 /* round up for the chip's needs */
2400 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2401 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2402 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2403 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2404
2405 /* set up individual rings */
2406 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2407 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2408
2409 return err;
2410}
2411
2412/**
2413 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2414 * @vsi: ptr to the VSI
2415 **/
2416static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2417{
2418 u16 qoffset, qcount;
2419 int i, n;
2420
2421 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2422 return;
2423
2424 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2425 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2426 continue;
2427
2428 qoffset = vsi->tc_config.tc_info[n].qoffset;
2429 qcount = vsi->tc_config.tc_info[n].qcount;
2430 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2431 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2432 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2433 rx_ring->dcb_tc = n;
2434 tx_ring->dcb_tc = n;
2435 }
2436 }
2437}
2438
2439/**
2440 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2441 * @vsi: ptr to the VSI
2442 **/
2443static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2444{
2445 if (vsi->netdev)
2446 i40e_set_rx_mode(vsi->netdev);
2447}
2448
17a73f6b
JG		 2449/**
2450 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2451 * @vsi: Pointer to the targeted VSI
2452 *
2453 * This function replays the hlist on the hw where all the SB Flow Director
2454 * filters were saved.
2455 **/
2456static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2457{
2458 struct i40e_fdir_filter *filter;
2459 struct i40e_pf *pf = vsi->back;
2460 struct hlist_node *node;
2461
55a5e60b
ASJ		 2462 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2463 return;
2464
17a73f6b
JG		 2465 hlist_for_each_entry_safe(filter, node,
2466 &pf->fdir_filter_list, fdir_node) {
2467 i40e_add_del_fdir(vsi, filter, true);
2468 }
2469}
2470
41c445ff
JB		 2471/**
2472 * i40e_vsi_configure - Set up the VSI for action
2473 * @vsi: the VSI being configured
2474 **/
2475static int i40e_vsi_configure(struct i40e_vsi *vsi)
2476{
2477 int err;
2478
2479 i40e_set_vsi_rx_mode(vsi);
2480 i40e_restore_vlan(vsi);
2481 i40e_vsi_config_dcb_rings(vsi);
2482 err = i40e_vsi_configure_tx(vsi);
2483 if (!err)
2484 err = i40e_vsi_configure_rx(vsi);
2485
2486 return err;
2487}
2488
2489/**
2490 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2491 * @vsi: the VSI being configured
2492 **/
2493static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2494{
2495 struct i40e_pf *pf = vsi->back;
2496 struct i40e_q_vector *q_vector;
2497 struct i40e_hw *hw = &pf->hw;
2498 u16 vector;
2499 int i, q;
2500 u32 val;
2501 u32 qp;
2502
2503 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2504 * and PFINT_LNKLSTn registers, e.g.:
2505 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2506 */
2507 qp = vsi->base_queue;
2508 vector = vsi->base_vector;
493fb300
AD		 2509 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2510 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2511 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2512 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2513 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2514 q_vector->rx.itr);
2515 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2516 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2517 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2518 q_vector->tx.itr);
2519
2520 /* Linked list for the queuepairs assigned to this vector */
2521 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2522 for (q = 0; q < q_vector->num_ringpairs; q++) {
2523 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2524 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2525 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2526 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2527 (I40E_QUEUE_TYPE_TX
2528 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2529
2530 wr32(hw, I40E_QINT_RQCTL(qp), val);
2531
2532 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2533 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2534 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2535 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2536 (I40E_QUEUE_TYPE_RX
2537 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2538
2539 /* Terminate the linked list */
2540 if (q == (q_vector->num_ringpairs - 1))
2541 val |= (I40E_QUEUE_END_OF_LIST
2542 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2543
2544 wr32(hw, I40E_QINT_TQCTL(qp), val);
2545 qp++;
2546 }
2547 }
2548
2549 i40e_flush(hw);
2550}
2551
2552/**
2553 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2554 * @hw: ptr to the hardware info
2555 **/
2556static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2557{
2558 u32 val;
2559
2560 /* clear things first */
2561 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2562 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2563
2564 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2565 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2566 I40E_PFINT_ICR0_ENA_GRST_MASK |
2567 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2568 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2569 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2570 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2571 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2572 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2573 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2574
2575 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2576
2577 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2578 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2579 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2580
2581 /* OTHER_ITR_IDX = 0 */
2582 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2583}
2584
2585/**
2586 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2587 * @vsi: the VSI being configured
2588 **/
2589static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2590{
493fb300 2591 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2592 struct i40e_pf *pf = vsi->back;
2593 struct i40e_hw *hw = &pf->hw;
2594 u32 val;
2595
2596 /* set the ITR configuration */
2597 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2598 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2599 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2600 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2601 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2602 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2603
2604 i40e_enable_misc_int_causes(hw);
2605
2606 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2607 wr32(hw, I40E_PFINT_LNKLST0, 0);
2608
f29eaa3d 2609 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2610 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2611 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2612 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2613
2614 wr32(hw, I40E_QINT_RQCTL(0), val);
2615
2616 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2617 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2618 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2619
2620 wr32(hw, I40E_QINT_TQCTL(0), val);
2621 i40e_flush(hw);
2622}
2623
2ef28cfb
MW		 2624/**
2625 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2626 * @pf: board private structure
2627 **/
2628void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2629{
2630 struct i40e_hw *hw = &pf->hw;
2631
2632 wr32(hw, I40E_PFINT_DYN_CTL0,
2633 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2634 i40e_flush(hw);
2635}
2636
41c445ff
JB		 2637/**
2638 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2639 * @pf: board private structure
2640 **/
116a57d4 2641void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2642{
2643 struct i40e_hw *hw = &pf->hw;
2644 u32 val;
2645
2646 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2647 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2648 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2649
2650 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2651 i40e_flush(hw);
2652}
2653
2654/**
2655 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2656 * @vsi: pointer to a vsi
2657 * @vector: enable a particular Hw Interrupt vector
2658 **/
2659void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2660{
2661 struct i40e_pf *pf = vsi->back;
2662 struct i40e_hw *hw = &pf->hw;
2663 u32 val;
2664
2665 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2666 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2667 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2668 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2669 /* skip the flush */
41c445ff
JB		 2670}
2671
2672/**
2673 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2674 * @irq: interrupt number
2675 * @data: pointer to a q_vector
2676 **/
2677static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2678{
2679 struct i40e_q_vector *q_vector = data;
2680
cd0b6fa6 2681 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2682 return IRQ_HANDLED;
2683
2684 napi_schedule(&q_vector->napi);
2685
2686 return IRQ_HANDLED;
2687}
2688
41c445ff
JB		 2689/**
2690 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2691 * @vsi: the VSI being configured
2692 * @basename: name for the vector
2693 *
2694 * Allocates MSI-X vectors and requests interrupts from the kernel.
2695 **/
2696static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2697{
2698 int q_vectors = vsi->num_q_vectors;
2699 struct i40e_pf *pf = vsi->back;
2700 int base = vsi->base_vector;
2701 int rx_int_idx = 0;
2702 int tx_int_idx = 0;
2703 int vector, err;
2704
2705 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2706 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2707
cd0b6fa6 2708 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2709 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2710 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2711 tx_int_idx++;
cd0b6fa6 2712 } else if (q_vector->rx.ring) {
41c445ff
JB		 2713 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2714 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2715 } else if (q_vector->tx.ring) {
41c445ff
JB		 2716 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2717 "%s-%s-%d", basename, "tx", tx_int_idx++);
2718 } else {
2719 /* skip this unused q_vector */
2720 continue;
2721 }
2722 err = request_irq(pf->msix_entries[base + vector].vector,
2723 vsi->irq_handler,
2724 0,
2725 q_vector->name,
2726 q_vector);
2727 if (err) {
2728 dev_info(&pf->pdev->dev,
2729 "%s: request_irq failed, error: %d\n",
2730 __func__, err);
2731 goto free_queue_irqs;
2732 }
2733 /* assign the mask for this irq */
2734 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2735 &q_vector->affinity_mask);
2736 }
2737
2738 return 0;
2739
2740free_queue_irqs:
2741 while (vector) {
2742 vector--;
2743 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2744 NULL);
2745 free_irq(pf->msix_entries[base + vector].vector,
2746 &(vsi->q_vectors[vector]));
2747 }
2748 return err;
2749}
2750
2751/**
2752 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2753 * @vsi: the VSI being un-configured
2754 **/
2755static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2756{
2757 struct i40e_pf *pf = vsi->back;
2758 struct i40e_hw *hw = &pf->hw;
2759 int base = vsi->base_vector;
2760 int i;
2761
2762 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2763 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2764 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2765 }
2766
2767 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2768 for (i = vsi->base_vector;
2769 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2770 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2771
2772 i40e_flush(hw);
2773 for (i = 0; i < vsi->num_q_vectors; i++)
2774 synchronize_irq(pf->msix_entries[i + base].vector);
2775 } else {
2776 /* Legacy and MSI mode - this stops all interrupt handling */
2777 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2778 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2779 i40e_flush(hw);
2780 synchronize_irq(pf->pdev->irq);
2781 }
2782}
2783
2784/**
2785 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2786 * @vsi: the VSI being configured
2787 **/
2788static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2789{
2790 struct i40e_pf *pf = vsi->back;
2791 int i;
2792
2793 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2794 for (i = vsi->base_vector;
2795 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2796 i40e_irq_dynamic_enable(vsi, i);
2797 } else {
2798 i40e_irq_dynamic_enable_icr0(pf);
2799 }
2800
1022cb6c 2801 i40e_flush(&pf->hw);
41c445ff
JB		 2802 return 0;
2803}
2804
2805/**
2806 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2807 * @pf: board private structure
2808 **/
2809static void i40e_stop_misc_vector(struct i40e_pf *pf)
2810{
2811 /* Disable ICR 0 */
2812 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2813 i40e_flush(&pf->hw);
2814}
2815
2816/**
2817 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2818 * @irq: interrupt number
2819 * @data: pointer to a q_vector
2820 *
2821 * This is the handler used for all MSI/Legacy interrupts, and deals
2822 * with both queue and non-queue interrupts. This is also used in
2823 * MSIX mode to handle the non-queue interrupts.
2824 **/
2825static irqreturn_t i40e_intr(int irq, void *data)
2826{
2827 struct i40e_pf *pf = (struct i40e_pf *)data;
2828 struct i40e_hw *hw = &pf->hw;
5e823066 2829 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2830 u32 icr0, icr0_remaining;
2831 u32 val, ena_mask;
2832
2833 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2834 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2835
116a57d4
SN		 2836 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2837 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2838 goto enable_intr;
41c445ff 2839
cd92e72f
SN		 2840 /* if interrupt but no bits showing, must be SWINT */
2841 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2842 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2843 pf->sw_int_count++;
2844
41c445ff
JB		 2845 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2846 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2847
2848 /* temporarily disable queue cause for NAPI processing */
2849 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2850 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2851 wr32(hw, I40E_QINT_RQCTL(0), qval);
2852
2853 qval = rd32(hw, I40E_QINT_TQCTL(0));
2854 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2855 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2856
2857 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2858 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2859 }
2860
2861 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2862 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2863 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2864 }
2865
2866 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2867 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2868 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2869 }
2870
2871 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2872 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2873 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2874 }
2875
2876 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2877 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2878 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2879 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2880 val = rd32(hw, I40E_GLGEN_RSTAT);
2881 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2882 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2883 if (val == I40E_RESET_CORER) {
41c445ff 2884 pf->corer_count++;
4eb3f768 2885 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2886 pf->globr_count++;
4eb3f768 2887 } else if (val == I40E_RESET_EMPR) {
41c445ff 2888 pf->empr_count++;
4eb3f768
SN		 2889 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2890 }
41c445ff
JB		 2891 }
2892
9c010ee0
ASJ		 2893 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2894 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2895 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2896 }
2897
beb0dff1
JK		 2898 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2899 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2900
2901 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 2902 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 2903 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 2904 }
beb0dff1
JK		 2905 }
2906
41c445ff
JB		 2907 /* If a critical error is pending we have no choice but to reset the
2908 * device.
2909 * Report and mask out any remaining unexpected interrupts.
2910 */
2911 icr0_remaining = icr0 & ena_mask;
2912 if (icr0_remaining) {
2913 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2914 icr0_remaining);
9c010ee0 2915 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2916 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2917 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2918 dev_info(&pf->pdev->dev, "device will be reset\n");
2919 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2920 i40e_service_event_schedule(pf);
41c445ff
JB		 2921 }
2922 ena_mask &= ~icr0_remaining;
2923 }
5e823066 2924 ret = IRQ_HANDLED;
41c445ff 2925
5e823066 2926enable_intr:
41c445ff
JB		 2927 /* re-enable interrupt causes */
2928 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2929 if (!test_bit(__I40E_DOWN, &pf->state)) {
2930 i40e_service_event_schedule(pf);
2931 i40e_irq_dynamic_enable_icr0(pf);
2932 }
2933
5e823066 2934 return ret;
41c445ff
JB		 2935}
2936
cbf61325
ASJ		 2937/**
2938 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2939 * @tx_ring: tx ring to clean
2940 * @budget: how many cleans we're allowed
2941 *
2942 * Returns true if there's any budget left (e.g. the clean is finished)
2943 **/
2944static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
2945{
2946 struct i40e_vsi *vsi = tx_ring->vsi;
2947 u16 i = tx_ring->next_to_clean;
2948 struct i40e_tx_buffer *tx_buf;
2949 struct i40e_tx_desc *tx_desc;
2950
2951 tx_buf = &tx_ring->tx_bi[i];
2952 tx_desc = I40E_TX_DESC(tx_ring, i);
2953 i -= tx_ring->count;
2954
2955 do {
2956 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
2957
2958 /* if next_to_watch is not set then there is no work pending */
2959 if (!eop_desc)
2960 break;
2961
2962 /* prevent any other reads prior to eop_desc */
2963 read_barrier_depends();
2964
2965 /* if the descriptor isn't done, no work yet to do */
2966 if (!(eop_desc->cmd_type_offset_bsz &
2967 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
2968 break;
2969
2970 /* clear next_to_watch to prevent false hangs */
2971 tx_buf->next_to_watch = NULL;
2972
2973 /* unmap skb header data */
2974 dma_unmap_single(tx_ring->dev,
2975 dma_unmap_addr(tx_buf, dma),
2976 dma_unmap_len(tx_buf, len),
2977 DMA_TO_DEVICE);
2978
2979 dma_unmap_len_set(tx_buf, len, 0);
2980
2981
2982 /* move to the next desc and buffer to clean */
2983 tx_buf++;
2984 tx_desc++;
2985 i++;
2986 if (unlikely(!i)) {
2987 i -= tx_ring->count;
2988 tx_buf = tx_ring->tx_bi;
2989 tx_desc = I40E_TX_DESC(tx_ring, 0);
2990 }
2991
2992 /* update budget accounting */
2993 budget--;
2994 } while (likely(budget));
2995
2996 i += tx_ring->count;
2997 tx_ring->next_to_clean = i;
2998
2999 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3000 i40e_irq_dynamic_enable(vsi,
3001 tx_ring->q_vector->v_idx + vsi->base_vector);
3002 }
3003 return budget > 0;
3004}
3005
3006/**
3007 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3008 * @irq: interrupt number
3009 * @data: pointer to a q_vector
3010 **/
3011static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3012{
3013 struct i40e_q_vector *q_vector = data;
3014 struct i40e_vsi *vsi;
3015
3016 if (!q_vector->tx.ring)
3017 return IRQ_HANDLED;
3018
3019 vsi = q_vector->tx.ring->vsi;
3020 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3021
3022 return IRQ_HANDLED;
3023}
3024
41c445ff 3025/**
cd0b6fa6 3026 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3027 * @vsi: the VSI being configured
3028 * @v_idx: vector index
cd0b6fa6 3029 * @qp_idx: queue pair index
41c445ff 3030 **/
cd0b6fa6 3031static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3032{
493fb300 3033 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3034 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3035 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3036
3037 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3038 tx_ring->next = q_vector->tx.ring;
3039 q_vector->tx.ring = tx_ring;
41c445ff 3040 q_vector->tx.count++;
cd0b6fa6
AD		 3041
3042 rx_ring->q_vector = q_vector;
3043 rx_ring->next = q_vector->rx.ring;
3044 q_vector->rx.ring = rx_ring;
3045 q_vector->rx.count++;
41c445ff
JB		 3046}
3047
3048/**
3049 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3050 * @vsi: the VSI being configured
3051 *
3052 * This function maps descriptor rings to the queue-specific vectors
3053 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3054 * one vector per queue pair, but on a constrained vector budget, we
3055 * group the queue pairs as "efficiently" as possible.
3056 **/
3057static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3058{
3059 int qp_remaining = vsi->num_queue_pairs;
3060 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3061 int num_ringpairs;
41c445ff
JB		 3062 int v_start = 0;
3063 int qp_idx = 0;
3064
3065 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3066 * group them so there are multiple queues per vector.
3067 */
3068 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3069 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3070
3071 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3072
3073 q_vector->num_ringpairs = num_ringpairs;
3074
3075 q_vector->rx.count = 0;
3076 q_vector->tx.count = 0;
3077 q_vector->rx.ring = NULL;
3078 q_vector->tx.ring = NULL;
3079
3080 while (num_ringpairs--) {
3081 map_vector_to_qp(vsi, v_start, qp_idx);
3082 qp_idx++;
3083 qp_remaining--;
41c445ff
JB		 3084 }
3085 }
3086}
3087
3088/**
3089 * i40e_vsi_request_irq - Request IRQ from the OS
3090 * @vsi: the VSI being configured
3091 * @basename: name for the vector
3092 **/
3093static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3094{
3095 struct i40e_pf *pf = vsi->back;
3096 int err;
3097
3098 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3099 err = i40e_vsi_request_irq_msix(vsi, basename);
3100 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3101 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3102 pf->misc_int_name, pf);
3103 else
3104 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3105 pf->misc_int_name, pf);
3106
3107 if (err)
3108 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3109
3110 return err;
3111}
3112
3113#ifdef CONFIG_NET_POLL_CONTROLLER
3114/**
3115 * i40e_netpoll - A Polling 'interrupt'handler
3116 * @netdev: network interface device structure
3117 *
3118 * This is used by netconsole to send skbs without having to re-enable
3119 * interrupts. It's not called while the normal interrupt routine is executing.
3120 **/
3121static void i40e_netpoll(struct net_device *netdev)
3122{
3123 struct i40e_netdev_priv *np = netdev_priv(netdev);
3124 struct i40e_vsi *vsi = np->vsi;
3125 struct i40e_pf *pf = vsi->back;
3126 int i;
3127
3128 /* if interface is down do nothing */
3129 if (test_bit(__I40E_DOWN, &vsi->state))
3130 return;
3131
3132 pf->flags |= I40E_FLAG_IN_NETPOLL;
3133 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3134 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3135 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3136 } else {
3137 i40e_intr(pf->pdev->irq, netdev);
3138 }
3139 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3140}
3141#endif
3142
3143/**
3144 * i40e_vsi_control_tx - Start or stop a VSI's rings
3145 * @vsi: the VSI being configured
3146 * @enable: start or stop the rings
3147 **/
3148static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3149{
3150 struct i40e_pf *pf = vsi->back;
3151 struct i40e_hw *hw = &pf->hw;
3152 int i, j, pf_q;
3153 u32 tx_reg;
3154
3155 pf_q = vsi->base_queue;
3156 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3157 for (j = 0; j < 50; j++) {
41c445ff 3158 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3159 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3160 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3161 break;
3162 usleep_range(1000, 2000);
3163 }
fda972f6 3164 /* Skip if the queue is already in the requested state */
7c122007 3165 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3166 continue;
41c445ff
JB		 3167
3168 /* turn on/off the queue */
c5c9eb9e
SN		 3169 if (enable) {
3170 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3171 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3172 } else {
41c445ff 3173 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3174 }
41c445ff
JB		 3175
3176 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3177
3178 /* wait for the change to finish */
3179 for (j = 0; j < 10; j++) {
3180 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
7c122007
CS		 3181 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3182 break;
41c445ff
JB		 3183
3184 udelay(10);
3185 }
3186 if (j >= 10) {
3187 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3188 pf_q, (enable ? "en" : "dis"));
3189 return -ETIMEDOUT;
3190 }
3191 }
3192
7134f9ce
JB		 3193 if (hw->revision_id == 0)
3194 mdelay(50);
3195
41c445ff
JB		 3196 return 0;
3197}
3198
3199/**
3200 * i40e_vsi_control_rx - Start or stop a VSI's rings
3201 * @vsi: the VSI being configured
3202 * @enable: start or stop the rings
3203 **/
3204static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3205{
3206 struct i40e_pf *pf = vsi->back;
3207 struct i40e_hw *hw = &pf->hw;
3208 int i, j, pf_q;
3209 u32 rx_reg;
3210
3211 pf_q = vsi->base_queue;
3212 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3213 for (j = 0; j < 50; j++) {
41c445ff 3214 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3215 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3216 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3217 break;
3218 usleep_range(1000, 2000);
3219 }
41c445ff 3220
7c122007
CS		 3221 /* Skip if the queue is already in the requested state */
3222 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3223 continue;
41c445ff
JB		 3224
3225 /* turn on/off the queue */
3226 if (enable)
6c5ef620 3227 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3228 else
6c5ef620 3229 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3230 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3231
3232 /* wait for the change to finish */
3233 for (j = 0; j < 10; j++) {
3234 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3235
7c122007
CS		 3236 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3237 break;
41c445ff
JB		 3238
3239 udelay(10);
3240 }
3241 if (j >= 10) {
3242 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3243 pf_q, (enable ? "en" : "dis"));
3244 return -ETIMEDOUT;
3245 }
3246 }
3247
3248 return 0;
3249}
3250
3251/**
3252 * i40e_vsi_control_rings - Start or stop a VSI's rings
3253 * @vsi: the VSI being configured
3254 * @enable: start or stop the rings
3255 **/
fc18eaa0 3256int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3257{
3b867b28 3258 int ret = 0;
41c445ff
JB		 3259
3260 /* do rx first for enable and last for disable */
3261 if (request) {
3262 ret = i40e_vsi_control_rx(vsi, request);
3263 if (ret)
3264 return ret;
3265 ret = i40e_vsi_control_tx(vsi, request);
3266 } else {
3b867b28
ASJ		 3267 /* Ignore return value, we need to shutdown whatever we can */
3268 i40e_vsi_control_tx(vsi, request);
3269 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3270 }
3271
3272 return ret;
3273}
3274
3275/**
3276 * i40e_vsi_free_irq - Free the irq association with the OS
3277 * @vsi: the VSI being configured
3278 **/
3279static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3280{
3281 struct i40e_pf *pf = vsi->back;
3282 struct i40e_hw *hw = &pf->hw;
3283 int base = vsi->base_vector;
3284 u32 val, qp;
3285 int i;
3286
3287 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3288 if (!vsi->q_vectors)
3289 return;
3290
3291 for (i = 0; i < vsi->num_q_vectors; i++) {
3292 u16 vector = i + base;
3293
3294 /* free only the irqs that were actually requested */
78681b1f
SN		 3295 if (!vsi->q_vectors[i] ||
3296 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3297 continue;
3298
3299 /* clear the affinity_mask in the IRQ descriptor */
3300 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3301 NULL);
3302 free_irq(pf->msix_entries[vector].vector,
493fb300 3303 vsi->q_vectors[i]);
41c445ff
JB		 3304
3305 /* Tear down the interrupt queue link list
3306 *
3307 * We know that they come in pairs and always
3308 * the Rx first, then the Tx. To clear the
3309 * link list, stick the EOL value into the
3310 * next_q field of the registers.
3311 */
3312 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3313 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3314 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3315 val |= I40E_QUEUE_END_OF_LIST
3316 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3317 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3318
3319 while (qp != I40E_QUEUE_END_OF_LIST) {
3320 u32 next;
3321
3322 val = rd32(hw, I40E_QINT_RQCTL(qp));
3323
3324 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3325 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3326 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3327 I40E_QINT_RQCTL_INTEVENT_MASK);
3328
3329 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3330 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3331
3332 wr32(hw, I40E_QINT_RQCTL(qp), val);
3333
3334 val = rd32(hw, I40E_QINT_TQCTL(qp));
3335
3336 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3337 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3338
3339 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3340 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3341 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3342 I40E_QINT_TQCTL_INTEVENT_MASK);
3343
3344 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3345 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3346
3347 wr32(hw, I40E_QINT_TQCTL(qp), val);
3348 qp = next;
3349 }
3350 }
3351 } else {
3352 free_irq(pf->pdev->irq, pf);
3353
3354 val = rd32(hw, I40E_PFINT_LNKLST0);
3355 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3356 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3357 val |= I40E_QUEUE_END_OF_LIST
3358 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3359 wr32(hw, I40E_PFINT_LNKLST0, val);
3360
3361 val = rd32(hw, I40E_QINT_RQCTL(qp));
3362 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3363 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3364 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3365 I40E_QINT_RQCTL_INTEVENT_MASK);
3366
3367 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3368 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3369
3370 wr32(hw, I40E_QINT_RQCTL(qp), val);
3371
3372 val = rd32(hw, I40E_QINT_TQCTL(qp));
3373
3374 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3375 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3376 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3377 I40E_QINT_TQCTL_INTEVENT_MASK);
3378
3379 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3380 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3381
3382 wr32(hw, I40E_QINT_TQCTL(qp), val);
3383 }
3384}
3385
493fb300
AD		 3386/**
3387 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3388 * @vsi: the VSI being configured
3389 * @v_idx: Index of vector to be freed
3390 *
3391 * This function frees the memory allocated to the q_vector. In addition if
3392 * NAPI is enabled it will delete any references to the NAPI struct prior
3393 * to freeing the q_vector.
3394 **/
3395static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3396{
3397 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3398 struct i40e_ring *ring;
493fb300
AD		 3399
3400 if (!q_vector)
3401 return;
3402
3403 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3404 i40e_for_each_ring(ring, q_vector->tx)
3405 ring->q_vector = NULL;
3406
3407 i40e_for_each_ring(ring, q_vector->rx)
3408 ring->q_vector = NULL;
493fb300
AD		 3409
3410 /* only VSI w/ an associated netdev is set up w/ NAPI */
3411 if (vsi->netdev)
3412 netif_napi_del(&q_vector->napi);
3413
3414 vsi->q_vectors[v_idx] = NULL;
3415
3416 kfree_rcu(q_vector, rcu);
3417}
3418
41c445ff
JB		 3419/**
3420 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3421 * @vsi: the VSI being un-configured
3422 *
3423 * This frees the memory allocated to the q_vectors and
3424 * deletes references to the NAPI struct.
3425 **/
3426static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3427{
3428 int v_idx;
3429
493fb300
AD		 3430 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3431 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3432}
3433
3434/**
3435 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3436 * @pf: board private structure
3437 **/
3438static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3439{
3440 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3441 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3442 pci_disable_msix(pf->pdev);
3443 kfree(pf->msix_entries);
3444 pf->msix_entries = NULL;
3445 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3446 pci_disable_msi(pf->pdev);
3447 }
3448 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3449}
3450
3451/**
3452 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3453 * @pf: board private structure
3454 *
3455 * We go through and clear interrupt specific resources and reset the structure
3456 * to pre-load conditions
3457 **/
3458static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3459{
3460 int i;
3461
3462 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3463 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3464 if (pf->vsi[i])
3465 i40e_vsi_free_q_vectors(pf->vsi[i]);
3466 i40e_reset_interrupt_capability(pf);
3467}
3468
3469/**
3470 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3471 * @vsi: the VSI being configured
3472 **/
3473static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3474{
3475 int q_idx;
3476
3477 if (!vsi->netdev)
3478 return;
3479
3480 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3481 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3482}
3483
3484/**
3485 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3486 * @vsi: the VSI being configured
3487 **/
3488static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3489{
3490 int q_idx;
3491
3492 if (!vsi->netdev)
3493 return;
3494
3495 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3496 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3497}
3498
90ef8d47
SN		 3499/**
3500 * i40e_vsi_close - Shut down a VSI
3501 * @vsi: the vsi to be quelled
3502 **/
3503static void i40e_vsi_close(struct i40e_vsi *vsi)
3504{
3505 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3506 i40e_down(vsi);
3507 i40e_vsi_free_irq(vsi);
3508 i40e_vsi_free_tx_resources(vsi);
3509 i40e_vsi_free_rx_resources(vsi);
3510}
3511
41c445ff
JB		 3512/**
3513 * i40e_quiesce_vsi - Pause a given VSI
3514 * @vsi: the VSI being paused
3515 **/
3516static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3517{
3518 if (test_bit(__I40E_DOWN, &vsi->state))
3519 return;
3520
3521 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3522 if (vsi->netdev && netif_running(vsi->netdev)) {
3523 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3524 } else {
90ef8d47 3525 i40e_vsi_close(vsi);
41c445ff
JB		 3526 }
3527}
3528
3529/**
3530 * i40e_unquiesce_vsi - Resume a given VSI
3531 * @vsi: the VSI being resumed
3532 **/
3533static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3534{
3535 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3536 return;
3537
3538 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3539 if (vsi->netdev && netif_running(vsi->netdev))
3540 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3541 else
8276f757 3542 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3543}
3544
3545/**
3546 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3547 * @pf: the PF
3548 **/
3549static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3550{
3551 int v;
3552
3553 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3554 if (pf->vsi[v])
3555 i40e_quiesce_vsi(pf->vsi[v]);
3556 }
3557}
3558
3559/**
3560 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3561 * @pf: the PF
3562 **/
3563static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3564{
3565 int v;
3566
3567 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3568 if (pf->vsi[v])
3569 i40e_unquiesce_vsi(pf->vsi[v]);
3570 }
3571}
3572
3573/**
3574 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3575 * @dcbcfg: the corresponding DCBx configuration structure
3576 *
3577 * Return the number of TCs from given DCBx configuration
3578 **/
3579static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3580{
078b5876
JB		 3581 u8 num_tc = 0;
3582 int i;
41c445ff
JB		 3583
3584 /* Scan the ETS Config Priority Table to find
3585 * traffic class enabled for a given priority
3586 * and use the traffic class index to get the
3587 * number of traffic classes enabled
3588 */
3589 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3590 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3591 num_tc = dcbcfg->etscfg.prioritytable[i];
3592 }
3593
3594 /* Traffic class index starts from zero so
3595 * increment to return the actual count
3596 */
078b5876 3597 return num_tc + 1;
41c445ff
JB		 3598}
3599
3600/**
3601 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3602 * @dcbcfg: the corresponding DCBx configuration structure
3603 *
3604 * Query the current DCB configuration and return the number of
3605 * traffic classes enabled from the given DCBX config
3606 **/
3607static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3608{
3609 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3610 u8 enabled_tc = 1;
3611 u8 i;
3612
3613 for (i = 0; i < num_tc; i++)
3614 enabled_tc |= 1 << i;
3615
3616 return enabled_tc;
3617}
3618
3619/**
3620 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3621 * @pf: PF being queried
3622 *
3623 * Return number of traffic classes enabled for the given PF
3624 **/
3625static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3626{
3627 struct i40e_hw *hw = &pf->hw;
3628 u8 i, enabled_tc;
3629 u8 num_tc = 0;
3630 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3631
3632 /* If DCB is not enabled then always in single TC */
3633 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3634 return 1;
3635
3636 /* MFP mode return count of enabled TCs for this PF */
3637 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3638 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3639 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3640 if (enabled_tc & (1 << i))
3641 num_tc++;
3642 }
3643 return num_tc;
3644 }
3645
3646 /* SFP mode will be enabled for all TCs on port */
3647 return i40e_dcb_get_num_tc(dcbcfg);
3648}
3649
3650/**
3651 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3652 * @pf: PF being queried
3653 *
3654 * Return a bitmap for first enabled traffic class for this PF.
3655 **/
3656static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3657{
3658 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3659 u8 i = 0;
3660
3661 if (!enabled_tc)
3662 return 0x1; /* TC0 */
3663
3664 /* Find the first enabled TC */
3665 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3666 if (enabled_tc & (1 << i))
3667 break;
3668 }
3669
3670 return 1 << i;
3671}
3672
3673/**
3674 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3675 * @pf: PF being queried
3676 *
3677 * Return a bitmap for enabled traffic classes for this PF.
3678 **/
3679static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3680{
3681 /* If DCB is not enabled for this PF then just return default TC */
3682 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3683 return i40e_pf_get_default_tc(pf);
3684
3685 /* MFP mode will have enabled TCs set by FW */
3686 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3687 return pf->hw.func_caps.enabled_tcmap;
3688
3689 /* SFP mode we want PF to be enabled for all TCs */
3690 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3691}
3692
3693/**
3694 * i40e_vsi_get_bw_info - Query VSI BW Information
3695 * @vsi: the VSI being queried
3696 *
3697 * Returns 0 on success, negative value on failure
3698 **/
3699static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3700{
3701 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3702 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3703 struct i40e_pf *pf = vsi->back;
3704 struct i40e_hw *hw = &pf->hw;
dcae29be 3705 i40e_status aq_ret;
41c445ff 3706 u32 tc_bw_max;
41c445ff
JB		 3707 int i;
3708
3709 /* Get the VSI level BW configuration */
dcae29be
JB		 3710 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3711 if (aq_ret) {
41c445ff
JB		 3712 dev_info(&pf->pdev->dev,
3713 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3714 aq_ret, pf->hw.aq.asq_last_status);
3715 return -EINVAL;
41c445ff
JB		 3716 }
3717
3718 /* Get the VSI level BW configuration per TC */
dcae29be 3719 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3720 NULL);
dcae29be 3721 if (aq_ret) {
41c445ff
JB		 3722 dev_info(&pf->pdev->dev,
3723 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3724 aq_ret, pf->hw.aq.asq_last_status);
3725 return -EINVAL;
41c445ff
JB		 3726 }
3727
3728 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3729 dev_info(&pf->pdev->dev,
3730 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3731 bw_config.tc_valid_bits,
3732 bw_ets_config.tc_valid_bits);
3733 /* Still continuing */
3734 }
3735
3736 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3737 vsi->bw_max_quanta = bw_config.max_bw;
3738 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3739 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3740 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3741 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3742 vsi->bw_ets_limit_credits[i] =
3743 le16_to_cpu(bw_ets_config.credits[i]);
3744 /* 3 bits out of 4 for each TC */
3745 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3746 }
078b5876 3747
dcae29be 3748 return 0;
41c445ff
JB		 3749}
3750
3751/**
3752 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3753 * @vsi: the VSI being configured
3754 * @enabled_tc: TC bitmap
3755 * @bw_credits: BW shared credits per TC
3756 *
3757 * Returns 0 on success, negative value on failure
3758 **/
dcae29be 3759static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3760 u8 *bw_share)
3761{
3762 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3763 i40e_status aq_ret;
3764 int i;
41c445ff
JB		 3765
3766 bw_data.tc_valid_bits = enabled_tc;
3767 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3768 bw_data.tc_bw_credits[i] = bw_share[i];
3769
dcae29be
JB		 3770 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3771 NULL);
3772 if (aq_ret) {
41c445ff 3773 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3774 "AQ command Config VSI BW allocation per TC failed = %d\n",
3775 vsi->back->hw.aq.asq_last_status);
dcae29be 3776 return -EINVAL;
41c445ff
JB		 3777 }
3778
3779 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3780 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3781
dcae29be 3782 return 0;
41c445ff
JB		 3783}
3784
3785/**
3786 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3787 * @vsi: the VSI being configured
3788 * @enabled_tc: TC map to be enabled
3789 *
3790 **/
3791static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3792{
3793 struct net_device *netdev = vsi->netdev;
3794 struct i40e_pf *pf = vsi->back;
3795 struct i40e_hw *hw = &pf->hw;
3796 u8 netdev_tc = 0;
3797 int i;
3798 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3799
3800 if (!netdev)
3801 return;
3802
3803 if (!enabled_tc) {
3804 netdev_reset_tc(netdev);
3805 return;
3806 }
3807
3808 /* Set up actual enabled TCs on the VSI */
3809 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3810 return;
3811
3812 /* set per TC queues for the VSI */
3813 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3814 /* Only set TC queues for enabled tcs
3815 *
3816 * e.g. For a VSI that has TC0 and TC3 enabled the
3817 * enabled_tc bitmap would be 0x00001001; the driver
3818 * will set the numtc for netdev as 2 that will be
3819 * referenced by the netdev layer as TC 0 and 1.
3820 */
3821 if (vsi->tc_config.enabled_tc & (1 << i))
3822 netdev_set_tc_queue(netdev,
3823 vsi->tc_config.tc_info[i].netdev_tc,
3824 vsi->tc_config.tc_info[i].qcount,
3825 vsi->tc_config.tc_info[i].qoffset);
3826 }
3827
3828 /* Assign UP2TC map for the VSI */
3829 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3830 /* Get the actual TC# for the UP */
3831 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3832 /* Get the mapped netdev TC# for the UP */
3833 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3834 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3835 }
3836}
3837
3838/**
3839 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3840 * @vsi: the VSI being configured
3841 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3842 **/
3843static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3844 struct i40e_vsi_context *ctxt)
3845{
3846 /* copy just the sections touched not the entire info
3847 * since not all sections are valid as returned by
3848 * update vsi params
3849 */
3850 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3851 memcpy(&vsi->info.queue_mapping,
3852 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3853 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3854 sizeof(vsi->info.tc_mapping));
3855}
3856
3857/**
3858 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3859 * @vsi: VSI to be configured
3860 * @enabled_tc: TC bitmap
3861 *
3862 * This configures a particular VSI for TCs that are mapped to the
3863 * given TC bitmap. It uses default bandwidth share for TCs across
3864 * VSIs to configure TC for a particular VSI.
3865 *
3866 * NOTE:
3867 * It is expected that the VSI queues have been quisced before calling
3868 * this function.
3869 **/
3870static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3871{
3872 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3873 struct i40e_vsi_context ctxt;
3874 int ret = 0;
3875 int i;
3876
3877 /* Check if enabled_tc is same as existing or new TCs */
3878 if (vsi->tc_config.enabled_tc == enabled_tc)
3879 return ret;
3880
3881 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3882 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3883 if (enabled_tc & (1 << i))
3884 bw_share[i] = 1;
3885 }
3886
3887 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3888 if (ret) {
3889 dev_info(&vsi->back->pdev->dev,
3890 "Failed configuring TC map %d for VSI %d\n",
3891 enabled_tc, vsi->seid);
3892 goto out;
3893 }
3894
3895 /* Update Queue Pairs Mapping for currently enabled UPs */
3896 ctxt.seid = vsi->seid;
3897 ctxt.pf_num = vsi->back->hw.pf_id;
3898 ctxt.vf_num = 0;
3899 ctxt.uplink_seid = vsi->uplink_seid;
3900 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3901 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3902
3903 /* Update the VSI after updating the VSI queue-mapping information */
3904 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3905 if (ret) {
3906 dev_info(&vsi->back->pdev->dev,
3907 "update vsi failed, aq_err=%d\n",
3908 vsi->back->hw.aq.asq_last_status);
3909 goto out;
3910 }
3911 /* update the local VSI info with updated queue map */
3912 i40e_vsi_update_queue_map(vsi, &ctxt);
3913 vsi->info.valid_sections = 0;
3914
3915 /* Update current VSI BW information */
3916 ret = i40e_vsi_get_bw_info(vsi);
3917 if (ret) {
3918 dev_info(&vsi->back->pdev->dev,
3919 "Failed updating vsi bw info, aq_err=%d\n",
3920 vsi->back->hw.aq.asq_last_status);
3921 goto out;
3922 }
3923
3924 /* Update the netdev TC setup */
3925 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3926out:
3927 return ret;
3928}
3929
4e3b35b0
NP		 3930/**
3931 * i40e_veb_config_tc - Configure TCs for given VEB
3932 * @veb: given VEB
3933 * @enabled_tc: TC bitmap
3934 *
3935 * Configures given TC bitmap for VEB (switching) element
3936 **/
3937int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
3938{
3939 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
3940 struct i40e_pf *pf = veb->pf;
3941 int ret = 0;
3942 int i;
3943
3944 /* No TCs or already enabled TCs just return */
3945 if (!enabled_tc || veb->enabled_tc == enabled_tc)
3946 return ret;
3947
3948 bw_data.tc_valid_bits = enabled_tc;
3949 /* bw_data.absolute_credits is not set (relative) */
3950
3951 /* Enable ETS TCs with equal BW Share for now */
3952 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3953 if (enabled_tc & (1 << i))
3954 bw_data.tc_bw_share_credits[i] = 1;
3955 }
3956
3957 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
3958 &bw_data, NULL);
3959 if (ret) {
3960 dev_info(&pf->pdev->dev,
3961 "veb bw config failed, aq_err=%d\n",
3962 pf->hw.aq.asq_last_status);
3963 goto out;
3964 }
3965
3966 /* Update the BW information */
3967 ret = i40e_veb_get_bw_info(veb);
3968 if (ret) {
3969 dev_info(&pf->pdev->dev,
3970 "Failed getting veb bw config, aq_err=%d\n",
3971 pf->hw.aq.asq_last_status);
3972 }
3973
3974out:
3975 return ret;
3976}
3977
3978#ifdef CONFIG_I40E_DCB
3979/**
3980 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
3981 * @pf: PF struct
3982 *
3983 * Reconfigure VEB/VSIs on a given PF; it is assumed that
3984 * the caller would've quiesce all the VSIs before calling
3985 * this function
3986 **/
3987static void i40e_dcb_reconfigure(struct i40e_pf *pf)
3988{
3989 u8 tc_map = 0;
3990 int ret;
3991 u8 v;
3992
3993 /* Enable the TCs available on PF to all VEBs */
3994 tc_map = i40e_pf_get_tc_map(pf);
3995 for (v = 0; v < I40E_MAX_VEB; v++) {
3996 if (!pf->veb[v])
3997 continue;
3998 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
3999 if (ret) {
4000 dev_info(&pf->pdev->dev,
4001 "Failed configuring TC for VEB seid=%d\n",
4002 pf->veb[v]->seid);
4003 /* Will try to configure as many components */
4004 }
4005 }
4006
4007 /* Update each VSI */
4008 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4009 if (!pf->vsi[v])
4010 continue;
4011
4012 /* - Enable all TCs for the LAN VSI
4013 * - For all others keep them at TC0 for now
4014 */
4015 if (v == pf->lan_vsi)
4016 tc_map = i40e_pf_get_tc_map(pf);
4017 else
4018 tc_map = i40e_pf_get_default_tc(pf);
4019
4020 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4021 if (ret) {
4022 dev_info(&pf->pdev->dev,
4023 "Failed configuring TC for VSI seid=%d\n",
4024 pf->vsi[v]->seid);
4025 /* Will try to configure as many components */
4026 } else {
0672a091
NP		 4027 /* Re-configure VSI vectors based on updated TC map */
4028 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4029 if (pf->vsi[v]->netdev)
4030 i40e_dcbnl_set_all(pf->vsi[v]);
4031 }
4032 }
4033}
4034
4035/**
4036 * i40e_init_pf_dcb - Initialize DCB configuration
4037 * @pf: PF being configured
4038 *
4039 * Query the current DCB configuration and cache it
4040 * in the hardware structure
4041 **/
4042static int i40e_init_pf_dcb(struct i40e_pf *pf)
4043{
4044 struct i40e_hw *hw = &pf->hw;
4045 int err = 0;
4046
4047 if (pf->hw.func_caps.npar_enable)
4048 goto out;
4049
4050 /* Get the initial DCB configuration */
4051 err = i40e_init_dcb(hw);
4052 if (!err) {
4053 /* Device/Function is not DCBX capable */
4054 if ((!hw->func_caps.dcb) ||
4055 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4056 dev_info(&pf->pdev->dev,
4057 "DCBX offload is not supported or is disabled for this PF.\n");
4058
4059 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4060 goto out;
4061
4062 } else {
4063 /* When status is not DISABLED then DCBX in FW */
4064 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4065 DCB_CAP_DCBX_VER_IEEE;
4066 pf->flags |= I40E_FLAG_DCB_ENABLED;
4067 }
014269ff
NP		 4068 } else {
4069 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4070 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4071 }
4072
4073out:
4074 return err;
4075}
4076#endif /* CONFIG_I40E_DCB */
4077
41c445ff
JB		 4078/**
4079 * i40e_up_complete - Finish the last steps of bringing up a connection
4080 * @vsi: the VSI being configured
4081 **/
4082static int i40e_up_complete(struct i40e_vsi *vsi)
4083{
4084 struct i40e_pf *pf = vsi->back;
4085 int err;
4086
4087 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4088 i40e_vsi_configure_msix(vsi);
4089 else
4090 i40e_configure_msi_and_legacy(vsi);
4091
4092 /* start rings */
4093 err = i40e_vsi_control_rings(vsi, true);
4094 if (err)
4095 return err;
4096
4097 clear_bit(__I40E_DOWN, &vsi->state);
4098 i40e_napi_enable_all(vsi);
4099 i40e_vsi_enable_irq(vsi);
4100
4101 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4102 (vsi->netdev)) {
6d779b41 4103 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 4104 netif_tx_start_all_queues(vsi->netdev);
4105 netif_carrier_on(vsi->netdev);
6d779b41
AS		 4106 } else if (vsi->netdev) {
4107 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff 4108 }
ca64fa4e
ASJ		 4109
4110 /* replay FDIR SB filters */
4111 if (vsi->type == I40E_VSI_FDIR)
4112 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4113 i40e_service_event_schedule(pf);
4114
4115 return 0;
4116}
4117
4118/**
4119 * i40e_vsi_reinit_locked - Reset the VSI
4120 * @vsi: the VSI being configured
4121 *
4122 * Rebuild the ring structs after some configuration
4123 * has changed, e.g. MTU size.
4124 **/
4125static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4126{
4127 struct i40e_pf *pf = vsi->back;
4128
4129 WARN_ON(in_interrupt());
4130 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4131 usleep_range(1000, 2000);
4132 i40e_down(vsi);
4133
4134 /* Give a VF some time to respond to the reset. The
4135 * two second wait is based upon the watchdog cycle in
4136 * the VF driver.
4137 */
4138 if (vsi->type == I40E_VSI_SRIOV)
4139 msleep(2000);
4140 i40e_up(vsi);
4141 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4142}
4143
4144/**
4145 * i40e_up - Bring the connection back up after being down
4146 * @vsi: the VSI being configured
4147 **/
4148int i40e_up(struct i40e_vsi *vsi)
4149{
4150 int err;
4151
4152 err = i40e_vsi_configure(vsi);
4153 if (!err)
4154 err = i40e_up_complete(vsi);
4155
4156 return err;
4157}
4158
4159/**
4160 * i40e_down - Shutdown the connection processing
4161 * @vsi: the VSI being stopped
4162 **/
4163void i40e_down(struct i40e_vsi *vsi)
4164{
4165 int i;
4166
4167 /* It is assumed that the caller of this function
4168 * sets the vsi->state __I40E_DOWN bit.
4169 */
4170 if (vsi->netdev) {
4171 netif_carrier_off(vsi->netdev);
4172 netif_tx_disable(vsi->netdev);
4173 }
4174 i40e_vsi_disable_irq(vsi);
4175 i40e_vsi_control_rings(vsi, false);
4176 i40e_napi_disable_all(vsi);
4177
4178 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4179 i40e_clean_tx_ring(vsi->tx_rings[i]);
4180 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4181 }
4182}
4183
4184/**
4185 * i40e_setup_tc - configure multiple traffic classes
4186 * @netdev: net device to configure
4187 * @tc: number of traffic classes to enable
4188 **/
4189static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4190{
4191 struct i40e_netdev_priv *np = netdev_priv(netdev);
4192 struct i40e_vsi *vsi = np->vsi;
4193 struct i40e_pf *pf = vsi->back;
4194 u8 enabled_tc = 0;
4195 int ret = -EINVAL;
4196 int i;
4197
4198 /* Check if DCB enabled to continue */
4199 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4200 netdev_info(netdev, "DCB is not enabled for adapter\n");
4201 goto exit;
4202 }
4203
4204 /* Check if MFP enabled */
4205 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4206 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4207 goto exit;
4208 }
4209
4210 /* Check whether tc count is within enabled limit */
4211 if (tc > i40e_pf_get_num_tc(pf)) {
4212 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4213 goto exit;
4214 }
4215
4216 /* Generate TC map for number of tc requested */
4217 for (i = 0; i < tc; i++)
4218 enabled_tc |= (1 << i);
4219
4220 /* Requesting same TC configuration as already enabled */
4221 if (enabled_tc == vsi->tc_config.enabled_tc)
4222 return 0;
4223
4224 /* Quiesce VSI queues */
4225 i40e_quiesce_vsi(vsi);
4226
4227 /* Configure VSI for enabled TCs */
4228 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4229 if (ret) {
4230 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4231 vsi->seid);
4232 goto exit;
4233 }
4234
4235 /* Unquiesce VSI */
4236 i40e_unquiesce_vsi(vsi);
4237
4238exit:
4239 return ret;
4240}
4241
4242/**
4243 * i40e_open - Called when a network interface is made active
4244 * @netdev: network interface device structure
4245 *
4246 * The open entry point is called when a network interface is made
4247 * active by the system (IFF_UP). At this point all resources needed
4248 * for transmit and receive operations are allocated, the interrupt
4249 * handler is registered with the OS, the netdev watchdog subtask is
4250 * enabled, and the stack is notified that the interface is ready.
4251 *
4252 * Returns 0 on success, negative value on failure
4253 **/
4254static int i40e_open(struct net_device *netdev)
4255{
4256 struct i40e_netdev_priv *np = netdev_priv(netdev);
4257 struct i40e_vsi *vsi = np->vsi;
4258 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4259 int err;
4260
4eb3f768
SN		 4261 /* disallow open during test or if eeprom is broken */
4262 if (test_bit(__I40E_TESTING, &pf->state) ||
4263 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4264 return -EBUSY;
4265
4266 netif_carrier_off(netdev);
4267
6c167f58
EK		 4268 err = i40e_vsi_open(vsi);
4269 if (err)
4270 return err;
4271
059dab69
JB		 4272 /* configure global TSO hardware offload settings */
4273 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4274 TCP_FLAG_FIN) >> 16);
4275 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4276 TCP_FLAG_FIN |
4277 TCP_FLAG_CWR) >> 16);
4278 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4279
6c167f58
EK		 4280#ifdef CONFIG_I40E_VXLAN
4281 vxlan_get_rx_port(netdev);
4282#endif
4283
4284 return 0;
4285}
4286
4287/**
4288 * i40e_vsi_open -
4289 * @vsi: the VSI to open
4290 *
4291 * Finish initialization of the VSI.
4292 *
4293 * Returns 0 on success, negative value on failure
4294 **/
4295int i40e_vsi_open(struct i40e_vsi *vsi)
4296{
4297 struct i40e_pf *pf = vsi->back;
4298 char int_name[IFNAMSIZ];
4299 int err;
4300
41c445ff
JB		 4301 /* allocate descriptors */
4302 err = i40e_vsi_setup_tx_resources(vsi);
4303 if (err)
4304 goto err_setup_tx;
4305 err = i40e_vsi_setup_rx_resources(vsi);
4306 if (err)
4307 goto err_setup_rx;
4308
4309 err = i40e_vsi_configure(vsi);
4310 if (err)
4311 goto err_setup_rx;
4312
c22e3c6c
SN		 4313 if (vsi->netdev) {
4314 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4315 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4316 err = i40e_vsi_request_irq(vsi, int_name);
4317 if (err)
4318 goto err_setup_rx;
4319
4320 /* Notify the stack of the actual queue counts. */
4321 err = netif_set_real_num_tx_queues(vsi->netdev,
4322 vsi->num_queue_pairs);
4323 if (err)
4324 goto err_set_queues;
4325
4326 err = netif_set_real_num_rx_queues(vsi->netdev,
4327 vsi->num_queue_pairs);
4328 if (err)
4329 goto err_set_queues;
8a9eb7d3
SN		 4330
4331 } else if (vsi->type == I40E_VSI_FDIR) {
4332 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4333 dev_driver_string(&pf->pdev->dev));
4334 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4335 } else {
6c167f58
EK		 4336 err = EINVAL;
4337 goto err_setup_rx;
4338 }
25946ddb 4339
41c445ff
JB		 4340 err = i40e_up_complete(vsi);
4341 if (err)
4342 goto err_up_complete;
4343
41c445ff
JB		 4344 return 0;
4345
4346err_up_complete:
4347 i40e_down(vsi);
25946ddb 4348err_set_queues:
41c445ff
JB		 4349 i40e_vsi_free_irq(vsi);
4350err_setup_rx:
4351 i40e_vsi_free_rx_resources(vsi);
4352err_setup_tx:
4353 i40e_vsi_free_tx_resources(vsi);
4354 if (vsi == pf->vsi[pf->lan_vsi])
4355 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4356
4357 return err;
4358}
4359
17a73f6b
JG		 4360/**
4361 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4362 * @pf: Pointer to pf
4363 *
4364 * This function destroys the hlist where all the Flow Director
4365 * filters were saved.
4366 **/
4367static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4368{
4369 struct i40e_fdir_filter *filter;
4370 struct hlist_node *node2;
4371
4372 hlist_for_each_entry_safe(filter, node2,
4373 &pf->fdir_filter_list, fdir_node) {
4374 hlist_del(&filter->fdir_node);
4375 kfree(filter);
4376 }
4377 pf->fdir_pf_active_filters = 0;
4378}
4379
41c445ff
JB		 4380/**
4381 * i40e_close - Disables a network interface
4382 * @netdev: network interface device structure
4383 *
4384 * The close entry point is called when an interface is de-activated
4385 * by the OS. The hardware is still under the driver's control, but
4386 * this netdev interface is disabled.
4387 *
4388 * Returns 0, this is not allowed to fail
4389 **/
4390static int i40e_close(struct net_device *netdev)
4391{
4392 struct i40e_netdev_priv *np = netdev_priv(netdev);
4393 struct i40e_vsi *vsi = np->vsi;
4394
90ef8d47 4395 i40e_vsi_close(vsi);
41c445ff
JB		 4396
4397 return 0;
4398}
4399
4400/**
4401 * i40e_do_reset - Start a PF or Core Reset sequence
4402 * @pf: board private structure
4403 * @reset_flags: which reset is requested
4404 *
4405 * The essential difference in resets is that the PF Reset
4406 * doesn't clear the packet buffers, doesn't reset the PE
4407 * firmware, and doesn't bother the other PFs on the chip.
4408 **/
4409void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4410{
4411 u32 val;
4412
4413 WARN_ON(in_interrupt());
4414
4415 /* do the biggest reset indicated */
4416 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4417
4418 /* Request a Global Reset
4419 *
4420 * This will start the chip's countdown to the actual full
4421 * chip reset event, and a warning interrupt to be sent
4422 * to all PFs, including the requestor. Our handler
4423 * for the warning interrupt will deal with the shutdown
4424 * and recovery of the switch setup.
4425 */
69bfb110 4426 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4427 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4428 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4429 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4430
4431 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4432
4433 /* Request a Core Reset
4434 *
4435 * Same as Global Reset, except does *not* include the MAC/PHY
4436 */
69bfb110 4437 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4438 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4439 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4440 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4441 i40e_flush(&pf->hw);
4442
7823fe34
SN		 4443 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4444
4445 /* Request a Firmware Reset
4446 *
4447 * Same as Global reset, plus restarting the
4448 * embedded firmware engine.
4449 */
4450 /* enable EMP Reset */
4451 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4452 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4453 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4454
4455 /* force the reset */
4456 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4457 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4458 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4459 i40e_flush(&pf->hw);
4460
41c445ff
JB		 4461 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4462
4463 /* Request a PF Reset
4464 *
4465 * Resets only the PF-specific registers
4466 *
4467 * This goes directly to the tear-down and rebuild of
4468 * the switch, since we need to do all the recovery as
4469 * for the Core Reset.
4470 */
69bfb110 4471 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4472 i40e_handle_reset_warning(pf);
4473
4474 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4475 int v;
4476
4477 /* Find the VSI(s) that requested a re-init */
4478 dev_info(&pf->pdev->dev,
4479 "VSI reinit requested\n");
4480 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4481 struct i40e_vsi *vsi = pf->vsi[v];
4482 if (vsi != NULL &&
4483 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4484 i40e_vsi_reinit_locked(pf->vsi[v]);
4485 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4486 }
4487 }
4488
4489 /* no further action needed, so return now */
4490 return;
4491 } else {
4492 dev_info(&pf->pdev->dev,
4493 "bad reset request 0x%08x\n", reset_flags);
4494 return;
4495 }
4496}
4497
4e3b35b0
NP		 4498#ifdef CONFIG_I40E_DCB
4499/**
4500 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4501 * @pf: board private structure
4502 * @old_cfg: current DCB config
4503 * @new_cfg: new DCB config
4504 **/
4505bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4506 struct i40e_dcbx_config *old_cfg,
4507 struct i40e_dcbx_config *new_cfg)
4508{
4509 bool need_reconfig = false;
4510
4511 /* Check if ETS configuration has changed */
4512 if (memcmp(&new_cfg->etscfg,
4513 &old_cfg->etscfg,
4514 sizeof(new_cfg->etscfg))) {
4515 /* If Priority Table has changed reconfig is needed */
4516 if (memcmp(&new_cfg->etscfg.prioritytable,
4517 &old_cfg->etscfg.prioritytable,
4518 sizeof(new_cfg->etscfg.prioritytable))) {
4519 need_reconfig = true;
69bfb110 4520 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4521 }
4522
4523 if (memcmp(&new_cfg->etscfg.tcbwtable,
4524 &old_cfg->etscfg.tcbwtable,
4525 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4526 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4527
4528 if (memcmp(&new_cfg->etscfg.tsatable,
4529 &old_cfg->etscfg.tsatable,
4530 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4531 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4532 }
4533
4534 /* Check if PFC configuration has changed */
4535 if (memcmp(&new_cfg->pfc,
4536 &old_cfg->pfc,
4537 sizeof(new_cfg->pfc))) {
4538 need_reconfig = true;
69bfb110 4539 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4540 }
4541
4542 /* Check if APP Table has changed */
4543 if (memcmp(&new_cfg->app,
4544 &old_cfg->app,
3d9667a9 4545 sizeof(new_cfg->app))) {
4e3b35b0 4546 need_reconfig = true;
69bfb110 4547 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4548 }
4e3b35b0
NP		 4549
4550 return need_reconfig;
4551}
4552
4553/**
4554 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4555 * @pf: board private structure
4556 * @e: event info posted on ARQ
4557 **/
4558static int i40e_handle_lldp_event(struct i40e_pf *pf,
4559 struct i40e_arq_event_info *e)
4560{
4561 struct i40e_aqc_lldp_get_mib *mib =
4562 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4563 struct i40e_hw *hw = &pf->hw;
4564 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4565 struct i40e_dcbx_config tmp_dcbx_cfg;
4566 bool need_reconfig = false;
4567 int ret = 0;
4568 u8 type;
4569
4570 /* Ignore if event is not for Nearest Bridge */
4571 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4572 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4573 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4574 return ret;
4575
4576 /* Check MIB Type and return if event for Remote MIB update */
4577 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4578 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4579 /* Update the remote cached instance and return */
4580 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4581 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4582 &hw->remote_dcbx_config);
4583 goto exit;
4584 }
4585
4586 /* Convert/store the DCBX data from LLDPDU temporarily */
4587 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4588 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4589 if (ret) {
4590 /* Error in LLDPDU parsing return */
4591 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4592 goto exit;
4593 }
4594
4595 /* No change detected in DCBX configs */
4596 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4597 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4598 goto exit;
4599 }
4600
4601 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4602
4603 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4604
4605 /* Overwrite the new configuration */
4606 *dcbx_cfg = tmp_dcbx_cfg;
4607
4608 if (!need_reconfig)
4609 goto exit;
4610
4611 /* Reconfiguration needed quiesce all VSIs */
4612 i40e_pf_quiesce_all_vsi(pf);
4613
4614 /* Changes in configuration update VEB/VSI */
4615 i40e_dcb_reconfigure(pf);
4616
4617 i40e_pf_unquiesce_all_vsi(pf);
4618exit:
4619 return ret;
4620}
4621#endif /* CONFIG_I40E_DCB */
4622
23326186
ASJ		 4623/**
4624 * i40e_do_reset_safe - Protected reset path for userland calls.
4625 * @pf: board private structure
4626 * @reset_flags: which reset is requested
4627 *
4628 **/
4629void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4630{
4631 rtnl_lock();
4632 i40e_do_reset(pf, reset_flags);
4633 rtnl_unlock();
4634}
4635
41c445ff
JB		 4636/**
4637 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4638 * @pf: board private structure
4639 * @e: event info posted on ARQ
4640 *
4641 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4642 * and VF queues
4643 **/
4644static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4645 struct i40e_arq_event_info *e)
4646{
4647 struct i40e_aqc_lan_overflow *data =
4648 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4649 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4650 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4651 struct i40e_hw *hw = &pf->hw;
4652 struct i40e_vf *vf;
4653 u16 vf_id;
4654
69bfb110
JB		 4655 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4656 queue, qtx_ctl);
41c445ff
JB		 4657
4658 /* Queue belongs to VF, find the VF and issue VF reset */
4659 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4660 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4661 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4662 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4663 vf_id -= hw->func_caps.vf_base_id;
4664 vf = &pf->vf[vf_id];
4665 i40e_vc_notify_vf_reset(vf);
4666 /* Allow VF to process pending reset notification */
4667 msleep(20);
4668 i40e_reset_vf(vf, false);
4669 }
4670}
4671
4672/**
4673 * i40e_service_event_complete - Finish up the service event
4674 * @pf: board private structure
4675 **/
4676static void i40e_service_event_complete(struct i40e_pf *pf)
4677{
4678 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4679
4680 /* flush memory to make sure state is correct before next watchog */
4681 smp_mb__before_clear_bit();
4682 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4683}
4684
55a5e60b
ASJ		 4685/**
4686 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4687 * @pf: board private structure
4688 **/
4689int i40e_get_current_fd_count(struct i40e_pf *pf)
4690{
4691 int val, fcnt_prog;
4692 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4693 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4694 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4695 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4696 return fcnt_prog;
4697}
4698
4699/**
4700 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4701 * @pf: board private structure
4702 **/
4703void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4704{
4705 u32 fcnt_prog, fcnt_avail;
4706
4707 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4708 * to re-enable
4709 */
4710 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4711 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4712 return;
4713 fcnt_prog = i40e_get_current_fd_count(pf);
4714 fcnt_avail = pf->hw.fdir_shared_filter_count +
4715 pf->fdir_pf_filter_count;
4716 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4717 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4718 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4719 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4720 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4721 }
4722 }
4723 /* Wait for some more space to be available to turn on ATR */
4724 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4725 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4726 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4727 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4728 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4729 }
4730 }
4731}
4732
41c445ff
JB		 4733/**
4734 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4735 * @pf: board private structure
4736 **/
4737static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4738{
4739 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4740 return;
4741
41c445ff
JB		 4742 /* if interface is down do nothing */
4743 if (test_bit(__I40E_DOWN, &pf->state))
4744 return;
55a5e60b
ASJ		 4745 i40e_fdir_check_and_reenable(pf);
4746
4747 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4748 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4749 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4750}
4751
4752/**
4753 * i40e_vsi_link_event - notify VSI of a link event
4754 * @vsi: vsi to be notified
4755 * @link_up: link up or down
4756 **/
4757static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4758{
4759 if (!vsi)
4760 return;
4761
4762 switch (vsi->type) {
4763 case I40E_VSI_MAIN:
4764 if (!vsi->netdev || !vsi->netdev_registered)
4765 break;
4766
4767 if (link_up) {
4768 netif_carrier_on(vsi->netdev);
4769 netif_tx_wake_all_queues(vsi->netdev);
4770 } else {
4771 netif_carrier_off(vsi->netdev);
4772 netif_tx_stop_all_queues(vsi->netdev);
4773 }
4774 break;
4775
4776 case I40E_VSI_SRIOV:
4777 break;
4778
4779 case I40E_VSI_VMDQ2:
4780 case I40E_VSI_CTRL:
4781 case I40E_VSI_MIRROR:
4782 default:
4783 /* there is no notification for other VSIs */
4784 break;
4785 }
4786}
4787
4788/**
4789 * i40e_veb_link_event - notify elements on the veb of a link event
4790 * @veb: veb to be notified
4791 * @link_up: link up or down
4792 **/
4793static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4794{
4795 struct i40e_pf *pf;
4796 int i;
4797
4798 if (!veb || !veb->pf)
4799 return;
4800 pf = veb->pf;
4801
4802 /* depth first... */
4803 for (i = 0; i < I40E_MAX_VEB; i++)
4804 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4805 i40e_veb_link_event(pf->veb[i], link_up);
4806
4807 /* ... now the local VSIs */
4808 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4809 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4810 i40e_vsi_link_event(pf->vsi[i], link_up);
4811}
4812
4813/**
4814 * i40e_link_event - Update netif_carrier status
4815 * @pf: board private structure
4816 **/
4817static void i40e_link_event(struct i40e_pf *pf)
4818{
4819 bool new_link, old_link;
4820
4821 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4822 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4823
4824 if (new_link == old_link)
4825 return;
4826
6d779b41
AS		 4827 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4828 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4829 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4830
4831 /* Notify the base of the switch tree connected to
4832 * the link. Floating VEBs are not notified.
4833 */
4834 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4835 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4836 else
4837 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4838
4839 if (pf->vf)
4840 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4841
4842 if (pf->flags & I40E_FLAG_PTP)
4843 i40e_ptp_set_increment(pf);
41c445ff
JB		 4844}
4845
4846/**
4847 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4848 * @pf: board private structure
4849 *
4850 * Set the per-queue flags to request a check for stuck queues in the irq
4851 * clean functions, then force interrupts to be sure the irq clean is called.
4852 **/
4853static void i40e_check_hang_subtask(struct i40e_pf *pf)
4854{
4855 int i, v;
4856
4857 /* If we're down or resetting, just bail */
4858 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4859 return;
4860
4861 /* for each VSI/netdev
4862 * for each Tx queue
4863 * set the check flag
4864 * for each q_vector
4865 * force an interrupt
4866 */
4867 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4868 struct i40e_vsi *vsi = pf->vsi[v];
4869 int armed = 0;
4870
4871 if (!pf->vsi[v] ||
4872 test_bit(__I40E_DOWN, &vsi->state) ||
4873 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4874 continue;
4875
4876 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4877 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4878 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4879 &vsi->tx_rings[i]->state))
41c445ff
JB		 4880 armed++;
4881 }
4882
4883 if (armed) {
4884 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4885 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4886 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4887 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4888 } else {
4889 u16 vec = vsi->base_vector - 1;
4890 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4891 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4892 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4893 wr32(&vsi->back->hw,
4894 I40E_PFINT_DYN_CTLN(vec), val);
4895 }
4896 i40e_flush(&vsi->back->hw);
4897 }
4898 }
4899}
4900
4901/**
4902 * i40e_watchdog_subtask - Check and bring link up
4903 * @pf: board private structure
4904 **/
4905static void i40e_watchdog_subtask(struct i40e_pf *pf)
4906{
4907 int i;
4908
4909 /* if interface is down do nothing */
4910 if (test_bit(__I40E_DOWN, &pf->state) ||
4911 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4912 return;
4913
4914 /* Update the stats for active netdevs so the network stack
4915 * can look at updated numbers whenever it cares to
4916 */
4917 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4918 if (pf->vsi[i] && pf->vsi[i]->netdev)
4919 i40e_update_stats(pf->vsi[i]);
4920
4921 /* Update the stats for the active switching components */
4922 for (i = 0; i < I40E_MAX_VEB; i++)
4923 if (pf->veb[i])
4924 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4925
4926 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4927}
4928
4929/**
4930 * i40e_reset_subtask - Set up for resetting the device and driver
4931 * @pf: board private structure
4932 **/
4933static void i40e_reset_subtask(struct i40e_pf *pf)
4934{
4935 u32 reset_flags = 0;
4936
23326186 4937 rtnl_lock();
41c445ff
JB		 4938 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4939 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4940 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4941 }
4942 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4943 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4944 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4945 }
4946 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4947 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4948 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4949 }
4950 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4951 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4952 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4953 }
4954
4955 /* If there's a recovery already waiting, it takes
4956 * precedence before starting a new reset sequence.
4957 */
4958 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4959 i40e_handle_reset_warning(pf);
23326186 4960 goto unlock;
41c445ff
JB		 4961 }
4962
4963 /* If we're already down or resetting, just bail */
4964 if (reset_flags &&
4965 !test_bit(__I40E_DOWN, &pf->state) &&
4966 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4967 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4968
4969unlock:
4970 rtnl_unlock();
41c445ff
JB		 4971}
4972
4973/**
4974 * i40e_handle_link_event - Handle link event
4975 * @pf: board private structure
4976 * @e: event info posted on ARQ
4977 **/
4978static void i40e_handle_link_event(struct i40e_pf *pf,
4979 struct i40e_arq_event_info *e)
4980{
4981 struct i40e_hw *hw = &pf->hw;
4982 struct i40e_aqc_get_link_status *status =
4983 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4984 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4985
4986 /* save off old link status information */
4987 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4988 sizeof(pf->hw.phy.link_info_old));
4989
4990 /* update link status */
4991 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4992 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4993 hw_link_info->link_info = status->link_info;
4994 hw_link_info->an_info = status->an_info;
4995 hw_link_info->ext_info = status->ext_info;
4996 hw_link_info->lse_enable =
4997 le16_to_cpu(status->command_flags) &
4998 I40E_AQ_LSE_ENABLE;
4999
5000 /* process the event */
5001 i40e_link_event(pf);
5002
5003 /* Do a new status request to re-enable LSE reporting
5004 * and load new status information into the hw struct,
5005 * then see if the status changed while processing the
5006 * initial event.
5007 */
5008 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5009 i40e_link_event(pf);
5010}
5011
5012/**
5013 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5014 * @pf: board private structure
5015 **/
5016static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5017{
5018 struct i40e_arq_event_info event;
5019 struct i40e_hw *hw = &pf->hw;
5020 u16 pending, i = 0;
5021 i40e_status ret;
5022 u16 opcode;
5023 u32 val;
5024
5025 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5026 return;
5027
3197ce22 5028 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5029 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5030 if (!event.msg_buf)
5031 return;
5032
5033 do {
2f019123 5034 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5035 ret = i40e_clean_arq_element(hw, &event, &pending);
5036 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5037 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5038 break;
5039 } else if (ret) {
5040 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5041 break;
5042 }
5043
5044 opcode = le16_to_cpu(event.desc.opcode);
5045 switch (opcode) {
5046
5047 case i40e_aqc_opc_get_link_status:
5048 i40e_handle_link_event(pf, &event);
5049 break;
5050 case i40e_aqc_opc_send_msg_to_pf:
5051 ret = i40e_vc_process_vf_msg(pf,
5052 le16_to_cpu(event.desc.retval),
5053 le32_to_cpu(event.desc.cookie_high),
5054 le32_to_cpu(event.desc.cookie_low),
5055 event.msg_buf,
5056 event.msg_size);
5057 break;
5058 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5059 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5060#ifdef CONFIG_I40E_DCB
5061 rtnl_lock();
5062 ret = i40e_handle_lldp_event(pf, &event);
5063 rtnl_unlock();
5064#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5065 break;
5066 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5067 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5068 i40e_handle_lan_overflow_event(pf, &event);
5069 break;
0467bc91
SN		 5070 case i40e_aqc_opc_send_msg_to_peer:
5071 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5072 break;
41c445ff
JB		 5073 default:
5074 dev_info(&pf->pdev->dev,
0467bc91
SN		 5075 "ARQ Error: Unknown event 0x%04x received\n",
5076 opcode);
41c445ff
JB		 5077 break;
5078 }
5079 } while (pending && (i++ < pf->adminq_work_limit));
5080
5081 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5082 /* re-enable Admin queue interrupt cause */
5083 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5084 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5085 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5086 i40e_flush(hw);
5087
5088 kfree(event.msg_buf);
5089}
5090
4eb3f768
SN		 5091/**
5092 * i40e_verify_eeprom - make sure eeprom is good to use
5093 * @pf: board private structure
5094 **/
5095static void i40e_verify_eeprom(struct i40e_pf *pf)
5096{
5097 int err;
5098
5099 err = i40e_diag_eeprom_test(&pf->hw);
5100 if (err) {
5101 /* retry in case of garbage read */
5102 err = i40e_diag_eeprom_test(&pf->hw);
5103 if (err) {
5104 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5105 err);
5106 set_bit(__I40E_BAD_EEPROM, &pf->state);
5107 }
5108 }
5109
5110 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5111 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5112 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5113 }
5114}
5115
41c445ff
JB		 5116/**
5117 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5118 * @veb: pointer to the VEB instance
5119 *
5120 * This is a recursive function that first builds the attached VSIs then
5121 * recurses in to build the next layer of VEB. We track the connections
5122 * through our own index numbers because the seid's from the HW could
5123 * change across the reset.
5124 **/
5125static int i40e_reconstitute_veb(struct i40e_veb *veb)
5126{
5127 struct i40e_vsi *ctl_vsi = NULL;
5128 struct i40e_pf *pf = veb->pf;
5129 int v, veb_idx;
5130 int ret;
5131
5132 /* build VSI that owns this VEB, temporarily attached to base VEB */
5133 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
5134 if (pf->vsi[v] &&
5135 pf->vsi[v]->veb_idx == veb->idx &&
5136 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5137 ctl_vsi = pf->vsi[v];
5138 break;
5139 }
5140 }
5141 if (!ctl_vsi) {
5142 dev_info(&pf->pdev->dev,
5143 "missing owner VSI for veb_idx %d\n", veb->idx);
5144 ret = -ENOENT;
5145 goto end_reconstitute;
5146 }
5147 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5148 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5149 ret = i40e_add_vsi(ctl_vsi);
5150 if (ret) {
5151 dev_info(&pf->pdev->dev,
5152 "rebuild of owner VSI failed: %d\n", ret);
5153 goto end_reconstitute;
5154 }
5155 i40e_vsi_reset_stats(ctl_vsi);
5156
5157 /* create the VEB in the switch and move the VSI onto the VEB */
5158 ret = i40e_add_veb(veb, ctl_vsi);
5159 if (ret)
5160 goto end_reconstitute;
5161
5162 /* create the remaining VSIs attached to this VEB */
5163 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5164 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5165 continue;
5166
5167 if (pf->vsi[v]->veb_idx == veb->idx) {
5168 struct i40e_vsi *vsi = pf->vsi[v];
5169 vsi->uplink_seid = veb->seid;
5170 ret = i40e_add_vsi(vsi);
5171 if (ret) {
5172 dev_info(&pf->pdev->dev,
5173 "rebuild of vsi_idx %d failed: %d\n",
5174 v, ret);
5175 goto end_reconstitute;
5176 }
5177 i40e_vsi_reset_stats(vsi);
5178 }
5179 }
5180
5181 /* create any VEBs attached to this VEB - RECURSION */
5182 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5183 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5184 pf->veb[veb_idx]->uplink_seid = veb->seid;
5185 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5186 if (ret)
5187 break;
5188 }
5189 }
5190
5191end_reconstitute:
5192 return ret;
5193}
5194
5195/**
5196 * i40e_get_capabilities - get info about the HW
5197 * @pf: the PF struct
5198 **/
5199static int i40e_get_capabilities(struct i40e_pf *pf)
5200{
5201 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5202 u16 data_size;
5203 int buf_len;
5204 int err;
5205
5206 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5207 do {
5208 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5209 if (!cap_buf)
5210 return -ENOMEM;
5211
5212 /* this loads the data into the hw struct for us */
5213 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5214 &data_size,
5215 i40e_aqc_opc_list_func_capabilities,
5216 NULL);
5217 /* data loaded, buffer no longer needed */
5218 kfree(cap_buf);
5219
5220 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5221 /* retry with a larger buffer */
5222 buf_len = data_size;
5223 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5224 dev_info(&pf->pdev->dev,
5225 "capability discovery failed: aq=%d\n",
5226 pf->hw.aq.asq_last_status);
5227 return -ENODEV;
5228 }
5229 } while (err);
5230
ac71b7ba
ASJ		 5231 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5232 (pf->hw.aq.fw_maj_ver < 2)) {
5233 pf->hw.func_caps.num_msix_vectors++;
5234 pf->hw.func_caps.num_msix_vectors_vf++;
5235 }
5236
41c445ff
JB		 5237 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5238 dev_info(&pf->pdev->dev,
5239 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5240 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5241 pf->hw.func_caps.num_msix_vectors,
5242 pf->hw.func_caps.num_msix_vectors_vf,
5243 pf->hw.func_caps.fd_filters_guaranteed,
5244 pf->hw.func_caps.fd_filters_best_effort,
5245 pf->hw.func_caps.num_tx_qp,
5246 pf->hw.func_caps.num_vsis);
5247
7134f9ce
JB		 5248#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5249 + pf->hw.func_caps.num_vfs)
5250 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5251 dev_info(&pf->pdev->dev,
5252 "got num_vsis %d, setting num_vsis to %d\n",
5253 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5254 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5255 }
5256
41c445ff
JB		 5257 return 0;
5258}
5259
cbf61325
ASJ		 5260static int i40e_vsi_clear(struct i40e_vsi *vsi);
5261
41c445ff 5262/**
cbf61325 5263 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5264 * @pf: board private structure
5265 **/
cbf61325 5266static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5267{
5268 struct i40e_vsi *vsi;
8a9eb7d3 5269 int i;
41c445ff 5270
cbf61325 5271 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5272 return;
5273
cbf61325 5274 /* find existing VSI and see if it needs configuring */
41c445ff 5275 vsi = NULL;
cbf61325
ASJ		 5276 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5277 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5278 vsi = pf->vsi[i];
cbf61325
ASJ		 5279 break;
5280 }
5281 }
5282
5283 /* create a new VSI if none exists */
41c445ff 5284 if (!vsi) {
cbf61325
ASJ		 5285 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5286 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5287 if (!vsi) {
5288 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5289 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5290 return;
41c445ff 5291 }
41c445ff 5292 }
cbf61325 5293
8a9eb7d3 5294 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5295}
5296
5297/**
5298 * i40e_fdir_teardown - release the Flow Director resources
5299 * @pf: board private structure
5300 **/
5301static void i40e_fdir_teardown(struct i40e_pf *pf)
5302{
5303 int i;
5304
17a73f6b 5305 i40e_fdir_filter_exit(pf);
41c445ff
JB		 5306 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
5307 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5308 i40e_vsi_release(pf->vsi[i]);
5309 break;
5310 }
5311 }
5312}
5313
5314/**
f650a38b 5315 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5316 * @pf: board private structure
5317 *
f650a38b
ASJ		 5318 * Close up the VFs and other things in prep for pf Reset.
5319 **/
5320static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5321{
41c445ff
JB		 5322 struct i40e_hw *hw = &pf->hw;
5323 i40e_status ret;
5324 u32 v;
5325
5326 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5327 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5328 return 0;
41c445ff 5329
69bfb110 5330 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5331
37f0be6d
ASJ		 5332 if (i40e_check_asq_alive(hw))
5333 i40e_vc_notify_reset(pf);
41c445ff
JB		 5334
5335 /* quiesce the VSIs and their queues that are not already DOWN */
5336 i40e_pf_quiesce_all_vsi(pf);
5337
5338 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
5339 if (pf->vsi[v])
5340 pf->vsi[v]->seid = 0;
5341 }
5342
5343 i40e_shutdown_adminq(&pf->hw);
5344
f650a38b
ASJ		 5345 /* call shutdown HMC */
5346 ret = i40e_shutdown_lan_hmc(hw);
5347 if (ret) {
5348 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
5349 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5350 }
5351 return ret;
5352}
5353
5354/**
4dda12e6 5355 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5356 * @pf: board private structure
bc7d338f 5357 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5358 **/
bc7d338f 5359static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 5360{
5361 struct i40e_driver_version dv;
5362 struct i40e_hw *hw = &pf->hw;
5363 i40e_status ret;
5364 u32 v;
5365
41c445ff
JB		 5366 /* Now we wait for GRST to settle out.
5367 * We don't have to delete the VEBs or VSIs from the hw switch
5368 * because the reset will make them disappear.
5369 */
5370 ret = i40e_pf_reset(hw);
5371 if (ret)
5372 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
5373 pf->pfr_count++;
5374
5375 if (test_bit(__I40E_DOWN, &pf->state))
5376 goto end_core_reset;
69bfb110 5377 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5378
5379 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5380 ret = i40e_init_adminq(&pf->hw);
5381 if (ret) {
5382 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5383 goto end_core_reset;
5384 }
5385
4eb3f768
SN		 5386 /* re-verify the eeprom if we just had an EMP reset */
5387 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5388 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5389 i40e_verify_eeprom(pf);
5390 }
5391
41c445ff
JB		 5392 ret = i40e_get_capabilities(pf);
5393 if (ret) {
5394 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5395 ret);
5396 goto end_core_reset;
5397 }
5398
41c445ff
JB		 5399 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5400 hw->func_caps.num_rx_qp,
5401 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5402 if (ret) {
5403 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5404 goto end_core_reset;
5405 }
5406 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5407 if (ret) {
5408 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5409 goto end_core_reset;
5410 }
5411
4e3b35b0
NP		 5412#ifdef CONFIG_I40E_DCB
5413 ret = i40e_init_pf_dcb(pf);
5414 if (ret) {
5415 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5416 goto end_core_reset;
5417 }
5418#endif /* CONFIG_I40E_DCB */
5419
41c445ff 5420 /* do basic switch setup */
bc7d338f 5421 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5422 if (ret)
5423 goto end_core_reset;
5424
5425 /* Rebuild the VSIs and VEBs that existed before reset.
5426 * They are still in our local switch element arrays, so only
5427 * need to rebuild the switch model in the HW.
5428 *
5429 * If there were VEBs but the reconstitution failed, we'll try
5430 * try to recover minimal use by getting the basic PF VSI working.
5431 */
5432 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5433 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5434 /* find the one VEB connected to the MAC, and find orphans */
5435 for (v = 0; v < I40E_MAX_VEB; v++) {
5436 if (!pf->veb[v])
5437 continue;
5438
5439 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5440 pf->veb[v]->uplink_seid == 0) {
5441 ret = i40e_reconstitute_veb(pf->veb[v]);
5442
5443 if (!ret)
5444 continue;
5445
5446 /* If Main VEB failed, we're in deep doodoo,
5447 * so give up rebuilding the switch and set up
5448 * for minimal rebuild of PF VSI.
5449 * If orphan failed, we'll report the error
5450 * but try to keep going.
5451 */
5452 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5453 dev_info(&pf->pdev->dev,
5454 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5455 ret);
5456 pf->vsi[pf->lan_vsi]->uplink_seid
5457 = pf->mac_seid;
5458 break;
5459 } else if (pf->veb[v]->uplink_seid == 0) {
5460 dev_info(&pf->pdev->dev,
5461 "rebuild of orphan VEB failed: %d\n",
5462 ret);
5463 }
5464 }
5465 }
5466 }
5467
5468 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5469 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5470 /* no VEB, so rebuild only the Main VSI */
5471 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5472 if (ret) {
5473 dev_info(&pf->pdev->dev,
5474 "rebuild of Main VSI failed: %d\n", ret);
5475 goto end_core_reset;
5476 }
5477 }
5478
5479 /* reinit the misc interrupt */
5480 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5481 ret = i40e_setup_misc_vector(pf);
5482
5483 /* restart the VSIs that were rebuilt and running before the reset */
5484 i40e_pf_unquiesce_all_vsi(pf);
5485
69f64b2b
MW		 5486 if (pf->num_alloc_vfs) {
5487 for (v = 0; v < pf->num_alloc_vfs; v++)
5488 i40e_reset_vf(&pf->vf[v], true);
5489 }
5490
41c445ff
JB		 5491 /* tell the firmware that we're starting */
5492 dv.major_version = DRV_VERSION_MAJOR;
5493 dv.minor_version = DRV_VERSION_MINOR;
5494 dv.build_version = DRV_VERSION_BUILD;
5495 dv.subbuild_version = 0;
5496 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5497
69bfb110 5498 dev_info(&pf->pdev->dev, "reset complete\n");
41c445ff
JB		 5499
5500end_core_reset:
5501 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5502}
5503
f650a38b
ASJ		 5504/**
5505 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5506 * @pf: board private structure
5507 *
5508 * Close up the VFs and other things in prep for a Core Reset,
5509 * then get ready to rebuild the world.
5510 **/
5511static void i40e_handle_reset_warning(struct i40e_pf *pf)
5512{
5513 i40e_status ret;
5514
5515 ret = i40e_prep_for_reset(pf);
5516 if (!ret)
bc7d338f 5517 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5518}
5519
41c445ff
JB		 5520/**
5521 * i40e_handle_mdd_event
5522 * @pf: pointer to the pf structure
5523 *
5524 * Called from the MDD irq handler to identify possibly malicious vfs
5525 **/
5526static void i40e_handle_mdd_event(struct i40e_pf *pf)
5527{
5528 struct i40e_hw *hw = &pf->hw;
5529 bool mdd_detected = false;
5530 struct i40e_vf *vf;
5531 u32 reg;
5532 int i;
5533
5534 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5535 return;
5536
5537 /* find what triggered the MDD event */
5538 reg = rd32(hw, I40E_GL_MDET_TX);
5539 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5540 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5541 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5542 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5543 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5544 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5545 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5546 dev_info(&pf->pdev->dev,
f29eaa3d 5547 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5548 event, queue, func);
5549 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5550 mdd_detected = true;
5551 }
5552 reg = rd32(hw, I40E_GL_MDET_RX);
5553 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5554 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5555 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5556 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5557 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5558 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5559 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5560 dev_info(&pf->pdev->dev,
f29eaa3d 5561 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5562 event, queue, func);
5563 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5564 mdd_detected = true;
5565 }
5566
5567 /* see if one of the VFs needs its hand slapped */
5568 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5569 vf = &(pf->vf[i]);
5570 reg = rd32(hw, I40E_VP_MDET_TX(i));
5571 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5572 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5573 vf->num_mdd_events++;
5574 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5575 }
5576
5577 reg = rd32(hw, I40E_VP_MDET_RX(i));
5578 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5579 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5580 vf->num_mdd_events++;
5581 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5582 }
5583
5584 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5585 dev_info(&pf->pdev->dev,
5586 "Too many MDD events on VF %d, disabled\n", i);
5587 dev_info(&pf->pdev->dev,
5588 "Use PF Control I/F to re-enable the VF\n");
5589 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5590 }
5591 }
5592
5593 /* re-enable mdd interrupt cause */
5594 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5595 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5596 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5597 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5598 i40e_flush(hw);
5599}
5600
a1c9a9d9
JK		 5601#ifdef CONFIG_I40E_VXLAN
5602/**
5603 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5604 * @pf: board private structure
5605 **/
5606static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5607{
a1c9a9d9
JK		 5608 struct i40e_hw *hw = &pf->hw;
5609 i40e_status ret;
5610 u8 filter_index;
5611 __be16 port;
5612 int i;
5613
5614 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5615 return;
5616
5617 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5618
5619 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5620 if (pf->pending_vxlan_bitmap & (1 << i)) {
5621 pf->pending_vxlan_bitmap &= ~(1 << i);
5622 port = pf->vxlan_ports[i];
5623 ret = port ?
5624 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5625 I40E_AQC_TUNNEL_TYPE_VXLAN,
5626 &filter_index, NULL)
5627 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5628
5629 if (ret) {
5630 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5631 port ? "adding" : "deleting",
5632 ntohs(port), port ? i : i);
5633
5634 pf->vxlan_ports[i] = 0;
5635 } else {
5636 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5637 port ? "Added" : "Deleted",
5638 ntohs(port), port ? i : filter_index);
5639 }
5640 }
5641 }
5642}
5643
5644#endif
41c445ff
JB		 5645/**
5646 * i40e_service_task - Run the driver's async subtasks
5647 * @work: pointer to work_struct containing our data
5648 **/
5649static void i40e_service_task(struct work_struct *work)
5650{
5651 struct i40e_pf *pf = container_of(work,
5652 struct i40e_pf,
5653 service_task);
5654 unsigned long start_time = jiffies;
5655
5656 i40e_reset_subtask(pf);
5657 i40e_handle_mdd_event(pf);
5658 i40e_vc_process_vflr_event(pf);
5659 i40e_watchdog_subtask(pf);
5660 i40e_fdir_reinit_subtask(pf);
5661 i40e_check_hang_subtask(pf);
5662 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5663#ifdef CONFIG_I40E_VXLAN
5664 i40e_sync_vxlan_filters_subtask(pf);
5665#endif
41c445ff
JB		 5666 i40e_clean_adminq_subtask(pf);
5667
5668 i40e_service_event_complete(pf);
5669
5670 /* If the tasks have taken longer than one timer cycle or there
5671 * is more work to be done, reschedule the service task now
5672 * rather than wait for the timer to tick again.
5673 */
5674 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5675 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5676 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5677 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5678 i40e_service_event_schedule(pf);
5679}
5680
5681/**
5682 * i40e_service_timer - timer callback
5683 * @data: pointer to PF struct
5684 **/
5685static void i40e_service_timer(unsigned long data)
5686{
5687 struct i40e_pf *pf = (struct i40e_pf *)data;
5688
5689 mod_timer(&pf->service_timer,
5690 round_jiffies(jiffies + pf->service_timer_period));
5691 i40e_service_event_schedule(pf);
5692}
5693
5694/**
5695 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5696 * @vsi: the VSI being configured
5697 **/
5698static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5699{
5700 struct i40e_pf *pf = vsi->back;
5701
5702 switch (vsi->type) {
5703 case I40E_VSI_MAIN:
5704 vsi->alloc_queue_pairs = pf->num_lan_qps;
5705 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5706 I40E_REQ_DESCRIPTOR_MULTIPLE);
5707 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5708 vsi->num_q_vectors = pf->num_lan_msix;
5709 else
5710 vsi->num_q_vectors = 1;
5711
5712 break;
5713
5714 case I40E_VSI_FDIR:
5715 vsi->alloc_queue_pairs = 1;
5716 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5717 I40E_REQ_DESCRIPTOR_MULTIPLE);
5718 vsi->num_q_vectors = 1;
5719 break;
5720
5721 case I40E_VSI_VMDQ2:
5722 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5723 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5724 I40E_REQ_DESCRIPTOR_MULTIPLE);
5725 vsi->num_q_vectors = pf->num_vmdq_msix;
5726 break;
5727
5728 case I40E_VSI_SRIOV:
5729 vsi->alloc_queue_pairs = pf->num_vf_qps;
5730 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5731 I40E_REQ_DESCRIPTOR_MULTIPLE);
5732 break;
5733
5734 default:
5735 WARN_ON(1);
5736 return -ENODATA;
5737 }
5738
5739 return 0;
5740}
5741
f650a38b
ASJ		 5742/**
5743 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5744 * @type: VSI pointer
bc7d338f 5745 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5746 *
5747 * On error: returns error code (negative)
5748 * On success: returns 0
5749 **/
bc7d338f 5750static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5751{
5752 int size;
5753 int ret = 0;
5754
ac6c5e3d 5755 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5756 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5757 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5758 if (!vsi->tx_rings)
5759 return -ENOMEM;
f650a38b
ASJ		 5760 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5761
bc7d338f
ASJ		 5762 if (alloc_qvectors) {
5763 /* allocate memory for q_vector pointers */
5764 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5765 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5766 if (!vsi->q_vectors) {
5767 ret = -ENOMEM;
5768 goto err_vectors;
5769 }
f650a38b
ASJ		 5770 }
5771 return ret;
5772
5773err_vectors:
5774 kfree(vsi->tx_rings);
5775 return ret;
5776}
5777
41c445ff
JB		 5778/**
5779 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5780 * @pf: board private structure
5781 * @type: type of VSI
5782 *
5783 * On error: returns error code (negative)
5784 * On success: returns vsi index in PF (positive)
5785 **/
5786static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5787{
5788 int ret = -ENODEV;
5789 struct i40e_vsi *vsi;
5790 int vsi_idx;
5791 int i;
5792
5793 /* Need to protect the allocation of the VSIs at the PF level */
5794 mutex_lock(&pf->switch_mutex);
5795
5796 /* VSI list may be fragmented if VSI creation/destruction has
5797 * been happening. We can afford to do a quick scan to look
5798 * for any free VSIs in the list.
5799 *
5800 * find next empty vsi slot, looping back around if necessary
5801 */
5802 i = pf->next_vsi;
5803 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5804 i++;
5805 if (i >= pf->hw.func_caps.num_vsis) {
5806 i = 0;
5807 while (i < pf->next_vsi && pf->vsi[i])
5808 i++;
5809 }
5810
5811 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5812 vsi_idx = i; /* Found one! */
5813 } else {
5814 ret = -ENODEV;
493fb300 5815 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5816 }
5817 pf->next_vsi = ++i;
5818
5819 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5820 if (!vsi) {
5821 ret = -ENOMEM;
493fb300 5822 goto unlock_pf;
41c445ff
JB		 5823 }
5824 vsi->type = type;
5825 vsi->back = pf;
5826 set_bit(__I40E_DOWN, &vsi->state);
5827 vsi->flags = 0;
5828 vsi->idx = vsi_idx;
5829 vsi->rx_itr_setting = pf->rx_itr_default;
5830 vsi->tx_itr_setting = pf->tx_itr_default;
5831 vsi->netdev_registered = false;
5832 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5833 INIT_LIST_HEAD(&vsi->mac_filter_list);
5834
9f65e15b
AD		 5835 ret = i40e_set_num_rings_in_vsi(vsi);
5836 if (ret)
5837 goto err_rings;
5838
bc7d338f 5839 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5840 if (ret)
9f65e15b 5841 goto err_rings;
493fb300 5842
41c445ff
JB		 5843 /* Setup default MSIX irq handler for VSI */
5844 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5845
5846 pf->vsi[vsi_idx] = vsi;
5847 ret = vsi_idx;
493fb300
AD		 5848 goto unlock_pf;
5849
9f65e15b 5850err_rings:
493fb300
AD		 5851 pf->next_vsi = i - 1;
5852 kfree(vsi);
5853unlock_pf:
41c445ff
JB		 5854 mutex_unlock(&pf->switch_mutex);
5855 return ret;
5856}
5857
f650a38b
ASJ		 5858/**
5859 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5860 * @type: VSI pointer
bc7d338f 5861 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5862 *
5863 * On error: returns error code (negative)
5864 * On success: returns 0
5865 **/
bc7d338f 5866static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5867{
5868 /* free the ring and vector containers */
bc7d338f
ASJ		 5869 if (free_qvectors) {
5870 kfree(vsi->q_vectors);
5871 vsi->q_vectors = NULL;
5872 }
f650a38b
ASJ		 5873 kfree(vsi->tx_rings);
5874 vsi->tx_rings = NULL;
5875 vsi->rx_rings = NULL;
5876}
5877
41c445ff
JB		 5878/**
5879 * i40e_vsi_clear - Deallocate the VSI provided
5880 * @vsi: the VSI being un-configured
5881 **/
5882static int i40e_vsi_clear(struct i40e_vsi *vsi)
5883{
5884 struct i40e_pf *pf;
5885
5886 if (!vsi)
5887 return 0;
5888
5889 if (!vsi->back)
5890 goto free_vsi;
5891 pf = vsi->back;
5892
5893 mutex_lock(&pf->switch_mutex);
5894 if (!pf->vsi[vsi->idx]) {
5895 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5896 vsi->idx, vsi->idx, vsi, vsi->type);
5897 goto unlock_vsi;
5898 }
5899
5900 if (pf->vsi[vsi->idx] != vsi) {
5901 dev_err(&pf->pdev->dev,
5902 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5903 pf->vsi[vsi->idx]->idx,
5904 pf->vsi[vsi->idx],
5905 pf->vsi[vsi->idx]->type,
5906 vsi->idx, vsi, vsi->type);
5907 goto unlock_vsi;
5908 }
5909
5910 /* updates the pf for this cleared vsi */
5911 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5912 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5913
bc7d338f 5914 i40e_vsi_free_arrays(vsi, true);
493fb300 5915
41c445ff
JB		 5916 pf->vsi[vsi->idx] = NULL;
5917 if (vsi->idx < pf->next_vsi)
5918 pf->next_vsi = vsi->idx;
5919
5920unlock_vsi:
5921 mutex_unlock(&pf->switch_mutex);
5922free_vsi:
5923 kfree(vsi);
5924
5925 return 0;
5926}
5927
9f65e15b
AD		 5928/**
5929 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5930 * @vsi: the VSI being cleaned
5931 **/
be1d5eea 5932static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5933{
5934 int i;
5935
8e9dca53 5936 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5937 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5938 kfree_rcu(vsi->tx_rings[i], rcu);
5939 vsi->tx_rings[i] = NULL;
5940 vsi->rx_rings[i] = NULL;
5941 }
be1d5eea 5942 }
9f65e15b
AD		 5943}
5944
41c445ff
JB		 5945/**
5946 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5947 * @vsi: the VSI being configured
5948 **/
5949static int i40e_alloc_rings(struct i40e_vsi *vsi)
5950{
5951 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5952 int i;
5953
41c445ff 5954 /* Set basic values in the rings to be used later during open() */
d7397644 5955 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5956 struct i40e_ring *tx_ring;
5957 struct i40e_ring *rx_ring;
5958
ac6c5e3d 5959 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5960 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5961 if (!tx_ring)
5962 goto err_out;
41c445ff
JB		 5963
5964 tx_ring->queue_index = i;
5965 tx_ring->reg_idx = vsi->base_queue + i;
5966 tx_ring->ring_active = false;
5967 tx_ring->vsi = vsi;
5968 tx_ring->netdev = vsi->netdev;
5969 tx_ring->dev = &pf->pdev->dev;
5970 tx_ring->count = vsi->num_desc;
5971 tx_ring->size = 0;
5972 tx_ring->dcb_tc = 0;
9f65e15b 5973 vsi->tx_rings[i] = tx_ring;
41c445ff 5974
9f65e15b 5975 rx_ring = &tx_ring[1];
41c445ff
JB		 5976 rx_ring->queue_index = i;
5977 rx_ring->reg_idx = vsi->base_queue + i;
5978 rx_ring->ring_active = false;
5979 rx_ring->vsi = vsi;
5980 rx_ring->netdev = vsi->netdev;
5981 rx_ring->dev = &pf->pdev->dev;
5982 rx_ring->count = vsi->num_desc;
5983 rx_ring->size = 0;
5984 rx_ring->dcb_tc = 0;
5985 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5986 set_ring_16byte_desc_enabled(rx_ring);
5987 else
5988 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5989 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5990 }
5991
5992 return 0;
9f65e15b
AD		 5993
5994err_out:
5995 i40e_vsi_clear_rings(vsi);
5996 return -ENOMEM;
41c445ff
JB		 5997}
5998
5999/**
6000 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6001 * @pf: board private structure
6002 * @vectors: the number of MSI-X vectors to request
6003 *
6004 * Returns the number of vectors reserved, or error
6005 **/
6006static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6007{
7b37f376
AG		 6008 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6009 I40E_MIN_MSIX, vectors);
6010 if (vectors < 0) {
41c445ff 6011 dev_info(&pf->pdev->dev,
7b37f376 6012 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6013 vectors = 0;
6014 }
6015
7b37f376
AG		 6016 pf->num_msix_entries = vectors;
6017
41c445ff
JB		 6018 return vectors;
6019}
6020
6021/**
6022 * i40e_init_msix - Setup the MSIX capability
6023 * @pf: board private structure
6024 *
6025 * Work with the OS to set up the MSIX vectors needed.
6026 *
6027 * Returns 0 on success, negative on failure
6028 **/
6029static int i40e_init_msix(struct i40e_pf *pf)
6030{
6031 i40e_status err = 0;
6032 struct i40e_hw *hw = &pf->hw;
6033 int v_budget, i;
6034 int vec;
6035
6036 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6037 return -ENODEV;
6038
6039 /* The number of vectors we'll request will be comprised of:
6040 * - Add 1 for "other" cause for Admin Queue events, etc.
6041 * - The number of LAN queue pairs
f8ff1464
ASJ		 6042 * - Queues being used for RSS.
6043 * We don't need as many as max_rss_size vectors.
6044 * use rss_size instead in the calculation since that
6045 * is governed by number of cpus in the system.
6046 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6047 * - The number of VMDq pairs
6048 * Once we count this up, try the request.
6049 *
6050 * If we can't get what we want, we'll simplify to nearly nothing
6051 * and try again. If that still fails, we punt.
6052 */
f8ff1464 6053 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6054 pf->num_vmdq_msix = pf->num_vmdq_qps;
6055 v_budget = 1 + pf->num_lan_msix;
6056 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6057 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6058 v_budget++;
6059
6060 /* Scale down if necessary, and the rings will share vectors */
6061 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6062
6063 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6064 GFP_KERNEL);
6065 if (!pf->msix_entries)
6066 return -ENOMEM;
6067
6068 for (i = 0; i < v_budget; i++)
6069 pf->msix_entries[i].entry = i;
6070 vec = i40e_reserve_msix_vectors(pf, v_budget);
6071 if (vec < I40E_MIN_MSIX) {
6072 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6073 kfree(pf->msix_entries);
6074 pf->msix_entries = NULL;
6075 return -ENODEV;
6076
6077 } else if (vec == I40E_MIN_MSIX) {
6078 /* Adjust for minimal MSIX use */
77fa28be 6079 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6080 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6081 pf->num_vmdq_vsis = 0;
6082 pf->num_vmdq_qps = 0;
6083 pf->num_vmdq_msix = 0;
6084 pf->num_lan_qps = 1;
6085 pf->num_lan_msix = 1;
6086
6087 } else if (vec != v_budget) {
6088 /* Scale vector usage down */
6089 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6090 vec--; /* reserve the misc vector */
6091
6092 /* partition out the remaining vectors */
6093 switch (vec) {
6094 case 2:
6095 pf->num_vmdq_vsis = 1;
6096 pf->num_lan_msix = 1;
6097 break;
6098 case 3:
6099 pf->num_vmdq_vsis = 1;
6100 pf->num_lan_msix = 2;
6101 break;
6102 default:
6103 pf->num_lan_msix = min_t(int, (vec / 2),
6104 pf->num_lan_qps);
6105 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6106 I40E_DEFAULT_NUM_VMDQ_VSI);
6107 break;
6108 }
6109 }
6110
6111 return err;
6112}
6113
493fb300 6114/**
90e04070 6115 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6116 * @vsi: the VSI being configured
6117 * @v_idx: index of the vector in the vsi struct
6118 *
6119 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6120 **/
90e04070 6121static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6122{
6123 struct i40e_q_vector *q_vector;
6124
6125 /* allocate q_vector */
6126 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6127 if (!q_vector)
6128 return -ENOMEM;
6129
6130 q_vector->vsi = vsi;
6131 q_vector->v_idx = v_idx;
6132 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6133 if (vsi->netdev)
6134 netif_napi_add(vsi->netdev, &q_vector->napi,
6135 i40e_napi_poll, vsi->work_limit);
6136
cd0b6fa6
AD		 6137 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6138 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6139
493fb300
AD		 6140 /* tie q_vector and vsi together */
6141 vsi->q_vectors[v_idx] = q_vector;
6142
6143 return 0;
6144}
6145
41c445ff 6146/**
90e04070 6147 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6148 * @vsi: the VSI being configured
6149 *
6150 * We allocate one q_vector per queue interrupt. If allocation fails we
6151 * return -ENOMEM.
6152 **/
90e04070 6153static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6154{
6155 struct i40e_pf *pf = vsi->back;
6156 int v_idx, num_q_vectors;
493fb300 6157 int err;
41c445ff
JB		 6158
6159 /* if not MSIX, give the one vector only to the LAN VSI */
6160 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6161 num_q_vectors = vsi->num_q_vectors;
6162 else if (vsi == pf->vsi[pf->lan_vsi])
6163 num_q_vectors = 1;
6164 else
6165 return -EINVAL;
6166
41c445ff 6167 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6168 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6169 if (err)
6170 goto err_out;
41c445ff
JB		 6171 }
6172
6173 return 0;
493fb300
AD		 6174
6175err_out:
6176 while (v_idx--)
6177 i40e_free_q_vector(vsi, v_idx);
6178
6179 return err;
41c445ff
JB		 6180}
6181
6182/**
6183 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6184 * @pf: board private structure to initialize
6185 **/
6186static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6187{
6188 int err = 0;
6189
6190 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6191 err = i40e_init_msix(pf);
6192 if (err) {
60ea5f83
JB		 6193 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6194 I40E_FLAG_RSS_ENABLED |
6195 I40E_FLAG_DCB_ENABLED |
6196 I40E_FLAG_SRIOV_ENABLED |
6197 I40E_FLAG_FD_SB_ENABLED |
6198 I40E_FLAG_FD_ATR_ENABLED |
6199 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6200
6201 /* rework the queue expectations without MSIX */
6202 i40e_determine_queue_usage(pf);
6203 }
6204 }
6205
6206 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6207 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6208 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6209 err = pci_enable_msi(pf->pdev);
6210 if (err) {
958a3e3b 6211 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6212 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6213 }
6214 }
6215
958a3e3b 6216 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6217 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6218
41c445ff
JB		 6219 /* track first vector for misc interrupts */
6220 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6221}
6222
6223/**
6224 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6225 * @pf: board private structure
6226 *
6227 * This sets up the handler for MSIX 0, which is used to manage the
6228 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6229 * when in MSI or Legacy interrupt mode.
6230 **/
6231static int i40e_setup_misc_vector(struct i40e_pf *pf)
6232{
6233 struct i40e_hw *hw = &pf->hw;
6234 int err = 0;
6235
6236 /* Only request the irq if this is the first time through, and
6237 * not when we're rebuilding after a Reset
6238 */
6239 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6240 err = request_irq(pf->msix_entries[0].vector,
6241 i40e_intr, 0, pf->misc_int_name, pf);
6242 if (err) {
6243 dev_info(&pf->pdev->dev,
77fa28be
CS		 6244 "request_irq for %s failed: %d\n",
6245 pf->misc_int_name, err);
41c445ff
JB		 6246 return -EFAULT;
6247 }
6248 }
6249
6250 i40e_enable_misc_int_causes(hw);
6251
6252 /* associate no queues to the misc vector */
6253 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6254 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6255
6256 i40e_flush(hw);
6257
6258 i40e_irq_dynamic_enable_icr0(pf);
6259
6260 return err;
6261}
6262
6263/**
6264 * i40e_config_rss - Prepare for RSS if used
6265 * @pf: board private structure
6266 **/
6267static int i40e_config_rss(struct i40e_pf *pf)
6268{
41c445ff
JB		 6269 /* Set of random keys generated using kernel random number generator */
6270 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6271 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6272 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6273 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6274 struct i40e_hw *hw = &pf->hw;
6275 u32 lut = 0;
6276 int i, j;
6277 u64 hena;
41c445ff
JB		 6278
6279 /* Fill out hash function seed */
6280 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6281 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6282
6283 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6284 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6285 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6286 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6287 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6288 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6289
6290 /* Populate the LUT with max no. of queues in round robin fashion */
6291 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6292
6293 /* The assumption is that lan qp count will be the highest
6294 * qp count for any PF VSI that needs RSS.
6295 * If multiple VSIs need RSS support, all the qp counts
6296 * for those VSIs should be a power of 2 for RSS to work.
6297 * If LAN VSI is the only consumer for RSS then this requirement
6298 * is not necessary.
6299 */
6300 if (j == pf->rss_size)
6301 j = 0;
6302 /* lut = 4-byte sliding window of 4 lut entries */
6303 lut = (lut << 8) | (j &
6304 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6305 /* On i = 3, we have 4 entries in lut; write to the register */
6306 if ((i & 3) == 3)
6307 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6308 }
6309 i40e_flush(hw);
6310
6311 return 0;
6312}
6313
f8ff1464
ASJ		 6314/**
6315 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6316 * @pf: board private structure
6317 * @queue_count: the requested queue count for rss.
6318 *
6319 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6320 * count which may be different from the requested queue count.
6321 **/
6322int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6323{
6324 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6325 return 0;
6326
6327 queue_count = min_t(int, queue_count, pf->rss_size_max);
6328 queue_count = rounddown_pow_of_two(queue_count);
6329
6330 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6331 i40e_prep_for_reset(pf);
6332
f8ff1464
ASJ		 6333 pf->rss_size = queue_count;
6334
6335 i40e_reset_and_rebuild(pf, true);
6336 i40e_config_rss(pf);
6337 }
6338 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6339 return pf->rss_size;
6340}
6341
41c445ff
JB		 6342/**
6343 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6344 * @pf: board private structure to initialize
6345 *
6346 * i40e_sw_init initializes the Adapter private data structure.
6347 * Fields are initialized based on PCI device information and
6348 * OS network device settings (MTU size).
6349 **/
6350static int i40e_sw_init(struct i40e_pf *pf)
6351{
6352 int err = 0;
6353 int size;
6354
6355 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6356 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6357 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6358 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6359 if (I40E_DEBUG_USER & debug)
6360 pf->hw.debug_mask = debug;
6361 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6362 I40E_DEFAULT_MSG_ENABLE);
6363 }
6364
6365 /* Set default capability flags */
6366 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6367 I40E_FLAG_MSI_ENABLED |
6368 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6369 I40E_FLAG_RX_1BUF_ENABLED;
6370
ca99eb99
MW		 6371 /* Set default ITR */
6372 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6373 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6374
7134f9ce
JB		 6375 /* Depending on PF configurations, it is possible that the RSS
6376 * maximum might end up larger than the available queues
6377 */
41c445ff 6378 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6379 pf->rss_size_max = min_t(int, pf->rss_size_max,
6380 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6381 if (pf->hw.func_caps.rss) {
6382 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6383 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6384 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6385 } else {
6386 pf->rss_size = 1;
6387 }
6388
2050bc65
CS		 6389 /* MFP mode enabled */
6390 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6391 pf->flags |= I40E_FLAG_MFP_ENABLED;
6392 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6393 }
6394
cbf61325
ASJ		 6395 /* FW/NVM is not yet fixed in this regard */
6396 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6397 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6398 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6399 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6400 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6401 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6402 } else {
6403 dev_info(&pf->pdev->dev,
0b67584f 6404 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6405 }
cbf61325
ASJ		 6406 pf->fdir_pf_filter_count =
6407 pf->hw.func_caps.fd_filters_guaranteed;
6408 pf->hw.fdir_shared_filter_count =
6409 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6410 }
6411
6412 if (pf->hw.func_caps.vmdq) {
6413 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6414 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6415 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6416 }
6417
41c445ff
JB		 6418#ifdef CONFIG_PCI_IOV
6419 if (pf->hw.func_caps.num_vfs) {
6420 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6421 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6422 pf->num_req_vfs = min_t(int,
6423 pf->hw.func_caps.num_vfs,
6424 I40E_MAX_VF_COUNT);
6425 }
6426#endif /* CONFIG_PCI_IOV */
6427 pf->eeprom_version = 0xDEAD;
6428 pf->lan_veb = I40E_NO_VEB;
6429 pf->lan_vsi = I40E_NO_VSI;
6430
6431 /* set up queue assignment tracking */
6432 size = sizeof(struct i40e_lump_tracking)
6433 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6434 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6435 if (!pf->qp_pile) {
6436 err = -ENOMEM;
6437 goto sw_init_done;
6438 }
6439 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6440 pf->qp_pile->search_hint = 0;
6441
6442 /* set up vector assignment tracking */
6443 size = sizeof(struct i40e_lump_tracking)
6444 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6445 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6446 if (!pf->irq_pile) {
6447 kfree(pf->qp_pile);
6448 err = -ENOMEM;
6449 goto sw_init_done;
6450 }
6451 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6452 pf->irq_pile->search_hint = 0;
6453
6454 mutex_init(&pf->switch_mutex);
6455
6456sw_init_done:
6457 return err;
6458}
6459
7c3c288b
ASJ		 6460/**
6461 * i40e_set_ntuple - set the ntuple feature flag and take action
6462 * @pf: board private structure to initialize
6463 * @features: the feature set that the stack is suggesting
6464 *
6465 * returns a bool to indicate if reset needs to happen
6466 **/
6467bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6468{
6469 bool need_reset = false;
6470
6471 /* Check if Flow Director n-tuple support was enabled or disabled. If
6472 * the state changed, we need to reset.
6473 */
6474 if (features & NETIF_F_NTUPLE) {
6475 /* Enable filters and mark for reset */
6476 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6477 need_reset = true;
6478 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6479 } else {
6480 /* turn off filters, mark for reset and clear SW filter list */
6481 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6482 need_reset = true;
6483 i40e_fdir_filter_exit(pf);
6484 }
6485 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6486 /* if ATR was disabled it can be re-enabled. */
6487 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6488 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6489 }
6490 return need_reset;
6491}
6492
41c445ff
JB		 6493/**
6494 * i40e_set_features - set the netdev feature flags
6495 * @netdev: ptr to the netdev being adjusted
6496 * @features: the feature set that the stack is suggesting
6497 **/
6498static int i40e_set_features(struct net_device *netdev,
6499 netdev_features_t features)
6500{
6501 struct i40e_netdev_priv *np = netdev_priv(netdev);
6502 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6503 struct i40e_pf *pf = vsi->back;
6504 bool need_reset;
41c445ff
JB		 6505
6506 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6507 i40e_vlan_stripping_enable(vsi);
6508 else
6509 i40e_vlan_stripping_disable(vsi);
6510
7c3c288b
ASJ		 6511 need_reset = i40e_set_ntuple(pf, features);
6512
6513 if (need_reset)
6514 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6515
41c445ff
JB		 6516 return 0;
6517}
6518
a1c9a9d9
JK		 6519#ifdef CONFIG_I40E_VXLAN
6520/**
6521 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6522 * @pf: board private structure
6523 * @port: The UDP port to look up
6524 *
6525 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6526 **/
6527static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6528{
6529 u8 i;
6530
6531 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6532 if (pf->vxlan_ports[i] == port)
6533 return i;
6534 }
6535
6536 return i;
6537}
6538
6539/**
6540 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6541 * @netdev: This physical port's netdev
6542 * @sa_family: Socket Family that VXLAN is notifying us about
6543 * @port: New UDP port number that VXLAN started listening to
6544 **/
6545static void i40e_add_vxlan_port(struct net_device *netdev,
6546 sa_family_t sa_family, __be16 port)
6547{
6548 struct i40e_netdev_priv *np = netdev_priv(netdev);
6549 struct i40e_vsi *vsi = np->vsi;
6550 struct i40e_pf *pf = vsi->back;
6551 u8 next_idx;
6552 u8 idx;
6553
6554 if (sa_family == AF_INET6)
6555 return;
6556
6557 idx = i40e_get_vxlan_port_idx(pf, port);
6558
6559 /* Check if port already exists */
6560 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6561 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6562 return;
6563 }
6564
6565 /* Now check if there is space to add the new port */
6566 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6567
6568 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6569 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6570 ntohs(port));
6571 return;
6572 }
6573
6574 /* New port: add it and mark its index in the bitmap */
6575 pf->vxlan_ports[next_idx] = port;
6576 pf->pending_vxlan_bitmap |= (1 << next_idx);
6577
6578 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6579}
6580
6581/**
6582 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6583 * @netdev: This physical port's netdev
6584 * @sa_family: Socket Family that VXLAN is notifying us about
6585 * @port: UDP port number that VXLAN stopped listening to
6586 **/
6587static void i40e_del_vxlan_port(struct net_device *netdev,
6588 sa_family_t sa_family, __be16 port)
6589{
6590 struct i40e_netdev_priv *np = netdev_priv(netdev);
6591 struct i40e_vsi *vsi = np->vsi;
6592 struct i40e_pf *pf = vsi->back;
6593 u8 idx;
6594
6595 if (sa_family == AF_INET6)
6596 return;
6597
6598 idx = i40e_get_vxlan_port_idx(pf, port);
6599
6600 /* Check if port already exists */
6601 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6602 /* if port exists, set it to 0 (mark for deletion)
6603 * and make it pending
6604 */
6605 pf->vxlan_ports[idx] = 0;
6606
6607 pf->pending_vxlan_bitmap |= (1 << idx);
6608
6609 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6610 } else {
6611 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6612 ntohs(port));
6613 }
6614}
6615
6616#endif
4ba0dea5
GR		 6617#ifdef HAVE_FDB_OPS
6618#ifdef USE_CONST_DEV_UC_CHAR
6619static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6620 struct net_device *dev,
6621 const unsigned char *addr,
6622 u16 flags)
6623#else
6624static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6625 struct net_device *dev,
6626 unsigned char *addr,
6627 u16 flags)
6628#endif
6629{
6630 struct i40e_netdev_priv *np = netdev_priv(dev);
6631 struct i40e_pf *pf = np->vsi->back;
6632 int err = 0;
6633
6634 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6635 return -EOPNOTSUPP;
6636
6637 /* Hardware does not support aging addresses so if a
6638 * ndm_state is given only allow permanent addresses
6639 */
6640 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6641 netdev_info(dev, "FDB only supports static addresses\n");
6642 return -EINVAL;
6643 }
6644
6645 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6646 err = dev_uc_add_excl(dev, addr);
6647 else if (is_multicast_ether_addr(addr))
6648 err = dev_mc_add_excl(dev, addr);
6649 else
6650 err = -EINVAL;
6651
6652 /* Only return duplicate errors if NLM_F_EXCL is set */
6653 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6654 err = 0;
6655
6656 return err;
6657}
6658
6659#ifndef USE_DEFAULT_FDB_DEL_DUMP
6660#ifdef USE_CONST_DEV_UC_CHAR
6661static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6662 struct net_device *dev,
6663 const unsigned char *addr)
6664#else
6665static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6666 struct net_device *dev,
6667 unsigned char *addr)
6668#endif
6669{
6670 struct i40e_netdev_priv *np = netdev_priv(dev);
6671 struct i40e_pf *pf = np->vsi->back;
6672 int err = -EOPNOTSUPP;
6673
6674 if (ndm->ndm_state & NUD_PERMANENT) {
6675 netdev_info(dev, "FDB only supports static addresses\n");
6676 return -EINVAL;
6677 }
6678
6679 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6680 if (is_unicast_ether_addr(addr))
6681 err = dev_uc_del(dev, addr);
6682 else if (is_multicast_ether_addr(addr))
6683 err = dev_mc_del(dev, addr);
6684 else
6685 err = -EINVAL;
6686 }
6687
6688 return err;
6689}
6690
6691static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6692 struct netlink_callback *cb,
6693 struct net_device *dev,
6694 int idx)
6695{
6696 struct i40e_netdev_priv *np = netdev_priv(dev);
6697 struct i40e_pf *pf = np->vsi->back;
6698
6699 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6700 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6701
6702 return idx;
6703}
6704
6705#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6706#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6707static const struct net_device_ops i40e_netdev_ops = {
6708 .ndo_open = i40e_open,
6709 .ndo_stop = i40e_close,
6710 .ndo_start_xmit = i40e_lan_xmit_frame,
6711 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6712 .ndo_set_rx_mode = i40e_set_rx_mode,
6713 .ndo_validate_addr = eth_validate_addr,
6714 .ndo_set_mac_address = i40e_set_mac,
6715 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6716 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6717 .ndo_tx_timeout = i40e_tx_timeout,
6718 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6719 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6720#ifdef CONFIG_NET_POLL_CONTROLLER
6721 .ndo_poll_controller = i40e_netpoll,
6722#endif
6723 .ndo_setup_tc = i40e_setup_tc,
6724 .ndo_set_features = i40e_set_features,
6725 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6726 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6727 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6728 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6729 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6730#ifdef CONFIG_I40E_VXLAN
6731 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6732 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6733#endif
4ba0dea5
GR		 6734#ifdef HAVE_FDB_OPS
6735 .ndo_fdb_add = i40e_ndo_fdb_add,
6736#ifndef USE_DEFAULT_FDB_DEL_DUMP
6737 .ndo_fdb_del = i40e_ndo_fdb_del,
6738 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6739#endif
6740#endif
41c445ff
JB		 6741};
6742
6743/**
6744 * i40e_config_netdev - Setup the netdev flags
6745 * @vsi: the VSI being configured
6746 *
6747 * Returns 0 on success, negative value on failure
6748 **/
6749static int i40e_config_netdev(struct i40e_vsi *vsi)
6750{
1a10370a 6751 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6752 struct i40e_pf *pf = vsi->back;
6753 struct i40e_hw *hw = &pf->hw;
6754 struct i40e_netdev_priv *np;
6755 struct net_device *netdev;
6756 u8 mac_addr[ETH_ALEN];
6757 int etherdev_size;
6758
6759 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6760 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6761 if (!netdev)
6762 return -ENOMEM;
6763
6764 vsi->netdev = netdev;
6765 np = netdev_priv(netdev);
6766 np->vsi = vsi;
6767
d70e941b 6768 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6769 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6770 NETIF_F_TSO;
41c445ff
JB		 6771
6772 netdev->features = NETIF_F_SG |
6773 NETIF_F_IP_CSUM |
6774 NETIF_F_SCTP_CSUM |
6775 NETIF_F_HIGHDMA |
6776 NETIF_F_GSO_UDP_TUNNEL |
6777 NETIF_F_HW_VLAN_CTAG_TX |
6778 NETIF_F_HW_VLAN_CTAG_RX |
6779 NETIF_F_HW_VLAN_CTAG_FILTER |
6780 NETIF_F_IPV6_CSUM |
6781 NETIF_F_TSO |
059dab69 6782 NETIF_F_TSO_ECN |
41c445ff
JB		 6783 NETIF_F_TSO6 |
6784 NETIF_F_RXCSUM |
6785 NETIF_F_RXHASH |
6786 0;
6787
2e86a0b6
ASJ		 6788 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
6789 netdev->features |= NETIF_F_NTUPLE;
6790
41c445ff
JB		 6791 /* copy netdev features into list of user selectable features */
6792 netdev->hw_features |= netdev->features;
6793
6794 if (vsi->type == I40E_VSI_MAIN) {
6795 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6796 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6797 } else {
6798 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6799 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6800 pf->vsi[pf->lan_vsi]->netdev->name);
6801 random_ether_addr(mac_addr);
6802 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6803 }
1a10370a 6804 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6805
6806 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6807 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6808 /* vlan gets same features (except vlan offload)
6809 * after any tweaks for specific VSI types
6810 */
6811 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6812 NETIF_F_HW_VLAN_CTAG_RX |
6813 NETIF_F_HW_VLAN_CTAG_FILTER);
6814 netdev->priv_flags |= IFF_UNICAST_FLT;
6815 netdev->priv_flags |= IFF_SUPP_NOFCS;
6816 /* Setup netdev TC information */
6817 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6818
6819 netdev->netdev_ops = &i40e_netdev_ops;
6820 netdev->watchdog_timeo = 5 * HZ;
6821 i40e_set_ethtool_ops(netdev);
6822
6823 return 0;
6824}
6825
6826/**
6827 * i40e_vsi_delete - Delete a VSI from the switch
6828 * @vsi: the VSI being removed
6829 *
6830 * Returns 0 on success, negative value on failure
6831 **/
6832static void i40e_vsi_delete(struct i40e_vsi *vsi)
6833{
6834 /* remove default VSI is not allowed */
6835 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6836 return;
6837
41c445ff
JB		 6838 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6839 return;
6840}
6841
6842/**
6843 * i40e_add_vsi - Add a VSI to the switch
6844 * @vsi: the VSI being configured
6845 *
6846 * This initializes a VSI context depending on the VSI type to be added and
6847 * passes it down to the add_vsi aq command.
6848 **/
6849static int i40e_add_vsi(struct i40e_vsi *vsi)
6850{
6851 int ret = -ENODEV;
6852 struct i40e_mac_filter *f, *ftmp;
6853 struct i40e_pf *pf = vsi->back;
6854 struct i40e_hw *hw = &pf->hw;
6855 struct i40e_vsi_context ctxt;
6856 u8 enabled_tc = 0x1; /* TC0 enabled */
6857 int f_count = 0;
6858
6859 memset(&ctxt, 0, sizeof(ctxt));
6860 switch (vsi->type) {
6861 case I40E_VSI_MAIN:
6862 /* The PF's main VSI is already setup as part of the
6863 * device initialization, so we'll not bother with
6864 * the add_vsi call, but we will retrieve the current
6865 * VSI context.
6866 */
6867 ctxt.seid = pf->main_vsi_seid;
6868 ctxt.pf_num = pf->hw.pf_id;
6869 ctxt.vf_num = 0;
6870 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6871 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6872 if (ret) {
6873 dev_info(&pf->pdev->dev,
6874 "couldn't get pf vsi config, err %d, aq_err %d\n",
6875 ret, pf->hw.aq.asq_last_status);
6876 return -ENOENT;
6877 }
6878 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6879 vsi->info.valid_sections = 0;
6880
6881 vsi->seid = ctxt.seid;
6882 vsi->id = ctxt.vsi_number;
6883
6884 enabled_tc = i40e_pf_get_tc_map(pf);
6885
6886 /* MFP mode setup queue map and update VSI */
6887 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6888 memset(&ctxt, 0, sizeof(ctxt));
6889 ctxt.seid = pf->main_vsi_seid;
6890 ctxt.pf_num = pf->hw.pf_id;
6891 ctxt.vf_num = 0;
6892 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6893 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6894 if (ret) {
6895 dev_info(&pf->pdev->dev,
6896 "update vsi failed, aq_err=%d\n",
6897 pf->hw.aq.asq_last_status);
6898 ret = -ENOENT;
6899 goto err;
6900 }
6901 /* update the local VSI info queue map */
6902 i40e_vsi_update_queue_map(vsi, &ctxt);
6903 vsi->info.valid_sections = 0;
6904 } else {
6905 /* Default/Main VSI is only enabled for TC0
6906 * reconfigure it to enable all TCs that are
6907 * available on the port in SFP mode.
6908 */
6909 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6910 if (ret) {
6911 dev_info(&pf->pdev->dev,
6912 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6913 enabled_tc, ret,
6914 pf->hw.aq.asq_last_status);
6915 ret = -ENOENT;
6916 }
6917 }
6918 break;
6919
6920 case I40E_VSI_FDIR:
cbf61325
ASJ		 6921 ctxt.pf_num = hw->pf_id;
6922 ctxt.vf_num = 0;
6923 ctxt.uplink_seid = vsi->uplink_seid;
6924 ctxt.connection_type = 0x1; /* regular data port */
6925 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 6926 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 6927 break;
6928
6929 case I40E_VSI_VMDQ2:
6930 ctxt.pf_num = hw->pf_id;
6931 ctxt.vf_num = 0;
6932 ctxt.uplink_seid = vsi->uplink_seid;
6933 ctxt.connection_type = 0x1; /* regular data port */
6934 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6935
6936 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6937
6938 /* This VSI is connected to VEB so the switch_id
6939 * should be set to zero by default.
6940 */
6941 ctxt.info.switch_id = 0;
6942 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6943 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6944
6945 /* Setup the VSI tx/rx queue map for TC0 only for now */
6946 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6947 break;
6948
6949 case I40E_VSI_SRIOV:
6950 ctxt.pf_num = hw->pf_id;
6951 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6952 ctxt.uplink_seid = vsi->uplink_seid;
6953 ctxt.connection_type = 0x1; /* regular data port */
6954 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6955
6956 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6957
6958 /* This VSI is connected to VEB so the switch_id
6959 * should be set to zero by default.
6960 */
6961 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6962
6963 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6964 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6965 /* Setup the VSI tx/rx queue map for TC0 only for now */
6966 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6967 break;
6968
6969 default:
6970 return -ENODEV;
6971 }
6972
6973 if (vsi->type != I40E_VSI_MAIN) {
6974 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6975 if (ret) {
6976 dev_info(&vsi->back->pdev->dev,
6977 "add vsi failed, aq_err=%d\n",
6978 vsi->back->hw.aq.asq_last_status);
6979 ret = -ENOENT;
6980 goto err;
6981 }
6982 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6983 vsi->info.valid_sections = 0;
6984 vsi->seid = ctxt.seid;
6985 vsi->id = ctxt.vsi_number;
6986 }
6987
6988 /* If macvlan filters already exist, force them to get loaded */
6989 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6990 f->changed = true;
6991 f_count++;
6992 }
6993 if (f_count) {
6994 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6995 pf->flags |= I40E_FLAG_FILTER_SYNC;
6996 }
6997
6998 /* Update VSI BW information */
6999 ret = i40e_vsi_get_bw_info(vsi);
7000 if (ret) {
7001 dev_info(&pf->pdev->dev,
7002 "couldn't get vsi bw info, err %d, aq_err %d\n",
7003 ret, pf->hw.aq.asq_last_status);
7004 /* VSI is already added so not tearing that up */
7005 ret = 0;
7006 }
7007
7008err:
7009 return ret;
7010}
7011
7012/**
7013 * i40e_vsi_release - Delete a VSI and free its resources
7014 * @vsi: the VSI being removed
7015 *
7016 * Returns 0 on success or < 0 on error
7017 **/
7018int i40e_vsi_release(struct i40e_vsi *vsi)
7019{
7020 struct i40e_mac_filter *f, *ftmp;
7021 struct i40e_veb *veb = NULL;
7022 struct i40e_pf *pf;
7023 u16 uplink_seid;
7024 int i, n;
7025
7026 pf = vsi->back;
7027
7028 /* release of a VEB-owner or last VSI is not allowed */
7029 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7030 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7031 vsi->seid, vsi->uplink_seid);
7032 return -ENODEV;
7033 }
7034 if (vsi == pf->vsi[pf->lan_vsi] &&
7035 !test_bit(__I40E_DOWN, &pf->state)) {
7036 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7037 return -ENODEV;
7038 }
7039
7040 uplink_seid = vsi->uplink_seid;
7041 if (vsi->type != I40E_VSI_SRIOV) {
7042 if (vsi->netdev_registered) {
7043 vsi->netdev_registered = false;
7044 if (vsi->netdev) {
7045 /* results in a call to i40e_close() */
7046 unregister_netdev(vsi->netdev);
41c445ff
JB		 7047 }
7048 } else {
90ef8d47 7049 i40e_vsi_close(vsi);
41c445ff
JB		 7050 }
7051 i40e_vsi_disable_irq(vsi);
7052 }
7053
7054 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7055 i40e_del_filter(vsi, f->macaddr, f->vlan,
7056 f->is_vf, f->is_netdev);
7057 i40e_sync_vsi_filters(vsi);
7058
7059 i40e_vsi_delete(vsi);
7060 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7061 if (vsi->netdev) {
7062 free_netdev(vsi->netdev);
7063 vsi->netdev = NULL;
7064 }
41c445ff
JB		 7065 i40e_vsi_clear_rings(vsi);
7066 i40e_vsi_clear(vsi);
7067
7068 /* If this was the last thing on the VEB, except for the
7069 * controlling VSI, remove the VEB, which puts the controlling
7070 * VSI onto the next level down in the switch.
7071 *
7072 * Well, okay, there's one more exception here: don't remove
7073 * the orphan VEBs yet. We'll wait for an explicit remove request
7074 * from up the network stack.
7075 */
7076 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7077 if (pf->vsi[i] &&
7078 pf->vsi[i]->uplink_seid == uplink_seid &&
7079 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7080 n++; /* count the VSIs */
7081 }
7082 }
7083 for (i = 0; i < I40E_MAX_VEB; i++) {
7084 if (!pf->veb[i])
7085 continue;
7086 if (pf->veb[i]->uplink_seid == uplink_seid)
7087 n++; /* count the VEBs */
7088 if (pf->veb[i]->seid == uplink_seid)
7089 veb = pf->veb[i];
7090 }
7091 if (n == 0 && veb && veb->uplink_seid != 0)
7092 i40e_veb_release(veb);
7093
7094 return 0;
7095}
7096
7097/**
7098 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7099 * @vsi: ptr to the VSI
7100 *
7101 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7102 * corresponding SW VSI structure and initializes num_queue_pairs for the
7103 * newly allocated VSI.
7104 *
7105 * Returns 0 on success or negative on failure
7106 **/
7107static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7108{
7109 int ret = -ENOENT;
7110 struct i40e_pf *pf = vsi->back;
7111
493fb300 7112 if (vsi->q_vectors[0]) {
41c445ff
JB		 7113 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7114 vsi->seid);
7115 return -EEXIST;
7116 }
7117
7118 if (vsi->base_vector) {
f29eaa3d 7119 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7120 vsi->seid, vsi->base_vector);
7121 return -EEXIST;
7122 }
7123
90e04070 7124 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7125 if (ret) {
7126 dev_info(&pf->pdev->dev,
7127 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7128 vsi->num_q_vectors, vsi->seid, ret);
7129 vsi->num_q_vectors = 0;
7130 goto vector_setup_out;
7131 }
7132
958a3e3b
SN		 7133 if (vsi->num_q_vectors)
7134 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7135 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7136 if (vsi->base_vector < 0) {
7137 dev_info(&pf->pdev->dev,
f29eaa3d 7138 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7139 vsi->seid, vsi->base_vector);
7140 i40e_vsi_free_q_vectors(vsi);
7141 ret = -ENOENT;
7142 goto vector_setup_out;
7143 }
7144
7145vector_setup_out:
7146 return ret;
7147}
7148
bc7d338f
ASJ		 7149/**
7150 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7151 * @vsi: pointer to the vsi.
7152 *
7153 * This re-allocates a vsi's queue resources.
7154 *
7155 * Returns pointer to the successfully allocated and configured VSI sw struct
7156 * on success, otherwise returns NULL on failure.
7157 **/
7158static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7159{
7160 struct i40e_pf *pf = vsi->back;
7161 u8 enabled_tc;
7162 int ret;
7163
7164 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7165 i40e_vsi_clear_rings(vsi);
7166
7167 i40e_vsi_free_arrays(vsi, false);
7168 i40e_set_num_rings_in_vsi(vsi);
7169 ret = i40e_vsi_alloc_arrays(vsi, false);
7170 if (ret)
7171 goto err_vsi;
7172
7173 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7174 if (ret < 0) {
7175 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7176 vsi->seid, ret);
7177 goto err_vsi;
7178 }
7179 vsi->base_queue = ret;
7180
7181 /* Update the FW view of the VSI. Force a reset of TC and queue
7182 * layout configurations.
7183 */
7184 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7185 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7186 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7187 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7188
7189 /* assign it some queues */
7190 ret = i40e_alloc_rings(vsi);
7191 if (ret)
7192 goto err_rings;
7193
7194 /* map all of the rings to the q_vectors */
7195 i40e_vsi_map_rings_to_vectors(vsi);
7196 return vsi;
7197
7198err_rings:
7199 i40e_vsi_free_q_vectors(vsi);
7200 if (vsi->netdev_registered) {
7201 vsi->netdev_registered = false;
7202 unregister_netdev(vsi->netdev);
7203 free_netdev(vsi->netdev);
7204 vsi->netdev = NULL;
7205 }
7206 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7207err_vsi:
7208 i40e_vsi_clear(vsi);
7209 return NULL;
7210}
7211
41c445ff
JB		 7212/**
7213 * i40e_vsi_setup - Set up a VSI by a given type
7214 * @pf: board private structure
7215 * @type: VSI type
7216 * @uplink_seid: the switch element to link to
7217 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7218 *
7219 * This allocates the sw VSI structure and its queue resources, then add a VSI
7220 * to the identified VEB.
7221 *
7222 * Returns pointer to the successfully allocated and configure VSI sw struct on
7223 * success, otherwise returns NULL on failure.
7224 **/
7225struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7226 u16 uplink_seid, u32 param1)
7227{
7228 struct i40e_vsi *vsi = NULL;
7229 struct i40e_veb *veb = NULL;
7230 int ret, i;
7231 int v_idx;
7232
7233 /* The requested uplink_seid must be either
7234 * - the PF's port seid
7235 * no VEB is needed because this is the PF
7236 * or this is a Flow Director special case VSI
7237 * - seid of an existing VEB
7238 * - seid of a VSI that owns an existing VEB
7239 * - seid of a VSI that doesn't own a VEB
7240 * a new VEB is created and the VSI becomes the owner
7241 * - seid of the PF VSI, which is what creates the first VEB
7242 * this is a special case of the previous
7243 *
7244 * Find which uplink_seid we were given and create a new VEB if needed
7245 */
7246 for (i = 0; i < I40E_MAX_VEB; i++) {
7247 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7248 veb = pf->veb[i];
7249 break;
7250 }
7251 }
7252
7253 if (!veb && uplink_seid != pf->mac_seid) {
7254
7255 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7256 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7257 vsi = pf->vsi[i];
7258 break;
7259 }
7260 }
7261 if (!vsi) {
7262 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7263 uplink_seid);
7264 return NULL;
7265 }
7266
7267 if (vsi->uplink_seid == pf->mac_seid)
7268 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7269 vsi->tc_config.enabled_tc);
7270 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7271 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7272 vsi->tc_config.enabled_tc);
7273
7274 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7275 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7276 veb = pf->veb[i];
7277 }
7278 if (!veb) {
7279 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7280 return NULL;
7281 }
7282
7283 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7284 uplink_seid = veb->seid;
7285 }
7286
7287 /* get vsi sw struct */
7288 v_idx = i40e_vsi_mem_alloc(pf, type);
7289 if (v_idx < 0)
7290 goto err_alloc;
7291 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7292 if (!vsi)
7293 goto err_alloc;
41c445ff
JB		 7294 vsi->type = type;
7295 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7296
7297 if (type == I40E_VSI_MAIN)
7298 pf->lan_vsi = v_idx;
7299 else if (type == I40E_VSI_SRIOV)
7300 vsi->vf_id = param1;
7301 /* assign it some queues */
cbf61325
ASJ		 7302 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7303 vsi->idx);
41c445ff
JB		 7304 if (ret < 0) {
7305 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7306 vsi->seid, ret);
7307 goto err_vsi;
7308 }
7309 vsi->base_queue = ret;
7310
7311 /* get a VSI from the hardware */
7312 vsi->uplink_seid = uplink_seid;
7313 ret = i40e_add_vsi(vsi);
7314 if (ret)
7315 goto err_vsi;
7316
7317 switch (vsi->type) {
7318 /* setup the netdev if needed */
7319 case I40E_VSI_MAIN:
7320 case I40E_VSI_VMDQ2:
7321 ret = i40e_config_netdev(vsi);
7322 if (ret)
7323 goto err_netdev;
7324 ret = register_netdev(vsi->netdev);
7325 if (ret)
7326 goto err_netdev;
7327 vsi->netdev_registered = true;
7328 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7329#ifdef CONFIG_I40E_DCB
7330 /* Setup DCB netlink interface */
7331 i40e_dcbnl_setup(vsi);
7332#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7333 /* fall through */
7334
7335 case I40E_VSI_FDIR:
7336 /* set up vectors and rings if needed */
7337 ret = i40e_vsi_setup_vectors(vsi);
7338 if (ret)
7339 goto err_msix;
7340
7341 ret = i40e_alloc_rings(vsi);
7342 if (ret)
7343 goto err_rings;
7344
7345 /* map all of the rings to the q_vectors */
7346 i40e_vsi_map_rings_to_vectors(vsi);
7347
7348 i40e_vsi_reset_stats(vsi);
7349 break;
7350
7351 default:
7352 /* no netdev or rings for the other VSI types */
7353 break;
7354 }
7355
7356 return vsi;
7357
7358err_rings:
7359 i40e_vsi_free_q_vectors(vsi);
7360err_msix:
7361 if (vsi->netdev_registered) {
7362 vsi->netdev_registered = false;
7363 unregister_netdev(vsi->netdev);
7364 free_netdev(vsi->netdev);
7365 vsi->netdev = NULL;
7366 }
7367err_netdev:
7368 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7369err_vsi:
7370 i40e_vsi_clear(vsi);
7371err_alloc:
7372 return NULL;
7373}
7374
7375/**
7376 * i40e_veb_get_bw_info - Query VEB BW information
7377 * @veb: the veb to query
7378 *
7379 * Query the Tx scheduler BW configuration data for given VEB
7380 **/
7381static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7382{
7383 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7384 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7385 struct i40e_pf *pf = veb->pf;
7386 struct i40e_hw *hw = &pf->hw;
7387 u32 tc_bw_max;
7388 int ret = 0;
7389 int i;
7390
7391 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7392 &bw_data, NULL);
7393 if (ret) {
7394 dev_info(&pf->pdev->dev,
7395 "query veb bw config failed, aq_err=%d\n",
7396 hw->aq.asq_last_status);
7397 goto out;
7398 }
7399
7400 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7401 &ets_data, NULL);
7402 if (ret) {
7403 dev_info(&pf->pdev->dev,
7404 "query veb bw ets config failed, aq_err=%d\n",
7405 hw->aq.asq_last_status);
7406 goto out;
7407 }
7408
7409 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7410 veb->bw_max_quanta = ets_data.tc_bw_max;
7411 veb->is_abs_credits = bw_data.absolute_credits_enable;
7412 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7413 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7414 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7415 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7416 veb->bw_tc_limit_credits[i] =
7417 le16_to_cpu(bw_data.tc_bw_limits[i]);
7418 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7419 }
7420
7421out:
7422 return ret;
7423}
7424
7425/**
7426 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7427 * @pf: board private structure
7428 *
7429 * On error: returns error code (negative)
7430 * On success: returns vsi index in PF (positive)
7431 **/
7432static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7433{
7434 int ret = -ENOENT;
7435 struct i40e_veb *veb;
7436 int i;
7437
7438 /* Need to protect the allocation of switch elements at the PF level */
7439 mutex_lock(&pf->switch_mutex);
7440
7441 /* VEB list may be fragmented if VEB creation/destruction has
7442 * been happening. We can afford to do a quick scan to look
7443 * for any free slots in the list.
7444 *
7445 * find next empty veb slot, looping back around if necessary
7446 */
7447 i = 0;
7448 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7449 i++;
7450 if (i >= I40E_MAX_VEB) {
7451 ret = -ENOMEM;
7452 goto err_alloc_veb; /* out of VEB slots! */
7453 }
7454
7455 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7456 if (!veb) {
7457 ret = -ENOMEM;
7458 goto err_alloc_veb;
7459 }
7460 veb->pf = pf;
7461 veb->idx = i;
7462 veb->enabled_tc = 1;
7463
7464 pf->veb[i] = veb;
7465 ret = i;
7466err_alloc_veb:
7467 mutex_unlock(&pf->switch_mutex);
7468 return ret;
7469}
7470
7471/**
7472 * i40e_switch_branch_release - Delete a branch of the switch tree
7473 * @branch: where to start deleting
7474 *
7475 * This uses recursion to find the tips of the branch to be
7476 * removed, deleting until we get back to and can delete this VEB.
7477 **/
7478static void i40e_switch_branch_release(struct i40e_veb *branch)
7479{
7480 struct i40e_pf *pf = branch->pf;
7481 u16 branch_seid = branch->seid;
7482 u16 veb_idx = branch->idx;
7483 int i;
7484
7485 /* release any VEBs on this VEB - RECURSION */
7486 for (i = 0; i < I40E_MAX_VEB; i++) {
7487 if (!pf->veb[i])
7488 continue;
7489 if (pf->veb[i]->uplink_seid == branch->seid)
7490 i40e_switch_branch_release(pf->veb[i]);
7491 }
7492
7493 /* Release the VSIs on this VEB, but not the owner VSI.
7494 *
7495 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7496 * the VEB itself, so don't use (*branch) after this loop.
7497 */
7498 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7499 if (!pf->vsi[i])
7500 continue;
7501 if (pf->vsi[i]->uplink_seid == branch_seid &&
7502 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7503 i40e_vsi_release(pf->vsi[i]);
7504 }
7505 }
7506
7507 /* There's one corner case where the VEB might not have been
7508 * removed, so double check it here and remove it if needed.
7509 * This case happens if the veb was created from the debugfs
7510 * commands and no VSIs were added to it.
7511 */
7512 if (pf->veb[veb_idx])
7513 i40e_veb_release(pf->veb[veb_idx]);
7514}
7515
7516/**
7517 * i40e_veb_clear - remove veb struct
7518 * @veb: the veb to remove
7519 **/
7520static void i40e_veb_clear(struct i40e_veb *veb)
7521{
7522 if (!veb)
7523 return;
7524
7525 if (veb->pf) {
7526 struct i40e_pf *pf = veb->pf;
7527
7528 mutex_lock(&pf->switch_mutex);
7529 if (pf->veb[veb->idx] == veb)
7530 pf->veb[veb->idx] = NULL;
7531 mutex_unlock(&pf->switch_mutex);
7532 }
7533
7534 kfree(veb);
7535}
7536
7537/**
7538 * i40e_veb_release - Delete a VEB and free its resources
7539 * @veb: the VEB being removed
7540 **/
7541void i40e_veb_release(struct i40e_veb *veb)
7542{
7543 struct i40e_vsi *vsi = NULL;
7544 struct i40e_pf *pf;
7545 int i, n = 0;
7546
7547 pf = veb->pf;
7548
7549 /* find the remaining VSI and check for extras */
7550 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7551 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7552 n++;
7553 vsi = pf->vsi[i];
7554 }
7555 }
7556 if (n != 1) {
7557 dev_info(&pf->pdev->dev,
7558 "can't remove VEB %d with %d VSIs left\n",
7559 veb->seid, n);
7560 return;
7561 }
7562
7563 /* move the remaining VSI to uplink veb */
7564 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7565 if (veb->uplink_seid) {
7566 vsi->uplink_seid = veb->uplink_seid;
7567 if (veb->uplink_seid == pf->mac_seid)
7568 vsi->veb_idx = I40E_NO_VEB;
7569 else
7570 vsi->veb_idx = veb->veb_idx;
7571 } else {
7572 /* floating VEB */
7573 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7574 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7575 }
7576
7577 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7578 i40e_veb_clear(veb);
7579
7580 return;
7581}
7582
7583/**
7584 * i40e_add_veb - create the VEB in the switch
7585 * @veb: the VEB to be instantiated
7586 * @vsi: the controlling VSI
7587 **/
7588static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7589{
56747264 7590 bool is_default = false;
e1c51b95 7591 bool is_cloud = false;
41c445ff
JB		 7592 int ret;
7593
7594 /* get a VEB from the hardware */
7595 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7596 veb->enabled_tc, is_default,
7597 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7598 if (ret) {
7599 dev_info(&veb->pf->pdev->dev,
7600 "couldn't add VEB, err %d, aq_err %d\n",
7601 ret, veb->pf->hw.aq.asq_last_status);
7602 return -EPERM;
7603 }
7604
7605 /* get statistics counter */
7606 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7607 &veb->stats_idx, NULL, NULL, NULL);
7608 if (ret) {
7609 dev_info(&veb->pf->pdev->dev,
7610 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7611 ret, veb->pf->hw.aq.asq_last_status);
7612 return -EPERM;
7613 }
7614 ret = i40e_veb_get_bw_info(veb);
7615 if (ret) {
7616 dev_info(&veb->pf->pdev->dev,
7617 "couldn't get VEB bw info, err %d, aq_err %d\n",
7618 ret, veb->pf->hw.aq.asq_last_status);
7619 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7620 return -ENOENT;
7621 }
7622
7623 vsi->uplink_seid = veb->seid;
7624 vsi->veb_idx = veb->idx;
7625 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7626
7627 return 0;
7628}
7629
7630/**
7631 * i40e_veb_setup - Set up a VEB
7632 * @pf: board private structure
7633 * @flags: VEB setup flags
7634 * @uplink_seid: the switch element to link to
7635 * @vsi_seid: the initial VSI seid
7636 * @enabled_tc: Enabled TC bit-map
7637 *
7638 * This allocates the sw VEB structure and links it into the switch
7639 * It is possible and legal for this to be a duplicate of an already
7640 * existing VEB. It is also possible for both uplink and vsi seids
7641 * to be zero, in order to create a floating VEB.
7642 *
7643 * Returns pointer to the successfully allocated VEB sw struct on
7644 * success, otherwise returns NULL on failure.
7645 **/
7646struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7647 u16 uplink_seid, u16 vsi_seid,
7648 u8 enabled_tc)
7649{
7650 struct i40e_veb *veb, *uplink_veb = NULL;
7651 int vsi_idx, veb_idx;
7652 int ret;
7653
7654 /* if one seid is 0, the other must be 0 to create a floating relay */
7655 if ((uplink_seid == 0 || vsi_seid == 0) &&
7656 (uplink_seid + vsi_seid != 0)) {
7657 dev_info(&pf->pdev->dev,
7658 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7659 uplink_seid, vsi_seid);
7660 return NULL;
7661 }
7662
7663 /* make sure there is such a vsi and uplink */
7664 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7665 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7666 break;
7667 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7668 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7669 vsi_seid);
7670 return NULL;
7671 }
7672
7673 if (uplink_seid && uplink_seid != pf->mac_seid) {
7674 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7675 if (pf->veb[veb_idx] &&
7676 pf->veb[veb_idx]->seid == uplink_seid) {
7677 uplink_veb = pf->veb[veb_idx];
7678 break;
7679 }
7680 }
7681 if (!uplink_veb) {
7682 dev_info(&pf->pdev->dev,
7683 "uplink seid %d not found\n", uplink_seid);
7684 return NULL;
7685 }
7686 }
7687
7688 /* get veb sw struct */
7689 veb_idx = i40e_veb_mem_alloc(pf);
7690 if (veb_idx < 0)
7691 goto err_alloc;
7692 veb = pf->veb[veb_idx];
7693 veb->flags = flags;
7694 veb->uplink_seid = uplink_seid;
7695 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7696 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7697
7698 /* create the VEB in the switch */
7699 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7700 if (ret)
7701 goto err_veb;
7702
7703 return veb;
7704
7705err_veb:
7706 i40e_veb_clear(veb);
7707err_alloc:
7708 return NULL;
7709}
7710
7711/**
7712 * i40e_setup_pf_switch_element - set pf vars based on switch type
7713 * @pf: board private structure
7714 * @ele: element we are building info from
7715 * @num_reported: total number of elements
7716 * @printconfig: should we print the contents
7717 *
7718 * helper function to assist in extracting a few useful SEID values.
7719 **/
7720static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7721 struct i40e_aqc_switch_config_element_resp *ele,
7722 u16 num_reported, bool printconfig)
7723{
7724 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7725 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7726 u8 element_type = ele->element_type;
7727 u16 seid = le16_to_cpu(ele->seid);
7728
7729 if (printconfig)
7730 dev_info(&pf->pdev->dev,
7731 "type=%d seid=%d uplink=%d downlink=%d\n",
7732 element_type, seid, uplink_seid, downlink_seid);
7733
7734 switch (element_type) {
7735 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7736 pf->mac_seid = seid;
7737 break;
7738 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7739 /* Main VEB? */
7740 if (uplink_seid != pf->mac_seid)
7741 break;
7742 if (pf->lan_veb == I40E_NO_VEB) {
7743 int v;
7744
7745 /* find existing or else empty VEB */
7746 for (v = 0; v < I40E_MAX_VEB; v++) {
7747 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7748 pf->lan_veb = v;
7749 break;
7750 }
7751 }
7752 if (pf->lan_veb == I40E_NO_VEB) {
7753 v = i40e_veb_mem_alloc(pf);
7754 if (v < 0)
7755 break;
7756 pf->lan_veb = v;
7757 }
7758 }
7759
7760 pf->veb[pf->lan_veb]->seid = seid;
7761 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7762 pf->veb[pf->lan_veb]->pf = pf;
7763 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7764 break;
7765 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7766 if (num_reported != 1)
7767 break;
7768 /* This is immediately after a reset so we can assume this is
7769 * the PF's VSI
7770 */
7771 pf->mac_seid = uplink_seid;
7772 pf->pf_seid = downlink_seid;
7773 pf->main_vsi_seid = seid;
7774 if (printconfig)
7775 dev_info(&pf->pdev->dev,
7776 "pf_seid=%d main_vsi_seid=%d\n",
7777 pf->pf_seid, pf->main_vsi_seid);
7778 break;
7779 case I40E_SWITCH_ELEMENT_TYPE_PF:
7780 case I40E_SWITCH_ELEMENT_TYPE_VF:
7781 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7782 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7783 case I40E_SWITCH_ELEMENT_TYPE_PE:
7784 case I40E_SWITCH_ELEMENT_TYPE_PA:
7785 /* ignore these for now */
7786 break;
7787 default:
7788 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7789 element_type, seid);
7790 break;
7791 }
7792}
7793
7794/**
7795 * i40e_fetch_switch_configuration - Get switch config from firmware
7796 * @pf: board private structure
7797 * @printconfig: should we print the contents
7798 *
7799 * Get the current switch configuration from the device and
7800 * extract a few useful SEID values.
7801 **/
7802int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7803{
7804 struct i40e_aqc_get_switch_config_resp *sw_config;
7805 u16 next_seid = 0;
7806 int ret = 0;
7807 u8 *aq_buf;
7808 int i;
7809
7810 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7811 if (!aq_buf)
7812 return -ENOMEM;
7813
7814 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7815 do {
7816 u16 num_reported, num_total;
7817
7818 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7819 I40E_AQ_LARGE_BUF,
7820 &next_seid, NULL);
7821 if (ret) {
7822 dev_info(&pf->pdev->dev,
7823 "get switch config failed %d aq_err=%x\n",
7824 ret, pf->hw.aq.asq_last_status);
7825 kfree(aq_buf);
7826 return -ENOENT;
7827 }
7828
7829 num_reported = le16_to_cpu(sw_config->header.num_reported);
7830 num_total = le16_to_cpu(sw_config->header.num_total);
7831
7832 if (printconfig)
7833 dev_info(&pf->pdev->dev,
7834 "header: %d reported %d total\n",
7835 num_reported, num_total);
7836
7837 if (num_reported) {
7838 int sz = sizeof(*sw_config) * num_reported;
7839
7840 kfree(pf->sw_config);
7841 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7842 if (pf->sw_config)
7843 memcpy(pf->sw_config, sw_config, sz);
7844 }
7845
7846 for (i = 0; i < num_reported; i++) {
7847 struct i40e_aqc_switch_config_element_resp *ele =
7848 &sw_config->element[i];
7849
7850 i40e_setup_pf_switch_element(pf, ele, num_reported,
7851 printconfig);
7852 }
7853 } while (next_seid != 0);
7854
7855 kfree(aq_buf);
7856 return ret;
7857}
7858
7859/**
7860 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7861 * @pf: board private structure
bc7d338f 7862 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7863 *
7864 * Returns 0 on success, negative value on failure
7865 **/
bc7d338f 7866static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7867{
895106a5 7868 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7869 int ret;
7870
7871 /* find out what's out there already */
7872 ret = i40e_fetch_switch_configuration(pf, false);
7873 if (ret) {
7874 dev_info(&pf->pdev->dev,
7875 "couldn't fetch switch config, err %d, aq_err %d\n",
7876 ret, pf->hw.aq.asq_last_status);
7877 return ret;
7878 }
7879 i40e_pf_reset_stats(pf);
7880
41c445ff 7881 /* first time setup */
bc7d338f 7882 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7883 struct i40e_vsi *vsi = NULL;
7884 u16 uplink_seid;
7885
7886 /* Set up the PF VSI associated with the PF's main VSI
7887 * that is already in the HW switch
7888 */
7889 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7890 uplink_seid = pf->veb[pf->lan_veb]->seid;
7891 else
7892 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7893 if (pf->lan_vsi == I40E_NO_VSI)
7894 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7895 else if (reinit)
7896 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7897 if (!vsi) {
7898 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7899 i40e_fdir_teardown(pf);
7900 return -EAGAIN;
7901 }
41c445ff
JB		 7902 } else {
7903 /* force a reset of TC and queue layout configurations */
7904 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7905 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7906 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7907 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7908 }
7909 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7910
cbf61325
ASJ		 7911 i40e_fdir_sb_setup(pf);
7912
41c445ff
JB		 7913 /* Setup static PF queue filter control settings */
7914 ret = i40e_setup_pf_filter_control(pf);
7915 if (ret) {
7916 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7917 ret);
7918 /* Failure here should not stop continuing other steps */
7919 }
7920
7921 /* enable RSS in the HW, even for only one queue, as the stack can use
7922 * the hash
7923 */
7924 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7925 i40e_config_rss(pf);
7926
7927 /* fill in link information and enable LSE reporting */
7928 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7929 i40e_link_event(pf);
7930
d52c20b7 7931 /* Initialize user-specific link properties */
41c445ff
JB		 7932 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7933 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7934 /* requested_mode is set in probe or by ethtool */
7935 if (!pf->fc_autoneg_status)
7936 goto no_autoneg;
7937
7938 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7939 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7940 pf->hw.fc.current_mode = I40E_FC_FULL;
7941 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7942 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7943 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7944 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7945 else
d52c20b7
JB		 7946 pf->hw.fc.current_mode = I40E_FC_NONE;
7947
7948 /* sync the flow control settings with the auto-neg values */
7949 switch (pf->hw.fc.current_mode) {
7950 case I40E_FC_FULL:
7951 txfc = 1;
7952 rxfc = 1;
7953 break;
7954 case I40E_FC_TX_PAUSE:
7955 txfc = 1;
7956 rxfc = 0;
7957 break;
7958 case I40E_FC_RX_PAUSE:
7959 txfc = 0;
7960 rxfc = 1;
7961 break;
7962 case I40E_FC_NONE:
7963 case I40E_FC_DEFAULT:
7964 txfc = 0;
7965 rxfc = 0;
7966 break;
7967 case I40E_FC_PFC:
7968 /* TBD */
7969 break;
7970 /* no default case, we have to handle all possibilities here */
7971 }
7972
7973 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7974
7975 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7976 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7977 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7978
7979 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7980
d52c20b7
JB		 7981 goto fc_complete;
7982
7983no_autoneg:
7984 /* disable L2 flow control, user can turn it on if they wish */
7985 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7986 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7987 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7988
7989fc_complete:
beb0dff1
JK		 7990 i40e_ptp_init(pf);
7991
41c445ff
JB		 7992 return ret;
7993}
7994
41c445ff
JB		 7995/**
7996 * i40e_determine_queue_usage - Work out queue distribution
7997 * @pf: board private structure
7998 **/
7999static void i40e_determine_queue_usage(struct i40e_pf *pf)
8000{
41c445ff
JB		 8001 int queues_left;
8002
8003 pf->num_lan_qps = 0;
41c445ff
JB		 8004
8005 /* Find the max queues to be put into basic use. We'll always be
8006 * using TC0, whether or not DCB is running, and TC0 will get the
8007 * big RSS set.
8008 */
8009 queues_left = pf->hw.func_caps.num_tx_qp;
8010
cbf61325
ASJ		 8011 if ((queues_left == 1) ||
8012 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8013 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8014 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8015 /* one qp for PF, no queues for anything else */
8016 queues_left = 0;
8017 pf->rss_size = pf->num_lan_qps = 1;
8018
8019 /* make sure all the fancies are disabled */
60ea5f83
JB		 8020 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8021 I40E_FLAG_FD_SB_ENABLED |
8022 I40E_FLAG_FD_ATR_ENABLED |
8023 I40E_FLAG_DCB_ENABLED |
8024 I40E_FLAG_SRIOV_ENABLED |
8025 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8026 } else {
cbf61325
ASJ		 8027 /* Not enough queues for all TCs */
8028 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8029 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8030 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8031 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8032 }
8033 pf->num_lan_qps = pf->rss_size_max;
8034 queues_left -= pf->num_lan_qps;
8035 }
8036
8037 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8038 if (queues_left > 1) {
8039 queues_left -= 1; /* save 1 queue for FD */
8040 } else {
8041 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8042 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8043 }
41c445ff
JB		 8044 }
8045
8046 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8047 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8048 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8049 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8050 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8051 }
8052
8053 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8054 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8055 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8056 (queues_left / pf->num_vmdq_qps));
8057 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8058 }
8059
f8ff1464 8060 pf->queues_left = queues_left;
41c445ff
JB		 8061 return;
8062}
8063
8064/**
8065 * i40e_setup_pf_filter_control - Setup PF static filter control
8066 * @pf: PF to be setup
8067 *
8068 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8069 * settings. If PE/FCoE are enabled then it will also set the per PF
8070 * based filter sizes required for them. It also enables Flow director,
8071 * ethertype and macvlan type filter settings for the pf.
8072 *
8073 * Returns 0 on success, negative on failure
8074 **/
8075static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8076{
8077 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8078
8079 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8080
8081 /* Flow Director is enabled */
60ea5f83 8082 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8083 settings->enable_fdir = true;
8084
8085 /* Ethtype and MACVLAN filters enabled for PF */
8086 settings->enable_ethtype = true;
8087 settings->enable_macvlan = true;
8088
8089 if (i40e_set_filter_control(&pf->hw, settings))
8090 return -ENOENT;
8091
8092 return 0;
8093}
8094
0c22b3dd
JB		 8095#define INFO_STRING_LEN 255
8096static void i40e_print_features(struct i40e_pf *pf)
8097{
8098 struct i40e_hw *hw = &pf->hw;
8099 char *buf, *string;
8100
8101 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8102 if (!string) {
8103 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8104 return;
8105 }
8106
8107 buf = string;
8108
8109 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8110#ifdef CONFIG_PCI_IOV
8111 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8112#endif
8113 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8114 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8115
8116 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8117 buf += sprintf(buf, "RSS ");
8118 buf += sprintf(buf, "FDir ");
8119 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
8120 buf += sprintf(buf, "ATR ");
8121 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
8122 buf += sprintf(buf, "NTUPLE ");
8123 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8124 buf += sprintf(buf, "DCB ");
8125 if (pf->flags & I40E_FLAG_PTP)
8126 buf += sprintf(buf, "PTP ");
8127
8128 BUG_ON(buf > (string + INFO_STRING_LEN));
8129 dev_info(&pf->pdev->dev, "%s\n", string);
8130 kfree(string);
8131}
8132
41c445ff
JB		 8133/**
8134 * i40e_probe - Device initialization routine
8135 * @pdev: PCI device information struct
8136 * @ent: entry in i40e_pci_tbl
8137 *
8138 * i40e_probe initializes a pf identified by a pci_dev structure.
8139 * The OS initialization, configuring of the pf private structure,
8140 * and a hardware reset occur.
8141 *
8142 * Returns 0 on success, negative on failure
8143 **/
8144static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8145{
8146 struct i40e_driver_version dv;
8147 struct i40e_pf *pf;
8148 struct i40e_hw *hw;
93cd765b 8149 static u16 pfs_found;
d4dfb81a 8150 u16 link_status;
41c445ff
JB		 8151 int err = 0;
8152 u32 len;
8a9eb7d3 8153 u32 i;
41c445ff
JB		 8154
8155 err = pci_enable_device_mem(pdev);
8156 if (err)
8157 return err;
8158
8159 /* set up for high or low dma */
6494294f 8160 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8161 if (err) {
e3e3bfdd
JS		 8162 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8163 if (err) {
8164 dev_err(&pdev->dev,
8165 "DMA configuration failed: 0x%x\n", err);
8166 goto err_dma;
8167 }
41c445ff
JB		 8168 }
8169
8170 /* set up pci connections */
8171 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8172 IORESOURCE_MEM), i40e_driver_name);
8173 if (err) {
8174 dev_info(&pdev->dev,
8175 "pci_request_selected_regions failed %d\n", err);
8176 goto err_pci_reg;
8177 }
8178
8179 pci_enable_pcie_error_reporting(pdev);
8180 pci_set_master(pdev);
8181
8182 /* Now that we have a PCI connection, we need to do the
8183 * low level device setup. This is primarily setting up
8184 * the Admin Queue structures and then querying for the
8185 * device's current profile information.
8186 */
8187 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8188 if (!pf) {
8189 err = -ENOMEM;
8190 goto err_pf_alloc;
8191 }
8192 pf->next_vsi = 0;
8193 pf->pdev = pdev;
8194 set_bit(__I40E_DOWN, &pf->state);
8195
8196 hw = &pf->hw;
8197 hw->back = pf;
8198 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8199 pci_resource_len(pdev, 0));
8200 if (!hw->hw_addr) {
8201 err = -EIO;
8202 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8203 (unsigned int)pci_resource_start(pdev, 0),
8204 (unsigned int)pci_resource_len(pdev, 0), err);
8205 goto err_ioremap;
8206 }
8207 hw->vendor_id = pdev->vendor;
8208 hw->device_id = pdev->device;
8209 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8210 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8211 hw->subsystem_device_id = pdev->subsystem_device;
8212 hw->bus.device = PCI_SLOT(pdev->devfn);
8213 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8214 pf->instance = pfs_found;
41c445ff 8215
7134f9ce
JB		 8216 /* do a special CORER for clearing PXE mode once at init */
8217 if (hw->revision_id == 0 &&
8218 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8219 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8220 i40e_flush(hw);
8221 msleep(200);
8222 pf->corer_count++;
8223
8224 i40e_clear_pxe_mode(hw);
8225 }
8226
41c445ff
JB		 8227 /* Reset here to make sure all is clean and to define PF 'n' */
8228 err = i40e_pf_reset(hw);
8229 if (err) {
8230 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8231 goto err_pf_reset;
8232 }
8233 pf->pfr_count++;
8234
8235 hw->aq.num_arq_entries = I40E_AQ_LEN;
8236 hw->aq.num_asq_entries = I40E_AQ_LEN;
8237 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8238 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8239 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8240 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8241 "%s-pf%d:misc",
8242 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8243
8244 err = i40e_init_shared_code(hw);
8245 if (err) {
8246 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8247 goto err_pf_reset;
8248 }
8249
d52c20b7
JB		 8250 /* set up a default setting for link flow control */
8251 pf->hw.fc.requested_mode = I40E_FC_NONE;
8252
41c445ff
JB		 8253 err = i40e_init_adminq(hw);
8254 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8255 if (err) {
8256 dev_info(&pdev->dev,
8257 "init_adminq failed: %d expecting API %02x.%02x\n",
8258 err,
8259 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8260 goto err_pf_reset;
8261 }
8262
4eb3f768
SN		 8263 i40e_verify_eeprom(pf);
8264
6ff4ef86 8265 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8266 err = i40e_get_capabilities(pf);
8267 if (err)
8268 goto err_adminq_setup;
8269
8270 err = i40e_sw_init(pf);
8271 if (err) {
8272 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8273 goto err_sw_init;
8274 }
8275
8276 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8277 hw->func_caps.num_rx_qp,
8278 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8279 if (err) {
8280 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8281 goto err_init_lan_hmc;
8282 }
8283
8284 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8285 if (err) {
8286 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8287 err = -ENOENT;
8288 goto err_configure_lan_hmc;
8289 }
8290
8291 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8292 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8293 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8294 err = -EIO;
8295 goto err_mac_addr;
8296 }
8297 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8298 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8299
8300 pci_set_drvdata(pdev, pf);
8301 pci_save_state(pdev);
4e3b35b0
NP		 8302#ifdef CONFIG_I40E_DCB
8303 err = i40e_init_pf_dcb(pf);
8304 if (err) {
8305 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8306 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
014269ff 8307 /* Continue without DCB enabled */
4e3b35b0
NP		 8308 }
8309#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8310
8311 /* set up periodic task facility */
8312 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8313 pf->service_timer_period = HZ;
8314
8315 INIT_WORK(&pf->service_task, i40e_service_task);
8316 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8317 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8318 pf->link_check_timeout = jiffies;
8319
8e2773ae
SN		 8320 /* WoL defaults to disabled */
8321 pf->wol_en = false;
8322 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8323
41c445ff
JB		 8324 /* set up the main switch operations */
8325 i40e_determine_queue_usage(pf);
8326 i40e_init_interrupt_scheme(pf);
8327
8328 /* Set up the *vsi struct based on the number of VSIs in the HW,
8329 * and set up our local tracking of the MAIN PF vsi.
8330 */
8331 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
8332 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8333 if (!pf->vsi) {
8334 err = -ENOMEM;
41c445ff 8335 goto err_switch_setup;
ed87ac09 8336 }
41c445ff 8337
bc7d338f 8338 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8339 if (err) {
8340 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8341 goto err_vsis;
8342 }
8a9eb7d3
SN		 8343 /* if FDIR VSI was set up, start it now */
8344 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8345 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8346 i40e_vsi_open(pf->vsi[i]);
8347 break;
8348 }
8349 }
41c445ff
JB		 8350
8351 /* The main driver is (mostly) up and happy. We need to set this state
8352 * before setting up the misc vector or we get a race and the vector
8353 * ends up disabled forever.
8354 */
8355 clear_bit(__I40E_DOWN, &pf->state);
8356
8357 /* In case of MSIX we are going to setup the misc vector right here
8358 * to handle admin queue events etc. In case of legacy and MSI
8359 * the misc functionality and queue processing is combined in
8360 * the same vector and that gets setup at open.
8361 */
8362 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8363 err = i40e_setup_misc_vector(pf);
8364 if (err) {
8365 dev_info(&pdev->dev,
8366 "setup of misc vector failed: %d\n", err);
8367 goto err_vsis;
8368 }
8369 }
8370
8371 /* prep for VF support */
8372 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8373 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8374 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8375 u32 val;
8376
8377 /* disable link interrupts for VFs */
8378 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8379 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8380 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8381 i40e_flush(hw);
4aeec010
MW		 8382
8383 if (pci_num_vf(pdev)) {
8384 dev_info(&pdev->dev,
8385 "Active VFs found, allocating resources.\n");
8386 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8387 if (err)
8388 dev_info(&pdev->dev,
8389 "Error %d allocating resources for existing VFs\n",
8390 err);
8391 }
41c445ff
JB		 8392 }
8393
93cd765b
ASJ		 8394 pfs_found++;
8395
41c445ff
JB		 8396 i40e_dbg_pf_init(pf);
8397
8398 /* tell the firmware that we're starting */
8399 dv.major_version = DRV_VERSION_MAJOR;
8400 dv.minor_version = DRV_VERSION_MINOR;
8401 dv.build_version = DRV_VERSION_BUILD;
8402 dv.subbuild_version = 0;
d2466013 8403 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
41c445ff
JB		 8404 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
8405
8406 /* since everything's happy, start the service_task timer */
8407 mod_timer(&pf->service_timer,
8408 round_jiffies(jiffies + pf->service_timer_period));
8409
d4dfb81a
CS		 8410 /* Get the negotiated link width and speed from PCI config space */
8411 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8412
8413 i40e_set_pci_config_data(hw, link_status);
8414
69bfb110 8415 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8416 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8417 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8418 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8419 "Unknown"),
8420 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8421 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8422 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8423 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8424 "Unknown"));
8425
8426 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8427 hw->bus.speed < i40e_bus_speed_8000) {
8428 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8429 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8430 }
8431
0c22b3dd
JB		 8432 /* print a string summarizing features */
8433 i40e_print_features(pf);
8434
41c445ff
JB		 8435 return 0;
8436
8437 /* Unwind what we've done if something failed in the setup */
8438err_vsis:
8439 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8440 i40e_clear_interrupt_scheme(pf);
8441 kfree(pf->vsi);
04b03013
SN		 8442err_switch_setup:
8443 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8444 del_timer_sync(&pf->service_timer);
8445err_mac_addr:
8446err_configure_lan_hmc:
8447 (void)i40e_shutdown_lan_hmc(hw);
8448err_init_lan_hmc:
8449 kfree(pf->qp_pile);
8450 kfree(pf->irq_pile);
8451err_sw_init:
8452err_adminq_setup:
8453 (void)i40e_shutdown_adminq(hw);
8454err_pf_reset:
8455 iounmap(hw->hw_addr);
8456err_ioremap:
8457 kfree(pf);
8458err_pf_alloc:
8459 pci_disable_pcie_error_reporting(pdev);
8460 pci_release_selected_regions(pdev,
8461 pci_select_bars(pdev, IORESOURCE_MEM));
8462err_pci_reg:
8463err_dma:
8464 pci_disable_device(pdev);
8465 return err;
8466}
8467
8468/**
8469 * i40e_remove - Device removal routine
8470 * @pdev: PCI device information struct
8471 *
8472 * i40e_remove is called by the PCI subsystem to alert the driver
8473 * that is should release a PCI device. This could be caused by a
8474 * Hot-Plug event, or because the driver is going to be removed from
8475 * memory.
8476 **/
8477static void i40e_remove(struct pci_dev *pdev)
8478{
8479 struct i40e_pf *pf = pci_get_drvdata(pdev);
8480 i40e_status ret_code;
8481 u32 reg;
8482 int i;
8483
8484 i40e_dbg_pf_exit(pf);
8485
beb0dff1
JK		 8486 i40e_ptp_stop(pf);
8487
41c445ff
JB		 8488 /* no more scheduling of any task */
8489 set_bit(__I40E_DOWN, &pf->state);
8490 del_timer_sync(&pf->service_timer);
8491 cancel_work_sync(&pf->service_task);
8492
eb2d80bc
MW		 8493 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8494 i40e_free_vfs(pf);
8495 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8496 }
8497
41c445ff
JB		 8498 i40e_fdir_teardown(pf);
8499
8500 /* If there is a switch structure or any orphans, remove them.
8501 * This will leave only the PF's VSI remaining.
8502 */
8503 for (i = 0; i < I40E_MAX_VEB; i++) {
8504 if (!pf->veb[i])
8505 continue;
8506
8507 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8508 pf->veb[i]->uplink_seid == 0)
8509 i40e_switch_branch_release(pf->veb[i]);
8510 }
8511
8512 /* Now we can shutdown the PF's VSI, just before we kill
8513 * adminq and hmc.
8514 */
8515 if (pf->vsi[pf->lan_vsi])
8516 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8517
8518 i40e_stop_misc_vector(pf);
8519 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8520 synchronize_irq(pf->msix_entries[0].vector);
8521 free_irq(pf->msix_entries[0].vector, pf);
8522 }
8523
8524 /* shutdown and destroy the HMC */
8525 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8526 if (ret_code)
8527 dev_warn(&pdev->dev,
8528 "Failed to destroy the HMC resources: %d\n", ret_code);
8529
8530 /* shutdown the adminq */
41c445ff
JB		 8531 ret_code = i40e_shutdown_adminq(&pf->hw);
8532 if (ret_code)
8533 dev_warn(&pdev->dev,
8534 "Failed to destroy the Admin Queue resources: %d\n",
8535 ret_code);
8536
8537 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8538 i40e_clear_interrupt_scheme(pf);
8539 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
8540 if (pf->vsi[i]) {
8541 i40e_vsi_clear_rings(pf->vsi[i]);
8542 i40e_vsi_clear(pf->vsi[i]);
8543 pf->vsi[i] = NULL;
8544 }
8545 }
8546
8547 for (i = 0; i < I40E_MAX_VEB; i++) {
8548 kfree(pf->veb[i]);
8549 pf->veb[i] = NULL;
8550 }
8551
8552 kfree(pf->qp_pile);
8553 kfree(pf->irq_pile);
8554 kfree(pf->sw_config);
8555 kfree(pf->vsi);
8556
8557 /* force a PF reset to clean anything leftover */
8558 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8559 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8560 i40e_flush(&pf->hw);
8561
8562 iounmap(pf->hw.hw_addr);
8563 kfree(pf);
8564 pci_release_selected_regions(pdev,
8565 pci_select_bars(pdev, IORESOURCE_MEM));
8566
8567 pci_disable_pcie_error_reporting(pdev);
8568 pci_disable_device(pdev);
8569}
8570
8571/**
8572 * i40e_pci_error_detected - warning that something funky happened in PCI land
8573 * @pdev: PCI device information struct
8574 *
8575 * Called to warn that something happened and the error handling steps
8576 * are in progress. Allows the driver to quiesce things, be ready for
8577 * remediation.
8578 **/
8579static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8580 enum pci_channel_state error)
8581{
8582 struct i40e_pf *pf = pci_get_drvdata(pdev);
8583
8584 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8585
8586 /* shutdown all operations */
9007bccd
SN		 8587 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8588 rtnl_lock();
8589 i40e_prep_for_reset(pf);
8590 rtnl_unlock();
8591 }
41c445ff
JB		 8592
8593 /* Request a slot reset */
8594 return PCI_ERS_RESULT_NEED_RESET;
8595}
8596
8597/**
8598 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8599 * @pdev: PCI device information struct
8600 *
8601 * Called to find if the driver can work with the device now that
8602 * the pci slot has been reset. If a basic connection seems good
8603 * (registers are readable and have sane content) then return a
8604 * happy little PCI_ERS_RESULT_xxx.
8605 **/
8606static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8607{
8608 struct i40e_pf *pf = pci_get_drvdata(pdev);
8609 pci_ers_result_t result;
8610 int err;
8611 u32 reg;
8612
8613 dev_info(&pdev->dev, "%s\n", __func__);
8614 if (pci_enable_device_mem(pdev)) {
8615 dev_info(&pdev->dev,
8616 "Cannot re-enable PCI device after reset.\n");
8617 result = PCI_ERS_RESULT_DISCONNECT;
8618 } else {
8619 pci_set_master(pdev);
8620 pci_restore_state(pdev);
8621 pci_save_state(pdev);
8622 pci_wake_from_d3(pdev, false);
8623
8624 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8625 if (reg == 0)
8626 result = PCI_ERS_RESULT_RECOVERED;
8627 else
8628 result = PCI_ERS_RESULT_DISCONNECT;
8629 }
8630
8631 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8632 if (err) {
8633 dev_info(&pdev->dev,
8634 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8635 err);
8636 /* non-fatal, continue */
8637 }
8638
8639 return result;
8640}
8641
8642/**
8643 * i40e_pci_error_resume - restart operations after PCI error recovery
8644 * @pdev: PCI device information struct
8645 *
8646 * Called to allow the driver to bring things back up after PCI error
8647 * and/or reset recovery has finished.
8648 **/
8649static void i40e_pci_error_resume(struct pci_dev *pdev)
8650{
8651 struct i40e_pf *pf = pci_get_drvdata(pdev);
8652
8653 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8654 if (test_bit(__I40E_SUSPENDED, &pf->state))
8655 return;
8656
8657 rtnl_lock();
41c445ff 8658 i40e_handle_reset_warning(pf);
9007bccd
SN		 8659 rtnl_lock();
8660}
8661
8662/**
8663 * i40e_shutdown - PCI callback for shutting down
8664 * @pdev: PCI device information struct
8665 **/
8666static void i40e_shutdown(struct pci_dev *pdev)
8667{
8668 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8669 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8670
8671 set_bit(__I40E_SUSPENDED, &pf->state);
8672 set_bit(__I40E_DOWN, &pf->state);
8673 rtnl_lock();
8674 i40e_prep_for_reset(pf);
8675 rtnl_unlock();
8676
8e2773ae
SN		 8677 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8678 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8679
9007bccd 8680 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8681 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8682 pci_set_power_state(pdev, PCI_D3hot);
8683 }
8684}
8685
8686#ifdef CONFIG_PM
8687/**
8688 * i40e_suspend - PCI callback for moving to D3
8689 * @pdev: PCI device information struct
8690 **/
8691static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8692{
8693 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8694 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8695
8696 set_bit(__I40E_SUSPENDED, &pf->state);
8697 set_bit(__I40E_DOWN, &pf->state);
8698 rtnl_lock();
8699 i40e_prep_for_reset(pf);
8700 rtnl_unlock();
8701
8e2773ae
SN		 8702 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8703 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8704
8705 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8706 pci_set_power_state(pdev, PCI_D3hot);
8707
8708 return 0;
41c445ff
JB		 8709}
8710
9007bccd
SN		 8711/**
8712 * i40e_resume - PCI callback for waking up from D3
8713 * @pdev: PCI device information struct
8714 **/
8715static int i40e_resume(struct pci_dev *pdev)
8716{
8717 struct i40e_pf *pf = pci_get_drvdata(pdev);
8718 u32 err;
8719
8720 pci_set_power_state(pdev, PCI_D0);
8721 pci_restore_state(pdev);
8722 /* pci_restore_state() clears dev->state_saves, so
8723 * call pci_save_state() again to restore it.
8724 */
8725 pci_save_state(pdev);
8726
8727 err = pci_enable_device_mem(pdev);
8728 if (err) {
8729 dev_err(&pdev->dev,
8730 "%s: Cannot enable PCI device from suspend\n",
8731 __func__);
8732 return err;
8733 }
8734 pci_set_master(pdev);
8735
8736 /* no wakeup events while running */
8737 pci_wake_from_d3(pdev, false);
8738
8739 /* handling the reset will rebuild the device state */
8740 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8741 clear_bit(__I40E_DOWN, &pf->state);
8742 rtnl_lock();
8743 i40e_reset_and_rebuild(pf, false);
8744 rtnl_unlock();
8745 }
8746
8747 return 0;
8748}
8749
8750#endif
41c445ff
JB		 8751static const struct pci_error_handlers i40e_err_handler = {
8752 .error_detected = i40e_pci_error_detected,
8753 .slot_reset = i40e_pci_error_slot_reset,
8754 .resume = i40e_pci_error_resume,
8755};
8756
8757static struct pci_driver i40e_driver = {
8758 .name = i40e_driver_name,
8759 .id_table = i40e_pci_tbl,
8760 .probe = i40e_probe,
8761 .remove = i40e_remove,
9007bccd
SN		 8762#ifdef CONFIG_PM
8763 .suspend = i40e_suspend,
8764 .resume = i40e_resume,
8765#endif
8766 .shutdown = i40e_shutdown,
41c445ff
JB		 8767 .err_handler = &i40e_err_handler,
8768 .sriov_configure = i40e_pci_sriov_configure,
8769};
8770
8771/**
8772 * i40e_init_module - Driver registration routine
8773 *
8774 * i40e_init_module is the first routine called when the driver is
8775 * loaded. All it does is register with the PCI subsystem.
8776 **/
8777static int __init i40e_init_module(void)
8778{
8779 pr_info("%s: %s - version %s\n", i40e_driver_name,
8780 i40e_driver_string, i40e_driver_version_str);
8781 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8782 i40e_dbg_init();
8783 return pci_register_driver(&i40e_driver);
8784}
8785module_init(i40e_init_module);
8786
8787/**
8788 * i40e_exit_module - Driver exit cleanup routine
8789 *
8790 * i40e_exit_module is called just before the driver is removed
8791 * from memory.
8792 **/
8793static void __exit i40e_exit_module(void)
8794{
8795 pci_unregister_driver(&i40e_driver);
8796 i40e_dbg_exit();
8797}
8798module_exit(i40e_exit_module);
Linux kernel - Deliverables
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