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i40e: make message meaningful
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
a1c9a9d9
JK		 29#ifdef CONFIG_I40E_VXLAN
30#include <net/vxlan.h>
31#endif
41c445ff
JB		 32
33const char i40e_driver_name[] = "i40e";
34static const char i40e_driver_string[] =
35 "Intel(R) Ethernet Connection XL710 Network Driver";
36
37#define DRV_KERN "-k"
38
39#define DRV_VERSION_MAJOR 0
40#define DRV_VERSION_MINOR 3
3029ff04 41#define DRV_VERSION_BUILD 28
41c445ff
JB		 42#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
43 __stringify(DRV_VERSION_MINOR) "." \
44 __stringify(DRV_VERSION_BUILD) DRV_KERN
45const char i40e_driver_version_str[] = DRV_VERSION;
46static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
47
48/* a bit of forward declarations */
49static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
50static void i40e_handle_reset_warning(struct i40e_pf *pf);
51static int i40e_add_vsi(struct i40e_vsi *vsi);
52static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 53static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 54static int i40e_setup_misc_vector(struct i40e_pf *pf);
55static void i40e_determine_queue_usage(struct i40e_pf *pf);
56static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
57
58/* i40e_pci_tbl - PCI Device ID Table
59 *
60 * Last entry must be all 0s
61 *
62 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
63 * Class, Class Mask, private data (not used) }
64 */
65static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
66 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
67 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
76 /* required last entry */
77 {0, }
78};
79MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
80
81#define I40E_MAX_VF_COUNT 128
82static int debug = -1;
83module_param(debug, int, 0);
84MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85
86MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
87MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
88MODULE_LICENSE("GPL");
89MODULE_VERSION(DRV_VERSION);
90
91/**
92 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
93 * @hw: pointer to the HW structure
94 * @mem: ptr to mem struct to fill out
95 * @size: size of memory requested
96 * @alignment: what to align the allocation to
97 **/
98int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
99 u64 size, u32 alignment)
100{
101 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
102
103 mem->size = ALIGN(size, alignment);
104 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
105 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 106 if (!mem->va)
107 return -ENOMEM;
41c445ff 108
93bc73b8 109 return 0;
41c445ff
JB		 110}
111
112/**
113 * i40e_free_dma_mem_d - OS specific memory free for shared code
114 * @hw: pointer to the HW structure
115 * @mem: ptr to mem struct to free
116 **/
117int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
122 mem->va = NULL;
123 mem->pa = 0;
124 mem->size = 0;
125
126 return 0;
127}
128
129/**
130 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
131 * @hw: pointer to the HW structure
132 * @mem: ptr to mem struct to fill out
133 * @size: size of memory requested
134 **/
135int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
136 u32 size)
137{
138 mem->size = size;
139 mem->va = kzalloc(size, GFP_KERNEL);
140
93bc73b8
JB		 141 if (!mem->va)
142 return -ENOMEM;
41c445ff 143
93bc73b8 144 return 0;
41c445ff
JB		 145}
146
147/**
148 * i40e_free_virt_mem_d - OS specific memory free for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to free
151 **/
152int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
153{
154 /* it's ok to kfree a NULL pointer */
155 kfree(mem->va);
156 mem->va = NULL;
157 mem->size = 0;
158
159 return 0;
160}
161
162/**
163 * i40e_get_lump - find a lump of free generic resource
164 * @pf: board private structure
165 * @pile: the pile of resource to search
166 * @needed: the number of items needed
167 * @id: an owner id to stick on the items assigned
168 *
169 * Returns the base item index of the lump, or negative for error
170 *
171 * The search_hint trick and lack of advanced fit-finding only work
172 * because we're highly likely to have all the same size lump requests.
173 * Linear search time and any fragmentation should be minimal.
174 **/
175static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
176 u16 needed, u16 id)
177{
178 int ret = -ENOMEM;
ddf434ac 179 int i, j;
41c445ff
JB		 180
181 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
182 dev_info(&pf->pdev->dev,
183 "param err: pile=%p needed=%d id=0x%04x\n",
184 pile, needed, id);
185 return -EINVAL;
186 }
187
188 /* start the linear search with an imperfect hint */
189 i = pile->search_hint;
ddf434ac 190 while (i < pile->num_entries) {
41c445ff
JB		 191 /* skip already allocated entries */
192 if (pile->list[i] & I40E_PILE_VALID_BIT) {
193 i++;
194 continue;
195 }
196
197 /* do we have enough in this lump? */
198 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
199 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
200 break;
201 }
202
203 if (j == needed) {
204 /* there was enough, so assign it to the requestor */
205 for (j = 0; j < needed; j++)
206 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
207 ret = i;
208 pile->search_hint = i + j;
ddf434ac 209 break;
41c445ff
JB		 210 } else {
211 /* not enough, so skip over it and continue looking */
212 i += j;
213 }
214 }
215
216 return ret;
217}
218
219/**
220 * i40e_put_lump - return a lump of generic resource
221 * @pile: the pile of resource to search
222 * @index: the base item index
223 * @id: the owner id of the items assigned
224 *
225 * Returns the count of items in the lump
226 **/
227static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
228{
229 int valid_id = (id | I40E_PILE_VALID_BIT);
230 int count = 0;
231 int i;
232
233 if (!pile || index >= pile->num_entries)
234 return -EINVAL;
235
236 for (i = index;
237 i < pile->num_entries && pile->list[i] == valid_id;
238 i++) {
239 pile->list[i] = 0;
240 count++;
241 }
242
243 if (count && index < pile->search_hint)
244 pile->search_hint = index;
245
246 return count;
247}
248
249/**
250 * i40e_service_event_schedule - Schedule the service task to wake up
251 * @pf: board private structure
252 *
253 * If not already scheduled, this puts the task into the work queue
254 **/
255static void i40e_service_event_schedule(struct i40e_pf *pf)
256{
257 if (!test_bit(__I40E_DOWN, &pf->state) &&
258 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
259 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
260 schedule_work(&pf->service_task);
261}
262
263/**
264 * i40e_tx_timeout - Respond to a Tx Hang
265 * @netdev: network interface device structure
266 *
267 * If any port has noticed a Tx timeout, it is likely that the whole
268 * device is munged, not just the one netdev port, so go for the full
269 * reset.
270 **/
271static void i40e_tx_timeout(struct net_device *netdev)
272{
273 struct i40e_netdev_priv *np = netdev_priv(netdev);
274 struct i40e_vsi *vsi = np->vsi;
275 struct i40e_pf *pf = vsi->back;
276
277 pf->tx_timeout_count++;
278
279 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
280 pf->tx_timeout_recovery_level = 0;
281 pf->tx_timeout_last_recovery = jiffies;
282 netdev_info(netdev, "tx_timeout recovery level %d\n",
283 pf->tx_timeout_recovery_level);
284
285 switch (pf->tx_timeout_recovery_level) {
286 case 0:
287 /* disable and re-enable queues for the VSI */
288 if (in_interrupt()) {
289 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
290 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
291 } else {
292 i40e_vsi_reinit_locked(vsi);
293 }
294 break;
295 case 1:
296 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
297 break;
298 case 2:
299 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
300 break;
301 case 3:
302 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
303 break;
304 default:
305 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
306 i40e_down(vsi);
307 break;
308 }
309 i40e_service_event_schedule(pf);
310 pf->tx_timeout_recovery_level++;
311}
312
313/**
314 * i40e_release_rx_desc - Store the new tail and head values
315 * @rx_ring: ring to bump
316 * @val: new head index
317 **/
318static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
319{
320 rx_ring->next_to_use = val;
321
322 /* Force memory writes to complete before letting h/w
323 * know there are new descriptors to fetch. (Only
324 * applicable for weak-ordered memory model archs,
325 * such as IA-64).
326 */
327 wmb();
328 writel(val, rx_ring->tail);
329}
330
331/**
332 * i40e_get_vsi_stats_struct - Get System Network Statistics
333 * @vsi: the VSI we care about
334 *
335 * Returns the address of the device statistics structure.
336 * The statistics are actually updated from the service task.
337 **/
338struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
339{
340 return &vsi->net_stats;
341}
342
343/**
344 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
345 * @netdev: network interface device structure
346 *
347 * Returns the address of the device statistics structure.
348 * The statistics are actually updated from the service task.
349 **/
350static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
351 struct net_device *netdev,
980e9b11 352 struct rtnl_link_stats64 *stats)
41c445ff
JB		 353{
354 struct i40e_netdev_priv *np = netdev_priv(netdev);
355 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 356 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
357 int i;
358
143c9054 359
bc7d338f
ASJ		 360 if (test_bit(__I40E_DOWN, &vsi->state))
361 return stats;
362
3c325ced
JB		 363 if (!vsi->tx_rings)
364 return stats;
365
980e9b11
AD		 366 rcu_read_lock();
367 for (i = 0; i < vsi->num_queue_pairs; i++) {
368 struct i40e_ring *tx_ring, *rx_ring;
369 u64 bytes, packets;
370 unsigned int start;
371
372 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
373 if (!tx_ring)
374 continue;
375
376 do {
377 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
378 packets = tx_ring->stats.packets;
379 bytes = tx_ring->stats.bytes;
380 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
381
382 stats->tx_packets += packets;
383 stats->tx_bytes += bytes;
384 rx_ring = &tx_ring[1];
385
386 do {
387 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
388 packets = rx_ring->stats.packets;
389 bytes = rx_ring->stats.bytes;
390 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 391
980e9b11
AD		 392 stats->rx_packets += packets;
393 stats->rx_bytes += bytes;
394 }
395 rcu_read_unlock();
396
397 /* following stats updated by ixgbe_watchdog_task() */
398 stats->multicast = vsi_stats->multicast;
399 stats->tx_errors = vsi_stats->tx_errors;
400 stats->tx_dropped = vsi_stats->tx_dropped;
401 stats->rx_errors = vsi_stats->rx_errors;
402 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
403 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 404
980e9b11 405 return stats;
41c445ff
JB		 406}
407
408/**
409 * i40e_vsi_reset_stats - Resets all stats of the given vsi
410 * @vsi: the VSI to have its stats reset
411 **/
412void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
413{
414 struct rtnl_link_stats64 *ns;
415 int i;
416
417 if (!vsi)
418 return;
419
420 ns = i40e_get_vsi_stats_struct(vsi);
421 memset(ns, 0, sizeof(*ns));
422 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
423 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
424 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 425 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 426 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 427 memset(&vsi->rx_rings[i]->stats, 0 ,
428 sizeof(vsi->rx_rings[i]->stats));
429 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
430 sizeof(vsi->rx_rings[i]->rx_stats));
431 memset(&vsi->tx_rings[i]->stats, 0 ,
432 sizeof(vsi->tx_rings[i]->stats));
433 memset(&vsi->tx_rings[i]->tx_stats, 0,
434 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 435 }
8e9dca53 436 }
41c445ff
JB		 437 vsi->stat_offsets_loaded = false;
438}
439
440/**
441 * i40e_pf_reset_stats - Reset all of the stats for the given pf
442 * @pf: the PF to be reset
443 **/
444void i40e_pf_reset_stats(struct i40e_pf *pf)
445{
446 memset(&pf->stats, 0, sizeof(pf->stats));
447 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
448 pf->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_stat_update48 - read and update a 48 bit stat from the chip
453 * @hw: ptr to the hardware info
454 * @hireg: the high 32 bit reg to read
455 * @loreg: the low 32 bit reg to read
456 * @offset_loaded: has the initial offset been loaded yet
457 * @offset: ptr to current offset value
458 * @stat: ptr to the stat
459 *
460 * Since the device stats are not reset at PFReset, they likely will not
461 * be zeroed when the driver starts. We'll save the first values read
462 * and use them as offsets to be subtracted from the raw values in order
463 * to report stats that count from zero. In the process, we also manage
464 * the potential roll-over.
465 **/
466static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
467 bool offset_loaded, u64 *offset, u64 *stat)
468{
469 u64 new_data;
470
471 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
472 new_data = rd32(hw, loreg);
473 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
474 } else {
475 new_data = rd64(hw, loreg);
476 }
477 if (!offset_loaded)
478 *offset = new_data;
479 if (likely(new_data >= *offset))
480 *stat = new_data - *offset;
481 else
482 *stat = (new_data + ((u64)1 << 48)) - *offset;
483 *stat &= 0xFFFFFFFFFFFFULL;
484}
485
486/**
487 * i40e_stat_update32 - read and update a 32 bit stat from the chip
488 * @hw: ptr to the hardware info
489 * @reg: the hw reg to read
490 * @offset_loaded: has the initial offset been loaded yet
491 * @offset: ptr to current offset value
492 * @stat: ptr to the stat
493 **/
494static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
495 bool offset_loaded, u64 *offset, u64 *stat)
496{
497 u32 new_data;
498
499 new_data = rd32(hw, reg);
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = (u32)(new_data - *offset);
504 else
505 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
506}
507
508/**
509 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
510 * @vsi: the VSI to be updated
511 **/
512void i40e_update_eth_stats(struct i40e_vsi *vsi)
513{
514 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
515 struct i40e_pf *pf = vsi->back;
516 struct i40e_hw *hw = &pf->hw;
517 struct i40e_eth_stats *oes;
518 struct i40e_eth_stats *es; /* device's eth stats */
519
520 es = &vsi->eth_stats;
521 oes = &vsi->eth_stats_offsets;
522
523 /* Gather up the stats that the hw collects */
524 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
525 vsi->stat_offsets_loaded,
526 &oes->tx_errors, &es->tx_errors);
527 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->rx_discards, &es->rx_discards);
530
531 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
532 I40E_GLV_GORCL(stat_idx),
533 vsi->stat_offsets_loaded,
534 &oes->rx_bytes, &es->rx_bytes);
535 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
536 I40E_GLV_UPRCL(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->rx_unicast, &es->rx_unicast);
539 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
540 I40E_GLV_MPRCL(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_multicast, &es->rx_multicast);
543 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
544 I40E_GLV_BPRCL(stat_idx),
545 vsi->stat_offsets_loaded,
546 &oes->rx_broadcast, &es->rx_broadcast);
547
548 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
549 I40E_GLV_GOTCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_bytes, &es->tx_bytes);
552 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
553 I40E_GLV_UPTCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->tx_unicast, &es->tx_unicast);
556 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
557 I40E_GLV_MPTCL(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_multicast, &es->tx_multicast);
560 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
561 I40E_GLV_BPTCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->tx_broadcast, &es->tx_broadcast);
564 vsi->stat_offsets_loaded = true;
565}
566
567/**
568 * i40e_update_veb_stats - Update Switch component statistics
569 * @veb: the VEB being updated
570 **/
571static void i40e_update_veb_stats(struct i40e_veb *veb)
572{
573 struct i40e_pf *pf = veb->pf;
574 struct i40e_hw *hw = &pf->hw;
575 struct i40e_eth_stats *oes;
576 struct i40e_eth_stats *es; /* device's eth stats */
577 int idx = 0;
578
579 idx = veb->stats_idx;
580 es = &veb->stats;
581 oes = &veb->stats_offsets;
582
583 /* Gather up the stats that the hw collects */
584 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
585 veb->stat_offsets_loaded,
586 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 587 if (hw->revision_id > 0)
588 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
589 veb->stat_offsets_loaded,
590 &oes->rx_unknown_protocol,
591 &es->rx_unknown_protocol);
41c445ff
JB		 592 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
593 veb->stat_offsets_loaded,
594 &oes->rx_bytes, &es->rx_bytes);
595 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unicast, &es->rx_unicast);
598 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_multicast, &es->rx_multicast);
601 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_broadcast, &es->rx_broadcast);
604
605 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->tx_bytes, &es->tx_bytes);
608 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_unicast, &es->tx_unicast);
611 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_multicast, &es->tx_multicast);
614 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_broadcast, &es->tx_broadcast);
617 veb->stat_offsets_loaded = true;
618}
619
620/**
621 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
622 * @pf: the corresponding PF
623 *
624 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
625 **/
626static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
627{
628 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
629 struct i40e_hw_port_stats *nsd = &pf->stats;
630 struct i40e_hw *hw = &pf->hw;
631 u64 xoff = 0;
632 u16 i, v;
633
634 if ((hw->fc.current_mode != I40E_FC_FULL) &&
635 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
636 return;
637
638 xoff = nsd->link_xoff_rx;
639 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
640 pf->stat_offsets_loaded,
641 &osd->link_xoff_rx, &nsd->link_xoff_rx);
642
643 /* No new LFC xoff rx */
644 if (!(nsd->link_xoff_rx - xoff))
645 return;
646
647 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
648 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
649 struct i40e_vsi *vsi = pf->vsi[v];
650
651 if (!vsi)
652 continue;
653
654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 655 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 656 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
657 }
658 }
659}
660
661/**
662 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
663 * @pf: the corresponding PF
664 *
665 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
666 **/
667static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
668{
669 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
670 struct i40e_hw_port_stats *nsd = &pf->stats;
671 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
672 struct i40e_dcbx_config *dcb_cfg;
673 struct i40e_hw *hw = &pf->hw;
674 u16 i, v;
675 u8 tc;
676
677 dcb_cfg = &hw->local_dcbx_config;
678
679 /* See if DCB enabled with PFC TC */
680 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
681 !(dcb_cfg->pfc.pfcenable)) {
682 i40e_update_link_xoff_rx(pf);
683 return;
684 }
685
686 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
687 u64 prio_xoff = nsd->priority_xoff_rx[i];
688 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
689 pf->stat_offsets_loaded,
690 &osd->priority_xoff_rx[i],
691 &nsd->priority_xoff_rx[i]);
692
693 /* No new PFC xoff rx */
694 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
695 continue;
696 /* Get the TC for given priority */
697 tc = dcb_cfg->etscfg.prioritytable[i];
698 xoff[tc] = true;
699 }
700
701 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
702 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
703 struct i40e_vsi *vsi = pf->vsi[v];
704
705 if (!vsi)
706 continue;
707
708 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 709 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 710
711 tc = ring->dcb_tc;
712 if (xoff[tc])
713 clear_bit(__I40E_HANG_CHECK_ARMED,
714 &ring->state);
715 }
716 }
717}
718
719/**
720 * i40e_update_stats - Update the board statistics counters.
721 * @vsi: the VSI to be updated
722 *
723 * There are a few instances where we store the same stat in a
724 * couple of different structs. This is partly because we have
725 * the netdev stats that need to be filled out, which is slightly
726 * different from the "eth_stats" defined by the chip and used in
727 * VF communications. We sort it all out here in a central place.
728 **/
729void i40e_update_stats(struct i40e_vsi *vsi)
730{
731 struct i40e_pf *pf = vsi->back;
732 struct i40e_hw *hw = &pf->hw;
733 struct rtnl_link_stats64 *ons;
734 struct rtnl_link_stats64 *ns; /* netdev stats */
735 struct i40e_eth_stats *oes;
736 struct i40e_eth_stats *es; /* device's eth stats */
737 u32 tx_restart, tx_busy;
738 u32 rx_page, rx_buf;
739 u64 rx_p, rx_b;
740 u64 tx_p, tx_b;
741 int i;
742 u16 q;
743
744 if (test_bit(__I40E_DOWN, &vsi->state) ||
745 test_bit(__I40E_CONFIG_BUSY, &pf->state))
746 return;
747
748 ns = i40e_get_vsi_stats_struct(vsi);
749 ons = &vsi->net_stats_offsets;
750 es = &vsi->eth_stats;
751 oes = &vsi->eth_stats_offsets;
752
753 /* Gather up the netdev and vsi stats that the driver collects
754 * on the fly during packet processing
755 */
756 rx_b = rx_p = 0;
757 tx_b = tx_p = 0;
758 tx_restart = tx_busy = 0;
759 rx_page = 0;
760 rx_buf = 0;
980e9b11 761 rcu_read_lock();
41c445ff
JB		 762 for (q = 0; q < vsi->num_queue_pairs; q++) {
763 struct i40e_ring *p;
980e9b11
AD		 764 u64 bytes, packets;
765 unsigned int start;
766
767 /* locate Tx ring */
768 p = ACCESS_ONCE(vsi->tx_rings[q]);
769
770 do {
771 start = u64_stats_fetch_begin_bh(&p->syncp);
772 packets = p->stats.packets;
773 bytes = p->stats.bytes;
774 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
775 tx_b += bytes;
776 tx_p += packets;
777 tx_restart += p->tx_stats.restart_queue;
778 tx_busy += p->tx_stats.tx_busy;
41c445ff 779
980e9b11
AD		 780 /* Rx queue is part of the same block as Tx queue */
781 p = &p[1];
782 do {
783 start = u64_stats_fetch_begin_bh(&p->syncp);
784 packets = p->stats.packets;
785 bytes = p->stats.bytes;
786 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
787 rx_b += bytes;
788 rx_p += packets;
420136cc
MW		 789 rx_buf += p->rx_stats.alloc_buff_failed;
790 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 791 }
980e9b11 792 rcu_read_unlock();
41c445ff
JB		 793 vsi->tx_restart = tx_restart;
794 vsi->tx_busy = tx_busy;
795 vsi->rx_page_failed = rx_page;
796 vsi->rx_buf_failed = rx_buf;
797
798 ns->rx_packets = rx_p;
799 ns->rx_bytes = rx_b;
800 ns->tx_packets = tx_p;
801 ns->tx_bytes = tx_b;
802
803 i40e_update_eth_stats(vsi);
804 /* update netdev stats from eth stats */
805 ons->rx_errors = oes->rx_errors;
806 ns->rx_errors = es->rx_errors;
807 ons->tx_errors = oes->tx_errors;
808 ns->tx_errors = es->tx_errors;
809 ons->multicast = oes->rx_multicast;
810 ns->multicast = es->rx_multicast;
811 ons->tx_dropped = oes->tx_discards;
812 ns->tx_dropped = es->tx_discards;
813
814 /* Get the port data only if this is the main PF VSI */
815 if (vsi == pf->vsi[pf->lan_vsi]) {
816 struct i40e_hw_port_stats *nsd = &pf->stats;
817 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
818
819 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
820 I40E_GLPRT_GORCL(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
823 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
824 I40E_GLPRT_GOTCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
827 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.rx_discards,
830 &nsd->eth.rx_discards);
831 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.tx_discards,
834 &nsd->eth.tx_discards);
835 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
836 I40E_GLPRT_MPRCL(hw->port),
837 pf->stat_offsets_loaded,
838 &osd->eth.rx_multicast,
839 &nsd->eth.rx_multicast);
840
841 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->tx_dropped_link_down,
844 &nsd->tx_dropped_link_down);
845
846 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->crc_errors, &nsd->crc_errors);
849 ns->rx_crc_errors = nsd->crc_errors;
850
851 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->illegal_bytes, &nsd->illegal_bytes);
854 ns->rx_errors = nsd->crc_errors
855 + nsd->illegal_bytes;
856
857 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->mac_local_faults,
860 &nsd->mac_local_faults);
861 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_remote_faults,
864 &nsd->mac_remote_faults);
865
866 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
867 pf->stat_offsets_loaded,
868 &osd->rx_length_errors,
869 &nsd->rx_length_errors);
870 ns->rx_length_errors = nsd->rx_length_errors;
871
872 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->link_xon_rx, &nsd->link_xon_rx);
875 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_tx, &nsd->link_xon_tx);
878 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
879 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xoff_tx, &nsd->link_xoff_tx);
882
883 for (i = 0; i < 8; i++) {
884 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
885 pf->stat_offsets_loaded,
886 &osd->priority_xon_rx[i],
887 &nsd->priority_xon_rx[i]);
888 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_tx[i],
891 &nsd->priority_xon_tx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xoff_tx[i],
895 &nsd->priority_xoff_tx[i]);
896 i40e_stat_update32(hw,
897 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
898 pf->stat_offsets_loaded,
899 &osd->priority_xon_2_xoff[i],
900 &nsd->priority_xon_2_xoff[i]);
901 }
902
903 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
904 I40E_GLPRT_PRC64L(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->rx_size_64, &nsd->rx_size_64);
907 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
908 I40E_GLPRT_PRC127L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_127, &nsd->rx_size_127);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
912 I40E_GLPRT_PRC255L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_255, &nsd->rx_size_255);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
916 I40E_GLPRT_PRC511L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_511, &nsd->rx_size_511);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
920 I40E_GLPRT_PRC1023L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_1023, &nsd->rx_size_1023);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
924 I40E_GLPRT_PRC1522L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1522, &nsd->rx_size_1522);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
928 I40E_GLPRT_PRC9522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_big, &nsd->rx_size_big);
931
932 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
933 I40E_GLPRT_PTC64L(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->tx_size_64, &nsd->tx_size_64);
936 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
937 I40E_GLPRT_PTC127L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_127, &nsd->tx_size_127);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
941 I40E_GLPRT_PTC255L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_255, &nsd->tx_size_255);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
945 I40E_GLPRT_PTC511L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_511, &nsd->tx_size_511);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
949 I40E_GLPRT_PTC1023L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_1023, &nsd->tx_size_1023);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
953 I40E_GLPRT_PTC1522L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1522, &nsd->tx_size_1522);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
957 I40E_GLPRT_PTC9522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_big, &nsd->tx_size_big);
960
961 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->rx_undersize, &nsd->rx_undersize);
964 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_fragments, &nsd->rx_fragments);
967 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_oversize, &nsd->rx_oversize);
970 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_jabber, &nsd->rx_jabber);
973 }
974
975 pf->stat_offsets_loaded = true;
976}
977
978/**
979 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
980 * @vsi: the VSI to be searched
981 * @macaddr: the MAC address
982 * @vlan: the vlan
983 * @is_vf: make sure its a vf filter, else doesn't matter
984 * @is_netdev: make sure its a netdev filter, else doesn't matter
985 *
986 * Returns ptr to the filter object or NULL
987 **/
988static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
989 u8 *macaddr, s16 vlan,
990 bool is_vf, bool is_netdev)
991{
992 struct i40e_mac_filter *f;
993
994 if (!vsi || !macaddr)
995 return NULL;
996
997 list_for_each_entry(f, &vsi->mac_filter_list, list) {
998 if ((ether_addr_equal(macaddr, f->macaddr)) &&
999 (vlan == f->vlan) &&
1000 (!is_vf || f->is_vf) &&
1001 (!is_netdev || f->is_netdev))
1002 return f;
1003 }
1004 return NULL;
1005}
1006
1007/**
1008 * i40e_find_mac - Find a mac addr in the macvlan filters list
1009 * @vsi: the VSI to be searched
1010 * @macaddr: the MAC address we are searching for
1011 * @is_vf: make sure its a vf filter, else doesn't matter
1012 * @is_netdev: make sure its a netdev filter, else doesn't matter
1013 *
1014 * Returns the first filter with the provided MAC address or NULL if
1015 * MAC address was not found
1016 **/
1017struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1018 bool is_vf, bool is_netdev)
1019{
1020 struct i40e_mac_filter *f;
1021
1022 if (!vsi || !macaddr)
1023 return NULL;
1024
1025 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1026 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1027 (!is_vf || f->is_vf) &&
1028 (!is_netdev || f->is_netdev))
1029 return f;
1030 }
1031 return NULL;
1032}
1033
1034/**
1035 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1036 * @vsi: the VSI to be searched
1037 *
1038 * Returns true if VSI is in vlan mode or false otherwise
1039 **/
1040bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1041{
1042 struct i40e_mac_filter *f;
1043
1044 /* Only -1 for all the filters denotes not in vlan mode
1045 * so we have to go through all the list in order to make sure
1046 */
1047 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1048 if (f->vlan >= 0)
1049 return true;
1050 }
1051
1052 return false;
1053}
1054
1055/**
1056 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1057 * @vsi: the VSI to be searched
1058 * @macaddr: the mac address to be filtered
1059 * @is_vf: true if it is a vf
1060 * @is_netdev: true if it is a netdev
1061 *
1062 * Goes through all the macvlan filters and adds a
1063 * macvlan filter for each unique vlan that already exists
1064 *
1065 * Returns first filter found on success, else NULL
1066 **/
1067struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1068 bool is_vf, bool is_netdev)
1069{
1070 struct i40e_mac_filter *f;
1071
1072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1073 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1074 is_vf, is_netdev)) {
1075 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev))
1077 return NULL;
1078 }
1079 }
1080
1081 return list_first_entry_or_null(&vsi->mac_filter_list,
1082 struct i40e_mac_filter, list);
1083}
1084
1085/**
1086 * i40e_add_filter - Add a mac/vlan filter to the VSI
1087 * @vsi: the VSI to be searched
1088 * @macaddr: the MAC address
1089 * @vlan: the vlan
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns ptr to the filter object or NULL when no memory available.
1094 **/
1095struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1096 u8 *macaddr, s16 vlan,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1105 if (!f) {
1106 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1107 if (!f)
1108 goto add_filter_out;
1109
1110 memcpy(f->macaddr, macaddr, ETH_ALEN);
1111 f->vlan = vlan;
1112 f->changed = true;
1113
1114 INIT_LIST_HEAD(&f->list);
1115 list_add(&f->list, &vsi->mac_filter_list);
1116 }
1117
1118 /* increment counter and add a new flag if needed */
1119 if (is_vf) {
1120 if (!f->is_vf) {
1121 f->is_vf = true;
1122 f->counter++;
1123 }
1124 } else if (is_netdev) {
1125 if (!f->is_netdev) {
1126 f->is_netdev = true;
1127 f->counter++;
1128 }
1129 } else {
1130 f->counter++;
1131 }
1132
1133 /* changed tells sync_filters_subtask to
1134 * push the filter down to the firmware
1135 */
1136 if (f->changed) {
1137 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1138 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1139 }
1140
1141add_filter_out:
1142 return f;
1143}
1144
1145/**
1146 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
1150 * @is_vf: make sure it's a vf filter, else doesn't matter
1151 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1152 **/
1153void i40e_del_filter(struct i40e_vsi *vsi,
1154 u8 *macaddr, s16 vlan,
1155 bool is_vf, bool is_netdev)
1156{
1157 struct i40e_mac_filter *f;
1158
1159 if (!vsi || !macaddr)
1160 return;
1161
1162 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1163 if (!f || f->counter == 0)
1164 return;
1165
1166 if (is_vf) {
1167 if (f->is_vf) {
1168 f->is_vf = false;
1169 f->counter--;
1170 }
1171 } else if (is_netdev) {
1172 if (f->is_netdev) {
1173 f->is_netdev = false;
1174 f->counter--;
1175 }
1176 } else {
1177 /* make sure we don't remove a filter in use by vf or netdev */
1178 int min_f = 0;
1179 min_f += (f->is_vf ? 1 : 0);
1180 min_f += (f->is_netdev ? 1 : 0);
1181
1182 if (f->counter > min_f)
1183 f->counter--;
1184 }
1185
1186 /* counter == 0 tells sync_filters_subtask to
1187 * remove the filter from the firmware's list
1188 */
1189 if (f->counter == 0) {
1190 f->changed = true;
1191 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1192 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1193 }
1194}
1195
1196/**
1197 * i40e_set_mac - NDO callback to set mac address
1198 * @netdev: network interface device structure
1199 * @p: pointer to an address structure
1200 *
1201 * Returns 0 on success, negative on failure
1202 **/
1203static int i40e_set_mac(struct net_device *netdev, void *p)
1204{
1205 struct i40e_netdev_priv *np = netdev_priv(netdev);
1206 struct i40e_vsi *vsi = np->vsi;
1207 struct sockaddr *addr = p;
1208 struct i40e_mac_filter *f;
1209
1210 if (!is_valid_ether_addr(addr->sa_data))
1211 return -EADDRNOTAVAIL;
1212
1213 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1214
1215 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1216 return 0;
1217
80f6428f
ASJ		 1218 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1219 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1220 return -EADDRNOTAVAIL;
1221
41c445ff
JB		 1222 if (vsi->type == I40E_VSI_MAIN) {
1223 i40e_status ret;
1224 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1225 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1226 addr->sa_data, NULL);
1227 if (ret) {
1228 netdev_info(netdev,
1229 "Addr change for Main VSI failed: %d\n",
1230 ret);
1231 return -EADDRNOTAVAIL;
1232 }
1233
1234 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1235 }
1236
1237 /* In order to be sure to not drop any packets, add the new address
1238 * then delete the old one.
1239 */
1240 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1241 if (!f)
1242 return -ENOMEM;
1243
1244 i40e_sync_vsi_filters(vsi);
1245 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1246 i40e_sync_vsi_filters(vsi);
1247
1248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1249
1250 return 0;
1251}
1252
1253/**
1254 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1255 * @vsi: the VSI being setup
1256 * @ctxt: VSI context structure
1257 * @enabled_tc: Enabled TCs bitmap
1258 * @is_add: True if called before Add VSI
1259 *
1260 * Setup VSI queue mapping for enabled traffic classes.
1261 **/
1262static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1263 struct i40e_vsi_context *ctxt,
1264 u8 enabled_tc,
1265 bool is_add)
1266{
1267 struct i40e_pf *pf = vsi->back;
1268 u16 sections = 0;
1269 u8 netdev_tc = 0;
1270 u16 numtc = 0;
1271 u16 qcount;
1272 u8 offset;
1273 u16 qmap;
1274 int i;
1275
1276 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1277 offset = 0;
1278
1279 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1280 /* Find numtc from enabled TC bitmap */
1281 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1282 if (enabled_tc & (1 << i)) /* TC is enabled */
1283 numtc++;
1284 }
1285 if (!numtc) {
1286 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1287 numtc = 1;
1288 }
1289 } else {
1290 /* At least TC0 is enabled in case of non-DCB case */
1291 numtc = 1;
1292 }
1293
1294 vsi->tc_config.numtc = numtc;
1295 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1296
1297 /* Setup queue offset/count for all TCs for given VSI */
1298 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1299 /* See if the given TC is enabled for the given VSI */
1300 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1301 int pow, num_qps;
1302
1303 vsi->tc_config.tc_info[i].qoffset = offset;
1304 switch (vsi->type) {
1305 case I40E_VSI_MAIN:
1306 if (i == 0)
1307 qcount = pf->rss_size;
1308 else
1309 qcount = pf->num_tc_qps;
1310 vsi->tc_config.tc_info[i].qcount = qcount;
1311 break;
1312 case I40E_VSI_FDIR:
1313 case I40E_VSI_SRIOV:
1314 case I40E_VSI_VMDQ2:
1315 default:
1316 qcount = vsi->alloc_queue_pairs;
1317 vsi->tc_config.tc_info[i].qcount = qcount;
1318 WARN_ON(i != 0);
1319 break;
1320 }
1321
1322 /* find the power-of-2 of the number of queue pairs */
1323 num_qps = vsi->tc_config.tc_info[i].qcount;
1324 pow = 0;
1325 while (num_qps &&
1326 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1327 pow++;
1328 num_qps >>= 1;
1329 }
1330
1331 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1332 qmap =
1333 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1334 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1335
1336 offset += vsi->tc_config.tc_info[i].qcount;
1337 } else {
1338 /* TC is not enabled so set the offset to
1339 * default queue and allocate one queue
1340 * for the given TC.
1341 */
1342 vsi->tc_config.tc_info[i].qoffset = 0;
1343 vsi->tc_config.tc_info[i].qcount = 1;
1344 vsi->tc_config.tc_info[i].netdev_tc = 0;
1345
1346 qmap = 0;
1347 }
1348 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1349 }
1350
1351 /* Set actual Tx/Rx queue pairs */
1352 vsi->num_queue_pairs = offset;
1353
1354 /* Scheduler section valid can only be set for ADD VSI */
1355 if (is_add) {
1356 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1357
1358 ctxt->info.up_enable_bits = enabled_tc;
1359 }
1360 if (vsi->type == I40E_VSI_SRIOV) {
1361 ctxt->info.mapping_flags |=
1362 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1363 for (i = 0; i < vsi->num_queue_pairs; i++)
1364 ctxt->info.queue_mapping[i] =
1365 cpu_to_le16(vsi->base_queue + i);
1366 } else {
1367 ctxt->info.mapping_flags |=
1368 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1369 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1370 }
1371 ctxt->info.valid_sections |= cpu_to_le16(sections);
1372}
1373
1374/**
1375 * i40e_set_rx_mode - NDO callback to set the netdev filters
1376 * @netdev: network interface device structure
1377 **/
1378static void i40e_set_rx_mode(struct net_device *netdev)
1379{
1380 struct i40e_netdev_priv *np = netdev_priv(netdev);
1381 struct i40e_mac_filter *f, *ftmp;
1382 struct i40e_vsi *vsi = np->vsi;
1383 struct netdev_hw_addr *uca;
1384 struct netdev_hw_addr *mca;
1385 struct netdev_hw_addr *ha;
1386
1387 /* add addr if not already in the filter list */
1388 netdev_for_each_uc_addr(uca, netdev) {
1389 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1390 if (i40e_is_vsi_in_vlan(vsi))
1391 i40e_put_mac_in_vlan(vsi, uca->addr,
1392 false, true);
1393 else
1394 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1395 false, true);
1396 }
1397 }
1398
1399 netdev_for_each_mc_addr(mca, netdev) {
1400 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1401 if (i40e_is_vsi_in_vlan(vsi))
1402 i40e_put_mac_in_vlan(vsi, mca->addr,
1403 false, true);
1404 else
1405 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1406 false, true);
1407 }
1408 }
1409
1410 /* remove filter if not in netdev list */
1411 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1412 bool found = false;
1413
1414 if (!f->is_netdev)
1415 continue;
1416
1417 if (is_multicast_ether_addr(f->macaddr)) {
1418 netdev_for_each_mc_addr(mca, netdev) {
1419 if (ether_addr_equal(mca->addr, f->macaddr)) {
1420 found = true;
1421 break;
1422 }
1423 }
1424 } else {
1425 netdev_for_each_uc_addr(uca, netdev) {
1426 if (ether_addr_equal(uca->addr, f->macaddr)) {
1427 found = true;
1428 break;
1429 }
1430 }
1431
1432 for_each_dev_addr(netdev, ha) {
1433 if (ether_addr_equal(ha->addr, f->macaddr)) {
1434 found = true;
1435 break;
1436 }
1437 }
1438 }
1439 if (!found)
1440 i40e_del_filter(
1441 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1442 }
1443
1444 /* check for other flag changes */
1445 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1446 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1447 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1448 }
1449}
1450
1451/**
1452 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1453 * @vsi: ptr to the VSI
1454 *
1455 * Push any outstanding VSI filter changes through the AdminQ.
1456 *
1457 * Returns 0 or error value
1458 **/
1459int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1460{
1461 struct i40e_mac_filter *f, *ftmp;
1462 bool promisc_forced_on = false;
1463 bool add_happened = false;
1464 int filter_list_len = 0;
1465 u32 changed_flags = 0;
dcae29be 1466 i40e_status aq_ret = 0;
41c445ff
JB		 1467 struct i40e_pf *pf;
1468 int num_add = 0;
1469 int num_del = 0;
1470 u16 cmd_flags;
1471
1472 /* empty array typed pointers, kcalloc later */
1473 struct i40e_aqc_add_macvlan_element_data *add_list;
1474 struct i40e_aqc_remove_macvlan_element_data *del_list;
1475
1476 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1477 usleep_range(1000, 2000);
1478 pf = vsi->back;
1479
1480 if (vsi->netdev) {
1481 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1482 vsi->current_netdev_flags = vsi->netdev->flags;
1483 }
1484
1485 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1486 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1487
1488 filter_list_len = pf->hw.aq.asq_buf_size /
1489 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1490 del_list = kcalloc(filter_list_len,
1491 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1492 GFP_KERNEL);
1493 if (!del_list)
1494 return -ENOMEM;
1495
1496 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1497 if (!f->changed)
1498 continue;
1499
1500 if (f->counter != 0)
1501 continue;
1502 f->changed = false;
1503 cmd_flags = 0;
1504
1505 /* add to delete list */
1506 memcpy(del_list[num_del].mac_addr,
1507 f->macaddr, ETH_ALEN);
1508 del_list[num_del].vlan_tag =
1509 cpu_to_le16((u16)(f->vlan ==
1510 I40E_VLAN_ANY ? 0 : f->vlan));
1511
41c445ff
JB		 1512 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1513 del_list[num_del].flags = cmd_flags;
1514 num_del++;
1515
1516 /* unlink from filter list */
1517 list_del(&f->list);
1518 kfree(f);
1519
1520 /* flush a full buffer */
1521 if (num_del == filter_list_len) {
dcae29be 1522 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1523 vsi->seid, del_list, num_del,
1524 NULL);
1525 num_del = 0;
1526 memset(del_list, 0, sizeof(*del_list));
1527
dcae29be 1528 if (aq_ret)
41c445ff
JB		 1529 dev_info(&pf->pdev->dev,
1530 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1531 aq_ret,
41c445ff
JB		 1532 pf->hw.aq.asq_last_status);
1533 }
1534 }
1535 if (num_del) {
dcae29be 1536 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1537 del_list, num_del, NULL);
1538 num_del = 0;
1539
dcae29be 1540 if (aq_ret)
41c445ff
JB		 1541 dev_info(&pf->pdev->dev,
1542 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1543 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1544 }
1545
1546 kfree(del_list);
1547 del_list = NULL;
1548
1549 /* do all the adds now */
1550 filter_list_len = pf->hw.aq.asq_buf_size /
1551 sizeof(struct i40e_aqc_add_macvlan_element_data),
1552 add_list = kcalloc(filter_list_len,
1553 sizeof(struct i40e_aqc_add_macvlan_element_data),
1554 GFP_KERNEL);
1555 if (!add_list)
1556 return -ENOMEM;
1557
1558 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1559 if (!f->changed)
1560 continue;
1561
1562 if (f->counter == 0)
1563 continue;
1564 f->changed = false;
1565 add_happened = true;
1566 cmd_flags = 0;
1567
1568 /* add to add array */
1569 memcpy(add_list[num_add].mac_addr,
1570 f->macaddr, ETH_ALEN);
1571 add_list[num_add].vlan_tag =
1572 cpu_to_le16(
1573 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1574 add_list[num_add].queue_number = 0;
1575
1576 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1577 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1578 num_add++;
1579
1580 /* flush a full buffer */
1581 if (num_add == filter_list_len) {
dcae29be
JB		 1582 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1583 add_list, num_add,
1584 NULL);
41c445ff
JB		 1585 num_add = 0;
1586
dcae29be 1587 if (aq_ret)
41c445ff
JB		 1588 break;
1589 memset(add_list, 0, sizeof(*add_list));
1590 }
1591 }
1592 if (num_add) {
dcae29be
JB		 1593 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1594 add_list, num_add, NULL);
41c445ff
JB		 1595 num_add = 0;
1596 }
1597 kfree(add_list);
1598 add_list = NULL;
1599
dcae29be 1600 if (add_happened && (!aq_ret)) {
41c445ff 1601 /* do nothing */;
dcae29be 1602 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1603 dev_info(&pf->pdev->dev,
1604 "add filter failed, err %d, aq_err %d\n",
dcae29be 1605 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1606 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1607 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1608 &vsi->state)) {
1609 promisc_forced_on = true;
1610 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1611 &vsi->state);
1612 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1613 }
1614 }
1615 }
1616
1617 /* check for changes in promiscuous modes */
1618 if (changed_flags & IFF_ALLMULTI) {
1619 bool cur_multipromisc;
1620 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1621 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1622 vsi->seid,
1623 cur_multipromisc,
1624 NULL);
1625 if (aq_ret)
41c445ff
JB		 1626 dev_info(&pf->pdev->dev,
1627 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1628 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1629 }
1630 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1631 bool cur_promisc;
1632 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1633 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1634 &vsi->state));
dcae29be
JB		 1635 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1636 vsi->seid,
1637 cur_promisc, NULL);
1638 if (aq_ret)
41c445ff
JB		 1639 dev_info(&pf->pdev->dev,
1640 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1641 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1642 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1643 vsi->seid,
1644 cur_promisc, NULL);
1645 if (aq_ret)
1646 dev_info(&pf->pdev->dev,
1647 "set brdcast promisc failed, err %d, aq_err %d\n",
1648 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1649 }
1650
1651 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1652 return 0;
1653}
1654
1655/**
1656 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1657 * @pf: board private structure
1658 **/
1659static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1660{
1661 int v;
1662
1663 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1664 return;
1665 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1666
1667 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1668 if (pf->vsi[v] &&
1669 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1670 i40e_sync_vsi_filters(pf->vsi[v]);
1671 }
1672}
1673
1674/**
1675 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1676 * @netdev: network interface device structure
1677 * @new_mtu: new value for maximum frame size
1678 *
1679 * Returns 0 on success, negative on failure
1680 **/
1681static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1682{
1683 struct i40e_netdev_priv *np = netdev_priv(netdev);
1684 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1685 struct i40e_vsi *vsi = np->vsi;
1686
1687 /* MTU < 68 is an error and causes problems on some kernels */
1688 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1689 return -EINVAL;
1690
1691 netdev_info(netdev, "changing MTU from %d to %d\n",
1692 netdev->mtu, new_mtu);
1693 netdev->mtu = new_mtu;
1694 if (netif_running(netdev))
1695 i40e_vsi_reinit_locked(vsi);
1696
1697 return 0;
1698}
1699
beb0dff1
JK		 1700/**
1701 * i40e_ioctl - Access the hwtstamp interface
1702 * @netdev: network interface device structure
1703 * @ifr: interface request data
1704 * @cmd: ioctl command
1705 **/
1706int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1707{
1708 struct i40e_netdev_priv *np = netdev_priv(netdev);
1709 struct i40e_pf *pf = np->vsi->back;
1710
1711 switch (cmd) {
1712 case SIOCGHWTSTAMP:
1713 return i40e_ptp_get_ts_config(pf, ifr);
1714 case SIOCSHWTSTAMP:
1715 return i40e_ptp_set_ts_config(pf, ifr);
1716 default:
1717 return -EOPNOTSUPP;
1718 }
1719}
1720
41c445ff
JB		 1721/**
1722 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1723 * @vsi: the vsi being adjusted
1724 **/
1725void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1726{
1727 struct i40e_vsi_context ctxt;
1728 i40e_status ret;
1729
1730 if ((vsi->info.valid_sections &
1731 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1732 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1733 return; /* already enabled */
1734
1735 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1736 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1737 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1738
1739 ctxt.seid = vsi->seid;
1740 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1741 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1742 if (ret) {
1743 dev_info(&vsi->back->pdev->dev,
1744 "%s: update vsi failed, aq_err=%d\n",
1745 __func__, vsi->back->hw.aq.asq_last_status);
1746 }
1747}
1748
1749/**
1750 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1751 * @vsi: the vsi being adjusted
1752 **/
1753void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1754{
1755 struct i40e_vsi_context ctxt;
1756 i40e_status ret;
1757
1758 if ((vsi->info.valid_sections &
1759 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1760 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1761 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1762 return; /* already disabled */
1763
1764 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1765 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1766 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1767
1768 ctxt.seid = vsi->seid;
1769 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1770 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1771 if (ret) {
1772 dev_info(&vsi->back->pdev->dev,
1773 "%s: update vsi failed, aq_err=%d\n",
1774 __func__, vsi->back->hw.aq.asq_last_status);
1775 }
1776}
1777
1778/**
1779 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1780 * @netdev: network interface to be adjusted
1781 * @features: netdev features to test if VLAN offload is enabled or not
1782 **/
1783static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1784{
1785 struct i40e_netdev_priv *np = netdev_priv(netdev);
1786 struct i40e_vsi *vsi = np->vsi;
1787
1788 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1789 i40e_vlan_stripping_enable(vsi);
1790 else
1791 i40e_vlan_stripping_disable(vsi);
1792}
1793
1794/**
1795 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1796 * @vsi: the vsi being configured
1797 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1798 **/
1799int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1800{
1801 struct i40e_mac_filter *f, *add_f;
1802 bool is_netdev, is_vf;
41c445ff
JB		 1803
1804 is_vf = (vsi->type == I40E_VSI_SRIOV);
1805 is_netdev = !!(vsi->netdev);
1806
1807 if (is_netdev) {
1808 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1809 is_vf, is_netdev);
1810 if (!add_f) {
1811 dev_info(&vsi->back->pdev->dev,
1812 "Could not add vlan filter %d for %pM\n",
1813 vid, vsi->netdev->dev_addr);
1814 return -ENOMEM;
1815 }
1816 }
1817
1818 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1819 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1820 if (!add_f) {
1821 dev_info(&vsi->back->pdev->dev,
1822 "Could not add vlan filter %d for %pM\n",
1823 vid, f->macaddr);
1824 return -ENOMEM;
1825 }
1826 }
1827
41c445ff
JB		 1828 /* Now if we add a vlan tag, make sure to check if it is the first
1829 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1830 * with 0, so we now accept untagged and specified tagged traffic
1831 * (and not any taged and untagged)
1832 */
1833 if (vid > 0) {
1834 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1835 I40E_VLAN_ANY,
1836 is_vf, is_netdev)) {
1837 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1838 I40E_VLAN_ANY, is_vf, is_netdev);
1839 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1840 is_vf, is_netdev);
1841 if (!add_f) {
1842 dev_info(&vsi->back->pdev->dev,
1843 "Could not add filter 0 for %pM\n",
1844 vsi->netdev->dev_addr);
1845 return -ENOMEM;
1846 }
1847 }
1848
1849 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1850 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1851 is_vf, is_netdev)) {
1852 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1853 is_vf, is_netdev);
1854 add_f = i40e_add_filter(vsi, f->macaddr,
1855 0, is_vf, is_netdev);
1856 if (!add_f) {
1857 dev_info(&vsi->back->pdev->dev,
1858 "Could not add filter 0 for %pM\n",
1859 f->macaddr);
1860 return -ENOMEM;
1861 }
1862 }
1863 }
41c445ff
JB		 1864 }
1865
80f6428f
ASJ		 1866 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1867 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1868 return 0;
1869
1870 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1871}
1872
1873/**
1874 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1875 * @vsi: the vsi being configured
1876 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1877 *
1878 * Return: 0 on success or negative otherwise
41c445ff
JB		 1879 **/
1880int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1881{
1882 struct net_device *netdev = vsi->netdev;
1883 struct i40e_mac_filter *f, *add_f;
1884 bool is_vf, is_netdev;
1885 int filter_count = 0;
41c445ff
JB		 1886
1887 is_vf = (vsi->type == I40E_VSI_SRIOV);
1888 is_netdev = !!(netdev);
1889
1890 if (is_netdev)
1891 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1892
1893 list_for_each_entry(f, &vsi->mac_filter_list, list)
1894 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1895
41c445ff
JB		 1896 /* go through all the filters for this VSI and if there is only
1897 * vid == 0 it means there are no other filters, so vid 0 must
1898 * be replaced with -1. This signifies that we should from now
1899 * on accept any traffic (with any tag present, or untagged)
1900 */
1901 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1902 if (is_netdev) {
1903 if (f->vlan &&
1904 ether_addr_equal(netdev->dev_addr, f->macaddr))
1905 filter_count++;
1906 }
1907
1908 if (f->vlan)
1909 filter_count++;
1910 }
1911
1912 if (!filter_count && is_netdev) {
1913 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1914 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1915 is_vf, is_netdev);
1916 if (!f) {
1917 dev_info(&vsi->back->pdev->dev,
1918 "Could not add filter %d for %pM\n",
1919 I40E_VLAN_ANY, netdev->dev_addr);
1920 return -ENOMEM;
1921 }
1922 }
1923
1924 if (!filter_count) {
1925 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1926 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1927 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1928 is_vf, is_netdev);
1929 if (!add_f) {
1930 dev_info(&vsi->back->pdev->dev,
1931 "Could not add filter %d for %pM\n",
1932 I40E_VLAN_ANY, f->macaddr);
1933 return -ENOMEM;
1934 }
1935 }
1936 }
1937
80f6428f
ASJ		 1938 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1939 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1940 return 0;
1941
41c445ff
JB		 1942 return i40e_sync_vsi_filters(vsi);
1943}
1944
1945/**
1946 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1947 * @netdev: network interface to be adjusted
1948 * @vid: vlan id to be added
078b5876
JB		 1949 *
1950 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1951 **/
1952static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1953 __always_unused __be16 proto, u16 vid)
1954{
1955 struct i40e_netdev_priv *np = netdev_priv(netdev);
1956 struct i40e_vsi *vsi = np->vsi;
078b5876 1957 int ret = 0;
41c445ff
JB		 1958
1959 if (vid > 4095)
078b5876
JB		 1960 return -EINVAL;
1961
1962 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1963
41c445ff
JB		 1964 /* If the network stack called us with vid = 0, we should
1965 * indicate to i40e_vsi_add_vlan() that we want to receive
1966 * any traffic (i.e. with any vlan tag, or untagged)
1967 */
1968 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1969
078b5876
JB		 1970 if (!ret && (vid < VLAN_N_VID))
1971 set_bit(vid, vsi->active_vlans);
41c445ff 1972
078b5876 1973 return ret;
41c445ff
JB		 1974}
1975
1976/**
1977 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1978 * @netdev: network interface to be adjusted
1979 * @vid: vlan id to be removed
078b5876
JB		 1980 *
1981 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1982 **/
1983static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1984 __always_unused __be16 proto, u16 vid)
1985{
1986 struct i40e_netdev_priv *np = netdev_priv(netdev);
1987 struct i40e_vsi *vsi = np->vsi;
1988
078b5876
JB		 1989 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1990
41c445ff
JB		 1991 /* return code is ignored as there is nothing a user
1992 * can do about failure to remove and a log message was
078b5876 1993 * already printed from the other function
41c445ff
JB		 1994 */
1995 i40e_vsi_kill_vlan(vsi, vid);
1996
1997 clear_bit(vid, vsi->active_vlans);
078b5876 1998
41c445ff
JB		 1999 return 0;
2000}
2001
2002/**
2003 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2004 * @vsi: the vsi being brought back up
2005 **/
2006static void i40e_restore_vlan(struct i40e_vsi *vsi)
2007{
2008 u16 vid;
2009
2010 if (!vsi->netdev)
2011 return;
2012
2013 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2014
2015 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2016 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2017 vid);
2018}
2019
2020/**
2021 * i40e_vsi_add_pvid - Add pvid for the VSI
2022 * @vsi: the vsi being adjusted
2023 * @vid: the vlan id to set as a PVID
2024 **/
dcae29be 2025int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2026{
2027 struct i40e_vsi_context ctxt;
dcae29be 2028 i40e_status aq_ret;
41c445ff
JB		 2029
2030 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2031 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2032 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2033 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2034 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2035
2036 ctxt.seid = vsi->seid;
2037 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2038 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2039 if (aq_ret) {
41c445ff
JB		 2040 dev_info(&vsi->back->pdev->dev,
2041 "%s: update vsi failed, aq_err=%d\n",
2042 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2043 return -ENOENT;
41c445ff
JB		 2044 }
2045
dcae29be 2046 return 0;
41c445ff
JB		 2047}
2048
2049/**
2050 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2051 * @vsi: the vsi being adjusted
2052 *
2053 * Just use the vlan_rx_register() service to put it back to normal
2054 **/
2055void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2056{
6c12fcbf
GR		 2057 i40e_vlan_stripping_disable(vsi);
2058
41c445ff 2059 vsi->info.pvid = 0;
41c445ff
JB		 2060}
2061
2062/**
2063 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2064 * @vsi: ptr to the VSI
2065 *
2066 * If this function returns with an error, then it's possible one or
2067 * more of the rings is populated (while the rest are not). It is the
2068 * callers duty to clean those orphaned rings.
2069 *
2070 * Return 0 on success, negative on failure
2071 **/
2072static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2073{
2074 int i, err = 0;
2075
2076 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2077 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2078
2079 return err;
2080}
2081
2082/**
2083 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2084 * @vsi: ptr to the VSI
2085 *
2086 * Free VSI's transmit software resources
2087 **/
2088static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2089{
2090 int i;
2091
8e9dca53
GR		 2092 if (!vsi->tx_rings)
2093 return;
2094
41c445ff 2095 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2096 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2097 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2098}
2099
2100/**
2101 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2102 * @vsi: ptr to the VSI
2103 *
2104 * If this function returns with an error, then it's possible one or
2105 * more of the rings is populated (while the rest are not). It is the
2106 * callers duty to clean those orphaned rings.
2107 *
2108 * Return 0 on success, negative on failure
2109 **/
2110static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2111{
2112 int i, err = 0;
2113
2114 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2115 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2116 return err;
2117}
2118
2119/**
2120 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2121 * @vsi: ptr to the VSI
2122 *
2123 * Free all receive software resources
2124 **/
2125static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2126{
2127 int i;
2128
8e9dca53
GR		 2129 if (!vsi->rx_rings)
2130 return;
2131
41c445ff 2132 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2133 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2134 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2135}
2136
2137/**
2138 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2139 * @ring: The Tx ring to configure
2140 *
2141 * Configure the Tx descriptor ring in the HMC context.
2142 **/
2143static int i40e_configure_tx_ring(struct i40e_ring *ring)
2144{
2145 struct i40e_vsi *vsi = ring->vsi;
2146 u16 pf_q = vsi->base_queue + ring->queue_index;
2147 struct i40e_hw *hw = &vsi->back->hw;
2148 struct i40e_hmc_obj_txq tx_ctx;
2149 i40e_status err = 0;
2150 u32 qtx_ctl = 0;
2151
2152 /* some ATR related tx ring init */
2153 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2154 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2155 ring->atr_count = 0;
2156 } else {
2157 ring->atr_sample_rate = 0;
2158 }
2159
2160 /* initialize XPS */
2161 if (ring->q_vector && ring->netdev &&
2162 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2163 netif_set_xps_queue(ring->netdev,
2164 &ring->q_vector->affinity_mask,
2165 ring->queue_index);
2166
2167 /* clear the context structure first */
2168 memset(&tx_ctx, 0, sizeof(tx_ctx));
2169
2170 tx_ctx.new_context = 1;
2171 tx_ctx.base = (ring->dma / 128);
2172 tx_ctx.qlen = ring->count;
2173 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
beb0dff1
JK		 2174 I40E_FLAG_FDIR_ATR_ENABLED));
2175 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
41c445ff
JB		 2176
2177 /* As part of VSI creation/update, FW allocates certain
2178 * Tx arbitration queue sets for each TC enabled for
2179 * the VSI. The FW returns the handles to these queue
2180 * sets as part of the response buffer to Add VSI,
2181 * Update VSI, etc. AQ commands. It is expected that
2182 * these queue set handles be associated with the Tx
2183 * queues by the driver as part of the TX queue context
2184 * initialization. This has to be done regardless of
2185 * DCB as by default everything is mapped to TC0.
2186 */
2187 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2188 tx_ctx.rdylist_act = 0;
2189
2190 /* clear the context in the HMC */
2191 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2192 if (err) {
2193 dev_info(&vsi->back->pdev->dev,
2194 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2195 ring->queue_index, pf_q, err);
2196 return -ENOMEM;
2197 }
2198
2199 /* set the context in the HMC */
2200 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2201 if (err) {
2202 dev_info(&vsi->back->pdev->dev,
2203 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2204 ring->queue_index, pf_q, err);
2205 return -ENOMEM;
2206 }
2207
2208 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2209 if (vsi->type == I40E_VSI_VMDQ2)
2210 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2211 else
2212 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2213 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2214 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2215 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2216 i40e_flush(hw);
2217
2218 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2219
2220 /* cache tail off for easier writes later */
2221 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2222
2223 return 0;
2224}
2225
2226/**
2227 * i40e_configure_rx_ring - Configure a receive ring context
2228 * @ring: The Rx ring to configure
2229 *
2230 * Configure the Rx descriptor ring in the HMC context.
2231 **/
2232static int i40e_configure_rx_ring(struct i40e_ring *ring)
2233{
2234 struct i40e_vsi *vsi = ring->vsi;
2235 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2236 u16 pf_q = vsi->base_queue + ring->queue_index;
2237 struct i40e_hw *hw = &vsi->back->hw;
2238 struct i40e_hmc_obj_rxq rx_ctx;
2239 i40e_status err = 0;
2240
2241 ring->state = 0;
2242
2243 /* clear the context structure first */
2244 memset(&rx_ctx, 0, sizeof(rx_ctx));
2245
2246 ring->rx_buf_len = vsi->rx_buf_len;
2247 ring->rx_hdr_len = vsi->rx_hdr_len;
2248
2249 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2250 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2251
2252 rx_ctx.base = (ring->dma / 128);
2253 rx_ctx.qlen = ring->count;
2254
2255 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2256 set_ring_16byte_desc_enabled(ring);
2257 rx_ctx.dsize = 0;
2258 } else {
2259 rx_ctx.dsize = 1;
2260 }
2261
2262 rx_ctx.dtype = vsi->dtype;
2263 if (vsi->dtype) {
2264 set_ring_ps_enabled(ring);
2265 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2266 I40E_RX_SPLIT_IP |
2267 I40E_RX_SPLIT_TCP_UDP |
2268 I40E_RX_SPLIT_SCTP;
2269 } else {
2270 rx_ctx.hsplit_0 = 0;
2271 }
2272
2273 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2274 (chain_len * ring->rx_buf_len));
2275 rx_ctx.tphrdesc_ena = 1;
2276 rx_ctx.tphwdesc_ena = 1;
2277 rx_ctx.tphdata_ena = 1;
2278 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2279 if (hw->revision_id == 0)
2280 rx_ctx.lrxqthresh = 0;
2281 else
2282 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2283 rx_ctx.crcstrip = 1;
2284 rx_ctx.l2tsel = 1;
2285 rx_ctx.showiv = 1;
2286
2287 /* clear the context in the HMC */
2288 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2289 if (err) {
2290 dev_info(&vsi->back->pdev->dev,
2291 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2292 ring->queue_index, pf_q, err);
2293 return -ENOMEM;
2294 }
2295
2296 /* set the context in the HMC */
2297 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2298 if (err) {
2299 dev_info(&vsi->back->pdev->dev,
2300 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2301 ring->queue_index, pf_q, err);
2302 return -ENOMEM;
2303 }
2304
2305 /* cache tail for quicker writes, and clear the reg before use */
2306 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2307 writel(0, ring->tail);
2308
2309 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2310
2311 return 0;
2312}
2313
2314/**
2315 * i40e_vsi_configure_tx - Configure the VSI for Tx
2316 * @vsi: VSI structure describing this set of rings and resources
2317 *
2318 * Configure the Tx VSI for operation.
2319 **/
2320static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2321{
2322 int err = 0;
2323 u16 i;
2324
9f65e15b
AD		 2325 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2326 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2327
2328 return err;
2329}
2330
2331/**
2332 * i40e_vsi_configure_rx - Configure the VSI for Rx
2333 * @vsi: the VSI being configured
2334 *
2335 * Configure the Rx VSI for operation.
2336 **/
2337static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2338{
2339 int err = 0;
2340 u16 i;
2341
2342 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2343 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2344 + ETH_FCS_LEN + VLAN_HLEN;
2345 else
2346 vsi->max_frame = I40E_RXBUFFER_2048;
2347
2348 /* figure out correct receive buffer length */
2349 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2350 I40E_FLAG_RX_PS_ENABLED)) {
2351 case I40E_FLAG_RX_1BUF_ENABLED:
2352 vsi->rx_hdr_len = 0;
2353 vsi->rx_buf_len = vsi->max_frame;
2354 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2355 break;
2356 case I40E_FLAG_RX_PS_ENABLED:
2357 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2358 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2359 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2360 break;
2361 default:
2362 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2363 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2364 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2365 break;
2366 }
2367
2368 /* round up for the chip's needs */
2369 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2370 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2371 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2372 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2373
2374 /* set up individual rings */
2375 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2376 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2377
2378 return err;
2379}
2380
2381/**
2382 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2383 * @vsi: ptr to the VSI
2384 **/
2385static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2386{
2387 u16 qoffset, qcount;
2388 int i, n;
2389
2390 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2391 return;
2392
2393 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2394 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2395 continue;
2396
2397 qoffset = vsi->tc_config.tc_info[n].qoffset;
2398 qcount = vsi->tc_config.tc_info[n].qcount;
2399 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2400 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2401 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2402 rx_ring->dcb_tc = n;
2403 tx_ring->dcb_tc = n;
2404 }
2405 }
2406}
2407
2408/**
2409 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2410 * @vsi: ptr to the VSI
2411 **/
2412static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2413{
2414 if (vsi->netdev)
2415 i40e_set_rx_mode(vsi->netdev);
2416}
2417
2418/**
2419 * i40e_vsi_configure - Set up the VSI for action
2420 * @vsi: the VSI being configured
2421 **/
2422static int i40e_vsi_configure(struct i40e_vsi *vsi)
2423{
2424 int err;
2425
2426 i40e_set_vsi_rx_mode(vsi);
2427 i40e_restore_vlan(vsi);
2428 i40e_vsi_config_dcb_rings(vsi);
2429 err = i40e_vsi_configure_tx(vsi);
2430 if (!err)
2431 err = i40e_vsi_configure_rx(vsi);
2432
2433 return err;
2434}
2435
2436/**
2437 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2438 * @vsi: the VSI being configured
2439 **/
2440static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2441{
2442 struct i40e_pf *pf = vsi->back;
2443 struct i40e_q_vector *q_vector;
2444 struct i40e_hw *hw = &pf->hw;
2445 u16 vector;
2446 int i, q;
2447 u32 val;
2448 u32 qp;
2449
2450 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2451 * and PFINT_LNKLSTn registers, e.g.:
2452 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2453 */
2454 qp = vsi->base_queue;
2455 vector = vsi->base_vector;
493fb300
AD		 2456 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2457 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2458 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2459 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2460 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2461 q_vector->rx.itr);
2462 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2463 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2464 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2465 q_vector->tx.itr);
2466
2467 /* Linked list for the queuepairs assigned to this vector */
2468 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2469 for (q = 0; q < q_vector->num_ringpairs; q++) {
2470 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2471 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2472 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2473 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2474 (I40E_QUEUE_TYPE_TX
2475 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2476
2477 wr32(hw, I40E_QINT_RQCTL(qp), val);
2478
2479 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2480 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2481 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2482 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2483 (I40E_QUEUE_TYPE_RX
2484 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2485
2486 /* Terminate the linked list */
2487 if (q == (q_vector->num_ringpairs - 1))
2488 val |= (I40E_QUEUE_END_OF_LIST
2489 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2490
2491 wr32(hw, I40E_QINT_TQCTL(qp), val);
2492 qp++;
2493 }
2494 }
2495
2496 i40e_flush(hw);
2497}
2498
2499/**
2500 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2501 * @hw: ptr to the hardware info
2502 **/
2503static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2504{
2505 u32 val;
2506
2507 /* clear things first */
2508 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2509 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2510
2511 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2512 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2513 I40E_PFINT_ICR0_ENA_GRST_MASK |
2514 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2515 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2516 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2517 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2518 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2519 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2520 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2521
2522 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2523
2524 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2525 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2526 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2527
2528 /* OTHER_ITR_IDX = 0 */
2529 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2530}
2531
2532/**
2533 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2534 * @vsi: the VSI being configured
2535 **/
2536static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2537{
493fb300 2538 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2539 struct i40e_pf *pf = vsi->back;
2540 struct i40e_hw *hw = &pf->hw;
2541 u32 val;
2542
2543 /* set the ITR configuration */
2544 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2545 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2546 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2547 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2548 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2549 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2550
2551 i40e_enable_misc_int_causes(hw);
2552
2553 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2554 wr32(hw, I40E_PFINT_LNKLST0, 0);
2555
2556 /* Associate the queue pair to the vector and enable the q int */
2557 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2558 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2559 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2560
2561 wr32(hw, I40E_QINT_RQCTL(0), val);
2562
2563 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2564 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2565 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2566
2567 wr32(hw, I40E_QINT_TQCTL(0), val);
2568 i40e_flush(hw);
2569}
2570
2ef28cfb
MW		 2571/**
2572 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2573 * @pf: board private structure
2574 **/
2575void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2576{
2577 struct i40e_hw *hw = &pf->hw;
2578
2579 wr32(hw, I40E_PFINT_DYN_CTL0,
2580 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2581 i40e_flush(hw);
2582}
2583
41c445ff
JB		 2584/**
2585 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2586 * @pf: board private structure
2587 **/
116a57d4 2588void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2589{
2590 struct i40e_hw *hw = &pf->hw;
2591 u32 val;
2592
2593 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2594 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2595 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2596
2597 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2598 i40e_flush(hw);
2599}
2600
2601/**
2602 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2603 * @vsi: pointer to a vsi
2604 * @vector: enable a particular Hw Interrupt vector
2605 **/
2606void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2607{
2608 struct i40e_pf *pf = vsi->back;
2609 struct i40e_hw *hw = &pf->hw;
2610 u32 val;
2611
2612 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2613 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2614 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2615 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2616 /* skip the flush */
41c445ff
JB		 2617}
2618
2619/**
2620 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2621 * @irq: interrupt number
2622 * @data: pointer to a q_vector
2623 **/
2624static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2625{
2626 struct i40e_q_vector *q_vector = data;
2627
cd0b6fa6 2628 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2629 return IRQ_HANDLED;
2630
2631 napi_schedule(&q_vector->napi);
2632
2633 return IRQ_HANDLED;
2634}
2635
2636/**
2637 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2638 * @irq: interrupt number
2639 * @data: pointer to a q_vector
2640 **/
2641static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2642{
2643 struct i40e_q_vector *q_vector = data;
2644
cd0b6fa6 2645 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2646 return IRQ_HANDLED;
2647
2648 pr_info("fdir ring cleaning needed\n");
2649
2650 return IRQ_HANDLED;
2651}
2652
2653/**
2654 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2655 * @vsi: the VSI being configured
2656 * @basename: name for the vector
2657 *
2658 * Allocates MSI-X vectors and requests interrupts from the kernel.
2659 **/
2660static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2661{
2662 int q_vectors = vsi->num_q_vectors;
2663 struct i40e_pf *pf = vsi->back;
2664 int base = vsi->base_vector;
2665 int rx_int_idx = 0;
2666 int tx_int_idx = 0;
2667 int vector, err;
2668
2669 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2670 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2671
cd0b6fa6 2672 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2673 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2674 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2675 tx_int_idx++;
cd0b6fa6 2676 } else if (q_vector->rx.ring) {
41c445ff
JB		 2677 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2678 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2679 } else if (q_vector->tx.ring) {
41c445ff
JB		 2680 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2681 "%s-%s-%d", basename, "tx", tx_int_idx++);
2682 } else {
2683 /* skip this unused q_vector */
2684 continue;
2685 }
2686 err = request_irq(pf->msix_entries[base + vector].vector,
2687 vsi->irq_handler,
2688 0,
2689 q_vector->name,
2690 q_vector);
2691 if (err) {
2692 dev_info(&pf->pdev->dev,
2693 "%s: request_irq failed, error: %d\n",
2694 __func__, err);
2695 goto free_queue_irqs;
2696 }
2697 /* assign the mask for this irq */
2698 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2699 &q_vector->affinity_mask);
2700 }
2701
2702 return 0;
2703
2704free_queue_irqs:
2705 while (vector) {
2706 vector--;
2707 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2708 NULL);
2709 free_irq(pf->msix_entries[base + vector].vector,
2710 &(vsi->q_vectors[vector]));
2711 }
2712 return err;
2713}
2714
2715/**
2716 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2717 * @vsi: the VSI being un-configured
2718 **/
2719static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2720{
2721 struct i40e_pf *pf = vsi->back;
2722 struct i40e_hw *hw = &pf->hw;
2723 int base = vsi->base_vector;
2724 int i;
2725
2726 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2727 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2728 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2729 }
2730
2731 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2732 for (i = vsi->base_vector;
2733 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2734 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2735
2736 i40e_flush(hw);
2737 for (i = 0; i < vsi->num_q_vectors; i++)
2738 synchronize_irq(pf->msix_entries[i + base].vector);
2739 } else {
2740 /* Legacy and MSI mode - this stops all interrupt handling */
2741 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2742 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2743 i40e_flush(hw);
2744 synchronize_irq(pf->pdev->irq);
2745 }
2746}
2747
2748/**
2749 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2750 * @vsi: the VSI being configured
2751 **/
2752static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2753{
2754 struct i40e_pf *pf = vsi->back;
2755 int i;
2756
2757 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2758 for (i = vsi->base_vector;
2759 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2760 i40e_irq_dynamic_enable(vsi, i);
2761 } else {
2762 i40e_irq_dynamic_enable_icr0(pf);
2763 }
2764
1022cb6c 2765 i40e_flush(&pf->hw);
41c445ff
JB		 2766 return 0;
2767}
2768
2769/**
2770 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2771 * @pf: board private structure
2772 **/
2773static void i40e_stop_misc_vector(struct i40e_pf *pf)
2774{
2775 /* Disable ICR 0 */
2776 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2777 i40e_flush(&pf->hw);
2778}
2779
2780/**
2781 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2782 * @irq: interrupt number
2783 * @data: pointer to a q_vector
2784 *
2785 * This is the handler used for all MSI/Legacy interrupts, and deals
2786 * with both queue and non-queue interrupts. This is also used in
2787 * MSIX mode to handle the non-queue interrupts.
2788 **/
2789static irqreturn_t i40e_intr(int irq, void *data)
2790{
2791 struct i40e_pf *pf = (struct i40e_pf *)data;
2792 struct i40e_hw *hw = &pf->hw;
5e823066 2793 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2794 u32 icr0, icr0_remaining;
2795 u32 val, ena_mask;
2796
2797 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2798 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2799
116a57d4
SN		 2800 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2801 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2802 goto enable_intr;
41c445ff 2803
cd92e72f
SN		 2804 /* if interrupt but no bits showing, must be SWINT */
2805 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2806 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2807 pf->sw_int_count++;
2808
41c445ff
JB		 2809 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2810 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2811
2812 /* temporarily disable queue cause for NAPI processing */
2813 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2814 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2815 wr32(hw, I40E_QINT_RQCTL(0), qval);
2816
2817 qval = rd32(hw, I40E_QINT_TQCTL(0));
2818 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2819 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2820
2821 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2822 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2823 }
2824
2825 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2826 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2827 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2828 }
2829
2830 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2831 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2832 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2833 }
2834
2835 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2836 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2837 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2838 }
2839
2840 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2841 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2842 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2843 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2844 val = rd32(hw, I40E_GLGEN_RSTAT);
2845 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2846 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2847 if (val == I40E_RESET_CORER)
41c445ff 2848 pf->corer_count++;
d52cf0a9 2849 else if (val == I40E_RESET_GLOBR)
41c445ff 2850 pf->globr_count++;
d52cf0a9 2851 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2852 pf->empr_count++;
2853 }
2854
9c010ee0
ASJ		 2855 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2856 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2857 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2858 }
2859
beb0dff1
JK		 2860 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2861 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2862
2863 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
2864 ena_mask &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
2865 i40e_ptp_tx_hwtstamp(pf);
2866 prttsyn_stat &= ~I40E_PRTTSYN_STAT_0_TXTIME_MASK;
2867 }
2868
2869 wr32(hw, I40E_PRTTSYN_STAT_0, prttsyn_stat);
2870 }
2871
41c445ff
JB		 2872 /* If a critical error is pending we have no choice but to reset the
2873 * device.
2874 * Report and mask out any remaining unexpected interrupts.
2875 */
2876 icr0_remaining = icr0 & ena_mask;
2877 if (icr0_remaining) {
2878 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2879 icr0_remaining);
9c010ee0 2880 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2881 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2882 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2883 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2884 dev_info(&pf->pdev->dev, "device will be reset\n");
2885 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2886 i40e_service_event_schedule(pf);
41c445ff
JB		 2887 }
2888 ena_mask &= ~icr0_remaining;
2889 }
5e823066 2890 ret = IRQ_HANDLED;
41c445ff 2891
5e823066 2892enable_intr:
41c445ff
JB		 2893 /* re-enable interrupt causes */
2894 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2895 if (!test_bit(__I40E_DOWN, &pf->state)) {
2896 i40e_service_event_schedule(pf);
2897 i40e_irq_dynamic_enable_icr0(pf);
2898 }
2899
5e823066 2900 return ret;
41c445ff
JB		 2901}
2902
2903/**
cd0b6fa6 2904 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2905 * @vsi: the VSI being configured
2906 * @v_idx: vector index
cd0b6fa6 2907 * @qp_idx: queue pair index
41c445ff 2908 **/
cd0b6fa6 2909static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2910{
493fb300 2911 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2912 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2913 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2914
2915 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2916 tx_ring->next = q_vector->tx.ring;
2917 q_vector->tx.ring = tx_ring;
41c445ff 2918 q_vector->tx.count++;
cd0b6fa6
AD		 2919
2920 rx_ring->q_vector = q_vector;
2921 rx_ring->next = q_vector->rx.ring;
2922 q_vector->rx.ring = rx_ring;
2923 q_vector->rx.count++;
41c445ff
JB		 2924}
2925
2926/**
2927 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2928 * @vsi: the VSI being configured
2929 *
2930 * This function maps descriptor rings to the queue-specific vectors
2931 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2932 * one vector per queue pair, but on a constrained vector budget, we
2933 * group the queue pairs as "efficiently" as possible.
2934 **/
2935static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2936{
2937 int qp_remaining = vsi->num_queue_pairs;
2938 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2939 int num_ringpairs;
41c445ff
JB		 2940 int v_start = 0;
2941 int qp_idx = 0;
2942
2943 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2944 * group them so there are multiple queues per vector.
2945 */
2946 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2947 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2948
2949 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2950
2951 q_vector->num_ringpairs = num_ringpairs;
2952
2953 q_vector->rx.count = 0;
2954 q_vector->tx.count = 0;
2955 q_vector->rx.ring = NULL;
2956 q_vector->tx.ring = NULL;
2957
2958 while (num_ringpairs--) {
2959 map_vector_to_qp(vsi, v_start, qp_idx);
2960 qp_idx++;
2961 qp_remaining--;
41c445ff
JB		 2962 }
2963 }
2964}
2965
2966/**
2967 * i40e_vsi_request_irq - Request IRQ from the OS
2968 * @vsi: the VSI being configured
2969 * @basename: name for the vector
2970 **/
2971static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2972{
2973 struct i40e_pf *pf = vsi->back;
2974 int err;
2975
2976 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2977 err = i40e_vsi_request_irq_msix(vsi, basename);
2978 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2979 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2980 pf->misc_int_name, pf);
2981 else
2982 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2983 pf->misc_int_name, pf);
2984
2985 if (err)
2986 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2987
2988 return err;
2989}
2990
2991#ifdef CONFIG_NET_POLL_CONTROLLER
2992/**
2993 * i40e_netpoll - A Polling 'interrupt'handler
2994 * @netdev: network interface device structure
2995 *
2996 * This is used by netconsole to send skbs without having to re-enable
2997 * interrupts. It's not called while the normal interrupt routine is executing.
2998 **/
2999static void i40e_netpoll(struct net_device *netdev)
3000{
3001 struct i40e_netdev_priv *np = netdev_priv(netdev);
3002 struct i40e_vsi *vsi = np->vsi;
3003 struct i40e_pf *pf = vsi->back;
3004 int i;
3005
3006 /* if interface is down do nothing */
3007 if (test_bit(__I40E_DOWN, &vsi->state))
3008 return;
3009
3010 pf->flags |= I40E_FLAG_IN_NETPOLL;
3011 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3012 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3013 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3014 } else {
3015 i40e_intr(pf->pdev->irq, netdev);
3016 }
3017 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3018}
3019#endif
3020
3021/**
3022 * i40e_vsi_control_tx - Start or stop a VSI's rings
3023 * @vsi: the VSI being configured
3024 * @enable: start or stop the rings
3025 **/
3026static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3027{
3028 struct i40e_pf *pf = vsi->back;
3029 struct i40e_hw *hw = &pf->hw;
3030 int i, j, pf_q;
3031 u32 tx_reg;
3032
3033 pf_q = vsi->base_queue;
3034 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3035 j = 1000;
3036 do {
3037 usleep_range(1000, 2000);
3038 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3039 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
3040 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
3041
fda972f6
MW		 3042 /* Skip if the queue is already in the requested state */
3043 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3044 continue;
3045 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3046 continue;
41c445ff
JB		 3047
3048 /* turn on/off the queue */
c5c9eb9e
SN		 3049 if (enable) {
3050 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
41c445ff
JB		 3051 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3052 I40E_QTX_ENA_QENA_STAT_MASK;
c5c9eb9e 3053 } else {
41c445ff 3054 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3055 }
41c445ff
JB		 3056
3057 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3058
3059 /* wait for the change to finish */
3060 for (j = 0; j < 10; j++) {
3061 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3062 if (enable) {
3063 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3064 break;
3065 } else {
3066 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3067 break;
3068 }
3069
3070 udelay(10);
3071 }
3072 if (j >= 10) {
3073 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3074 pf_q, (enable ? "en" : "dis"));
3075 return -ETIMEDOUT;
3076 }
3077 }
3078
7134f9ce
JB		 3079 if (hw->revision_id == 0)
3080 mdelay(50);
3081
41c445ff
JB		 3082 return 0;
3083}
3084
3085/**
3086 * i40e_vsi_control_rx - Start or stop a VSI's rings
3087 * @vsi: the VSI being configured
3088 * @enable: start or stop the rings
3089 **/
3090static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3091{
3092 struct i40e_pf *pf = vsi->back;
3093 struct i40e_hw *hw = &pf->hw;
3094 int i, j, pf_q;
3095 u32 rx_reg;
3096
3097 pf_q = vsi->base_queue;
3098 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3099 j = 1000;
3100 do {
3101 usleep_range(1000, 2000);
3102 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3103 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3104 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3105
3106 if (enable) {
3107 /* is STAT set ? */
3108 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3109 continue;
3110 } else {
3111 /* is !STAT set ? */
3112 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3113 continue;
3114 }
3115
3116 /* turn on/off the queue */
3117 if (enable)
3118 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3119 I40E_QRX_ENA_QENA_STAT_MASK;
3120 else
3121 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3122 I40E_QRX_ENA_QENA_STAT_MASK);
3123 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3124
3125 /* wait for the change to finish */
3126 for (j = 0; j < 10; j++) {
3127 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3128
3129 if (enable) {
3130 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3131 break;
3132 } else {
3133 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3134 break;
3135 }
3136
3137 udelay(10);
3138 }
3139 if (j >= 10) {
3140 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3141 pf_q, (enable ? "en" : "dis"));
3142 return -ETIMEDOUT;
3143 }
3144 }
3145
3146 return 0;
3147}
3148
3149/**
3150 * i40e_vsi_control_rings - Start or stop a VSI's rings
3151 * @vsi: the VSI being configured
3152 * @enable: start or stop the rings
3153 **/
fc18eaa0 3154int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3155{
3b867b28 3156 int ret = 0;
41c445ff
JB		 3157
3158 /* do rx first for enable and last for disable */
3159 if (request) {
3160 ret = i40e_vsi_control_rx(vsi, request);
3161 if (ret)
3162 return ret;
3163 ret = i40e_vsi_control_tx(vsi, request);
3164 } else {
3b867b28
ASJ		 3165 /* Ignore return value, we need to shutdown whatever we can */
3166 i40e_vsi_control_tx(vsi, request);
3167 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3168 }
3169
3170 return ret;
3171}
3172
3173/**
3174 * i40e_vsi_free_irq - Free the irq association with the OS
3175 * @vsi: the VSI being configured
3176 **/
3177static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3178{
3179 struct i40e_pf *pf = vsi->back;
3180 struct i40e_hw *hw = &pf->hw;
3181 int base = vsi->base_vector;
3182 u32 val, qp;
3183 int i;
3184
3185 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3186 if (!vsi->q_vectors)
3187 return;
3188
3189 for (i = 0; i < vsi->num_q_vectors; i++) {
3190 u16 vector = i + base;
3191
3192 /* free only the irqs that were actually requested */
78681b1f
SN		 3193 if (!vsi->q_vectors[i] ||
3194 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3195 continue;
3196
3197 /* clear the affinity_mask in the IRQ descriptor */
3198 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3199 NULL);
3200 free_irq(pf->msix_entries[vector].vector,
493fb300 3201 vsi->q_vectors[i]);
41c445ff
JB		 3202
3203 /* Tear down the interrupt queue link list
3204 *
3205 * We know that they come in pairs and always
3206 * the Rx first, then the Tx. To clear the
3207 * link list, stick the EOL value into the
3208 * next_q field of the registers.
3209 */
3210 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3211 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3212 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3213 val |= I40E_QUEUE_END_OF_LIST
3214 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3215 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3216
3217 while (qp != I40E_QUEUE_END_OF_LIST) {
3218 u32 next;
3219
3220 val = rd32(hw, I40E_QINT_RQCTL(qp));
3221
3222 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3223 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3224 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3225 I40E_QINT_RQCTL_INTEVENT_MASK);
3226
3227 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3228 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3229
3230 wr32(hw, I40E_QINT_RQCTL(qp), val);
3231
3232 val = rd32(hw, I40E_QINT_TQCTL(qp));
3233
3234 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3235 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3236
3237 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3238 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3239 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3240 I40E_QINT_TQCTL_INTEVENT_MASK);
3241
3242 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3243 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3244
3245 wr32(hw, I40E_QINT_TQCTL(qp), val);
3246 qp = next;
3247 }
3248 }
3249 } else {
3250 free_irq(pf->pdev->irq, pf);
3251
3252 val = rd32(hw, I40E_PFINT_LNKLST0);
3253 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3254 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3255 val |= I40E_QUEUE_END_OF_LIST
3256 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3257 wr32(hw, I40E_PFINT_LNKLST0, val);
3258
3259 val = rd32(hw, I40E_QINT_RQCTL(qp));
3260 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3261 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3262 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3263 I40E_QINT_RQCTL_INTEVENT_MASK);
3264
3265 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3266 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3267
3268 wr32(hw, I40E_QINT_RQCTL(qp), val);
3269
3270 val = rd32(hw, I40E_QINT_TQCTL(qp));
3271
3272 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3273 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3274 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3275 I40E_QINT_TQCTL_INTEVENT_MASK);
3276
3277 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3278 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3279
3280 wr32(hw, I40E_QINT_TQCTL(qp), val);
3281 }
3282}
3283
493fb300
AD		 3284/**
3285 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3286 * @vsi: the VSI being configured
3287 * @v_idx: Index of vector to be freed
3288 *
3289 * This function frees the memory allocated to the q_vector. In addition if
3290 * NAPI is enabled it will delete any references to the NAPI struct prior
3291 * to freeing the q_vector.
3292 **/
3293static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3294{
3295 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3296 struct i40e_ring *ring;
493fb300
AD		 3297
3298 if (!q_vector)
3299 return;
3300
3301 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3302 i40e_for_each_ring(ring, q_vector->tx)
3303 ring->q_vector = NULL;
3304
3305 i40e_for_each_ring(ring, q_vector->rx)
3306 ring->q_vector = NULL;
493fb300
AD		 3307
3308 /* only VSI w/ an associated netdev is set up w/ NAPI */
3309 if (vsi->netdev)
3310 netif_napi_del(&q_vector->napi);
3311
3312 vsi->q_vectors[v_idx] = NULL;
3313
3314 kfree_rcu(q_vector, rcu);
3315}
3316
41c445ff
JB		 3317/**
3318 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3319 * @vsi: the VSI being un-configured
3320 *
3321 * This frees the memory allocated to the q_vectors and
3322 * deletes references to the NAPI struct.
3323 **/
3324static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3325{
3326 int v_idx;
3327
493fb300
AD		 3328 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3329 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3330}
3331
3332/**
3333 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3334 * @pf: board private structure
3335 **/
3336static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3337{
3338 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3339 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3340 pci_disable_msix(pf->pdev);
3341 kfree(pf->msix_entries);
3342 pf->msix_entries = NULL;
3343 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3344 pci_disable_msi(pf->pdev);
3345 }
3346 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3347}
3348
3349/**
3350 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3351 * @pf: board private structure
3352 *
3353 * We go through and clear interrupt specific resources and reset the structure
3354 * to pre-load conditions
3355 **/
3356static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3357{
3358 int i;
3359
3360 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3361 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3362 if (pf->vsi[i])
3363 i40e_vsi_free_q_vectors(pf->vsi[i]);
3364 i40e_reset_interrupt_capability(pf);
3365}
3366
3367/**
3368 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3369 * @vsi: the VSI being configured
3370 **/
3371static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3372{
3373 int q_idx;
3374
3375 if (!vsi->netdev)
3376 return;
3377
3378 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3379 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3380}
3381
3382/**
3383 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3384 * @vsi: the VSI being configured
3385 **/
3386static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3387{
3388 int q_idx;
3389
3390 if (!vsi->netdev)
3391 return;
3392
3393 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3394 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3395}
3396
3397/**
3398 * i40e_quiesce_vsi - Pause a given VSI
3399 * @vsi: the VSI being paused
3400 **/
3401static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3402{
3403 if (test_bit(__I40E_DOWN, &vsi->state))
3404 return;
3405
3406 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3407 if (vsi->netdev && netif_running(vsi->netdev)) {
3408 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3409 } else {
3410 set_bit(__I40E_DOWN, &vsi->state);
3411 i40e_down(vsi);
3412 }
3413}
3414
3415/**
3416 * i40e_unquiesce_vsi - Resume a given VSI
3417 * @vsi: the VSI being resumed
3418 **/
3419static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3420{
3421 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3422 return;
3423
3424 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3425 if (vsi->netdev && netif_running(vsi->netdev))
3426 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3427 else
3428 i40e_up(vsi); /* this clears the DOWN bit */
3429}
3430
3431/**
3432 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3433 * @pf: the PF
3434 **/
3435static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3436{
3437 int v;
3438
3439 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3440 if (pf->vsi[v])
3441 i40e_quiesce_vsi(pf->vsi[v]);
3442 }
3443}
3444
3445/**
3446 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3447 * @pf: the PF
3448 **/
3449static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3450{
3451 int v;
3452
3453 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3454 if (pf->vsi[v])
3455 i40e_unquiesce_vsi(pf->vsi[v]);
3456 }
3457}
3458
3459/**
3460 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3461 * @dcbcfg: the corresponding DCBx configuration structure
3462 *
3463 * Return the number of TCs from given DCBx configuration
3464 **/
3465static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3466{
078b5876
JB		 3467 u8 num_tc = 0;
3468 int i;
41c445ff
JB		 3469
3470 /* Scan the ETS Config Priority Table to find
3471 * traffic class enabled for a given priority
3472 * and use the traffic class index to get the
3473 * number of traffic classes enabled
3474 */
3475 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3476 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3477 num_tc = dcbcfg->etscfg.prioritytable[i];
3478 }
3479
3480 /* Traffic class index starts from zero so
3481 * increment to return the actual count
3482 */
078b5876 3483 return num_tc + 1;
41c445ff
JB		 3484}
3485
3486/**
3487 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3488 * @dcbcfg: the corresponding DCBx configuration structure
3489 *
3490 * Query the current DCB configuration and return the number of
3491 * traffic classes enabled from the given DCBX config
3492 **/
3493static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3494{
3495 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3496 u8 enabled_tc = 1;
3497 u8 i;
3498
3499 for (i = 0; i < num_tc; i++)
3500 enabled_tc |= 1 << i;
3501
3502 return enabled_tc;
3503}
3504
3505/**
3506 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3507 * @pf: PF being queried
3508 *
3509 * Return number of traffic classes enabled for the given PF
3510 **/
3511static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3512{
3513 struct i40e_hw *hw = &pf->hw;
3514 u8 i, enabled_tc;
3515 u8 num_tc = 0;
3516 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3517
3518 /* If DCB is not enabled then always in single TC */
3519 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3520 return 1;
3521
3522 /* MFP mode return count of enabled TCs for this PF */
3523 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3524 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3525 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3526 if (enabled_tc & (1 << i))
3527 num_tc++;
3528 }
3529 return num_tc;
3530 }
3531
3532 /* SFP mode will be enabled for all TCs on port */
3533 return i40e_dcb_get_num_tc(dcbcfg);
3534}
3535
3536/**
3537 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3538 * @pf: PF being queried
3539 *
3540 * Return a bitmap for first enabled traffic class for this PF.
3541 **/
3542static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3543{
3544 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3545 u8 i = 0;
3546
3547 if (!enabled_tc)
3548 return 0x1; /* TC0 */
3549
3550 /* Find the first enabled TC */
3551 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3552 if (enabled_tc & (1 << i))
3553 break;
3554 }
3555
3556 return 1 << i;
3557}
3558
3559/**
3560 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3561 * @pf: PF being queried
3562 *
3563 * Return a bitmap for enabled traffic classes for this PF.
3564 **/
3565static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3566{
3567 /* If DCB is not enabled for this PF then just return default TC */
3568 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3569 return i40e_pf_get_default_tc(pf);
3570
3571 /* MFP mode will have enabled TCs set by FW */
3572 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3573 return pf->hw.func_caps.enabled_tcmap;
3574
3575 /* SFP mode we want PF to be enabled for all TCs */
3576 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3577}
3578
3579/**
3580 * i40e_vsi_get_bw_info - Query VSI BW Information
3581 * @vsi: the VSI being queried
3582 *
3583 * Returns 0 on success, negative value on failure
3584 **/
3585static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3586{
3587 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3588 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3589 struct i40e_pf *pf = vsi->back;
3590 struct i40e_hw *hw = &pf->hw;
dcae29be 3591 i40e_status aq_ret;
41c445ff 3592 u32 tc_bw_max;
41c445ff
JB		 3593 int i;
3594
3595 /* Get the VSI level BW configuration */
dcae29be
JB		 3596 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3597 if (aq_ret) {
41c445ff
JB		 3598 dev_info(&pf->pdev->dev,
3599 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3600 aq_ret, pf->hw.aq.asq_last_status);
3601 return -EINVAL;
41c445ff
JB		 3602 }
3603
3604 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3605 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3606 NULL);
3607 if (aq_ret) {
41c445ff
JB		 3608 dev_info(&pf->pdev->dev,
3609 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3610 aq_ret, pf->hw.aq.asq_last_status);
3611 return -EINVAL;
41c445ff
JB		 3612 }
3613
3614 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3615 dev_info(&pf->pdev->dev,
3616 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3617 bw_config.tc_valid_bits,
3618 bw_ets_config.tc_valid_bits);
3619 /* Still continuing */
3620 }
3621
3622 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3623 vsi->bw_max_quanta = bw_config.max_bw;
3624 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3625 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3626 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3627 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3628 vsi->bw_ets_limit_credits[i] =
3629 le16_to_cpu(bw_ets_config.credits[i]);
3630 /* 3 bits out of 4 for each TC */
3631 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3632 }
078b5876 3633
dcae29be 3634 return 0;
41c445ff
JB		 3635}
3636
3637/**
3638 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3639 * @vsi: the VSI being configured
3640 * @enabled_tc: TC bitmap
3641 * @bw_credits: BW shared credits per TC
3642 *
3643 * Returns 0 on success, negative value on failure
3644 **/
dcae29be 3645static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3646 u8 *bw_share)
3647{
3648 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3649 i40e_status aq_ret;
3650 int i;
41c445ff
JB		 3651
3652 bw_data.tc_valid_bits = enabled_tc;
3653 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3654 bw_data.tc_bw_credits[i] = bw_share[i];
3655
dcae29be
JB		 3656 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3657 NULL);
3658 if (aq_ret) {
41c445ff
JB		 3659 dev_info(&vsi->back->pdev->dev,
3660 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3661 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3662 return -EINVAL;
41c445ff
JB		 3663 }
3664
3665 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3666 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3667
dcae29be 3668 return 0;
41c445ff
JB		 3669}
3670
3671/**
3672 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3673 * @vsi: the VSI being configured
3674 * @enabled_tc: TC map to be enabled
3675 *
3676 **/
3677static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3678{
3679 struct net_device *netdev = vsi->netdev;
3680 struct i40e_pf *pf = vsi->back;
3681 struct i40e_hw *hw = &pf->hw;
3682 u8 netdev_tc = 0;
3683 int i;
3684 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3685
3686 if (!netdev)
3687 return;
3688
3689 if (!enabled_tc) {
3690 netdev_reset_tc(netdev);
3691 return;
3692 }
3693
3694 /* Set up actual enabled TCs on the VSI */
3695 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3696 return;
3697
3698 /* set per TC queues for the VSI */
3699 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3700 /* Only set TC queues for enabled tcs
3701 *
3702 * e.g. For a VSI that has TC0 and TC3 enabled the
3703 * enabled_tc bitmap would be 0x00001001; the driver
3704 * will set the numtc for netdev as 2 that will be
3705 * referenced by the netdev layer as TC 0 and 1.
3706 */
3707 if (vsi->tc_config.enabled_tc & (1 << i))
3708 netdev_set_tc_queue(netdev,
3709 vsi->tc_config.tc_info[i].netdev_tc,
3710 vsi->tc_config.tc_info[i].qcount,
3711 vsi->tc_config.tc_info[i].qoffset);
3712 }
3713
3714 /* Assign UP2TC map for the VSI */
3715 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3716 /* Get the actual TC# for the UP */
3717 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3718 /* Get the mapped netdev TC# for the UP */
3719 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3720 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3721 }
3722}
3723
3724/**
3725 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3726 * @vsi: the VSI being configured
3727 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3728 **/
3729static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3730 struct i40e_vsi_context *ctxt)
3731{
3732 /* copy just the sections touched not the entire info
3733 * since not all sections are valid as returned by
3734 * update vsi params
3735 */
3736 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3737 memcpy(&vsi->info.queue_mapping,
3738 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3739 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3740 sizeof(vsi->info.tc_mapping));
3741}
3742
3743/**
3744 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3745 * @vsi: VSI to be configured
3746 * @enabled_tc: TC bitmap
3747 *
3748 * This configures a particular VSI for TCs that are mapped to the
3749 * given TC bitmap. It uses default bandwidth share for TCs across
3750 * VSIs to configure TC for a particular VSI.
3751 *
3752 * NOTE:
3753 * It is expected that the VSI queues have been quisced before calling
3754 * this function.
3755 **/
3756static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3757{
3758 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3759 struct i40e_vsi_context ctxt;
3760 int ret = 0;
3761 int i;
3762
3763 /* Check if enabled_tc is same as existing or new TCs */
3764 if (vsi->tc_config.enabled_tc == enabled_tc)
3765 return ret;
3766
3767 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3768 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3769 if (enabled_tc & (1 << i))
3770 bw_share[i] = 1;
3771 }
3772
3773 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3774 if (ret) {
3775 dev_info(&vsi->back->pdev->dev,
3776 "Failed configuring TC map %d for VSI %d\n",
3777 enabled_tc, vsi->seid);
3778 goto out;
3779 }
3780
3781 /* Update Queue Pairs Mapping for currently enabled UPs */
3782 ctxt.seid = vsi->seid;
3783 ctxt.pf_num = vsi->back->hw.pf_id;
3784 ctxt.vf_num = 0;
3785 ctxt.uplink_seid = vsi->uplink_seid;
3786 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3787 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3788
3789 /* Update the VSI after updating the VSI queue-mapping information */
3790 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3791 if (ret) {
3792 dev_info(&vsi->back->pdev->dev,
3793 "update vsi failed, aq_err=%d\n",
3794 vsi->back->hw.aq.asq_last_status);
3795 goto out;
3796 }
3797 /* update the local VSI info with updated queue map */
3798 i40e_vsi_update_queue_map(vsi, &ctxt);
3799 vsi->info.valid_sections = 0;
3800
3801 /* Update current VSI BW information */
3802 ret = i40e_vsi_get_bw_info(vsi);
3803 if (ret) {
3804 dev_info(&vsi->back->pdev->dev,
3805 "Failed updating vsi bw info, aq_err=%d\n",
3806 vsi->back->hw.aq.asq_last_status);
3807 goto out;
3808 }
3809
3810 /* Update the netdev TC setup */
3811 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3812out:
3813 return ret;
3814}
3815
3816/**
3817 * i40e_up_complete - Finish the last steps of bringing up a connection
3818 * @vsi: the VSI being configured
3819 **/
3820static int i40e_up_complete(struct i40e_vsi *vsi)
3821{
3822 struct i40e_pf *pf = vsi->back;
3823 int err;
3824
3825 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3826 i40e_vsi_configure_msix(vsi);
3827 else
3828 i40e_configure_msi_and_legacy(vsi);
3829
3830 /* start rings */
3831 err = i40e_vsi_control_rings(vsi, true);
3832 if (err)
3833 return err;
3834
3835 clear_bit(__I40E_DOWN, &vsi->state);
3836 i40e_napi_enable_all(vsi);
3837 i40e_vsi_enable_irq(vsi);
3838
3839 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3840 (vsi->netdev)) {
6d779b41 3841 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3842 netif_tx_start_all_queues(vsi->netdev);
3843 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3844 } else if (vsi->netdev) {
3845 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3846 }
3847 i40e_service_event_schedule(pf);
3848
3849 return 0;
3850}
3851
3852/**
3853 * i40e_vsi_reinit_locked - Reset the VSI
3854 * @vsi: the VSI being configured
3855 *
3856 * Rebuild the ring structs after some configuration
3857 * has changed, e.g. MTU size.
3858 **/
3859static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3860{
3861 struct i40e_pf *pf = vsi->back;
3862
3863 WARN_ON(in_interrupt());
3864 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3865 usleep_range(1000, 2000);
3866 i40e_down(vsi);
3867
3868 /* Give a VF some time to respond to the reset. The
3869 * two second wait is based upon the watchdog cycle in
3870 * the VF driver.
3871 */
3872 if (vsi->type == I40E_VSI_SRIOV)
3873 msleep(2000);
3874 i40e_up(vsi);
3875 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3876}
3877
3878/**
3879 * i40e_up - Bring the connection back up after being down
3880 * @vsi: the VSI being configured
3881 **/
3882int i40e_up(struct i40e_vsi *vsi)
3883{
3884 int err;
3885
3886 err = i40e_vsi_configure(vsi);
3887 if (!err)
3888 err = i40e_up_complete(vsi);
3889
3890 return err;
3891}
3892
3893/**
3894 * i40e_down - Shutdown the connection processing
3895 * @vsi: the VSI being stopped
3896 **/
3897void i40e_down(struct i40e_vsi *vsi)
3898{
3899 int i;
3900
3901 /* It is assumed that the caller of this function
3902 * sets the vsi->state __I40E_DOWN bit.
3903 */
3904 if (vsi->netdev) {
3905 netif_carrier_off(vsi->netdev);
3906 netif_tx_disable(vsi->netdev);
3907 }
3908 i40e_vsi_disable_irq(vsi);
3909 i40e_vsi_control_rings(vsi, false);
3910 i40e_napi_disable_all(vsi);
3911
3912 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3913 i40e_clean_tx_ring(vsi->tx_rings[i]);
3914 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3915 }
3916}
3917
3918/**
3919 * i40e_setup_tc - configure multiple traffic classes
3920 * @netdev: net device to configure
3921 * @tc: number of traffic classes to enable
3922 **/
3923static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3924{
3925 struct i40e_netdev_priv *np = netdev_priv(netdev);
3926 struct i40e_vsi *vsi = np->vsi;
3927 struct i40e_pf *pf = vsi->back;
3928 u8 enabled_tc = 0;
3929 int ret = -EINVAL;
3930 int i;
3931
3932 /* Check if DCB enabled to continue */
3933 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3934 netdev_info(netdev, "DCB is not enabled for adapter\n");
3935 goto exit;
3936 }
3937
3938 /* Check if MFP enabled */
3939 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3940 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3941 goto exit;
3942 }
3943
3944 /* Check whether tc count is within enabled limit */
3945 if (tc > i40e_pf_get_num_tc(pf)) {
3946 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3947 goto exit;
3948 }
3949
3950 /* Generate TC map for number of tc requested */
3951 for (i = 0; i < tc; i++)
3952 enabled_tc |= (1 << i);
3953
3954 /* Requesting same TC configuration as already enabled */
3955 if (enabled_tc == vsi->tc_config.enabled_tc)
3956 return 0;
3957
3958 /* Quiesce VSI queues */
3959 i40e_quiesce_vsi(vsi);
3960
3961 /* Configure VSI for enabled TCs */
3962 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3963 if (ret) {
3964 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3965 vsi->seid);
3966 goto exit;
3967 }
3968
3969 /* Unquiesce VSI */
3970 i40e_unquiesce_vsi(vsi);
3971
3972exit:
3973 return ret;
3974}
3975
3976/**
3977 * i40e_open - Called when a network interface is made active
3978 * @netdev: network interface device structure
3979 *
3980 * The open entry point is called when a network interface is made
3981 * active by the system (IFF_UP). At this point all resources needed
3982 * for transmit and receive operations are allocated, the interrupt
3983 * handler is registered with the OS, the netdev watchdog subtask is
3984 * enabled, and the stack is notified that the interface is ready.
3985 *
3986 * Returns 0 on success, negative value on failure
3987 **/
3988static int i40e_open(struct net_device *netdev)
3989{
3990 struct i40e_netdev_priv *np = netdev_priv(netdev);
3991 struct i40e_vsi *vsi = np->vsi;
3992 struct i40e_pf *pf = vsi->back;
3993 char int_name[IFNAMSIZ];
3994 int err;
3995
3996 /* disallow open during test */
3997 if (test_bit(__I40E_TESTING, &pf->state))
3998 return -EBUSY;
3999
4000 netif_carrier_off(netdev);
4001
4002 /* allocate descriptors */
4003 err = i40e_vsi_setup_tx_resources(vsi);
4004 if (err)
4005 goto err_setup_tx;
4006 err = i40e_vsi_setup_rx_resources(vsi);
4007 if (err)
4008 goto err_setup_rx;
4009
4010 err = i40e_vsi_configure(vsi);
4011 if (err)
4012 goto err_setup_rx;
4013
4014 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4015 dev_driver_string(&pf->pdev->dev), netdev->name);
4016 err = i40e_vsi_request_irq(vsi, int_name);
4017 if (err)
4018 goto err_setup_rx;
4019
25946ddb 4020 /* Notify the stack of the actual queue counts. */
d7397644 4021 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4022 if (err)
4023 goto err_set_queues;
4024
d7397644 4025 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 4026 if (err)
4027 goto err_set_queues;
4028
41c445ff
JB		 4029 err = i40e_up_complete(vsi);
4030 if (err)
4031 goto err_up_complete;
4032
a1c9a9d9
JK		 4033#ifdef CONFIG_I40E_VXLAN
4034 vxlan_get_rx_port(netdev);
4035#endif
41c445ff
JB		 4036
4037 return 0;
4038
4039err_up_complete:
4040 i40e_down(vsi);
25946ddb 4041err_set_queues:
41c445ff
JB		 4042 i40e_vsi_free_irq(vsi);
4043err_setup_rx:
4044 i40e_vsi_free_rx_resources(vsi);
4045err_setup_tx:
4046 i40e_vsi_free_tx_resources(vsi);
4047 if (vsi == pf->vsi[pf->lan_vsi])
4048 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4049
4050 return err;
4051}
4052
4053/**
4054 * i40e_close - Disables a network interface
4055 * @netdev: network interface device structure
4056 *
4057 * The close entry point is called when an interface is de-activated
4058 * by the OS. The hardware is still under the driver's control, but
4059 * this netdev interface is disabled.
4060 *
4061 * Returns 0, this is not allowed to fail
4062 **/
4063static int i40e_close(struct net_device *netdev)
4064{
4065 struct i40e_netdev_priv *np = netdev_priv(netdev);
4066 struct i40e_vsi *vsi = np->vsi;
4067
4068 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4069 return 0;
4070
4071 i40e_down(vsi);
4072 i40e_vsi_free_irq(vsi);
4073
4074 i40e_vsi_free_tx_resources(vsi);
4075 i40e_vsi_free_rx_resources(vsi);
4076
4077 return 0;
4078}
4079
4080/**
4081 * i40e_do_reset - Start a PF or Core Reset sequence
4082 * @pf: board private structure
4083 * @reset_flags: which reset is requested
4084 *
4085 * The essential difference in resets is that the PF Reset
4086 * doesn't clear the packet buffers, doesn't reset the PE
4087 * firmware, and doesn't bother the other PFs on the chip.
4088 **/
4089void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4090{
4091 u32 val;
4092
4093 WARN_ON(in_interrupt());
4094
4095 /* do the biggest reset indicated */
4096 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4097
4098 /* Request a Global Reset
4099 *
4100 * This will start the chip's countdown to the actual full
4101 * chip reset event, and a warning interrupt to be sent
4102 * to all PFs, including the requestor. Our handler
4103 * for the warning interrupt will deal with the shutdown
4104 * and recovery of the switch setup.
4105 */
4106 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4107 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4108 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4109 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4110
4111 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4112
4113 /* Request a Core Reset
4114 *
4115 * Same as Global Reset, except does *not* include the MAC/PHY
4116 */
4117 dev_info(&pf->pdev->dev, "CoreR requested\n");
4118 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4119 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4120 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4121 i40e_flush(&pf->hw);
4122
7823fe34
SN		 4123 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4124
4125 /* Request a Firmware Reset
4126 *
4127 * Same as Global reset, plus restarting the
4128 * embedded firmware engine.
4129 */
4130 /* enable EMP Reset */
4131 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4132 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4133 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4134
4135 /* force the reset */
4136 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4137 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4138 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4139 i40e_flush(&pf->hw);
4140
41c445ff
JB		 4141 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4142
4143 /* Request a PF Reset
4144 *
4145 * Resets only the PF-specific registers
4146 *
4147 * This goes directly to the tear-down and rebuild of
4148 * the switch, since we need to do all the recovery as
4149 * for the Core Reset.
4150 */
4151 dev_info(&pf->pdev->dev, "PFR requested\n");
4152 i40e_handle_reset_warning(pf);
4153
4154 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4155 int v;
4156
4157 /* Find the VSI(s) that requested a re-init */
4158 dev_info(&pf->pdev->dev,
4159 "VSI reinit requested\n");
4160 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4161 struct i40e_vsi *vsi = pf->vsi[v];
4162 if (vsi != NULL &&
4163 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4164 i40e_vsi_reinit_locked(pf->vsi[v]);
4165 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4166 }
4167 }
4168
4169 /* no further action needed, so return now */
4170 return;
4171 } else {
4172 dev_info(&pf->pdev->dev,
4173 "bad reset request 0x%08x\n", reset_flags);
4174 return;
4175 }
4176}
4177
23326186
ASJ		 4178/**
4179 * i40e_do_reset_safe - Protected reset path for userland calls.
4180 * @pf: board private structure
4181 * @reset_flags: which reset is requested
4182 *
4183 **/
4184void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4185{
4186 rtnl_lock();
4187 i40e_do_reset(pf, reset_flags);
4188 rtnl_unlock();
4189}
4190
41c445ff
JB		 4191/**
4192 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4193 * @pf: board private structure
4194 * @e: event info posted on ARQ
4195 *
4196 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4197 * and VF queues
4198 **/
4199static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4200 struct i40e_arq_event_info *e)
4201{
4202 struct i40e_aqc_lan_overflow *data =
4203 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4204 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4205 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4206 struct i40e_hw *hw = &pf->hw;
4207 struct i40e_vf *vf;
4208 u16 vf_id;
4209
4210 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4211 __func__, queue, qtx_ctl);
4212
4213 /* Queue belongs to VF, find the VF and issue VF reset */
4214 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4215 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4216 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4217 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4218 vf_id -= hw->func_caps.vf_base_id;
4219 vf = &pf->vf[vf_id];
4220 i40e_vc_notify_vf_reset(vf);
4221 /* Allow VF to process pending reset notification */
4222 msleep(20);
4223 i40e_reset_vf(vf, false);
4224 }
4225}
4226
4227/**
4228 * i40e_service_event_complete - Finish up the service event
4229 * @pf: board private structure
4230 **/
4231static void i40e_service_event_complete(struct i40e_pf *pf)
4232{
4233 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4234
4235 /* flush memory to make sure state is correct before next watchog */
4236 smp_mb__before_clear_bit();
4237 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4238}
4239
4240/**
4241 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4242 * @pf: board private structure
4243 **/
4244static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4245{
4246 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4247 return;
4248
4249 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4250
4251 /* if interface is down do nothing */
4252 if (test_bit(__I40E_DOWN, &pf->state))
4253 return;
4254}
4255
4256/**
4257 * i40e_vsi_link_event - notify VSI of a link event
4258 * @vsi: vsi to be notified
4259 * @link_up: link up or down
4260 **/
4261static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4262{
4263 if (!vsi)
4264 return;
4265
4266 switch (vsi->type) {
4267 case I40E_VSI_MAIN:
4268 if (!vsi->netdev || !vsi->netdev_registered)
4269 break;
4270
4271 if (link_up) {
4272 netif_carrier_on(vsi->netdev);
4273 netif_tx_wake_all_queues(vsi->netdev);
4274 } else {
4275 netif_carrier_off(vsi->netdev);
4276 netif_tx_stop_all_queues(vsi->netdev);
4277 }
4278 break;
4279
4280 case I40E_VSI_SRIOV:
4281 break;
4282
4283 case I40E_VSI_VMDQ2:
4284 case I40E_VSI_CTRL:
4285 case I40E_VSI_MIRROR:
4286 default:
4287 /* there is no notification for other VSIs */
4288 break;
4289 }
4290}
4291
4292/**
4293 * i40e_veb_link_event - notify elements on the veb of a link event
4294 * @veb: veb to be notified
4295 * @link_up: link up or down
4296 **/
4297static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4298{
4299 struct i40e_pf *pf;
4300 int i;
4301
4302 if (!veb || !veb->pf)
4303 return;
4304 pf = veb->pf;
4305
4306 /* depth first... */
4307 for (i = 0; i < I40E_MAX_VEB; i++)
4308 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4309 i40e_veb_link_event(pf->veb[i], link_up);
4310
4311 /* ... now the local VSIs */
4312 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4313 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4314 i40e_vsi_link_event(pf->vsi[i], link_up);
4315}
4316
4317/**
4318 * i40e_link_event - Update netif_carrier status
4319 * @pf: board private structure
4320 **/
4321static void i40e_link_event(struct i40e_pf *pf)
4322{
4323 bool new_link, old_link;
4324
4325 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4326 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4327
4328 if (new_link == old_link)
4329 return;
4330
6d779b41
AS		 4331 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4332 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4333 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4334
4335 /* Notify the base of the switch tree connected to
4336 * the link. Floating VEBs are not notified.
4337 */
4338 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4339 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4340 else
4341 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4342
4343 if (pf->vf)
4344 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4345
4346 if (pf->flags & I40E_FLAG_PTP)
4347 i40e_ptp_set_increment(pf);
41c445ff
JB		 4348}
4349
4350/**
4351 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4352 * @pf: board private structure
4353 *
4354 * Set the per-queue flags to request a check for stuck queues in the irq
4355 * clean functions, then force interrupts to be sure the irq clean is called.
4356 **/
4357static void i40e_check_hang_subtask(struct i40e_pf *pf)
4358{
4359 int i, v;
4360
4361 /* If we're down or resetting, just bail */
4362 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4363 return;
4364
4365 /* for each VSI/netdev
4366 * for each Tx queue
4367 * set the check flag
4368 * for each q_vector
4369 * force an interrupt
4370 */
4371 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4372 struct i40e_vsi *vsi = pf->vsi[v];
4373 int armed = 0;
4374
4375 if (!pf->vsi[v] ||
4376 test_bit(__I40E_DOWN, &vsi->state) ||
4377 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4378 continue;
4379
4380 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4381 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4382 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4383 &vsi->tx_rings[i]->state))
41c445ff
JB		 4384 armed++;
4385 }
4386
4387 if (armed) {
4388 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4389 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4390 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4391 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4392 } else {
4393 u16 vec = vsi->base_vector - 1;
4394 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4395 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4396 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4397 wr32(&vsi->back->hw,
4398 I40E_PFINT_DYN_CTLN(vec), val);
4399 }
4400 i40e_flush(&vsi->back->hw);
4401 }
4402 }
4403}
4404
4405/**
4406 * i40e_watchdog_subtask - Check and bring link up
4407 * @pf: board private structure
4408 **/
4409static void i40e_watchdog_subtask(struct i40e_pf *pf)
4410{
4411 int i;
4412
4413 /* if interface is down do nothing */
4414 if (test_bit(__I40E_DOWN, &pf->state) ||
4415 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4416 return;
4417
4418 /* Update the stats for active netdevs so the network stack
4419 * can look at updated numbers whenever it cares to
4420 */
4421 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4422 if (pf->vsi[i] && pf->vsi[i]->netdev)
4423 i40e_update_stats(pf->vsi[i]);
4424
4425 /* Update the stats for the active switching components */
4426 for (i = 0; i < I40E_MAX_VEB; i++)
4427 if (pf->veb[i])
4428 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 4429
4430 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 4431}
4432
4433/**
4434 * i40e_reset_subtask - Set up for resetting the device and driver
4435 * @pf: board private structure
4436 **/
4437static void i40e_reset_subtask(struct i40e_pf *pf)
4438{
4439 u32 reset_flags = 0;
4440
23326186 4441 rtnl_lock();
41c445ff
JB		 4442 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4443 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4444 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4445 }
4446 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4447 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4448 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4449 }
4450 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4451 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4452 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4453 }
4454 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4455 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4456 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4457 }
4458
4459 /* If there's a recovery already waiting, it takes
4460 * precedence before starting a new reset sequence.
4461 */
4462 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4463 i40e_handle_reset_warning(pf);
23326186 4464 goto unlock;
41c445ff
JB		 4465 }
4466
4467 /* If we're already down or resetting, just bail */
4468 if (reset_flags &&
4469 !test_bit(__I40E_DOWN, &pf->state) &&
4470 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4471 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4472
4473unlock:
4474 rtnl_unlock();
41c445ff
JB		 4475}
4476
4477/**
4478 * i40e_handle_link_event - Handle link event
4479 * @pf: board private structure
4480 * @e: event info posted on ARQ
4481 **/
4482static void i40e_handle_link_event(struct i40e_pf *pf,
4483 struct i40e_arq_event_info *e)
4484{
4485 struct i40e_hw *hw = &pf->hw;
4486 struct i40e_aqc_get_link_status *status =
4487 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4488 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4489
4490 /* save off old link status information */
4491 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4492 sizeof(pf->hw.phy.link_info_old));
4493
4494 /* update link status */
4495 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4496 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4497 hw_link_info->link_info = status->link_info;
4498 hw_link_info->an_info = status->an_info;
4499 hw_link_info->ext_info = status->ext_info;
4500 hw_link_info->lse_enable =
4501 le16_to_cpu(status->command_flags) &
4502 I40E_AQ_LSE_ENABLE;
4503
4504 /* process the event */
4505 i40e_link_event(pf);
4506
4507 /* Do a new status request to re-enable LSE reporting
4508 * and load new status information into the hw struct,
4509 * then see if the status changed while processing the
4510 * initial event.
4511 */
4512 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4513 i40e_link_event(pf);
4514}
4515
4516/**
4517 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4518 * @pf: board private structure
4519 **/
4520static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4521{
4522 struct i40e_arq_event_info event;
4523 struct i40e_hw *hw = &pf->hw;
4524 u16 pending, i = 0;
4525 i40e_status ret;
4526 u16 opcode;
4527 u32 val;
4528
4529 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4530 return;
4531
3197ce22 4532 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4533 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4534 if (!event.msg_buf)
4535 return;
4536
4537 do {
2f019123 4538 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4539 ret = i40e_clean_arq_element(hw, &event, &pending);
4540 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4541 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4542 break;
4543 } else if (ret) {
4544 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4545 break;
4546 }
4547
4548 opcode = le16_to_cpu(event.desc.opcode);
4549 switch (opcode) {
4550
4551 case i40e_aqc_opc_get_link_status:
4552 i40e_handle_link_event(pf, &event);
4553 break;
4554 case i40e_aqc_opc_send_msg_to_pf:
4555 ret = i40e_vc_process_vf_msg(pf,
4556 le16_to_cpu(event.desc.retval),
4557 le32_to_cpu(event.desc.cookie_high),
4558 le32_to_cpu(event.desc.cookie_low),
4559 event.msg_buf,
4560 event.msg_size);
4561 break;
4562 case i40e_aqc_opc_lldp_update_mib:
4563 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4564 break;
4565 case i40e_aqc_opc_event_lan_overflow:
4566 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4567 i40e_handle_lan_overflow_event(pf, &event);
4568 break;
0467bc91
SN		 4569 case i40e_aqc_opc_send_msg_to_peer:
4570 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
4571 break;
41c445ff
JB		 4572 default:
4573 dev_info(&pf->pdev->dev,
0467bc91
SN		 4574 "ARQ Error: Unknown event 0x%04x received\n",
4575 opcode);
41c445ff
JB		 4576 break;
4577 }
4578 } while (pending && (i++ < pf->adminq_work_limit));
4579
4580 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4581 /* re-enable Admin queue interrupt cause */
4582 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4583 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4584 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4585 i40e_flush(hw);
4586
4587 kfree(event.msg_buf);
4588}
4589
4590/**
4591 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4592 * @veb: pointer to the VEB instance
4593 *
4594 * This is a recursive function that first builds the attached VSIs then
4595 * recurses in to build the next layer of VEB. We track the connections
4596 * through our own index numbers because the seid's from the HW could
4597 * change across the reset.
4598 **/
4599static int i40e_reconstitute_veb(struct i40e_veb *veb)
4600{
4601 struct i40e_vsi *ctl_vsi = NULL;
4602 struct i40e_pf *pf = veb->pf;
4603 int v, veb_idx;
4604 int ret;
4605
4606 /* build VSI that owns this VEB, temporarily attached to base VEB */
4607 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4608 if (pf->vsi[v] &&
4609 pf->vsi[v]->veb_idx == veb->idx &&
4610 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4611 ctl_vsi = pf->vsi[v];
4612 break;
4613 }
4614 }
4615 if (!ctl_vsi) {
4616 dev_info(&pf->pdev->dev,
4617 "missing owner VSI for veb_idx %d\n", veb->idx);
4618 ret = -ENOENT;
4619 goto end_reconstitute;
4620 }
4621 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4622 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4623 ret = i40e_add_vsi(ctl_vsi);
4624 if (ret) {
4625 dev_info(&pf->pdev->dev,
4626 "rebuild of owner VSI failed: %d\n", ret);
4627 goto end_reconstitute;
4628 }
4629 i40e_vsi_reset_stats(ctl_vsi);
4630
4631 /* create the VEB in the switch and move the VSI onto the VEB */
4632 ret = i40e_add_veb(veb, ctl_vsi);
4633 if (ret)
4634 goto end_reconstitute;
4635
4636 /* create the remaining VSIs attached to this VEB */
4637 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4638 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4639 continue;
4640
4641 if (pf->vsi[v]->veb_idx == veb->idx) {
4642 struct i40e_vsi *vsi = pf->vsi[v];
4643 vsi->uplink_seid = veb->seid;
4644 ret = i40e_add_vsi(vsi);
4645 if (ret) {
4646 dev_info(&pf->pdev->dev,
4647 "rebuild of vsi_idx %d failed: %d\n",
4648 v, ret);
4649 goto end_reconstitute;
4650 }
4651 i40e_vsi_reset_stats(vsi);
4652 }
4653 }
4654
4655 /* create any VEBs attached to this VEB - RECURSION */
4656 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4657 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4658 pf->veb[veb_idx]->uplink_seid = veb->seid;
4659 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4660 if (ret)
4661 break;
4662 }
4663 }
4664
4665end_reconstitute:
4666 return ret;
4667}
4668
4669/**
4670 * i40e_get_capabilities - get info about the HW
4671 * @pf: the PF struct
4672 **/
4673static int i40e_get_capabilities(struct i40e_pf *pf)
4674{
4675 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4676 u16 data_size;
4677 int buf_len;
4678 int err;
4679
4680 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4681 do {
4682 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4683 if (!cap_buf)
4684 return -ENOMEM;
4685
4686 /* this loads the data into the hw struct for us */
4687 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4688 &data_size,
4689 i40e_aqc_opc_list_func_capabilities,
4690 NULL);
4691 /* data loaded, buffer no longer needed */
4692 kfree(cap_buf);
4693
4694 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4695 /* retry with a larger buffer */
4696 buf_len = data_size;
4697 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4698 dev_info(&pf->pdev->dev,
4699 "capability discovery failed: aq=%d\n",
4700 pf->hw.aq.asq_last_status);
4701 return -ENODEV;
4702 }
4703 } while (err);
4704
2050bc65 4705 if (pf->hw.revision_id == 0 && (pf->flags & I40E_FLAG_MFP_ENABLED)) {
7134f9ce
JB		 4706 pf->hw.func_caps.num_msix_vectors += 1;
4707 pf->hw.func_caps.num_tx_qp =
4708 min_t(int, pf->hw.func_caps.num_tx_qp,
4709 I40E_MAX_NPAR_QPS);
4710 }
4711
41c445ff
JB		 4712 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4713 dev_info(&pf->pdev->dev,
4714 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4715 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4716 pf->hw.func_caps.num_msix_vectors,
4717 pf->hw.func_caps.num_msix_vectors_vf,
4718 pf->hw.func_caps.fd_filters_guaranteed,
4719 pf->hw.func_caps.fd_filters_best_effort,
4720 pf->hw.func_caps.num_tx_qp,
4721 pf->hw.func_caps.num_vsis);
4722
7134f9ce
JB		 4723#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4724 + pf->hw.func_caps.num_vfs)
4725 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4726 dev_info(&pf->pdev->dev,
4727 "got num_vsis %d, setting num_vsis to %d\n",
4728 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4729 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4730 }
4731
41c445ff
JB		 4732 return 0;
4733}
4734
4735/**
4736 * i40e_fdir_setup - initialize the Flow Director resources
4737 * @pf: board private structure
4738 **/
4739static void i40e_fdir_setup(struct i40e_pf *pf)
4740{
4741 struct i40e_vsi *vsi;
4742 bool new_vsi = false;
4743 int err, i;
4744
958a3e3b
SN		 4745 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4746 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4747 return;
4748
4749 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4750
4751 /* find existing or make new FDIR VSI */
4752 vsi = NULL;
4753 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4754 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4755 vsi = pf->vsi[i];
4756 if (!vsi) {
4757 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4758 if (!vsi) {
4759 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4760 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4761 return;
4762 }
4763 new_vsi = true;
4764 }
4765 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4766 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4767
4768 err = i40e_vsi_setup_tx_resources(vsi);
4769 if (!err)
4770 err = i40e_vsi_setup_rx_resources(vsi);
4771 if (!err)
4772 err = i40e_vsi_configure(vsi);
4773 if (!err && new_vsi) {
4774 char int_name[IFNAMSIZ + 9];
4775 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4776 dev_driver_string(&pf->pdev->dev));
4777 err = i40e_vsi_request_irq(vsi, int_name);
4778 }
4779 if (!err)
4780 err = i40e_up_complete(vsi);
4781
4782 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4783}
4784
4785/**
4786 * i40e_fdir_teardown - release the Flow Director resources
4787 * @pf: board private structure
4788 **/
4789static void i40e_fdir_teardown(struct i40e_pf *pf)
4790{
4791 int i;
4792
4793 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4794 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4795 i40e_vsi_release(pf->vsi[i]);
4796 break;
4797 }
4798 }
4799}
4800
4801/**
f650a38b 4802 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4803 * @pf: board private structure
4804 *
f650a38b
ASJ		 4805 * Close up the VFs and other things in prep for pf Reset.
4806 **/
4807static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4808{
41c445ff
JB		 4809 struct i40e_hw *hw = &pf->hw;
4810 i40e_status ret;
4811 u32 v;
4812
4813 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4814 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4815 return 0;
41c445ff
JB		 4816
4817 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4818
37f0be6d
ASJ		 4819 if (i40e_check_asq_alive(hw))
4820 i40e_vc_notify_reset(pf);
41c445ff
JB		 4821
4822 /* quiesce the VSIs and their queues that are not already DOWN */
4823 i40e_pf_quiesce_all_vsi(pf);
4824
4825 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4826 if (pf->vsi[v])
4827 pf->vsi[v]->seid = 0;
4828 }
4829
4830 i40e_shutdown_adminq(&pf->hw);
4831
f650a38b
ASJ		 4832 /* call shutdown HMC */
4833 ret = i40e_shutdown_lan_hmc(hw);
4834 if (ret) {
4835 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4836 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4837 }
4838 return ret;
4839}
4840
4841/**
4dda12e6 4842 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 4843 * @pf: board private structure
bc7d338f 4844 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4845 **/
bc7d338f 4846static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4847{
4848 struct i40e_driver_version dv;
4849 struct i40e_hw *hw = &pf->hw;
4850 i40e_status ret;
4851 u32 v;
4852
41c445ff
JB		 4853 /* Now we wait for GRST to settle out.
4854 * We don't have to delete the VEBs or VSIs from the hw switch
4855 * because the reset will make them disappear.
4856 */
4857 ret = i40e_pf_reset(hw);
4858 if (ret)
4859 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4860 pf->pfr_count++;
4861
4862 if (test_bit(__I40E_DOWN, &pf->state))
4863 goto end_core_reset;
4864 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4865
4866 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4867 ret = i40e_init_adminq(&pf->hw);
4868 if (ret) {
4869 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4870 goto end_core_reset;
4871 }
4872
4873 ret = i40e_get_capabilities(pf);
4874 if (ret) {
4875 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4876 ret);
4877 goto end_core_reset;
4878 }
4879
41c445ff
JB		 4880 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4881 hw->func_caps.num_rx_qp,
4882 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4883 if (ret) {
4884 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4885 goto end_core_reset;
4886 }
4887 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4888 if (ret) {
4889 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4890 goto end_core_reset;
4891 }
4892
4893 /* do basic switch setup */
bc7d338f 4894 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4895 if (ret)
4896 goto end_core_reset;
4897
4898 /* Rebuild the VSIs and VEBs that existed before reset.
4899 * They are still in our local switch element arrays, so only
4900 * need to rebuild the switch model in the HW.
4901 *
4902 * If there were VEBs but the reconstitution failed, we'll try
4903 * try to recover minimal use by getting the basic PF VSI working.
4904 */
4905 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4906 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4907 /* find the one VEB connected to the MAC, and find orphans */
4908 for (v = 0; v < I40E_MAX_VEB; v++) {
4909 if (!pf->veb[v])
4910 continue;
4911
4912 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4913 pf->veb[v]->uplink_seid == 0) {
4914 ret = i40e_reconstitute_veb(pf->veb[v]);
4915
4916 if (!ret)
4917 continue;
4918
4919 /* If Main VEB failed, we're in deep doodoo,
4920 * so give up rebuilding the switch and set up
4921 * for minimal rebuild of PF VSI.
4922 * If orphan failed, we'll report the error
4923 * but try to keep going.
4924 */
4925 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4926 dev_info(&pf->pdev->dev,
4927 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4928 ret);
4929 pf->vsi[pf->lan_vsi]->uplink_seid
4930 = pf->mac_seid;
4931 break;
4932 } else if (pf->veb[v]->uplink_seid == 0) {
4933 dev_info(&pf->pdev->dev,
4934 "rebuild of orphan VEB failed: %d\n",
4935 ret);
4936 }
4937 }
4938 }
4939 }
4940
4941 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4942 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4943 /* no VEB, so rebuild only the Main VSI */
4944 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4945 if (ret) {
4946 dev_info(&pf->pdev->dev,
4947 "rebuild of Main VSI failed: %d\n", ret);
4948 goto end_core_reset;
4949 }
4950 }
4951
4952 /* reinit the misc interrupt */
4953 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4954 ret = i40e_setup_misc_vector(pf);
4955
4956 /* restart the VSIs that were rebuilt and running before the reset */
4957 i40e_pf_unquiesce_all_vsi(pf);
4958
4959 /* tell the firmware that we're starting */
4960 dv.major_version = DRV_VERSION_MAJOR;
4961 dv.minor_version = DRV_VERSION_MINOR;
4962 dv.build_version = DRV_VERSION_BUILD;
4963 dv.subbuild_version = 0;
4964 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4965
4966 dev_info(&pf->pdev->dev, "PF reset done\n");
4967
4968end_core_reset:
4969 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4970}
4971
f650a38b
ASJ		 4972/**
4973 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4974 * @pf: board private structure
4975 *
4976 * Close up the VFs and other things in prep for a Core Reset,
4977 * then get ready to rebuild the world.
4978 **/
4979static void i40e_handle_reset_warning(struct i40e_pf *pf)
4980{
4981 i40e_status ret;
4982
4983 ret = i40e_prep_for_reset(pf);
4984 if (!ret)
bc7d338f 4985 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4986}
4987
41c445ff
JB		 4988/**
4989 * i40e_handle_mdd_event
4990 * @pf: pointer to the pf structure
4991 *
4992 * Called from the MDD irq handler to identify possibly malicious vfs
4993 **/
4994static void i40e_handle_mdd_event(struct i40e_pf *pf)
4995{
4996 struct i40e_hw *hw = &pf->hw;
4997 bool mdd_detected = false;
4998 struct i40e_vf *vf;
4999 u32 reg;
5000 int i;
5001
5002 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5003 return;
5004
5005 /* find what triggered the MDD event */
5006 reg = rd32(hw, I40E_GL_MDET_TX);
5007 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5008 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5009 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5010 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5011 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5012 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5013 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5014 dev_info(&pf->pdev->dev,
5015 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
5016 event, queue, func);
5017 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5018 mdd_detected = true;
5019 }
5020 reg = rd32(hw, I40E_GL_MDET_RX);
5021 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5022 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5023 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5024 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5025 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5026 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5027 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5028 dev_info(&pf->pdev->dev,
5029 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
5030 event, queue, func);
5031 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5032 mdd_detected = true;
5033 }
5034
5035 /* see if one of the VFs needs its hand slapped */
5036 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5037 vf = &(pf->vf[i]);
5038 reg = rd32(hw, I40E_VP_MDET_TX(i));
5039 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5040 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5041 vf->num_mdd_events++;
5042 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5043 }
5044
5045 reg = rd32(hw, I40E_VP_MDET_RX(i));
5046 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5047 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5048 vf->num_mdd_events++;
5049 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5050 }
5051
5052 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5053 dev_info(&pf->pdev->dev,
5054 "Too many MDD events on VF %d, disabled\n", i);
5055 dev_info(&pf->pdev->dev,
5056 "Use PF Control I/F to re-enable the VF\n");
5057 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5058 }
5059 }
5060
5061 /* re-enable mdd interrupt cause */
5062 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5063 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5064 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5065 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5066 i40e_flush(hw);
5067}
5068
a1c9a9d9
JK		 5069#ifdef CONFIG_I40E_VXLAN
5070/**
5071 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5072 * @pf: board private structure
5073 **/
5074static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5075{
5076 const int vxlan_hdr_qwords = 4;
5077 struct i40e_hw *hw = &pf->hw;
5078 i40e_status ret;
5079 u8 filter_index;
5080 __be16 port;
5081 int i;
5082
5083 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5084 return;
5085
5086 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5087
5088 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5089 if (pf->pending_vxlan_bitmap & (1 << i)) {
5090 pf->pending_vxlan_bitmap &= ~(1 << i);
5091 port = pf->vxlan_ports[i];
5092 ret = port ?
5093 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5094 vxlan_hdr_qwords,
5095 I40E_AQC_TUNNEL_TYPE_VXLAN,
5096 &filter_index, NULL)
5097 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5098
5099 if (ret) {
5100 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5101 port ? "adding" : "deleting",
5102 ntohs(port), port ? i : i);
5103
5104 pf->vxlan_ports[i] = 0;
5105 } else {
5106 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5107 port ? "Added" : "Deleted",
5108 ntohs(port), port ? i : filter_index);
5109 }
5110 }
5111 }
5112}
5113
5114#endif
41c445ff
JB		 5115/**
5116 * i40e_service_task - Run the driver's async subtasks
5117 * @work: pointer to work_struct containing our data
5118 **/
5119static void i40e_service_task(struct work_struct *work)
5120{
5121 struct i40e_pf *pf = container_of(work,
5122 struct i40e_pf,
5123 service_task);
5124 unsigned long start_time = jiffies;
5125
5126 i40e_reset_subtask(pf);
5127 i40e_handle_mdd_event(pf);
5128 i40e_vc_process_vflr_event(pf);
5129 i40e_watchdog_subtask(pf);
5130 i40e_fdir_reinit_subtask(pf);
5131 i40e_check_hang_subtask(pf);
5132 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5133#ifdef CONFIG_I40E_VXLAN
5134 i40e_sync_vxlan_filters_subtask(pf);
5135#endif
41c445ff
JB		 5136 i40e_clean_adminq_subtask(pf);
5137
5138 i40e_service_event_complete(pf);
5139
5140 /* If the tasks have taken longer than one timer cycle or there
5141 * is more work to be done, reschedule the service task now
5142 * rather than wait for the timer to tick again.
5143 */
5144 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5145 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5146 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5147 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5148 i40e_service_event_schedule(pf);
5149}
5150
5151/**
5152 * i40e_service_timer - timer callback
5153 * @data: pointer to PF struct
5154 **/
5155static void i40e_service_timer(unsigned long data)
5156{
5157 struct i40e_pf *pf = (struct i40e_pf *)data;
5158
5159 mod_timer(&pf->service_timer,
5160 round_jiffies(jiffies + pf->service_timer_period));
5161 i40e_service_event_schedule(pf);
5162}
5163
5164/**
5165 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5166 * @vsi: the VSI being configured
5167 **/
5168static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5169{
5170 struct i40e_pf *pf = vsi->back;
5171
5172 switch (vsi->type) {
5173 case I40E_VSI_MAIN:
5174 vsi->alloc_queue_pairs = pf->num_lan_qps;
5175 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5176 I40E_REQ_DESCRIPTOR_MULTIPLE);
5177 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5178 vsi->num_q_vectors = pf->num_lan_msix;
5179 else
5180 vsi->num_q_vectors = 1;
5181
5182 break;
5183
5184 case I40E_VSI_FDIR:
5185 vsi->alloc_queue_pairs = 1;
5186 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5187 I40E_REQ_DESCRIPTOR_MULTIPLE);
5188 vsi->num_q_vectors = 1;
5189 break;
5190
5191 case I40E_VSI_VMDQ2:
5192 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5193 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5194 I40E_REQ_DESCRIPTOR_MULTIPLE);
5195 vsi->num_q_vectors = pf->num_vmdq_msix;
5196 break;
5197
5198 case I40E_VSI_SRIOV:
5199 vsi->alloc_queue_pairs = pf->num_vf_qps;
5200 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5201 I40E_REQ_DESCRIPTOR_MULTIPLE);
5202 break;
5203
5204 default:
5205 WARN_ON(1);
5206 return -ENODATA;
5207 }
5208
5209 return 0;
5210}
5211
f650a38b
ASJ		 5212/**
5213 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5214 * @type: VSI pointer
bc7d338f 5215 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5216 *
5217 * On error: returns error code (negative)
5218 * On success: returns 0
5219 **/
bc7d338f 5220static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5221{
5222 int size;
5223 int ret = 0;
5224
ac6c5e3d 5225 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5226 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5227 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5228 if (!vsi->tx_rings)
5229 return -ENOMEM;
f650a38b
ASJ		 5230 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5231
bc7d338f
ASJ		 5232 if (alloc_qvectors) {
5233 /* allocate memory for q_vector pointers */
5234 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5235 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5236 if (!vsi->q_vectors) {
5237 ret = -ENOMEM;
5238 goto err_vectors;
5239 }
f650a38b
ASJ		 5240 }
5241 return ret;
5242
5243err_vectors:
5244 kfree(vsi->tx_rings);
5245 return ret;
5246}
5247
41c445ff
JB		 5248/**
5249 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5250 * @pf: board private structure
5251 * @type: type of VSI
5252 *
5253 * On error: returns error code (negative)
5254 * On success: returns vsi index in PF (positive)
5255 **/
5256static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5257{
5258 int ret = -ENODEV;
5259 struct i40e_vsi *vsi;
5260 int vsi_idx;
5261 int i;
5262
5263 /* Need to protect the allocation of the VSIs at the PF level */
5264 mutex_lock(&pf->switch_mutex);
5265
5266 /* VSI list may be fragmented if VSI creation/destruction has
5267 * been happening. We can afford to do a quick scan to look
5268 * for any free VSIs in the list.
5269 *
5270 * find next empty vsi slot, looping back around if necessary
5271 */
5272 i = pf->next_vsi;
5273 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5274 i++;
5275 if (i >= pf->hw.func_caps.num_vsis) {
5276 i = 0;
5277 while (i < pf->next_vsi && pf->vsi[i])
5278 i++;
5279 }
5280
5281 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5282 vsi_idx = i; /* Found one! */
5283 } else {
5284 ret = -ENODEV;
493fb300 5285 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5286 }
5287 pf->next_vsi = ++i;
5288
5289 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5290 if (!vsi) {
5291 ret = -ENOMEM;
493fb300 5292 goto unlock_pf;
41c445ff
JB		 5293 }
5294 vsi->type = type;
5295 vsi->back = pf;
5296 set_bit(__I40E_DOWN, &vsi->state);
5297 vsi->flags = 0;
5298 vsi->idx = vsi_idx;
5299 vsi->rx_itr_setting = pf->rx_itr_default;
5300 vsi->tx_itr_setting = pf->tx_itr_default;
5301 vsi->netdev_registered = false;
5302 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5303 INIT_LIST_HEAD(&vsi->mac_filter_list);
5304
9f65e15b
AD		 5305 ret = i40e_set_num_rings_in_vsi(vsi);
5306 if (ret)
5307 goto err_rings;
5308
bc7d338f 5309 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5310 if (ret)
9f65e15b 5311 goto err_rings;
493fb300 5312
41c445ff
JB		 5313 /* Setup default MSIX irq handler for VSI */
5314 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5315
5316 pf->vsi[vsi_idx] = vsi;
5317 ret = vsi_idx;
493fb300
AD		 5318 goto unlock_pf;
5319
9f65e15b 5320err_rings:
493fb300
AD		 5321 pf->next_vsi = i - 1;
5322 kfree(vsi);
5323unlock_pf:
41c445ff
JB		 5324 mutex_unlock(&pf->switch_mutex);
5325 return ret;
5326}
5327
f650a38b
ASJ		 5328/**
5329 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5330 * @type: VSI pointer
bc7d338f 5331 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5332 *
5333 * On error: returns error code (negative)
5334 * On success: returns 0
5335 **/
bc7d338f 5336static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5337{
5338 /* free the ring and vector containers */
bc7d338f
ASJ		 5339 if (free_qvectors) {
5340 kfree(vsi->q_vectors);
5341 vsi->q_vectors = NULL;
5342 }
f650a38b
ASJ		 5343 kfree(vsi->tx_rings);
5344 vsi->tx_rings = NULL;
5345 vsi->rx_rings = NULL;
5346}
5347
41c445ff
JB		 5348/**
5349 * i40e_vsi_clear - Deallocate the VSI provided
5350 * @vsi: the VSI being un-configured
5351 **/
5352static int i40e_vsi_clear(struct i40e_vsi *vsi)
5353{
5354 struct i40e_pf *pf;
5355
5356 if (!vsi)
5357 return 0;
5358
5359 if (!vsi->back)
5360 goto free_vsi;
5361 pf = vsi->back;
5362
5363 mutex_lock(&pf->switch_mutex);
5364 if (!pf->vsi[vsi->idx]) {
5365 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5366 vsi->idx, vsi->idx, vsi, vsi->type);
5367 goto unlock_vsi;
5368 }
5369
5370 if (pf->vsi[vsi->idx] != vsi) {
5371 dev_err(&pf->pdev->dev,
5372 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5373 pf->vsi[vsi->idx]->idx,
5374 pf->vsi[vsi->idx],
5375 pf->vsi[vsi->idx]->type,
5376 vsi->idx, vsi, vsi->type);
5377 goto unlock_vsi;
5378 }
5379
5380 /* updates the pf for this cleared vsi */
5381 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5382 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5383
bc7d338f 5384 i40e_vsi_free_arrays(vsi, true);
493fb300 5385
41c445ff
JB		 5386 pf->vsi[vsi->idx] = NULL;
5387 if (vsi->idx < pf->next_vsi)
5388 pf->next_vsi = vsi->idx;
5389
5390unlock_vsi:
5391 mutex_unlock(&pf->switch_mutex);
5392free_vsi:
5393 kfree(vsi);
5394
5395 return 0;
5396}
5397
9f65e15b
AD		 5398/**
5399 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5400 * @vsi: the VSI being cleaned
5401 **/
be1d5eea 5402static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5403{
5404 int i;
5405
8e9dca53 5406 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 5407 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5408 kfree_rcu(vsi->tx_rings[i], rcu);
5409 vsi->tx_rings[i] = NULL;
5410 vsi->rx_rings[i] = NULL;
5411 }
be1d5eea 5412 }
9f65e15b
AD		 5413}
5414
41c445ff
JB		 5415/**
5416 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5417 * @vsi: the VSI being configured
5418 **/
5419static int i40e_alloc_rings(struct i40e_vsi *vsi)
5420{
5421 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5422 int i;
5423
41c445ff 5424 /* Set basic values in the rings to be used later during open() */
d7397644 5425 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5426 struct i40e_ring *tx_ring;
5427 struct i40e_ring *rx_ring;
5428
ac6c5e3d 5429 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5430 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5431 if (!tx_ring)
5432 goto err_out;
41c445ff
JB		 5433
5434 tx_ring->queue_index = i;
5435 tx_ring->reg_idx = vsi->base_queue + i;
5436 tx_ring->ring_active = false;
5437 tx_ring->vsi = vsi;
5438 tx_ring->netdev = vsi->netdev;
5439 tx_ring->dev = &pf->pdev->dev;
5440 tx_ring->count = vsi->num_desc;
5441 tx_ring->size = 0;
5442 tx_ring->dcb_tc = 0;
9f65e15b 5443 vsi->tx_rings[i] = tx_ring;
41c445ff 5444
9f65e15b 5445 rx_ring = &tx_ring[1];
41c445ff
JB		 5446 rx_ring->queue_index = i;
5447 rx_ring->reg_idx = vsi->base_queue + i;
5448 rx_ring->ring_active = false;
5449 rx_ring->vsi = vsi;
5450 rx_ring->netdev = vsi->netdev;
5451 rx_ring->dev = &pf->pdev->dev;
5452 rx_ring->count = vsi->num_desc;
5453 rx_ring->size = 0;
5454 rx_ring->dcb_tc = 0;
5455 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5456 set_ring_16byte_desc_enabled(rx_ring);
5457 else
5458 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5459 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5460 }
5461
5462 return 0;
9f65e15b
AD		 5463
5464err_out:
5465 i40e_vsi_clear_rings(vsi);
5466 return -ENOMEM;
41c445ff
JB		 5467}
5468
5469/**
5470 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5471 * @pf: board private structure
5472 * @vectors: the number of MSI-X vectors to request
5473 *
5474 * Returns the number of vectors reserved, or error
5475 **/
5476static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5477{
5478 int err = 0;
5479
5480 pf->num_msix_entries = 0;
5481 while (vectors >= I40E_MIN_MSIX) {
5482 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5483 if (err == 0) {
5484 /* good to go */
5485 pf->num_msix_entries = vectors;
5486 break;
5487 } else if (err < 0) {
5488 /* total failure */
5489 dev_info(&pf->pdev->dev,
5490 "MSI-X vector reservation failed: %d\n", err);
5491 vectors = 0;
5492 break;
5493 } else {
5494 /* err > 0 is the hint for retry */
5495 dev_info(&pf->pdev->dev,
5496 "MSI-X vectors wanted %d, retrying with %d\n",
5497 vectors, err);
5498 vectors = err;
5499 }
5500 }
5501
5502 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5503 dev_info(&pf->pdev->dev,
5504 "Couldn't get enough vectors, only %d available\n",
5505 vectors);
5506 vectors = 0;
5507 }
5508
5509 return vectors;
5510}
5511
5512/**
5513 * i40e_init_msix - Setup the MSIX capability
5514 * @pf: board private structure
5515 *
5516 * Work with the OS to set up the MSIX vectors needed.
5517 *
5518 * Returns 0 on success, negative on failure
5519 **/
5520static int i40e_init_msix(struct i40e_pf *pf)
5521{
5522 i40e_status err = 0;
5523 struct i40e_hw *hw = &pf->hw;
5524 int v_budget, i;
5525 int vec;
5526
5527 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5528 return -ENODEV;
5529
5530 /* The number of vectors we'll request will be comprised of:
5531 * - Add 1 for "other" cause for Admin Queue events, etc.
5532 * - The number of LAN queue pairs
f8ff1464
ASJ		 5533 * - Queues being used for RSS.
5534 * We don't need as many as max_rss_size vectors.
5535 * use rss_size instead in the calculation since that
5536 * is governed by number of cpus in the system.
5537 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5538 * - The number of VMDq pairs
5539 * Once we count this up, try the request.
5540 *
5541 * If we can't get what we want, we'll simplify to nearly nothing
5542 * and try again. If that still fails, we punt.
5543 */
f8ff1464 5544 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5545 pf->num_vmdq_msix = pf->num_vmdq_qps;
5546 v_budget = 1 + pf->num_lan_msix;
5547 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5548 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5549 v_budget++;
5550
5551 /* Scale down if necessary, and the rings will share vectors */
5552 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5553
5554 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5555 GFP_KERNEL);
5556 if (!pf->msix_entries)
5557 return -ENOMEM;
5558
5559 for (i = 0; i < v_budget; i++)
5560 pf->msix_entries[i].entry = i;
5561 vec = i40e_reserve_msix_vectors(pf, v_budget);
5562 if (vec < I40E_MIN_MSIX) {
5563 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5564 kfree(pf->msix_entries);
5565 pf->msix_entries = NULL;
5566 return -ENODEV;
5567
5568 } else if (vec == I40E_MIN_MSIX) {
5569 /* Adjust for minimal MSIX use */
5570 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5571 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5572 pf->num_vmdq_vsis = 0;
5573 pf->num_vmdq_qps = 0;
5574 pf->num_vmdq_msix = 0;
5575 pf->num_lan_qps = 1;
5576 pf->num_lan_msix = 1;
5577
5578 } else if (vec != v_budget) {
5579 /* Scale vector usage down */
5580 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5581 vec--; /* reserve the misc vector */
5582
5583 /* partition out the remaining vectors */
5584 switch (vec) {
5585 case 2:
5586 pf->num_vmdq_vsis = 1;
5587 pf->num_lan_msix = 1;
5588 break;
5589 case 3:
5590 pf->num_vmdq_vsis = 1;
5591 pf->num_lan_msix = 2;
5592 break;
5593 default:
5594 pf->num_lan_msix = min_t(int, (vec / 2),
5595 pf->num_lan_qps);
5596 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5597 I40E_DEFAULT_NUM_VMDQ_VSI);
5598 break;
5599 }
5600 }
5601
5602 return err;
5603}
5604
493fb300
AD		 5605/**
5606 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5607 * @vsi: the VSI being configured
5608 * @v_idx: index of the vector in the vsi struct
5609 *
5610 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5611 **/
5612static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5613{
5614 struct i40e_q_vector *q_vector;
5615
5616 /* allocate q_vector */
5617 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5618 if (!q_vector)
5619 return -ENOMEM;
5620
5621 q_vector->vsi = vsi;
5622 q_vector->v_idx = v_idx;
5623 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5624 if (vsi->netdev)
5625 netif_napi_add(vsi->netdev, &q_vector->napi,
5626 i40e_napi_poll, vsi->work_limit);
5627
cd0b6fa6
AD		 5628 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5629 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5630
493fb300
AD		 5631 /* tie q_vector and vsi together */
5632 vsi->q_vectors[v_idx] = q_vector;
5633
5634 return 0;
5635}
5636
41c445ff
JB		 5637/**
5638 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5639 * @vsi: the VSI being configured
5640 *
5641 * We allocate one q_vector per queue interrupt. If allocation fails we
5642 * return -ENOMEM.
5643 **/
5644static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5645{
5646 struct i40e_pf *pf = vsi->back;
5647 int v_idx, num_q_vectors;
493fb300 5648 int err;
41c445ff
JB		 5649
5650 /* if not MSIX, give the one vector only to the LAN VSI */
5651 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5652 num_q_vectors = vsi->num_q_vectors;
5653 else if (vsi == pf->vsi[pf->lan_vsi])
5654 num_q_vectors = 1;
5655 else
5656 return -EINVAL;
5657
41c445ff 5658 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5659 err = i40e_alloc_q_vector(vsi, v_idx);
5660 if (err)
5661 goto err_out;
41c445ff
JB		 5662 }
5663
5664 return 0;
493fb300
AD		 5665
5666err_out:
5667 while (v_idx--)
5668 i40e_free_q_vector(vsi, v_idx);
5669
5670 return err;
41c445ff
JB		 5671}
5672
5673/**
5674 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5675 * @pf: board private structure to initialize
5676 **/
5677static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5678{
5679 int err = 0;
5680
5681 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5682 err = i40e_init_msix(pf);
5683 if (err) {
958a3e3b
SN		 5684 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5685 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5686 I40E_FLAG_DCB_ENABLED |
5687 I40E_FLAG_SRIOV_ENABLED |
5688 I40E_FLAG_FDIR_ENABLED |
5689 I40E_FLAG_FDIR_ATR_ENABLED |
5690 I40E_FLAG_VMDQ_ENABLED);
5691
5692 /* rework the queue expectations without MSIX */
5693 i40e_determine_queue_usage(pf);
5694 }
5695 }
5696
5697 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5698 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5699 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5700 err = pci_enable_msi(pf->pdev);
5701 if (err) {
958a3e3b 5702 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5703 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5704 }
5705 }
5706
958a3e3b
SN		 5707 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5708 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5709
41c445ff
JB		 5710 /* track first vector for misc interrupts */
5711 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5712}
5713
5714/**
5715 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5716 * @pf: board private structure
5717 *
5718 * This sets up the handler for MSIX 0, which is used to manage the
5719 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5720 * when in MSI or Legacy interrupt mode.
5721 **/
5722static int i40e_setup_misc_vector(struct i40e_pf *pf)
5723{
5724 struct i40e_hw *hw = &pf->hw;
5725 int err = 0;
5726
5727 /* Only request the irq if this is the first time through, and
5728 * not when we're rebuilding after a Reset
5729 */
5730 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5731 err = request_irq(pf->msix_entries[0].vector,
5732 i40e_intr, 0, pf->misc_int_name, pf);
5733 if (err) {
5734 dev_info(&pf->pdev->dev,
5735 "request_irq for msix_misc failed: %d\n", err);
5736 return -EFAULT;
5737 }
5738 }
5739
5740 i40e_enable_misc_int_causes(hw);
5741
5742 /* associate no queues to the misc vector */
5743 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5744 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5745
5746 i40e_flush(hw);
5747
5748 i40e_irq_dynamic_enable_icr0(pf);
5749
5750 return err;
5751}
5752
5753/**
5754 * i40e_config_rss - Prepare for RSS if used
5755 * @pf: board private structure
5756 **/
5757static int i40e_config_rss(struct i40e_pf *pf)
5758{
41c445ff
JB		 5759 /* Set of random keys generated using kernel random number generator */
5760 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5761 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5762 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5763 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5764 struct i40e_hw *hw = &pf->hw;
5765 u32 lut = 0;
5766 int i, j;
5767 u64 hena;
41c445ff
JB		 5768
5769 /* Fill out hash function seed */
5770 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5771 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5772
5773 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5774 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5775 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5776 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5777 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5778 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5779
5780 /* Populate the LUT with max no. of queues in round robin fashion */
5781 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5782
5783 /* The assumption is that lan qp count will be the highest
5784 * qp count for any PF VSI that needs RSS.
5785 * If multiple VSIs need RSS support, all the qp counts
5786 * for those VSIs should be a power of 2 for RSS to work.
5787 * If LAN VSI is the only consumer for RSS then this requirement
5788 * is not necessary.
5789 */
5790 if (j == pf->rss_size)
5791 j = 0;
5792 /* lut = 4-byte sliding window of 4 lut entries */
5793 lut = (lut << 8) | (j &
5794 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5795 /* On i = 3, we have 4 entries in lut; write to the register */
5796 if ((i & 3) == 3)
5797 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5798 }
5799 i40e_flush(hw);
5800
5801 return 0;
5802}
5803
f8ff1464
ASJ		 5804/**
5805 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5806 * @pf: board private structure
5807 * @queue_count: the requested queue count for rss.
5808 *
5809 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5810 * count which may be different from the requested queue count.
5811 **/
5812int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5813{
5814 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5815 return 0;
5816
5817 queue_count = min_t(int, queue_count, pf->rss_size_max);
5818 queue_count = rounddown_pow_of_two(queue_count);
5819
5820 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 5821 i40e_prep_for_reset(pf);
5822
f8ff1464
ASJ		 5823 pf->rss_size = queue_count;
5824
5825 i40e_reset_and_rebuild(pf, true);
5826 i40e_config_rss(pf);
5827 }
5828 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5829 return pf->rss_size;
5830}
5831
41c445ff
JB		 5832/**
5833 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5834 * @pf: board private structure to initialize
5835 *
5836 * i40e_sw_init initializes the Adapter private data structure.
5837 * Fields are initialized based on PCI device information and
5838 * OS network device settings (MTU size).
5839 **/
5840static int i40e_sw_init(struct i40e_pf *pf)
5841{
5842 int err = 0;
5843 int size;
5844
5845 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5846 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5847 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5848 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5849 if (I40E_DEBUG_USER & debug)
5850 pf->hw.debug_mask = debug;
5851 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5852 I40E_DEFAULT_MSG_ENABLE);
5853 }
5854
5855 /* Set default capability flags */
5856 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5857 I40E_FLAG_MSI_ENABLED |
5858 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 5859 I40E_FLAG_RX_1BUF_ENABLED;
5860
7134f9ce
JB		 5861 /* Depending on PF configurations, it is possible that the RSS
5862 * maximum might end up larger than the available queues
5863 */
41c445ff 5864 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5865 pf->rss_size_max = min_t(int, pf->rss_size_max,
5866 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5867 if (pf->hw.func_caps.rss) {
5868 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5869 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5870 } else {
5871 pf->rss_size = 1;
5872 }
5873
2050bc65
CS		 5874 /* MFP mode enabled */
5875 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5876 pf->flags |= I40E_FLAG_MFP_ENABLED;
5877 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5878 }
5879
41c445ff
JB		 5880 if (pf->hw.func_caps.dcb)
5881 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5882 else
5883 pf->num_tc_qps = 0;
5884
5885 if (pf->hw.func_caps.fd) {
5886 /* FW/NVM is not yet fixed in this regard */
5887 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5888 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5889 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5890 dev_info(&pf->pdev->dev,
5891 "Flow Director ATR mode Enabled\n");
5892 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5893 dev_info(&pf->pdev->dev,
5894 "Flow Director Side Band mode Enabled\n");
5895 pf->fdir_pf_filter_count =
5896 pf->hw.func_caps.fd_filters_guaranteed;
5897 }
5898 } else {
5899 pf->fdir_pf_filter_count = 0;
5900 }
5901
5902 if (pf->hw.func_caps.vmdq) {
5903 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5904 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5905 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5906 }
5907
41c445ff
JB		 5908#ifdef CONFIG_PCI_IOV
5909 if (pf->hw.func_caps.num_vfs) {
5910 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5911 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5912 pf->num_req_vfs = min_t(int,
5913 pf->hw.func_caps.num_vfs,
5914 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5915 dev_info(&pf->pdev->dev,
5916 "Number of VFs being requested for PF[%d] = %d\n",
5917 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5918 }
5919#endif /* CONFIG_PCI_IOV */
5920 pf->eeprom_version = 0xDEAD;
5921 pf->lan_veb = I40E_NO_VEB;
5922 pf->lan_vsi = I40E_NO_VSI;
5923
5924 /* set up queue assignment tracking */
5925 size = sizeof(struct i40e_lump_tracking)
5926 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5927 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5928 if (!pf->qp_pile) {
5929 err = -ENOMEM;
5930 goto sw_init_done;
5931 }
5932 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5933 pf->qp_pile->search_hint = 0;
5934
5935 /* set up vector assignment tracking */
5936 size = sizeof(struct i40e_lump_tracking)
5937 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5938 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5939 if (!pf->irq_pile) {
5940 kfree(pf->qp_pile);
5941 err = -ENOMEM;
5942 goto sw_init_done;
5943 }
5944 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5945 pf->irq_pile->search_hint = 0;
5946
5947 mutex_init(&pf->switch_mutex);
5948
5949sw_init_done:
5950 return err;
5951}
5952
5953/**
5954 * i40e_set_features - set the netdev feature flags
5955 * @netdev: ptr to the netdev being adjusted
5956 * @features: the feature set that the stack is suggesting
5957 **/
5958static int i40e_set_features(struct net_device *netdev,
5959 netdev_features_t features)
5960{
5961 struct i40e_netdev_priv *np = netdev_priv(netdev);
5962 struct i40e_vsi *vsi = np->vsi;
5963
5964 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5965 i40e_vlan_stripping_enable(vsi);
5966 else
5967 i40e_vlan_stripping_disable(vsi);
5968
5969 return 0;
5970}
5971
a1c9a9d9
JK		 5972#ifdef CONFIG_I40E_VXLAN
5973/**
5974 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5975 * @pf: board private structure
5976 * @port: The UDP port to look up
5977 *
5978 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5979 **/
5980static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5981{
5982 u8 i;
5983
5984 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5985 if (pf->vxlan_ports[i] == port)
5986 return i;
5987 }
5988
5989 return i;
5990}
5991
5992/**
5993 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5994 * @netdev: This physical port's netdev
5995 * @sa_family: Socket Family that VXLAN is notifying us about
5996 * @port: New UDP port number that VXLAN started listening to
5997 **/
5998static void i40e_add_vxlan_port(struct net_device *netdev,
5999 sa_family_t sa_family, __be16 port)
6000{
6001 struct i40e_netdev_priv *np = netdev_priv(netdev);
6002 struct i40e_vsi *vsi = np->vsi;
6003 struct i40e_pf *pf = vsi->back;
6004 u8 next_idx;
6005 u8 idx;
6006
6007 if (sa_family == AF_INET6)
6008 return;
6009
6010 idx = i40e_get_vxlan_port_idx(pf, port);
6011
6012 /* Check if port already exists */
6013 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6014 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6015 return;
6016 }
6017
6018 /* Now check if there is space to add the new port */
6019 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6020
6021 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6022 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6023 ntohs(port));
6024 return;
6025 }
6026
6027 /* New port: add it and mark its index in the bitmap */
6028 pf->vxlan_ports[next_idx] = port;
6029 pf->pending_vxlan_bitmap |= (1 << next_idx);
6030
6031 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6032}
6033
6034/**
6035 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6036 * @netdev: This physical port's netdev
6037 * @sa_family: Socket Family that VXLAN is notifying us about
6038 * @port: UDP port number that VXLAN stopped listening to
6039 **/
6040static void i40e_del_vxlan_port(struct net_device *netdev,
6041 sa_family_t sa_family, __be16 port)
6042{
6043 struct i40e_netdev_priv *np = netdev_priv(netdev);
6044 struct i40e_vsi *vsi = np->vsi;
6045 struct i40e_pf *pf = vsi->back;
6046 u8 idx;
6047
6048 if (sa_family == AF_INET6)
6049 return;
6050
6051 idx = i40e_get_vxlan_port_idx(pf, port);
6052
6053 /* Check if port already exists */
6054 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6055 /* if port exists, set it to 0 (mark for deletion)
6056 * and make it pending
6057 */
6058 pf->vxlan_ports[idx] = 0;
6059
6060 pf->pending_vxlan_bitmap |= (1 << idx);
6061
6062 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6063 } else {
6064 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6065 ntohs(port));
6066 }
6067}
6068
6069#endif
41c445ff
JB		 6070static const struct net_device_ops i40e_netdev_ops = {
6071 .ndo_open = i40e_open,
6072 .ndo_stop = i40e_close,
6073 .ndo_start_xmit = i40e_lan_xmit_frame,
6074 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6075 .ndo_set_rx_mode = i40e_set_rx_mode,
6076 .ndo_validate_addr = eth_validate_addr,
6077 .ndo_set_mac_address = i40e_set_mac,
6078 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6079 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6080 .ndo_tx_timeout = i40e_tx_timeout,
6081 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6082 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6083#ifdef CONFIG_NET_POLL_CONTROLLER
6084 .ndo_poll_controller = i40e_netpoll,
6085#endif
6086 .ndo_setup_tc = i40e_setup_tc,
6087 .ndo_set_features = i40e_set_features,
6088 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6089 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6090 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6091 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6092#ifdef CONFIG_I40E_VXLAN
6093 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6094 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6095#endif
41c445ff
JB		 6096};
6097
6098/**
6099 * i40e_config_netdev - Setup the netdev flags
6100 * @vsi: the VSI being configured
6101 *
6102 * Returns 0 on success, negative value on failure
6103 **/
6104static int i40e_config_netdev(struct i40e_vsi *vsi)
6105{
1a10370a 6106 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6107 struct i40e_pf *pf = vsi->back;
6108 struct i40e_hw *hw = &pf->hw;
6109 struct i40e_netdev_priv *np;
6110 struct net_device *netdev;
6111 u8 mac_addr[ETH_ALEN];
6112 int etherdev_size;
6113
6114 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6115 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6116 if (!netdev)
6117 return -ENOMEM;
6118
6119 vsi->netdev = netdev;
6120 np = netdev_priv(netdev);
6121 np->vsi = vsi;
6122
6123 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6124 NETIF_F_GSO_UDP_TUNNEL |
6125 NETIF_F_TSO |
6126 NETIF_F_SG;
6127
6128 netdev->features = NETIF_F_SG |
6129 NETIF_F_IP_CSUM |
6130 NETIF_F_SCTP_CSUM |
6131 NETIF_F_HIGHDMA |
6132 NETIF_F_GSO_UDP_TUNNEL |
6133 NETIF_F_HW_VLAN_CTAG_TX |
6134 NETIF_F_HW_VLAN_CTAG_RX |
6135 NETIF_F_HW_VLAN_CTAG_FILTER |
6136 NETIF_F_IPV6_CSUM |
6137 NETIF_F_TSO |
6138 NETIF_F_TSO6 |
6139 NETIF_F_RXCSUM |
6140 NETIF_F_RXHASH |
6141 0;
6142
6143 /* copy netdev features into list of user selectable features */
6144 netdev->hw_features |= netdev->features;
6145
6146 if (vsi->type == I40E_VSI_MAIN) {
6147 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6148 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6149 } else {
6150 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6151 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6152 pf->vsi[pf->lan_vsi]->netdev->name);
6153 random_ether_addr(mac_addr);
6154 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6155 }
1a10370a 6156 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6157
6158 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6159 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6160 /* vlan gets same features (except vlan offload)
6161 * after any tweaks for specific VSI types
6162 */
6163 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6164 NETIF_F_HW_VLAN_CTAG_RX |
6165 NETIF_F_HW_VLAN_CTAG_FILTER);
6166 netdev->priv_flags |= IFF_UNICAST_FLT;
6167 netdev->priv_flags |= IFF_SUPP_NOFCS;
6168 /* Setup netdev TC information */
6169 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6170
6171 netdev->netdev_ops = &i40e_netdev_ops;
6172 netdev->watchdog_timeo = 5 * HZ;
6173 i40e_set_ethtool_ops(netdev);
6174
6175 return 0;
6176}
6177
6178/**
6179 * i40e_vsi_delete - Delete a VSI from the switch
6180 * @vsi: the VSI being removed
6181 *
6182 * Returns 0 on success, negative value on failure
6183 **/
6184static void i40e_vsi_delete(struct i40e_vsi *vsi)
6185{
6186 /* remove default VSI is not allowed */
6187 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6188 return;
6189
6190 /* there is no HW VSI for FDIR */
6191 if (vsi->type == I40E_VSI_FDIR)
6192 return;
6193
6194 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6195 return;
6196}
6197
6198/**
6199 * i40e_add_vsi - Add a VSI to the switch
6200 * @vsi: the VSI being configured
6201 *
6202 * This initializes a VSI context depending on the VSI type to be added and
6203 * passes it down to the add_vsi aq command.
6204 **/
6205static int i40e_add_vsi(struct i40e_vsi *vsi)
6206{
6207 int ret = -ENODEV;
6208 struct i40e_mac_filter *f, *ftmp;
6209 struct i40e_pf *pf = vsi->back;
6210 struct i40e_hw *hw = &pf->hw;
6211 struct i40e_vsi_context ctxt;
6212 u8 enabled_tc = 0x1; /* TC0 enabled */
6213 int f_count = 0;
6214
6215 memset(&ctxt, 0, sizeof(ctxt));
6216 switch (vsi->type) {
6217 case I40E_VSI_MAIN:
6218 /* The PF's main VSI is already setup as part of the
6219 * device initialization, so we'll not bother with
6220 * the add_vsi call, but we will retrieve the current
6221 * VSI context.
6222 */
6223 ctxt.seid = pf->main_vsi_seid;
6224 ctxt.pf_num = pf->hw.pf_id;
6225 ctxt.vf_num = 0;
6226 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6227 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6228 if (ret) {
6229 dev_info(&pf->pdev->dev,
6230 "couldn't get pf vsi config, err %d, aq_err %d\n",
6231 ret, pf->hw.aq.asq_last_status);
6232 return -ENOENT;
6233 }
6234 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6235 vsi->info.valid_sections = 0;
6236
6237 vsi->seid = ctxt.seid;
6238 vsi->id = ctxt.vsi_number;
6239
6240 enabled_tc = i40e_pf_get_tc_map(pf);
6241
6242 /* MFP mode setup queue map and update VSI */
6243 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6244 memset(&ctxt, 0, sizeof(ctxt));
6245 ctxt.seid = pf->main_vsi_seid;
6246 ctxt.pf_num = pf->hw.pf_id;
6247 ctxt.vf_num = 0;
6248 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6249 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6250 if (ret) {
6251 dev_info(&pf->pdev->dev,
6252 "update vsi failed, aq_err=%d\n",
6253 pf->hw.aq.asq_last_status);
6254 ret = -ENOENT;
6255 goto err;
6256 }
6257 /* update the local VSI info queue map */
6258 i40e_vsi_update_queue_map(vsi, &ctxt);
6259 vsi->info.valid_sections = 0;
6260 } else {
6261 /* Default/Main VSI is only enabled for TC0
6262 * reconfigure it to enable all TCs that are
6263 * available on the port in SFP mode.
6264 */
6265 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6266 if (ret) {
6267 dev_info(&pf->pdev->dev,
6268 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6269 enabled_tc, ret,
6270 pf->hw.aq.asq_last_status);
6271 ret = -ENOENT;
6272 }
6273 }
6274 break;
6275
6276 case I40E_VSI_FDIR:
6277 /* no queue mapping or actual HW VSI needed */
6278 vsi->info.valid_sections = 0;
6279 vsi->seid = 0;
6280 vsi->id = 0;
6281 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6282 return 0;
6283 break;
6284
6285 case I40E_VSI_VMDQ2:
6286 ctxt.pf_num = hw->pf_id;
6287 ctxt.vf_num = 0;
6288 ctxt.uplink_seid = vsi->uplink_seid;
6289 ctxt.connection_type = 0x1; /* regular data port */
6290 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6291
6292 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6293
6294 /* This VSI is connected to VEB so the switch_id
6295 * should be set to zero by default.
6296 */
6297 ctxt.info.switch_id = 0;
6298 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6299 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6300
6301 /* Setup the VSI tx/rx queue map for TC0 only for now */
6302 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6303 break;
6304
6305 case I40E_VSI_SRIOV:
6306 ctxt.pf_num = hw->pf_id;
6307 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6308 ctxt.uplink_seid = vsi->uplink_seid;
6309 ctxt.connection_type = 0x1; /* regular data port */
6310 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6311
6312 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6313
6314 /* This VSI is connected to VEB so the switch_id
6315 * should be set to zero by default.
6316 */
6317 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6318
6319 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6320 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6321 /* Setup the VSI tx/rx queue map for TC0 only for now */
6322 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6323 break;
6324
6325 default:
6326 return -ENODEV;
6327 }
6328
6329 if (vsi->type != I40E_VSI_MAIN) {
6330 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6331 if (ret) {
6332 dev_info(&vsi->back->pdev->dev,
6333 "add vsi failed, aq_err=%d\n",
6334 vsi->back->hw.aq.asq_last_status);
6335 ret = -ENOENT;
6336 goto err;
6337 }
6338 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6339 vsi->info.valid_sections = 0;
6340 vsi->seid = ctxt.seid;
6341 vsi->id = ctxt.vsi_number;
6342 }
6343
6344 /* If macvlan filters already exist, force them to get loaded */
6345 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6346 f->changed = true;
6347 f_count++;
6348 }
6349 if (f_count) {
6350 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6351 pf->flags |= I40E_FLAG_FILTER_SYNC;
6352 }
6353
6354 /* Update VSI BW information */
6355 ret = i40e_vsi_get_bw_info(vsi);
6356 if (ret) {
6357 dev_info(&pf->pdev->dev,
6358 "couldn't get vsi bw info, err %d, aq_err %d\n",
6359 ret, pf->hw.aq.asq_last_status);
6360 /* VSI is already added so not tearing that up */
6361 ret = 0;
6362 }
6363
6364err:
6365 return ret;
6366}
6367
6368/**
6369 * i40e_vsi_release - Delete a VSI and free its resources
6370 * @vsi: the VSI being removed
6371 *
6372 * Returns 0 on success or < 0 on error
6373 **/
6374int i40e_vsi_release(struct i40e_vsi *vsi)
6375{
6376 struct i40e_mac_filter *f, *ftmp;
6377 struct i40e_veb *veb = NULL;
6378 struct i40e_pf *pf;
6379 u16 uplink_seid;
6380 int i, n;
6381
6382 pf = vsi->back;
6383
6384 /* release of a VEB-owner or last VSI is not allowed */
6385 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6386 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6387 vsi->seid, vsi->uplink_seid);
6388 return -ENODEV;
6389 }
6390 if (vsi == pf->vsi[pf->lan_vsi] &&
6391 !test_bit(__I40E_DOWN, &pf->state)) {
6392 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6393 return -ENODEV;
6394 }
6395
6396 uplink_seid = vsi->uplink_seid;
6397 if (vsi->type != I40E_VSI_SRIOV) {
6398 if (vsi->netdev_registered) {
6399 vsi->netdev_registered = false;
6400 if (vsi->netdev) {
6401 /* results in a call to i40e_close() */
6402 unregister_netdev(vsi->netdev);
6403 free_netdev(vsi->netdev);
6404 vsi->netdev = NULL;
6405 }
6406 } else {
6407 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6408 i40e_down(vsi);
6409 i40e_vsi_free_irq(vsi);
6410 i40e_vsi_free_tx_resources(vsi);
6411 i40e_vsi_free_rx_resources(vsi);
6412 }
6413 i40e_vsi_disable_irq(vsi);
6414 }
6415
6416 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6417 i40e_del_filter(vsi, f->macaddr, f->vlan,
6418 f->is_vf, f->is_netdev);
6419 i40e_sync_vsi_filters(vsi);
6420
6421 i40e_vsi_delete(vsi);
6422 i40e_vsi_free_q_vectors(vsi);
6423 i40e_vsi_clear_rings(vsi);
6424 i40e_vsi_clear(vsi);
6425
6426 /* If this was the last thing on the VEB, except for the
6427 * controlling VSI, remove the VEB, which puts the controlling
6428 * VSI onto the next level down in the switch.
6429 *
6430 * Well, okay, there's one more exception here: don't remove
6431 * the orphan VEBs yet. We'll wait for an explicit remove request
6432 * from up the network stack.
6433 */
6434 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6435 if (pf->vsi[i] &&
6436 pf->vsi[i]->uplink_seid == uplink_seid &&
6437 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6438 n++; /* count the VSIs */
6439 }
6440 }
6441 for (i = 0; i < I40E_MAX_VEB; i++) {
6442 if (!pf->veb[i])
6443 continue;
6444 if (pf->veb[i]->uplink_seid == uplink_seid)
6445 n++; /* count the VEBs */
6446 if (pf->veb[i]->seid == uplink_seid)
6447 veb = pf->veb[i];
6448 }
6449 if (n == 0 && veb && veb->uplink_seid != 0)
6450 i40e_veb_release(veb);
6451
6452 return 0;
6453}
6454
6455/**
6456 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6457 * @vsi: ptr to the VSI
6458 *
6459 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6460 * corresponding SW VSI structure and initializes num_queue_pairs for the
6461 * newly allocated VSI.
6462 *
6463 * Returns 0 on success or negative on failure
6464 **/
6465static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6466{
6467 int ret = -ENOENT;
6468 struct i40e_pf *pf = vsi->back;
6469
493fb300 6470 if (vsi->q_vectors[0]) {
41c445ff
JB		 6471 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6472 vsi->seid);
6473 return -EEXIST;
6474 }
6475
6476 if (vsi->base_vector) {
6477 dev_info(&pf->pdev->dev,
6478 "VSI %d has non-zero base vector %d\n",
6479 vsi->seid, vsi->base_vector);
6480 return -EEXIST;
6481 }
6482
6483 ret = i40e_alloc_q_vectors(vsi);
6484 if (ret) {
6485 dev_info(&pf->pdev->dev,
6486 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6487 vsi->num_q_vectors, vsi->seid, ret);
6488 vsi->num_q_vectors = 0;
6489 goto vector_setup_out;
6490 }
6491
958a3e3b
SN		 6492 if (vsi->num_q_vectors)
6493 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6494 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6495 if (vsi->base_vector < 0) {
6496 dev_info(&pf->pdev->dev,
6497 "failed to get q tracking for VSI %d, err=%d\n",
6498 vsi->seid, vsi->base_vector);
6499 i40e_vsi_free_q_vectors(vsi);
6500 ret = -ENOENT;
6501 goto vector_setup_out;
6502 }
6503
6504vector_setup_out:
6505 return ret;
6506}
6507
bc7d338f
ASJ		 6508/**
6509 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6510 * @vsi: pointer to the vsi.
6511 *
6512 * This re-allocates a vsi's queue resources.
6513 *
6514 * Returns pointer to the successfully allocated and configured VSI sw struct
6515 * on success, otherwise returns NULL on failure.
6516 **/
6517static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6518{
6519 struct i40e_pf *pf = vsi->back;
6520 u8 enabled_tc;
6521 int ret;
6522
6523 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6524 i40e_vsi_clear_rings(vsi);
6525
6526 i40e_vsi_free_arrays(vsi, false);
6527 i40e_set_num_rings_in_vsi(vsi);
6528 ret = i40e_vsi_alloc_arrays(vsi, false);
6529 if (ret)
6530 goto err_vsi;
6531
6532 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6533 if (ret < 0) {
6534 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6535 vsi->seid, ret);
6536 goto err_vsi;
6537 }
6538 vsi->base_queue = ret;
6539
6540 /* Update the FW view of the VSI. Force a reset of TC and queue
6541 * layout configurations.
6542 */
6543 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6544 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6545 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6546 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6547
6548 /* assign it some queues */
6549 ret = i40e_alloc_rings(vsi);
6550 if (ret)
6551 goto err_rings;
6552
6553 /* map all of the rings to the q_vectors */
6554 i40e_vsi_map_rings_to_vectors(vsi);
6555 return vsi;
6556
6557err_rings:
6558 i40e_vsi_free_q_vectors(vsi);
6559 if (vsi->netdev_registered) {
6560 vsi->netdev_registered = false;
6561 unregister_netdev(vsi->netdev);
6562 free_netdev(vsi->netdev);
6563 vsi->netdev = NULL;
6564 }
6565 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6566err_vsi:
6567 i40e_vsi_clear(vsi);
6568 return NULL;
6569}
6570
41c445ff
JB		 6571/**
6572 * i40e_vsi_setup - Set up a VSI by a given type
6573 * @pf: board private structure
6574 * @type: VSI type
6575 * @uplink_seid: the switch element to link to
6576 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6577 *
6578 * This allocates the sw VSI structure and its queue resources, then add a VSI
6579 * to the identified VEB.
6580 *
6581 * Returns pointer to the successfully allocated and configure VSI sw struct on
6582 * success, otherwise returns NULL on failure.
6583 **/
6584struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6585 u16 uplink_seid, u32 param1)
6586{
6587 struct i40e_vsi *vsi = NULL;
6588 struct i40e_veb *veb = NULL;
6589 int ret, i;
6590 int v_idx;
6591
6592 /* The requested uplink_seid must be either
6593 * - the PF's port seid
6594 * no VEB is needed because this is the PF
6595 * or this is a Flow Director special case VSI
6596 * - seid of an existing VEB
6597 * - seid of a VSI that owns an existing VEB
6598 * - seid of a VSI that doesn't own a VEB
6599 * a new VEB is created and the VSI becomes the owner
6600 * - seid of the PF VSI, which is what creates the first VEB
6601 * this is a special case of the previous
6602 *
6603 * Find which uplink_seid we were given and create a new VEB if needed
6604 */
6605 for (i = 0; i < I40E_MAX_VEB; i++) {
6606 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6607 veb = pf->veb[i];
6608 break;
6609 }
6610 }
6611
6612 if (!veb && uplink_seid != pf->mac_seid) {
6613
6614 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6615 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6616 vsi = pf->vsi[i];
6617 break;
6618 }
6619 }
6620 if (!vsi) {
6621 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6622 uplink_seid);
6623 return NULL;
6624 }
6625
6626 if (vsi->uplink_seid == pf->mac_seid)
6627 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6628 vsi->tc_config.enabled_tc);
6629 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6630 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6631 vsi->tc_config.enabled_tc);
6632
6633 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6634 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6635 veb = pf->veb[i];
6636 }
6637 if (!veb) {
6638 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6639 return NULL;
6640 }
6641
6642 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6643 uplink_seid = veb->seid;
6644 }
6645
6646 /* get vsi sw struct */
6647 v_idx = i40e_vsi_mem_alloc(pf, type);
6648 if (v_idx < 0)
6649 goto err_alloc;
6650 vsi = pf->vsi[v_idx];
6651 vsi->type = type;
6652 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6653
6654 if (type == I40E_VSI_MAIN)
6655 pf->lan_vsi = v_idx;
6656 else if (type == I40E_VSI_SRIOV)
6657 vsi->vf_id = param1;
6658 /* assign it some queues */
6659 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6660 if (ret < 0) {
6661 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6662 vsi->seid, ret);
6663 goto err_vsi;
6664 }
6665 vsi->base_queue = ret;
6666
6667 /* get a VSI from the hardware */
6668 vsi->uplink_seid = uplink_seid;
6669 ret = i40e_add_vsi(vsi);
6670 if (ret)
6671 goto err_vsi;
6672
6673 switch (vsi->type) {
6674 /* setup the netdev if needed */
6675 case I40E_VSI_MAIN:
6676 case I40E_VSI_VMDQ2:
6677 ret = i40e_config_netdev(vsi);
6678 if (ret)
6679 goto err_netdev;
6680 ret = register_netdev(vsi->netdev);
6681 if (ret)
6682 goto err_netdev;
6683 vsi->netdev_registered = true;
6684 netif_carrier_off(vsi->netdev);
6685 /* fall through */
6686
6687 case I40E_VSI_FDIR:
6688 /* set up vectors and rings if needed */
6689 ret = i40e_vsi_setup_vectors(vsi);
6690 if (ret)
6691 goto err_msix;
6692
6693 ret = i40e_alloc_rings(vsi);
6694 if (ret)
6695 goto err_rings;
6696
6697 /* map all of the rings to the q_vectors */
6698 i40e_vsi_map_rings_to_vectors(vsi);
6699
6700 i40e_vsi_reset_stats(vsi);
6701 break;
6702
6703 default:
6704 /* no netdev or rings for the other VSI types */
6705 break;
6706 }
6707
6708 return vsi;
6709
6710err_rings:
6711 i40e_vsi_free_q_vectors(vsi);
6712err_msix:
6713 if (vsi->netdev_registered) {
6714 vsi->netdev_registered = false;
6715 unregister_netdev(vsi->netdev);
6716 free_netdev(vsi->netdev);
6717 vsi->netdev = NULL;
6718 }
6719err_netdev:
6720 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6721err_vsi:
6722 i40e_vsi_clear(vsi);
6723err_alloc:
6724 return NULL;
6725}
6726
6727/**
6728 * i40e_veb_get_bw_info - Query VEB BW information
6729 * @veb: the veb to query
6730 *
6731 * Query the Tx scheduler BW configuration data for given VEB
6732 **/
6733static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6734{
6735 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6736 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6737 struct i40e_pf *pf = veb->pf;
6738 struct i40e_hw *hw = &pf->hw;
6739 u32 tc_bw_max;
6740 int ret = 0;
6741 int i;
6742
6743 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6744 &bw_data, NULL);
6745 if (ret) {
6746 dev_info(&pf->pdev->dev,
6747 "query veb bw config failed, aq_err=%d\n",
6748 hw->aq.asq_last_status);
6749 goto out;
6750 }
6751
6752 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6753 &ets_data, NULL);
6754 if (ret) {
6755 dev_info(&pf->pdev->dev,
6756 "query veb bw ets config failed, aq_err=%d\n",
6757 hw->aq.asq_last_status);
6758 goto out;
6759 }
6760
6761 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6762 veb->bw_max_quanta = ets_data.tc_bw_max;
6763 veb->is_abs_credits = bw_data.absolute_credits_enable;
6764 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6765 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6766 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6767 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6768 veb->bw_tc_limit_credits[i] =
6769 le16_to_cpu(bw_data.tc_bw_limits[i]);
6770 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6771 }
6772
6773out:
6774 return ret;
6775}
6776
6777/**
6778 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6779 * @pf: board private structure
6780 *
6781 * On error: returns error code (negative)
6782 * On success: returns vsi index in PF (positive)
6783 **/
6784static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6785{
6786 int ret = -ENOENT;
6787 struct i40e_veb *veb;
6788 int i;
6789
6790 /* Need to protect the allocation of switch elements at the PF level */
6791 mutex_lock(&pf->switch_mutex);
6792
6793 /* VEB list may be fragmented if VEB creation/destruction has
6794 * been happening. We can afford to do a quick scan to look
6795 * for any free slots in the list.
6796 *
6797 * find next empty veb slot, looping back around if necessary
6798 */
6799 i = 0;
6800 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6801 i++;
6802 if (i >= I40E_MAX_VEB) {
6803 ret = -ENOMEM;
6804 goto err_alloc_veb; /* out of VEB slots! */
6805 }
6806
6807 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6808 if (!veb) {
6809 ret = -ENOMEM;
6810 goto err_alloc_veb;
6811 }
6812 veb->pf = pf;
6813 veb->idx = i;
6814 veb->enabled_tc = 1;
6815
6816 pf->veb[i] = veb;
6817 ret = i;
6818err_alloc_veb:
6819 mutex_unlock(&pf->switch_mutex);
6820 return ret;
6821}
6822
6823/**
6824 * i40e_switch_branch_release - Delete a branch of the switch tree
6825 * @branch: where to start deleting
6826 *
6827 * This uses recursion to find the tips of the branch to be
6828 * removed, deleting until we get back to and can delete this VEB.
6829 **/
6830static void i40e_switch_branch_release(struct i40e_veb *branch)
6831{
6832 struct i40e_pf *pf = branch->pf;
6833 u16 branch_seid = branch->seid;
6834 u16 veb_idx = branch->idx;
6835 int i;
6836
6837 /* release any VEBs on this VEB - RECURSION */
6838 for (i = 0; i < I40E_MAX_VEB; i++) {
6839 if (!pf->veb[i])
6840 continue;
6841 if (pf->veb[i]->uplink_seid == branch->seid)
6842 i40e_switch_branch_release(pf->veb[i]);
6843 }
6844
6845 /* Release the VSIs on this VEB, but not the owner VSI.
6846 *
6847 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6848 * the VEB itself, so don't use (*branch) after this loop.
6849 */
6850 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6851 if (!pf->vsi[i])
6852 continue;
6853 if (pf->vsi[i]->uplink_seid == branch_seid &&
6854 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6855 i40e_vsi_release(pf->vsi[i]);
6856 }
6857 }
6858
6859 /* There's one corner case where the VEB might not have been
6860 * removed, so double check it here and remove it if needed.
6861 * This case happens if the veb was created from the debugfs
6862 * commands and no VSIs were added to it.
6863 */
6864 if (pf->veb[veb_idx])
6865 i40e_veb_release(pf->veb[veb_idx]);
6866}
6867
6868/**
6869 * i40e_veb_clear - remove veb struct
6870 * @veb: the veb to remove
6871 **/
6872static void i40e_veb_clear(struct i40e_veb *veb)
6873{
6874 if (!veb)
6875 return;
6876
6877 if (veb->pf) {
6878 struct i40e_pf *pf = veb->pf;
6879
6880 mutex_lock(&pf->switch_mutex);
6881 if (pf->veb[veb->idx] == veb)
6882 pf->veb[veb->idx] = NULL;
6883 mutex_unlock(&pf->switch_mutex);
6884 }
6885
6886 kfree(veb);
6887}
6888
6889/**
6890 * i40e_veb_release - Delete a VEB and free its resources
6891 * @veb: the VEB being removed
6892 **/
6893void i40e_veb_release(struct i40e_veb *veb)
6894{
6895 struct i40e_vsi *vsi = NULL;
6896 struct i40e_pf *pf;
6897 int i, n = 0;
6898
6899 pf = veb->pf;
6900
6901 /* find the remaining VSI and check for extras */
6902 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6903 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6904 n++;
6905 vsi = pf->vsi[i];
6906 }
6907 }
6908 if (n != 1) {
6909 dev_info(&pf->pdev->dev,
6910 "can't remove VEB %d with %d VSIs left\n",
6911 veb->seid, n);
6912 return;
6913 }
6914
6915 /* move the remaining VSI to uplink veb */
6916 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6917 if (veb->uplink_seid) {
6918 vsi->uplink_seid = veb->uplink_seid;
6919 if (veb->uplink_seid == pf->mac_seid)
6920 vsi->veb_idx = I40E_NO_VEB;
6921 else
6922 vsi->veb_idx = veb->veb_idx;
6923 } else {
6924 /* floating VEB */
6925 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6926 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6927 }
6928
6929 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6930 i40e_veb_clear(veb);
6931
6932 return;
6933}
6934
6935/**
6936 * i40e_add_veb - create the VEB in the switch
6937 * @veb: the VEB to be instantiated
6938 * @vsi: the controlling VSI
6939 **/
6940static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6941{
56747264 6942 bool is_default = false;
e1c51b95 6943 bool is_cloud = false;
41c445ff
JB		 6944 int ret;
6945
6946 /* get a VEB from the hardware */
6947 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6948 veb->enabled_tc, is_default,
6949 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6950 if (ret) {
6951 dev_info(&veb->pf->pdev->dev,
6952 "couldn't add VEB, err %d, aq_err %d\n",
6953 ret, veb->pf->hw.aq.asq_last_status);
6954 return -EPERM;
6955 }
6956
6957 /* get statistics counter */
6958 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6959 &veb->stats_idx, NULL, NULL, NULL);
6960 if (ret) {
6961 dev_info(&veb->pf->pdev->dev,
6962 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6963 ret, veb->pf->hw.aq.asq_last_status);
6964 return -EPERM;
6965 }
6966 ret = i40e_veb_get_bw_info(veb);
6967 if (ret) {
6968 dev_info(&veb->pf->pdev->dev,
6969 "couldn't get VEB bw info, err %d, aq_err %d\n",
6970 ret, veb->pf->hw.aq.asq_last_status);
6971 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6972 return -ENOENT;
6973 }
6974
6975 vsi->uplink_seid = veb->seid;
6976 vsi->veb_idx = veb->idx;
6977 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6978
6979 return 0;
6980}
6981
6982/**
6983 * i40e_veb_setup - Set up a VEB
6984 * @pf: board private structure
6985 * @flags: VEB setup flags
6986 * @uplink_seid: the switch element to link to
6987 * @vsi_seid: the initial VSI seid
6988 * @enabled_tc: Enabled TC bit-map
6989 *
6990 * This allocates the sw VEB structure and links it into the switch
6991 * It is possible and legal for this to be a duplicate of an already
6992 * existing VEB. It is also possible for both uplink and vsi seids
6993 * to be zero, in order to create a floating VEB.
6994 *
6995 * Returns pointer to the successfully allocated VEB sw struct on
6996 * success, otherwise returns NULL on failure.
6997 **/
6998struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6999 u16 uplink_seid, u16 vsi_seid,
7000 u8 enabled_tc)
7001{
7002 struct i40e_veb *veb, *uplink_veb = NULL;
7003 int vsi_idx, veb_idx;
7004 int ret;
7005
7006 /* if one seid is 0, the other must be 0 to create a floating relay */
7007 if ((uplink_seid == 0 || vsi_seid == 0) &&
7008 (uplink_seid + vsi_seid != 0)) {
7009 dev_info(&pf->pdev->dev,
7010 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7011 uplink_seid, vsi_seid);
7012 return NULL;
7013 }
7014
7015 /* make sure there is such a vsi and uplink */
7016 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
7017 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7018 break;
7019 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
7020 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7021 vsi_seid);
7022 return NULL;
7023 }
7024
7025 if (uplink_seid && uplink_seid != pf->mac_seid) {
7026 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7027 if (pf->veb[veb_idx] &&
7028 pf->veb[veb_idx]->seid == uplink_seid) {
7029 uplink_veb = pf->veb[veb_idx];
7030 break;
7031 }
7032 }
7033 if (!uplink_veb) {
7034 dev_info(&pf->pdev->dev,
7035 "uplink seid %d not found\n", uplink_seid);
7036 return NULL;
7037 }
7038 }
7039
7040 /* get veb sw struct */
7041 veb_idx = i40e_veb_mem_alloc(pf);
7042 if (veb_idx < 0)
7043 goto err_alloc;
7044 veb = pf->veb[veb_idx];
7045 veb->flags = flags;
7046 veb->uplink_seid = uplink_seid;
7047 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7048 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7049
7050 /* create the VEB in the switch */
7051 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7052 if (ret)
7053 goto err_veb;
7054
7055 return veb;
7056
7057err_veb:
7058 i40e_veb_clear(veb);
7059err_alloc:
7060 return NULL;
7061}
7062
7063/**
7064 * i40e_setup_pf_switch_element - set pf vars based on switch type
7065 * @pf: board private structure
7066 * @ele: element we are building info from
7067 * @num_reported: total number of elements
7068 * @printconfig: should we print the contents
7069 *
7070 * helper function to assist in extracting a few useful SEID values.
7071 **/
7072static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7073 struct i40e_aqc_switch_config_element_resp *ele,
7074 u16 num_reported, bool printconfig)
7075{
7076 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7077 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7078 u8 element_type = ele->element_type;
7079 u16 seid = le16_to_cpu(ele->seid);
7080
7081 if (printconfig)
7082 dev_info(&pf->pdev->dev,
7083 "type=%d seid=%d uplink=%d downlink=%d\n",
7084 element_type, seid, uplink_seid, downlink_seid);
7085
7086 switch (element_type) {
7087 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7088 pf->mac_seid = seid;
7089 break;
7090 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7091 /* Main VEB? */
7092 if (uplink_seid != pf->mac_seid)
7093 break;
7094 if (pf->lan_veb == I40E_NO_VEB) {
7095 int v;
7096
7097 /* find existing or else empty VEB */
7098 for (v = 0; v < I40E_MAX_VEB; v++) {
7099 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7100 pf->lan_veb = v;
7101 break;
7102 }
7103 }
7104 if (pf->lan_veb == I40E_NO_VEB) {
7105 v = i40e_veb_mem_alloc(pf);
7106 if (v < 0)
7107 break;
7108 pf->lan_veb = v;
7109 }
7110 }
7111
7112 pf->veb[pf->lan_veb]->seid = seid;
7113 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7114 pf->veb[pf->lan_veb]->pf = pf;
7115 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7116 break;
7117 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7118 if (num_reported != 1)
7119 break;
7120 /* This is immediately after a reset so we can assume this is
7121 * the PF's VSI
7122 */
7123 pf->mac_seid = uplink_seid;
7124 pf->pf_seid = downlink_seid;
7125 pf->main_vsi_seid = seid;
7126 if (printconfig)
7127 dev_info(&pf->pdev->dev,
7128 "pf_seid=%d main_vsi_seid=%d\n",
7129 pf->pf_seid, pf->main_vsi_seid);
7130 break;
7131 case I40E_SWITCH_ELEMENT_TYPE_PF:
7132 case I40E_SWITCH_ELEMENT_TYPE_VF:
7133 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7134 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7135 case I40E_SWITCH_ELEMENT_TYPE_PE:
7136 case I40E_SWITCH_ELEMENT_TYPE_PA:
7137 /* ignore these for now */
7138 break;
7139 default:
7140 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7141 element_type, seid);
7142 break;
7143 }
7144}
7145
7146/**
7147 * i40e_fetch_switch_configuration - Get switch config from firmware
7148 * @pf: board private structure
7149 * @printconfig: should we print the contents
7150 *
7151 * Get the current switch configuration from the device and
7152 * extract a few useful SEID values.
7153 **/
7154int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7155{
7156 struct i40e_aqc_get_switch_config_resp *sw_config;
7157 u16 next_seid = 0;
7158 int ret = 0;
7159 u8 *aq_buf;
7160 int i;
7161
7162 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7163 if (!aq_buf)
7164 return -ENOMEM;
7165
7166 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7167 do {
7168 u16 num_reported, num_total;
7169
7170 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7171 I40E_AQ_LARGE_BUF,
7172 &next_seid, NULL);
7173 if (ret) {
7174 dev_info(&pf->pdev->dev,
7175 "get switch config failed %d aq_err=%x\n",
7176 ret, pf->hw.aq.asq_last_status);
7177 kfree(aq_buf);
7178 return -ENOENT;
7179 }
7180
7181 num_reported = le16_to_cpu(sw_config->header.num_reported);
7182 num_total = le16_to_cpu(sw_config->header.num_total);
7183
7184 if (printconfig)
7185 dev_info(&pf->pdev->dev,
7186 "header: %d reported %d total\n",
7187 num_reported, num_total);
7188
7189 if (num_reported) {
7190 int sz = sizeof(*sw_config) * num_reported;
7191
7192 kfree(pf->sw_config);
7193 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7194 if (pf->sw_config)
7195 memcpy(pf->sw_config, sw_config, sz);
7196 }
7197
7198 for (i = 0; i < num_reported; i++) {
7199 struct i40e_aqc_switch_config_element_resp *ele =
7200 &sw_config->element[i];
7201
7202 i40e_setup_pf_switch_element(pf, ele, num_reported,
7203 printconfig);
7204 }
7205 } while (next_seid != 0);
7206
7207 kfree(aq_buf);
7208 return ret;
7209}
7210
7211/**
7212 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7213 * @pf: board private structure
bc7d338f 7214 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7215 *
7216 * Returns 0 on success, negative value on failure
7217 **/
bc7d338f 7218static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7219{
895106a5 7220 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7221 int ret;
7222
7223 /* find out what's out there already */
7224 ret = i40e_fetch_switch_configuration(pf, false);
7225 if (ret) {
7226 dev_info(&pf->pdev->dev,
7227 "couldn't fetch switch config, err %d, aq_err %d\n",
7228 ret, pf->hw.aq.asq_last_status);
7229 return ret;
7230 }
7231 i40e_pf_reset_stats(pf);
7232
7233 /* fdir VSI must happen first to be sure it gets queue 0, but only
7234 * if there is enough room for the fdir VSI
7235 */
7236 if (pf->num_lan_qps > 1)
7237 i40e_fdir_setup(pf);
7238
7239 /* first time setup */
bc7d338f 7240 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7241 struct i40e_vsi *vsi = NULL;
7242 u16 uplink_seid;
7243
7244 /* Set up the PF VSI associated with the PF's main VSI
7245 * that is already in the HW switch
7246 */
7247 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7248 uplink_seid = pf->veb[pf->lan_veb]->seid;
7249 else
7250 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7251 if (pf->lan_vsi == I40E_NO_VSI)
7252 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7253 else if (reinit)
7254 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7255 if (!vsi) {
7256 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7257 i40e_fdir_teardown(pf);
7258 return -EAGAIN;
7259 }
41c445ff
JB		 7260 } else {
7261 /* force a reset of TC and queue layout configurations */
7262 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7263 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7264 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7265 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7266 }
7267 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7268
7269 /* Setup static PF queue filter control settings */
7270 ret = i40e_setup_pf_filter_control(pf);
7271 if (ret) {
7272 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7273 ret);
7274 /* Failure here should not stop continuing other steps */
7275 }
7276
7277 /* enable RSS in the HW, even for only one queue, as the stack can use
7278 * the hash
7279 */
7280 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7281 i40e_config_rss(pf);
7282
7283 /* fill in link information and enable LSE reporting */
7284 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7285 i40e_link_event(pf);
7286
d52c20b7 7287 /* Initialize user-specific link properties */
41c445ff
JB		 7288 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7289 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7290 /* requested_mode is set in probe or by ethtool */
7291 if (!pf->fc_autoneg_status)
7292 goto no_autoneg;
7293
7294 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7295 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7296 pf->hw.fc.current_mode = I40E_FC_FULL;
7297 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7298 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7299 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7300 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7301 else
d52c20b7
JB		 7302 pf->hw.fc.current_mode = I40E_FC_NONE;
7303
7304 /* sync the flow control settings with the auto-neg values */
7305 switch (pf->hw.fc.current_mode) {
7306 case I40E_FC_FULL:
7307 txfc = 1;
7308 rxfc = 1;
7309 break;
7310 case I40E_FC_TX_PAUSE:
7311 txfc = 1;
7312 rxfc = 0;
7313 break;
7314 case I40E_FC_RX_PAUSE:
7315 txfc = 0;
7316 rxfc = 1;
7317 break;
7318 case I40E_FC_NONE:
7319 case I40E_FC_DEFAULT:
7320 txfc = 0;
7321 rxfc = 0;
7322 break;
7323 case I40E_FC_PFC:
7324 /* TBD */
7325 break;
7326 /* no default case, we have to handle all possibilities here */
7327 }
7328
7329 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7330
7331 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7332 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7333 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7334
7335 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7336
d52c20b7
JB		 7337 goto fc_complete;
7338
7339no_autoneg:
7340 /* disable L2 flow control, user can turn it on if they wish */
7341 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7342 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7343 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7344
7345fc_complete:
beb0dff1
JK		 7346 i40e_ptp_init(pf);
7347
41c445ff
JB		 7348 return ret;
7349}
7350
7351/**
7352 * i40e_set_rss_size - helper to set rss_size
7353 * @pf: board private structure
7354 * @queues_left: how many queues
7355 */
7356static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7357{
7358 int num_tc0;
7359
7360 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7361 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7362 num_tc0 = rounddown_pow_of_two(num_tc0);
7363
7364 return num_tc0;
7365}
7366
7367/**
7368 * i40e_determine_queue_usage - Work out queue distribution
7369 * @pf: board private structure
7370 **/
7371static void i40e_determine_queue_usage(struct i40e_pf *pf)
7372{
7373 int accum_tc_size;
7374 int queues_left;
7375
7376 pf->num_lan_qps = 0;
7377 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7378 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7379
7380 /* Find the max queues to be put into basic use. We'll always be
7381 * using TC0, whether or not DCB is running, and TC0 will get the
7382 * big RSS set.
7383 */
7384 queues_left = pf->hw.func_caps.num_tx_qp;
7385
9f52987b 7386 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7387 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7388 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7389 (queues_left == 1)) {
7390
7391 /* one qp for PF, no queues for anything else */
7392 queues_left = 0;
7393 pf->rss_size = pf->num_lan_qps = 1;
7394
7395 /* make sure all the fancies are disabled */
7396 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7397 I40E_FLAG_FDIR_ENABLED |
7398 I40E_FLAG_FDIR_ATR_ENABLED |
7399 I40E_FLAG_DCB_ENABLED |
7400 I40E_FLAG_SRIOV_ENABLED |
7401 I40E_FLAG_VMDQ_ENABLED);
7402
7403 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7404 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7405 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7406
7407 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7408
7409 queues_left -= pf->rss_size;
f8ff1464 7410 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7411
7412 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7413 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7414 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7415
7416 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7417 * are set up for RSS in TC0
7418 */
7419 queues_left -= accum_tc_size;
7420
7421 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7422
7423 queues_left -= pf->rss_size;
7424 if (queues_left < 0) {
7425 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7426 return;
7427 }
7428
f8ff1464 7429 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7430
7431 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7432 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7433 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7434
7435 queues_left -= 1; /* save 1 queue for FD */
7436
7437 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7438
7439 queues_left -= pf->rss_size;
7440 if (queues_left < 0) {
7441 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7442 return;
7443 }
7444
f8ff1464 7445 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7446
7447 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7448 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7449 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7450
7451 /* save 1 queue for TCs 1 thru 7,
7452 * 1 queue for flow director,
7453 * and the rest are set up for RSS in TC0
7454 */
7455 queues_left -= 1;
7456 queues_left -= accum_tc_size;
7457
7458 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7459 queues_left -= pf->rss_size;
7460 if (queues_left < 0) {
7461 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7462 return;
7463 }
7464
f8ff1464 7465 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7466
7467 } else {
7468 dev_info(&pf->pdev->dev,
7469 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7470 return;
7471 }
7472
7473 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7474 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7475 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7476 pf->num_vf_qps));
7477 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7478 }
7479
7480 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7481 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7482 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7483 (queues_left / pf->num_vmdq_qps));
7484 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7485 }
7486
f8ff1464 7487 pf->queues_left = queues_left;
41c445ff
JB		 7488 return;
7489}
7490
7491/**
7492 * i40e_setup_pf_filter_control - Setup PF static filter control
7493 * @pf: PF to be setup
7494 *
7495 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7496 * settings. If PE/FCoE are enabled then it will also set the per PF
7497 * based filter sizes required for them. It also enables Flow director,
7498 * ethertype and macvlan type filter settings for the pf.
7499 *
7500 * Returns 0 on success, negative on failure
7501 **/
7502static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7503{
7504 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7505
7506 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7507
7508 /* Flow Director is enabled */
7509 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7510 settings->enable_fdir = true;
7511
7512 /* Ethtype and MACVLAN filters enabled for PF */
7513 settings->enable_ethtype = true;
7514 settings->enable_macvlan = true;
7515
7516 if (i40e_set_filter_control(&pf->hw, settings))
7517 return -ENOENT;
7518
7519 return 0;
7520}
7521
7522/**
7523 * i40e_probe - Device initialization routine
7524 * @pdev: PCI device information struct
7525 * @ent: entry in i40e_pci_tbl
7526 *
7527 * i40e_probe initializes a pf identified by a pci_dev structure.
7528 * The OS initialization, configuring of the pf private structure,
7529 * and a hardware reset occur.
7530 *
7531 * Returns 0 on success, negative on failure
7532 **/
7533static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7534{
7535 struct i40e_driver_version dv;
7536 struct i40e_pf *pf;
7537 struct i40e_hw *hw;
93cd765b 7538 static u16 pfs_found;
d4dfb81a 7539 u16 link_status;
41c445ff
JB		 7540 int err = 0;
7541 u32 len;
7542
7543 err = pci_enable_device_mem(pdev);
7544 if (err)
7545 return err;
7546
7547 /* set up for high or low dma */
7548 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7549 /* coherent mask for the same size will always succeed if
7550 * dma_set_mask does
7551 */
7552 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7553 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7554 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7555 } else {
7556 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7557 err = -EIO;
7558 goto err_dma;
7559 }
7560
7561 /* set up pci connections */
7562 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7563 IORESOURCE_MEM), i40e_driver_name);
7564 if (err) {
7565 dev_info(&pdev->dev,
7566 "pci_request_selected_regions failed %d\n", err);
7567 goto err_pci_reg;
7568 }
7569
7570 pci_enable_pcie_error_reporting(pdev);
7571 pci_set_master(pdev);
7572
7573 /* Now that we have a PCI connection, we need to do the
7574 * low level device setup. This is primarily setting up
7575 * the Admin Queue structures and then querying for the
7576 * device's current profile information.
7577 */
7578 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7579 if (!pf) {
7580 err = -ENOMEM;
7581 goto err_pf_alloc;
7582 }
7583 pf->next_vsi = 0;
7584 pf->pdev = pdev;
7585 set_bit(__I40E_DOWN, &pf->state);
7586
7587 hw = &pf->hw;
7588 hw->back = pf;
7589 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7590 pci_resource_len(pdev, 0));
7591 if (!hw->hw_addr) {
7592 err = -EIO;
7593 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7594 (unsigned int)pci_resource_start(pdev, 0),
7595 (unsigned int)pci_resource_len(pdev, 0), err);
7596 goto err_ioremap;
7597 }
7598 hw->vendor_id = pdev->vendor;
7599 hw->device_id = pdev->device;
7600 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7601 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7602 hw->subsystem_device_id = pdev->subsystem_device;
7603 hw->bus.device = PCI_SLOT(pdev->devfn);
7604 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7605 pf->instance = pfs_found;
41c445ff 7606
7134f9ce
JB		 7607 /* do a special CORER for clearing PXE mode once at init */
7608 if (hw->revision_id == 0 &&
7609 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7610 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7611 i40e_flush(hw);
7612 msleep(200);
7613 pf->corer_count++;
7614
7615 i40e_clear_pxe_mode(hw);
7616 }
7617
41c445ff
JB		 7618 /* Reset here to make sure all is clean and to define PF 'n' */
7619 err = i40e_pf_reset(hw);
7620 if (err) {
7621 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7622 goto err_pf_reset;
7623 }
7624 pf->pfr_count++;
7625
7626 hw->aq.num_arq_entries = I40E_AQ_LEN;
7627 hw->aq.num_asq_entries = I40E_AQ_LEN;
7628 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7629 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7630 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7631 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7632 "%s-pf%d:misc",
7633 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7634
7635 err = i40e_init_shared_code(hw);
7636 if (err) {
7637 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7638 goto err_pf_reset;
7639 }
7640
d52c20b7
JB		 7641 /* set up a default setting for link flow control */
7642 pf->hw.fc.requested_mode = I40E_FC_NONE;
7643
41c445ff
JB		 7644 err = i40e_init_adminq(hw);
7645 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7646 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7647 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7648 dev_info(&pdev->dev,
7649 "warning: NVM version not supported, supported version: %02x.%02x\n",
7650 I40E_CURRENT_NVM_VERSION_HI,
7651 I40E_CURRENT_NVM_VERSION_LO);
7652 }
41c445ff
JB		 7653 if (err) {
7654 dev_info(&pdev->dev,
7655 "init_adminq failed: %d expecting API %02x.%02x\n",
7656 err,
7657 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7658 goto err_pf_reset;
7659 }
7660
6ff4ef86 7661 i40e_clear_pxe_mode(hw);
41c445ff
JB		 7662 err = i40e_get_capabilities(pf);
7663 if (err)
7664 goto err_adminq_setup;
7665
7666 err = i40e_sw_init(pf);
7667 if (err) {
7668 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7669 goto err_sw_init;
7670 }
7671
7672 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7673 hw->func_caps.num_rx_qp,
7674 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7675 if (err) {
7676 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7677 goto err_init_lan_hmc;
7678 }
7679
7680 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7681 if (err) {
7682 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7683 err = -ENOENT;
7684 goto err_configure_lan_hmc;
7685 }
7686
7687 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7688 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7689 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7690 err = -EIO;
7691 goto err_mac_addr;
7692 }
7693 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7694 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7695
7696 pci_set_drvdata(pdev, pf);
7697 pci_save_state(pdev);
7698
7699 /* set up periodic task facility */
7700 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7701 pf->service_timer_period = HZ;
7702
7703 INIT_WORK(&pf->service_task, i40e_service_task);
7704 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7705 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7706 pf->link_check_timeout = jiffies;
7707
8e2773ae
SN		 7708 /* WoL defaults to disabled */
7709 pf->wol_en = false;
7710 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7711
41c445ff
JB		 7712 /* set up the main switch operations */
7713 i40e_determine_queue_usage(pf);
7714 i40e_init_interrupt_scheme(pf);
7715
7716 /* Set up the *vsi struct based on the number of VSIs in the HW,
7717 * and set up our local tracking of the MAIN PF vsi.
7718 */
7719 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7720 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7721 if (!pf->vsi) {
7722 err = -ENOMEM;
41c445ff 7723 goto err_switch_setup;
ed87ac09 7724 }
41c445ff 7725
bc7d338f 7726 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7727 if (err) {
7728 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7729 goto err_vsis;
7730 }
7731
7732 /* The main driver is (mostly) up and happy. We need to set this state
7733 * before setting up the misc vector or we get a race and the vector
7734 * ends up disabled forever.
7735 */
7736 clear_bit(__I40E_DOWN, &pf->state);
7737
7738 /* In case of MSIX we are going to setup the misc vector right here
7739 * to handle admin queue events etc. In case of legacy and MSI
7740 * the misc functionality and queue processing is combined in
7741 * the same vector and that gets setup at open.
7742 */
7743 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7744 err = i40e_setup_misc_vector(pf);
7745 if (err) {
7746 dev_info(&pdev->dev,
7747 "setup of misc vector failed: %d\n", err);
7748 goto err_vsis;
7749 }
7750 }
7751
7752 /* prep for VF support */
7753 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7754 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7755 u32 val;
7756
7757 /* disable link interrupts for VFs */
7758 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7759 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7760 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7761 i40e_flush(hw);
7762 }
7763
93cd765b
ASJ		 7764 pfs_found++;
7765
41c445ff
JB		 7766 i40e_dbg_pf_init(pf);
7767
7768 /* tell the firmware that we're starting */
7769 dv.major_version = DRV_VERSION_MAJOR;
7770 dv.minor_version = DRV_VERSION_MINOR;
7771 dv.build_version = DRV_VERSION_BUILD;
7772 dv.subbuild_version = 0;
7773 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7774
7775 /* since everything's happy, start the service_task timer */
7776 mod_timer(&pf->service_timer,
7777 round_jiffies(jiffies + pf->service_timer_period));
7778
d4dfb81a
CS		 7779 /* Get the negotiated link width and speed from PCI config space */
7780 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7781
7782 i40e_set_pci_config_data(hw, link_status);
7783
7784 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7785 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7786 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7787 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7788 "Unknown"),
7789 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7790 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7791 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7792 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7793 "Unknown"));
7794
7795 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7796 hw->bus.speed < i40e_bus_speed_8000) {
7797 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7798 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7799 }
7800
41c445ff
JB		 7801 return 0;
7802
7803 /* Unwind what we've done if something failed in the setup */
7804err_vsis:
7805 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7806 i40e_clear_interrupt_scheme(pf);
7807 kfree(pf->vsi);
04b03013
SN		 7808err_switch_setup:
7809 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7810 del_timer_sync(&pf->service_timer);
7811err_mac_addr:
7812err_configure_lan_hmc:
7813 (void)i40e_shutdown_lan_hmc(hw);
7814err_init_lan_hmc:
7815 kfree(pf->qp_pile);
7816 kfree(pf->irq_pile);
7817err_sw_init:
7818err_adminq_setup:
7819 (void)i40e_shutdown_adminq(hw);
7820err_pf_reset:
7821 iounmap(hw->hw_addr);
7822err_ioremap:
7823 kfree(pf);
7824err_pf_alloc:
7825 pci_disable_pcie_error_reporting(pdev);
7826 pci_release_selected_regions(pdev,
7827 pci_select_bars(pdev, IORESOURCE_MEM));
7828err_pci_reg:
7829err_dma:
7830 pci_disable_device(pdev);
7831 return err;
7832}
7833
7834/**
7835 * i40e_remove - Device removal routine
7836 * @pdev: PCI device information struct
7837 *
7838 * i40e_remove is called by the PCI subsystem to alert the driver
7839 * that is should release a PCI device. This could be caused by a
7840 * Hot-Plug event, or because the driver is going to be removed from
7841 * memory.
7842 **/
7843static void i40e_remove(struct pci_dev *pdev)
7844{
7845 struct i40e_pf *pf = pci_get_drvdata(pdev);
7846 i40e_status ret_code;
7847 u32 reg;
7848 int i;
7849
7850 i40e_dbg_pf_exit(pf);
7851
beb0dff1
JK		 7852 i40e_ptp_stop(pf);
7853
41c445ff
JB		 7854 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7855 i40e_free_vfs(pf);
7856 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7857 }
7858
7859 /* no more scheduling of any task */
7860 set_bit(__I40E_DOWN, &pf->state);
7861 del_timer_sync(&pf->service_timer);
7862 cancel_work_sync(&pf->service_task);
7863
7864 i40e_fdir_teardown(pf);
7865
7866 /* If there is a switch structure or any orphans, remove them.
7867 * This will leave only the PF's VSI remaining.
7868 */
7869 for (i = 0; i < I40E_MAX_VEB; i++) {
7870 if (!pf->veb[i])
7871 continue;
7872
7873 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7874 pf->veb[i]->uplink_seid == 0)
7875 i40e_switch_branch_release(pf->veb[i]);
7876 }
7877
7878 /* Now we can shutdown the PF's VSI, just before we kill
7879 * adminq and hmc.
7880 */
7881 if (pf->vsi[pf->lan_vsi])
7882 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7883
7884 i40e_stop_misc_vector(pf);
7885 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7886 synchronize_irq(pf->msix_entries[0].vector);
7887 free_irq(pf->msix_entries[0].vector, pf);
7888 }
7889
7890 /* shutdown and destroy the HMC */
7891 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7892 if (ret_code)
7893 dev_warn(&pdev->dev,
7894 "Failed to destroy the HMC resources: %d\n", ret_code);
7895
7896 /* shutdown the adminq */
41c445ff
JB		 7897 ret_code = i40e_shutdown_adminq(&pf->hw);
7898 if (ret_code)
7899 dev_warn(&pdev->dev,
7900 "Failed to destroy the Admin Queue resources: %d\n",
7901 ret_code);
7902
7903 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7904 i40e_clear_interrupt_scheme(pf);
7905 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7906 if (pf->vsi[i]) {
7907 i40e_vsi_clear_rings(pf->vsi[i]);
7908 i40e_vsi_clear(pf->vsi[i]);
7909 pf->vsi[i] = NULL;
7910 }
7911 }
7912
7913 for (i = 0; i < I40E_MAX_VEB; i++) {
7914 kfree(pf->veb[i]);
7915 pf->veb[i] = NULL;
7916 }
7917
7918 kfree(pf->qp_pile);
7919 kfree(pf->irq_pile);
7920 kfree(pf->sw_config);
7921 kfree(pf->vsi);
7922
7923 /* force a PF reset to clean anything leftover */
7924 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7925 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7926 i40e_flush(&pf->hw);
7927
7928 iounmap(pf->hw.hw_addr);
7929 kfree(pf);
7930 pci_release_selected_regions(pdev,
7931 pci_select_bars(pdev, IORESOURCE_MEM));
7932
7933 pci_disable_pcie_error_reporting(pdev);
7934 pci_disable_device(pdev);
7935}
7936
7937/**
7938 * i40e_pci_error_detected - warning that something funky happened in PCI land
7939 * @pdev: PCI device information struct
7940 *
7941 * Called to warn that something happened and the error handling steps
7942 * are in progress. Allows the driver to quiesce things, be ready for
7943 * remediation.
7944 **/
7945static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7946 enum pci_channel_state error)
7947{
7948 struct i40e_pf *pf = pci_get_drvdata(pdev);
7949
7950 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7951
7952 /* shutdown all operations */
9007bccd
SN		 7953 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7954 rtnl_lock();
7955 i40e_prep_for_reset(pf);
7956 rtnl_unlock();
7957 }
41c445ff
JB		 7958
7959 /* Request a slot reset */
7960 return PCI_ERS_RESULT_NEED_RESET;
7961}
7962
7963/**
7964 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7965 * @pdev: PCI device information struct
7966 *
7967 * Called to find if the driver can work with the device now that
7968 * the pci slot has been reset. If a basic connection seems good
7969 * (registers are readable and have sane content) then return a
7970 * happy little PCI_ERS_RESULT_xxx.
7971 **/
7972static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7973{
7974 struct i40e_pf *pf = pci_get_drvdata(pdev);
7975 pci_ers_result_t result;
7976 int err;
7977 u32 reg;
7978
7979 dev_info(&pdev->dev, "%s\n", __func__);
7980 if (pci_enable_device_mem(pdev)) {
7981 dev_info(&pdev->dev,
7982 "Cannot re-enable PCI device after reset.\n");
7983 result = PCI_ERS_RESULT_DISCONNECT;
7984 } else {
7985 pci_set_master(pdev);
7986 pci_restore_state(pdev);
7987 pci_save_state(pdev);
7988 pci_wake_from_d3(pdev, false);
7989
7990 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7991 if (reg == 0)
7992 result = PCI_ERS_RESULT_RECOVERED;
7993 else
7994 result = PCI_ERS_RESULT_DISCONNECT;
7995 }
7996
7997 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7998 if (err) {
7999 dev_info(&pdev->dev,
8000 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8001 err);
8002 /* non-fatal, continue */
8003 }
8004
8005 return result;
8006}
8007
8008/**
8009 * i40e_pci_error_resume - restart operations after PCI error recovery
8010 * @pdev: PCI device information struct
8011 *
8012 * Called to allow the driver to bring things back up after PCI error
8013 * and/or reset recovery has finished.
8014 **/
8015static void i40e_pci_error_resume(struct pci_dev *pdev)
8016{
8017 struct i40e_pf *pf = pci_get_drvdata(pdev);
8018
8019 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8020 if (test_bit(__I40E_SUSPENDED, &pf->state))
8021 return;
8022
8023 rtnl_lock();
41c445ff 8024 i40e_handle_reset_warning(pf);
9007bccd
SN		 8025 rtnl_lock();
8026}
8027
8028/**
8029 * i40e_shutdown - PCI callback for shutting down
8030 * @pdev: PCI device information struct
8031 **/
8032static void i40e_shutdown(struct pci_dev *pdev)
8033{
8034 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8035 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8036
8037 set_bit(__I40E_SUSPENDED, &pf->state);
8038 set_bit(__I40E_DOWN, &pf->state);
8039 rtnl_lock();
8040 i40e_prep_for_reset(pf);
8041 rtnl_unlock();
8042
8e2773ae
SN		 8043 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8044 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8045
9007bccd 8046 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8047 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8048 pci_set_power_state(pdev, PCI_D3hot);
8049 }
8050}
8051
8052#ifdef CONFIG_PM
8053/**
8054 * i40e_suspend - PCI callback for moving to D3
8055 * @pdev: PCI device information struct
8056 **/
8057static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8058{
8059 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8060 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8061
8062 set_bit(__I40E_SUSPENDED, &pf->state);
8063 set_bit(__I40E_DOWN, &pf->state);
8064 rtnl_lock();
8065 i40e_prep_for_reset(pf);
8066 rtnl_unlock();
8067
8e2773ae
SN		 8068 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8069 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8070
8071 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8072 pci_set_power_state(pdev, PCI_D3hot);
8073
8074 return 0;
41c445ff
JB		 8075}
8076
9007bccd
SN		 8077/**
8078 * i40e_resume - PCI callback for waking up from D3
8079 * @pdev: PCI device information struct
8080 **/
8081static int i40e_resume(struct pci_dev *pdev)
8082{
8083 struct i40e_pf *pf = pci_get_drvdata(pdev);
8084 u32 err;
8085
8086 pci_set_power_state(pdev, PCI_D0);
8087 pci_restore_state(pdev);
8088 /* pci_restore_state() clears dev->state_saves, so
8089 * call pci_save_state() again to restore it.
8090 */
8091 pci_save_state(pdev);
8092
8093 err = pci_enable_device_mem(pdev);
8094 if (err) {
8095 dev_err(&pdev->dev,
8096 "%s: Cannot enable PCI device from suspend\n",
8097 __func__);
8098 return err;
8099 }
8100 pci_set_master(pdev);
8101
8102 /* no wakeup events while running */
8103 pci_wake_from_d3(pdev, false);
8104
8105 /* handling the reset will rebuild the device state */
8106 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8107 clear_bit(__I40E_DOWN, &pf->state);
8108 rtnl_lock();
8109 i40e_reset_and_rebuild(pf, false);
8110 rtnl_unlock();
8111 }
8112
8113 return 0;
8114}
8115
8116#endif
41c445ff
JB		 8117static const struct pci_error_handlers i40e_err_handler = {
8118 .error_detected = i40e_pci_error_detected,
8119 .slot_reset = i40e_pci_error_slot_reset,
8120 .resume = i40e_pci_error_resume,
8121};
8122
8123static struct pci_driver i40e_driver = {
8124 .name = i40e_driver_name,
8125 .id_table = i40e_pci_tbl,
8126 .probe = i40e_probe,
8127 .remove = i40e_remove,
9007bccd
SN		 8128#ifdef CONFIG_PM
8129 .suspend = i40e_suspend,
8130 .resume = i40e_resume,
8131#endif
8132 .shutdown = i40e_shutdown,
41c445ff
JB		 8133 .err_handler = &i40e_err_handler,
8134 .sriov_configure = i40e_pci_sriov_configure,
8135};
8136
8137/**
8138 * i40e_init_module - Driver registration routine
8139 *
8140 * i40e_init_module is the first routine called when the driver is
8141 * loaded. All it does is register with the PCI subsystem.
8142 **/
8143static int __init i40e_init_module(void)
8144{
8145 pr_info("%s: %s - version %s\n", i40e_driver_name,
8146 i40e_driver_string, i40e_driver_version_str);
8147 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8148 i40e_dbg_init();
8149 return pci_register_driver(&i40e_driver);
8150}
8151module_init(i40e_init_module);
8152
8153/**
8154 * i40e_exit_module - Driver exit cleanup routine
8155 *
8156 * i40e_exit_module is called just before the driver is removed
8157 * from memory.
8158 **/
8159static void __exit i40e_exit_module(void)
8160{
8161 pci_unregister_driver(&i40e_driver);
8162 i40e_dbg_exit();
8163}
8164module_exit(i40e_exit_module);
Linux kernel - Deliverables
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