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i40e: Expose AQ debugfs hooks
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28/* Local includes */
29#include "i40e.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
41#define DRV_VERSION_MINOR 3
582a74e5 42#define DRV_VERSION_BUILD 14
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
47static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
58
59/* i40e_pci_tbl - PCI Device ID Table
60 *
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
67 {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
68 {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
69 {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
70 {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
71 {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
72 {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
73 {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
74 {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
75 {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
76 {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
307 i40e_down(vsi);
308 break;
309 }
310 i40e_service_event_schedule(pf);
311 pf->tx_timeout_recovery_level++;
312}
313
314/**
315 * i40e_release_rx_desc - Store the new tail and head values
316 * @rx_ring: ring to bump
317 * @val: new head index
318 **/
319static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
320{
321 rx_ring->next_to_use = val;
322
323 /* Force memory writes to complete before letting h/w
324 * know there are new descriptors to fetch. (Only
325 * applicable for weak-ordered memory model archs,
326 * such as IA-64).
327 */
328 wmb();
329 writel(val, rx_ring->tail);
330}
331
332/**
333 * i40e_get_vsi_stats_struct - Get System Network Statistics
334 * @vsi: the VSI we care about
335 *
336 * Returns the address of the device statistics structure.
337 * The statistics are actually updated from the service task.
338 **/
339struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
340{
341 return &vsi->net_stats;
342}
343
344/**
345 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
346 * @netdev: network interface device structure
347 *
348 * Returns the address of the device statistics structure.
349 * The statistics are actually updated from the service task.
350 **/
351static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
352 struct net_device *netdev,
980e9b11 353 struct rtnl_link_stats64 *stats)
41c445ff
JB		 354{
355 struct i40e_netdev_priv *np = netdev_priv(netdev);
356 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 357 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
358 int i;
359
143c9054 360
bc7d338f
ASJ		 361 if (test_bit(__I40E_DOWN, &vsi->state))
362 return stats;
363
3c325ced
JB		 364 if (!vsi->tx_rings)
365 return stats;
366
980e9b11
AD		 367 rcu_read_lock();
368 for (i = 0; i < vsi->num_queue_pairs; i++) {
369 struct i40e_ring *tx_ring, *rx_ring;
370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
378 start = u64_stats_fetch_begin_bh(&tx_ring->syncp);
379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
381 } while (u64_stats_fetch_retry_bh(&tx_ring->syncp, start));
382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
388 start = u64_stats_fetch_begin_bh(&rx_ring->syncp);
389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
391 } while (u64_stats_fetch_retry_bh(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
398 /* following stats updated by ixgbe_watchdog_task() */
399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
426 if (vsi->rx_rings)
427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff
JB		 436 }
437 vsi->stat_offsets_loaded = false;
438}
439
440/**
441 * i40e_pf_reset_stats - Reset all of the stats for the given pf
442 * @pf: the PF to be reset
443 **/
444void i40e_pf_reset_stats(struct i40e_pf *pf)
445{
446 memset(&pf->stats, 0, sizeof(pf->stats));
447 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
448 pf->stat_offsets_loaded = false;
449}
450
451/**
452 * i40e_stat_update48 - read and update a 48 bit stat from the chip
453 * @hw: ptr to the hardware info
454 * @hireg: the high 32 bit reg to read
455 * @loreg: the low 32 bit reg to read
456 * @offset_loaded: has the initial offset been loaded yet
457 * @offset: ptr to current offset value
458 * @stat: ptr to the stat
459 *
460 * Since the device stats are not reset at PFReset, they likely will not
461 * be zeroed when the driver starts. We'll save the first values read
462 * and use them as offsets to be subtracted from the raw values in order
463 * to report stats that count from zero. In the process, we also manage
464 * the potential roll-over.
465 **/
466static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
467 bool offset_loaded, u64 *offset, u64 *stat)
468{
469 u64 new_data;
470
471 if (hw->device_id == I40E_QEMU_DEVICE_ID) {
472 new_data = rd32(hw, loreg);
473 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
474 } else {
475 new_data = rd64(hw, loreg);
476 }
477 if (!offset_loaded)
478 *offset = new_data;
479 if (likely(new_data >= *offset))
480 *stat = new_data - *offset;
481 else
482 *stat = (new_data + ((u64)1 << 48)) - *offset;
483 *stat &= 0xFFFFFFFFFFFFULL;
484}
485
486/**
487 * i40e_stat_update32 - read and update a 32 bit stat from the chip
488 * @hw: ptr to the hardware info
489 * @reg: the hw reg to read
490 * @offset_loaded: has the initial offset been loaded yet
491 * @offset: ptr to current offset value
492 * @stat: ptr to the stat
493 **/
494static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
495 bool offset_loaded, u64 *offset, u64 *stat)
496{
497 u32 new_data;
498
499 new_data = rd32(hw, reg);
500 if (!offset_loaded)
501 *offset = new_data;
502 if (likely(new_data >= *offset))
503 *stat = (u32)(new_data - *offset);
504 else
505 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
506}
507
508/**
509 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
510 * @vsi: the VSI to be updated
511 **/
512void i40e_update_eth_stats(struct i40e_vsi *vsi)
513{
514 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
515 struct i40e_pf *pf = vsi->back;
516 struct i40e_hw *hw = &pf->hw;
517 struct i40e_eth_stats *oes;
518 struct i40e_eth_stats *es; /* device's eth stats */
519
520 es = &vsi->eth_stats;
521 oes = &vsi->eth_stats_offsets;
522
523 /* Gather up the stats that the hw collects */
524 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
525 vsi->stat_offsets_loaded,
526 &oes->tx_errors, &es->tx_errors);
527 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
528 vsi->stat_offsets_loaded,
529 &oes->rx_discards, &es->rx_discards);
530
531 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
532 I40E_GLV_GORCL(stat_idx),
533 vsi->stat_offsets_loaded,
534 &oes->rx_bytes, &es->rx_bytes);
535 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
536 I40E_GLV_UPRCL(stat_idx),
537 vsi->stat_offsets_loaded,
538 &oes->rx_unicast, &es->rx_unicast);
539 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
540 I40E_GLV_MPRCL(stat_idx),
541 vsi->stat_offsets_loaded,
542 &oes->rx_multicast, &es->rx_multicast);
543 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
544 I40E_GLV_BPRCL(stat_idx),
545 vsi->stat_offsets_loaded,
546 &oes->rx_broadcast, &es->rx_broadcast);
547
548 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
549 I40E_GLV_GOTCL(stat_idx),
550 vsi->stat_offsets_loaded,
551 &oes->tx_bytes, &es->tx_bytes);
552 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
553 I40E_GLV_UPTCL(stat_idx),
554 vsi->stat_offsets_loaded,
555 &oes->tx_unicast, &es->tx_unicast);
556 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
557 I40E_GLV_MPTCL(stat_idx),
558 vsi->stat_offsets_loaded,
559 &oes->tx_multicast, &es->tx_multicast);
560 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
561 I40E_GLV_BPTCL(stat_idx),
562 vsi->stat_offsets_loaded,
563 &oes->tx_broadcast, &es->tx_broadcast);
564 vsi->stat_offsets_loaded = true;
565}
566
567/**
568 * i40e_update_veb_stats - Update Switch component statistics
569 * @veb: the VEB being updated
570 **/
571static void i40e_update_veb_stats(struct i40e_veb *veb)
572{
573 struct i40e_pf *pf = veb->pf;
574 struct i40e_hw *hw = &pf->hw;
575 struct i40e_eth_stats *oes;
576 struct i40e_eth_stats *es; /* device's eth stats */
577 int idx = 0;
578
579 idx = veb->stats_idx;
580 es = &veb->stats;
581 oes = &veb->stats_offsets;
582
583 /* Gather up the stats that the hw collects */
584 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
585 veb->stat_offsets_loaded,
586 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 587 if (hw->revision_id > 0)
588 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
589 veb->stat_offsets_loaded,
590 &oes->rx_unknown_protocol,
591 &es->rx_unknown_protocol);
41c445ff
JB		 592 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
593 veb->stat_offsets_loaded,
594 &oes->rx_bytes, &es->rx_bytes);
595 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unicast, &es->rx_unicast);
598 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
599 veb->stat_offsets_loaded,
600 &oes->rx_multicast, &es->rx_multicast);
601 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
602 veb->stat_offsets_loaded,
603 &oes->rx_broadcast, &es->rx_broadcast);
604
605 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->tx_bytes, &es->tx_bytes);
608 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->tx_unicast, &es->tx_unicast);
611 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
612 veb->stat_offsets_loaded,
613 &oes->tx_multicast, &es->tx_multicast);
614 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
615 veb->stat_offsets_loaded,
616 &oes->tx_broadcast, &es->tx_broadcast);
617 veb->stat_offsets_loaded = true;
618}
619
620/**
621 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
622 * @pf: the corresponding PF
623 *
624 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
625 **/
626static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
627{
628 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
629 struct i40e_hw_port_stats *nsd = &pf->stats;
630 struct i40e_hw *hw = &pf->hw;
631 u64 xoff = 0;
632 u16 i, v;
633
634 if ((hw->fc.current_mode != I40E_FC_FULL) &&
635 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
636 return;
637
638 xoff = nsd->link_xoff_rx;
639 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
640 pf->stat_offsets_loaded,
641 &osd->link_xoff_rx, &nsd->link_xoff_rx);
642
643 /* No new LFC xoff rx */
644 if (!(nsd->link_xoff_rx - xoff))
645 return;
646
647 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
648 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
649 struct i40e_vsi *vsi = pf->vsi[v];
650
651 if (!vsi)
652 continue;
653
654 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 655 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 656 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
657 }
658 }
659}
660
661/**
662 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
663 * @pf: the corresponding PF
664 *
665 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
666 **/
667static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
668{
669 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
670 struct i40e_hw_port_stats *nsd = &pf->stats;
671 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
672 struct i40e_dcbx_config *dcb_cfg;
673 struct i40e_hw *hw = &pf->hw;
674 u16 i, v;
675 u8 tc;
676
677 dcb_cfg = &hw->local_dcbx_config;
678
679 /* See if DCB enabled with PFC TC */
680 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
681 !(dcb_cfg->pfc.pfcenable)) {
682 i40e_update_link_xoff_rx(pf);
683 return;
684 }
685
686 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
687 u64 prio_xoff = nsd->priority_xoff_rx[i];
688 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
689 pf->stat_offsets_loaded,
690 &osd->priority_xoff_rx[i],
691 &nsd->priority_xoff_rx[i]);
692
693 /* No new PFC xoff rx */
694 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
695 continue;
696 /* Get the TC for given priority */
697 tc = dcb_cfg->etscfg.prioritytable[i];
698 xoff[tc] = true;
699 }
700
701 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
702 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
703 struct i40e_vsi *vsi = pf->vsi[v];
704
705 if (!vsi)
706 continue;
707
708 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 709 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 710
711 tc = ring->dcb_tc;
712 if (xoff[tc])
713 clear_bit(__I40E_HANG_CHECK_ARMED,
714 &ring->state);
715 }
716 }
717}
718
719/**
720 * i40e_update_stats - Update the board statistics counters.
721 * @vsi: the VSI to be updated
722 *
723 * There are a few instances where we store the same stat in a
724 * couple of different structs. This is partly because we have
725 * the netdev stats that need to be filled out, which is slightly
726 * different from the "eth_stats" defined by the chip and used in
727 * VF communications. We sort it all out here in a central place.
728 **/
729void i40e_update_stats(struct i40e_vsi *vsi)
730{
731 struct i40e_pf *pf = vsi->back;
732 struct i40e_hw *hw = &pf->hw;
733 struct rtnl_link_stats64 *ons;
734 struct rtnl_link_stats64 *ns; /* netdev stats */
735 struct i40e_eth_stats *oes;
736 struct i40e_eth_stats *es; /* device's eth stats */
737 u32 tx_restart, tx_busy;
738 u32 rx_page, rx_buf;
739 u64 rx_p, rx_b;
740 u64 tx_p, tx_b;
741 int i;
742 u16 q;
743
744 if (test_bit(__I40E_DOWN, &vsi->state) ||
745 test_bit(__I40E_CONFIG_BUSY, &pf->state))
746 return;
747
748 ns = i40e_get_vsi_stats_struct(vsi);
749 ons = &vsi->net_stats_offsets;
750 es = &vsi->eth_stats;
751 oes = &vsi->eth_stats_offsets;
752
753 /* Gather up the netdev and vsi stats that the driver collects
754 * on the fly during packet processing
755 */
756 rx_b = rx_p = 0;
757 tx_b = tx_p = 0;
758 tx_restart = tx_busy = 0;
759 rx_page = 0;
760 rx_buf = 0;
980e9b11 761 rcu_read_lock();
41c445ff
JB		 762 for (q = 0; q < vsi->num_queue_pairs; q++) {
763 struct i40e_ring *p;
980e9b11
AD		 764 u64 bytes, packets;
765 unsigned int start;
766
767 /* locate Tx ring */
768 p = ACCESS_ONCE(vsi->tx_rings[q]);
769
770 do {
771 start = u64_stats_fetch_begin_bh(&p->syncp);
772 packets = p->stats.packets;
773 bytes = p->stats.bytes;
774 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
775 tx_b += bytes;
776 tx_p += packets;
777 tx_restart += p->tx_stats.restart_queue;
778 tx_busy += p->tx_stats.tx_busy;
41c445ff 779
980e9b11
AD		 780 /* Rx queue is part of the same block as Tx queue */
781 p = &p[1];
782 do {
783 start = u64_stats_fetch_begin_bh(&p->syncp);
784 packets = p->stats.packets;
785 bytes = p->stats.bytes;
786 } while (u64_stats_fetch_retry_bh(&p->syncp, start));
787 rx_b += bytes;
788 rx_p += packets;
41c445ff
JB		 789 rx_buf += p->rx_stats.alloc_rx_buff_failed;
790 rx_page += p->rx_stats.alloc_rx_page_failed;
41c445ff 791 }
980e9b11 792 rcu_read_unlock();
41c445ff
JB		 793 vsi->tx_restart = tx_restart;
794 vsi->tx_busy = tx_busy;
795 vsi->rx_page_failed = rx_page;
796 vsi->rx_buf_failed = rx_buf;
797
798 ns->rx_packets = rx_p;
799 ns->rx_bytes = rx_b;
800 ns->tx_packets = tx_p;
801 ns->tx_bytes = tx_b;
802
803 i40e_update_eth_stats(vsi);
804 /* update netdev stats from eth stats */
805 ons->rx_errors = oes->rx_errors;
806 ns->rx_errors = es->rx_errors;
807 ons->tx_errors = oes->tx_errors;
808 ns->tx_errors = es->tx_errors;
809 ons->multicast = oes->rx_multicast;
810 ns->multicast = es->rx_multicast;
811 ons->tx_dropped = oes->tx_discards;
812 ns->tx_dropped = es->tx_discards;
813
814 /* Get the port data only if this is the main PF VSI */
815 if (vsi == pf->vsi[pf->lan_vsi]) {
816 struct i40e_hw_port_stats *nsd = &pf->stats;
817 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
818
819 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
820 I40E_GLPRT_GORCL(hw->port),
821 pf->stat_offsets_loaded,
822 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
823 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
824 I40E_GLPRT_GOTCL(hw->port),
825 pf->stat_offsets_loaded,
826 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
827 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
828 pf->stat_offsets_loaded,
829 &osd->eth.rx_discards,
830 &nsd->eth.rx_discards);
831 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
832 pf->stat_offsets_loaded,
833 &osd->eth.tx_discards,
834 &nsd->eth.tx_discards);
835 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
836 I40E_GLPRT_MPRCL(hw->port),
837 pf->stat_offsets_loaded,
838 &osd->eth.rx_multicast,
839 &nsd->eth.rx_multicast);
840
841 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
842 pf->stat_offsets_loaded,
843 &osd->tx_dropped_link_down,
844 &nsd->tx_dropped_link_down);
845
846 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
847 pf->stat_offsets_loaded,
848 &osd->crc_errors, &nsd->crc_errors);
849 ns->rx_crc_errors = nsd->crc_errors;
850
851 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->illegal_bytes, &nsd->illegal_bytes);
854 ns->rx_errors = nsd->crc_errors
855 + nsd->illegal_bytes;
856
857 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->mac_local_faults,
860 &nsd->mac_local_faults);
861 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
862 pf->stat_offsets_loaded,
863 &osd->mac_remote_faults,
864 &nsd->mac_remote_faults);
865
866 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
867 pf->stat_offsets_loaded,
868 &osd->rx_length_errors,
869 &nsd->rx_length_errors);
870 ns->rx_length_errors = nsd->rx_length_errors;
871
872 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->link_xon_rx, &nsd->link_xon_rx);
875 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
876 pf->stat_offsets_loaded,
877 &osd->link_xon_tx, &nsd->link_xon_tx);
878 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
879 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
880 pf->stat_offsets_loaded,
881 &osd->link_xoff_tx, &nsd->link_xoff_tx);
882
883 for (i = 0; i < 8; i++) {
884 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
885 pf->stat_offsets_loaded,
886 &osd->priority_xon_rx[i],
887 &nsd->priority_xon_rx[i]);
888 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
889 pf->stat_offsets_loaded,
890 &osd->priority_xon_tx[i],
891 &nsd->priority_xon_tx[i]);
892 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
893 pf->stat_offsets_loaded,
894 &osd->priority_xoff_tx[i],
895 &nsd->priority_xoff_tx[i]);
896 i40e_stat_update32(hw,
897 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
898 pf->stat_offsets_loaded,
899 &osd->priority_xon_2_xoff[i],
900 &nsd->priority_xon_2_xoff[i]);
901 }
902
903 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
904 I40E_GLPRT_PRC64L(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->rx_size_64, &nsd->rx_size_64);
907 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
908 I40E_GLPRT_PRC127L(hw->port),
909 pf->stat_offsets_loaded,
910 &osd->rx_size_127, &nsd->rx_size_127);
911 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
912 I40E_GLPRT_PRC255L(hw->port),
913 pf->stat_offsets_loaded,
914 &osd->rx_size_255, &nsd->rx_size_255);
915 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
916 I40E_GLPRT_PRC511L(hw->port),
917 pf->stat_offsets_loaded,
918 &osd->rx_size_511, &nsd->rx_size_511);
919 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
920 I40E_GLPRT_PRC1023L(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->rx_size_1023, &nsd->rx_size_1023);
923 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
924 I40E_GLPRT_PRC1522L(hw->port),
925 pf->stat_offsets_loaded,
926 &osd->rx_size_1522, &nsd->rx_size_1522);
927 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
928 I40E_GLPRT_PRC9522L(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->rx_size_big, &nsd->rx_size_big);
931
932 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
933 I40E_GLPRT_PTC64L(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->tx_size_64, &nsd->tx_size_64);
936 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
937 I40E_GLPRT_PTC127L(hw->port),
938 pf->stat_offsets_loaded,
939 &osd->tx_size_127, &nsd->tx_size_127);
940 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
941 I40E_GLPRT_PTC255L(hw->port),
942 pf->stat_offsets_loaded,
943 &osd->tx_size_255, &nsd->tx_size_255);
944 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
945 I40E_GLPRT_PTC511L(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->tx_size_511, &nsd->tx_size_511);
948 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
949 I40E_GLPRT_PTC1023L(hw->port),
950 pf->stat_offsets_loaded,
951 &osd->tx_size_1023, &nsd->tx_size_1023);
952 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
953 I40E_GLPRT_PTC1522L(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->tx_size_1522, &nsd->tx_size_1522);
956 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
957 I40E_GLPRT_PTC9522L(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->tx_size_big, &nsd->tx_size_big);
960
961 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->rx_undersize, &nsd->rx_undersize);
964 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->rx_fragments, &nsd->rx_fragments);
967 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
968 pf->stat_offsets_loaded,
969 &osd->rx_oversize, &nsd->rx_oversize);
970 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_jabber, &nsd->rx_jabber);
973 }
974
975 pf->stat_offsets_loaded = true;
976}
977
978/**
979 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
980 * @vsi: the VSI to be searched
981 * @macaddr: the MAC address
982 * @vlan: the vlan
983 * @is_vf: make sure its a vf filter, else doesn't matter
984 * @is_netdev: make sure its a netdev filter, else doesn't matter
985 *
986 * Returns ptr to the filter object or NULL
987 **/
988static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
989 u8 *macaddr, s16 vlan,
990 bool is_vf, bool is_netdev)
991{
992 struct i40e_mac_filter *f;
993
994 if (!vsi || !macaddr)
995 return NULL;
996
997 list_for_each_entry(f, &vsi->mac_filter_list, list) {
998 if ((ether_addr_equal(macaddr, f->macaddr)) &&
999 (vlan == f->vlan) &&
1000 (!is_vf || f->is_vf) &&
1001 (!is_netdev || f->is_netdev))
1002 return f;
1003 }
1004 return NULL;
1005}
1006
1007/**
1008 * i40e_find_mac - Find a mac addr in the macvlan filters list
1009 * @vsi: the VSI to be searched
1010 * @macaddr: the MAC address we are searching for
1011 * @is_vf: make sure its a vf filter, else doesn't matter
1012 * @is_netdev: make sure its a netdev filter, else doesn't matter
1013 *
1014 * Returns the first filter with the provided MAC address or NULL if
1015 * MAC address was not found
1016 **/
1017struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1018 bool is_vf, bool is_netdev)
1019{
1020 struct i40e_mac_filter *f;
1021
1022 if (!vsi || !macaddr)
1023 return NULL;
1024
1025 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1026 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1027 (!is_vf || f->is_vf) &&
1028 (!is_netdev || f->is_netdev))
1029 return f;
1030 }
1031 return NULL;
1032}
1033
1034/**
1035 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1036 * @vsi: the VSI to be searched
1037 *
1038 * Returns true if VSI is in vlan mode or false otherwise
1039 **/
1040bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1041{
1042 struct i40e_mac_filter *f;
1043
1044 /* Only -1 for all the filters denotes not in vlan mode
1045 * so we have to go through all the list in order to make sure
1046 */
1047 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1048 if (f->vlan >= 0)
1049 return true;
1050 }
1051
1052 return false;
1053}
1054
1055/**
1056 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1057 * @vsi: the VSI to be searched
1058 * @macaddr: the mac address to be filtered
1059 * @is_vf: true if it is a vf
1060 * @is_netdev: true if it is a netdev
1061 *
1062 * Goes through all the macvlan filters and adds a
1063 * macvlan filter for each unique vlan that already exists
1064 *
1065 * Returns first filter found on success, else NULL
1066 **/
1067struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1068 bool is_vf, bool is_netdev)
1069{
1070 struct i40e_mac_filter *f;
1071
1072 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1073 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1074 is_vf, is_netdev)) {
1075 if (!i40e_add_filter(vsi, macaddr, f->vlan,
1076 is_vf, is_netdev))
1077 return NULL;
1078 }
1079 }
1080
1081 return list_first_entry_or_null(&vsi->mac_filter_list,
1082 struct i40e_mac_filter, list);
1083}
1084
1085/**
1086 * i40e_add_filter - Add a mac/vlan filter to the VSI
1087 * @vsi: the VSI to be searched
1088 * @macaddr: the MAC address
1089 * @vlan: the vlan
1090 * @is_vf: make sure its a vf filter, else doesn't matter
1091 * @is_netdev: make sure its a netdev filter, else doesn't matter
1092 *
1093 * Returns ptr to the filter object or NULL when no memory available.
1094 **/
1095struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1096 u8 *macaddr, s16 vlan,
1097 bool is_vf, bool is_netdev)
1098{
1099 struct i40e_mac_filter *f;
1100
1101 if (!vsi || !macaddr)
1102 return NULL;
1103
1104 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1105 if (!f) {
1106 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1107 if (!f)
1108 goto add_filter_out;
1109
1110 memcpy(f->macaddr, macaddr, ETH_ALEN);
1111 f->vlan = vlan;
1112 f->changed = true;
1113
1114 INIT_LIST_HEAD(&f->list);
1115 list_add(&f->list, &vsi->mac_filter_list);
1116 }
1117
1118 /* increment counter and add a new flag if needed */
1119 if (is_vf) {
1120 if (!f->is_vf) {
1121 f->is_vf = true;
1122 f->counter++;
1123 }
1124 } else if (is_netdev) {
1125 if (!f->is_netdev) {
1126 f->is_netdev = true;
1127 f->counter++;
1128 }
1129 } else {
1130 f->counter++;
1131 }
1132
1133 /* changed tells sync_filters_subtask to
1134 * push the filter down to the firmware
1135 */
1136 if (f->changed) {
1137 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1138 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1139 }
1140
1141add_filter_out:
1142 return f;
1143}
1144
1145/**
1146 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
1150 * @is_vf: make sure it's a vf filter, else doesn't matter
1151 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1152 **/
1153void i40e_del_filter(struct i40e_vsi *vsi,
1154 u8 *macaddr, s16 vlan,
1155 bool is_vf, bool is_netdev)
1156{
1157 struct i40e_mac_filter *f;
1158
1159 if (!vsi || !macaddr)
1160 return;
1161
1162 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1163 if (!f || f->counter == 0)
1164 return;
1165
1166 if (is_vf) {
1167 if (f->is_vf) {
1168 f->is_vf = false;
1169 f->counter--;
1170 }
1171 } else if (is_netdev) {
1172 if (f->is_netdev) {
1173 f->is_netdev = false;
1174 f->counter--;
1175 }
1176 } else {
1177 /* make sure we don't remove a filter in use by vf or netdev */
1178 int min_f = 0;
1179 min_f += (f->is_vf ? 1 : 0);
1180 min_f += (f->is_netdev ? 1 : 0);
1181
1182 if (f->counter > min_f)
1183 f->counter--;
1184 }
1185
1186 /* counter == 0 tells sync_filters_subtask to
1187 * remove the filter from the firmware's list
1188 */
1189 if (f->counter == 0) {
1190 f->changed = true;
1191 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1192 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1193 }
1194}
1195
1196/**
1197 * i40e_set_mac - NDO callback to set mac address
1198 * @netdev: network interface device structure
1199 * @p: pointer to an address structure
1200 *
1201 * Returns 0 on success, negative on failure
1202 **/
1203static int i40e_set_mac(struct net_device *netdev, void *p)
1204{
1205 struct i40e_netdev_priv *np = netdev_priv(netdev);
1206 struct i40e_vsi *vsi = np->vsi;
1207 struct sockaddr *addr = p;
1208 struct i40e_mac_filter *f;
1209
1210 if (!is_valid_ether_addr(addr->sa_data))
1211 return -EADDRNOTAVAIL;
1212
1213 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1214
1215 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1216 return 0;
1217
80f6428f
ASJ		 1218 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1219 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1220 return -EADDRNOTAVAIL;
1221
41c445ff
JB		 1222 if (vsi->type == I40E_VSI_MAIN) {
1223 i40e_status ret;
1224 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1225 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1226 addr->sa_data, NULL);
1227 if (ret) {
1228 netdev_info(netdev,
1229 "Addr change for Main VSI failed: %d\n",
1230 ret);
1231 return -EADDRNOTAVAIL;
1232 }
1233
1234 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1235 }
1236
1237 /* In order to be sure to not drop any packets, add the new address
1238 * then delete the old one.
1239 */
1240 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1241 if (!f)
1242 return -ENOMEM;
1243
1244 i40e_sync_vsi_filters(vsi);
1245 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1246 i40e_sync_vsi_filters(vsi);
1247
1248 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1249
1250 return 0;
1251}
1252
1253/**
1254 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1255 * @vsi: the VSI being setup
1256 * @ctxt: VSI context structure
1257 * @enabled_tc: Enabled TCs bitmap
1258 * @is_add: True if called before Add VSI
1259 *
1260 * Setup VSI queue mapping for enabled traffic classes.
1261 **/
1262static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1263 struct i40e_vsi_context *ctxt,
1264 u8 enabled_tc,
1265 bool is_add)
1266{
1267 struct i40e_pf *pf = vsi->back;
1268 u16 sections = 0;
1269 u8 netdev_tc = 0;
1270 u16 numtc = 0;
1271 u16 qcount;
1272 u8 offset;
1273 u16 qmap;
1274 int i;
1275
1276 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1277 offset = 0;
1278
1279 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1280 /* Find numtc from enabled TC bitmap */
1281 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1282 if (enabled_tc & (1 << i)) /* TC is enabled */
1283 numtc++;
1284 }
1285 if (!numtc) {
1286 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1287 numtc = 1;
1288 }
1289 } else {
1290 /* At least TC0 is enabled in case of non-DCB case */
1291 numtc = 1;
1292 }
1293
1294 vsi->tc_config.numtc = numtc;
1295 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1296
1297 /* Setup queue offset/count for all TCs for given VSI */
1298 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1299 /* See if the given TC is enabled for the given VSI */
1300 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1301 int pow, num_qps;
1302
1303 vsi->tc_config.tc_info[i].qoffset = offset;
1304 switch (vsi->type) {
1305 case I40E_VSI_MAIN:
1306 if (i == 0)
1307 qcount = pf->rss_size;
1308 else
1309 qcount = pf->num_tc_qps;
1310 vsi->tc_config.tc_info[i].qcount = qcount;
1311 break;
1312 case I40E_VSI_FDIR:
1313 case I40E_VSI_SRIOV:
1314 case I40E_VSI_VMDQ2:
1315 default:
1316 qcount = vsi->alloc_queue_pairs;
1317 vsi->tc_config.tc_info[i].qcount = qcount;
1318 WARN_ON(i != 0);
1319 break;
1320 }
1321
1322 /* find the power-of-2 of the number of queue pairs */
1323 num_qps = vsi->tc_config.tc_info[i].qcount;
1324 pow = 0;
1325 while (num_qps &&
1326 ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
1327 pow++;
1328 num_qps >>= 1;
1329 }
1330
1331 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1332 qmap =
1333 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1334 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1335
1336 offset += vsi->tc_config.tc_info[i].qcount;
1337 } else {
1338 /* TC is not enabled so set the offset to
1339 * default queue and allocate one queue
1340 * for the given TC.
1341 */
1342 vsi->tc_config.tc_info[i].qoffset = 0;
1343 vsi->tc_config.tc_info[i].qcount = 1;
1344 vsi->tc_config.tc_info[i].netdev_tc = 0;
1345
1346 qmap = 0;
1347 }
1348 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1349 }
1350
1351 /* Set actual Tx/Rx queue pairs */
1352 vsi->num_queue_pairs = offset;
1353
1354 /* Scheduler section valid can only be set for ADD VSI */
1355 if (is_add) {
1356 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1357
1358 ctxt->info.up_enable_bits = enabled_tc;
1359 }
1360 if (vsi->type == I40E_VSI_SRIOV) {
1361 ctxt->info.mapping_flags |=
1362 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1363 for (i = 0; i < vsi->num_queue_pairs; i++)
1364 ctxt->info.queue_mapping[i] =
1365 cpu_to_le16(vsi->base_queue + i);
1366 } else {
1367 ctxt->info.mapping_flags |=
1368 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1369 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1370 }
1371 ctxt->info.valid_sections |= cpu_to_le16(sections);
1372}
1373
1374/**
1375 * i40e_set_rx_mode - NDO callback to set the netdev filters
1376 * @netdev: network interface device structure
1377 **/
1378static void i40e_set_rx_mode(struct net_device *netdev)
1379{
1380 struct i40e_netdev_priv *np = netdev_priv(netdev);
1381 struct i40e_mac_filter *f, *ftmp;
1382 struct i40e_vsi *vsi = np->vsi;
1383 struct netdev_hw_addr *uca;
1384 struct netdev_hw_addr *mca;
1385 struct netdev_hw_addr *ha;
1386
1387 /* add addr if not already in the filter list */
1388 netdev_for_each_uc_addr(uca, netdev) {
1389 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1390 if (i40e_is_vsi_in_vlan(vsi))
1391 i40e_put_mac_in_vlan(vsi, uca->addr,
1392 false, true);
1393 else
1394 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1395 false, true);
1396 }
1397 }
1398
1399 netdev_for_each_mc_addr(mca, netdev) {
1400 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1401 if (i40e_is_vsi_in_vlan(vsi))
1402 i40e_put_mac_in_vlan(vsi, mca->addr,
1403 false, true);
1404 else
1405 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1406 false, true);
1407 }
1408 }
1409
1410 /* remove filter if not in netdev list */
1411 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1412 bool found = false;
1413
1414 if (!f->is_netdev)
1415 continue;
1416
1417 if (is_multicast_ether_addr(f->macaddr)) {
1418 netdev_for_each_mc_addr(mca, netdev) {
1419 if (ether_addr_equal(mca->addr, f->macaddr)) {
1420 found = true;
1421 break;
1422 }
1423 }
1424 } else {
1425 netdev_for_each_uc_addr(uca, netdev) {
1426 if (ether_addr_equal(uca->addr, f->macaddr)) {
1427 found = true;
1428 break;
1429 }
1430 }
1431
1432 for_each_dev_addr(netdev, ha) {
1433 if (ether_addr_equal(ha->addr, f->macaddr)) {
1434 found = true;
1435 break;
1436 }
1437 }
1438 }
1439 if (!found)
1440 i40e_del_filter(
1441 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1442 }
1443
1444 /* check for other flag changes */
1445 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1446 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1447 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1448 }
1449}
1450
1451/**
1452 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1453 * @vsi: ptr to the VSI
1454 *
1455 * Push any outstanding VSI filter changes through the AdminQ.
1456 *
1457 * Returns 0 or error value
1458 **/
1459int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1460{
1461 struct i40e_mac_filter *f, *ftmp;
1462 bool promisc_forced_on = false;
1463 bool add_happened = false;
1464 int filter_list_len = 0;
1465 u32 changed_flags = 0;
dcae29be 1466 i40e_status aq_ret = 0;
41c445ff
JB		 1467 struct i40e_pf *pf;
1468 int num_add = 0;
1469 int num_del = 0;
1470 u16 cmd_flags;
1471
1472 /* empty array typed pointers, kcalloc later */
1473 struct i40e_aqc_add_macvlan_element_data *add_list;
1474 struct i40e_aqc_remove_macvlan_element_data *del_list;
1475
1476 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1477 usleep_range(1000, 2000);
1478 pf = vsi->back;
1479
1480 if (vsi->netdev) {
1481 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1482 vsi->current_netdev_flags = vsi->netdev->flags;
1483 }
1484
1485 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1486 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1487
1488 filter_list_len = pf->hw.aq.asq_buf_size /
1489 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1490 del_list = kcalloc(filter_list_len,
1491 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1492 GFP_KERNEL);
1493 if (!del_list)
1494 return -ENOMEM;
1495
1496 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1497 if (!f->changed)
1498 continue;
1499
1500 if (f->counter != 0)
1501 continue;
1502 f->changed = false;
1503 cmd_flags = 0;
1504
1505 /* add to delete list */
1506 memcpy(del_list[num_del].mac_addr,
1507 f->macaddr, ETH_ALEN);
1508 del_list[num_del].vlan_tag =
1509 cpu_to_le16((u16)(f->vlan ==
1510 I40E_VLAN_ANY ? 0 : f->vlan));
1511
1512 /* vlan0 as wild card to allow packets from all vlans */
1513 if (f->vlan == I40E_VLAN_ANY ||
1514 (vsi->netdev && !(vsi->netdev->features &
1515 NETIF_F_HW_VLAN_CTAG_FILTER)))
1516 cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1517 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1518 del_list[num_del].flags = cmd_flags;
1519 num_del++;
1520
1521 /* unlink from filter list */
1522 list_del(&f->list);
1523 kfree(f);
1524
1525 /* flush a full buffer */
1526 if (num_del == filter_list_len) {
dcae29be 1527 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1528 vsi->seid, del_list, num_del,
1529 NULL);
1530 num_del = 0;
1531 memset(del_list, 0, sizeof(*del_list));
1532
dcae29be 1533 if (aq_ret)
41c445ff
JB		 1534 dev_info(&pf->pdev->dev,
1535 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1536 aq_ret,
41c445ff
JB		 1537 pf->hw.aq.asq_last_status);
1538 }
1539 }
1540 if (num_del) {
dcae29be 1541 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1542 del_list, num_del, NULL);
1543 num_del = 0;
1544
dcae29be 1545 if (aq_ret)
41c445ff
JB		 1546 dev_info(&pf->pdev->dev,
1547 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1548 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1549 }
1550
1551 kfree(del_list);
1552 del_list = NULL;
1553
1554 /* do all the adds now */
1555 filter_list_len = pf->hw.aq.asq_buf_size /
1556 sizeof(struct i40e_aqc_add_macvlan_element_data),
1557 add_list = kcalloc(filter_list_len,
1558 sizeof(struct i40e_aqc_add_macvlan_element_data),
1559 GFP_KERNEL);
1560 if (!add_list)
1561 return -ENOMEM;
1562
1563 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1564 if (!f->changed)
1565 continue;
1566
1567 if (f->counter == 0)
1568 continue;
1569 f->changed = false;
1570 add_happened = true;
1571 cmd_flags = 0;
1572
1573 /* add to add array */
1574 memcpy(add_list[num_add].mac_addr,
1575 f->macaddr, ETH_ALEN);
1576 add_list[num_add].vlan_tag =
1577 cpu_to_le16(
1578 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1579 add_list[num_add].queue_number = 0;
1580
1581 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
1582
1583 /* vlan0 as wild card to allow packets from all vlans */
1584 if (f->vlan == I40E_VLAN_ANY || (vsi->netdev &&
1585 !(vsi->netdev->features &
1586 NETIF_F_HW_VLAN_CTAG_FILTER)))
1587 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
1588 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1589 num_add++;
1590
1591 /* flush a full buffer */
1592 if (num_add == filter_list_len) {
dcae29be
JB		 1593 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1594 add_list, num_add,
1595 NULL);
41c445ff
JB		 1596 num_add = 0;
1597
dcae29be 1598 if (aq_ret)
41c445ff
JB		 1599 break;
1600 memset(add_list, 0, sizeof(*add_list));
1601 }
1602 }
1603 if (num_add) {
dcae29be
JB		 1604 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1605 add_list, num_add, NULL);
41c445ff
JB		 1606 num_add = 0;
1607 }
1608 kfree(add_list);
1609 add_list = NULL;
1610
dcae29be 1611 if (add_happened && (!aq_ret)) {
41c445ff 1612 /* do nothing */;
dcae29be 1613 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1614 dev_info(&pf->pdev->dev,
1615 "add filter failed, err %d, aq_err %d\n",
dcae29be 1616 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1617 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1618 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1619 &vsi->state)) {
1620 promisc_forced_on = true;
1621 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1622 &vsi->state);
1623 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1624 }
1625 }
1626 }
1627
1628 /* check for changes in promiscuous modes */
1629 if (changed_flags & IFF_ALLMULTI) {
1630 bool cur_multipromisc;
1631 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1632 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1633 vsi->seid,
1634 cur_multipromisc,
1635 NULL);
1636 if (aq_ret)
41c445ff
JB		 1637 dev_info(&pf->pdev->dev,
1638 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1639 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1640 }
1641 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1642 bool cur_promisc;
1643 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1644 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1645 &vsi->state));
dcae29be
JB		 1646 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1647 vsi->seid,
1648 cur_promisc, NULL);
1649 if (aq_ret)
41c445ff
JB		 1650 dev_info(&pf->pdev->dev,
1651 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1652 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1653 }
1654
1655 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1656 return 0;
1657}
1658
1659/**
1660 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1661 * @pf: board private structure
1662 **/
1663static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1664{
1665 int v;
1666
1667 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1668 return;
1669 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1670
1671 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
1672 if (pf->vsi[v] &&
1673 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1674 i40e_sync_vsi_filters(pf->vsi[v]);
1675 }
1676}
1677
1678/**
1679 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1680 * @netdev: network interface device structure
1681 * @new_mtu: new value for maximum frame size
1682 *
1683 * Returns 0 on success, negative on failure
1684 **/
1685static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1686{
1687 struct i40e_netdev_priv *np = netdev_priv(netdev);
1688 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1689 struct i40e_vsi *vsi = np->vsi;
1690
1691 /* MTU < 68 is an error and causes problems on some kernels */
1692 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1693 return -EINVAL;
1694
1695 netdev_info(netdev, "changing MTU from %d to %d\n",
1696 netdev->mtu, new_mtu);
1697 netdev->mtu = new_mtu;
1698 if (netif_running(netdev))
1699 i40e_vsi_reinit_locked(vsi);
1700
1701 return 0;
1702}
1703
1704/**
1705 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1706 * @vsi: the vsi being adjusted
1707 **/
1708void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1709{
1710 struct i40e_vsi_context ctxt;
1711 i40e_status ret;
1712
1713 if ((vsi->info.valid_sections &
1714 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1715 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1716 return; /* already enabled */
1717
1718 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1719 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1720 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1721
1722 ctxt.seid = vsi->seid;
1723 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1724 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1725 if (ret) {
1726 dev_info(&vsi->back->pdev->dev,
1727 "%s: update vsi failed, aq_err=%d\n",
1728 __func__, vsi->back->hw.aq.asq_last_status);
1729 }
1730}
1731
1732/**
1733 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1734 * @vsi: the vsi being adjusted
1735 **/
1736void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1737{
1738 struct i40e_vsi_context ctxt;
1739 i40e_status ret;
1740
1741 if ((vsi->info.valid_sections &
1742 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1743 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1744 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1745 return; /* already disabled */
1746
1747 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1748 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1749 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1750
1751 ctxt.seid = vsi->seid;
1752 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1753 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1754 if (ret) {
1755 dev_info(&vsi->back->pdev->dev,
1756 "%s: update vsi failed, aq_err=%d\n",
1757 __func__, vsi->back->hw.aq.asq_last_status);
1758 }
1759}
1760
1761/**
1762 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1763 * @netdev: network interface to be adjusted
1764 * @features: netdev features to test if VLAN offload is enabled or not
1765 **/
1766static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1767{
1768 struct i40e_netdev_priv *np = netdev_priv(netdev);
1769 struct i40e_vsi *vsi = np->vsi;
1770
1771 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1772 i40e_vlan_stripping_enable(vsi);
1773 else
1774 i40e_vlan_stripping_disable(vsi);
1775}
1776
1777/**
1778 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1779 * @vsi: the vsi being configured
1780 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1781 **/
1782int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1783{
1784 struct i40e_mac_filter *f, *add_f;
1785 bool is_netdev, is_vf;
41c445ff
JB		 1786
1787 is_vf = (vsi->type == I40E_VSI_SRIOV);
1788 is_netdev = !!(vsi->netdev);
1789
1790 if (is_netdev) {
1791 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1792 is_vf, is_netdev);
1793 if (!add_f) {
1794 dev_info(&vsi->back->pdev->dev,
1795 "Could not add vlan filter %d for %pM\n",
1796 vid, vsi->netdev->dev_addr);
1797 return -ENOMEM;
1798 }
1799 }
1800
1801 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1802 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1803 if (!add_f) {
1804 dev_info(&vsi->back->pdev->dev,
1805 "Could not add vlan filter %d for %pM\n",
1806 vid, f->macaddr);
1807 return -ENOMEM;
1808 }
1809 }
1810
41c445ff
JB		 1811 /* Now if we add a vlan tag, make sure to check if it is the first
1812 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1813 * with 0, so we now accept untagged and specified tagged traffic
1814 * (and not any taged and untagged)
1815 */
1816 if (vid > 0) {
1817 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1818 I40E_VLAN_ANY,
1819 is_vf, is_netdev)) {
1820 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1821 I40E_VLAN_ANY, is_vf, is_netdev);
1822 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1823 is_vf, is_netdev);
1824 if (!add_f) {
1825 dev_info(&vsi->back->pdev->dev,
1826 "Could not add filter 0 for %pM\n",
1827 vsi->netdev->dev_addr);
1828 return -ENOMEM;
1829 }
1830 }
1831
1832 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1833 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1834 is_vf, is_netdev)) {
1835 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1836 is_vf, is_netdev);
1837 add_f = i40e_add_filter(vsi, f->macaddr,
1838 0, is_vf, is_netdev);
1839 if (!add_f) {
1840 dev_info(&vsi->back->pdev->dev,
1841 "Could not add filter 0 for %pM\n",
1842 f->macaddr);
1843 return -ENOMEM;
1844 }
1845 }
1846 }
41c445ff
JB		 1847 }
1848
80f6428f
ASJ		 1849 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1850 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1851 return 0;
1852
1853 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1854}
1855
1856/**
1857 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1858 * @vsi: the vsi being configured
1859 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1860 *
1861 * Return: 0 on success or negative otherwise
41c445ff
JB		 1862 **/
1863int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1864{
1865 struct net_device *netdev = vsi->netdev;
1866 struct i40e_mac_filter *f, *add_f;
1867 bool is_vf, is_netdev;
1868 int filter_count = 0;
41c445ff
JB		 1869
1870 is_vf = (vsi->type == I40E_VSI_SRIOV);
1871 is_netdev = !!(netdev);
1872
1873 if (is_netdev)
1874 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1875
1876 list_for_each_entry(f, &vsi->mac_filter_list, list)
1877 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1878
41c445ff
JB		 1879 /* go through all the filters for this VSI and if there is only
1880 * vid == 0 it means there are no other filters, so vid 0 must
1881 * be replaced with -1. This signifies that we should from now
1882 * on accept any traffic (with any tag present, or untagged)
1883 */
1884 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1885 if (is_netdev) {
1886 if (f->vlan &&
1887 ether_addr_equal(netdev->dev_addr, f->macaddr))
1888 filter_count++;
1889 }
1890
1891 if (f->vlan)
1892 filter_count++;
1893 }
1894
1895 if (!filter_count && is_netdev) {
1896 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1897 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1898 is_vf, is_netdev);
1899 if (!f) {
1900 dev_info(&vsi->back->pdev->dev,
1901 "Could not add filter %d for %pM\n",
1902 I40E_VLAN_ANY, netdev->dev_addr);
1903 return -ENOMEM;
1904 }
1905 }
1906
1907 if (!filter_count) {
1908 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1909 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
1910 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1911 is_vf, is_netdev);
1912 if (!add_f) {
1913 dev_info(&vsi->back->pdev->dev,
1914 "Could not add filter %d for %pM\n",
1915 I40E_VLAN_ANY, f->macaddr);
1916 return -ENOMEM;
1917 }
1918 }
1919 }
1920
80f6428f
ASJ		 1921 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1922 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1923 return 0;
1924
41c445ff
JB		 1925 return i40e_sync_vsi_filters(vsi);
1926}
1927
1928/**
1929 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
1930 * @netdev: network interface to be adjusted
1931 * @vid: vlan id to be added
078b5876
JB		 1932 *
1933 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1934 **/
1935static int i40e_vlan_rx_add_vid(struct net_device *netdev,
1936 __always_unused __be16 proto, u16 vid)
1937{
1938 struct i40e_netdev_priv *np = netdev_priv(netdev);
1939 struct i40e_vsi *vsi = np->vsi;
078b5876 1940 int ret = 0;
41c445ff
JB		 1941
1942 if (vid > 4095)
078b5876
JB		 1943 return -EINVAL;
1944
1945 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 1946
41c445ff
JB		 1947 /* If the network stack called us with vid = 0, we should
1948 * indicate to i40e_vsi_add_vlan() that we want to receive
1949 * any traffic (i.e. with any vlan tag, or untagged)
1950 */
1951 ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
1952
078b5876
JB		 1953 if (!ret && (vid < VLAN_N_VID))
1954 set_bit(vid, vsi->active_vlans);
41c445ff 1955
078b5876 1956 return ret;
41c445ff
JB		 1957}
1958
1959/**
1960 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
1961 * @netdev: network interface to be adjusted
1962 * @vid: vlan id to be removed
078b5876
JB		 1963 *
1964 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 1965 **/
1966static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
1967 __always_unused __be16 proto, u16 vid)
1968{
1969 struct i40e_netdev_priv *np = netdev_priv(netdev);
1970 struct i40e_vsi *vsi = np->vsi;
1971
078b5876
JB		 1972 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
1973
41c445ff
JB		 1974 /* return code is ignored as there is nothing a user
1975 * can do about failure to remove and a log message was
078b5876 1976 * already printed from the other function
41c445ff
JB		 1977 */
1978 i40e_vsi_kill_vlan(vsi, vid);
1979
1980 clear_bit(vid, vsi->active_vlans);
078b5876 1981
41c445ff
JB		 1982 return 0;
1983}
1984
1985/**
1986 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
1987 * @vsi: the vsi being brought back up
1988 **/
1989static void i40e_restore_vlan(struct i40e_vsi *vsi)
1990{
1991 u16 vid;
1992
1993 if (!vsi->netdev)
1994 return;
1995
1996 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
1997
1998 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
1999 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2000 vid);
2001}
2002
2003/**
2004 * i40e_vsi_add_pvid - Add pvid for the VSI
2005 * @vsi: the vsi being adjusted
2006 * @vid: the vlan id to set as a PVID
2007 **/
dcae29be 2008int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2009{
2010 struct i40e_vsi_context ctxt;
dcae29be 2011 i40e_status aq_ret;
41c445ff
JB		 2012
2013 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2014 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2015 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2016 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2017 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2018
2019 ctxt.seid = vsi->seid;
2020 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2021 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2022 if (aq_ret) {
41c445ff
JB		 2023 dev_info(&vsi->back->pdev->dev,
2024 "%s: update vsi failed, aq_err=%d\n",
2025 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2026 return -ENOENT;
41c445ff
JB		 2027 }
2028
dcae29be 2029 return 0;
41c445ff
JB		 2030}
2031
2032/**
2033 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2034 * @vsi: the vsi being adjusted
2035 *
2036 * Just use the vlan_rx_register() service to put it back to normal
2037 **/
2038void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2039{
6c12fcbf
GR		 2040 i40e_vlan_stripping_disable(vsi);
2041
41c445ff 2042 vsi->info.pvid = 0;
41c445ff
JB		 2043}
2044
2045/**
2046 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2047 * @vsi: ptr to the VSI
2048 *
2049 * If this function returns with an error, then it's possible one or
2050 * more of the rings is populated (while the rest are not). It is the
2051 * callers duty to clean those orphaned rings.
2052 *
2053 * Return 0 on success, negative on failure
2054 **/
2055static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2056{
2057 int i, err = 0;
2058
2059 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2060 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2061
2062 return err;
2063}
2064
2065/**
2066 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2067 * @vsi: ptr to the VSI
2068 *
2069 * Free VSI's transmit software resources
2070 **/
2071static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2072{
2073 int i;
2074
2075 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2076 if (vsi->tx_rings[i]->desc)
2077 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2078}
2079
2080/**
2081 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2082 * @vsi: ptr to the VSI
2083 *
2084 * If this function returns with an error, then it's possible one or
2085 * more of the rings is populated (while the rest are not). It is the
2086 * callers duty to clean those orphaned rings.
2087 *
2088 * Return 0 on success, negative on failure
2089 **/
2090static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2091{
2092 int i, err = 0;
2093
2094 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2095 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2096 return err;
2097}
2098
2099/**
2100 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2101 * @vsi: ptr to the VSI
2102 *
2103 * Free all receive software resources
2104 **/
2105static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2106{
2107 int i;
2108
2109 for (i = 0; i < vsi->num_queue_pairs; i++)
9f65e15b
AD		 2110 if (vsi->rx_rings[i]->desc)
2111 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2112}
2113
2114/**
2115 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2116 * @ring: The Tx ring to configure
2117 *
2118 * Configure the Tx descriptor ring in the HMC context.
2119 **/
2120static int i40e_configure_tx_ring(struct i40e_ring *ring)
2121{
2122 struct i40e_vsi *vsi = ring->vsi;
2123 u16 pf_q = vsi->base_queue + ring->queue_index;
2124 struct i40e_hw *hw = &vsi->back->hw;
2125 struct i40e_hmc_obj_txq tx_ctx;
2126 i40e_status err = 0;
2127 u32 qtx_ctl = 0;
2128
2129 /* some ATR related tx ring init */
2130 if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
2131 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2132 ring->atr_count = 0;
2133 } else {
2134 ring->atr_sample_rate = 0;
2135 }
2136
2137 /* initialize XPS */
2138 if (ring->q_vector && ring->netdev &&
2139 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2140 netif_set_xps_queue(ring->netdev,
2141 &ring->q_vector->affinity_mask,
2142 ring->queue_index);
2143
2144 /* clear the context structure first */
2145 memset(&tx_ctx, 0, sizeof(tx_ctx));
2146
2147 tx_ctx.new_context = 1;
2148 tx_ctx.base = (ring->dma / 128);
2149 tx_ctx.qlen = ring->count;
2150 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
2151 I40E_FLAG_FDIR_ATR_ENABLED));
2152
2153 /* As part of VSI creation/update, FW allocates certain
2154 * Tx arbitration queue sets for each TC enabled for
2155 * the VSI. The FW returns the handles to these queue
2156 * sets as part of the response buffer to Add VSI,
2157 * Update VSI, etc. AQ commands. It is expected that
2158 * these queue set handles be associated with the Tx
2159 * queues by the driver as part of the TX queue context
2160 * initialization. This has to be done regardless of
2161 * DCB as by default everything is mapped to TC0.
2162 */
2163 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2164 tx_ctx.rdylist_act = 0;
2165
2166 /* clear the context in the HMC */
2167 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2168 if (err) {
2169 dev_info(&vsi->back->pdev->dev,
2170 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2171 ring->queue_index, pf_q, err);
2172 return -ENOMEM;
2173 }
2174
2175 /* set the context in the HMC */
2176 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2177 if (err) {
2178 dev_info(&vsi->back->pdev->dev,
2179 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2180 ring->queue_index, pf_q, err);
2181 return -ENOMEM;
2182 }
2183
2184 /* Now associate this queue with this PCI function */
2185 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2186 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2187 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2188 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2189 i40e_flush(hw);
2190
2191 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2192
2193 /* cache tail off for easier writes later */
2194 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2195
2196 return 0;
2197}
2198
2199/**
2200 * i40e_configure_rx_ring - Configure a receive ring context
2201 * @ring: The Rx ring to configure
2202 *
2203 * Configure the Rx descriptor ring in the HMC context.
2204 **/
2205static int i40e_configure_rx_ring(struct i40e_ring *ring)
2206{
2207 struct i40e_vsi *vsi = ring->vsi;
2208 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2209 u16 pf_q = vsi->base_queue + ring->queue_index;
2210 struct i40e_hw *hw = &vsi->back->hw;
2211 struct i40e_hmc_obj_rxq rx_ctx;
2212 i40e_status err = 0;
2213
2214 ring->state = 0;
2215
2216 /* clear the context structure first */
2217 memset(&rx_ctx, 0, sizeof(rx_ctx));
2218
2219 ring->rx_buf_len = vsi->rx_buf_len;
2220 ring->rx_hdr_len = vsi->rx_hdr_len;
2221
2222 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2223 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2224
2225 rx_ctx.base = (ring->dma / 128);
2226 rx_ctx.qlen = ring->count;
2227
2228 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2229 set_ring_16byte_desc_enabled(ring);
2230 rx_ctx.dsize = 0;
2231 } else {
2232 rx_ctx.dsize = 1;
2233 }
2234
2235 rx_ctx.dtype = vsi->dtype;
2236 if (vsi->dtype) {
2237 set_ring_ps_enabled(ring);
2238 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2239 I40E_RX_SPLIT_IP |
2240 I40E_RX_SPLIT_TCP_UDP |
2241 I40E_RX_SPLIT_SCTP;
2242 } else {
2243 rx_ctx.hsplit_0 = 0;
2244 }
2245
2246 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2247 (chain_len * ring->rx_buf_len));
2248 rx_ctx.tphrdesc_ena = 1;
2249 rx_ctx.tphwdesc_ena = 1;
2250 rx_ctx.tphdata_ena = 1;
2251 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2252 if (hw->revision_id == 0)
2253 rx_ctx.lrxqthresh = 0;
2254 else
2255 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2256 rx_ctx.crcstrip = 1;
2257 rx_ctx.l2tsel = 1;
2258 rx_ctx.showiv = 1;
2259
2260 /* clear the context in the HMC */
2261 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2262 if (err) {
2263 dev_info(&vsi->back->pdev->dev,
2264 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2265 ring->queue_index, pf_q, err);
2266 return -ENOMEM;
2267 }
2268
2269 /* set the context in the HMC */
2270 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2271 if (err) {
2272 dev_info(&vsi->back->pdev->dev,
2273 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2274 ring->queue_index, pf_q, err);
2275 return -ENOMEM;
2276 }
2277
2278 /* cache tail for quicker writes, and clear the reg before use */
2279 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2280 writel(0, ring->tail);
2281
2282 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2283
2284 return 0;
2285}
2286
2287/**
2288 * i40e_vsi_configure_tx - Configure the VSI for Tx
2289 * @vsi: VSI structure describing this set of rings and resources
2290 *
2291 * Configure the Tx VSI for operation.
2292 **/
2293static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2294{
2295 int err = 0;
2296 u16 i;
2297
9f65e15b
AD		 2298 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2299 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2300
2301 return err;
2302}
2303
2304/**
2305 * i40e_vsi_configure_rx - Configure the VSI for Rx
2306 * @vsi: the VSI being configured
2307 *
2308 * Configure the Rx VSI for operation.
2309 **/
2310static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2311{
2312 int err = 0;
2313 u16 i;
2314
2315 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2316 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2317 + ETH_FCS_LEN + VLAN_HLEN;
2318 else
2319 vsi->max_frame = I40E_RXBUFFER_2048;
2320
2321 /* figure out correct receive buffer length */
2322 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2323 I40E_FLAG_RX_PS_ENABLED)) {
2324 case I40E_FLAG_RX_1BUF_ENABLED:
2325 vsi->rx_hdr_len = 0;
2326 vsi->rx_buf_len = vsi->max_frame;
2327 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2328 break;
2329 case I40E_FLAG_RX_PS_ENABLED:
2330 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2331 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2332 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2333 break;
2334 default:
2335 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2336 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2337 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2338 break;
2339 }
2340
2341 /* round up for the chip's needs */
2342 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2343 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2344 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2345 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2346
2347 /* set up individual rings */
2348 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2349 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2350
2351 return err;
2352}
2353
2354/**
2355 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2356 * @vsi: ptr to the VSI
2357 **/
2358static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2359{
2360 u16 qoffset, qcount;
2361 int i, n;
2362
2363 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2364 return;
2365
2366 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2367 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2368 continue;
2369
2370 qoffset = vsi->tc_config.tc_info[n].qoffset;
2371 qcount = vsi->tc_config.tc_info[n].qcount;
2372 for (i = qoffset; i < (qoffset + qcount); i++) {
9f65e15b
AD		 2373 struct i40e_ring *rx_ring = vsi->rx_rings[i];
2374 struct i40e_ring *tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2375 rx_ring->dcb_tc = n;
2376 tx_ring->dcb_tc = n;
2377 }
2378 }
2379}
2380
2381/**
2382 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2383 * @vsi: ptr to the VSI
2384 **/
2385static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2386{
2387 if (vsi->netdev)
2388 i40e_set_rx_mode(vsi->netdev);
2389}
2390
2391/**
2392 * i40e_vsi_configure - Set up the VSI for action
2393 * @vsi: the VSI being configured
2394 **/
2395static int i40e_vsi_configure(struct i40e_vsi *vsi)
2396{
2397 int err;
2398
2399 i40e_set_vsi_rx_mode(vsi);
2400 i40e_restore_vlan(vsi);
2401 i40e_vsi_config_dcb_rings(vsi);
2402 err = i40e_vsi_configure_tx(vsi);
2403 if (!err)
2404 err = i40e_vsi_configure_rx(vsi);
2405
2406 return err;
2407}
2408
2409/**
2410 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2411 * @vsi: the VSI being configured
2412 **/
2413static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2414{
2415 struct i40e_pf *pf = vsi->back;
2416 struct i40e_q_vector *q_vector;
2417 struct i40e_hw *hw = &pf->hw;
2418 u16 vector;
2419 int i, q;
2420 u32 val;
2421 u32 qp;
2422
2423 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2424 * and PFINT_LNKLSTn registers, e.g.:
2425 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2426 */
2427 qp = vsi->base_queue;
2428 vector = vsi->base_vector;
493fb300
AD		 2429 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2430 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2431 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2432 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2433 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2434 q_vector->rx.itr);
2435 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2436 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2437 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2438 q_vector->tx.itr);
2439
2440 /* Linked list for the queuepairs assigned to this vector */
2441 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2442 for (q = 0; q < q_vector->num_ringpairs; q++) {
2443 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2444 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2445 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2446 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2447 (I40E_QUEUE_TYPE_TX
2448 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2449
2450 wr32(hw, I40E_QINT_RQCTL(qp), val);
2451
2452 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2453 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2454 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2455 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2456 (I40E_QUEUE_TYPE_RX
2457 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2458
2459 /* Terminate the linked list */
2460 if (q == (q_vector->num_ringpairs - 1))
2461 val |= (I40E_QUEUE_END_OF_LIST
2462 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2463
2464 wr32(hw, I40E_QINT_TQCTL(qp), val);
2465 qp++;
2466 }
2467 }
2468
2469 i40e_flush(hw);
2470}
2471
2472/**
2473 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2474 * @hw: ptr to the hardware info
2475 **/
2476static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2477{
2478 u32 val;
2479
2480 /* clear things first */
2481 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2482 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2483
2484 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2485 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2486 I40E_PFINT_ICR0_ENA_GRST_MASK |
2487 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2488 I40E_PFINT_ICR0_ENA_GPIO_MASK |
2489 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
2490 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2491 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2492 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2493
2494 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2495
2496 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2497 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2498 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2499
2500 /* OTHER_ITR_IDX = 0 */
2501 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2502}
2503
2504/**
2505 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2506 * @vsi: the VSI being configured
2507 **/
2508static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2509{
493fb300 2510 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2511 struct i40e_pf *pf = vsi->back;
2512 struct i40e_hw *hw = &pf->hw;
2513 u32 val;
2514
2515 /* set the ITR configuration */
2516 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2517 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2518 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2519 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2520 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2521 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2522
2523 i40e_enable_misc_int_causes(hw);
2524
2525 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2526 wr32(hw, I40E_PFINT_LNKLST0, 0);
2527
2528 /* Associate the queue pair to the vector and enable the q int */
2529 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2530 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2531 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2532
2533 wr32(hw, I40E_QINT_RQCTL(0), val);
2534
2535 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2536 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2537 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2538
2539 wr32(hw, I40E_QINT_TQCTL(0), val);
2540 i40e_flush(hw);
2541}
2542
2ef28cfb
MW		 2543/**
2544 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2545 * @pf: board private structure
2546 **/
2547void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2548{
2549 struct i40e_hw *hw = &pf->hw;
2550
2551 wr32(hw, I40E_PFINT_DYN_CTL0,
2552 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2553 i40e_flush(hw);
2554}
2555
41c445ff
JB		 2556/**
2557 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2558 * @pf: board private structure
2559 **/
116a57d4 2560void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2561{
2562 struct i40e_hw *hw = &pf->hw;
2563 u32 val;
2564
2565 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2566 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2567 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2568
2569 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2570 i40e_flush(hw);
2571}
2572
2573/**
2574 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2575 * @vsi: pointer to a vsi
2576 * @vector: enable a particular Hw Interrupt vector
2577 **/
2578void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2579{
2580 struct i40e_pf *pf = vsi->back;
2581 struct i40e_hw *hw = &pf->hw;
2582 u32 val;
2583
2584 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2585 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2586 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2587 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2588 /* skip the flush */
41c445ff
JB		 2589}
2590
2591/**
2592 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2593 * @irq: interrupt number
2594 * @data: pointer to a q_vector
2595 **/
2596static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2597{
2598 struct i40e_q_vector *q_vector = data;
2599
cd0b6fa6 2600 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2601 return IRQ_HANDLED;
2602
2603 napi_schedule(&q_vector->napi);
2604
2605 return IRQ_HANDLED;
2606}
2607
2608/**
2609 * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
2610 * @irq: interrupt number
2611 * @data: pointer to a q_vector
2612 **/
2613static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
2614{
2615 struct i40e_q_vector *q_vector = data;
2616
cd0b6fa6 2617 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2618 return IRQ_HANDLED;
2619
2620 pr_info("fdir ring cleaning needed\n");
2621
2622 return IRQ_HANDLED;
2623}
2624
2625/**
2626 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2627 * @vsi: the VSI being configured
2628 * @basename: name for the vector
2629 *
2630 * Allocates MSI-X vectors and requests interrupts from the kernel.
2631 **/
2632static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2633{
2634 int q_vectors = vsi->num_q_vectors;
2635 struct i40e_pf *pf = vsi->back;
2636 int base = vsi->base_vector;
2637 int rx_int_idx = 0;
2638 int tx_int_idx = 0;
2639 int vector, err;
2640
2641 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2642 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2643
cd0b6fa6 2644 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2645 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2646 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2647 tx_int_idx++;
cd0b6fa6 2648 } else if (q_vector->rx.ring) {
41c445ff
JB		 2649 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2650 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2651 } else if (q_vector->tx.ring) {
41c445ff
JB		 2652 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2653 "%s-%s-%d", basename, "tx", tx_int_idx++);
2654 } else {
2655 /* skip this unused q_vector */
2656 continue;
2657 }
2658 err = request_irq(pf->msix_entries[base + vector].vector,
2659 vsi->irq_handler,
2660 0,
2661 q_vector->name,
2662 q_vector);
2663 if (err) {
2664 dev_info(&pf->pdev->dev,
2665 "%s: request_irq failed, error: %d\n",
2666 __func__, err);
2667 goto free_queue_irqs;
2668 }
2669 /* assign the mask for this irq */
2670 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2671 &q_vector->affinity_mask);
2672 }
2673
2674 return 0;
2675
2676free_queue_irqs:
2677 while (vector) {
2678 vector--;
2679 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2680 NULL);
2681 free_irq(pf->msix_entries[base + vector].vector,
2682 &(vsi->q_vectors[vector]));
2683 }
2684 return err;
2685}
2686
2687/**
2688 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2689 * @vsi: the VSI being un-configured
2690 **/
2691static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2692{
2693 struct i40e_pf *pf = vsi->back;
2694 struct i40e_hw *hw = &pf->hw;
2695 int base = vsi->base_vector;
2696 int i;
2697
2698 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2699 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2700 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2701 }
2702
2703 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2704 for (i = vsi->base_vector;
2705 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2706 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2707
2708 i40e_flush(hw);
2709 for (i = 0; i < vsi->num_q_vectors; i++)
2710 synchronize_irq(pf->msix_entries[i + base].vector);
2711 } else {
2712 /* Legacy and MSI mode - this stops all interrupt handling */
2713 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2714 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2715 i40e_flush(hw);
2716 synchronize_irq(pf->pdev->irq);
2717 }
2718}
2719
2720/**
2721 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2722 * @vsi: the VSI being configured
2723 **/
2724static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2725{
2726 struct i40e_pf *pf = vsi->back;
2727 int i;
2728
2729 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2730 for (i = vsi->base_vector;
2731 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2732 i40e_irq_dynamic_enable(vsi, i);
2733 } else {
2734 i40e_irq_dynamic_enable_icr0(pf);
2735 }
2736
1022cb6c 2737 i40e_flush(&pf->hw);
41c445ff
JB		 2738 return 0;
2739}
2740
2741/**
2742 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2743 * @pf: board private structure
2744 **/
2745static void i40e_stop_misc_vector(struct i40e_pf *pf)
2746{
2747 /* Disable ICR 0 */
2748 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2749 i40e_flush(&pf->hw);
2750}
2751
2752/**
2753 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2754 * @irq: interrupt number
2755 * @data: pointer to a q_vector
2756 *
2757 * This is the handler used for all MSI/Legacy interrupts, and deals
2758 * with both queue and non-queue interrupts. This is also used in
2759 * MSIX mode to handle the non-queue interrupts.
2760 **/
2761static irqreturn_t i40e_intr(int irq, void *data)
2762{
2763 struct i40e_pf *pf = (struct i40e_pf *)data;
2764 struct i40e_hw *hw = &pf->hw;
2765 u32 icr0, icr0_remaining;
2766 u32 val, ena_mask;
2767
2768 icr0 = rd32(hw, I40E_PFINT_ICR0);
2769
116a57d4
SN		 2770 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2771 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
2772 return IRQ_NONE;
2773
41c445ff
JB		 2774 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
2775
cd92e72f
SN		 2776 /* if interrupt but no bits showing, must be SWINT */
2777 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2778 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2779 pf->sw_int_count++;
2780
41c445ff
JB		 2781 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2782 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2783
2784 /* temporarily disable queue cause for NAPI processing */
2785 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2786 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2787 wr32(hw, I40E_QINT_RQCTL(0), qval);
2788
2789 qval = rd32(hw, I40E_QINT_TQCTL(0));
2790 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2791 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2792
2793 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2794 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2795 }
2796
2797 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2798 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2799 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2800 }
2801
2802 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2803 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2804 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2805 }
2806
2807 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2808 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2809 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2810 }
2811
2812 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2813 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2814 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2815 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2816 val = rd32(hw, I40E_GLGEN_RSTAT);
2817 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2818 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
d52cf0a9 2819 if (val == I40E_RESET_CORER)
41c445ff 2820 pf->corer_count++;
d52cf0a9 2821 else if (val == I40E_RESET_GLOBR)
41c445ff 2822 pf->globr_count++;
d52cf0a9 2823 else if (val == I40E_RESET_EMPR)
41c445ff
JB		 2824 pf->empr_count++;
2825 }
2826
9c010ee0
ASJ		 2827 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2828 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2829 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2830 }
2831
41c445ff
JB		 2832 /* If a critical error is pending we have no choice but to reset the
2833 * device.
2834 * Report and mask out any remaining unexpected interrupts.
2835 */
2836 icr0_remaining = icr0 & ena_mask;
2837 if (icr0_remaining) {
2838 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2839 icr0_remaining);
9c010ee0 2840 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff
JB		 2841 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
2842 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
2843 (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
9c010ee0
ASJ		 2844 dev_info(&pf->pdev->dev, "device will be reset\n");
2845 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2846 i40e_service_event_schedule(pf);
41c445ff
JB		 2847 }
2848 ena_mask &= ~icr0_remaining;
2849 }
2850
2851 /* re-enable interrupt causes */
2852 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2853 if (!test_bit(__I40E_DOWN, &pf->state)) {
2854 i40e_service_event_schedule(pf);
2855 i40e_irq_dynamic_enable_icr0(pf);
2856 }
2857
2858 return IRQ_HANDLED;
2859}
2860
2861/**
cd0b6fa6 2862 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 2863 * @vsi: the VSI being configured
2864 * @v_idx: vector index
cd0b6fa6 2865 * @qp_idx: queue pair index
41c445ff 2866 **/
cd0b6fa6 2867static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 2868{
493fb300 2869 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 2870 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
2871 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 2872
2873 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 2874 tx_ring->next = q_vector->tx.ring;
2875 q_vector->tx.ring = tx_ring;
41c445ff 2876 q_vector->tx.count++;
cd0b6fa6
AD		 2877
2878 rx_ring->q_vector = q_vector;
2879 rx_ring->next = q_vector->rx.ring;
2880 q_vector->rx.ring = rx_ring;
2881 q_vector->rx.count++;
41c445ff
JB		 2882}
2883
2884/**
2885 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
2886 * @vsi: the VSI being configured
2887 *
2888 * This function maps descriptor rings to the queue-specific vectors
2889 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2890 * one vector per queue pair, but on a constrained vector budget, we
2891 * group the queue pairs as "efficiently" as possible.
2892 **/
2893static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
2894{
2895 int qp_remaining = vsi->num_queue_pairs;
2896 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 2897 int num_ringpairs;
41c445ff
JB		 2898 int v_start = 0;
2899 int qp_idx = 0;
2900
2901 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2902 * group them so there are multiple queues per vector.
2903 */
2904 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 2905 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
2906
2907 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
2908
2909 q_vector->num_ringpairs = num_ringpairs;
2910
2911 q_vector->rx.count = 0;
2912 q_vector->tx.count = 0;
2913 q_vector->rx.ring = NULL;
2914 q_vector->tx.ring = NULL;
2915
2916 while (num_ringpairs--) {
2917 map_vector_to_qp(vsi, v_start, qp_idx);
2918 qp_idx++;
2919 qp_remaining--;
41c445ff
JB		 2920 }
2921 }
2922}
2923
2924/**
2925 * i40e_vsi_request_irq - Request IRQ from the OS
2926 * @vsi: the VSI being configured
2927 * @basename: name for the vector
2928 **/
2929static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
2930{
2931 struct i40e_pf *pf = vsi->back;
2932 int err;
2933
2934 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
2935 err = i40e_vsi_request_irq_msix(vsi, basename);
2936 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
2937 err = request_irq(pf->pdev->irq, i40e_intr, 0,
2938 pf->misc_int_name, pf);
2939 else
2940 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
2941 pf->misc_int_name, pf);
2942
2943 if (err)
2944 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
2945
2946 return err;
2947}
2948
2949#ifdef CONFIG_NET_POLL_CONTROLLER
2950/**
2951 * i40e_netpoll - A Polling 'interrupt'handler
2952 * @netdev: network interface device structure
2953 *
2954 * This is used by netconsole to send skbs without having to re-enable
2955 * interrupts. It's not called while the normal interrupt routine is executing.
2956 **/
2957static void i40e_netpoll(struct net_device *netdev)
2958{
2959 struct i40e_netdev_priv *np = netdev_priv(netdev);
2960 struct i40e_vsi *vsi = np->vsi;
2961 struct i40e_pf *pf = vsi->back;
2962 int i;
2963
2964 /* if interface is down do nothing */
2965 if (test_bit(__I40E_DOWN, &vsi->state))
2966 return;
2967
2968 pf->flags |= I40E_FLAG_IN_NETPOLL;
2969 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2970 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 2971 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 2972 } else {
2973 i40e_intr(pf->pdev->irq, netdev);
2974 }
2975 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
2976}
2977#endif
2978
2979/**
2980 * i40e_vsi_control_tx - Start or stop a VSI's rings
2981 * @vsi: the VSI being configured
2982 * @enable: start or stop the rings
2983 **/
2984static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
2985{
2986 struct i40e_pf *pf = vsi->back;
2987 struct i40e_hw *hw = &pf->hw;
2988 int i, j, pf_q;
2989 u32 tx_reg;
2990
2991 pf_q = vsi->base_queue;
2992 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
2993 j = 1000;
2994 do {
2995 usleep_range(1000, 2000);
2996 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
2997 } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
2998 ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
2999
fda972f6
MW		 3000 /* Skip if the queue is already in the requested state */
3001 if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3002 continue;
3003 if (!enable && !(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3004 continue;
41c445ff
JB		 3005
3006 /* turn on/off the queue */
3007 if (enable)
3008 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
3009 I40E_QTX_ENA_QENA_STAT_MASK;
3010 else
3011 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3012
3013 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3014
3015 /* wait for the change to finish */
3016 for (j = 0; j < 10; j++) {
3017 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
3018 if (enable) {
3019 if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3020 break;
3021 } else {
3022 if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3023 break;
3024 }
3025
3026 udelay(10);
3027 }
3028 if (j >= 10) {
3029 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3030 pf_q, (enable ? "en" : "dis"));
3031 return -ETIMEDOUT;
3032 }
3033 }
3034
7134f9ce
JB		 3035 if (hw->revision_id == 0)
3036 mdelay(50);
3037
41c445ff
JB		 3038 return 0;
3039}
3040
3041/**
3042 * i40e_vsi_control_rx - Start or stop a VSI's rings
3043 * @vsi: the VSI being configured
3044 * @enable: start or stop the rings
3045 **/
3046static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3047{
3048 struct i40e_pf *pf = vsi->back;
3049 struct i40e_hw *hw = &pf->hw;
3050 int i, j, pf_q;
3051 u32 rx_reg;
3052
3053 pf_q = vsi->base_queue;
3054 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
3055 j = 1000;
3056 do {
3057 usleep_range(1000, 2000);
3058 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3059 } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
3060 ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
3061
3062 if (enable) {
3063 /* is STAT set ? */
3064 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3065 continue;
3066 } else {
3067 /* is !STAT set ? */
3068 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3069 continue;
3070 }
3071
3072 /* turn on/off the queue */
3073 if (enable)
3074 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
3075 I40E_QRX_ENA_QENA_STAT_MASK;
3076 else
3077 rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
3078 I40E_QRX_ENA_QENA_STAT_MASK);
3079 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3080
3081 /* wait for the change to finish */
3082 for (j = 0; j < 10; j++) {
3083 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3084
3085 if (enable) {
3086 if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3087 break;
3088 } else {
3089 if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3090 break;
3091 }
3092
3093 udelay(10);
3094 }
3095 if (j >= 10) {
3096 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3097 pf_q, (enable ? "en" : "dis"));
3098 return -ETIMEDOUT;
3099 }
3100 }
3101
3102 return 0;
3103}
3104
3105/**
3106 * i40e_vsi_control_rings - Start or stop a VSI's rings
3107 * @vsi: the VSI being configured
3108 * @enable: start or stop the rings
3109 **/
fc18eaa0 3110int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff
JB		 3111{
3112 int ret;
3113
3114 /* do rx first for enable and last for disable */
3115 if (request) {
3116 ret = i40e_vsi_control_rx(vsi, request);
3117 if (ret)
3118 return ret;
3119 ret = i40e_vsi_control_tx(vsi, request);
3120 } else {
3121 ret = i40e_vsi_control_tx(vsi, request);
3122 if (ret)
3123 return ret;
3124 ret = i40e_vsi_control_rx(vsi, request);
3125 }
3126
3127 return ret;
3128}
3129
3130/**
3131 * i40e_vsi_free_irq - Free the irq association with the OS
3132 * @vsi: the VSI being configured
3133 **/
3134static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3135{
3136 struct i40e_pf *pf = vsi->back;
3137 struct i40e_hw *hw = &pf->hw;
3138 int base = vsi->base_vector;
3139 u32 val, qp;
3140 int i;
3141
3142 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3143 if (!vsi->q_vectors)
3144 return;
3145
3146 for (i = 0; i < vsi->num_q_vectors; i++) {
3147 u16 vector = i + base;
3148
3149 /* free only the irqs that were actually requested */
78681b1f
SN		 3150 if (!vsi->q_vectors[i] ||
3151 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3152 continue;
3153
3154 /* clear the affinity_mask in the IRQ descriptor */
3155 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3156 NULL);
3157 free_irq(pf->msix_entries[vector].vector,
493fb300 3158 vsi->q_vectors[i]);
41c445ff
JB		 3159
3160 /* Tear down the interrupt queue link list
3161 *
3162 * We know that they come in pairs and always
3163 * the Rx first, then the Tx. To clear the
3164 * link list, stick the EOL value into the
3165 * next_q field of the registers.
3166 */
3167 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3168 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3169 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3170 val |= I40E_QUEUE_END_OF_LIST
3171 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3172 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3173
3174 while (qp != I40E_QUEUE_END_OF_LIST) {
3175 u32 next;
3176
3177 val = rd32(hw, I40E_QINT_RQCTL(qp));
3178
3179 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3180 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3181 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3182 I40E_QINT_RQCTL_INTEVENT_MASK);
3183
3184 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3185 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3186
3187 wr32(hw, I40E_QINT_RQCTL(qp), val);
3188
3189 val = rd32(hw, I40E_QINT_TQCTL(qp));
3190
3191 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3192 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3193
3194 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3195 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3196 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3197 I40E_QINT_TQCTL_INTEVENT_MASK);
3198
3199 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3200 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3201
3202 wr32(hw, I40E_QINT_TQCTL(qp), val);
3203 qp = next;
3204 }
3205 }
3206 } else {
3207 free_irq(pf->pdev->irq, pf);
3208
3209 val = rd32(hw, I40E_PFINT_LNKLST0);
3210 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3211 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3212 val |= I40E_QUEUE_END_OF_LIST
3213 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3214 wr32(hw, I40E_PFINT_LNKLST0, val);
3215
3216 val = rd32(hw, I40E_QINT_RQCTL(qp));
3217 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3218 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3219 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3220 I40E_QINT_RQCTL_INTEVENT_MASK);
3221
3222 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3223 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3224
3225 wr32(hw, I40E_QINT_RQCTL(qp), val);
3226
3227 val = rd32(hw, I40E_QINT_TQCTL(qp));
3228
3229 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3230 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3231 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3232 I40E_QINT_TQCTL_INTEVENT_MASK);
3233
3234 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3235 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3236
3237 wr32(hw, I40E_QINT_TQCTL(qp), val);
3238 }
3239}
3240
493fb300
AD		 3241/**
3242 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3243 * @vsi: the VSI being configured
3244 * @v_idx: Index of vector to be freed
3245 *
3246 * This function frees the memory allocated to the q_vector. In addition if
3247 * NAPI is enabled it will delete any references to the NAPI struct prior
3248 * to freeing the q_vector.
3249 **/
3250static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3251{
3252 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3253 struct i40e_ring *ring;
493fb300
AD		 3254
3255 if (!q_vector)
3256 return;
3257
3258 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3259 i40e_for_each_ring(ring, q_vector->tx)
3260 ring->q_vector = NULL;
3261
3262 i40e_for_each_ring(ring, q_vector->rx)
3263 ring->q_vector = NULL;
493fb300
AD		 3264
3265 /* only VSI w/ an associated netdev is set up w/ NAPI */
3266 if (vsi->netdev)
3267 netif_napi_del(&q_vector->napi);
3268
3269 vsi->q_vectors[v_idx] = NULL;
3270
3271 kfree_rcu(q_vector, rcu);
3272}
3273
41c445ff
JB		 3274/**
3275 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3276 * @vsi: the VSI being un-configured
3277 *
3278 * This frees the memory allocated to the q_vectors and
3279 * deletes references to the NAPI struct.
3280 **/
3281static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3282{
3283 int v_idx;
3284
493fb300
AD		 3285 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3286 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3287}
3288
3289/**
3290 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3291 * @pf: board private structure
3292 **/
3293static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3294{
3295 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3296 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3297 pci_disable_msix(pf->pdev);
3298 kfree(pf->msix_entries);
3299 pf->msix_entries = NULL;
3300 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3301 pci_disable_msi(pf->pdev);
3302 }
3303 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3304}
3305
3306/**
3307 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3308 * @pf: board private structure
3309 *
3310 * We go through and clear interrupt specific resources and reset the structure
3311 * to pre-load conditions
3312 **/
3313static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3314{
3315 int i;
3316
3317 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
3318 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
3319 if (pf->vsi[i])
3320 i40e_vsi_free_q_vectors(pf->vsi[i]);
3321 i40e_reset_interrupt_capability(pf);
3322}
3323
3324/**
3325 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3326 * @vsi: the VSI being configured
3327 **/
3328static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3329{
3330 int q_idx;
3331
3332 if (!vsi->netdev)
3333 return;
3334
3335 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3336 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3337}
3338
3339/**
3340 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3341 * @vsi: the VSI being configured
3342 **/
3343static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3344{
3345 int q_idx;
3346
3347 if (!vsi->netdev)
3348 return;
3349
3350 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3351 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3352}
3353
3354/**
3355 * i40e_quiesce_vsi - Pause a given VSI
3356 * @vsi: the VSI being paused
3357 **/
3358static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3359{
3360 if (test_bit(__I40E_DOWN, &vsi->state))
3361 return;
3362
3363 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3364 if (vsi->netdev && netif_running(vsi->netdev)) {
3365 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3366 } else {
3367 set_bit(__I40E_DOWN, &vsi->state);
3368 i40e_down(vsi);
3369 }
3370}
3371
3372/**
3373 * i40e_unquiesce_vsi - Resume a given VSI
3374 * @vsi: the VSI being resumed
3375 **/
3376static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3377{
3378 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3379 return;
3380
3381 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3382 if (vsi->netdev && netif_running(vsi->netdev))
3383 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3384 else
3385 i40e_up(vsi); /* this clears the DOWN bit */
3386}
3387
3388/**
3389 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3390 * @pf: the PF
3391 **/
3392static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3393{
3394 int v;
3395
3396 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3397 if (pf->vsi[v])
3398 i40e_quiesce_vsi(pf->vsi[v]);
3399 }
3400}
3401
3402/**
3403 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3404 * @pf: the PF
3405 **/
3406static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3407{
3408 int v;
3409
3410 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
3411 if (pf->vsi[v])
3412 i40e_unquiesce_vsi(pf->vsi[v]);
3413 }
3414}
3415
3416/**
3417 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3418 * @dcbcfg: the corresponding DCBx configuration structure
3419 *
3420 * Return the number of TCs from given DCBx configuration
3421 **/
3422static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3423{
078b5876
JB		 3424 u8 num_tc = 0;
3425 int i;
41c445ff
JB		 3426
3427 /* Scan the ETS Config Priority Table to find
3428 * traffic class enabled for a given priority
3429 * and use the traffic class index to get the
3430 * number of traffic classes enabled
3431 */
3432 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3433 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3434 num_tc = dcbcfg->etscfg.prioritytable[i];
3435 }
3436
3437 /* Traffic class index starts from zero so
3438 * increment to return the actual count
3439 */
078b5876 3440 return num_tc + 1;
41c445ff
JB		 3441}
3442
3443/**
3444 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3445 * @dcbcfg: the corresponding DCBx configuration structure
3446 *
3447 * Query the current DCB configuration and return the number of
3448 * traffic classes enabled from the given DCBX config
3449 **/
3450static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3451{
3452 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3453 u8 enabled_tc = 1;
3454 u8 i;
3455
3456 for (i = 0; i < num_tc; i++)
3457 enabled_tc |= 1 << i;
3458
3459 return enabled_tc;
3460}
3461
3462/**
3463 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3464 * @pf: PF being queried
3465 *
3466 * Return number of traffic classes enabled for the given PF
3467 **/
3468static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3469{
3470 struct i40e_hw *hw = &pf->hw;
3471 u8 i, enabled_tc;
3472 u8 num_tc = 0;
3473 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3474
3475 /* If DCB is not enabled then always in single TC */
3476 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3477 return 1;
3478
3479 /* MFP mode return count of enabled TCs for this PF */
3480 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3481 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3482 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3483 if (enabled_tc & (1 << i))
3484 num_tc++;
3485 }
3486 return num_tc;
3487 }
3488
3489 /* SFP mode will be enabled for all TCs on port */
3490 return i40e_dcb_get_num_tc(dcbcfg);
3491}
3492
3493/**
3494 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3495 * @pf: PF being queried
3496 *
3497 * Return a bitmap for first enabled traffic class for this PF.
3498 **/
3499static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3500{
3501 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3502 u8 i = 0;
3503
3504 if (!enabled_tc)
3505 return 0x1; /* TC0 */
3506
3507 /* Find the first enabled TC */
3508 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3509 if (enabled_tc & (1 << i))
3510 break;
3511 }
3512
3513 return 1 << i;
3514}
3515
3516/**
3517 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3518 * @pf: PF being queried
3519 *
3520 * Return a bitmap for enabled traffic classes for this PF.
3521 **/
3522static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3523{
3524 /* If DCB is not enabled for this PF then just return default TC */
3525 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3526 return i40e_pf_get_default_tc(pf);
3527
3528 /* MFP mode will have enabled TCs set by FW */
3529 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3530 return pf->hw.func_caps.enabled_tcmap;
3531
3532 /* SFP mode we want PF to be enabled for all TCs */
3533 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3534}
3535
3536/**
3537 * i40e_vsi_get_bw_info - Query VSI BW Information
3538 * @vsi: the VSI being queried
3539 *
3540 * Returns 0 on success, negative value on failure
3541 **/
3542static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3543{
3544 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3545 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3546 struct i40e_pf *pf = vsi->back;
3547 struct i40e_hw *hw = &pf->hw;
dcae29be 3548 i40e_status aq_ret;
41c445ff 3549 u32 tc_bw_max;
41c445ff
JB		 3550 int i;
3551
3552 /* Get the VSI level BW configuration */
dcae29be
JB		 3553 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3554 if (aq_ret) {
41c445ff
JB		 3555 dev_info(&pf->pdev->dev,
3556 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3557 aq_ret, pf->hw.aq.asq_last_status);
3558 return -EINVAL;
41c445ff
JB		 3559 }
3560
3561 /* Get the VSI level BW configuration per TC */
dcae29be
JB		 3562 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
3563 NULL);
3564 if (aq_ret) {
41c445ff
JB		 3565 dev_info(&pf->pdev->dev,
3566 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3567 aq_ret, pf->hw.aq.asq_last_status);
3568 return -EINVAL;
41c445ff
JB		 3569 }
3570
3571 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3572 dev_info(&pf->pdev->dev,
3573 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3574 bw_config.tc_valid_bits,
3575 bw_ets_config.tc_valid_bits);
3576 /* Still continuing */
3577 }
3578
3579 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3580 vsi->bw_max_quanta = bw_config.max_bw;
3581 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3582 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3584 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3585 vsi->bw_ets_limit_credits[i] =
3586 le16_to_cpu(bw_ets_config.credits[i]);
3587 /* 3 bits out of 4 for each TC */
3588 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3589 }
078b5876 3590
dcae29be 3591 return 0;
41c445ff
JB		 3592}
3593
3594/**
3595 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3596 * @vsi: the VSI being configured
3597 * @enabled_tc: TC bitmap
3598 * @bw_credits: BW shared credits per TC
3599 *
3600 * Returns 0 on success, negative value on failure
3601 **/
dcae29be 3602static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3603 u8 *bw_share)
3604{
3605 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3606 i40e_status aq_ret;
3607 int i;
41c445ff
JB		 3608
3609 bw_data.tc_valid_bits = enabled_tc;
3610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3611 bw_data.tc_bw_credits[i] = bw_share[i];
3612
dcae29be
JB		 3613 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3614 NULL);
3615 if (aq_ret) {
41c445ff
JB		 3616 dev_info(&vsi->back->pdev->dev,
3617 "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
3618 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 3619 return -EINVAL;
41c445ff
JB		 3620 }
3621
3622 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3623 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3624
dcae29be 3625 return 0;
41c445ff
JB		 3626}
3627
3628/**
3629 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3630 * @vsi: the VSI being configured
3631 * @enabled_tc: TC map to be enabled
3632 *
3633 **/
3634static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3635{
3636 struct net_device *netdev = vsi->netdev;
3637 struct i40e_pf *pf = vsi->back;
3638 struct i40e_hw *hw = &pf->hw;
3639 u8 netdev_tc = 0;
3640 int i;
3641 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3642
3643 if (!netdev)
3644 return;
3645
3646 if (!enabled_tc) {
3647 netdev_reset_tc(netdev);
3648 return;
3649 }
3650
3651 /* Set up actual enabled TCs on the VSI */
3652 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3653 return;
3654
3655 /* set per TC queues for the VSI */
3656 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3657 /* Only set TC queues for enabled tcs
3658 *
3659 * e.g. For a VSI that has TC0 and TC3 enabled the
3660 * enabled_tc bitmap would be 0x00001001; the driver
3661 * will set the numtc for netdev as 2 that will be
3662 * referenced by the netdev layer as TC 0 and 1.
3663 */
3664 if (vsi->tc_config.enabled_tc & (1 << i))
3665 netdev_set_tc_queue(netdev,
3666 vsi->tc_config.tc_info[i].netdev_tc,
3667 vsi->tc_config.tc_info[i].qcount,
3668 vsi->tc_config.tc_info[i].qoffset);
3669 }
3670
3671 /* Assign UP2TC map for the VSI */
3672 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3673 /* Get the actual TC# for the UP */
3674 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3675 /* Get the mapped netdev TC# for the UP */
3676 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3677 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3678 }
3679}
3680
3681/**
3682 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3683 * @vsi: the VSI being configured
3684 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3685 **/
3686static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3687 struct i40e_vsi_context *ctxt)
3688{
3689 /* copy just the sections touched not the entire info
3690 * since not all sections are valid as returned by
3691 * update vsi params
3692 */
3693 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3694 memcpy(&vsi->info.queue_mapping,
3695 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3696 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3697 sizeof(vsi->info.tc_mapping));
3698}
3699
3700/**
3701 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3702 * @vsi: VSI to be configured
3703 * @enabled_tc: TC bitmap
3704 *
3705 * This configures a particular VSI for TCs that are mapped to the
3706 * given TC bitmap. It uses default bandwidth share for TCs across
3707 * VSIs to configure TC for a particular VSI.
3708 *
3709 * NOTE:
3710 * It is expected that the VSI queues have been quisced before calling
3711 * this function.
3712 **/
3713static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3714{
3715 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3716 struct i40e_vsi_context ctxt;
3717 int ret = 0;
3718 int i;
3719
3720 /* Check if enabled_tc is same as existing or new TCs */
3721 if (vsi->tc_config.enabled_tc == enabled_tc)
3722 return ret;
3723
3724 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3725 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3726 if (enabled_tc & (1 << i))
3727 bw_share[i] = 1;
3728 }
3729
3730 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3731 if (ret) {
3732 dev_info(&vsi->back->pdev->dev,
3733 "Failed configuring TC map %d for VSI %d\n",
3734 enabled_tc, vsi->seid);
3735 goto out;
3736 }
3737
3738 /* Update Queue Pairs Mapping for currently enabled UPs */
3739 ctxt.seid = vsi->seid;
3740 ctxt.pf_num = vsi->back->hw.pf_id;
3741 ctxt.vf_num = 0;
3742 ctxt.uplink_seid = vsi->uplink_seid;
3743 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3744 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3745
3746 /* Update the VSI after updating the VSI queue-mapping information */
3747 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3748 if (ret) {
3749 dev_info(&vsi->back->pdev->dev,
3750 "update vsi failed, aq_err=%d\n",
3751 vsi->back->hw.aq.asq_last_status);
3752 goto out;
3753 }
3754 /* update the local VSI info with updated queue map */
3755 i40e_vsi_update_queue_map(vsi, &ctxt);
3756 vsi->info.valid_sections = 0;
3757
3758 /* Update current VSI BW information */
3759 ret = i40e_vsi_get_bw_info(vsi);
3760 if (ret) {
3761 dev_info(&vsi->back->pdev->dev,
3762 "Failed updating vsi bw info, aq_err=%d\n",
3763 vsi->back->hw.aq.asq_last_status);
3764 goto out;
3765 }
3766
3767 /* Update the netdev TC setup */
3768 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3769out:
3770 return ret;
3771}
3772
3773/**
3774 * i40e_up_complete - Finish the last steps of bringing up a connection
3775 * @vsi: the VSI being configured
3776 **/
3777static int i40e_up_complete(struct i40e_vsi *vsi)
3778{
3779 struct i40e_pf *pf = vsi->back;
3780 int err;
3781
3782 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3783 i40e_vsi_configure_msix(vsi);
3784 else
3785 i40e_configure_msi_and_legacy(vsi);
3786
3787 /* start rings */
3788 err = i40e_vsi_control_rings(vsi, true);
3789 if (err)
3790 return err;
3791
3792 clear_bit(__I40E_DOWN, &vsi->state);
3793 i40e_napi_enable_all(vsi);
3794 i40e_vsi_enable_irq(vsi);
3795
3796 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
3797 (vsi->netdev)) {
6d779b41 3798 netdev_info(vsi->netdev, "NIC Link is Up\n");
41c445ff
JB		 3799 netif_tx_start_all_queues(vsi->netdev);
3800 netif_carrier_on(vsi->netdev);
6d779b41
AS		 3801 } else if (vsi->netdev) {
3802 netdev_info(vsi->netdev, "NIC Link is Down\n");
41c445ff
JB		 3803 }
3804 i40e_service_event_schedule(pf);
3805
3806 return 0;
3807}
3808
3809/**
3810 * i40e_vsi_reinit_locked - Reset the VSI
3811 * @vsi: the VSI being configured
3812 *
3813 * Rebuild the ring structs after some configuration
3814 * has changed, e.g. MTU size.
3815 **/
3816static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
3817{
3818 struct i40e_pf *pf = vsi->back;
3819
3820 WARN_ON(in_interrupt());
3821 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
3822 usleep_range(1000, 2000);
3823 i40e_down(vsi);
3824
3825 /* Give a VF some time to respond to the reset. The
3826 * two second wait is based upon the watchdog cycle in
3827 * the VF driver.
3828 */
3829 if (vsi->type == I40E_VSI_SRIOV)
3830 msleep(2000);
3831 i40e_up(vsi);
3832 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
3833}
3834
3835/**
3836 * i40e_up - Bring the connection back up after being down
3837 * @vsi: the VSI being configured
3838 **/
3839int i40e_up(struct i40e_vsi *vsi)
3840{
3841 int err;
3842
3843 err = i40e_vsi_configure(vsi);
3844 if (!err)
3845 err = i40e_up_complete(vsi);
3846
3847 return err;
3848}
3849
3850/**
3851 * i40e_down - Shutdown the connection processing
3852 * @vsi: the VSI being stopped
3853 **/
3854void i40e_down(struct i40e_vsi *vsi)
3855{
3856 int i;
3857
3858 /* It is assumed that the caller of this function
3859 * sets the vsi->state __I40E_DOWN bit.
3860 */
3861 if (vsi->netdev) {
3862 netif_carrier_off(vsi->netdev);
3863 netif_tx_disable(vsi->netdev);
3864 }
3865 i40e_vsi_disable_irq(vsi);
3866 i40e_vsi_control_rings(vsi, false);
3867 i40e_napi_disable_all(vsi);
3868
3869 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3870 i40e_clean_tx_ring(vsi->tx_rings[i]);
3871 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 3872 }
3873}
3874
3875/**
3876 * i40e_setup_tc - configure multiple traffic classes
3877 * @netdev: net device to configure
3878 * @tc: number of traffic classes to enable
3879 **/
3880static int i40e_setup_tc(struct net_device *netdev, u8 tc)
3881{
3882 struct i40e_netdev_priv *np = netdev_priv(netdev);
3883 struct i40e_vsi *vsi = np->vsi;
3884 struct i40e_pf *pf = vsi->back;
3885 u8 enabled_tc = 0;
3886 int ret = -EINVAL;
3887 int i;
3888
3889 /* Check if DCB enabled to continue */
3890 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
3891 netdev_info(netdev, "DCB is not enabled for adapter\n");
3892 goto exit;
3893 }
3894
3895 /* Check if MFP enabled */
3896 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3897 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
3898 goto exit;
3899 }
3900
3901 /* Check whether tc count is within enabled limit */
3902 if (tc > i40e_pf_get_num_tc(pf)) {
3903 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
3904 goto exit;
3905 }
3906
3907 /* Generate TC map for number of tc requested */
3908 for (i = 0; i < tc; i++)
3909 enabled_tc |= (1 << i);
3910
3911 /* Requesting same TC configuration as already enabled */
3912 if (enabled_tc == vsi->tc_config.enabled_tc)
3913 return 0;
3914
3915 /* Quiesce VSI queues */
3916 i40e_quiesce_vsi(vsi);
3917
3918 /* Configure VSI for enabled TCs */
3919 ret = i40e_vsi_config_tc(vsi, enabled_tc);
3920 if (ret) {
3921 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
3922 vsi->seid);
3923 goto exit;
3924 }
3925
3926 /* Unquiesce VSI */
3927 i40e_unquiesce_vsi(vsi);
3928
3929exit:
3930 return ret;
3931}
3932
3933/**
3934 * i40e_open - Called when a network interface is made active
3935 * @netdev: network interface device structure
3936 *
3937 * The open entry point is called when a network interface is made
3938 * active by the system (IFF_UP). At this point all resources needed
3939 * for transmit and receive operations are allocated, the interrupt
3940 * handler is registered with the OS, the netdev watchdog subtask is
3941 * enabled, and the stack is notified that the interface is ready.
3942 *
3943 * Returns 0 on success, negative value on failure
3944 **/
3945static int i40e_open(struct net_device *netdev)
3946{
3947 struct i40e_netdev_priv *np = netdev_priv(netdev);
3948 struct i40e_vsi *vsi = np->vsi;
3949 struct i40e_pf *pf = vsi->back;
3950 char int_name[IFNAMSIZ];
3951 int err;
3952
3953 /* disallow open during test */
3954 if (test_bit(__I40E_TESTING, &pf->state))
3955 return -EBUSY;
3956
3957 netif_carrier_off(netdev);
3958
3959 /* allocate descriptors */
3960 err = i40e_vsi_setup_tx_resources(vsi);
3961 if (err)
3962 goto err_setup_tx;
3963 err = i40e_vsi_setup_rx_resources(vsi);
3964 if (err)
3965 goto err_setup_rx;
3966
3967 err = i40e_vsi_configure(vsi);
3968 if (err)
3969 goto err_setup_rx;
3970
3971 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
3972 dev_driver_string(&pf->pdev->dev), netdev->name);
3973 err = i40e_vsi_request_irq(vsi, int_name);
3974 if (err)
3975 goto err_setup_rx;
3976
25946ddb 3977 /* Notify the stack of the actual queue counts. */
d7397644 3978 err = netif_set_real_num_tx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3979 if (err)
3980 goto err_set_queues;
3981
d7397644 3982 err = netif_set_real_num_rx_queues(netdev, vsi->num_queue_pairs);
25946ddb
ASJ		 3983 if (err)
3984 goto err_set_queues;
3985
41c445ff
JB		 3986 err = i40e_up_complete(vsi);
3987 if (err)
3988 goto err_up_complete;
3989
3990 if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
3991 err = i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, true, NULL);
3992 if (err)
3993 netdev_info(netdev,
3994 "couldn't set broadcast err %d aq_err %d\n",
3995 err, pf->hw.aq.asq_last_status);
3996 }
a1c9a9d9
JK		 3997#ifdef CONFIG_I40E_VXLAN
3998 vxlan_get_rx_port(netdev);
3999#endif
41c445ff
JB		 4000
4001 return 0;
4002
4003err_up_complete:
4004 i40e_down(vsi);
25946ddb 4005err_set_queues:
41c445ff
JB		 4006 i40e_vsi_free_irq(vsi);
4007err_setup_rx:
4008 i40e_vsi_free_rx_resources(vsi);
4009err_setup_tx:
4010 i40e_vsi_free_tx_resources(vsi);
4011 if (vsi == pf->vsi[pf->lan_vsi])
4012 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4013
4014 return err;
4015}
4016
4017/**
4018 * i40e_close - Disables a network interface
4019 * @netdev: network interface device structure
4020 *
4021 * The close entry point is called when an interface is de-activated
4022 * by the OS. The hardware is still under the driver's control, but
4023 * this netdev interface is disabled.
4024 *
4025 * Returns 0, this is not allowed to fail
4026 **/
4027static int i40e_close(struct net_device *netdev)
4028{
4029 struct i40e_netdev_priv *np = netdev_priv(netdev);
4030 struct i40e_vsi *vsi = np->vsi;
4031
4032 if (test_and_set_bit(__I40E_DOWN, &vsi->state))
4033 return 0;
4034
4035 i40e_down(vsi);
4036 i40e_vsi_free_irq(vsi);
4037
4038 i40e_vsi_free_tx_resources(vsi);
4039 i40e_vsi_free_rx_resources(vsi);
4040
4041 return 0;
4042}
4043
4044/**
4045 * i40e_do_reset - Start a PF or Core Reset sequence
4046 * @pf: board private structure
4047 * @reset_flags: which reset is requested
4048 *
4049 * The essential difference in resets is that the PF Reset
4050 * doesn't clear the packet buffers, doesn't reset the PE
4051 * firmware, and doesn't bother the other PFs on the chip.
4052 **/
4053void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4054{
4055 u32 val;
4056
4057 WARN_ON(in_interrupt());
4058
4059 /* do the biggest reset indicated */
4060 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4061
4062 /* Request a Global Reset
4063 *
4064 * This will start the chip's countdown to the actual full
4065 * chip reset event, and a warning interrupt to be sent
4066 * to all PFs, including the requestor. Our handler
4067 * for the warning interrupt will deal with the shutdown
4068 * and recovery of the switch setup.
4069 */
4070 dev_info(&pf->pdev->dev, "GlobalR requested\n");
4071 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4072 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4073 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4074
4075 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4076
4077 /* Request a Core Reset
4078 *
4079 * Same as Global Reset, except does *not* include the MAC/PHY
4080 */
4081 dev_info(&pf->pdev->dev, "CoreR requested\n");
4082 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4083 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4084 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4085 i40e_flush(&pf->hw);
4086
7823fe34
SN		 4087 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4088
4089 /* Request a Firmware Reset
4090 *
4091 * Same as Global reset, plus restarting the
4092 * embedded firmware engine.
4093 */
4094 /* enable EMP Reset */
4095 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4096 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4097 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4098
4099 /* force the reset */
4100 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4101 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4102 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4103 i40e_flush(&pf->hw);
4104
41c445ff
JB		 4105 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4106
4107 /* Request a PF Reset
4108 *
4109 * Resets only the PF-specific registers
4110 *
4111 * This goes directly to the tear-down and rebuild of
4112 * the switch, since we need to do all the recovery as
4113 * for the Core Reset.
4114 */
4115 dev_info(&pf->pdev->dev, "PFR requested\n");
4116 i40e_handle_reset_warning(pf);
4117
4118 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4119 int v;
4120
4121 /* Find the VSI(s) that requested a re-init */
4122 dev_info(&pf->pdev->dev,
4123 "VSI reinit requested\n");
4124 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4125 struct i40e_vsi *vsi = pf->vsi[v];
4126 if (vsi != NULL &&
4127 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4128 i40e_vsi_reinit_locked(pf->vsi[v]);
4129 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4130 }
4131 }
4132
4133 /* no further action needed, so return now */
4134 return;
4135 } else {
4136 dev_info(&pf->pdev->dev,
4137 "bad reset request 0x%08x\n", reset_flags);
4138 return;
4139 }
4140}
4141
23326186
ASJ		 4142/**
4143 * i40e_do_reset_safe - Protected reset path for userland calls.
4144 * @pf: board private structure
4145 * @reset_flags: which reset is requested
4146 *
4147 **/
4148void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4149{
4150 rtnl_lock();
4151 i40e_do_reset(pf, reset_flags);
4152 rtnl_unlock();
4153}
4154
41c445ff
JB		 4155/**
4156 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4157 * @pf: board private structure
4158 * @e: event info posted on ARQ
4159 *
4160 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4161 * and VF queues
4162 **/
4163static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4164 struct i40e_arq_event_info *e)
4165{
4166 struct i40e_aqc_lan_overflow *data =
4167 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4168 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4169 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4170 struct i40e_hw *hw = &pf->hw;
4171 struct i40e_vf *vf;
4172 u16 vf_id;
4173
4174 dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
4175 __func__, queue, qtx_ctl);
4176
4177 /* Queue belongs to VF, find the VF and issue VF reset */
4178 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4179 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4180 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4181 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4182 vf_id -= hw->func_caps.vf_base_id;
4183 vf = &pf->vf[vf_id];
4184 i40e_vc_notify_vf_reset(vf);
4185 /* Allow VF to process pending reset notification */
4186 msleep(20);
4187 i40e_reset_vf(vf, false);
4188 }
4189}
4190
4191/**
4192 * i40e_service_event_complete - Finish up the service event
4193 * @pf: board private structure
4194 **/
4195static void i40e_service_event_complete(struct i40e_pf *pf)
4196{
4197 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4198
4199 /* flush memory to make sure state is correct before next watchog */
4200 smp_mb__before_clear_bit();
4201 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4202}
4203
4204/**
4205 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4206 * @pf: board private structure
4207 **/
4208static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4209{
4210 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4211 return;
4212
4213 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
4214
4215 /* if interface is down do nothing */
4216 if (test_bit(__I40E_DOWN, &pf->state))
4217 return;
4218}
4219
4220/**
4221 * i40e_vsi_link_event - notify VSI of a link event
4222 * @vsi: vsi to be notified
4223 * @link_up: link up or down
4224 **/
4225static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4226{
4227 if (!vsi)
4228 return;
4229
4230 switch (vsi->type) {
4231 case I40E_VSI_MAIN:
4232 if (!vsi->netdev || !vsi->netdev_registered)
4233 break;
4234
4235 if (link_up) {
4236 netif_carrier_on(vsi->netdev);
4237 netif_tx_wake_all_queues(vsi->netdev);
4238 } else {
4239 netif_carrier_off(vsi->netdev);
4240 netif_tx_stop_all_queues(vsi->netdev);
4241 }
4242 break;
4243
4244 case I40E_VSI_SRIOV:
4245 break;
4246
4247 case I40E_VSI_VMDQ2:
4248 case I40E_VSI_CTRL:
4249 case I40E_VSI_MIRROR:
4250 default:
4251 /* there is no notification for other VSIs */
4252 break;
4253 }
4254}
4255
4256/**
4257 * i40e_veb_link_event - notify elements on the veb of a link event
4258 * @veb: veb to be notified
4259 * @link_up: link up or down
4260 **/
4261static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4262{
4263 struct i40e_pf *pf;
4264 int i;
4265
4266 if (!veb || !veb->pf)
4267 return;
4268 pf = veb->pf;
4269
4270 /* depth first... */
4271 for (i = 0; i < I40E_MAX_VEB; i++)
4272 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4273 i40e_veb_link_event(pf->veb[i], link_up);
4274
4275 /* ... now the local VSIs */
4276 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4277 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4278 i40e_vsi_link_event(pf->vsi[i], link_up);
4279}
4280
4281/**
4282 * i40e_link_event - Update netif_carrier status
4283 * @pf: board private structure
4284 **/
4285static void i40e_link_event(struct i40e_pf *pf)
4286{
4287 bool new_link, old_link;
4288
4289 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4290 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4291
4292 if (new_link == old_link)
4293 return;
4294
6d779b41
AS		 4295 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
4296 netdev_info(pf->vsi[pf->lan_vsi]->netdev,
4297 "NIC Link is %s\n", (new_link ? "Up" : "Down"));
41c445ff
JB		 4298
4299 /* Notify the base of the switch tree connected to
4300 * the link. Floating VEBs are not notified.
4301 */
4302 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4303 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4304 else
4305 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4306
4307 if (pf->vf)
4308 i40e_vc_notify_link_state(pf);
4309}
4310
4311/**
4312 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4313 * @pf: board private structure
4314 *
4315 * Set the per-queue flags to request a check for stuck queues in the irq
4316 * clean functions, then force interrupts to be sure the irq clean is called.
4317 **/
4318static void i40e_check_hang_subtask(struct i40e_pf *pf)
4319{
4320 int i, v;
4321
4322 /* If we're down or resetting, just bail */
4323 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4324 return;
4325
4326 /* for each VSI/netdev
4327 * for each Tx queue
4328 * set the check flag
4329 * for each q_vector
4330 * force an interrupt
4331 */
4332 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4333 struct i40e_vsi *vsi = pf->vsi[v];
4334 int armed = 0;
4335
4336 if (!pf->vsi[v] ||
4337 test_bit(__I40E_DOWN, &vsi->state) ||
4338 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4339 continue;
4340
4341 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4342 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4343 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4344 &vsi->tx_rings[i]->state))
41c445ff
JB		 4345 armed++;
4346 }
4347
4348 if (armed) {
4349 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
4350 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
4351 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
4352 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
4353 } else {
4354 u16 vec = vsi->base_vector - 1;
4355 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
4356 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
4357 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
4358 wr32(&vsi->back->hw,
4359 I40E_PFINT_DYN_CTLN(vec), val);
4360 }
4361 i40e_flush(&vsi->back->hw);
4362 }
4363 }
4364}
4365
4366/**
4367 * i40e_watchdog_subtask - Check and bring link up
4368 * @pf: board private structure
4369 **/
4370static void i40e_watchdog_subtask(struct i40e_pf *pf)
4371{
4372 int i;
4373
4374 /* if interface is down do nothing */
4375 if (test_bit(__I40E_DOWN, &pf->state) ||
4376 test_bit(__I40E_CONFIG_BUSY, &pf->state))
4377 return;
4378
4379 /* Update the stats for active netdevs so the network stack
4380 * can look at updated numbers whenever it cares to
4381 */
4382 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4383 if (pf->vsi[i] && pf->vsi[i]->netdev)
4384 i40e_update_stats(pf->vsi[i]);
4385
4386 /* Update the stats for the active switching components */
4387 for (i = 0; i < I40E_MAX_VEB; i++)
4388 if (pf->veb[i])
4389 i40e_update_veb_stats(pf->veb[i]);
4390}
4391
4392/**
4393 * i40e_reset_subtask - Set up for resetting the device and driver
4394 * @pf: board private structure
4395 **/
4396static void i40e_reset_subtask(struct i40e_pf *pf)
4397{
4398 u32 reset_flags = 0;
4399
23326186 4400 rtnl_lock();
41c445ff
JB		 4401 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
4402 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
4403 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
4404 }
4405 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
4406 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
4407 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4408 }
4409 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
4410 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
4411 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
4412 }
4413 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
4414 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
4415 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
4416 }
4417
4418 /* If there's a recovery already waiting, it takes
4419 * precedence before starting a new reset sequence.
4420 */
4421 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
4422 i40e_handle_reset_warning(pf);
23326186 4423 goto unlock;
41c445ff
JB		 4424 }
4425
4426 /* If we're already down or resetting, just bail */
4427 if (reset_flags &&
4428 !test_bit(__I40E_DOWN, &pf->state) &&
4429 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
4430 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 4431
4432unlock:
4433 rtnl_unlock();
41c445ff
JB		 4434}
4435
4436/**
4437 * i40e_handle_link_event - Handle link event
4438 * @pf: board private structure
4439 * @e: event info posted on ARQ
4440 **/
4441static void i40e_handle_link_event(struct i40e_pf *pf,
4442 struct i40e_arq_event_info *e)
4443{
4444 struct i40e_hw *hw = &pf->hw;
4445 struct i40e_aqc_get_link_status *status =
4446 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
4447 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
4448
4449 /* save off old link status information */
4450 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
4451 sizeof(pf->hw.phy.link_info_old));
4452
4453 /* update link status */
4454 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
4455 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
4456 hw_link_info->link_info = status->link_info;
4457 hw_link_info->an_info = status->an_info;
4458 hw_link_info->ext_info = status->ext_info;
4459 hw_link_info->lse_enable =
4460 le16_to_cpu(status->command_flags) &
4461 I40E_AQ_LSE_ENABLE;
4462
4463 /* process the event */
4464 i40e_link_event(pf);
4465
4466 /* Do a new status request to re-enable LSE reporting
4467 * and load new status information into the hw struct,
4468 * then see if the status changed while processing the
4469 * initial event.
4470 */
4471 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
4472 i40e_link_event(pf);
4473}
4474
4475/**
4476 * i40e_clean_adminq_subtask - Clean the AdminQ rings
4477 * @pf: board private structure
4478 **/
4479static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
4480{
4481 struct i40e_arq_event_info event;
4482 struct i40e_hw *hw = &pf->hw;
4483 u16 pending, i = 0;
4484 i40e_status ret;
4485 u16 opcode;
4486 u32 val;
4487
4488 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
4489 return;
4490
3197ce22 4491 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 4492 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
4493 if (!event.msg_buf)
4494 return;
4495
4496 do {
2f019123 4497 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 4498 ret = i40e_clean_arq_element(hw, &event, &pending);
4499 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
4500 dev_info(&pf->pdev->dev, "No ARQ event found\n");
4501 break;
4502 } else if (ret) {
4503 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
4504 break;
4505 }
4506
4507 opcode = le16_to_cpu(event.desc.opcode);
4508 switch (opcode) {
4509
4510 case i40e_aqc_opc_get_link_status:
4511 i40e_handle_link_event(pf, &event);
4512 break;
4513 case i40e_aqc_opc_send_msg_to_pf:
4514 ret = i40e_vc_process_vf_msg(pf,
4515 le16_to_cpu(event.desc.retval),
4516 le32_to_cpu(event.desc.cookie_high),
4517 le32_to_cpu(event.desc.cookie_low),
4518 event.msg_buf,
4519 event.msg_size);
4520 break;
4521 case i40e_aqc_opc_lldp_update_mib:
4522 dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4523 break;
4524 case i40e_aqc_opc_event_lan_overflow:
4525 dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
4526 i40e_handle_lan_overflow_event(pf, &event);
4527 break;
4528 default:
4529 dev_info(&pf->pdev->dev,
4530 "ARQ Error: Unknown event %d received\n",
4531 event.desc.opcode);
4532 break;
4533 }
4534 } while (pending && (i++ < pf->adminq_work_limit));
4535
4536 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
4537 /* re-enable Admin queue interrupt cause */
4538 val = rd32(hw, I40E_PFINT_ICR0_ENA);
4539 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
4540 wr32(hw, I40E_PFINT_ICR0_ENA, val);
4541 i40e_flush(hw);
4542
4543 kfree(event.msg_buf);
4544}
4545
4546/**
4547 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
4548 * @veb: pointer to the VEB instance
4549 *
4550 * This is a recursive function that first builds the attached VSIs then
4551 * recurses in to build the next layer of VEB. We track the connections
4552 * through our own index numbers because the seid's from the HW could
4553 * change across the reset.
4554 **/
4555static int i40e_reconstitute_veb(struct i40e_veb *veb)
4556{
4557 struct i40e_vsi *ctl_vsi = NULL;
4558 struct i40e_pf *pf = veb->pf;
4559 int v, veb_idx;
4560 int ret;
4561
4562 /* build VSI that owns this VEB, temporarily attached to base VEB */
4563 for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
4564 if (pf->vsi[v] &&
4565 pf->vsi[v]->veb_idx == veb->idx &&
4566 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
4567 ctl_vsi = pf->vsi[v];
4568 break;
4569 }
4570 }
4571 if (!ctl_vsi) {
4572 dev_info(&pf->pdev->dev,
4573 "missing owner VSI for veb_idx %d\n", veb->idx);
4574 ret = -ENOENT;
4575 goto end_reconstitute;
4576 }
4577 if (ctl_vsi != pf->vsi[pf->lan_vsi])
4578 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
4579 ret = i40e_add_vsi(ctl_vsi);
4580 if (ret) {
4581 dev_info(&pf->pdev->dev,
4582 "rebuild of owner VSI failed: %d\n", ret);
4583 goto end_reconstitute;
4584 }
4585 i40e_vsi_reset_stats(ctl_vsi);
4586
4587 /* create the VEB in the switch and move the VSI onto the VEB */
4588 ret = i40e_add_veb(veb, ctl_vsi);
4589 if (ret)
4590 goto end_reconstitute;
4591
4592 /* create the remaining VSIs attached to this VEB */
4593 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4594 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
4595 continue;
4596
4597 if (pf->vsi[v]->veb_idx == veb->idx) {
4598 struct i40e_vsi *vsi = pf->vsi[v];
4599 vsi->uplink_seid = veb->seid;
4600 ret = i40e_add_vsi(vsi);
4601 if (ret) {
4602 dev_info(&pf->pdev->dev,
4603 "rebuild of vsi_idx %d failed: %d\n",
4604 v, ret);
4605 goto end_reconstitute;
4606 }
4607 i40e_vsi_reset_stats(vsi);
4608 }
4609 }
4610
4611 /* create any VEBs attached to this VEB - RECURSION */
4612 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
4613 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
4614 pf->veb[veb_idx]->uplink_seid = veb->seid;
4615 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
4616 if (ret)
4617 break;
4618 }
4619 }
4620
4621end_reconstitute:
4622 return ret;
4623}
4624
4625/**
4626 * i40e_get_capabilities - get info about the HW
4627 * @pf: the PF struct
4628 **/
4629static int i40e_get_capabilities(struct i40e_pf *pf)
4630{
4631 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
4632 u16 data_size;
4633 int buf_len;
4634 int err;
4635
4636 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
4637 do {
4638 cap_buf = kzalloc(buf_len, GFP_KERNEL);
4639 if (!cap_buf)
4640 return -ENOMEM;
4641
4642 /* this loads the data into the hw struct for us */
4643 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
4644 &data_size,
4645 i40e_aqc_opc_list_func_capabilities,
4646 NULL);
4647 /* data loaded, buffer no longer needed */
4648 kfree(cap_buf);
4649
4650 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
4651 /* retry with a larger buffer */
4652 buf_len = data_size;
4653 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
4654 dev_info(&pf->pdev->dev,
4655 "capability discovery failed: aq=%d\n",
4656 pf->hw.aq.asq_last_status);
4657 return -ENODEV;
4658 }
4659 } while (err);
4660
7134f9ce
JB		 4661 if (pf->hw.revision_id == 0 && pf->hw.func_caps.npar_enable) {
4662 pf->hw.func_caps.num_msix_vectors += 1;
4663 pf->hw.func_caps.num_tx_qp =
4664 min_t(int, pf->hw.func_caps.num_tx_qp,
4665 I40E_MAX_NPAR_QPS);
4666 }
4667
41c445ff
JB		 4668 if (pf->hw.debug_mask & I40E_DEBUG_USER)
4669 dev_info(&pf->pdev->dev,
4670 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
4671 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
4672 pf->hw.func_caps.num_msix_vectors,
4673 pf->hw.func_caps.num_msix_vectors_vf,
4674 pf->hw.func_caps.fd_filters_guaranteed,
4675 pf->hw.func_caps.fd_filters_best_effort,
4676 pf->hw.func_caps.num_tx_qp,
4677 pf->hw.func_caps.num_vsis);
4678
7134f9ce
JB		 4679#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
4680 + pf->hw.func_caps.num_vfs)
4681 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
4682 dev_info(&pf->pdev->dev,
4683 "got num_vsis %d, setting num_vsis to %d\n",
4684 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
4685 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
4686 }
4687
41c445ff
JB		 4688 return 0;
4689}
4690
4691/**
4692 * i40e_fdir_setup - initialize the Flow Director resources
4693 * @pf: board private structure
4694 **/
4695static void i40e_fdir_setup(struct i40e_pf *pf)
4696{
4697 struct i40e_vsi *vsi;
4698 bool new_vsi = false;
4699 int err, i;
4700
958a3e3b
SN		 4701 if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED |
4702 I40E_FLAG_FDIR_ATR_ENABLED)))
41c445ff
JB		 4703 return;
4704
4705 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
4706
4707 /* find existing or make new FDIR VSI */
4708 vsi = NULL;
4709 for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
4710 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
4711 vsi = pf->vsi[i];
4712 if (!vsi) {
4713 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
4714 if (!vsi) {
4715 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
4716 pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
4717 return;
4718 }
4719 new_vsi = true;
4720 }
4721 WARN_ON(vsi->base_queue != I40E_FDIR_RING);
4722 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
4723
4724 err = i40e_vsi_setup_tx_resources(vsi);
4725 if (!err)
4726 err = i40e_vsi_setup_rx_resources(vsi);
4727 if (!err)
4728 err = i40e_vsi_configure(vsi);
4729 if (!err && new_vsi) {
4730 char int_name[IFNAMSIZ + 9];
4731 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4732 dev_driver_string(&pf->pdev->dev));
4733 err = i40e_vsi_request_irq(vsi, int_name);
4734 }
4735 if (!err)
4736 err = i40e_up_complete(vsi);
4737
4738 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4739}
4740
4741/**
4742 * i40e_fdir_teardown - release the Flow Director resources
4743 * @pf: board private structure
4744 **/
4745static void i40e_fdir_teardown(struct i40e_pf *pf)
4746{
4747 int i;
4748
4749 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
4750 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
4751 i40e_vsi_release(pf->vsi[i]);
4752 break;
4753 }
4754 }
4755}
4756
4757/**
f650a38b 4758 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 4759 * @pf: board private structure
4760 *
f650a38b
ASJ		 4761 * Close up the VFs and other things in prep for pf Reset.
4762 **/
4763static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 4764{
41c445ff
JB		 4765 struct i40e_hw *hw = &pf->hw;
4766 i40e_status ret;
4767 u32 v;
4768
4769 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
4770 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 4771 return 0;
41c445ff
JB		 4772
4773 dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
4774
37f0be6d
ASJ		 4775 if (i40e_check_asq_alive(hw))
4776 i40e_vc_notify_reset(pf);
41c445ff
JB		 4777
4778 /* quiesce the VSIs and their queues that are not already DOWN */
4779 i40e_pf_quiesce_all_vsi(pf);
4780
4781 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4782 if (pf->vsi[v])
4783 pf->vsi[v]->seid = 0;
4784 }
4785
4786 i40e_shutdown_adminq(&pf->hw);
4787
f650a38b
ASJ		 4788 /* call shutdown HMC */
4789 ret = i40e_shutdown_lan_hmc(hw);
4790 if (ret) {
4791 dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
4792 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4793 }
4794 return ret;
4795}
4796
4797/**
4798 * i40e_reset_and_rebuild - reset and rebuid using a saved config
4799 * @pf: board private structure
bc7d338f 4800 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 4801 **/
bc7d338f 4802static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b
ASJ		 4803{
4804 struct i40e_driver_version dv;
4805 struct i40e_hw *hw = &pf->hw;
4806 i40e_status ret;
4807 u32 v;
4808
41c445ff
JB		 4809 /* Now we wait for GRST to settle out.
4810 * We don't have to delete the VEBs or VSIs from the hw switch
4811 * because the reset will make them disappear.
4812 */
4813 ret = i40e_pf_reset(hw);
4814 if (ret)
4815 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
4816 pf->pfr_count++;
4817
4818 if (test_bit(__I40E_DOWN, &pf->state))
4819 goto end_core_reset;
4820 dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
4821
4822 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
4823 ret = i40e_init_adminq(&pf->hw);
4824 if (ret) {
4825 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
4826 goto end_core_reset;
4827 }
4828
4829 ret = i40e_get_capabilities(pf);
4830 if (ret) {
4831 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
4832 ret);
4833 goto end_core_reset;
4834 }
4835
41c445ff
JB		 4836 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
4837 hw->func_caps.num_rx_qp,
4838 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
4839 if (ret) {
4840 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
4841 goto end_core_reset;
4842 }
4843 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
4844 if (ret) {
4845 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
4846 goto end_core_reset;
4847 }
4848
4849 /* do basic switch setup */
bc7d338f 4850 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 4851 if (ret)
4852 goto end_core_reset;
4853
4854 /* Rebuild the VSIs and VEBs that existed before reset.
4855 * They are still in our local switch element arrays, so only
4856 * need to rebuild the switch model in the HW.
4857 *
4858 * If there were VEBs but the reconstitution failed, we'll try
4859 * try to recover minimal use by getting the basic PF VSI working.
4860 */
4861 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
4862 dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
4863 /* find the one VEB connected to the MAC, and find orphans */
4864 for (v = 0; v < I40E_MAX_VEB; v++) {
4865 if (!pf->veb[v])
4866 continue;
4867
4868 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
4869 pf->veb[v]->uplink_seid == 0) {
4870 ret = i40e_reconstitute_veb(pf->veb[v]);
4871
4872 if (!ret)
4873 continue;
4874
4875 /* If Main VEB failed, we're in deep doodoo,
4876 * so give up rebuilding the switch and set up
4877 * for minimal rebuild of PF VSI.
4878 * If orphan failed, we'll report the error
4879 * but try to keep going.
4880 */
4881 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
4882 dev_info(&pf->pdev->dev,
4883 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
4884 ret);
4885 pf->vsi[pf->lan_vsi]->uplink_seid
4886 = pf->mac_seid;
4887 break;
4888 } else if (pf->veb[v]->uplink_seid == 0) {
4889 dev_info(&pf->pdev->dev,
4890 "rebuild of orphan VEB failed: %d\n",
4891 ret);
4892 }
4893 }
4894 }
4895 }
4896
4897 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
4898 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
4899 /* no VEB, so rebuild only the Main VSI */
4900 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
4901 if (ret) {
4902 dev_info(&pf->pdev->dev,
4903 "rebuild of Main VSI failed: %d\n", ret);
4904 goto end_core_reset;
4905 }
4906 }
4907
4908 /* reinit the misc interrupt */
4909 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4910 ret = i40e_setup_misc_vector(pf);
4911
4912 /* restart the VSIs that were rebuilt and running before the reset */
4913 i40e_pf_unquiesce_all_vsi(pf);
4914
4915 /* tell the firmware that we're starting */
4916 dv.major_version = DRV_VERSION_MAJOR;
4917 dv.minor_version = DRV_VERSION_MINOR;
4918 dv.build_version = DRV_VERSION_BUILD;
4919 dv.subbuild_version = 0;
4920 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
4921
4922 dev_info(&pf->pdev->dev, "PF reset done\n");
4923
4924end_core_reset:
4925 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
4926}
4927
f650a38b
ASJ		 4928/**
4929 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
4930 * @pf: board private structure
4931 *
4932 * Close up the VFs and other things in prep for a Core Reset,
4933 * then get ready to rebuild the world.
4934 **/
4935static void i40e_handle_reset_warning(struct i40e_pf *pf)
4936{
4937 i40e_status ret;
4938
4939 ret = i40e_prep_for_reset(pf);
4940 if (!ret)
bc7d338f 4941 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 4942}
4943
41c445ff
JB		 4944/**
4945 * i40e_handle_mdd_event
4946 * @pf: pointer to the pf structure
4947 *
4948 * Called from the MDD irq handler to identify possibly malicious vfs
4949 **/
4950static void i40e_handle_mdd_event(struct i40e_pf *pf)
4951{
4952 struct i40e_hw *hw = &pf->hw;
4953 bool mdd_detected = false;
4954 struct i40e_vf *vf;
4955 u32 reg;
4956 int i;
4957
4958 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
4959 return;
4960
4961 /* find what triggered the MDD event */
4962 reg = rd32(hw, I40E_GL_MDET_TX);
4963 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4964 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
4965 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
4966 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
4967 >> I40E_GL_MDET_TX_EVENT_SHIFT;
4968 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
4969 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
4970 dev_info(&pf->pdev->dev,
4971 "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
4972 event, queue, func);
4973 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
4974 mdd_detected = true;
4975 }
4976 reg = rd32(hw, I40E_GL_MDET_RX);
4977 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4978 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
4979 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
4980 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
4981 >> I40E_GL_MDET_RX_EVENT_SHIFT;
4982 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
4983 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
4984 dev_info(&pf->pdev->dev,
4985 "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
4986 event, queue, func);
4987 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
4988 mdd_detected = true;
4989 }
4990
4991 /* see if one of the VFs needs its hand slapped */
4992 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
4993 vf = &(pf->vf[i]);
4994 reg = rd32(hw, I40E_VP_MDET_TX(i));
4995 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
4996 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
4997 vf->num_mdd_events++;
4998 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
4999 }
5000
5001 reg = rd32(hw, I40E_VP_MDET_RX(i));
5002 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5003 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5004 vf->num_mdd_events++;
5005 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5006 }
5007
5008 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5009 dev_info(&pf->pdev->dev,
5010 "Too many MDD events on VF %d, disabled\n", i);
5011 dev_info(&pf->pdev->dev,
5012 "Use PF Control I/F to re-enable the VF\n");
5013 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5014 }
5015 }
5016
5017 /* re-enable mdd interrupt cause */
5018 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5019 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5020 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5021 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5022 i40e_flush(hw);
5023}
5024
a1c9a9d9
JK		 5025#ifdef CONFIG_I40E_VXLAN
5026/**
5027 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5028 * @pf: board private structure
5029 **/
5030static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5031{
5032 const int vxlan_hdr_qwords = 4;
5033 struct i40e_hw *hw = &pf->hw;
5034 i40e_status ret;
5035 u8 filter_index;
5036 __be16 port;
5037 int i;
5038
5039 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5040 return;
5041
5042 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5043
5044 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5045 if (pf->pending_vxlan_bitmap & (1 << i)) {
5046 pf->pending_vxlan_bitmap &= ~(1 << i);
5047 port = pf->vxlan_ports[i];
5048 ret = port ?
5049 i40e_aq_add_udp_tunnel(hw, ntohs(port),
5050 vxlan_hdr_qwords,
5051 I40E_AQC_TUNNEL_TYPE_VXLAN,
5052 &filter_index, NULL)
5053 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5054
5055 if (ret) {
5056 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5057 port ? "adding" : "deleting",
5058 ntohs(port), port ? i : i);
5059
5060 pf->vxlan_ports[i] = 0;
5061 } else {
5062 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5063 port ? "Added" : "Deleted",
5064 ntohs(port), port ? i : filter_index);
5065 }
5066 }
5067 }
5068}
5069
5070#endif
41c445ff
JB		 5071/**
5072 * i40e_service_task - Run the driver's async subtasks
5073 * @work: pointer to work_struct containing our data
5074 **/
5075static void i40e_service_task(struct work_struct *work)
5076{
5077 struct i40e_pf *pf = container_of(work,
5078 struct i40e_pf,
5079 service_task);
5080 unsigned long start_time = jiffies;
5081
5082 i40e_reset_subtask(pf);
5083 i40e_handle_mdd_event(pf);
5084 i40e_vc_process_vflr_event(pf);
5085 i40e_watchdog_subtask(pf);
5086 i40e_fdir_reinit_subtask(pf);
5087 i40e_check_hang_subtask(pf);
5088 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5089#ifdef CONFIG_I40E_VXLAN
5090 i40e_sync_vxlan_filters_subtask(pf);
5091#endif
41c445ff
JB		 5092 i40e_clean_adminq_subtask(pf);
5093
5094 i40e_service_event_complete(pf);
5095
5096 /* If the tasks have taken longer than one timer cycle or there
5097 * is more work to be done, reschedule the service task now
5098 * rather than wait for the timer to tick again.
5099 */
5100 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5101 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5102 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5103 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5104 i40e_service_event_schedule(pf);
5105}
5106
5107/**
5108 * i40e_service_timer - timer callback
5109 * @data: pointer to PF struct
5110 **/
5111static void i40e_service_timer(unsigned long data)
5112{
5113 struct i40e_pf *pf = (struct i40e_pf *)data;
5114
5115 mod_timer(&pf->service_timer,
5116 round_jiffies(jiffies + pf->service_timer_period));
5117 i40e_service_event_schedule(pf);
5118}
5119
5120/**
5121 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5122 * @vsi: the VSI being configured
5123 **/
5124static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5125{
5126 struct i40e_pf *pf = vsi->back;
5127
5128 switch (vsi->type) {
5129 case I40E_VSI_MAIN:
5130 vsi->alloc_queue_pairs = pf->num_lan_qps;
5131 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5132 I40E_REQ_DESCRIPTOR_MULTIPLE);
5133 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5134 vsi->num_q_vectors = pf->num_lan_msix;
5135 else
5136 vsi->num_q_vectors = 1;
5137
5138 break;
5139
5140 case I40E_VSI_FDIR:
5141 vsi->alloc_queue_pairs = 1;
5142 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5143 I40E_REQ_DESCRIPTOR_MULTIPLE);
5144 vsi->num_q_vectors = 1;
5145 break;
5146
5147 case I40E_VSI_VMDQ2:
5148 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5149 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5150 I40E_REQ_DESCRIPTOR_MULTIPLE);
5151 vsi->num_q_vectors = pf->num_vmdq_msix;
5152 break;
5153
5154 case I40E_VSI_SRIOV:
5155 vsi->alloc_queue_pairs = pf->num_vf_qps;
5156 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5157 I40E_REQ_DESCRIPTOR_MULTIPLE);
5158 break;
5159
5160 default:
5161 WARN_ON(1);
5162 return -ENODATA;
5163 }
5164
5165 return 0;
5166}
5167
f650a38b
ASJ		 5168/**
5169 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5170 * @type: VSI pointer
bc7d338f 5171 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5172 *
5173 * On error: returns error code (negative)
5174 * On success: returns 0
5175 **/
bc7d338f 5176static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5177{
5178 int size;
5179 int ret = 0;
5180
ac6c5e3d 5181 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5182 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5183 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5184 if (!vsi->tx_rings)
5185 return -ENOMEM;
f650a38b
ASJ		 5186 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5187
bc7d338f
ASJ		 5188 if (alloc_qvectors) {
5189 /* allocate memory for q_vector pointers */
5190 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5191 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5192 if (!vsi->q_vectors) {
5193 ret = -ENOMEM;
5194 goto err_vectors;
5195 }
f650a38b
ASJ		 5196 }
5197 return ret;
5198
5199err_vectors:
5200 kfree(vsi->tx_rings);
5201 return ret;
5202}
5203
41c445ff
JB		 5204/**
5205 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5206 * @pf: board private structure
5207 * @type: type of VSI
5208 *
5209 * On error: returns error code (negative)
5210 * On success: returns vsi index in PF (positive)
5211 **/
5212static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5213{
5214 int ret = -ENODEV;
5215 struct i40e_vsi *vsi;
5216 int vsi_idx;
5217 int i;
5218
5219 /* Need to protect the allocation of the VSIs at the PF level */
5220 mutex_lock(&pf->switch_mutex);
5221
5222 /* VSI list may be fragmented if VSI creation/destruction has
5223 * been happening. We can afford to do a quick scan to look
5224 * for any free VSIs in the list.
5225 *
5226 * find next empty vsi slot, looping back around if necessary
5227 */
5228 i = pf->next_vsi;
5229 while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
5230 i++;
5231 if (i >= pf->hw.func_caps.num_vsis) {
5232 i = 0;
5233 while (i < pf->next_vsi && pf->vsi[i])
5234 i++;
5235 }
5236
5237 if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
5238 vsi_idx = i; /* Found one! */
5239 } else {
5240 ret = -ENODEV;
493fb300 5241 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5242 }
5243 pf->next_vsi = ++i;
5244
5245 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5246 if (!vsi) {
5247 ret = -ENOMEM;
493fb300 5248 goto unlock_pf;
41c445ff
JB		 5249 }
5250 vsi->type = type;
5251 vsi->back = pf;
5252 set_bit(__I40E_DOWN, &vsi->state);
5253 vsi->flags = 0;
5254 vsi->idx = vsi_idx;
5255 vsi->rx_itr_setting = pf->rx_itr_default;
5256 vsi->tx_itr_setting = pf->tx_itr_default;
5257 vsi->netdev_registered = false;
5258 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5259 INIT_LIST_HEAD(&vsi->mac_filter_list);
5260
9f65e15b
AD		 5261 ret = i40e_set_num_rings_in_vsi(vsi);
5262 if (ret)
5263 goto err_rings;
5264
bc7d338f 5265 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 5266 if (ret)
9f65e15b 5267 goto err_rings;
493fb300 5268
41c445ff
JB		 5269 /* Setup default MSIX irq handler for VSI */
5270 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
5271
5272 pf->vsi[vsi_idx] = vsi;
5273 ret = vsi_idx;
493fb300
AD		 5274 goto unlock_pf;
5275
9f65e15b 5276err_rings:
493fb300
AD		 5277 pf->next_vsi = i - 1;
5278 kfree(vsi);
5279unlock_pf:
41c445ff
JB		 5280 mutex_unlock(&pf->switch_mutex);
5281 return ret;
5282}
5283
f650a38b
ASJ		 5284/**
5285 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
5286 * @type: VSI pointer
bc7d338f 5287 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 5288 *
5289 * On error: returns error code (negative)
5290 * On success: returns 0
5291 **/
bc7d338f 5292static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 5293{
5294 /* free the ring and vector containers */
bc7d338f
ASJ		 5295 if (free_qvectors) {
5296 kfree(vsi->q_vectors);
5297 vsi->q_vectors = NULL;
5298 }
f650a38b
ASJ		 5299 kfree(vsi->tx_rings);
5300 vsi->tx_rings = NULL;
5301 vsi->rx_rings = NULL;
5302}
5303
41c445ff
JB		 5304/**
5305 * i40e_vsi_clear - Deallocate the VSI provided
5306 * @vsi: the VSI being un-configured
5307 **/
5308static int i40e_vsi_clear(struct i40e_vsi *vsi)
5309{
5310 struct i40e_pf *pf;
5311
5312 if (!vsi)
5313 return 0;
5314
5315 if (!vsi->back)
5316 goto free_vsi;
5317 pf = vsi->back;
5318
5319 mutex_lock(&pf->switch_mutex);
5320 if (!pf->vsi[vsi->idx]) {
5321 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
5322 vsi->idx, vsi->idx, vsi, vsi->type);
5323 goto unlock_vsi;
5324 }
5325
5326 if (pf->vsi[vsi->idx] != vsi) {
5327 dev_err(&pf->pdev->dev,
5328 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
5329 pf->vsi[vsi->idx]->idx,
5330 pf->vsi[vsi->idx],
5331 pf->vsi[vsi->idx]->type,
5332 vsi->idx, vsi, vsi->type);
5333 goto unlock_vsi;
5334 }
5335
5336 /* updates the pf for this cleared vsi */
5337 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
5338 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
5339
bc7d338f 5340 i40e_vsi_free_arrays(vsi, true);
493fb300 5341
41c445ff
JB		 5342 pf->vsi[vsi->idx] = NULL;
5343 if (vsi->idx < pf->next_vsi)
5344 pf->next_vsi = vsi->idx;
5345
5346unlock_vsi:
5347 mutex_unlock(&pf->switch_mutex);
5348free_vsi:
5349 kfree(vsi);
5350
5351 return 0;
5352}
5353
9f65e15b
AD		 5354/**
5355 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
5356 * @vsi: the VSI being cleaned
5357 **/
be1d5eea 5358static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 5359{
5360 int i;
5361
be1d5eea 5362 if (vsi->tx_rings[0]) {
d7397644 5363 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 5364 kfree_rcu(vsi->tx_rings[i], rcu);
5365 vsi->tx_rings[i] = NULL;
5366 vsi->rx_rings[i] = NULL;
5367 }
be1d5eea 5368 }
9f65e15b
AD		 5369}
5370
41c445ff
JB		 5371/**
5372 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
5373 * @vsi: the VSI being configured
5374 **/
5375static int i40e_alloc_rings(struct i40e_vsi *vsi)
5376{
5377 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5378 int i;
5379
41c445ff 5380 /* Set basic values in the rings to be used later during open() */
d7397644 5381 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
9f65e15b
AD		 5382 struct i40e_ring *tx_ring;
5383 struct i40e_ring *rx_ring;
5384
ac6c5e3d 5385 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 5386 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
5387 if (!tx_ring)
5388 goto err_out;
41c445ff
JB		 5389
5390 tx_ring->queue_index = i;
5391 tx_ring->reg_idx = vsi->base_queue + i;
5392 tx_ring->ring_active = false;
5393 tx_ring->vsi = vsi;
5394 tx_ring->netdev = vsi->netdev;
5395 tx_ring->dev = &pf->pdev->dev;
5396 tx_ring->count = vsi->num_desc;
5397 tx_ring->size = 0;
5398 tx_ring->dcb_tc = 0;
9f65e15b 5399 vsi->tx_rings[i] = tx_ring;
41c445ff 5400
9f65e15b 5401 rx_ring = &tx_ring[1];
41c445ff
JB		 5402 rx_ring->queue_index = i;
5403 rx_ring->reg_idx = vsi->base_queue + i;
5404 rx_ring->ring_active = false;
5405 rx_ring->vsi = vsi;
5406 rx_ring->netdev = vsi->netdev;
5407 rx_ring->dev = &pf->pdev->dev;
5408 rx_ring->count = vsi->num_desc;
5409 rx_ring->size = 0;
5410 rx_ring->dcb_tc = 0;
5411 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
5412 set_ring_16byte_desc_enabled(rx_ring);
5413 else
5414 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 5415 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 5416 }
5417
5418 return 0;
9f65e15b
AD		 5419
5420err_out:
5421 i40e_vsi_clear_rings(vsi);
5422 return -ENOMEM;
41c445ff
JB		 5423}
5424
5425/**
5426 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
5427 * @pf: board private structure
5428 * @vectors: the number of MSI-X vectors to request
5429 *
5430 * Returns the number of vectors reserved, or error
5431 **/
5432static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
5433{
5434 int err = 0;
5435
5436 pf->num_msix_entries = 0;
5437 while (vectors >= I40E_MIN_MSIX) {
5438 err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
5439 if (err == 0) {
5440 /* good to go */
5441 pf->num_msix_entries = vectors;
5442 break;
5443 } else if (err < 0) {
5444 /* total failure */
5445 dev_info(&pf->pdev->dev,
5446 "MSI-X vector reservation failed: %d\n", err);
5447 vectors = 0;
5448 break;
5449 } else {
5450 /* err > 0 is the hint for retry */
5451 dev_info(&pf->pdev->dev,
5452 "MSI-X vectors wanted %d, retrying with %d\n",
5453 vectors, err);
5454 vectors = err;
5455 }
5456 }
5457
5458 if (vectors > 0 && vectors < I40E_MIN_MSIX) {
5459 dev_info(&pf->pdev->dev,
5460 "Couldn't get enough vectors, only %d available\n",
5461 vectors);
5462 vectors = 0;
5463 }
5464
5465 return vectors;
5466}
5467
5468/**
5469 * i40e_init_msix - Setup the MSIX capability
5470 * @pf: board private structure
5471 *
5472 * Work with the OS to set up the MSIX vectors needed.
5473 *
5474 * Returns 0 on success, negative on failure
5475 **/
5476static int i40e_init_msix(struct i40e_pf *pf)
5477{
5478 i40e_status err = 0;
5479 struct i40e_hw *hw = &pf->hw;
5480 int v_budget, i;
5481 int vec;
5482
5483 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
5484 return -ENODEV;
5485
5486 /* The number of vectors we'll request will be comprised of:
5487 * - Add 1 for "other" cause for Admin Queue events, etc.
5488 * - The number of LAN queue pairs
f8ff1464
ASJ		 5489 * - Queues being used for RSS.
5490 * We don't need as many as max_rss_size vectors.
5491 * use rss_size instead in the calculation since that
5492 * is governed by number of cpus in the system.
5493 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 5494 * - The number of VMDq pairs
5495 * Once we count this up, try the request.
5496 *
5497 * If we can't get what we want, we'll simplify to nearly nothing
5498 * and try again. If that still fails, we punt.
5499 */
f8ff1464 5500 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 5501 pf->num_vmdq_msix = pf->num_vmdq_qps;
5502 v_budget = 1 + pf->num_lan_msix;
5503 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
5504 if (pf->flags & I40E_FLAG_FDIR_ENABLED)
5505 v_budget++;
5506
5507 /* Scale down if necessary, and the rings will share vectors */
5508 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
5509
5510 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
5511 GFP_KERNEL);
5512 if (!pf->msix_entries)
5513 return -ENOMEM;
5514
5515 for (i = 0; i < v_budget; i++)
5516 pf->msix_entries[i].entry = i;
5517 vec = i40e_reserve_msix_vectors(pf, v_budget);
5518 if (vec < I40E_MIN_MSIX) {
5519 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
5520 kfree(pf->msix_entries);
5521 pf->msix_entries = NULL;
5522 return -ENODEV;
5523
5524 } else if (vec == I40E_MIN_MSIX) {
5525 /* Adjust for minimal MSIX use */
5526 dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
5527 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
5528 pf->num_vmdq_vsis = 0;
5529 pf->num_vmdq_qps = 0;
5530 pf->num_vmdq_msix = 0;
5531 pf->num_lan_qps = 1;
5532 pf->num_lan_msix = 1;
5533
5534 } else if (vec != v_budget) {
5535 /* Scale vector usage down */
5536 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
5537 vec--; /* reserve the misc vector */
5538
5539 /* partition out the remaining vectors */
5540 switch (vec) {
5541 case 2:
5542 pf->num_vmdq_vsis = 1;
5543 pf->num_lan_msix = 1;
5544 break;
5545 case 3:
5546 pf->num_vmdq_vsis = 1;
5547 pf->num_lan_msix = 2;
5548 break;
5549 default:
5550 pf->num_lan_msix = min_t(int, (vec / 2),
5551 pf->num_lan_qps);
5552 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
5553 I40E_DEFAULT_NUM_VMDQ_VSI);
5554 break;
5555 }
5556 }
5557
5558 return err;
5559}
5560
493fb300
AD		 5561/**
5562 * i40e_alloc_q_vector - Allocate memory for a single interrupt vector
5563 * @vsi: the VSI being configured
5564 * @v_idx: index of the vector in the vsi struct
5565 *
5566 * We allocate one q_vector. If allocation fails we return -ENOMEM.
5567 **/
5568static int i40e_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
5569{
5570 struct i40e_q_vector *q_vector;
5571
5572 /* allocate q_vector */
5573 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
5574 if (!q_vector)
5575 return -ENOMEM;
5576
5577 q_vector->vsi = vsi;
5578 q_vector->v_idx = v_idx;
5579 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
5580 if (vsi->netdev)
5581 netif_napi_add(vsi->netdev, &q_vector->napi,
5582 i40e_napi_poll, vsi->work_limit);
5583
cd0b6fa6
AD		 5584 q_vector->rx.latency_range = I40E_LOW_LATENCY;
5585 q_vector->tx.latency_range = I40E_LOW_LATENCY;
5586
493fb300
AD		 5587 /* tie q_vector and vsi together */
5588 vsi->q_vectors[v_idx] = q_vector;
5589
5590 return 0;
5591}
5592
41c445ff
JB		 5593/**
5594 * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
5595 * @vsi: the VSI being configured
5596 *
5597 * We allocate one q_vector per queue interrupt. If allocation fails we
5598 * return -ENOMEM.
5599 **/
5600static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
5601{
5602 struct i40e_pf *pf = vsi->back;
5603 int v_idx, num_q_vectors;
493fb300 5604 int err;
41c445ff
JB		 5605
5606 /* if not MSIX, give the one vector only to the LAN VSI */
5607 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5608 num_q_vectors = vsi->num_q_vectors;
5609 else if (vsi == pf->vsi[pf->lan_vsi])
5610 num_q_vectors = 1;
5611 else
5612 return -EINVAL;
5613
41c445ff 5614 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
493fb300
AD		 5615 err = i40e_alloc_q_vector(vsi, v_idx);
5616 if (err)
5617 goto err_out;
41c445ff
JB		 5618 }
5619
5620 return 0;
493fb300
AD		 5621
5622err_out:
5623 while (v_idx--)
5624 i40e_free_q_vector(vsi, v_idx);
5625
5626 return err;
41c445ff
JB		 5627}
5628
5629/**
5630 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
5631 * @pf: board private structure to initialize
5632 **/
5633static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
5634{
5635 int err = 0;
5636
5637 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
5638 err = i40e_init_msix(pf);
5639 if (err) {
958a3e3b
SN		 5640 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
5641 I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 5642 I40E_FLAG_DCB_ENABLED |
5643 I40E_FLAG_SRIOV_ENABLED |
5644 I40E_FLAG_FDIR_ENABLED |
5645 I40E_FLAG_FDIR_ATR_ENABLED |
5646 I40E_FLAG_VMDQ_ENABLED);
5647
5648 /* rework the queue expectations without MSIX */
5649 i40e_determine_queue_usage(pf);
5650 }
5651 }
5652
5653 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
5654 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
958a3e3b 5655 dev_info(&pf->pdev->dev, "MSIX not available, trying MSI\n");
41c445ff
JB		 5656 err = pci_enable_msi(pf->pdev);
5657 if (err) {
958a3e3b 5658 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 5659 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
5660 }
5661 }
5662
958a3e3b
SN		 5663 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
5664 dev_info(&pf->pdev->dev, "MSIX and MSI not available, falling back to Legacy IRQ\n");
5665
41c445ff
JB		 5666 /* track first vector for misc interrupts */
5667 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
5668}
5669
5670/**
5671 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
5672 * @pf: board private structure
5673 *
5674 * This sets up the handler for MSIX 0, which is used to manage the
5675 * non-queue interrupts, e.g. AdminQ and errors. This is not used
5676 * when in MSI or Legacy interrupt mode.
5677 **/
5678static int i40e_setup_misc_vector(struct i40e_pf *pf)
5679{
5680 struct i40e_hw *hw = &pf->hw;
5681 int err = 0;
5682
5683 /* Only request the irq if this is the first time through, and
5684 * not when we're rebuilding after a Reset
5685 */
5686 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
5687 err = request_irq(pf->msix_entries[0].vector,
5688 i40e_intr, 0, pf->misc_int_name, pf);
5689 if (err) {
5690 dev_info(&pf->pdev->dev,
5691 "request_irq for msix_misc failed: %d\n", err);
5692 return -EFAULT;
5693 }
5694 }
5695
5696 i40e_enable_misc_int_causes(hw);
5697
5698 /* associate no queues to the misc vector */
5699 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
5700 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
5701
5702 i40e_flush(hw);
5703
5704 i40e_irq_dynamic_enable_icr0(pf);
5705
5706 return err;
5707}
5708
5709/**
5710 * i40e_config_rss - Prepare for RSS if used
5711 * @pf: board private structure
5712 **/
5713static int i40e_config_rss(struct i40e_pf *pf)
5714{
41c445ff
JB		 5715 /* Set of random keys generated using kernel random number generator */
5716 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
5717 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
5718 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
5719 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 5720 struct i40e_hw *hw = &pf->hw;
5721 u32 lut = 0;
5722 int i, j;
5723 u64 hena;
41c445ff
JB		 5724
5725 /* Fill out hash function seed */
5726 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5727 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
5728
5729 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
5730 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
5731 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 5732 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 5733 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
5734 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
5735
5736 /* Populate the LUT with max no. of queues in round robin fashion */
5737 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
5738
5739 /* The assumption is that lan qp count will be the highest
5740 * qp count for any PF VSI that needs RSS.
5741 * If multiple VSIs need RSS support, all the qp counts
5742 * for those VSIs should be a power of 2 for RSS to work.
5743 * If LAN VSI is the only consumer for RSS then this requirement
5744 * is not necessary.
5745 */
5746 if (j == pf->rss_size)
5747 j = 0;
5748 /* lut = 4-byte sliding window of 4 lut entries */
5749 lut = (lut << 8) | (j &
5750 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
5751 /* On i = 3, we have 4 entries in lut; write to the register */
5752 if ((i & 3) == 3)
5753 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
5754 }
5755 i40e_flush(hw);
5756
5757 return 0;
5758}
5759
f8ff1464
ASJ		 5760/**
5761 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
5762 * @pf: board private structure
5763 * @queue_count: the requested queue count for rss.
5764 *
5765 * returns 0 if rss is not enabled, if enabled returns the final rss queue
5766 * count which may be different from the requested queue count.
5767 **/
5768int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
5769{
5770 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
5771 return 0;
5772
5773 queue_count = min_t(int, queue_count, pf->rss_size_max);
5774 queue_count = rounddown_pow_of_two(queue_count);
5775
5776 if (queue_count != pf->rss_size) {
5777 if (pf->queues_left < (queue_count - pf->rss_size)) {
5778 dev_info(&pf->pdev->dev,
5779 "Not enough queues to do RSS on %d queues: remaining queues %d\n",
5780 queue_count, pf->queues_left);
5781 return pf->rss_size;
5782 }
5783 i40e_prep_for_reset(pf);
5784
5785 pf->num_lan_qps += (queue_count - pf->rss_size);
5786 pf->queues_left -= (queue_count - pf->rss_size);
5787 pf->rss_size = queue_count;
5788
5789 i40e_reset_and_rebuild(pf, true);
5790 i40e_config_rss(pf);
5791 }
5792 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
5793 return pf->rss_size;
5794}
5795
41c445ff
JB		 5796/**
5797 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
5798 * @pf: board private structure to initialize
5799 *
5800 * i40e_sw_init initializes the Adapter private data structure.
5801 * Fields are initialized based on PCI device information and
5802 * OS network device settings (MTU size).
5803 **/
5804static int i40e_sw_init(struct i40e_pf *pf)
5805{
5806 int err = 0;
5807 int size;
5808
5809 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
5810 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 5811 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 5812 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
5813 if (I40E_DEBUG_USER & debug)
5814 pf->hw.debug_mask = debug;
5815 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
5816 I40E_DEFAULT_MSG_ENABLE);
5817 }
5818
5819 /* Set default capability flags */
5820 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
5821 I40E_FLAG_MSI_ENABLED |
5822 I40E_FLAG_MSIX_ENABLED |
5823 I40E_FLAG_RX_PS_ENABLED |
41c445ff
JB		 5824 I40E_FLAG_RX_1BUF_ENABLED;
5825
7134f9ce
JB		 5826 /* Depending on PF configurations, it is possible that the RSS
5827 * maximum might end up larger than the available queues
5828 */
41c445ff 5829 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 5830 pf->rss_size_max = min_t(int, pf->rss_size_max,
5831 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 5832 if (pf->hw.func_caps.rss) {
5833 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 5834 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
41c445ff
JB		 5835 } else {
5836 pf->rss_size = 1;
5837 }
5838
5839 if (pf->hw.func_caps.dcb)
5840 pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
5841 else
5842 pf->num_tc_qps = 0;
5843
5844 if (pf->hw.func_caps.fd) {
5845 /* FW/NVM is not yet fixed in this regard */
5846 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
5847 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
5848 pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
5849 dev_info(&pf->pdev->dev,
5850 "Flow Director ATR mode Enabled\n");
5851 pf->flags |= I40E_FLAG_FDIR_ENABLED;
5852 dev_info(&pf->pdev->dev,
5853 "Flow Director Side Band mode Enabled\n");
5854 pf->fdir_pf_filter_count =
5855 pf->hw.func_caps.fd_filters_guaranteed;
5856 }
5857 } else {
5858 pf->fdir_pf_filter_count = 0;
5859 }
5860
5861 if (pf->hw.func_caps.vmdq) {
5862 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
5863 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
5864 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
5865 }
5866
5867 /* MFP mode enabled */
5868 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
5869 pf->flags |= I40E_FLAG_MFP_ENABLED;
5870 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
5871 }
5872
5873#ifdef CONFIG_PCI_IOV
5874 if (pf->hw.func_caps.num_vfs) {
5875 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
5876 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
5877 pf->num_req_vfs = min_t(int,
5878 pf->hw.func_caps.num_vfs,
5879 I40E_MAX_VF_COUNT);
4a38d09c
ASJ		 5880 dev_info(&pf->pdev->dev,
5881 "Number of VFs being requested for PF[%d] = %d\n",
5882 pf->hw.pf_id, pf->num_req_vfs);
41c445ff
JB		 5883 }
5884#endif /* CONFIG_PCI_IOV */
5885 pf->eeprom_version = 0xDEAD;
5886 pf->lan_veb = I40E_NO_VEB;
5887 pf->lan_vsi = I40E_NO_VSI;
5888
5889 /* set up queue assignment tracking */
5890 size = sizeof(struct i40e_lump_tracking)
5891 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
5892 pf->qp_pile = kzalloc(size, GFP_KERNEL);
5893 if (!pf->qp_pile) {
5894 err = -ENOMEM;
5895 goto sw_init_done;
5896 }
5897 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
5898 pf->qp_pile->search_hint = 0;
5899
5900 /* set up vector assignment tracking */
5901 size = sizeof(struct i40e_lump_tracking)
5902 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
5903 pf->irq_pile = kzalloc(size, GFP_KERNEL);
5904 if (!pf->irq_pile) {
5905 kfree(pf->qp_pile);
5906 err = -ENOMEM;
5907 goto sw_init_done;
5908 }
5909 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
5910 pf->irq_pile->search_hint = 0;
5911
5912 mutex_init(&pf->switch_mutex);
5913
5914sw_init_done:
5915 return err;
5916}
5917
5918/**
5919 * i40e_set_features - set the netdev feature flags
5920 * @netdev: ptr to the netdev being adjusted
5921 * @features: the feature set that the stack is suggesting
5922 **/
5923static int i40e_set_features(struct net_device *netdev,
5924 netdev_features_t features)
5925{
5926 struct i40e_netdev_priv *np = netdev_priv(netdev);
5927 struct i40e_vsi *vsi = np->vsi;
5928
5929 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5930 i40e_vlan_stripping_enable(vsi);
5931 else
5932 i40e_vlan_stripping_disable(vsi);
5933
5934 return 0;
5935}
5936
a1c9a9d9
JK		 5937#ifdef CONFIG_I40E_VXLAN
5938/**
5939 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
5940 * @pf: board private structure
5941 * @port: The UDP port to look up
5942 *
5943 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
5944 **/
5945static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
5946{
5947 u8 i;
5948
5949 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5950 if (pf->vxlan_ports[i] == port)
5951 return i;
5952 }
5953
5954 return i;
5955}
5956
5957/**
5958 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
5959 * @netdev: This physical port's netdev
5960 * @sa_family: Socket Family that VXLAN is notifying us about
5961 * @port: New UDP port number that VXLAN started listening to
5962 **/
5963static void i40e_add_vxlan_port(struct net_device *netdev,
5964 sa_family_t sa_family, __be16 port)
5965{
5966 struct i40e_netdev_priv *np = netdev_priv(netdev);
5967 struct i40e_vsi *vsi = np->vsi;
5968 struct i40e_pf *pf = vsi->back;
5969 u8 next_idx;
5970 u8 idx;
5971
5972 if (sa_family == AF_INET6)
5973 return;
5974
5975 idx = i40e_get_vxlan_port_idx(pf, port);
5976
5977 /* Check if port already exists */
5978 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5979 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
5980 return;
5981 }
5982
5983 /* Now check if there is space to add the new port */
5984 next_idx = i40e_get_vxlan_port_idx(pf, 0);
5985
5986 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
5987 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
5988 ntohs(port));
5989 return;
5990 }
5991
5992 /* New port: add it and mark its index in the bitmap */
5993 pf->vxlan_ports[next_idx] = port;
5994 pf->pending_vxlan_bitmap |= (1 << next_idx);
5995
5996 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
5997}
5998
5999/**
6000 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6001 * @netdev: This physical port's netdev
6002 * @sa_family: Socket Family that VXLAN is notifying us about
6003 * @port: UDP port number that VXLAN stopped listening to
6004 **/
6005static void i40e_del_vxlan_port(struct net_device *netdev,
6006 sa_family_t sa_family, __be16 port)
6007{
6008 struct i40e_netdev_priv *np = netdev_priv(netdev);
6009 struct i40e_vsi *vsi = np->vsi;
6010 struct i40e_pf *pf = vsi->back;
6011 u8 idx;
6012
6013 if (sa_family == AF_INET6)
6014 return;
6015
6016 idx = i40e_get_vxlan_port_idx(pf, port);
6017
6018 /* Check if port already exists */
6019 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6020 /* if port exists, set it to 0 (mark for deletion)
6021 * and make it pending
6022 */
6023 pf->vxlan_ports[idx] = 0;
6024
6025 pf->pending_vxlan_bitmap |= (1 << idx);
6026
6027 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6028 } else {
6029 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6030 ntohs(port));
6031 }
6032}
6033
6034#endif
41c445ff
JB		 6035static const struct net_device_ops i40e_netdev_ops = {
6036 .ndo_open = i40e_open,
6037 .ndo_stop = i40e_close,
6038 .ndo_start_xmit = i40e_lan_xmit_frame,
6039 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6040 .ndo_set_rx_mode = i40e_set_rx_mode,
6041 .ndo_validate_addr = eth_validate_addr,
6042 .ndo_set_mac_address = i40e_set_mac,
6043 .ndo_change_mtu = i40e_change_mtu,
6044 .ndo_tx_timeout = i40e_tx_timeout,
6045 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6046 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6047#ifdef CONFIG_NET_POLL_CONTROLLER
6048 .ndo_poll_controller = i40e_netpoll,
6049#endif
6050 .ndo_setup_tc = i40e_setup_tc,
6051 .ndo_set_features = i40e_set_features,
6052 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6053 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
6054 .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
6055 .ndo_get_vf_config = i40e_ndo_get_vf_config,
a1c9a9d9
JK		 6056#ifdef CONFIG_I40E_VXLAN
6057 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6058 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6059#endif
41c445ff
JB		 6060};
6061
6062/**
6063 * i40e_config_netdev - Setup the netdev flags
6064 * @vsi: the VSI being configured
6065 *
6066 * Returns 0 on success, negative value on failure
6067 **/
6068static int i40e_config_netdev(struct i40e_vsi *vsi)
6069{
6070 struct i40e_pf *pf = vsi->back;
6071 struct i40e_hw *hw = &pf->hw;
6072 struct i40e_netdev_priv *np;
6073 struct net_device *netdev;
6074 u8 mac_addr[ETH_ALEN];
6075 int etherdev_size;
6076
6077 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6078 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6079 if (!netdev)
6080 return -ENOMEM;
6081
6082 vsi->netdev = netdev;
6083 np = netdev_priv(netdev);
6084 np->vsi = vsi;
6085
6086 netdev->hw_enc_features = NETIF_F_IP_CSUM |
6087 NETIF_F_GSO_UDP_TUNNEL |
6088 NETIF_F_TSO |
6089 NETIF_F_SG;
6090
6091 netdev->features = NETIF_F_SG |
6092 NETIF_F_IP_CSUM |
6093 NETIF_F_SCTP_CSUM |
6094 NETIF_F_HIGHDMA |
6095 NETIF_F_GSO_UDP_TUNNEL |
6096 NETIF_F_HW_VLAN_CTAG_TX |
6097 NETIF_F_HW_VLAN_CTAG_RX |
6098 NETIF_F_HW_VLAN_CTAG_FILTER |
6099 NETIF_F_IPV6_CSUM |
6100 NETIF_F_TSO |
6101 NETIF_F_TSO6 |
6102 NETIF_F_RXCSUM |
6103 NETIF_F_RXHASH |
6104 0;
6105
6106 /* copy netdev features into list of user selectable features */
6107 netdev->hw_features |= netdev->features;
6108
6109 if (vsi->type == I40E_VSI_MAIN) {
6110 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6111 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6112 } else {
6113 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6114 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6115 pf->vsi[pf->lan_vsi]->netdev->name);
6116 random_ether_addr(mac_addr);
6117 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6118 }
6119
6120 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6121 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6122 /* vlan gets same features (except vlan offload)
6123 * after any tweaks for specific VSI types
6124 */
6125 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6126 NETIF_F_HW_VLAN_CTAG_RX |
6127 NETIF_F_HW_VLAN_CTAG_FILTER);
6128 netdev->priv_flags |= IFF_UNICAST_FLT;
6129 netdev->priv_flags |= IFF_SUPP_NOFCS;
6130 /* Setup netdev TC information */
6131 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6132
6133 netdev->netdev_ops = &i40e_netdev_ops;
6134 netdev->watchdog_timeo = 5 * HZ;
6135 i40e_set_ethtool_ops(netdev);
6136
6137 return 0;
6138}
6139
6140/**
6141 * i40e_vsi_delete - Delete a VSI from the switch
6142 * @vsi: the VSI being removed
6143 *
6144 * Returns 0 on success, negative value on failure
6145 **/
6146static void i40e_vsi_delete(struct i40e_vsi *vsi)
6147{
6148 /* remove default VSI is not allowed */
6149 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6150 return;
6151
6152 /* there is no HW VSI for FDIR */
6153 if (vsi->type == I40E_VSI_FDIR)
6154 return;
6155
6156 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
6157 return;
6158}
6159
6160/**
6161 * i40e_add_vsi - Add a VSI to the switch
6162 * @vsi: the VSI being configured
6163 *
6164 * This initializes a VSI context depending on the VSI type to be added and
6165 * passes it down to the add_vsi aq command.
6166 **/
6167static int i40e_add_vsi(struct i40e_vsi *vsi)
6168{
6169 int ret = -ENODEV;
6170 struct i40e_mac_filter *f, *ftmp;
6171 struct i40e_pf *pf = vsi->back;
6172 struct i40e_hw *hw = &pf->hw;
6173 struct i40e_vsi_context ctxt;
6174 u8 enabled_tc = 0x1; /* TC0 enabled */
6175 int f_count = 0;
6176
6177 memset(&ctxt, 0, sizeof(ctxt));
6178 switch (vsi->type) {
6179 case I40E_VSI_MAIN:
6180 /* The PF's main VSI is already setup as part of the
6181 * device initialization, so we'll not bother with
6182 * the add_vsi call, but we will retrieve the current
6183 * VSI context.
6184 */
6185 ctxt.seid = pf->main_vsi_seid;
6186 ctxt.pf_num = pf->hw.pf_id;
6187 ctxt.vf_num = 0;
6188 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6189 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6190 if (ret) {
6191 dev_info(&pf->pdev->dev,
6192 "couldn't get pf vsi config, err %d, aq_err %d\n",
6193 ret, pf->hw.aq.asq_last_status);
6194 return -ENOENT;
6195 }
6196 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6197 vsi->info.valid_sections = 0;
6198
6199 vsi->seid = ctxt.seid;
6200 vsi->id = ctxt.vsi_number;
6201
6202 enabled_tc = i40e_pf_get_tc_map(pf);
6203
6204 /* MFP mode setup queue map and update VSI */
6205 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6206 memset(&ctxt, 0, sizeof(ctxt));
6207 ctxt.seid = pf->main_vsi_seid;
6208 ctxt.pf_num = pf->hw.pf_id;
6209 ctxt.vf_num = 0;
6210 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
6211 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6212 if (ret) {
6213 dev_info(&pf->pdev->dev,
6214 "update vsi failed, aq_err=%d\n",
6215 pf->hw.aq.asq_last_status);
6216 ret = -ENOENT;
6217 goto err;
6218 }
6219 /* update the local VSI info queue map */
6220 i40e_vsi_update_queue_map(vsi, &ctxt);
6221 vsi->info.valid_sections = 0;
6222 } else {
6223 /* Default/Main VSI is only enabled for TC0
6224 * reconfigure it to enable all TCs that are
6225 * available on the port in SFP mode.
6226 */
6227 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6228 if (ret) {
6229 dev_info(&pf->pdev->dev,
6230 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
6231 enabled_tc, ret,
6232 pf->hw.aq.asq_last_status);
6233 ret = -ENOENT;
6234 }
6235 }
6236 break;
6237
6238 case I40E_VSI_FDIR:
6239 /* no queue mapping or actual HW VSI needed */
6240 vsi->info.valid_sections = 0;
6241 vsi->seid = 0;
6242 vsi->id = 0;
6243 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6244 return 0;
6245 break;
6246
6247 case I40E_VSI_VMDQ2:
6248 ctxt.pf_num = hw->pf_id;
6249 ctxt.vf_num = 0;
6250 ctxt.uplink_seid = vsi->uplink_seid;
6251 ctxt.connection_type = 0x1; /* regular data port */
6252 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6253
6254 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6255
6256 /* This VSI is connected to VEB so the switch_id
6257 * should be set to zero by default.
6258 */
6259 ctxt.info.switch_id = 0;
6260 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6261 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6262
6263 /* Setup the VSI tx/rx queue map for TC0 only for now */
6264 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6265 break;
6266
6267 case I40E_VSI_SRIOV:
6268 ctxt.pf_num = hw->pf_id;
6269 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
6270 ctxt.uplink_seid = vsi->uplink_seid;
6271 ctxt.connection_type = 0x1; /* regular data port */
6272 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6273
6274 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6275
6276 /* This VSI is connected to VEB so the switch_id
6277 * should be set to zero by default.
6278 */
6279 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6280
6281 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
6282 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6283 /* Setup the VSI tx/rx queue map for TC0 only for now */
6284 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
6285 break;
6286
6287 default:
6288 return -ENODEV;
6289 }
6290
6291 if (vsi->type != I40E_VSI_MAIN) {
6292 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6293 if (ret) {
6294 dev_info(&vsi->back->pdev->dev,
6295 "add vsi failed, aq_err=%d\n",
6296 vsi->back->hw.aq.asq_last_status);
6297 ret = -ENOENT;
6298 goto err;
6299 }
6300 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6301 vsi->info.valid_sections = 0;
6302 vsi->seid = ctxt.seid;
6303 vsi->id = ctxt.vsi_number;
6304 }
6305
6306 /* If macvlan filters already exist, force them to get loaded */
6307 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
6308 f->changed = true;
6309 f_count++;
6310 }
6311 if (f_count) {
6312 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
6313 pf->flags |= I40E_FLAG_FILTER_SYNC;
6314 }
6315
6316 /* Update VSI BW information */
6317 ret = i40e_vsi_get_bw_info(vsi);
6318 if (ret) {
6319 dev_info(&pf->pdev->dev,
6320 "couldn't get vsi bw info, err %d, aq_err %d\n",
6321 ret, pf->hw.aq.asq_last_status);
6322 /* VSI is already added so not tearing that up */
6323 ret = 0;
6324 }
6325
6326err:
6327 return ret;
6328}
6329
6330/**
6331 * i40e_vsi_release - Delete a VSI and free its resources
6332 * @vsi: the VSI being removed
6333 *
6334 * Returns 0 on success or < 0 on error
6335 **/
6336int i40e_vsi_release(struct i40e_vsi *vsi)
6337{
6338 struct i40e_mac_filter *f, *ftmp;
6339 struct i40e_veb *veb = NULL;
6340 struct i40e_pf *pf;
6341 u16 uplink_seid;
6342 int i, n;
6343
6344 pf = vsi->back;
6345
6346 /* release of a VEB-owner or last VSI is not allowed */
6347 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
6348 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
6349 vsi->seid, vsi->uplink_seid);
6350 return -ENODEV;
6351 }
6352 if (vsi == pf->vsi[pf->lan_vsi] &&
6353 !test_bit(__I40E_DOWN, &pf->state)) {
6354 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
6355 return -ENODEV;
6356 }
6357
6358 uplink_seid = vsi->uplink_seid;
6359 if (vsi->type != I40E_VSI_SRIOV) {
6360 if (vsi->netdev_registered) {
6361 vsi->netdev_registered = false;
6362 if (vsi->netdev) {
6363 /* results in a call to i40e_close() */
6364 unregister_netdev(vsi->netdev);
6365 free_netdev(vsi->netdev);
6366 vsi->netdev = NULL;
6367 }
6368 } else {
6369 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
6370 i40e_down(vsi);
6371 i40e_vsi_free_irq(vsi);
6372 i40e_vsi_free_tx_resources(vsi);
6373 i40e_vsi_free_rx_resources(vsi);
6374 }
6375 i40e_vsi_disable_irq(vsi);
6376 }
6377
6378 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
6379 i40e_del_filter(vsi, f->macaddr, f->vlan,
6380 f->is_vf, f->is_netdev);
6381 i40e_sync_vsi_filters(vsi);
6382
6383 i40e_vsi_delete(vsi);
6384 i40e_vsi_free_q_vectors(vsi);
6385 i40e_vsi_clear_rings(vsi);
6386 i40e_vsi_clear(vsi);
6387
6388 /* If this was the last thing on the VEB, except for the
6389 * controlling VSI, remove the VEB, which puts the controlling
6390 * VSI onto the next level down in the switch.
6391 *
6392 * Well, okay, there's one more exception here: don't remove
6393 * the orphan VEBs yet. We'll wait for an explicit remove request
6394 * from up the network stack.
6395 */
6396 for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6397 if (pf->vsi[i] &&
6398 pf->vsi[i]->uplink_seid == uplink_seid &&
6399 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6400 n++; /* count the VSIs */
6401 }
6402 }
6403 for (i = 0; i < I40E_MAX_VEB; i++) {
6404 if (!pf->veb[i])
6405 continue;
6406 if (pf->veb[i]->uplink_seid == uplink_seid)
6407 n++; /* count the VEBs */
6408 if (pf->veb[i]->seid == uplink_seid)
6409 veb = pf->veb[i];
6410 }
6411 if (n == 0 && veb && veb->uplink_seid != 0)
6412 i40e_veb_release(veb);
6413
6414 return 0;
6415}
6416
6417/**
6418 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
6419 * @vsi: ptr to the VSI
6420 *
6421 * This should only be called after i40e_vsi_mem_alloc() which allocates the
6422 * corresponding SW VSI structure and initializes num_queue_pairs for the
6423 * newly allocated VSI.
6424 *
6425 * Returns 0 on success or negative on failure
6426 **/
6427static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
6428{
6429 int ret = -ENOENT;
6430 struct i40e_pf *pf = vsi->back;
6431
493fb300 6432 if (vsi->q_vectors[0]) {
41c445ff
JB		 6433 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
6434 vsi->seid);
6435 return -EEXIST;
6436 }
6437
6438 if (vsi->base_vector) {
6439 dev_info(&pf->pdev->dev,
6440 "VSI %d has non-zero base vector %d\n",
6441 vsi->seid, vsi->base_vector);
6442 return -EEXIST;
6443 }
6444
6445 ret = i40e_alloc_q_vectors(vsi);
6446 if (ret) {
6447 dev_info(&pf->pdev->dev,
6448 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
6449 vsi->num_q_vectors, vsi->seid, ret);
6450 vsi->num_q_vectors = 0;
6451 goto vector_setup_out;
6452 }
6453
958a3e3b
SN		 6454 if (vsi->num_q_vectors)
6455 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
6456 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 6457 if (vsi->base_vector < 0) {
6458 dev_info(&pf->pdev->dev,
6459 "failed to get q tracking for VSI %d, err=%d\n",
6460 vsi->seid, vsi->base_vector);
6461 i40e_vsi_free_q_vectors(vsi);
6462 ret = -ENOENT;
6463 goto vector_setup_out;
6464 }
6465
6466vector_setup_out:
6467 return ret;
6468}
6469
bc7d338f
ASJ		 6470/**
6471 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
6472 * @vsi: pointer to the vsi.
6473 *
6474 * This re-allocates a vsi's queue resources.
6475 *
6476 * Returns pointer to the successfully allocated and configured VSI sw struct
6477 * on success, otherwise returns NULL on failure.
6478 **/
6479static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
6480{
6481 struct i40e_pf *pf = vsi->back;
6482 u8 enabled_tc;
6483 int ret;
6484
6485 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6486 i40e_vsi_clear_rings(vsi);
6487
6488 i40e_vsi_free_arrays(vsi, false);
6489 i40e_set_num_rings_in_vsi(vsi);
6490 ret = i40e_vsi_alloc_arrays(vsi, false);
6491 if (ret)
6492 goto err_vsi;
6493
6494 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6495 if (ret < 0) {
6496 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6497 vsi->seid, ret);
6498 goto err_vsi;
6499 }
6500 vsi->base_queue = ret;
6501
6502 /* Update the FW view of the VSI. Force a reset of TC and queue
6503 * layout configurations.
6504 */
6505 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6506 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
6507 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
6508 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
6509
6510 /* assign it some queues */
6511 ret = i40e_alloc_rings(vsi);
6512 if (ret)
6513 goto err_rings;
6514
6515 /* map all of the rings to the q_vectors */
6516 i40e_vsi_map_rings_to_vectors(vsi);
6517 return vsi;
6518
6519err_rings:
6520 i40e_vsi_free_q_vectors(vsi);
6521 if (vsi->netdev_registered) {
6522 vsi->netdev_registered = false;
6523 unregister_netdev(vsi->netdev);
6524 free_netdev(vsi->netdev);
6525 vsi->netdev = NULL;
6526 }
6527 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6528err_vsi:
6529 i40e_vsi_clear(vsi);
6530 return NULL;
6531}
6532
41c445ff
JB		 6533/**
6534 * i40e_vsi_setup - Set up a VSI by a given type
6535 * @pf: board private structure
6536 * @type: VSI type
6537 * @uplink_seid: the switch element to link to
6538 * @param1: usage depends upon VSI type. For VF types, indicates VF id
6539 *
6540 * This allocates the sw VSI structure and its queue resources, then add a VSI
6541 * to the identified VEB.
6542 *
6543 * Returns pointer to the successfully allocated and configure VSI sw struct on
6544 * success, otherwise returns NULL on failure.
6545 **/
6546struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
6547 u16 uplink_seid, u32 param1)
6548{
6549 struct i40e_vsi *vsi = NULL;
6550 struct i40e_veb *veb = NULL;
6551 int ret, i;
6552 int v_idx;
6553
6554 /* The requested uplink_seid must be either
6555 * - the PF's port seid
6556 * no VEB is needed because this is the PF
6557 * or this is a Flow Director special case VSI
6558 * - seid of an existing VEB
6559 * - seid of a VSI that owns an existing VEB
6560 * - seid of a VSI that doesn't own a VEB
6561 * a new VEB is created and the VSI becomes the owner
6562 * - seid of the PF VSI, which is what creates the first VEB
6563 * this is a special case of the previous
6564 *
6565 * Find which uplink_seid we were given and create a new VEB if needed
6566 */
6567 for (i = 0; i < I40E_MAX_VEB; i++) {
6568 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
6569 veb = pf->veb[i];
6570 break;
6571 }
6572 }
6573
6574 if (!veb && uplink_seid != pf->mac_seid) {
6575
6576 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6577 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
6578 vsi = pf->vsi[i];
6579 break;
6580 }
6581 }
6582 if (!vsi) {
6583 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
6584 uplink_seid);
6585 return NULL;
6586 }
6587
6588 if (vsi->uplink_seid == pf->mac_seid)
6589 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
6590 vsi->tc_config.enabled_tc);
6591 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
6592 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
6593 vsi->tc_config.enabled_tc);
6594
6595 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
6596 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
6597 veb = pf->veb[i];
6598 }
6599 if (!veb) {
6600 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
6601 return NULL;
6602 }
6603
6604 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6605 uplink_seid = veb->seid;
6606 }
6607
6608 /* get vsi sw struct */
6609 v_idx = i40e_vsi_mem_alloc(pf, type);
6610 if (v_idx < 0)
6611 goto err_alloc;
6612 vsi = pf->vsi[v_idx];
6613 vsi->type = type;
6614 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
6615
6616 if (type == I40E_VSI_MAIN)
6617 pf->lan_vsi = v_idx;
6618 else if (type == I40E_VSI_SRIOV)
6619 vsi->vf_id = param1;
6620 /* assign it some queues */
6621 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
6622 if (ret < 0) {
6623 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
6624 vsi->seid, ret);
6625 goto err_vsi;
6626 }
6627 vsi->base_queue = ret;
6628
6629 /* get a VSI from the hardware */
6630 vsi->uplink_seid = uplink_seid;
6631 ret = i40e_add_vsi(vsi);
6632 if (ret)
6633 goto err_vsi;
6634
6635 switch (vsi->type) {
6636 /* setup the netdev if needed */
6637 case I40E_VSI_MAIN:
6638 case I40E_VSI_VMDQ2:
6639 ret = i40e_config_netdev(vsi);
6640 if (ret)
6641 goto err_netdev;
6642 ret = register_netdev(vsi->netdev);
6643 if (ret)
6644 goto err_netdev;
6645 vsi->netdev_registered = true;
6646 netif_carrier_off(vsi->netdev);
6647 /* fall through */
6648
6649 case I40E_VSI_FDIR:
6650 /* set up vectors and rings if needed */
6651 ret = i40e_vsi_setup_vectors(vsi);
6652 if (ret)
6653 goto err_msix;
6654
6655 ret = i40e_alloc_rings(vsi);
6656 if (ret)
6657 goto err_rings;
6658
6659 /* map all of the rings to the q_vectors */
6660 i40e_vsi_map_rings_to_vectors(vsi);
6661
6662 i40e_vsi_reset_stats(vsi);
6663 break;
6664
6665 default:
6666 /* no netdev or rings for the other VSI types */
6667 break;
6668 }
6669
6670 return vsi;
6671
6672err_rings:
6673 i40e_vsi_free_q_vectors(vsi);
6674err_msix:
6675 if (vsi->netdev_registered) {
6676 vsi->netdev_registered = false;
6677 unregister_netdev(vsi->netdev);
6678 free_netdev(vsi->netdev);
6679 vsi->netdev = NULL;
6680 }
6681err_netdev:
6682 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
6683err_vsi:
6684 i40e_vsi_clear(vsi);
6685err_alloc:
6686 return NULL;
6687}
6688
6689/**
6690 * i40e_veb_get_bw_info - Query VEB BW information
6691 * @veb: the veb to query
6692 *
6693 * Query the Tx scheduler BW configuration data for given VEB
6694 **/
6695static int i40e_veb_get_bw_info(struct i40e_veb *veb)
6696{
6697 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
6698 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
6699 struct i40e_pf *pf = veb->pf;
6700 struct i40e_hw *hw = &pf->hw;
6701 u32 tc_bw_max;
6702 int ret = 0;
6703 int i;
6704
6705 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
6706 &bw_data, NULL);
6707 if (ret) {
6708 dev_info(&pf->pdev->dev,
6709 "query veb bw config failed, aq_err=%d\n",
6710 hw->aq.asq_last_status);
6711 goto out;
6712 }
6713
6714 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
6715 &ets_data, NULL);
6716 if (ret) {
6717 dev_info(&pf->pdev->dev,
6718 "query veb bw ets config failed, aq_err=%d\n",
6719 hw->aq.asq_last_status);
6720 goto out;
6721 }
6722
6723 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
6724 veb->bw_max_quanta = ets_data.tc_bw_max;
6725 veb->is_abs_credits = bw_data.absolute_credits_enable;
6726 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
6727 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
6728 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6729 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
6730 veb->bw_tc_limit_credits[i] =
6731 le16_to_cpu(bw_data.tc_bw_limits[i]);
6732 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
6733 }
6734
6735out:
6736 return ret;
6737}
6738
6739/**
6740 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
6741 * @pf: board private structure
6742 *
6743 * On error: returns error code (negative)
6744 * On success: returns vsi index in PF (positive)
6745 **/
6746static int i40e_veb_mem_alloc(struct i40e_pf *pf)
6747{
6748 int ret = -ENOENT;
6749 struct i40e_veb *veb;
6750 int i;
6751
6752 /* Need to protect the allocation of switch elements at the PF level */
6753 mutex_lock(&pf->switch_mutex);
6754
6755 /* VEB list may be fragmented if VEB creation/destruction has
6756 * been happening. We can afford to do a quick scan to look
6757 * for any free slots in the list.
6758 *
6759 * find next empty veb slot, looping back around if necessary
6760 */
6761 i = 0;
6762 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
6763 i++;
6764 if (i >= I40E_MAX_VEB) {
6765 ret = -ENOMEM;
6766 goto err_alloc_veb; /* out of VEB slots! */
6767 }
6768
6769 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
6770 if (!veb) {
6771 ret = -ENOMEM;
6772 goto err_alloc_veb;
6773 }
6774 veb->pf = pf;
6775 veb->idx = i;
6776 veb->enabled_tc = 1;
6777
6778 pf->veb[i] = veb;
6779 ret = i;
6780err_alloc_veb:
6781 mutex_unlock(&pf->switch_mutex);
6782 return ret;
6783}
6784
6785/**
6786 * i40e_switch_branch_release - Delete a branch of the switch tree
6787 * @branch: where to start deleting
6788 *
6789 * This uses recursion to find the tips of the branch to be
6790 * removed, deleting until we get back to and can delete this VEB.
6791 **/
6792static void i40e_switch_branch_release(struct i40e_veb *branch)
6793{
6794 struct i40e_pf *pf = branch->pf;
6795 u16 branch_seid = branch->seid;
6796 u16 veb_idx = branch->idx;
6797 int i;
6798
6799 /* release any VEBs on this VEB - RECURSION */
6800 for (i = 0; i < I40E_MAX_VEB; i++) {
6801 if (!pf->veb[i])
6802 continue;
6803 if (pf->veb[i]->uplink_seid == branch->seid)
6804 i40e_switch_branch_release(pf->veb[i]);
6805 }
6806
6807 /* Release the VSIs on this VEB, but not the owner VSI.
6808 *
6809 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
6810 * the VEB itself, so don't use (*branch) after this loop.
6811 */
6812 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6813 if (!pf->vsi[i])
6814 continue;
6815 if (pf->vsi[i]->uplink_seid == branch_seid &&
6816 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
6817 i40e_vsi_release(pf->vsi[i]);
6818 }
6819 }
6820
6821 /* There's one corner case where the VEB might not have been
6822 * removed, so double check it here and remove it if needed.
6823 * This case happens if the veb was created from the debugfs
6824 * commands and no VSIs were added to it.
6825 */
6826 if (pf->veb[veb_idx])
6827 i40e_veb_release(pf->veb[veb_idx]);
6828}
6829
6830/**
6831 * i40e_veb_clear - remove veb struct
6832 * @veb: the veb to remove
6833 **/
6834static void i40e_veb_clear(struct i40e_veb *veb)
6835{
6836 if (!veb)
6837 return;
6838
6839 if (veb->pf) {
6840 struct i40e_pf *pf = veb->pf;
6841
6842 mutex_lock(&pf->switch_mutex);
6843 if (pf->veb[veb->idx] == veb)
6844 pf->veb[veb->idx] = NULL;
6845 mutex_unlock(&pf->switch_mutex);
6846 }
6847
6848 kfree(veb);
6849}
6850
6851/**
6852 * i40e_veb_release - Delete a VEB and free its resources
6853 * @veb: the VEB being removed
6854 **/
6855void i40e_veb_release(struct i40e_veb *veb)
6856{
6857 struct i40e_vsi *vsi = NULL;
6858 struct i40e_pf *pf;
6859 int i, n = 0;
6860
6861 pf = veb->pf;
6862
6863 /* find the remaining VSI and check for extras */
6864 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
6865 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
6866 n++;
6867 vsi = pf->vsi[i];
6868 }
6869 }
6870 if (n != 1) {
6871 dev_info(&pf->pdev->dev,
6872 "can't remove VEB %d with %d VSIs left\n",
6873 veb->seid, n);
6874 return;
6875 }
6876
6877 /* move the remaining VSI to uplink veb */
6878 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
6879 if (veb->uplink_seid) {
6880 vsi->uplink_seid = veb->uplink_seid;
6881 if (veb->uplink_seid == pf->mac_seid)
6882 vsi->veb_idx = I40E_NO_VEB;
6883 else
6884 vsi->veb_idx = veb->veb_idx;
6885 } else {
6886 /* floating VEB */
6887 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6888 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
6889 }
6890
6891 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
6892 i40e_veb_clear(veb);
6893
6894 return;
6895}
6896
6897/**
6898 * i40e_add_veb - create the VEB in the switch
6899 * @veb: the VEB to be instantiated
6900 * @vsi: the controlling VSI
6901 **/
6902static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
6903{
56747264 6904 bool is_default = false;
e1c51b95 6905 bool is_cloud = false;
41c445ff
JB		 6906 int ret;
6907
6908 /* get a VEB from the hardware */
6909 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 6910 veb->enabled_tc, is_default,
6911 is_cloud, &veb->seid, NULL);
41c445ff
JB		 6912 if (ret) {
6913 dev_info(&veb->pf->pdev->dev,
6914 "couldn't add VEB, err %d, aq_err %d\n",
6915 ret, veb->pf->hw.aq.asq_last_status);
6916 return -EPERM;
6917 }
6918
6919 /* get statistics counter */
6920 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
6921 &veb->stats_idx, NULL, NULL, NULL);
6922 if (ret) {
6923 dev_info(&veb->pf->pdev->dev,
6924 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
6925 ret, veb->pf->hw.aq.asq_last_status);
6926 return -EPERM;
6927 }
6928 ret = i40e_veb_get_bw_info(veb);
6929 if (ret) {
6930 dev_info(&veb->pf->pdev->dev,
6931 "couldn't get VEB bw info, err %d, aq_err %d\n",
6932 ret, veb->pf->hw.aq.asq_last_status);
6933 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
6934 return -ENOENT;
6935 }
6936
6937 vsi->uplink_seid = veb->seid;
6938 vsi->veb_idx = veb->idx;
6939 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
6940
6941 return 0;
6942}
6943
6944/**
6945 * i40e_veb_setup - Set up a VEB
6946 * @pf: board private structure
6947 * @flags: VEB setup flags
6948 * @uplink_seid: the switch element to link to
6949 * @vsi_seid: the initial VSI seid
6950 * @enabled_tc: Enabled TC bit-map
6951 *
6952 * This allocates the sw VEB structure and links it into the switch
6953 * It is possible and legal for this to be a duplicate of an already
6954 * existing VEB. It is also possible for both uplink and vsi seids
6955 * to be zero, in order to create a floating VEB.
6956 *
6957 * Returns pointer to the successfully allocated VEB sw struct on
6958 * success, otherwise returns NULL on failure.
6959 **/
6960struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
6961 u16 uplink_seid, u16 vsi_seid,
6962 u8 enabled_tc)
6963{
6964 struct i40e_veb *veb, *uplink_veb = NULL;
6965 int vsi_idx, veb_idx;
6966 int ret;
6967
6968 /* if one seid is 0, the other must be 0 to create a floating relay */
6969 if ((uplink_seid == 0 || vsi_seid == 0) &&
6970 (uplink_seid + vsi_seid != 0)) {
6971 dev_info(&pf->pdev->dev,
6972 "one, not both seid's are 0: uplink=%d vsi=%d\n",
6973 uplink_seid, vsi_seid);
6974 return NULL;
6975 }
6976
6977 /* make sure there is such a vsi and uplink */
6978 for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
6979 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
6980 break;
6981 if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
6982 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
6983 vsi_seid);
6984 return NULL;
6985 }
6986
6987 if (uplink_seid && uplink_seid != pf->mac_seid) {
6988 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6989 if (pf->veb[veb_idx] &&
6990 pf->veb[veb_idx]->seid == uplink_seid) {
6991 uplink_veb = pf->veb[veb_idx];
6992 break;
6993 }
6994 }
6995 if (!uplink_veb) {
6996 dev_info(&pf->pdev->dev,
6997 "uplink seid %d not found\n", uplink_seid);
6998 return NULL;
6999 }
7000 }
7001
7002 /* get veb sw struct */
7003 veb_idx = i40e_veb_mem_alloc(pf);
7004 if (veb_idx < 0)
7005 goto err_alloc;
7006 veb = pf->veb[veb_idx];
7007 veb->flags = flags;
7008 veb->uplink_seid = uplink_seid;
7009 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7010 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7011
7012 /* create the VEB in the switch */
7013 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7014 if (ret)
7015 goto err_veb;
7016
7017 return veb;
7018
7019err_veb:
7020 i40e_veb_clear(veb);
7021err_alloc:
7022 return NULL;
7023}
7024
7025/**
7026 * i40e_setup_pf_switch_element - set pf vars based on switch type
7027 * @pf: board private structure
7028 * @ele: element we are building info from
7029 * @num_reported: total number of elements
7030 * @printconfig: should we print the contents
7031 *
7032 * helper function to assist in extracting a few useful SEID values.
7033 **/
7034static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7035 struct i40e_aqc_switch_config_element_resp *ele,
7036 u16 num_reported, bool printconfig)
7037{
7038 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7039 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7040 u8 element_type = ele->element_type;
7041 u16 seid = le16_to_cpu(ele->seid);
7042
7043 if (printconfig)
7044 dev_info(&pf->pdev->dev,
7045 "type=%d seid=%d uplink=%d downlink=%d\n",
7046 element_type, seid, uplink_seid, downlink_seid);
7047
7048 switch (element_type) {
7049 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7050 pf->mac_seid = seid;
7051 break;
7052 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7053 /* Main VEB? */
7054 if (uplink_seid != pf->mac_seid)
7055 break;
7056 if (pf->lan_veb == I40E_NO_VEB) {
7057 int v;
7058
7059 /* find existing or else empty VEB */
7060 for (v = 0; v < I40E_MAX_VEB; v++) {
7061 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7062 pf->lan_veb = v;
7063 break;
7064 }
7065 }
7066 if (pf->lan_veb == I40E_NO_VEB) {
7067 v = i40e_veb_mem_alloc(pf);
7068 if (v < 0)
7069 break;
7070 pf->lan_veb = v;
7071 }
7072 }
7073
7074 pf->veb[pf->lan_veb]->seid = seid;
7075 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7076 pf->veb[pf->lan_veb]->pf = pf;
7077 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7078 break;
7079 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7080 if (num_reported != 1)
7081 break;
7082 /* This is immediately after a reset so we can assume this is
7083 * the PF's VSI
7084 */
7085 pf->mac_seid = uplink_seid;
7086 pf->pf_seid = downlink_seid;
7087 pf->main_vsi_seid = seid;
7088 if (printconfig)
7089 dev_info(&pf->pdev->dev,
7090 "pf_seid=%d main_vsi_seid=%d\n",
7091 pf->pf_seid, pf->main_vsi_seid);
7092 break;
7093 case I40E_SWITCH_ELEMENT_TYPE_PF:
7094 case I40E_SWITCH_ELEMENT_TYPE_VF:
7095 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7096 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7097 case I40E_SWITCH_ELEMENT_TYPE_PE:
7098 case I40E_SWITCH_ELEMENT_TYPE_PA:
7099 /* ignore these for now */
7100 break;
7101 default:
7102 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7103 element_type, seid);
7104 break;
7105 }
7106}
7107
7108/**
7109 * i40e_fetch_switch_configuration - Get switch config from firmware
7110 * @pf: board private structure
7111 * @printconfig: should we print the contents
7112 *
7113 * Get the current switch configuration from the device and
7114 * extract a few useful SEID values.
7115 **/
7116int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7117{
7118 struct i40e_aqc_get_switch_config_resp *sw_config;
7119 u16 next_seid = 0;
7120 int ret = 0;
7121 u8 *aq_buf;
7122 int i;
7123
7124 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7125 if (!aq_buf)
7126 return -ENOMEM;
7127
7128 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7129 do {
7130 u16 num_reported, num_total;
7131
7132 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7133 I40E_AQ_LARGE_BUF,
7134 &next_seid, NULL);
7135 if (ret) {
7136 dev_info(&pf->pdev->dev,
7137 "get switch config failed %d aq_err=%x\n",
7138 ret, pf->hw.aq.asq_last_status);
7139 kfree(aq_buf);
7140 return -ENOENT;
7141 }
7142
7143 num_reported = le16_to_cpu(sw_config->header.num_reported);
7144 num_total = le16_to_cpu(sw_config->header.num_total);
7145
7146 if (printconfig)
7147 dev_info(&pf->pdev->dev,
7148 "header: %d reported %d total\n",
7149 num_reported, num_total);
7150
7151 if (num_reported) {
7152 int sz = sizeof(*sw_config) * num_reported;
7153
7154 kfree(pf->sw_config);
7155 pf->sw_config = kzalloc(sz, GFP_KERNEL);
7156 if (pf->sw_config)
7157 memcpy(pf->sw_config, sw_config, sz);
7158 }
7159
7160 for (i = 0; i < num_reported; i++) {
7161 struct i40e_aqc_switch_config_element_resp *ele =
7162 &sw_config->element[i];
7163
7164 i40e_setup_pf_switch_element(pf, ele, num_reported,
7165 printconfig);
7166 }
7167 } while (next_seid != 0);
7168
7169 kfree(aq_buf);
7170 return ret;
7171}
7172
7173/**
7174 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
7175 * @pf: board private structure
bc7d338f 7176 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 7177 *
7178 * Returns 0 on success, negative value on failure
7179 **/
bc7d338f 7180static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 7181{
895106a5 7182 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 7183 int ret;
7184
7185 /* find out what's out there already */
7186 ret = i40e_fetch_switch_configuration(pf, false);
7187 if (ret) {
7188 dev_info(&pf->pdev->dev,
7189 "couldn't fetch switch config, err %d, aq_err %d\n",
7190 ret, pf->hw.aq.asq_last_status);
7191 return ret;
7192 }
7193 i40e_pf_reset_stats(pf);
7194
7195 /* fdir VSI must happen first to be sure it gets queue 0, but only
7196 * if there is enough room for the fdir VSI
7197 */
7198 if (pf->num_lan_qps > 1)
7199 i40e_fdir_setup(pf);
7200
7201 /* first time setup */
bc7d338f 7202 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 7203 struct i40e_vsi *vsi = NULL;
7204 u16 uplink_seid;
7205
7206 /* Set up the PF VSI associated with the PF's main VSI
7207 * that is already in the HW switch
7208 */
7209 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
7210 uplink_seid = pf->veb[pf->lan_veb]->seid;
7211 else
7212 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 7213 if (pf->lan_vsi == I40E_NO_VSI)
7214 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
7215 else if (reinit)
7216 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 7217 if (!vsi) {
7218 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
7219 i40e_fdir_teardown(pf);
7220 return -EAGAIN;
7221 }
41c445ff
JB		 7222 } else {
7223 /* force a reset of TC and queue layout configurations */
7224 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7225 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7226 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7227 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7228 }
7229 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
7230
7231 /* Setup static PF queue filter control settings */
7232 ret = i40e_setup_pf_filter_control(pf);
7233 if (ret) {
7234 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
7235 ret);
7236 /* Failure here should not stop continuing other steps */
7237 }
7238
7239 /* enable RSS in the HW, even for only one queue, as the stack can use
7240 * the hash
7241 */
7242 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
7243 i40e_config_rss(pf);
7244
7245 /* fill in link information and enable LSE reporting */
7246 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
7247 i40e_link_event(pf);
7248
d52c20b7 7249 /* Initialize user-specific link properties */
41c445ff
JB		 7250 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
7251 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 7252 /* requested_mode is set in probe or by ethtool */
7253 if (!pf->fc_autoneg_status)
7254 goto no_autoneg;
7255
7256 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
7257 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 7258 pf->hw.fc.current_mode = I40E_FC_FULL;
7259 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
7260 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
7261 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
7262 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
7263 else
d52c20b7
JB		 7264 pf->hw.fc.current_mode = I40E_FC_NONE;
7265
7266 /* sync the flow control settings with the auto-neg values */
7267 switch (pf->hw.fc.current_mode) {
7268 case I40E_FC_FULL:
7269 txfc = 1;
7270 rxfc = 1;
7271 break;
7272 case I40E_FC_TX_PAUSE:
7273 txfc = 1;
7274 rxfc = 0;
7275 break;
7276 case I40E_FC_RX_PAUSE:
7277 txfc = 0;
7278 rxfc = 1;
7279 break;
7280 case I40E_FC_NONE:
7281 case I40E_FC_DEFAULT:
7282 txfc = 0;
7283 rxfc = 0;
7284 break;
7285 case I40E_FC_PFC:
7286 /* TBD */
7287 break;
7288 /* no default case, we have to handle all possibilities here */
7289 }
7290
7291 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
7292
7293 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7294 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
7295 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
7296
7297 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 7298
d52c20b7
JB		 7299 goto fc_complete;
7300
7301no_autoneg:
7302 /* disable L2 flow control, user can turn it on if they wish */
7303 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
7304 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
7305 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
7306
7307fc_complete:
41c445ff
JB		 7308 return ret;
7309}
7310
7311/**
7312 * i40e_set_rss_size - helper to set rss_size
7313 * @pf: board private structure
7314 * @queues_left: how many queues
7315 */
7316static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
7317{
7318 int num_tc0;
7319
7320 num_tc0 = min_t(int, queues_left, pf->rss_size_max);
bf051a3b 7321 num_tc0 = min_t(int, num_tc0, num_online_cpus());
41c445ff
JB		 7322 num_tc0 = rounddown_pow_of_two(num_tc0);
7323
7324 return num_tc0;
7325}
7326
7327/**
7328 * i40e_determine_queue_usage - Work out queue distribution
7329 * @pf: board private structure
7330 **/
7331static void i40e_determine_queue_usage(struct i40e_pf *pf)
7332{
7333 int accum_tc_size;
7334 int queues_left;
7335
7336 pf->num_lan_qps = 0;
7337 pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
7338 accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
7339
7340 /* Find the max queues to be put into basic use. We'll always be
7341 * using TC0, whether or not DCB is running, and TC0 will get the
7342 * big RSS set.
7343 */
7344 queues_left = pf->hw.func_caps.num_tx_qp;
7345
9f52987b 7346 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
41c445ff
JB		 7347 !(pf->flags & (I40E_FLAG_RSS_ENABLED |
7348 I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
7349 (queues_left == 1)) {
7350
7351 /* one qp for PF, no queues for anything else */
7352 queues_left = 0;
7353 pf->rss_size = pf->num_lan_qps = 1;
7354
7355 /* make sure all the fancies are disabled */
7356 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
41c445ff
JB		 7357 I40E_FLAG_FDIR_ENABLED |
7358 I40E_FLAG_FDIR_ATR_ENABLED |
7359 I40E_FLAG_DCB_ENABLED |
7360 I40E_FLAG_SRIOV_ENABLED |
7361 I40E_FLAG_VMDQ_ENABLED);
7362
7363 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7364 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7365 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7366
7367 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7368
7369 queues_left -= pf->rss_size;
f8ff1464 7370 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7371
7372 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7373 !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7374 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7375
7376 /* save num_tc_qps queues for TCs 1 thru 7 and the rest
7377 * are set up for RSS in TC0
7378 */
7379 queues_left -= accum_tc_size;
7380
7381 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7382
7383 queues_left -= pf->rss_size;
7384 if (queues_left < 0) {
7385 dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
7386 return;
7387 }
7388
f8ff1464 7389 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7390
7391 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7392 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7393 !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
7394
7395 queues_left -= 1; /* save 1 queue for FD */
7396
7397 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7398
7399 queues_left -= pf->rss_size;
7400 if (queues_left < 0) {
7401 dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
7402 return;
7403 }
7404
f8ff1464 7405 pf->num_lan_qps = pf->rss_size_max;
41c445ff
JB		 7406
7407 } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
7408 (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
7409 (pf->flags & I40E_FLAG_DCB_ENABLED)) {
7410
7411 /* save 1 queue for TCs 1 thru 7,
7412 * 1 queue for flow director,
7413 * and the rest are set up for RSS in TC0
7414 */
7415 queues_left -= 1;
7416 queues_left -= accum_tc_size;
7417
7418 pf->rss_size = i40e_set_rss_size(pf, queues_left);
7419 queues_left -= pf->rss_size;
7420 if (queues_left < 0) {
7421 dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
7422 return;
7423 }
7424
f8ff1464 7425 pf->num_lan_qps = pf->rss_size_max + accum_tc_size;
41c445ff
JB		 7426
7427 } else {
7428 dev_info(&pf->pdev->dev,
7429 "Invalid configuration, flags=0x%08llx\n", pf->flags);
7430 return;
7431 }
7432
7433 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7434 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
7435 pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
7436 pf->num_vf_qps));
7437 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
7438 }
7439
7440 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7441 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
7442 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
7443 (queues_left / pf->num_vmdq_qps));
7444 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
7445 }
7446
f8ff1464 7447 pf->queues_left = queues_left;
41c445ff
JB		 7448 return;
7449}
7450
7451/**
7452 * i40e_setup_pf_filter_control - Setup PF static filter control
7453 * @pf: PF to be setup
7454 *
7455 * i40e_setup_pf_filter_control sets up a pf's initial filter control
7456 * settings. If PE/FCoE are enabled then it will also set the per PF
7457 * based filter sizes required for them. It also enables Flow director,
7458 * ethertype and macvlan type filter settings for the pf.
7459 *
7460 * Returns 0 on success, negative on failure
7461 **/
7462static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
7463{
7464 struct i40e_filter_control_settings *settings = &pf->filter_settings;
7465
7466 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
7467
7468 /* Flow Director is enabled */
7469 if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
7470 settings->enable_fdir = true;
7471
7472 /* Ethtype and MACVLAN filters enabled for PF */
7473 settings->enable_ethtype = true;
7474 settings->enable_macvlan = true;
7475
7476 if (i40e_set_filter_control(&pf->hw, settings))
7477 return -ENOENT;
7478
7479 return 0;
7480}
7481
7482/**
7483 * i40e_probe - Device initialization routine
7484 * @pdev: PCI device information struct
7485 * @ent: entry in i40e_pci_tbl
7486 *
7487 * i40e_probe initializes a pf identified by a pci_dev structure.
7488 * The OS initialization, configuring of the pf private structure,
7489 * and a hardware reset occur.
7490 *
7491 * Returns 0 on success, negative on failure
7492 **/
7493static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7494{
7495 struct i40e_driver_version dv;
7496 struct i40e_pf *pf;
7497 struct i40e_hw *hw;
93cd765b 7498 static u16 pfs_found;
d4dfb81a 7499 u16 link_status;
41c445ff
JB		 7500 int err = 0;
7501 u32 len;
7502
7503 err = pci_enable_device_mem(pdev);
7504 if (err)
7505 return err;
7506
7507 /* set up for high or low dma */
7508 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7509 /* coherent mask for the same size will always succeed if
7510 * dma_set_mask does
7511 */
7512 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
7513 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
7514 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7515 } else {
7516 dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
7517 err = -EIO;
7518 goto err_dma;
7519 }
7520
7521 /* set up pci connections */
7522 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7523 IORESOURCE_MEM), i40e_driver_name);
7524 if (err) {
7525 dev_info(&pdev->dev,
7526 "pci_request_selected_regions failed %d\n", err);
7527 goto err_pci_reg;
7528 }
7529
7530 pci_enable_pcie_error_reporting(pdev);
7531 pci_set_master(pdev);
7532
7533 /* Now that we have a PCI connection, we need to do the
7534 * low level device setup. This is primarily setting up
7535 * the Admin Queue structures and then querying for the
7536 * device's current profile information.
7537 */
7538 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
7539 if (!pf) {
7540 err = -ENOMEM;
7541 goto err_pf_alloc;
7542 }
7543 pf->next_vsi = 0;
7544 pf->pdev = pdev;
7545 set_bit(__I40E_DOWN, &pf->state);
7546
7547 hw = &pf->hw;
7548 hw->back = pf;
7549 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7550 pci_resource_len(pdev, 0));
7551 if (!hw->hw_addr) {
7552 err = -EIO;
7553 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
7554 (unsigned int)pci_resource_start(pdev, 0),
7555 (unsigned int)pci_resource_len(pdev, 0), err);
7556 goto err_ioremap;
7557 }
7558 hw->vendor_id = pdev->vendor;
7559 hw->device_id = pdev->device;
7560 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
7561 hw->subsystem_vendor_id = pdev->subsystem_vendor;
7562 hw->subsystem_device_id = pdev->subsystem_device;
7563 hw->bus.device = PCI_SLOT(pdev->devfn);
7564 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 7565 pf->instance = pfs_found;
41c445ff 7566
7134f9ce
JB		 7567 /* do a special CORER for clearing PXE mode once at init */
7568 if (hw->revision_id == 0 &&
7569 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
7570 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
7571 i40e_flush(hw);
7572 msleep(200);
7573 pf->corer_count++;
7574
7575 i40e_clear_pxe_mode(hw);
7576 }
7577
41c445ff
JB		 7578 /* Reset here to make sure all is clean and to define PF 'n' */
7579 err = i40e_pf_reset(hw);
7580 if (err) {
7581 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
7582 goto err_pf_reset;
7583 }
7584 pf->pfr_count++;
7585
7586 hw->aq.num_arq_entries = I40E_AQ_LEN;
7587 hw->aq.num_asq_entries = I40E_AQ_LEN;
7588 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7589 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
7590 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
7591 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
7592 "%s-pf%d:misc",
7593 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
7594
7595 err = i40e_init_shared_code(hw);
7596 if (err) {
7597 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
7598 goto err_pf_reset;
7599 }
7600
d52c20b7
JB		 7601 /* set up a default setting for link flow control */
7602 pf->hw.fc.requested_mode = I40E_FC_NONE;
7603
41c445ff
JB		 7604 err = i40e_init_adminq(hw);
7605 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
fe310704
AS		 7606 if (((hw->nvm.version & I40E_NVM_VERSION_HI_MASK)
7607 >> I40E_NVM_VERSION_HI_SHIFT) != I40E_CURRENT_NVM_VERSION_HI) {
7608 dev_info(&pdev->dev,
7609 "warning: NVM version not supported, supported version: %02x.%02x\n",
7610 I40E_CURRENT_NVM_VERSION_HI,
7611 I40E_CURRENT_NVM_VERSION_LO);
7612 }
41c445ff
JB		 7613 if (err) {
7614 dev_info(&pdev->dev,
7615 "init_adminq failed: %d expecting API %02x.%02x\n",
7616 err,
7617 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
7618 goto err_pf_reset;
7619 }
7620
7621 err = i40e_get_capabilities(pf);
7622 if (err)
7623 goto err_adminq_setup;
7624
7625 err = i40e_sw_init(pf);
7626 if (err) {
7627 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
7628 goto err_sw_init;
7629 }
7630
7631 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
7632 hw->func_caps.num_rx_qp,
7633 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
7634 if (err) {
7635 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
7636 goto err_init_lan_hmc;
7637 }
7638
7639 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
7640 if (err) {
7641 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
7642 err = -ENOENT;
7643 goto err_configure_lan_hmc;
7644 }
7645
7646 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 7647 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 7648 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
7649 err = -EIO;
7650 goto err_mac_addr;
7651 }
7652 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
7653 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
7654
7655 pci_set_drvdata(pdev, pf);
7656 pci_save_state(pdev);
7657
7658 /* set up periodic task facility */
7659 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
7660 pf->service_timer_period = HZ;
7661
7662 INIT_WORK(&pf->service_task, i40e_service_task);
7663 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
7664 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
7665 pf->link_check_timeout = jiffies;
7666
8e2773ae
SN		 7667 /* WoL defaults to disabled */
7668 pf->wol_en = false;
7669 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
7670
41c445ff
JB		 7671 /* set up the main switch operations */
7672 i40e_determine_queue_usage(pf);
7673 i40e_init_interrupt_scheme(pf);
7674
7675 /* Set up the *vsi struct based on the number of VSIs in the HW,
7676 * and set up our local tracking of the MAIN PF vsi.
7677 */
7678 len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
7679 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 7680 if (!pf->vsi) {
7681 err = -ENOMEM;
41c445ff 7682 goto err_switch_setup;
ed87ac09 7683 }
41c445ff 7684
bc7d338f 7685 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 7686 if (err) {
7687 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
7688 goto err_vsis;
7689 }
7690
7691 /* The main driver is (mostly) up and happy. We need to set this state
7692 * before setting up the misc vector or we get a race and the vector
7693 * ends up disabled forever.
7694 */
7695 clear_bit(__I40E_DOWN, &pf->state);
7696
7697 /* In case of MSIX we are going to setup the misc vector right here
7698 * to handle admin queue events etc. In case of legacy and MSI
7699 * the misc functionality and queue processing is combined in
7700 * the same vector and that gets setup at open.
7701 */
7702 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7703 err = i40e_setup_misc_vector(pf);
7704 if (err) {
7705 dev_info(&pdev->dev,
7706 "setup of misc vector failed: %d\n", err);
7707 goto err_vsis;
7708 }
7709 }
7710
7711 /* prep for VF support */
7712 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
7713 (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
7714 u32 val;
7715
7716 /* disable link interrupts for VFs */
7717 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
7718 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
7719 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
7720 i40e_flush(hw);
7721 }
7722
93cd765b
ASJ		 7723 pfs_found++;
7724
41c445ff
JB		 7725 i40e_dbg_pf_init(pf);
7726
7727 /* tell the firmware that we're starting */
7728 dv.major_version = DRV_VERSION_MAJOR;
7729 dv.minor_version = DRV_VERSION_MINOR;
7730 dv.build_version = DRV_VERSION_BUILD;
7731 dv.subbuild_version = 0;
7732 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
7733
7734 /* since everything's happy, start the service_task timer */
7735 mod_timer(&pf->service_timer,
7736 round_jiffies(jiffies + pf->service_timer_period));
7737
d4dfb81a
CS		 7738 /* Get the negotiated link width and speed from PCI config space */
7739 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
7740
7741 i40e_set_pci_config_data(hw, link_status);
7742
7743 dev_info(&pdev->dev, "PCI Express: %s %s\n",
7744 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
7745 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
7746 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
7747 "Unknown"),
7748 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
7749 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
7750 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
7751 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
7752 "Unknown"));
7753
7754 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
7755 hw->bus.speed < i40e_bus_speed_8000) {
7756 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
7757 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
7758 }
7759
41c445ff
JB		 7760 return 0;
7761
7762 /* Unwind what we've done if something failed in the setup */
7763err_vsis:
7764 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 7765 i40e_clear_interrupt_scheme(pf);
7766 kfree(pf->vsi);
04b03013
SN		 7767err_switch_setup:
7768 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 7769 del_timer_sync(&pf->service_timer);
7770err_mac_addr:
7771err_configure_lan_hmc:
7772 (void)i40e_shutdown_lan_hmc(hw);
7773err_init_lan_hmc:
7774 kfree(pf->qp_pile);
7775 kfree(pf->irq_pile);
7776err_sw_init:
7777err_adminq_setup:
7778 (void)i40e_shutdown_adminq(hw);
7779err_pf_reset:
7780 iounmap(hw->hw_addr);
7781err_ioremap:
7782 kfree(pf);
7783err_pf_alloc:
7784 pci_disable_pcie_error_reporting(pdev);
7785 pci_release_selected_regions(pdev,
7786 pci_select_bars(pdev, IORESOURCE_MEM));
7787err_pci_reg:
7788err_dma:
7789 pci_disable_device(pdev);
7790 return err;
7791}
7792
7793/**
7794 * i40e_remove - Device removal routine
7795 * @pdev: PCI device information struct
7796 *
7797 * i40e_remove is called by the PCI subsystem to alert the driver
7798 * that is should release a PCI device. This could be caused by a
7799 * Hot-Plug event, or because the driver is going to be removed from
7800 * memory.
7801 **/
7802static void i40e_remove(struct pci_dev *pdev)
7803{
7804 struct i40e_pf *pf = pci_get_drvdata(pdev);
7805 i40e_status ret_code;
7806 u32 reg;
7807 int i;
7808
7809 i40e_dbg_pf_exit(pf);
7810
7811 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
7812 i40e_free_vfs(pf);
7813 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
7814 }
7815
7816 /* no more scheduling of any task */
7817 set_bit(__I40E_DOWN, &pf->state);
7818 del_timer_sync(&pf->service_timer);
7819 cancel_work_sync(&pf->service_task);
7820
7821 i40e_fdir_teardown(pf);
7822
7823 /* If there is a switch structure or any orphans, remove them.
7824 * This will leave only the PF's VSI remaining.
7825 */
7826 for (i = 0; i < I40E_MAX_VEB; i++) {
7827 if (!pf->veb[i])
7828 continue;
7829
7830 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
7831 pf->veb[i]->uplink_seid == 0)
7832 i40e_switch_branch_release(pf->veb[i]);
7833 }
7834
7835 /* Now we can shutdown the PF's VSI, just before we kill
7836 * adminq and hmc.
7837 */
7838 if (pf->vsi[pf->lan_vsi])
7839 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
7840
7841 i40e_stop_misc_vector(pf);
7842 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7843 synchronize_irq(pf->msix_entries[0].vector);
7844 free_irq(pf->msix_entries[0].vector, pf);
7845 }
7846
7847 /* shutdown and destroy the HMC */
7848 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
7849 if (ret_code)
7850 dev_warn(&pdev->dev,
7851 "Failed to destroy the HMC resources: %d\n", ret_code);
7852
7853 /* shutdown the adminq */
41c445ff
JB		 7854 ret_code = i40e_shutdown_adminq(&pf->hw);
7855 if (ret_code)
7856 dev_warn(&pdev->dev,
7857 "Failed to destroy the Admin Queue resources: %d\n",
7858 ret_code);
7859
7860 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
7861 i40e_clear_interrupt_scheme(pf);
7862 for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
7863 if (pf->vsi[i]) {
7864 i40e_vsi_clear_rings(pf->vsi[i]);
7865 i40e_vsi_clear(pf->vsi[i]);
7866 pf->vsi[i] = NULL;
7867 }
7868 }
7869
7870 for (i = 0; i < I40E_MAX_VEB; i++) {
7871 kfree(pf->veb[i]);
7872 pf->veb[i] = NULL;
7873 }
7874
7875 kfree(pf->qp_pile);
7876 kfree(pf->irq_pile);
7877 kfree(pf->sw_config);
7878 kfree(pf->vsi);
7879
7880 /* force a PF reset to clean anything leftover */
7881 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
7882 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7883 i40e_flush(&pf->hw);
7884
7885 iounmap(pf->hw.hw_addr);
7886 kfree(pf);
7887 pci_release_selected_regions(pdev,
7888 pci_select_bars(pdev, IORESOURCE_MEM));
7889
7890 pci_disable_pcie_error_reporting(pdev);
7891 pci_disable_device(pdev);
7892}
7893
7894/**
7895 * i40e_pci_error_detected - warning that something funky happened in PCI land
7896 * @pdev: PCI device information struct
7897 *
7898 * Called to warn that something happened and the error handling steps
7899 * are in progress. Allows the driver to quiesce things, be ready for
7900 * remediation.
7901 **/
7902static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
7903 enum pci_channel_state error)
7904{
7905 struct i40e_pf *pf = pci_get_drvdata(pdev);
7906
7907 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
7908
7909 /* shutdown all operations */
9007bccd
SN		 7910 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
7911 rtnl_lock();
7912 i40e_prep_for_reset(pf);
7913 rtnl_unlock();
7914 }
41c445ff
JB		 7915
7916 /* Request a slot reset */
7917 return PCI_ERS_RESULT_NEED_RESET;
7918}
7919
7920/**
7921 * i40e_pci_error_slot_reset - a PCI slot reset just happened
7922 * @pdev: PCI device information struct
7923 *
7924 * Called to find if the driver can work with the device now that
7925 * the pci slot has been reset. If a basic connection seems good
7926 * (registers are readable and have sane content) then return a
7927 * happy little PCI_ERS_RESULT_xxx.
7928 **/
7929static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
7930{
7931 struct i40e_pf *pf = pci_get_drvdata(pdev);
7932 pci_ers_result_t result;
7933 int err;
7934 u32 reg;
7935
7936 dev_info(&pdev->dev, "%s\n", __func__);
7937 if (pci_enable_device_mem(pdev)) {
7938 dev_info(&pdev->dev,
7939 "Cannot re-enable PCI device after reset.\n");
7940 result = PCI_ERS_RESULT_DISCONNECT;
7941 } else {
7942 pci_set_master(pdev);
7943 pci_restore_state(pdev);
7944 pci_save_state(pdev);
7945 pci_wake_from_d3(pdev, false);
7946
7947 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7948 if (reg == 0)
7949 result = PCI_ERS_RESULT_RECOVERED;
7950 else
7951 result = PCI_ERS_RESULT_DISCONNECT;
7952 }
7953
7954 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7955 if (err) {
7956 dev_info(&pdev->dev,
7957 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7958 err);
7959 /* non-fatal, continue */
7960 }
7961
7962 return result;
7963}
7964
7965/**
7966 * i40e_pci_error_resume - restart operations after PCI error recovery
7967 * @pdev: PCI device information struct
7968 *
7969 * Called to allow the driver to bring things back up after PCI error
7970 * and/or reset recovery has finished.
7971 **/
7972static void i40e_pci_error_resume(struct pci_dev *pdev)
7973{
7974 struct i40e_pf *pf = pci_get_drvdata(pdev);
7975
7976 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 7977 if (test_bit(__I40E_SUSPENDED, &pf->state))
7978 return;
7979
7980 rtnl_lock();
41c445ff 7981 i40e_handle_reset_warning(pf);
9007bccd
SN		 7982 rtnl_lock();
7983}
7984
7985/**
7986 * i40e_shutdown - PCI callback for shutting down
7987 * @pdev: PCI device information struct
7988 **/
7989static void i40e_shutdown(struct pci_dev *pdev)
7990{
7991 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 7992 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 7993
7994 set_bit(__I40E_SUSPENDED, &pf->state);
7995 set_bit(__I40E_DOWN, &pf->state);
7996 rtnl_lock();
7997 i40e_prep_for_reset(pf);
7998 rtnl_unlock();
7999
8e2773ae
SN		 8000 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8001 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8002
9007bccd 8003 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8004 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8005 pci_set_power_state(pdev, PCI_D3hot);
8006 }
8007}
8008
8009#ifdef CONFIG_PM
8010/**
8011 * i40e_suspend - PCI callback for moving to D3
8012 * @pdev: PCI device information struct
8013 **/
8014static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8015{
8016 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8017 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8018
8019 set_bit(__I40E_SUSPENDED, &pf->state);
8020 set_bit(__I40E_DOWN, &pf->state);
8021 rtnl_lock();
8022 i40e_prep_for_reset(pf);
8023 rtnl_unlock();
8024
8e2773ae
SN		 8025 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8026 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8027
8028 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8029 pci_set_power_state(pdev, PCI_D3hot);
8030
8031 return 0;
41c445ff
JB		 8032}
8033
9007bccd
SN		 8034/**
8035 * i40e_resume - PCI callback for waking up from D3
8036 * @pdev: PCI device information struct
8037 **/
8038static int i40e_resume(struct pci_dev *pdev)
8039{
8040 struct i40e_pf *pf = pci_get_drvdata(pdev);
8041 u32 err;
8042
8043 pci_set_power_state(pdev, PCI_D0);
8044 pci_restore_state(pdev);
8045 /* pci_restore_state() clears dev->state_saves, so
8046 * call pci_save_state() again to restore it.
8047 */
8048 pci_save_state(pdev);
8049
8050 err = pci_enable_device_mem(pdev);
8051 if (err) {
8052 dev_err(&pdev->dev,
8053 "%s: Cannot enable PCI device from suspend\n",
8054 __func__);
8055 return err;
8056 }
8057 pci_set_master(pdev);
8058
8059 /* no wakeup events while running */
8060 pci_wake_from_d3(pdev, false);
8061
8062 /* handling the reset will rebuild the device state */
8063 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8064 clear_bit(__I40E_DOWN, &pf->state);
8065 rtnl_lock();
8066 i40e_reset_and_rebuild(pf, false);
8067 rtnl_unlock();
8068 }
8069
8070 return 0;
8071}
8072
8073#endif
41c445ff
JB		 8074static const struct pci_error_handlers i40e_err_handler = {
8075 .error_detected = i40e_pci_error_detected,
8076 .slot_reset = i40e_pci_error_slot_reset,
8077 .resume = i40e_pci_error_resume,
8078};
8079
8080static struct pci_driver i40e_driver = {
8081 .name = i40e_driver_name,
8082 .id_table = i40e_pci_tbl,
8083 .probe = i40e_probe,
8084 .remove = i40e_remove,
9007bccd
SN		 8085#ifdef CONFIG_PM
8086 .suspend = i40e_suspend,
8087 .resume = i40e_resume,
8088#endif
8089 .shutdown = i40e_shutdown,
41c445ff
JB		 8090 .err_handler = &i40e_err_handler,
8091 .sriov_configure = i40e_pci_sriov_configure,
8092};
8093
8094/**
8095 * i40e_init_module - Driver registration routine
8096 *
8097 * i40e_init_module is the first routine called when the driver is
8098 * loaded. All it does is register with the PCI subsystem.
8099 **/
8100static int __init i40e_init_module(void)
8101{
8102 pr_info("%s: %s - version %s\n", i40e_driver_name,
8103 i40e_driver_string, i40e_driver_version_str);
8104 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8105 i40e_dbg_init();
8106 return pci_register_driver(&i40e_driver);
8107}
8108module_init(i40e_init_module);
8109
8110/**
8111 * i40e_exit_module - Driver exit cleanup routine
8112 *
8113 * i40e_exit_module is called just before the driver is removed
8114 * from memory.
8115 **/
8116static void __exit i40e_exit_module(void)
8117{
8118 pci_unregister_driver(&i40e_driver);
8119 i40e_dbg_exit();
8120}
8121module_exit(i40e_exit_module);
Linux kernel - Deliverables
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