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i40e: don't complain about removing non-existent addresses
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
a1c9a9d9
JK		 30#ifdef CONFIG_I40E_VXLAN
31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
40#define DRV_VERSION_MAJOR 0
e454d6bf 41#define DRV_VERSION_MINOR 4
eeb6b645 42#define DRV_VERSION_BUILD 5
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
cbf61325 58static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 59static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 60
61/* i40e_pci_tbl - PCI Device ID Table
62 *
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
ab60085e 69 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 70 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
41c445ff
JB		 77 /* required last entry */
78 {0, }
79};
80MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
81
82#define I40E_MAX_VF_COUNT 128
83static int debug = -1;
84module_param(debug, int, 0);
85MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
86
87MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
88MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
89MODULE_LICENSE("GPL");
90MODULE_VERSION(DRV_VERSION);
91
92/**
93 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
94 * @hw: pointer to the HW structure
95 * @mem: ptr to mem struct to fill out
96 * @size: size of memory requested
97 * @alignment: what to align the allocation to
98 **/
99int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
100 u64 size, u32 alignment)
101{
102 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
103
104 mem->size = ALIGN(size, alignment);
105 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
106 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 107 if (!mem->va)
108 return -ENOMEM;
41c445ff 109
93bc73b8 110 return 0;
41c445ff
JB		 111}
112
113/**
114 * i40e_free_dma_mem_d - OS specific memory free for shared code
115 * @hw: pointer to the HW structure
116 * @mem: ptr to mem struct to free
117 **/
118int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
119{
120 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
121
122 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
123 mem->va = NULL;
124 mem->pa = 0;
125 mem->size = 0;
126
127 return 0;
128}
129
130/**
131 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to fill out
134 * @size: size of memory requested
135 **/
136int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
137 u32 size)
138{
139 mem->size = size;
140 mem->va = kzalloc(size, GFP_KERNEL);
141
93bc73b8
JB		 142 if (!mem->va)
143 return -ENOMEM;
41c445ff 144
93bc73b8 145 return 0;
41c445ff
JB		 146}
147
148/**
149 * i40e_free_virt_mem_d - OS specific memory free for shared code
150 * @hw: pointer to the HW structure
151 * @mem: ptr to mem struct to free
152 **/
153int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
154{
155 /* it's ok to kfree a NULL pointer */
156 kfree(mem->va);
157 mem->va = NULL;
158 mem->size = 0;
159
160 return 0;
161}
162
163/**
164 * i40e_get_lump - find a lump of free generic resource
165 * @pf: board private structure
166 * @pile: the pile of resource to search
167 * @needed: the number of items needed
168 * @id: an owner id to stick on the items assigned
169 *
170 * Returns the base item index of the lump, or negative for error
171 *
172 * The search_hint trick and lack of advanced fit-finding only work
173 * because we're highly likely to have all the same size lump requests.
174 * Linear search time and any fragmentation should be minimal.
175 **/
176static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
177 u16 needed, u16 id)
178{
179 int ret = -ENOMEM;
ddf434ac 180 int i, j;
41c445ff
JB		 181
182 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
183 dev_info(&pf->pdev->dev,
184 "param err: pile=%p needed=%d id=0x%04x\n",
185 pile, needed, id);
186 return -EINVAL;
187 }
188
189 /* start the linear search with an imperfect hint */
190 i = pile->search_hint;
ddf434ac 191 while (i < pile->num_entries) {
41c445ff
JB		 192 /* skip already allocated entries */
193 if (pile->list[i] & I40E_PILE_VALID_BIT) {
194 i++;
195 continue;
196 }
197
198 /* do we have enough in this lump? */
199 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
200 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
201 break;
202 }
203
204 if (j == needed) {
205 /* there was enough, so assign it to the requestor */
206 for (j = 0; j < needed; j++)
207 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
208 ret = i;
209 pile->search_hint = i + j;
ddf434ac 210 break;
41c445ff
JB		 211 } else {
212 /* not enough, so skip over it and continue looking */
213 i += j;
214 }
215 }
216
217 return ret;
218}
219
220/**
221 * i40e_put_lump - return a lump of generic resource
222 * @pile: the pile of resource to search
223 * @index: the base item index
224 * @id: the owner id of the items assigned
225 *
226 * Returns the count of items in the lump
227 **/
228static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
229{
230 int valid_id = (id | I40E_PILE_VALID_BIT);
231 int count = 0;
232 int i;
233
234 if (!pile || index >= pile->num_entries)
235 return -EINVAL;
236
237 for (i = index;
238 i < pile->num_entries && pile->list[i] == valid_id;
239 i++) {
240 pile->list[i] = 0;
241 count++;
242 }
243
244 if (count && index < pile->search_hint)
245 pile->search_hint = index;
246
247 return count;
248}
249
250/**
251 * i40e_service_event_schedule - Schedule the service task to wake up
252 * @pf: board private structure
253 *
254 * If not already scheduled, this puts the task into the work queue
255 **/
256static void i40e_service_event_schedule(struct i40e_pf *pf)
257{
258 if (!test_bit(__I40E_DOWN, &pf->state) &&
259 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
260 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
261 schedule_work(&pf->service_task);
262}
263
264/**
265 * i40e_tx_timeout - Respond to a Tx Hang
266 * @netdev: network interface device structure
267 *
268 * If any port has noticed a Tx timeout, it is likely that the whole
269 * device is munged, not just the one netdev port, so go for the full
270 * reset.
271 **/
272static void i40e_tx_timeout(struct net_device *netdev)
273{
274 struct i40e_netdev_priv *np = netdev_priv(netdev);
275 struct i40e_vsi *vsi = np->vsi;
276 struct i40e_pf *pf = vsi->back;
277
278 pf->tx_timeout_count++;
279
280 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
281 pf->tx_timeout_recovery_level = 0;
282 pf->tx_timeout_last_recovery = jiffies;
283 netdev_info(netdev, "tx_timeout recovery level %d\n",
284 pf->tx_timeout_recovery_level);
285
286 switch (pf->tx_timeout_recovery_level) {
287 case 0:
288 /* disable and re-enable queues for the VSI */
289 if (in_interrupt()) {
290 set_bit(__I40E_REINIT_REQUESTED, &pf->state);
291 set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
292 } else {
293 i40e_vsi_reinit_locked(vsi);
294 }
295 break;
296 case 1:
297 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
298 break;
299 case 2:
300 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
301 break;
302 case 3:
303 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
304 break;
305 default:
306 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
e108b0e3 307 set_bit(__I40E_DOWN, &vsi->state);
41c445ff
JB		 308 i40e_down(vsi);
309 break;
310 }
311 i40e_service_event_schedule(pf);
312 pf->tx_timeout_recovery_level++;
313}
314
315/**
316 * i40e_release_rx_desc - Store the new tail and head values
317 * @rx_ring: ring to bump
318 * @val: new head index
319 **/
320static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
321{
322 rx_ring->next_to_use = val;
323
324 /* Force memory writes to complete before letting h/w
325 * know there are new descriptors to fetch. (Only
326 * applicable for weak-ordered memory model archs,
327 * such as IA-64).
328 */
329 wmb();
330 writel(val, rx_ring->tail);
331}
332
333/**
334 * i40e_get_vsi_stats_struct - Get System Network Statistics
335 * @vsi: the VSI we care about
336 *
337 * Returns the address of the device statistics structure.
338 * The statistics are actually updated from the service task.
339 **/
340struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
341{
342 return &vsi->net_stats;
343}
344
345/**
346 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
347 * @netdev: network interface device structure
348 *
349 * Returns the address of the device statistics structure.
350 * The statistics are actually updated from the service task.
351 **/
352static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
353 struct net_device *netdev,
980e9b11 354 struct rtnl_link_stats64 *stats)
41c445ff
JB		 355{
356 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 357 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 358 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 359 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
360 int i;
361
bc7d338f
ASJ		 362 if (test_bit(__I40E_DOWN, &vsi->state))
363 return stats;
364
3c325ced
JB		 365 if (!vsi->tx_rings)
366 return stats;
367
980e9b11
AD		 368 rcu_read_lock();
369 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 370 u64 bytes, packets;
371 unsigned int start;
372
373 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
374 if (!tx_ring)
375 continue;
376
377 do {
57a7744e 378 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 379 packets = tx_ring->stats.packets;
380 bytes = tx_ring->stats.bytes;
57a7744e 381 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 382
383 stats->tx_packets += packets;
384 stats->tx_bytes += bytes;
385 rx_ring = &tx_ring[1];
386
387 do {
57a7744e 388 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 389 packets = rx_ring->stats.packets;
390 bytes = rx_ring->stats.bytes;
57a7744e 391 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 392
980e9b11
AD		 393 stats->rx_packets += packets;
394 stats->rx_bytes += bytes;
395 }
396 rcu_read_unlock();
397
a5282f44 398 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 399 stats->multicast = vsi_stats->multicast;
400 stats->tx_errors = vsi_stats->tx_errors;
401 stats->tx_dropped = vsi_stats->tx_dropped;
402 stats->rx_errors = vsi_stats->rx_errors;
403 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
404 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 405
980e9b11 406 return stats;
41c445ff
JB		 407}
408
409/**
410 * i40e_vsi_reset_stats - Resets all stats of the given vsi
411 * @vsi: the VSI to have its stats reset
412 **/
413void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
414{
415 struct rtnl_link_stats64 *ns;
416 int i;
417
418 if (!vsi)
419 return;
420
421 ns = i40e_get_vsi_stats_struct(vsi);
422 memset(ns, 0, sizeof(*ns));
423 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
424 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
425 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 426 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 427 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 428 memset(&vsi->rx_rings[i]->stats, 0 ,
429 sizeof(vsi->rx_rings[i]->stats));
430 memset(&vsi->rx_rings[i]->rx_stats, 0 ,
431 sizeof(vsi->rx_rings[i]->rx_stats));
432 memset(&vsi->tx_rings[i]->stats, 0 ,
433 sizeof(vsi->tx_rings[i]->stats));
434 memset(&vsi->tx_rings[i]->tx_stats, 0,
435 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 436 }
8e9dca53 437 }
41c445ff
JB		 438 vsi->stat_offsets_loaded = false;
439}
440
441/**
442 * i40e_pf_reset_stats - Reset all of the stats for the given pf
443 * @pf: the PF to be reset
444 **/
445void i40e_pf_reset_stats(struct i40e_pf *pf)
446{
447 memset(&pf->stats, 0, sizeof(pf->stats));
448 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
449 pf->stat_offsets_loaded = false;
450}
451
452/**
453 * i40e_stat_update48 - read and update a 48 bit stat from the chip
454 * @hw: ptr to the hardware info
455 * @hireg: the high 32 bit reg to read
456 * @loreg: the low 32 bit reg to read
457 * @offset_loaded: has the initial offset been loaded yet
458 * @offset: ptr to current offset value
459 * @stat: ptr to the stat
460 *
461 * Since the device stats are not reset at PFReset, they likely will not
462 * be zeroed when the driver starts. We'll save the first values read
463 * and use them as offsets to be subtracted from the raw values in order
464 * to report stats that count from zero. In the process, we also manage
465 * the potential roll-over.
466 **/
467static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
468 bool offset_loaded, u64 *offset, u64 *stat)
469{
470 u64 new_data;
471
ab60085e 472 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 473 new_data = rd32(hw, loreg);
474 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
475 } else {
476 new_data = rd64(hw, loreg);
477 }
478 if (!offset_loaded)
479 *offset = new_data;
480 if (likely(new_data >= *offset))
481 *stat = new_data - *offset;
482 else
483 *stat = (new_data + ((u64)1 << 48)) - *offset;
484 *stat &= 0xFFFFFFFFFFFFULL;
485}
486
487/**
488 * i40e_stat_update32 - read and update a 32 bit stat from the chip
489 * @hw: ptr to the hardware info
490 * @reg: the hw reg to read
491 * @offset_loaded: has the initial offset been loaded yet
492 * @offset: ptr to current offset value
493 * @stat: ptr to the stat
494 **/
495static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
496 bool offset_loaded, u64 *offset, u64 *stat)
497{
498 u32 new_data;
499
500 new_data = rd32(hw, reg);
501 if (!offset_loaded)
502 *offset = new_data;
503 if (likely(new_data >= *offset))
504 *stat = (u32)(new_data - *offset);
505 else
506 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
507}
508
509/**
510 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
511 * @vsi: the VSI to be updated
512 **/
513void i40e_update_eth_stats(struct i40e_vsi *vsi)
514{
515 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
516 struct i40e_pf *pf = vsi->back;
517 struct i40e_hw *hw = &pf->hw;
518 struct i40e_eth_stats *oes;
519 struct i40e_eth_stats *es; /* device's eth stats */
520
521 es = &vsi->eth_stats;
522 oes = &vsi->eth_stats_offsets;
523
524 /* Gather up the stats that the hw collects */
525 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
526 vsi->stat_offsets_loaded,
527 &oes->tx_errors, &es->tx_errors);
528 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
529 vsi->stat_offsets_loaded,
530 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 531 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
532 vsi->stat_offsets_loaded,
533 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
534 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
535 vsi->stat_offsets_loaded,
536 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 537
538 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
539 I40E_GLV_GORCL(stat_idx),
540 vsi->stat_offsets_loaded,
541 &oes->rx_bytes, &es->rx_bytes);
542 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
543 I40E_GLV_UPRCL(stat_idx),
544 vsi->stat_offsets_loaded,
545 &oes->rx_unicast, &es->rx_unicast);
546 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
547 I40E_GLV_MPRCL(stat_idx),
548 vsi->stat_offsets_loaded,
549 &oes->rx_multicast, &es->rx_multicast);
550 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
551 I40E_GLV_BPRCL(stat_idx),
552 vsi->stat_offsets_loaded,
553 &oes->rx_broadcast, &es->rx_broadcast);
554
555 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
556 I40E_GLV_GOTCL(stat_idx),
557 vsi->stat_offsets_loaded,
558 &oes->tx_bytes, &es->tx_bytes);
559 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
560 I40E_GLV_UPTCL(stat_idx),
561 vsi->stat_offsets_loaded,
562 &oes->tx_unicast, &es->tx_unicast);
563 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
564 I40E_GLV_MPTCL(stat_idx),
565 vsi->stat_offsets_loaded,
566 &oes->tx_multicast, &es->tx_multicast);
567 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
568 I40E_GLV_BPTCL(stat_idx),
569 vsi->stat_offsets_loaded,
570 &oes->tx_broadcast, &es->tx_broadcast);
571 vsi->stat_offsets_loaded = true;
572}
573
574/**
575 * i40e_update_veb_stats - Update Switch component statistics
576 * @veb: the VEB being updated
577 **/
578static void i40e_update_veb_stats(struct i40e_veb *veb)
579{
580 struct i40e_pf *pf = veb->pf;
581 struct i40e_hw *hw = &pf->hw;
582 struct i40e_eth_stats *oes;
583 struct i40e_eth_stats *es; /* device's eth stats */
584 int idx = 0;
585
586 idx = veb->stats_idx;
587 es = &veb->stats;
588 oes = &veb->stats_offsets;
589
590 /* Gather up the stats that the hw collects */
591 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
592 veb->stat_offsets_loaded,
593 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 594 if (hw->revision_id > 0)
595 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
596 veb->stat_offsets_loaded,
597 &oes->rx_unknown_protocol,
598 &es->rx_unknown_protocol);
41c445ff
JB		 599 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
600 veb->stat_offsets_loaded,
601 &oes->rx_bytes, &es->rx_bytes);
602 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
603 veb->stat_offsets_loaded,
604 &oes->rx_unicast, &es->rx_unicast);
605 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
606 veb->stat_offsets_loaded,
607 &oes->rx_multicast, &es->rx_multicast);
608 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
609 veb->stat_offsets_loaded,
610 &oes->rx_broadcast, &es->rx_broadcast);
611
612 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
613 veb->stat_offsets_loaded,
614 &oes->tx_bytes, &es->tx_bytes);
615 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
616 veb->stat_offsets_loaded,
617 &oes->tx_unicast, &es->tx_unicast);
618 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
619 veb->stat_offsets_loaded,
620 &oes->tx_multicast, &es->tx_multicast);
621 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
622 veb->stat_offsets_loaded,
623 &oes->tx_broadcast, &es->tx_broadcast);
624 veb->stat_offsets_loaded = true;
625}
626
627/**
628 * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
629 * @pf: the corresponding PF
630 *
631 * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
632 **/
633static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
634{
635 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
636 struct i40e_hw_port_stats *nsd = &pf->stats;
637 struct i40e_hw *hw = &pf->hw;
638 u64 xoff = 0;
639 u16 i, v;
640
641 if ((hw->fc.current_mode != I40E_FC_FULL) &&
642 (hw->fc.current_mode != I40E_FC_RX_PAUSE))
643 return;
644
645 xoff = nsd->link_xoff_rx;
646 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
647 pf->stat_offsets_loaded,
648 &osd->link_xoff_rx, &nsd->link_xoff_rx);
649
650 /* No new LFC xoff rx */
651 if (!(nsd->link_xoff_rx - xoff))
652 return;
653
654 /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
505682cd 655 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 656 struct i40e_vsi *vsi = pf->vsi[v];
657
ddfda80f 658 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 659 continue;
660
661 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 662 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 663 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
664 }
665 }
666}
667
668/**
669 * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
670 * @pf: the corresponding PF
671 *
672 * Update the Rx XOFF counter (PAUSE frames) in PFC mode
673 **/
674static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
675{
676 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
677 struct i40e_hw_port_stats *nsd = &pf->stats;
678 bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
679 struct i40e_dcbx_config *dcb_cfg;
680 struct i40e_hw *hw = &pf->hw;
681 u16 i, v;
682 u8 tc;
683
684 dcb_cfg = &hw->local_dcbx_config;
685
686 /* See if DCB enabled with PFC TC */
687 if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
688 !(dcb_cfg->pfc.pfcenable)) {
689 i40e_update_link_xoff_rx(pf);
690 return;
691 }
692
693 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
694 u64 prio_xoff = nsd->priority_xoff_rx[i];
695 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
696 pf->stat_offsets_loaded,
697 &osd->priority_xoff_rx[i],
698 &nsd->priority_xoff_rx[i]);
699
700 /* No new PFC xoff rx */
701 if (!(nsd->priority_xoff_rx[i] - prio_xoff))
702 continue;
703 /* Get the TC for given priority */
704 tc = dcb_cfg->etscfg.prioritytable[i];
705 xoff[tc] = true;
706 }
707
708 /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
505682cd 709 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 710 struct i40e_vsi *vsi = pf->vsi[v];
711
ddfda80f 712 if (!vsi || !vsi->tx_rings[0])
41c445ff
JB		 713 continue;
714
715 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 716 struct i40e_ring *ring = vsi->tx_rings[i];
41c445ff
JB		 717
718 tc = ring->dcb_tc;
719 if (xoff[tc])
720 clear_bit(__I40E_HANG_CHECK_ARMED,
721 &ring->state);
722 }
723 }
724}
725
726/**
7812fddc 727 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 728 * @vsi: the VSI to be updated
729 *
730 * There are a few instances where we store the same stat in a
731 * couple of different structs. This is partly because we have
732 * the netdev stats that need to be filled out, which is slightly
733 * different from the "eth_stats" defined by the chip and used in
7812fddc 734 * VF communications. We sort it out here.
41c445ff 735 **/
7812fddc 736static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 737{
738 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 739 struct rtnl_link_stats64 *ons;
740 struct rtnl_link_stats64 *ns; /* netdev stats */
741 struct i40e_eth_stats *oes;
742 struct i40e_eth_stats *es; /* device's eth stats */
743 u32 tx_restart, tx_busy;
744 u32 rx_page, rx_buf;
745 u64 rx_p, rx_b;
746 u64 tx_p, tx_b;
41c445ff
JB		 747 u16 q;
748
749 if (test_bit(__I40E_DOWN, &vsi->state) ||
750 test_bit(__I40E_CONFIG_BUSY, &pf->state))
751 return;
752
753 ns = i40e_get_vsi_stats_struct(vsi);
754 ons = &vsi->net_stats_offsets;
755 es = &vsi->eth_stats;
756 oes = &vsi->eth_stats_offsets;
757
758 /* Gather up the netdev and vsi stats that the driver collects
759 * on the fly during packet processing
760 */
761 rx_b = rx_p = 0;
762 tx_b = tx_p = 0;
763 tx_restart = tx_busy = 0;
764 rx_page = 0;
765 rx_buf = 0;
980e9b11 766 rcu_read_lock();
41c445ff
JB		 767 for (q = 0; q < vsi->num_queue_pairs; q++) {
768 struct i40e_ring *p;
980e9b11
AD		 769 u64 bytes, packets;
770 unsigned int start;
771
772 /* locate Tx ring */
773 p = ACCESS_ONCE(vsi->tx_rings[q]);
774
775 do {
57a7744e 776 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 777 packets = p->stats.packets;
778 bytes = p->stats.bytes;
57a7744e 779 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 780 tx_b += bytes;
781 tx_p += packets;
782 tx_restart += p->tx_stats.restart_queue;
783 tx_busy += p->tx_stats.tx_busy;
41c445ff 784
980e9b11
AD		 785 /* Rx queue is part of the same block as Tx queue */
786 p = &p[1];
787 do {
57a7744e 788 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 789 packets = p->stats.packets;
790 bytes = p->stats.bytes;
57a7744e 791 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 792 rx_b += bytes;
793 rx_p += packets;
420136cc
MW		 794 rx_buf += p->rx_stats.alloc_buff_failed;
795 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 796 }
980e9b11 797 rcu_read_unlock();
41c445ff
JB		 798 vsi->tx_restart = tx_restart;
799 vsi->tx_busy = tx_busy;
800 vsi->rx_page_failed = rx_page;
801 vsi->rx_buf_failed = rx_buf;
802
803 ns->rx_packets = rx_p;
804 ns->rx_bytes = rx_b;
805 ns->tx_packets = tx_p;
806 ns->tx_bytes = tx_b;
807
41c445ff 808 /* update netdev stats from eth stats */
7812fddc 809 i40e_update_eth_stats(vsi);
41c445ff
JB		 810 ons->tx_errors = oes->tx_errors;
811 ns->tx_errors = es->tx_errors;
812 ons->multicast = oes->rx_multicast;
813 ns->multicast = es->rx_multicast;
41a9e55c
SN		 814 ons->rx_dropped = oes->rx_discards;
815 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 816 ons->tx_dropped = oes->tx_discards;
817 ns->tx_dropped = es->tx_discards;
818
7812fddc 819 /* pull in a couple PF stats if this is the main vsi */
41c445ff 820 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 821 ns->rx_crc_errors = pf->stats.crc_errors;
822 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
823 ns->rx_length_errors = pf->stats.rx_length_errors;
824 }
825}
41c445ff 826
7812fddc
SN		 827/**
828 * i40e_update_pf_stats - Update the pf statistics counters.
829 * @pf: the PF to be updated
830 **/
831static void i40e_update_pf_stats(struct i40e_pf *pf)
832{
833 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
834 struct i40e_hw_port_stats *nsd = &pf->stats;
835 struct i40e_hw *hw = &pf->hw;
836 u32 val;
837 int i;
41c445ff 838
7812fddc
SN		 839 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
840 I40E_GLPRT_GORCL(hw->port),
841 pf->stat_offsets_loaded,
842 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
843 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
844 I40E_GLPRT_GOTCL(hw->port),
845 pf->stat_offsets_loaded,
846 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
847 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
848 pf->stat_offsets_loaded,
849 &osd->eth.rx_discards,
850 &nsd->eth.rx_discards);
851 i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
852 pf->stat_offsets_loaded,
853 &osd->eth.tx_discards,
854 &nsd->eth.tx_discards);
532d283d
SN		 855
856 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
857 I40E_GLPRT_UPRCL(hw->port),
858 pf->stat_offsets_loaded,
859 &osd->eth.rx_unicast,
860 &nsd->eth.rx_unicast);
7812fddc
SN		 861 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
862 I40E_GLPRT_MPRCL(hw->port),
863 pf->stat_offsets_loaded,
864 &osd->eth.rx_multicast,
865 &nsd->eth.rx_multicast);
532d283d
SN		 866 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
867 I40E_GLPRT_BPRCL(hw->port),
868 pf->stat_offsets_loaded,
869 &osd->eth.rx_broadcast,
870 &nsd->eth.rx_broadcast);
871 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
872 I40E_GLPRT_UPTCL(hw->port),
873 pf->stat_offsets_loaded,
874 &osd->eth.tx_unicast,
875 &nsd->eth.tx_unicast);
876 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
877 I40E_GLPRT_MPTCL(hw->port),
878 pf->stat_offsets_loaded,
879 &osd->eth.tx_multicast,
880 &nsd->eth.tx_multicast);
881 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
882 I40E_GLPRT_BPTCL(hw->port),
883 pf->stat_offsets_loaded,
884 &osd->eth.tx_broadcast,
885 &nsd->eth.tx_broadcast);
41c445ff 886
7812fddc
SN		 887 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
888 pf->stat_offsets_loaded,
889 &osd->tx_dropped_link_down,
890 &nsd->tx_dropped_link_down);
41c445ff 891
7812fddc
SN		 892 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
893 pf->stat_offsets_loaded,
894 &osd->crc_errors, &nsd->crc_errors);
41c445ff 895
7812fddc
SN		 896 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
897 pf->stat_offsets_loaded,
898 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 899
7812fddc
SN		 900 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
901 pf->stat_offsets_loaded,
902 &osd->mac_local_faults,
903 &nsd->mac_local_faults);
904 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
905 pf->stat_offsets_loaded,
906 &osd->mac_remote_faults,
907 &nsd->mac_remote_faults);
41c445ff 908
7812fddc
SN		 909 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
910 pf->stat_offsets_loaded,
911 &osd->rx_length_errors,
912 &nsd->rx_length_errors);
41c445ff 913
7812fddc
SN		 914 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
915 pf->stat_offsets_loaded,
916 &osd->link_xon_rx, &nsd->link_xon_rx);
917 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->link_xon_tx, &nsd->link_xon_tx);
920 i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
921 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
922 pf->stat_offsets_loaded,
923 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 924
7812fddc
SN		 925 for (i = 0; i < 8; i++) {
926 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 927 pf->stat_offsets_loaded,
7812fddc
SN		 928 &osd->priority_xon_rx[i],
929 &nsd->priority_xon_rx[i]);
930 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 931 pf->stat_offsets_loaded,
7812fddc
SN		 932 &osd->priority_xon_tx[i],
933 &nsd->priority_xon_tx[i]);
934 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 935 pf->stat_offsets_loaded,
7812fddc
SN		 936 &osd->priority_xoff_tx[i],
937 &nsd->priority_xoff_tx[i]);
938 i40e_stat_update32(hw,
939 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
41c445ff 940 pf->stat_offsets_loaded,
7812fddc
SN		 941 &osd->priority_xon_2_xoff[i],
942 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 943 }
944
7812fddc
SN		 945 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
946 I40E_GLPRT_PRC64L(hw->port),
947 pf->stat_offsets_loaded,
948 &osd->rx_size_64, &nsd->rx_size_64);
949 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
950 I40E_GLPRT_PRC127L(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->rx_size_127, &nsd->rx_size_127);
953 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
954 I40E_GLPRT_PRC255L(hw->port),
955 pf->stat_offsets_loaded,
956 &osd->rx_size_255, &nsd->rx_size_255);
957 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
958 I40E_GLPRT_PRC511L(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->rx_size_511, &nsd->rx_size_511);
961 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
962 I40E_GLPRT_PRC1023L(hw->port),
963 pf->stat_offsets_loaded,
964 &osd->rx_size_1023, &nsd->rx_size_1023);
965 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
966 I40E_GLPRT_PRC1522L(hw->port),
967 pf->stat_offsets_loaded,
968 &osd->rx_size_1522, &nsd->rx_size_1522);
969 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
970 I40E_GLPRT_PRC9522L(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_size_big, &nsd->rx_size_big);
973
974 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
975 I40E_GLPRT_PTC64L(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->tx_size_64, &nsd->tx_size_64);
978 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
979 I40E_GLPRT_PTC127L(hw->port),
980 pf->stat_offsets_loaded,
981 &osd->tx_size_127, &nsd->tx_size_127);
982 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
983 I40E_GLPRT_PTC255L(hw->port),
984 pf->stat_offsets_loaded,
985 &osd->tx_size_255, &nsd->tx_size_255);
986 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
987 I40E_GLPRT_PTC511L(hw->port),
988 pf->stat_offsets_loaded,
989 &osd->tx_size_511, &nsd->tx_size_511);
990 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
991 I40E_GLPRT_PTC1023L(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->tx_size_1023, &nsd->tx_size_1023);
994 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
995 I40E_GLPRT_PTC1522L(hw->port),
996 pf->stat_offsets_loaded,
997 &osd->tx_size_1522, &nsd->tx_size_1522);
998 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
999 I40E_GLPRT_PTC9522L(hw->port),
1000 pf->stat_offsets_loaded,
1001 &osd->tx_size_big, &nsd->tx_size_big);
1002
1003 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1004 pf->stat_offsets_loaded,
1005 &osd->rx_undersize, &nsd->rx_undersize);
1006 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->rx_fragments, &nsd->rx_fragments);
1009 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1010 pf->stat_offsets_loaded,
1011 &osd->rx_oversize, &nsd->rx_oversize);
1012 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1013 pf->stat_offsets_loaded,
1014 &osd->rx_jabber, &nsd->rx_jabber);
1015
1016 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1017 nsd->tx_lpi_status =
1018 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1019 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1020 nsd->rx_lpi_status =
1021 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1022 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1023 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1024 pf->stat_offsets_loaded,
1025 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1026 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1027 pf->stat_offsets_loaded,
1028 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1029
41c445ff
JB		 1030 pf->stat_offsets_loaded = true;
1031}
1032
7812fddc
SN		 1033/**
1034 * i40e_update_stats - Update the various statistics counters.
1035 * @vsi: the VSI to be updated
1036 *
1037 * Update the various stats for this VSI and its related entities.
1038 **/
1039void i40e_update_stats(struct i40e_vsi *vsi)
1040{
1041 struct i40e_pf *pf = vsi->back;
1042
1043 if (vsi == pf->vsi[pf->lan_vsi])
1044 i40e_update_pf_stats(pf);
1045
1046 i40e_update_vsi_stats(vsi);
1047}
1048
41c445ff
JB		 1049/**
1050 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1051 * @vsi: the VSI to be searched
1052 * @macaddr: the MAC address
1053 * @vlan: the vlan
1054 * @is_vf: make sure its a vf filter, else doesn't matter
1055 * @is_netdev: make sure its a netdev filter, else doesn't matter
1056 *
1057 * Returns ptr to the filter object or NULL
1058 **/
1059static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1060 u8 *macaddr, s16 vlan,
1061 bool is_vf, bool is_netdev)
1062{
1063 struct i40e_mac_filter *f;
1064
1065 if (!vsi || !macaddr)
1066 return NULL;
1067
1068 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1069 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1070 (vlan == f->vlan) &&
1071 (!is_vf || f->is_vf) &&
1072 (!is_netdev || f->is_netdev))
1073 return f;
1074 }
1075 return NULL;
1076}
1077
1078/**
1079 * i40e_find_mac - Find a mac addr in the macvlan filters list
1080 * @vsi: the VSI to be searched
1081 * @macaddr: the MAC address we are searching for
1082 * @is_vf: make sure its a vf filter, else doesn't matter
1083 * @is_netdev: make sure its a netdev filter, else doesn't matter
1084 *
1085 * Returns the first filter with the provided MAC address or NULL if
1086 * MAC address was not found
1087 **/
1088struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1089 bool is_vf, bool is_netdev)
1090{
1091 struct i40e_mac_filter *f;
1092
1093 if (!vsi || !macaddr)
1094 return NULL;
1095
1096 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1097 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1098 (!is_vf || f->is_vf) &&
1099 (!is_netdev || f->is_netdev))
1100 return f;
1101 }
1102 return NULL;
1103}
1104
1105/**
1106 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1107 * @vsi: the VSI to be searched
1108 *
1109 * Returns true if VSI is in vlan mode or false otherwise
1110 **/
1111bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1112{
1113 struct i40e_mac_filter *f;
1114
1115 /* Only -1 for all the filters denotes not in vlan mode
1116 * so we have to go through all the list in order to make sure
1117 */
1118 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1119 if (f->vlan >= 0)
1120 return true;
1121 }
1122
1123 return false;
1124}
1125
1126/**
1127 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1128 * @vsi: the VSI to be searched
1129 * @macaddr: the mac address to be filtered
1130 * @is_vf: true if it is a vf
1131 * @is_netdev: true if it is a netdev
1132 *
1133 * Goes through all the macvlan filters and adds a
1134 * macvlan filter for each unique vlan that already exists
1135 *
1136 * Returns first filter found on success, else NULL
1137 **/
1138struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1139 bool is_vf, bool is_netdev)
1140{
1141 struct i40e_mac_filter *f;
1142
1143 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1144 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1145 is_vf, is_netdev)) {
1146 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1147 is_vf, is_netdev))
41c445ff
JB		 1148 return NULL;
1149 }
1150 }
1151
1152 return list_first_entry_or_null(&vsi->mac_filter_list,
1153 struct i40e_mac_filter, list);
1154}
1155
1156/**
1157 * i40e_add_filter - Add a mac/vlan filter to the VSI
1158 * @vsi: the VSI to be searched
1159 * @macaddr: the MAC address
1160 * @vlan: the vlan
1161 * @is_vf: make sure its a vf filter, else doesn't matter
1162 * @is_netdev: make sure its a netdev filter, else doesn't matter
1163 *
1164 * Returns ptr to the filter object or NULL when no memory available.
1165 **/
1166struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1167 u8 *macaddr, s16 vlan,
1168 bool is_vf, bool is_netdev)
1169{
1170 struct i40e_mac_filter *f;
1171
1172 if (!vsi || !macaddr)
1173 return NULL;
1174
1175 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1176 if (!f) {
1177 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1178 if (!f)
1179 goto add_filter_out;
1180
1181 memcpy(f->macaddr, macaddr, ETH_ALEN);
1182 f->vlan = vlan;
1183 f->changed = true;
1184
1185 INIT_LIST_HEAD(&f->list);
1186 list_add(&f->list, &vsi->mac_filter_list);
1187 }
1188
1189 /* increment counter and add a new flag if needed */
1190 if (is_vf) {
1191 if (!f->is_vf) {
1192 f->is_vf = true;
1193 f->counter++;
1194 }
1195 } else if (is_netdev) {
1196 if (!f->is_netdev) {
1197 f->is_netdev = true;
1198 f->counter++;
1199 }
1200 } else {
1201 f->counter++;
1202 }
1203
1204 /* changed tells sync_filters_subtask to
1205 * push the filter down to the firmware
1206 */
1207 if (f->changed) {
1208 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1209 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1210 }
1211
1212add_filter_out:
1213 return f;
1214}
1215
1216/**
1217 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1218 * @vsi: the VSI to be searched
1219 * @macaddr: the MAC address
1220 * @vlan: the vlan
1221 * @is_vf: make sure it's a vf filter, else doesn't matter
1222 * @is_netdev: make sure it's a netdev filter, else doesn't matter
1223 **/
1224void i40e_del_filter(struct i40e_vsi *vsi,
1225 u8 *macaddr, s16 vlan,
1226 bool is_vf, bool is_netdev)
1227{
1228 struct i40e_mac_filter *f;
1229
1230 if (!vsi || !macaddr)
1231 return;
1232
1233 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1234 if (!f || f->counter == 0)
1235 return;
1236
1237 if (is_vf) {
1238 if (f->is_vf) {
1239 f->is_vf = false;
1240 f->counter--;
1241 }
1242 } else if (is_netdev) {
1243 if (f->is_netdev) {
1244 f->is_netdev = false;
1245 f->counter--;
1246 }
1247 } else {
1248 /* make sure we don't remove a filter in use by vf or netdev */
1249 int min_f = 0;
1250 min_f += (f->is_vf ? 1 : 0);
1251 min_f += (f->is_netdev ? 1 : 0);
1252
1253 if (f->counter > min_f)
1254 f->counter--;
1255 }
1256
1257 /* counter == 0 tells sync_filters_subtask to
1258 * remove the filter from the firmware's list
1259 */
1260 if (f->counter == 0) {
1261 f->changed = true;
1262 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1263 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1264 }
1265}
1266
1267/**
1268 * i40e_set_mac - NDO callback to set mac address
1269 * @netdev: network interface device structure
1270 * @p: pointer to an address structure
1271 *
1272 * Returns 0 on success, negative on failure
1273 **/
1274static int i40e_set_mac(struct net_device *netdev, void *p)
1275{
1276 struct i40e_netdev_priv *np = netdev_priv(netdev);
1277 struct i40e_vsi *vsi = np->vsi;
1278 struct sockaddr *addr = p;
1279 struct i40e_mac_filter *f;
1280
1281 if (!is_valid_ether_addr(addr->sa_data))
1282 return -EADDRNOTAVAIL;
1283
1284 netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
1285
1286 if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
1287 return 0;
1288
80f6428f
ASJ		 1289 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1290 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1291 return -EADDRNOTAVAIL;
1292
41c445ff
JB		 1293 if (vsi->type == I40E_VSI_MAIN) {
1294 i40e_status ret;
1295 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1296 I40E_AQC_WRITE_TYPE_LAA_ONLY,
1297 addr->sa_data, NULL);
1298 if (ret) {
1299 netdev_info(netdev,
1300 "Addr change for Main VSI failed: %d\n",
1301 ret);
1302 return -EADDRNOTAVAIL;
1303 }
1304
1305 memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
1306 }
1307
1308 /* In order to be sure to not drop any packets, add the new address
1309 * then delete the old one.
1310 */
1311 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
1312 if (!f)
1313 return -ENOMEM;
1314
1315 i40e_sync_vsi_filters(vsi);
1316 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
1317 i40e_sync_vsi_filters(vsi);
1318
1319 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1320
1321 return 0;
1322}
1323
1324/**
1325 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1326 * @vsi: the VSI being setup
1327 * @ctxt: VSI context structure
1328 * @enabled_tc: Enabled TCs bitmap
1329 * @is_add: True if called before Add VSI
1330 *
1331 * Setup VSI queue mapping for enabled traffic classes.
1332 **/
1333static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1334 struct i40e_vsi_context *ctxt,
1335 u8 enabled_tc,
1336 bool is_add)
1337{
1338 struct i40e_pf *pf = vsi->back;
1339 u16 sections = 0;
1340 u8 netdev_tc = 0;
1341 u16 numtc = 0;
1342 u16 qcount;
1343 u8 offset;
1344 u16 qmap;
1345 int i;
4e3b35b0 1346 u16 num_tc_qps = 0;
41c445ff
JB		 1347
1348 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1349 offset = 0;
1350
1351 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1352 /* Find numtc from enabled TC bitmap */
1353 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1354 if (enabled_tc & (1 << i)) /* TC is enabled */
1355 numtc++;
1356 }
1357 if (!numtc) {
1358 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1359 numtc = 1;
1360 }
1361 } else {
1362 /* At least TC0 is enabled in case of non-DCB case */
1363 numtc = 1;
1364 }
1365
1366 vsi->tc_config.numtc = numtc;
1367 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0
NP		 1368 /* Number of queues per enabled TC */
1369 num_tc_qps = rounddown_pow_of_two(vsi->alloc_queue_pairs/numtc);
1370 num_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);
41c445ff
JB		 1371
1372 /* Setup queue offset/count for all TCs for given VSI */
1373 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1374 /* See if the given TC is enabled for the given VSI */
1375 if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
1376 int pow, num_qps;
1377
41c445ff
JB		 1378 switch (vsi->type) {
1379 case I40E_VSI_MAIN:
4e3b35b0 1380 qcount = min_t(int, pf->rss_size, num_tc_qps);
41c445ff
JB		 1381 break;
1382 case I40E_VSI_FDIR:
1383 case I40E_VSI_SRIOV:
1384 case I40E_VSI_VMDQ2:
1385 default:
4e3b35b0 1386 qcount = num_tc_qps;
41c445ff
JB		 1387 WARN_ON(i != 0);
1388 break;
1389 }
4e3b35b0
NP		 1390 vsi->tc_config.tc_info[i].qoffset = offset;
1391 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff
JB		 1392
1393 /* find the power-of-2 of the number of queue pairs */
4e3b35b0 1394 num_qps = qcount;
41c445ff 1395 pow = 0;
4e3b35b0 1396 while (num_qps && ((1 << pow) < qcount)) {
41c445ff
JB		 1397 pow++;
1398 num_qps >>= 1;
1399 }
1400
1401 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1402 qmap =
1403 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1404 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1405
4e3b35b0 1406 offset += qcount;
41c445ff
JB		 1407 } else {
1408 /* TC is not enabled so set the offset to
1409 * default queue and allocate one queue
1410 * for the given TC.
1411 */
1412 vsi->tc_config.tc_info[i].qoffset = 0;
1413 vsi->tc_config.tc_info[i].qcount = 1;
1414 vsi->tc_config.tc_info[i].netdev_tc = 0;
1415
1416 qmap = 0;
1417 }
1418 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1419 }
1420
1421 /* Set actual Tx/Rx queue pairs */
1422 vsi->num_queue_pairs = offset;
1423
1424 /* Scheduler section valid can only be set for ADD VSI */
1425 if (is_add) {
1426 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1427
1428 ctxt->info.up_enable_bits = enabled_tc;
1429 }
1430 if (vsi->type == I40E_VSI_SRIOV) {
1431 ctxt->info.mapping_flags |=
1432 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1433 for (i = 0; i < vsi->num_queue_pairs; i++)
1434 ctxt->info.queue_mapping[i] =
1435 cpu_to_le16(vsi->base_queue + i);
1436 } else {
1437 ctxt->info.mapping_flags |=
1438 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1439 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1440 }
1441 ctxt->info.valid_sections |= cpu_to_le16(sections);
1442}
1443
1444/**
1445 * i40e_set_rx_mode - NDO callback to set the netdev filters
1446 * @netdev: network interface device structure
1447 **/
1448static void i40e_set_rx_mode(struct net_device *netdev)
1449{
1450 struct i40e_netdev_priv *np = netdev_priv(netdev);
1451 struct i40e_mac_filter *f, *ftmp;
1452 struct i40e_vsi *vsi = np->vsi;
1453 struct netdev_hw_addr *uca;
1454 struct netdev_hw_addr *mca;
1455 struct netdev_hw_addr *ha;
1456
1457 /* add addr if not already in the filter list */
1458 netdev_for_each_uc_addr(uca, netdev) {
1459 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1460 if (i40e_is_vsi_in_vlan(vsi))
1461 i40e_put_mac_in_vlan(vsi, uca->addr,
1462 false, true);
1463 else
1464 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1465 false, true);
1466 }
1467 }
1468
1469 netdev_for_each_mc_addr(mca, netdev) {
1470 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1471 if (i40e_is_vsi_in_vlan(vsi))
1472 i40e_put_mac_in_vlan(vsi, mca->addr,
1473 false, true);
1474 else
1475 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1476 false, true);
1477 }
1478 }
1479
1480 /* remove filter if not in netdev list */
1481 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1482 bool found = false;
1483
1484 if (!f->is_netdev)
1485 continue;
1486
1487 if (is_multicast_ether_addr(f->macaddr)) {
1488 netdev_for_each_mc_addr(mca, netdev) {
1489 if (ether_addr_equal(mca->addr, f->macaddr)) {
1490 found = true;
1491 break;
1492 }
1493 }
1494 } else {
1495 netdev_for_each_uc_addr(uca, netdev) {
1496 if (ether_addr_equal(uca->addr, f->macaddr)) {
1497 found = true;
1498 break;
1499 }
1500 }
1501
1502 for_each_dev_addr(netdev, ha) {
1503 if (ether_addr_equal(ha->addr, f->macaddr)) {
1504 found = true;
1505 break;
1506 }
1507 }
1508 }
1509 if (!found)
1510 i40e_del_filter(
1511 vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1512 }
1513
1514 /* check for other flag changes */
1515 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1516 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1517 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1518 }
1519}
1520
1521/**
1522 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1523 * @vsi: ptr to the VSI
1524 *
1525 * Push any outstanding VSI filter changes through the AdminQ.
1526 *
1527 * Returns 0 or error value
1528 **/
1529int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
1530{
1531 struct i40e_mac_filter *f, *ftmp;
1532 bool promisc_forced_on = false;
1533 bool add_happened = false;
1534 int filter_list_len = 0;
1535 u32 changed_flags = 0;
dcae29be 1536 i40e_status aq_ret = 0;
41c445ff
JB		 1537 struct i40e_pf *pf;
1538 int num_add = 0;
1539 int num_del = 0;
1540 u16 cmd_flags;
1541
1542 /* empty array typed pointers, kcalloc later */
1543 struct i40e_aqc_add_macvlan_element_data *add_list;
1544 struct i40e_aqc_remove_macvlan_element_data *del_list;
1545
1546 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1547 usleep_range(1000, 2000);
1548 pf = vsi->back;
1549
1550 if (vsi->netdev) {
1551 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1552 vsi->current_netdev_flags = vsi->netdev->flags;
1553 }
1554
1555 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1556 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1557
1558 filter_list_len = pf->hw.aq.asq_buf_size /
1559 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1560 del_list = kcalloc(filter_list_len,
1561 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1562 GFP_KERNEL);
1563 if (!del_list)
1564 return -ENOMEM;
1565
1566 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1567 if (!f->changed)
1568 continue;
1569
1570 if (f->counter != 0)
1571 continue;
1572 f->changed = false;
1573 cmd_flags = 0;
1574
1575 /* add to delete list */
1576 memcpy(del_list[num_del].mac_addr,
1577 f->macaddr, ETH_ALEN);
1578 del_list[num_del].vlan_tag =
1579 cpu_to_le16((u16)(f->vlan ==
1580 I40E_VLAN_ANY ? 0 : f->vlan));
1581
41c445ff
JB		 1582 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1583 del_list[num_del].flags = cmd_flags;
1584 num_del++;
1585
1586 /* unlink from filter list */
1587 list_del(&f->list);
1588 kfree(f);
1589
1590 /* flush a full buffer */
1591 if (num_del == filter_list_len) {
dcae29be 1592 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
41c445ff
JB		 1593 vsi->seid, del_list, num_del,
1594 NULL);
1595 num_del = 0;
1596 memset(del_list, 0, sizeof(*del_list));
1597
fdfe9cbe
SN		 1598 if (aq_ret &&
1599 pf->hw.aq.asq_last_status !=
1600 I40E_AQ_RC_ENOENT)
41c445ff
JB		 1601 dev_info(&pf->pdev->dev,
1602 "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
dcae29be 1603 aq_ret,
41c445ff
JB		 1604 pf->hw.aq.asq_last_status);
1605 }
1606 }
1607 if (num_del) {
dcae29be 1608 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
41c445ff
JB		 1609 del_list, num_del, NULL);
1610 num_del = 0;
1611
fdfe9cbe
SN		 1612 if (aq_ret &&
1613 pf->hw.aq.asq_last_status != I40E_AQ_RC_ENOENT)
41c445ff
JB		 1614 dev_info(&pf->pdev->dev,
1615 "ignoring delete macvlan error, err %d, aq_err %d\n",
dcae29be 1616 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1617 }
1618
1619 kfree(del_list);
1620 del_list = NULL;
1621
1622 /* do all the adds now */
1623 filter_list_len = pf->hw.aq.asq_buf_size /
1624 sizeof(struct i40e_aqc_add_macvlan_element_data),
1625 add_list = kcalloc(filter_list_len,
1626 sizeof(struct i40e_aqc_add_macvlan_element_data),
1627 GFP_KERNEL);
1628 if (!add_list)
1629 return -ENOMEM;
1630
1631 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1632 if (!f->changed)
1633 continue;
1634
1635 if (f->counter == 0)
1636 continue;
1637 f->changed = false;
1638 add_happened = true;
1639 cmd_flags = 0;
1640
1641 /* add to add array */
1642 memcpy(add_list[num_add].mac_addr,
1643 f->macaddr, ETH_ALEN);
1644 add_list[num_add].vlan_tag =
1645 cpu_to_le16(
1646 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1647 add_list[num_add].queue_number = 0;
1648
1649 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1650 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1651 num_add++;
1652
1653 /* flush a full buffer */
1654 if (num_add == filter_list_len) {
dcae29be
JB		 1655 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1656 add_list, num_add,
1657 NULL);
41c445ff
JB		 1658 num_add = 0;
1659
dcae29be 1660 if (aq_ret)
41c445ff
JB		 1661 break;
1662 memset(add_list, 0, sizeof(*add_list));
1663 }
1664 }
1665 if (num_add) {
dcae29be
JB		 1666 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1667 add_list, num_add, NULL);
41c445ff
JB		 1668 num_add = 0;
1669 }
1670 kfree(add_list);
1671 add_list = NULL;
1672
dcae29be 1673 if (add_happened && (!aq_ret)) {
41c445ff 1674 /* do nothing */;
dcae29be 1675 } else if (add_happened && (aq_ret)) {
41c445ff
JB		 1676 dev_info(&pf->pdev->dev,
1677 "add filter failed, err %d, aq_err %d\n",
dcae29be 1678 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1679 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
1680 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1681 &vsi->state)) {
1682 promisc_forced_on = true;
1683 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1684 &vsi->state);
1685 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
1686 }
1687 }
1688 }
1689
1690 /* check for changes in promiscuous modes */
1691 if (changed_flags & IFF_ALLMULTI) {
1692 bool cur_multipromisc;
1693 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
dcae29be
JB		 1694 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
1695 vsi->seid,
1696 cur_multipromisc,
1697 NULL);
1698 if (aq_ret)
41c445ff
JB		 1699 dev_info(&pf->pdev->dev,
1700 "set multi promisc failed, err %d, aq_err %d\n",
dcae29be 1701 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1702 }
1703 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
1704 bool cur_promisc;
1705 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
1706 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
1707 &vsi->state));
dcae29be
JB		 1708 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
1709 vsi->seid,
1710 cur_promisc, NULL);
1711 if (aq_ret)
41c445ff
JB		 1712 dev_info(&pf->pdev->dev,
1713 "set uni promisc failed, err %d, aq_err %d\n",
dcae29be 1714 aq_ret, pf->hw.aq.asq_last_status);
1a10370a
GR		 1715 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
1716 vsi->seid,
1717 cur_promisc, NULL);
1718 if (aq_ret)
1719 dev_info(&pf->pdev->dev,
1720 "set brdcast promisc failed, err %d, aq_err %d\n",
1721 aq_ret, pf->hw.aq.asq_last_status);
41c445ff
JB		 1722 }
1723
1724 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
1725 return 0;
1726}
1727
1728/**
1729 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
1730 * @pf: board private structure
1731 **/
1732static void i40e_sync_filters_subtask(struct i40e_pf *pf)
1733{
1734 int v;
1735
1736 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
1737 return;
1738 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
1739
505682cd 1740 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 1741 if (pf->vsi[v] &&
1742 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
1743 i40e_sync_vsi_filters(pf->vsi[v]);
1744 }
1745}
1746
1747/**
1748 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
1749 * @netdev: network interface device structure
1750 * @new_mtu: new value for maximum frame size
1751 *
1752 * Returns 0 on success, negative on failure
1753 **/
1754static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
1755{
1756 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 1757 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 1758 struct i40e_vsi *vsi = np->vsi;
1759
1760 /* MTU < 68 is an error and causes problems on some kernels */
1761 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
1762 return -EINVAL;
1763
1764 netdev_info(netdev, "changing MTU from %d to %d\n",
1765 netdev->mtu, new_mtu);
1766 netdev->mtu = new_mtu;
1767 if (netif_running(netdev))
1768 i40e_vsi_reinit_locked(vsi);
1769
1770 return 0;
1771}
1772
beb0dff1
JK		 1773/**
1774 * i40e_ioctl - Access the hwtstamp interface
1775 * @netdev: network interface device structure
1776 * @ifr: interface request data
1777 * @cmd: ioctl command
1778 **/
1779int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1780{
1781 struct i40e_netdev_priv *np = netdev_priv(netdev);
1782 struct i40e_pf *pf = np->vsi->back;
1783
1784 switch (cmd) {
1785 case SIOCGHWTSTAMP:
1786 return i40e_ptp_get_ts_config(pf, ifr);
1787 case SIOCSHWTSTAMP:
1788 return i40e_ptp_set_ts_config(pf, ifr);
1789 default:
1790 return -EOPNOTSUPP;
1791 }
1792}
1793
41c445ff
JB		 1794/**
1795 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
1796 * @vsi: the vsi being adjusted
1797 **/
1798void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
1799{
1800 struct i40e_vsi_context ctxt;
1801 i40e_status ret;
1802
1803 if ((vsi->info.valid_sections &
1804 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1805 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
1806 return; /* already enabled */
1807
1808 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1809 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1810 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
1811
1812 ctxt.seid = vsi->seid;
1813 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1814 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1815 if (ret) {
1816 dev_info(&vsi->back->pdev->dev,
1817 "%s: update vsi failed, aq_err=%d\n",
1818 __func__, vsi->back->hw.aq.asq_last_status);
1819 }
1820}
1821
1822/**
1823 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
1824 * @vsi: the vsi being adjusted
1825 **/
1826void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
1827{
1828 struct i40e_vsi_context ctxt;
1829 i40e_status ret;
1830
1831 if ((vsi->info.valid_sections &
1832 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
1833 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
1834 I40E_AQ_VSI_PVLAN_EMOD_MASK))
1835 return; /* already disabled */
1836
1837 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
1838 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
1839 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
1840
1841 ctxt.seid = vsi->seid;
1842 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1843 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
1844 if (ret) {
1845 dev_info(&vsi->back->pdev->dev,
1846 "%s: update vsi failed, aq_err=%d\n",
1847 __func__, vsi->back->hw.aq.asq_last_status);
1848 }
1849}
1850
1851/**
1852 * i40e_vlan_rx_register - Setup or shutdown vlan offload
1853 * @netdev: network interface to be adjusted
1854 * @features: netdev features to test if VLAN offload is enabled or not
1855 **/
1856static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
1857{
1858 struct i40e_netdev_priv *np = netdev_priv(netdev);
1859 struct i40e_vsi *vsi = np->vsi;
1860
1861 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1862 i40e_vlan_stripping_enable(vsi);
1863 else
1864 i40e_vlan_stripping_disable(vsi);
1865}
1866
1867/**
1868 * i40e_vsi_add_vlan - Add vsi membership for given vlan
1869 * @vsi: the vsi being configured
1870 * @vid: vlan id to be added (0 = untagged only , -1 = any)
1871 **/
1872int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
1873{
1874 struct i40e_mac_filter *f, *add_f;
1875 bool is_netdev, is_vf;
41c445ff
JB		 1876
1877 is_vf = (vsi->type == I40E_VSI_SRIOV);
1878 is_netdev = !!(vsi->netdev);
1879
1880 if (is_netdev) {
1881 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
1882 is_vf, is_netdev);
1883 if (!add_f) {
1884 dev_info(&vsi->back->pdev->dev,
1885 "Could not add vlan filter %d for %pM\n",
1886 vid, vsi->netdev->dev_addr);
1887 return -ENOMEM;
1888 }
1889 }
1890
1891 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1892 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1893 if (!add_f) {
1894 dev_info(&vsi->back->pdev->dev,
1895 "Could not add vlan filter %d for %pM\n",
1896 vid, f->macaddr);
1897 return -ENOMEM;
1898 }
1899 }
1900
41c445ff
JB		 1901 /* Now if we add a vlan tag, make sure to check if it is the first
1902 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
1903 * with 0, so we now accept untagged and specified tagged traffic
1904 * (and not any taged and untagged)
1905 */
1906 if (vid > 0) {
1907 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
1908 I40E_VLAN_ANY,
1909 is_vf, is_netdev)) {
1910 i40e_del_filter(vsi, vsi->netdev->dev_addr,
1911 I40E_VLAN_ANY, is_vf, is_netdev);
1912 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
1913 is_vf, is_netdev);
1914 if (!add_f) {
1915 dev_info(&vsi->back->pdev->dev,
1916 "Could not add filter 0 for %pM\n",
1917 vsi->netdev->dev_addr);
1918 return -ENOMEM;
1919 }
1920 }
8d82a7c5 1921 }
41c445ff 1922
8d82a7c5
GR		 1923 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
1924 if (vid > 0 && !vsi->info.pvid) {
41c445ff
JB		 1925 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1926 if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1927 is_vf, is_netdev)) {
1928 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
1929 is_vf, is_netdev);
1930 add_f = i40e_add_filter(vsi, f->macaddr,
1931 0, is_vf, is_netdev);
1932 if (!add_f) {
1933 dev_info(&vsi->back->pdev->dev,
1934 "Could not add filter 0 for %pM\n",
1935 f->macaddr);
1936 return -ENOMEM;
1937 }
1938 }
1939 }
41c445ff
JB		 1940 }
1941
80f6428f
ASJ		 1942 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1943 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1944 return 0;
1945
1946 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1947}
1948
1949/**
1950 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
1951 * @vsi: the vsi being configured
1952 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 1953 *
1954 * Return: 0 on success or negative otherwise
41c445ff
JB		 1955 **/
1956int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
1957{
1958 struct net_device *netdev = vsi->netdev;
1959 struct i40e_mac_filter *f, *add_f;
1960 bool is_vf, is_netdev;
1961 int filter_count = 0;
41c445ff
JB		 1962
1963 is_vf = (vsi->type == I40E_VSI_SRIOV);
1964 is_netdev = !!(netdev);
1965
1966 if (is_netdev)
1967 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
1968
1969 list_for_each_entry(f, &vsi->mac_filter_list, list)
1970 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
1971
41c445ff
JB		 1972 /* go through all the filters for this VSI and if there is only
1973 * vid == 0 it means there are no other filters, so vid 0 must
1974 * be replaced with -1. This signifies that we should from now
1975 * on accept any traffic (with any tag present, or untagged)
1976 */
1977 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1978 if (is_netdev) {
1979 if (f->vlan &&
1980 ether_addr_equal(netdev->dev_addr, f->macaddr))
1981 filter_count++;
1982 }
1983
1984 if (f->vlan)
1985 filter_count++;
1986 }
1987
1988 if (!filter_count && is_netdev) {
1989 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
1990 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1991 is_vf, is_netdev);
1992 if (!f) {
1993 dev_info(&vsi->back->pdev->dev,
1994 "Could not add filter %d for %pM\n",
1995 I40E_VLAN_ANY, netdev->dev_addr);
1996 return -ENOMEM;
1997 }
1998 }
1999
2000 if (!filter_count) {
2001 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2002 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2003 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2004 is_vf, is_netdev);
2005 if (!add_f) {
2006 dev_info(&vsi->back->pdev->dev,
2007 "Could not add filter %d for %pM\n",
2008 I40E_VLAN_ANY, f->macaddr);
2009 return -ENOMEM;
2010 }
2011 }
2012 }
2013
80f6428f
ASJ		 2014 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
2015 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
2016 return 0;
2017
41c445ff
JB		 2018 return i40e_sync_vsi_filters(vsi);
2019}
2020
2021/**
2022 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2023 * @netdev: network interface to be adjusted
2024 * @vid: vlan id to be added
078b5876
JB		 2025 *
2026 * net_device_ops implementation for adding vlan ids
41c445ff
JB		 2027 **/
2028static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2029 __always_unused __be16 proto, u16 vid)
2030{
2031 struct i40e_netdev_priv *np = netdev_priv(netdev);
2032 struct i40e_vsi *vsi = np->vsi;
078b5876 2033 int ret = 0;
41c445ff
JB		 2034
2035 if (vid > 4095)
078b5876
JB		 2036 return -EINVAL;
2037
2038 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2039
6982d429
ASJ		 2040 /* If the network stack called us with vid = 0 then
2041 * it is asking to receive priority tagged packets with
2042 * vlan id 0. Our HW receives them by default when configured
2043 * to receive untagged packets so there is no need to add an
2044 * extra filter for vlan 0 tagged packets.
41c445ff 2045 */
6982d429
ASJ		 2046 if (vid)
2047 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2048
078b5876
JB		 2049 if (!ret && (vid < VLAN_N_VID))
2050 set_bit(vid, vsi->active_vlans);
41c445ff 2051
078b5876 2052 return ret;
41c445ff
JB		 2053}
2054
2055/**
2056 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2057 * @netdev: network interface to be adjusted
2058 * @vid: vlan id to be removed
078b5876 2059 *
fdfd943e 2060 * net_device_ops implementation for removing vlan ids
41c445ff
JB		 2061 **/
2062static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2063 __always_unused __be16 proto, u16 vid)
2064{
2065 struct i40e_netdev_priv *np = netdev_priv(netdev);
2066 struct i40e_vsi *vsi = np->vsi;
2067
078b5876
JB		 2068 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2069
41c445ff
JB		 2070 /* return code is ignored as there is nothing a user
2071 * can do about failure to remove and a log message was
078b5876 2072 * already printed from the other function
41c445ff
JB		 2073 */
2074 i40e_vsi_kill_vlan(vsi, vid);
2075
2076 clear_bit(vid, vsi->active_vlans);
078b5876 2077
41c445ff
JB		 2078 return 0;
2079}
2080
2081/**
2082 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2083 * @vsi: the vsi being brought back up
2084 **/
2085static void i40e_restore_vlan(struct i40e_vsi *vsi)
2086{
2087 u16 vid;
2088
2089 if (!vsi->netdev)
2090 return;
2091
2092 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2093
2094 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2095 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2096 vid);
2097}
2098
2099/**
2100 * i40e_vsi_add_pvid - Add pvid for the VSI
2101 * @vsi: the vsi being adjusted
2102 * @vid: the vlan id to set as a PVID
2103 **/
dcae29be 2104int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2105{
2106 struct i40e_vsi_context ctxt;
dcae29be 2107 i40e_status aq_ret;
41c445ff
JB		 2108
2109 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2110 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2111 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2112 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2113 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2114
2115 ctxt.seid = vsi->seid;
2116 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
dcae29be
JB		 2117 aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2118 if (aq_ret) {
41c445ff
JB		 2119 dev_info(&vsi->back->pdev->dev,
2120 "%s: update vsi failed, aq_err=%d\n",
2121 __func__, vsi->back->hw.aq.asq_last_status);
dcae29be 2122 return -ENOENT;
41c445ff
JB		 2123 }
2124
dcae29be 2125 return 0;
41c445ff
JB		 2126}
2127
2128/**
2129 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2130 * @vsi: the vsi being adjusted
2131 *
2132 * Just use the vlan_rx_register() service to put it back to normal
2133 **/
2134void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2135{
6c12fcbf
GR		 2136 i40e_vlan_stripping_disable(vsi);
2137
41c445ff 2138 vsi->info.pvid = 0;
41c445ff
JB		 2139}
2140
2141/**
2142 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2143 * @vsi: ptr to the VSI
2144 *
2145 * If this function returns with an error, then it's possible one or
2146 * more of the rings is populated (while the rest are not). It is the
2147 * callers duty to clean those orphaned rings.
2148 *
2149 * Return 0 on success, negative on failure
2150 **/
2151static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2152{
2153 int i, err = 0;
2154
2155 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2156 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2157
2158 return err;
2159}
2160
2161/**
2162 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2163 * @vsi: ptr to the VSI
2164 *
2165 * Free VSI's transmit software resources
2166 **/
2167static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2168{
2169 int i;
2170
8e9dca53
GR		 2171 if (!vsi->tx_rings)
2172 return;
2173
41c445ff 2174 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2175 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2176 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2177}
2178
2179/**
2180 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2181 * @vsi: ptr to the VSI
2182 *
2183 * If this function returns with an error, then it's possible one or
2184 * more of the rings is populated (while the rest are not). It is the
2185 * callers duty to clean those orphaned rings.
2186 *
2187 * Return 0 on success, negative on failure
2188 **/
2189static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2190{
2191 int i, err = 0;
2192
2193 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2194 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
41c445ff
JB		 2195 return err;
2196}
2197
2198/**
2199 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2200 * @vsi: ptr to the VSI
2201 *
2202 * Free all receive software resources
2203 **/
2204static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2205{
2206 int i;
2207
8e9dca53
GR		 2208 if (!vsi->rx_rings)
2209 return;
2210
41c445ff 2211 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2212 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2213 i40e_free_rx_resources(vsi->rx_rings[i]);
41c445ff
JB		 2214}
2215
2216/**
2217 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2218 * @ring: The Tx ring to configure
2219 *
2220 * Configure the Tx descriptor ring in the HMC context.
2221 **/
2222static int i40e_configure_tx_ring(struct i40e_ring *ring)
2223{
2224 struct i40e_vsi *vsi = ring->vsi;
2225 u16 pf_q = vsi->base_queue + ring->queue_index;
2226 struct i40e_hw *hw = &vsi->back->hw;
2227 struct i40e_hmc_obj_txq tx_ctx;
2228 i40e_status err = 0;
2229 u32 qtx_ctl = 0;
2230
2231 /* some ATR related tx ring init */
60ea5f83 2232 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2233 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2234 ring->atr_count = 0;
2235 } else {
2236 ring->atr_sample_rate = 0;
2237 }
2238
2239 /* initialize XPS */
2240 if (ring->q_vector && ring->netdev &&
4e3b35b0 2241 vsi->tc_config.numtc <= 1 &&
41c445ff
JB		 2242 !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
2243 netif_set_xps_queue(ring->netdev,
2244 &ring->q_vector->affinity_mask,
2245 ring->queue_index);
2246
2247 /* clear the context structure first */
2248 memset(&tx_ctx, 0, sizeof(tx_ctx));
2249
2250 tx_ctx.new_context = 1;
2251 tx_ctx.base = (ring->dma / 128);
2252 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2253 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2254 I40E_FLAG_FD_ATR_ENABLED));
beb0dff1 2255 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2256 /* FDIR VSI tx ring can still use RS bit and writebacks */
2257 if (vsi->type != I40E_VSI_FDIR)
2258 tx_ctx.head_wb_ena = 1;
2259 tx_ctx.head_wb_addr = ring->dma +
2260 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2261
2262 /* As part of VSI creation/update, FW allocates certain
2263 * Tx arbitration queue sets for each TC enabled for
2264 * the VSI. The FW returns the handles to these queue
2265 * sets as part of the response buffer to Add VSI,
2266 * Update VSI, etc. AQ commands. It is expected that
2267 * these queue set handles be associated with the Tx
2268 * queues by the driver as part of the TX queue context
2269 * initialization. This has to be done regardless of
2270 * DCB as by default everything is mapped to TC0.
2271 */
2272 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2273 tx_ctx.rdylist_act = 0;
2274
2275 /* clear the context in the HMC */
2276 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2277 if (err) {
2278 dev_info(&vsi->back->pdev->dev,
2279 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2280 ring->queue_index, pf_q, err);
2281 return -ENOMEM;
2282 }
2283
2284 /* set the context in the HMC */
2285 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2286 if (err) {
2287 dev_info(&vsi->back->pdev->dev,
2288 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2289 ring->queue_index, pf_q, err);
2290 return -ENOMEM;
2291 }
2292
2293 /* Now associate this queue with this PCI function */
9d8bf547
SN		 2294 if (vsi->type == I40E_VSI_VMDQ2)
2295 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
2296 else
2297 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
13fd9774
SN		 2298 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2299 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2300 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2301 i40e_flush(hw);
2302
2303 clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
2304
2305 /* cache tail off for easier writes later */
2306 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2307
2308 return 0;
2309}
2310
2311/**
2312 * i40e_configure_rx_ring - Configure a receive ring context
2313 * @ring: The Rx ring to configure
2314 *
2315 * Configure the Rx descriptor ring in the HMC context.
2316 **/
2317static int i40e_configure_rx_ring(struct i40e_ring *ring)
2318{
2319 struct i40e_vsi *vsi = ring->vsi;
2320 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2321 u16 pf_q = vsi->base_queue + ring->queue_index;
2322 struct i40e_hw *hw = &vsi->back->hw;
2323 struct i40e_hmc_obj_rxq rx_ctx;
2324 i40e_status err = 0;
2325
2326 ring->state = 0;
2327
2328 /* clear the context structure first */
2329 memset(&rx_ctx, 0, sizeof(rx_ctx));
2330
2331 ring->rx_buf_len = vsi->rx_buf_len;
2332 ring->rx_hdr_len = vsi->rx_hdr_len;
2333
2334 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2335 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2336
2337 rx_ctx.base = (ring->dma / 128);
2338 rx_ctx.qlen = ring->count;
2339
2340 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2341 set_ring_16byte_desc_enabled(ring);
2342 rx_ctx.dsize = 0;
2343 } else {
2344 rx_ctx.dsize = 1;
2345 }
2346
2347 rx_ctx.dtype = vsi->dtype;
2348 if (vsi->dtype) {
2349 set_ring_ps_enabled(ring);
2350 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2351 I40E_RX_SPLIT_IP |
2352 I40E_RX_SPLIT_TCP_UDP |
2353 I40E_RX_SPLIT_SCTP;
2354 } else {
2355 rx_ctx.hsplit_0 = 0;
2356 }
2357
2358 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2359 (chain_len * ring->rx_buf_len));
2360 rx_ctx.tphrdesc_ena = 1;
2361 rx_ctx.tphwdesc_ena = 1;
2362 rx_ctx.tphdata_ena = 1;
2363 rx_ctx.tphhead_ena = 1;
7134f9ce
JB		 2364 if (hw->revision_id == 0)
2365 rx_ctx.lrxqthresh = 0;
2366 else
2367 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2368 rx_ctx.crcstrip = 1;
2369 rx_ctx.l2tsel = 1;
2370 rx_ctx.showiv = 1;
acb3676b
CS		 2371 /* set the prefena field to 1 because the manual says to */
2372 rx_ctx.prefena = 1;
41c445ff
JB		 2373
2374 /* clear the context in the HMC */
2375 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2376 if (err) {
2377 dev_info(&vsi->back->pdev->dev,
2378 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2379 ring->queue_index, pf_q, err);
2380 return -ENOMEM;
2381 }
2382
2383 /* set the context in the HMC */
2384 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2385 if (err) {
2386 dev_info(&vsi->back->pdev->dev,
2387 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2388 ring->queue_index, pf_q, err);
2389 return -ENOMEM;
2390 }
2391
2392 /* cache tail for quicker writes, and clear the reg before use */
2393 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2394 writel(0, ring->tail);
2395
2396 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
2397
2398 return 0;
2399}
2400
2401/**
2402 * i40e_vsi_configure_tx - Configure the VSI for Tx
2403 * @vsi: VSI structure describing this set of rings and resources
2404 *
2405 * Configure the Tx VSI for operation.
2406 **/
2407static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2408{
2409 int err = 0;
2410 u16 i;
2411
9f65e15b
AD		 2412 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2413 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2414
2415 return err;
2416}
2417
2418/**
2419 * i40e_vsi_configure_rx - Configure the VSI for Rx
2420 * @vsi: the VSI being configured
2421 *
2422 * Configure the Rx VSI for operation.
2423 **/
2424static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2425{
2426 int err = 0;
2427 u16 i;
2428
2429 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2430 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2431 + ETH_FCS_LEN + VLAN_HLEN;
2432 else
2433 vsi->max_frame = I40E_RXBUFFER_2048;
2434
2435 /* figure out correct receive buffer length */
2436 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2437 I40E_FLAG_RX_PS_ENABLED)) {
2438 case I40E_FLAG_RX_1BUF_ENABLED:
2439 vsi->rx_hdr_len = 0;
2440 vsi->rx_buf_len = vsi->max_frame;
2441 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2442 break;
2443 case I40E_FLAG_RX_PS_ENABLED:
2444 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2445 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2446 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2447 break;
2448 default:
2449 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2450 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2451 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2452 break;
2453 }
2454
2455 /* round up for the chip's needs */
2456 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
2457 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2458 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
2459 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2460
2461 /* set up individual rings */
2462 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2463 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2464
2465 return err;
2466}
2467
2468/**
2469 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2470 * @vsi: ptr to the VSI
2471 **/
2472static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2473{
e7046ee1 2474 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2475 u16 qoffset, qcount;
2476 int i, n;
2477
2478 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2479 return;
2480
2481 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
2482 if (!(vsi->tc_config.enabled_tc & (1 << n)))
2483 continue;
2484
2485 qoffset = vsi->tc_config.tc_info[n].qoffset;
2486 qcount = vsi->tc_config.tc_info[n].qcount;
2487 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2488 rx_ring = vsi->rx_rings[i];
2489 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2490 rx_ring->dcb_tc = n;
2491 tx_ring->dcb_tc = n;
2492 }
2493 }
2494}
2495
2496/**
2497 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2498 * @vsi: ptr to the VSI
2499 **/
2500static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2501{
2502 if (vsi->netdev)
2503 i40e_set_rx_mode(vsi->netdev);
2504}
2505
17a73f6b
JG		 2506/**
2507 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2508 * @vsi: Pointer to the targeted VSI
2509 *
2510 * This function replays the hlist on the hw where all the SB Flow Director
2511 * filters were saved.
2512 **/
2513static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
2514{
2515 struct i40e_fdir_filter *filter;
2516 struct i40e_pf *pf = vsi->back;
2517 struct hlist_node *node;
2518
55a5e60b
ASJ		 2519 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
2520 return;
2521
17a73f6b
JG		 2522 hlist_for_each_entry_safe(filter, node,
2523 &pf->fdir_filter_list, fdir_node) {
2524 i40e_add_del_fdir(vsi, filter, true);
2525 }
2526}
2527
41c445ff
JB		 2528/**
2529 * i40e_vsi_configure - Set up the VSI for action
2530 * @vsi: the VSI being configured
2531 **/
2532static int i40e_vsi_configure(struct i40e_vsi *vsi)
2533{
2534 int err;
2535
2536 i40e_set_vsi_rx_mode(vsi);
2537 i40e_restore_vlan(vsi);
2538 i40e_vsi_config_dcb_rings(vsi);
2539 err = i40e_vsi_configure_tx(vsi);
2540 if (!err)
2541 err = i40e_vsi_configure_rx(vsi);
2542
2543 return err;
2544}
2545
2546/**
2547 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
2548 * @vsi: the VSI being configured
2549 **/
2550static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
2551{
2552 struct i40e_pf *pf = vsi->back;
2553 struct i40e_q_vector *q_vector;
2554 struct i40e_hw *hw = &pf->hw;
2555 u16 vector;
2556 int i, q;
2557 u32 val;
2558 u32 qp;
2559
2560 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
2561 * and PFINT_LNKLSTn registers, e.g.:
2562 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
2563 */
2564 qp = vsi->base_queue;
2565 vector = vsi->base_vector;
493fb300
AD		 2566 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
2567 q_vector = vsi->q_vectors[i];
41c445ff
JB		 2568 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2569 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2570 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
2571 q_vector->rx.itr);
2572 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2573 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2574 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
2575 q_vector->tx.itr);
2576
2577 /* Linked list for the queuepairs assigned to this vector */
2578 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
2579 for (q = 0; q < q_vector->num_ringpairs; q++) {
2580 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2581 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2582 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2583 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
2584 (I40E_QUEUE_TYPE_TX
2585 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2586
2587 wr32(hw, I40E_QINT_RQCTL(qp), val);
2588
2589 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2590 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2591 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2592 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
2593 (I40E_QUEUE_TYPE_RX
2594 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2595
2596 /* Terminate the linked list */
2597 if (q == (q_vector->num_ringpairs - 1))
2598 val |= (I40E_QUEUE_END_OF_LIST
2599 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2600
2601 wr32(hw, I40E_QINT_TQCTL(qp), val);
2602 qp++;
2603 }
2604 }
2605
2606 i40e_flush(hw);
2607}
2608
2609/**
2610 * i40e_enable_misc_int_causes - enable the non-queue interrupts
2611 * @hw: ptr to the hardware info
2612 **/
2613static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
2614{
2615 u32 val;
2616
2617 /* clear things first */
2618 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
2619 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
2620
2621 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
2622 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
2623 I40E_PFINT_ICR0_ENA_GRST_MASK |
2624 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
2625 I40E_PFINT_ICR0_ENA_GPIO_MASK |
beb0dff1 2626 I40E_PFINT_ICR0_ENA_TIMESYNC_MASK |
41c445ff
JB		 2627 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
2628 I40E_PFINT_ICR0_ENA_VFLR_MASK |
2629 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2630
2631 wr32(hw, I40E_PFINT_ICR0_ENA, val);
2632
2633 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 2634 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
2635 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 2636
2637 /* OTHER_ITR_IDX = 0 */
2638 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
2639}
2640
2641/**
2642 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
2643 * @vsi: the VSI being configured
2644 **/
2645static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
2646{
493fb300 2647 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 2648 struct i40e_pf *pf = vsi->back;
2649 struct i40e_hw *hw = &pf->hw;
2650 u32 val;
2651
2652 /* set the ITR configuration */
2653 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
2654 q_vector->rx.latency_range = I40E_LOW_LATENCY;
2655 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
2656 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
2657 q_vector->tx.latency_range = I40E_LOW_LATENCY;
2658 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
2659
2660 i40e_enable_misc_int_causes(hw);
2661
2662 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
2663 wr32(hw, I40E_PFINT_LNKLST0, 0);
2664
f29eaa3d 2665 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 2666 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2667 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2668 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2669
2670 wr32(hw, I40E_QINT_RQCTL(0), val);
2671
2672 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2673 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2674 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2675
2676 wr32(hw, I40E_QINT_TQCTL(0), val);
2677 i40e_flush(hw);
2678}
2679
2ef28cfb
MW		 2680/**
2681 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
2682 * @pf: board private structure
2683 **/
2684void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
2685{
2686 struct i40e_hw *hw = &pf->hw;
2687
2688 wr32(hw, I40E_PFINT_DYN_CTL0,
2689 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2690 i40e_flush(hw);
2691}
2692
41c445ff
JB		 2693/**
2694 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
2695 * @pf: board private structure
2696 **/
116a57d4 2697void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 2698{
2699 struct i40e_hw *hw = &pf->hw;
2700 u32 val;
2701
2702 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
2703 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2704 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
2705
2706 wr32(hw, I40E_PFINT_DYN_CTL0, val);
2707 i40e_flush(hw);
2708}
2709
2710/**
2711 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
2712 * @vsi: pointer to a vsi
2713 * @vector: enable a particular Hw Interrupt vector
2714 **/
2715void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
2716{
2717 struct i40e_pf *pf = vsi->back;
2718 struct i40e_hw *hw = &pf->hw;
2719 u32 val;
2720
2721 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2722 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2723 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
2724 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
1022cb6c 2725 /* skip the flush */
41c445ff
JB		 2726}
2727
2728/**
2729 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
2730 * @irq: interrupt number
2731 * @data: pointer to a q_vector
2732 **/
2733static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
2734{
2735 struct i40e_q_vector *q_vector = data;
2736
cd0b6fa6 2737 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 2738 return IRQ_HANDLED;
2739
2740 napi_schedule(&q_vector->napi);
2741
2742 return IRQ_HANDLED;
2743}
2744
41c445ff
JB		 2745/**
2746 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
2747 * @vsi: the VSI being configured
2748 * @basename: name for the vector
2749 *
2750 * Allocates MSI-X vectors and requests interrupts from the kernel.
2751 **/
2752static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
2753{
2754 int q_vectors = vsi->num_q_vectors;
2755 struct i40e_pf *pf = vsi->back;
2756 int base = vsi->base_vector;
2757 int rx_int_idx = 0;
2758 int tx_int_idx = 0;
2759 int vector, err;
2760
2761 for (vector = 0; vector < q_vectors; vector++) {
493fb300 2762 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 2763
cd0b6fa6 2764 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 2765 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2766 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2767 tx_int_idx++;
cd0b6fa6 2768 } else if (q_vector->rx.ring) {
41c445ff
JB		 2769 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2770 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 2771 } else if (q_vector->tx.ring) {
41c445ff
JB		 2772 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2773 "%s-%s-%d", basename, "tx", tx_int_idx++);
2774 } else {
2775 /* skip this unused q_vector */
2776 continue;
2777 }
2778 err = request_irq(pf->msix_entries[base + vector].vector,
2779 vsi->irq_handler,
2780 0,
2781 q_vector->name,
2782 q_vector);
2783 if (err) {
2784 dev_info(&pf->pdev->dev,
2785 "%s: request_irq failed, error: %d\n",
2786 __func__, err);
2787 goto free_queue_irqs;
2788 }
2789 /* assign the mask for this irq */
2790 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2791 &q_vector->affinity_mask);
2792 }
2793
63741846 2794 vsi->irqs_ready = true;
41c445ff
JB		 2795 return 0;
2796
2797free_queue_irqs:
2798 while (vector) {
2799 vector--;
2800 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
2801 NULL);
2802 free_irq(pf->msix_entries[base + vector].vector,
2803 &(vsi->q_vectors[vector]));
2804 }
2805 return err;
2806}
2807
2808/**
2809 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
2810 * @vsi: the VSI being un-configured
2811 **/
2812static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
2813{
2814 struct i40e_pf *pf = vsi->back;
2815 struct i40e_hw *hw = &pf->hw;
2816 int base = vsi->base_vector;
2817 int i;
2818
2819 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 2820 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
2821 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 2822 }
2823
2824 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2825 for (i = vsi->base_vector;
2826 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2827 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
2828
2829 i40e_flush(hw);
2830 for (i = 0; i < vsi->num_q_vectors; i++)
2831 synchronize_irq(pf->msix_entries[i + base].vector);
2832 } else {
2833 /* Legacy and MSI mode - this stops all interrupt handling */
2834 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
2835 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
2836 i40e_flush(hw);
2837 synchronize_irq(pf->pdev->irq);
2838 }
2839}
2840
2841/**
2842 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
2843 * @vsi: the VSI being configured
2844 **/
2845static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
2846{
2847 struct i40e_pf *pf = vsi->back;
2848 int i;
2849
2850 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
2851 for (i = vsi->base_vector;
2852 i < (vsi->num_q_vectors + vsi->base_vector); i++)
2853 i40e_irq_dynamic_enable(vsi, i);
2854 } else {
2855 i40e_irq_dynamic_enable_icr0(pf);
2856 }
2857
1022cb6c 2858 i40e_flush(&pf->hw);
41c445ff
JB		 2859 return 0;
2860}
2861
2862/**
2863 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
2864 * @pf: board private structure
2865 **/
2866static void i40e_stop_misc_vector(struct i40e_pf *pf)
2867{
2868 /* Disable ICR 0 */
2869 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
2870 i40e_flush(&pf->hw);
2871}
2872
2873/**
2874 * i40e_intr - MSI/Legacy and non-queue interrupt handler
2875 * @irq: interrupt number
2876 * @data: pointer to a q_vector
2877 *
2878 * This is the handler used for all MSI/Legacy interrupts, and deals
2879 * with both queue and non-queue interrupts. This is also used in
2880 * MSIX mode to handle the non-queue interrupts.
2881 **/
2882static irqreturn_t i40e_intr(int irq, void *data)
2883{
2884 struct i40e_pf *pf = (struct i40e_pf *)data;
2885 struct i40e_hw *hw = &pf->hw;
5e823066 2886 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 2887 u32 icr0, icr0_remaining;
2888 u32 val, ena_mask;
2889
2890 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 2891 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 2892
116a57d4
SN		 2893 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
2894 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 2895 goto enable_intr;
41c445ff 2896
cd92e72f
SN		 2897 /* if interrupt but no bits showing, must be SWINT */
2898 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
2899 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
2900 pf->sw_int_count++;
2901
41c445ff
JB		 2902 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
2903 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
2904
2905 /* temporarily disable queue cause for NAPI processing */
2906 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
2907 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2908 wr32(hw, I40E_QINT_RQCTL(0), qval);
2909
2910 qval = rd32(hw, I40E_QINT_TQCTL(0));
2911 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
2912 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 2913
2914 if (!test_bit(__I40E_DOWN, &pf->state))
493fb300 2915 napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0]->napi);
41c445ff
JB		 2916 }
2917
2918 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
2919 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
2920 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
2921 }
2922
2923 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
2924 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
2925 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
2926 }
2927
2928 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
2929 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
2930 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
2931 }
2932
2933 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
2934 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
2935 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
2936 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
2937 val = rd32(hw, I40E_GLGEN_RSTAT);
2938 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
2939 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 2940 if (val == I40E_RESET_CORER) {
41c445ff 2941 pf->corer_count++;
4eb3f768 2942 } else if (val == I40E_RESET_GLOBR) {
41c445ff 2943 pf->globr_count++;
4eb3f768 2944 } else if (val == I40E_RESET_EMPR) {
41c445ff 2945 pf->empr_count++;
4eb3f768
SN		 2946 set_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
2947 }
41c445ff
JB		 2948 }
2949
9c010ee0
ASJ		 2950 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
2951 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
2952 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
2953 }
2954
beb0dff1
JK		 2955 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
2956 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
2957
2958 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 2959 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 2960 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 2961 }
beb0dff1
JK		 2962 }
2963
41c445ff
JB		 2964 /* If a critical error is pending we have no choice but to reset the
2965 * device.
2966 * Report and mask out any remaining unexpected interrupts.
2967 */
2968 icr0_remaining = icr0 & ena_mask;
2969 if (icr0_remaining) {
2970 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
2971 icr0_remaining);
9c010ee0 2972 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 2973 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 2974 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 2975 dev_info(&pf->pdev->dev, "device will be reset\n");
2976 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
2977 i40e_service_event_schedule(pf);
41c445ff
JB		 2978 }
2979 ena_mask &= ~icr0_remaining;
2980 }
5e823066 2981 ret = IRQ_HANDLED;
41c445ff 2982
5e823066 2983enable_intr:
41c445ff
JB		 2984 /* re-enable interrupt causes */
2985 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 2986 if (!test_bit(__I40E_DOWN, &pf->state)) {
2987 i40e_service_event_schedule(pf);
2988 i40e_irq_dynamic_enable_icr0(pf);
2989 }
2990
5e823066 2991 return ret;
41c445ff
JB		 2992}
2993
cbf61325
ASJ		 2994/**
2995 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
2996 * @tx_ring: tx ring to clean
2997 * @budget: how many cleans we're allowed
2998 *
2999 * Returns true if there's any budget left (e.g. the clean is finished)
3000 **/
3001static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3002{
3003 struct i40e_vsi *vsi = tx_ring->vsi;
3004 u16 i = tx_ring->next_to_clean;
3005 struct i40e_tx_buffer *tx_buf;
3006 struct i40e_tx_desc *tx_desc;
3007
3008 tx_buf = &tx_ring->tx_bi[i];
3009 tx_desc = I40E_TX_DESC(tx_ring, i);
3010 i -= tx_ring->count;
3011
3012 do {
3013 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3014
3015 /* if next_to_watch is not set then there is no work pending */
3016 if (!eop_desc)
3017 break;
3018
3019 /* prevent any other reads prior to eop_desc */
3020 read_barrier_depends();
3021
3022 /* if the descriptor isn't done, no work yet to do */
3023 if (!(eop_desc->cmd_type_offset_bsz &
3024 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3025 break;
3026
3027 /* clear next_to_watch to prevent false hangs */
3028 tx_buf->next_to_watch = NULL;
3029
3030 /* unmap skb header data */
3031 dma_unmap_single(tx_ring->dev,
3032 dma_unmap_addr(tx_buf, dma),
3033 dma_unmap_len(tx_buf, len),
3034 DMA_TO_DEVICE);
3035
3036 dma_unmap_len_set(tx_buf, len, 0);
3037
3038
3039 /* move to the next desc and buffer to clean */
3040 tx_buf++;
3041 tx_desc++;
3042 i++;
3043 if (unlikely(!i)) {
3044 i -= tx_ring->count;
3045 tx_buf = tx_ring->tx_bi;
3046 tx_desc = I40E_TX_DESC(tx_ring, 0);
3047 }
3048
3049 /* update budget accounting */
3050 budget--;
3051 } while (likely(budget));
3052
3053 i += tx_ring->count;
3054 tx_ring->next_to_clean = i;
3055
3056 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
3057 i40e_irq_dynamic_enable(vsi,
3058 tx_ring->q_vector->v_idx + vsi->base_vector);
3059 }
3060 return budget > 0;
3061}
3062
3063/**
3064 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3065 * @irq: interrupt number
3066 * @data: pointer to a q_vector
3067 **/
3068static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3069{
3070 struct i40e_q_vector *q_vector = data;
3071 struct i40e_vsi *vsi;
3072
3073 if (!q_vector->tx.ring)
3074 return IRQ_HANDLED;
3075
3076 vsi = q_vector->tx.ring->vsi;
3077 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3078
3079 return IRQ_HANDLED;
3080}
3081
41c445ff 3082/**
cd0b6fa6 3083 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3084 * @vsi: the VSI being configured
3085 * @v_idx: vector index
cd0b6fa6 3086 * @qp_idx: queue pair index
41c445ff 3087 **/
cd0b6fa6 3088static void map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3089{
493fb300 3090 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3091 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3092 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3093
3094 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3095 tx_ring->next = q_vector->tx.ring;
3096 q_vector->tx.ring = tx_ring;
41c445ff 3097 q_vector->tx.count++;
cd0b6fa6
AD		 3098
3099 rx_ring->q_vector = q_vector;
3100 rx_ring->next = q_vector->rx.ring;
3101 q_vector->rx.ring = rx_ring;
3102 q_vector->rx.count++;
41c445ff
JB		 3103}
3104
3105/**
3106 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3107 * @vsi: the VSI being configured
3108 *
3109 * This function maps descriptor rings to the queue-specific vectors
3110 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3111 * one vector per queue pair, but on a constrained vector budget, we
3112 * group the queue pairs as "efficiently" as possible.
3113 **/
3114static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3115{
3116 int qp_remaining = vsi->num_queue_pairs;
3117 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3118 int num_ringpairs;
41c445ff
JB		 3119 int v_start = 0;
3120 int qp_idx = 0;
3121
3122 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3123 * group them so there are multiple queues per vector.
3124 */
3125 for (; v_start < q_vectors && qp_remaining; v_start++) {
cd0b6fa6
AD		 3126 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3127
3128 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3129
3130 q_vector->num_ringpairs = num_ringpairs;
3131
3132 q_vector->rx.count = 0;
3133 q_vector->tx.count = 0;
3134 q_vector->rx.ring = NULL;
3135 q_vector->tx.ring = NULL;
3136
3137 while (num_ringpairs--) {
3138 map_vector_to_qp(vsi, v_start, qp_idx);
3139 qp_idx++;
3140 qp_remaining--;
41c445ff
JB		 3141 }
3142 }
3143}
3144
3145/**
3146 * i40e_vsi_request_irq - Request IRQ from the OS
3147 * @vsi: the VSI being configured
3148 * @basename: name for the vector
3149 **/
3150static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3151{
3152 struct i40e_pf *pf = vsi->back;
3153 int err;
3154
3155 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3156 err = i40e_vsi_request_irq_msix(vsi, basename);
3157 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3158 err = request_irq(pf->pdev->irq, i40e_intr, 0,
3159 pf->misc_int_name, pf);
3160 else
3161 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
3162 pf->misc_int_name, pf);
3163
3164 if (err)
3165 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3166
3167 return err;
3168}
3169
3170#ifdef CONFIG_NET_POLL_CONTROLLER
3171/**
3172 * i40e_netpoll - A Polling 'interrupt'handler
3173 * @netdev: network interface device structure
3174 *
3175 * This is used by netconsole to send skbs without having to re-enable
3176 * interrupts. It's not called while the normal interrupt routine is executing.
3177 **/
3178static void i40e_netpoll(struct net_device *netdev)
3179{
3180 struct i40e_netdev_priv *np = netdev_priv(netdev);
3181 struct i40e_vsi *vsi = np->vsi;
3182 struct i40e_pf *pf = vsi->back;
3183 int i;
3184
3185 /* if interface is down do nothing */
3186 if (test_bit(__I40E_DOWN, &vsi->state))
3187 return;
3188
3189 pf->flags |= I40E_FLAG_IN_NETPOLL;
3190 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3191 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3192 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3193 } else {
3194 i40e_intr(pf->pdev->irq, netdev);
3195 }
3196 pf->flags &= ~I40E_FLAG_IN_NETPOLL;
3197}
3198#endif
3199
3200/**
3201 * i40e_vsi_control_tx - Start or stop a VSI's rings
3202 * @vsi: the VSI being configured
3203 * @enable: start or stop the rings
3204 **/
3205static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3206{
3207 struct i40e_pf *pf = vsi->back;
3208 struct i40e_hw *hw = &pf->hw;
3209 int i, j, pf_q;
3210 u32 tx_reg;
3211
3212 pf_q = vsi->base_queue;
3213 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3214
3215 /* warn the TX unit of coming changes */
3216 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3217 if (!enable)
3218 udelay(10);
3219
6c5ef620 3220 for (j = 0; j < 50; j++) {
41c445ff 3221 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3222 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3223 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3224 break;
3225 usleep_range(1000, 2000);
3226 }
fda972f6 3227 /* Skip if the queue is already in the requested state */
7c122007 3228 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3229 continue;
41c445ff
JB		 3230
3231 /* turn on/off the queue */
c5c9eb9e
SN		 3232 if (enable) {
3233 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3234 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3235 } else {
41c445ff 3236 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3237 }
41c445ff
JB		 3238
3239 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
3240
3241 /* wait for the change to finish */
3242 for (j = 0; j < 10; j++) {
3243 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
7c122007
CS		 3244 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3245 break;
41c445ff
JB		 3246
3247 udelay(10);
3248 }
3249 if (j >= 10) {
3250 dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
3251 pf_q, (enable ? "en" : "dis"));
3252 return -ETIMEDOUT;
3253 }
3254 }
3255
7134f9ce
JB		 3256 if (hw->revision_id == 0)
3257 mdelay(50);
3258
41c445ff
JB		 3259 return 0;
3260}
3261
3262/**
3263 * i40e_vsi_control_rx - Start or stop a VSI's rings
3264 * @vsi: the VSI being configured
3265 * @enable: start or stop the rings
3266 **/
3267static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3268{
3269 struct i40e_pf *pf = vsi->back;
3270 struct i40e_hw *hw = &pf->hw;
3271 int i, j, pf_q;
3272 u32 rx_reg;
3273
3274 pf_q = vsi->base_queue;
3275 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3276 for (j = 0; j < 50; j++) {
41c445ff 3277 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3278 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3279 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3280 break;
3281 usleep_range(1000, 2000);
3282 }
41c445ff 3283
7c122007
CS		 3284 /* Skip if the queue is already in the requested state */
3285 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3286 continue;
41c445ff
JB		 3287
3288 /* turn on/off the queue */
3289 if (enable)
6c5ef620 3290 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3291 else
6c5ef620 3292 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3293 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3294
3295 /* wait for the change to finish */
3296 for (j = 0; j < 10; j++) {
3297 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
3298
7c122007
CS		 3299 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3300 break;
41c445ff
JB		 3301
3302 udelay(10);
3303 }
3304 if (j >= 10) {
3305 dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
3306 pf_q, (enable ? "en" : "dis"));
3307 return -ETIMEDOUT;
3308 }
3309 }
3310
3311 return 0;
3312}
3313
3314/**
3315 * i40e_vsi_control_rings - Start or stop a VSI's rings
3316 * @vsi: the VSI being configured
3317 * @enable: start or stop the rings
3318 **/
fc18eaa0 3319int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3320{
3b867b28 3321 int ret = 0;
41c445ff
JB		 3322
3323 /* do rx first for enable and last for disable */
3324 if (request) {
3325 ret = i40e_vsi_control_rx(vsi, request);
3326 if (ret)
3327 return ret;
3328 ret = i40e_vsi_control_tx(vsi, request);
3329 } else {
3b867b28
ASJ		 3330 /* Ignore return value, we need to shutdown whatever we can */
3331 i40e_vsi_control_tx(vsi, request);
3332 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3333 }
3334
3335 return ret;
3336}
3337
3338/**
3339 * i40e_vsi_free_irq - Free the irq association with the OS
3340 * @vsi: the VSI being configured
3341 **/
3342static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3343{
3344 struct i40e_pf *pf = vsi->back;
3345 struct i40e_hw *hw = &pf->hw;
3346 int base = vsi->base_vector;
3347 u32 val, qp;
3348 int i;
3349
3350 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3351 if (!vsi->q_vectors)
3352 return;
3353
63741846
SN		 3354 if (!vsi->irqs_ready)
3355 return;
3356
3357 vsi->irqs_ready = false;
41c445ff
JB		 3358 for (i = 0; i < vsi->num_q_vectors; i++) {
3359 u16 vector = i + base;
3360
3361 /* free only the irqs that were actually requested */
78681b1f
SN		 3362 if (!vsi->q_vectors[i] ||
3363 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3364 continue;
3365
3366 /* clear the affinity_mask in the IRQ descriptor */
3367 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3368 NULL);
3369 free_irq(pf->msix_entries[vector].vector,
493fb300 3370 vsi->q_vectors[i]);
41c445ff
JB		 3371
3372 /* Tear down the interrupt queue link list
3373 *
3374 * We know that they come in pairs and always
3375 * the Rx first, then the Tx. To clear the
3376 * link list, stick the EOL value into the
3377 * next_q field of the registers.
3378 */
3379 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3380 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3381 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3382 val |= I40E_QUEUE_END_OF_LIST
3383 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3384 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3385
3386 while (qp != I40E_QUEUE_END_OF_LIST) {
3387 u32 next;
3388
3389 val = rd32(hw, I40E_QINT_RQCTL(qp));
3390
3391 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3392 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3393 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3394 I40E_QINT_RQCTL_INTEVENT_MASK);
3395
3396 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3397 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3398
3399 wr32(hw, I40E_QINT_RQCTL(qp), val);
3400
3401 val = rd32(hw, I40E_QINT_TQCTL(qp));
3402
3403 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3404 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3405
3406 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3407 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3408 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3409 I40E_QINT_TQCTL_INTEVENT_MASK);
3410
3411 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3412 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3413
3414 wr32(hw, I40E_QINT_TQCTL(qp), val);
3415 qp = next;
3416 }
3417 }
3418 } else {
3419 free_irq(pf->pdev->irq, pf);
3420
3421 val = rd32(hw, I40E_PFINT_LNKLST0);
3422 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3423 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3424 val |= I40E_QUEUE_END_OF_LIST
3425 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
3426 wr32(hw, I40E_PFINT_LNKLST0, val);
3427
3428 val = rd32(hw, I40E_QINT_RQCTL(qp));
3429 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3430 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3431 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3432 I40E_QINT_RQCTL_INTEVENT_MASK);
3433
3434 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3435 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3436
3437 wr32(hw, I40E_QINT_RQCTL(qp), val);
3438
3439 val = rd32(hw, I40E_QINT_TQCTL(qp));
3440
3441 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3442 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3443 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3444 I40E_QINT_TQCTL_INTEVENT_MASK);
3445
3446 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3447 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3448
3449 wr32(hw, I40E_QINT_TQCTL(qp), val);
3450 }
3451}
3452
493fb300
AD		 3453/**
3454 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
3455 * @vsi: the VSI being configured
3456 * @v_idx: Index of vector to be freed
3457 *
3458 * This function frees the memory allocated to the q_vector. In addition if
3459 * NAPI is enabled it will delete any references to the NAPI struct prior
3460 * to freeing the q_vector.
3461 **/
3462static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
3463{
3464 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 3465 struct i40e_ring *ring;
493fb300
AD		 3466
3467 if (!q_vector)
3468 return;
3469
3470 /* disassociate q_vector from rings */
cd0b6fa6
AD		 3471 i40e_for_each_ring(ring, q_vector->tx)
3472 ring->q_vector = NULL;
3473
3474 i40e_for_each_ring(ring, q_vector->rx)
3475 ring->q_vector = NULL;
493fb300
AD		 3476
3477 /* only VSI w/ an associated netdev is set up w/ NAPI */
3478 if (vsi->netdev)
3479 netif_napi_del(&q_vector->napi);
3480
3481 vsi->q_vectors[v_idx] = NULL;
3482
3483 kfree_rcu(q_vector, rcu);
3484}
3485
41c445ff
JB		 3486/**
3487 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
3488 * @vsi: the VSI being un-configured
3489 *
3490 * This frees the memory allocated to the q_vectors and
3491 * deletes references to the NAPI struct.
3492 **/
3493static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
3494{
3495 int v_idx;
3496
493fb300
AD		 3497 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
3498 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 3499}
3500
3501/**
3502 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
3503 * @pf: board private structure
3504 **/
3505static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
3506{
3507 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
3508 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3509 pci_disable_msix(pf->pdev);
3510 kfree(pf->msix_entries);
3511 pf->msix_entries = NULL;
3512 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
3513 pci_disable_msi(pf->pdev);
3514 }
3515 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
3516}
3517
3518/**
3519 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
3520 * @pf: board private structure
3521 *
3522 * We go through and clear interrupt specific resources and reset the structure
3523 * to pre-load conditions
3524 **/
3525static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
3526{
3527 int i;
3528
3529 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 3530 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 3531 if (pf->vsi[i])
3532 i40e_vsi_free_q_vectors(pf->vsi[i]);
3533 i40e_reset_interrupt_capability(pf);
3534}
3535
3536/**
3537 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
3538 * @vsi: the VSI being configured
3539 **/
3540static void i40e_napi_enable_all(struct i40e_vsi *vsi)
3541{
3542 int q_idx;
3543
3544 if (!vsi->netdev)
3545 return;
3546
3547 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3548 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3549}
3550
3551/**
3552 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
3553 * @vsi: the VSI being configured
3554 **/
3555static void i40e_napi_disable_all(struct i40e_vsi *vsi)
3556{
3557 int q_idx;
3558
3559 if (!vsi->netdev)
3560 return;
3561
3562 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 3563 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 3564}
3565
90ef8d47
SN		 3566/**
3567 * i40e_vsi_close - Shut down a VSI
3568 * @vsi: the vsi to be quelled
3569 **/
3570static void i40e_vsi_close(struct i40e_vsi *vsi)
3571{
3572 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
3573 i40e_down(vsi);
3574 i40e_vsi_free_irq(vsi);
3575 i40e_vsi_free_tx_resources(vsi);
3576 i40e_vsi_free_rx_resources(vsi);
3577}
3578
41c445ff
JB		 3579/**
3580 * i40e_quiesce_vsi - Pause a given VSI
3581 * @vsi: the VSI being paused
3582 **/
3583static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
3584{
3585 if (test_bit(__I40E_DOWN, &vsi->state))
3586 return;
3587
3588 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
3589 if (vsi->netdev && netif_running(vsi->netdev)) {
3590 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
3591 } else {
90ef8d47 3592 i40e_vsi_close(vsi);
41c445ff
JB		 3593 }
3594}
3595
3596/**
3597 * i40e_unquiesce_vsi - Resume a given VSI
3598 * @vsi: the VSI being resumed
3599 **/
3600static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
3601{
3602 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
3603 return;
3604
3605 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
3606 if (vsi->netdev && netif_running(vsi->netdev))
3607 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
3608 else
8276f757 3609 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 3610}
3611
3612/**
3613 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
3614 * @pf: the PF
3615 **/
3616static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
3617{
3618 int v;
3619
505682cd 3620 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3621 if (pf->vsi[v])
3622 i40e_quiesce_vsi(pf->vsi[v]);
3623 }
3624}
3625
3626/**
3627 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
3628 * @pf: the PF
3629 **/
3630static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
3631{
3632 int v;
3633
505682cd 3634 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 3635 if (pf->vsi[v])
3636 i40e_unquiesce_vsi(pf->vsi[v]);
3637 }
3638}
3639
3640/**
3641 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
3642 * @dcbcfg: the corresponding DCBx configuration structure
3643 *
3644 * Return the number of TCs from given DCBx configuration
3645 **/
3646static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
3647{
078b5876
JB		 3648 u8 num_tc = 0;
3649 int i;
41c445ff
JB		 3650
3651 /* Scan the ETS Config Priority Table to find
3652 * traffic class enabled for a given priority
3653 * and use the traffic class index to get the
3654 * number of traffic classes enabled
3655 */
3656 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3657 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
3658 num_tc = dcbcfg->etscfg.prioritytable[i];
3659 }
3660
3661 /* Traffic class index starts from zero so
3662 * increment to return the actual count
3663 */
078b5876 3664 return num_tc + 1;
41c445ff
JB		 3665}
3666
3667/**
3668 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
3669 * @dcbcfg: the corresponding DCBx configuration structure
3670 *
3671 * Query the current DCB configuration and return the number of
3672 * traffic classes enabled from the given DCBX config
3673 **/
3674static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
3675{
3676 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
3677 u8 enabled_tc = 1;
3678 u8 i;
3679
3680 for (i = 0; i < num_tc; i++)
3681 enabled_tc |= 1 << i;
3682
3683 return enabled_tc;
3684}
3685
3686/**
3687 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
3688 * @pf: PF being queried
3689 *
3690 * Return number of traffic classes enabled for the given PF
3691 **/
3692static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
3693{
3694 struct i40e_hw *hw = &pf->hw;
3695 u8 i, enabled_tc;
3696 u8 num_tc = 0;
3697 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3698
3699 /* If DCB is not enabled then always in single TC */
3700 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3701 return 1;
3702
3703 /* MFP mode return count of enabled TCs for this PF */
3704 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3705 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3706 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3707 if (enabled_tc & (1 << i))
3708 num_tc++;
3709 }
3710 return num_tc;
3711 }
3712
3713 /* SFP mode will be enabled for all TCs on port */
3714 return i40e_dcb_get_num_tc(dcbcfg);
3715}
3716
3717/**
3718 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
3719 * @pf: PF being queried
3720 *
3721 * Return a bitmap for first enabled traffic class for this PF.
3722 **/
3723static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
3724{
3725 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
3726 u8 i = 0;
3727
3728 if (!enabled_tc)
3729 return 0x1; /* TC0 */
3730
3731 /* Find the first enabled TC */
3732 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3733 if (enabled_tc & (1 << i))
3734 break;
3735 }
3736
3737 return 1 << i;
3738}
3739
3740/**
3741 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
3742 * @pf: PF being queried
3743 *
3744 * Return a bitmap for enabled traffic classes for this PF.
3745 **/
3746static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
3747{
3748 /* If DCB is not enabled for this PF then just return default TC */
3749 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
3750 return i40e_pf_get_default_tc(pf);
3751
3752 /* MFP mode will have enabled TCs set by FW */
3753 if (pf->flags & I40E_FLAG_MFP_ENABLED)
3754 return pf->hw.func_caps.enabled_tcmap;
3755
3756 /* SFP mode we want PF to be enabled for all TCs */
3757 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
3758}
3759
3760/**
3761 * i40e_vsi_get_bw_info - Query VSI BW Information
3762 * @vsi: the VSI being queried
3763 *
3764 * Returns 0 on success, negative value on failure
3765 **/
3766static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
3767{
3768 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
3769 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
3770 struct i40e_pf *pf = vsi->back;
3771 struct i40e_hw *hw = &pf->hw;
dcae29be 3772 i40e_status aq_ret;
41c445ff 3773 u32 tc_bw_max;
41c445ff
JB		 3774 int i;
3775
3776 /* Get the VSI level BW configuration */
dcae29be
JB		 3777 aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3778 if (aq_ret) {
41c445ff
JB		 3779 dev_info(&pf->pdev->dev,
3780 "couldn't get pf vsi bw config, err %d, aq_err %d\n",
dcae29be
JB		 3781 aq_ret, pf->hw.aq.asq_last_status);
3782 return -EINVAL;
41c445ff
JB		 3783 }
3784
3785 /* Get the VSI level BW configuration per TC */
dcae29be 3786 aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6838b535 3787 NULL);
dcae29be 3788 if (aq_ret) {
41c445ff
JB		 3789 dev_info(&pf->pdev->dev,
3790 "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
dcae29be
JB		 3791 aq_ret, pf->hw.aq.asq_last_status);
3792 return -EINVAL;
41c445ff
JB		 3793 }
3794
3795 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
3796 dev_info(&pf->pdev->dev,
3797 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
3798 bw_config.tc_valid_bits,
3799 bw_ets_config.tc_valid_bits);
3800 /* Still continuing */
3801 }
3802
3803 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
3804 vsi->bw_max_quanta = bw_config.max_bw;
3805 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
3806 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
3807 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3808 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
3809 vsi->bw_ets_limit_credits[i] =
3810 le16_to_cpu(bw_ets_config.credits[i]);
3811 /* 3 bits out of 4 for each TC */
3812 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
3813 }
078b5876 3814
dcae29be 3815 return 0;
41c445ff
JB		 3816}
3817
3818/**
3819 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
3820 * @vsi: the VSI being configured
3821 * @enabled_tc: TC bitmap
3822 * @bw_credits: BW shared credits per TC
3823 *
3824 * Returns 0 on success, negative value on failure
3825 **/
dcae29be 3826static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 3827 u8 *bw_share)
3828{
3829 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
dcae29be
JB		 3830 i40e_status aq_ret;
3831 int i;
41c445ff
JB		 3832
3833 bw_data.tc_valid_bits = enabled_tc;
3834 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3835 bw_data.tc_bw_credits[i] = bw_share[i];
3836
dcae29be
JB		 3837 aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
3838 NULL);
3839 if (aq_ret) {
41c445ff 3840 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 3841 "AQ command Config VSI BW allocation per TC failed = %d\n",
3842 vsi->back->hw.aq.asq_last_status);
dcae29be 3843 return -EINVAL;
41c445ff
JB		 3844 }
3845
3846 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3847 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
3848
dcae29be 3849 return 0;
41c445ff
JB		 3850}
3851
3852/**
3853 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
3854 * @vsi: the VSI being configured
3855 * @enabled_tc: TC map to be enabled
3856 *
3857 **/
3858static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3859{
3860 struct net_device *netdev = vsi->netdev;
3861 struct i40e_pf *pf = vsi->back;
3862 struct i40e_hw *hw = &pf->hw;
3863 u8 netdev_tc = 0;
3864 int i;
3865 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
3866
3867 if (!netdev)
3868 return;
3869
3870 if (!enabled_tc) {
3871 netdev_reset_tc(netdev);
3872 return;
3873 }
3874
3875 /* Set up actual enabled TCs on the VSI */
3876 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
3877 return;
3878
3879 /* set per TC queues for the VSI */
3880 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3881 /* Only set TC queues for enabled tcs
3882 *
3883 * e.g. For a VSI that has TC0 and TC3 enabled the
3884 * enabled_tc bitmap would be 0x00001001; the driver
3885 * will set the numtc for netdev as 2 that will be
3886 * referenced by the netdev layer as TC 0 and 1.
3887 */
3888 if (vsi->tc_config.enabled_tc & (1 << i))
3889 netdev_set_tc_queue(netdev,
3890 vsi->tc_config.tc_info[i].netdev_tc,
3891 vsi->tc_config.tc_info[i].qcount,
3892 vsi->tc_config.tc_info[i].qoffset);
3893 }
3894
3895 /* Assign UP2TC map for the VSI */
3896 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
3897 /* Get the actual TC# for the UP */
3898 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
3899 /* Get the mapped netdev TC# for the UP */
3900 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
3901 netdev_set_prio_tc_map(netdev, i, netdev_tc);
3902 }
3903}
3904
3905/**
3906 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
3907 * @vsi: the VSI being configured
3908 * @ctxt: the ctxt buffer returned from AQ VSI update param command
3909 **/
3910static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
3911 struct i40e_vsi_context *ctxt)
3912{
3913 /* copy just the sections touched not the entire info
3914 * since not all sections are valid as returned by
3915 * update vsi params
3916 */
3917 vsi->info.mapping_flags = ctxt->info.mapping_flags;
3918 memcpy(&vsi->info.queue_mapping,
3919 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
3920 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
3921 sizeof(vsi->info.tc_mapping));
3922}
3923
3924/**
3925 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
3926 * @vsi: VSI to be configured
3927 * @enabled_tc: TC bitmap
3928 *
3929 * This configures a particular VSI for TCs that are mapped to the
3930 * given TC bitmap. It uses default bandwidth share for TCs across
3931 * VSIs to configure TC for a particular VSI.
3932 *
3933 * NOTE:
3934 * It is expected that the VSI queues have been quisced before calling
3935 * this function.
3936 **/
3937static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
3938{
3939 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
3940 struct i40e_vsi_context ctxt;
3941 int ret = 0;
3942 int i;
3943
3944 /* Check if enabled_tc is same as existing or new TCs */
3945 if (vsi->tc_config.enabled_tc == enabled_tc)
3946 return ret;
3947
3948 /* Enable ETS TCs with equal BW Share for now across all VSIs */
3949 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3950 if (enabled_tc & (1 << i))
3951 bw_share[i] = 1;
3952 }
3953
3954 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
3955 if (ret) {
3956 dev_info(&vsi->back->pdev->dev,
3957 "Failed configuring TC map %d for VSI %d\n",
3958 enabled_tc, vsi->seid);
3959 goto out;
3960 }
3961
3962 /* Update Queue Pairs Mapping for currently enabled UPs */
3963 ctxt.seid = vsi->seid;
3964 ctxt.pf_num = vsi->back->hw.pf_id;
3965 ctxt.vf_num = 0;
3966 ctxt.uplink_seid = vsi->uplink_seid;
3967 memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3968 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
3969
3970 /* Update the VSI after updating the VSI queue-mapping information */
3971 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
3972 if (ret) {
3973 dev_info(&vsi->back->pdev->dev,
3974 "update vsi failed, aq_err=%d\n",
3975 vsi->back->hw.aq.asq_last_status);
3976 goto out;
3977 }
3978 /* update the local VSI info with updated queue map */
3979 i40e_vsi_update_queue_map(vsi, &ctxt);
3980 vsi->info.valid_sections = 0;
3981
3982 /* Update current VSI BW information */
3983 ret = i40e_vsi_get_bw_info(vsi);
3984 if (ret) {
3985 dev_info(&vsi->back->pdev->dev,
3986 "Failed updating vsi bw info, aq_err=%d\n",
3987 vsi->back->hw.aq.asq_last_status);
3988 goto out;
3989 }
3990
3991 /* Update the netdev TC setup */
3992 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
3993out:
3994 return ret;
3995}
3996
4e3b35b0
NP		 3997/**
3998 * i40e_veb_config_tc - Configure TCs for given VEB
3999 * @veb: given VEB
4000 * @enabled_tc: TC bitmap
4001 *
4002 * Configures given TC bitmap for VEB (switching) element
4003 **/
4004int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4005{
4006 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4007 struct i40e_pf *pf = veb->pf;
4008 int ret = 0;
4009 int i;
4010
4011 /* No TCs or already enabled TCs just return */
4012 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4013 return ret;
4014
4015 bw_data.tc_valid_bits = enabled_tc;
4016 /* bw_data.absolute_credits is not set (relative) */
4017
4018 /* Enable ETS TCs with equal BW Share for now */
4019 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4020 if (enabled_tc & (1 << i))
4021 bw_data.tc_bw_share_credits[i] = 1;
4022 }
4023
4024 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4025 &bw_data, NULL);
4026 if (ret) {
4027 dev_info(&pf->pdev->dev,
4028 "veb bw config failed, aq_err=%d\n",
4029 pf->hw.aq.asq_last_status);
4030 goto out;
4031 }
4032
4033 /* Update the BW information */
4034 ret = i40e_veb_get_bw_info(veb);
4035 if (ret) {
4036 dev_info(&pf->pdev->dev,
4037 "Failed getting veb bw config, aq_err=%d\n",
4038 pf->hw.aq.asq_last_status);
4039 }
4040
4041out:
4042 return ret;
4043}
4044
4045#ifdef CONFIG_I40E_DCB
4046/**
4047 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4048 * @pf: PF struct
4049 *
4050 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4051 * the caller would've quiesce all the VSIs before calling
4052 * this function
4053 **/
4054static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4055{
4056 u8 tc_map = 0;
4057 int ret;
4058 u8 v;
4059
4060 /* Enable the TCs available on PF to all VEBs */
4061 tc_map = i40e_pf_get_tc_map(pf);
4062 for (v = 0; v < I40E_MAX_VEB; v++) {
4063 if (!pf->veb[v])
4064 continue;
4065 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4066 if (ret) {
4067 dev_info(&pf->pdev->dev,
4068 "Failed configuring TC for VEB seid=%d\n",
4069 pf->veb[v]->seid);
4070 /* Will try to configure as many components */
4071 }
4072 }
4073
4074 /* Update each VSI */
505682cd 4075 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4076 if (!pf->vsi[v])
4077 continue;
4078
4079 /* - Enable all TCs for the LAN VSI
4080 * - For all others keep them at TC0 for now
4081 */
4082 if (v == pf->lan_vsi)
4083 tc_map = i40e_pf_get_tc_map(pf);
4084 else
4085 tc_map = i40e_pf_get_default_tc(pf);
4086
4087 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4088 if (ret) {
4089 dev_info(&pf->pdev->dev,
4090 "Failed configuring TC for VSI seid=%d\n",
4091 pf->vsi[v]->seid);
4092 /* Will try to configure as many components */
4093 } else {
0672a091
NP		 4094 /* Re-configure VSI vectors based on updated TC map */
4095 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4096 if (pf->vsi[v]->netdev)
4097 i40e_dcbnl_set_all(pf->vsi[v]);
4098 }
4099 }
4100}
4101
4102/**
4103 * i40e_init_pf_dcb - Initialize DCB configuration
4104 * @pf: PF being configured
4105 *
4106 * Query the current DCB configuration and cache it
4107 * in the hardware structure
4108 **/
4109static int i40e_init_pf_dcb(struct i40e_pf *pf)
4110{
4111 struct i40e_hw *hw = &pf->hw;
4112 int err = 0;
4113
4114 if (pf->hw.func_caps.npar_enable)
4115 goto out;
4116
4117 /* Get the initial DCB configuration */
4118 err = i40e_init_dcb(hw);
4119 if (!err) {
4120 /* Device/Function is not DCBX capable */
4121 if ((!hw->func_caps.dcb) ||
4122 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4123 dev_info(&pf->pdev->dev,
4124 "DCBX offload is not supported or is disabled for this PF.\n");
4125
4126 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4127 goto out;
4128
4129 } else {
4130 /* When status is not DISABLED then DCBX in FW */
4131 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4132 DCB_CAP_DCBX_VER_IEEE;
4133 pf->flags |= I40E_FLAG_DCB_ENABLED;
4134 }
014269ff
NP		 4135 } else {
4136 dev_info(&pf->pdev->dev, "AQ Querying DCB configuration failed: %d\n",
4137 pf->hw.aq.asq_last_status);
4e3b35b0
NP		 4138 }
4139
4140out:
4141 return err;
4142}
4143#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 4144#define SPEED_SIZE 14
4145#define FC_SIZE 8
4146/**
4147 * i40e_print_link_message - print link up or down
4148 * @vsi: the VSI for which link needs a message
4149 */
4150static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
4151{
4152 char speed[SPEED_SIZE] = "Unknown";
4153 char fc[FC_SIZE] = "RX/TX";
4154
4155 if (!isup) {
4156 netdev_info(vsi->netdev, "NIC Link is Down\n");
4157 return;
4158 }
4159
4160 switch (vsi->back->hw.phy.link_info.link_speed) {
4161 case I40E_LINK_SPEED_40GB:
4162 strncpy(speed, "40 Gbps", SPEED_SIZE);
4163 break;
4164 case I40E_LINK_SPEED_10GB:
4165 strncpy(speed, "10 Gbps", SPEED_SIZE);
4166 break;
4167 case I40E_LINK_SPEED_1GB:
4168 strncpy(speed, "1000 Mbps", SPEED_SIZE);
4169 break;
4170 default:
4171 break;
4172 }
4173
4174 switch (vsi->back->hw.fc.current_mode) {
4175 case I40E_FC_FULL:
4176 strncpy(fc, "RX/TX", FC_SIZE);
4177 break;
4178 case I40E_FC_TX_PAUSE:
4179 strncpy(fc, "TX", FC_SIZE);
4180 break;
4181 case I40E_FC_RX_PAUSE:
4182 strncpy(fc, "RX", FC_SIZE);
4183 break;
4184 default:
4185 strncpy(fc, "None", FC_SIZE);
4186 break;
4187 }
4188
4189 netdev_info(vsi->netdev, "NIC Link is Up %s Full Duplex, Flow Control: %s\n",
4190 speed, fc);
4191}
4e3b35b0 4192
41c445ff
JB		 4193/**
4194 * i40e_up_complete - Finish the last steps of bringing up a connection
4195 * @vsi: the VSI being configured
4196 **/
4197static int i40e_up_complete(struct i40e_vsi *vsi)
4198{
4199 struct i40e_pf *pf = vsi->back;
4200 int err;
4201
4202 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4203 i40e_vsi_configure_msix(vsi);
4204 else
4205 i40e_configure_msi_and_legacy(vsi);
4206
4207 /* start rings */
4208 err = i40e_vsi_control_rings(vsi, true);
4209 if (err)
4210 return err;
4211
4212 clear_bit(__I40E_DOWN, &vsi->state);
4213 i40e_napi_enable_all(vsi);
4214 i40e_vsi_enable_irq(vsi);
4215
4216 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
4217 (vsi->netdev)) {
cf05ed08 4218 i40e_print_link_message(vsi, true);
41c445ff
JB		 4219 netif_tx_start_all_queues(vsi->netdev);
4220 netif_carrier_on(vsi->netdev);
6d779b41 4221 } else if (vsi->netdev) {
cf05ed08 4222 i40e_print_link_message(vsi, false);
41c445ff 4223 }
ca64fa4e
ASJ		 4224
4225 /* replay FDIR SB filters */
4226 if (vsi->type == I40E_VSI_FDIR)
4227 i40e_fdir_filter_restore(vsi);
41c445ff
JB		 4228 i40e_service_event_schedule(pf);
4229
4230 return 0;
4231}
4232
4233/**
4234 * i40e_vsi_reinit_locked - Reset the VSI
4235 * @vsi: the VSI being configured
4236 *
4237 * Rebuild the ring structs after some configuration
4238 * has changed, e.g. MTU size.
4239 **/
4240static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
4241{
4242 struct i40e_pf *pf = vsi->back;
4243
4244 WARN_ON(in_interrupt());
4245 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
4246 usleep_range(1000, 2000);
4247 i40e_down(vsi);
4248
4249 /* Give a VF some time to respond to the reset. The
4250 * two second wait is based upon the watchdog cycle in
4251 * the VF driver.
4252 */
4253 if (vsi->type == I40E_VSI_SRIOV)
4254 msleep(2000);
4255 i40e_up(vsi);
4256 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
4257}
4258
4259/**
4260 * i40e_up - Bring the connection back up after being down
4261 * @vsi: the VSI being configured
4262 **/
4263int i40e_up(struct i40e_vsi *vsi)
4264{
4265 int err;
4266
4267 err = i40e_vsi_configure(vsi);
4268 if (!err)
4269 err = i40e_up_complete(vsi);
4270
4271 return err;
4272}
4273
4274/**
4275 * i40e_down - Shutdown the connection processing
4276 * @vsi: the VSI being stopped
4277 **/
4278void i40e_down(struct i40e_vsi *vsi)
4279{
4280 int i;
4281
4282 /* It is assumed that the caller of this function
4283 * sets the vsi->state __I40E_DOWN bit.
4284 */
4285 if (vsi->netdev) {
4286 netif_carrier_off(vsi->netdev);
4287 netif_tx_disable(vsi->netdev);
4288 }
4289 i40e_vsi_disable_irq(vsi);
4290 i40e_vsi_control_rings(vsi, false);
4291 i40e_napi_disable_all(vsi);
4292
4293 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 4294 i40e_clean_tx_ring(vsi->tx_rings[i]);
4295 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 4296 }
4297}
4298
4299/**
4300 * i40e_setup_tc - configure multiple traffic classes
4301 * @netdev: net device to configure
4302 * @tc: number of traffic classes to enable
4303 **/
4304static int i40e_setup_tc(struct net_device *netdev, u8 tc)
4305{
4306 struct i40e_netdev_priv *np = netdev_priv(netdev);
4307 struct i40e_vsi *vsi = np->vsi;
4308 struct i40e_pf *pf = vsi->back;
4309 u8 enabled_tc = 0;
4310 int ret = -EINVAL;
4311 int i;
4312
4313 /* Check if DCB enabled to continue */
4314 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
4315 netdev_info(netdev, "DCB is not enabled for adapter\n");
4316 goto exit;
4317 }
4318
4319 /* Check if MFP enabled */
4320 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4321 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
4322 goto exit;
4323 }
4324
4325 /* Check whether tc count is within enabled limit */
4326 if (tc > i40e_pf_get_num_tc(pf)) {
4327 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
4328 goto exit;
4329 }
4330
4331 /* Generate TC map for number of tc requested */
4332 for (i = 0; i < tc; i++)
4333 enabled_tc |= (1 << i);
4334
4335 /* Requesting same TC configuration as already enabled */
4336 if (enabled_tc == vsi->tc_config.enabled_tc)
4337 return 0;
4338
4339 /* Quiesce VSI queues */
4340 i40e_quiesce_vsi(vsi);
4341
4342 /* Configure VSI for enabled TCs */
4343 ret = i40e_vsi_config_tc(vsi, enabled_tc);
4344 if (ret) {
4345 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
4346 vsi->seid);
4347 goto exit;
4348 }
4349
4350 /* Unquiesce VSI */
4351 i40e_unquiesce_vsi(vsi);
4352
4353exit:
4354 return ret;
4355}
4356
4357/**
4358 * i40e_open - Called when a network interface is made active
4359 * @netdev: network interface device structure
4360 *
4361 * The open entry point is called when a network interface is made
4362 * active by the system (IFF_UP). At this point all resources needed
4363 * for transmit and receive operations are allocated, the interrupt
4364 * handler is registered with the OS, the netdev watchdog subtask is
4365 * enabled, and the stack is notified that the interface is ready.
4366 *
4367 * Returns 0 on success, negative value on failure
4368 **/
4369static int i40e_open(struct net_device *netdev)
4370{
4371 struct i40e_netdev_priv *np = netdev_priv(netdev);
4372 struct i40e_vsi *vsi = np->vsi;
4373 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 4374 int err;
4375
4eb3f768
SN		 4376 /* disallow open during test or if eeprom is broken */
4377 if (test_bit(__I40E_TESTING, &pf->state) ||
4378 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 4379 return -EBUSY;
4380
4381 netif_carrier_off(netdev);
4382
6c167f58
EK		 4383 err = i40e_vsi_open(vsi);
4384 if (err)
4385 return err;
4386
059dab69
JB		 4387 /* configure global TSO hardware offload settings */
4388 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
4389 TCP_FLAG_FIN) >> 16);
4390 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
4391 TCP_FLAG_FIN |
4392 TCP_FLAG_CWR) >> 16);
4393 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
4394
6c167f58
EK		 4395#ifdef CONFIG_I40E_VXLAN
4396 vxlan_get_rx_port(netdev);
4397#endif
4398
4399 return 0;
4400}
4401
4402/**
4403 * i40e_vsi_open -
4404 * @vsi: the VSI to open
4405 *
4406 * Finish initialization of the VSI.
4407 *
4408 * Returns 0 on success, negative value on failure
4409 **/
4410int i40e_vsi_open(struct i40e_vsi *vsi)
4411{
4412 struct i40e_pf *pf = vsi->back;
4413 char int_name[IFNAMSIZ];
4414 int err;
4415
41c445ff
JB		 4416 /* allocate descriptors */
4417 err = i40e_vsi_setup_tx_resources(vsi);
4418 if (err)
4419 goto err_setup_tx;
4420 err = i40e_vsi_setup_rx_resources(vsi);
4421 if (err)
4422 goto err_setup_rx;
4423
4424 err = i40e_vsi_configure(vsi);
4425 if (err)
4426 goto err_setup_rx;
4427
c22e3c6c
SN		 4428 if (vsi->netdev) {
4429 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
4430 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
4431 err = i40e_vsi_request_irq(vsi, int_name);
4432 if (err)
4433 goto err_setup_rx;
4434
4435 /* Notify the stack of the actual queue counts. */
4436 err = netif_set_real_num_tx_queues(vsi->netdev,
4437 vsi->num_queue_pairs);
4438 if (err)
4439 goto err_set_queues;
4440
4441 err = netif_set_real_num_rx_queues(vsi->netdev,
4442 vsi->num_queue_pairs);
4443 if (err)
4444 goto err_set_queues;
8a9eb7d3
SN		 4445
4446 } else if (vsi->type == I40E_VSI_FDIR) {
4447 snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
4448 dev_driver_string(&pf->pdev->dev));
4449 err = i40e_vsi_request_irq(vsi, int_name);
c22e3c6c 4450 } else {
ce9ccb17 4451 err = -EINVAL;
6c167f58
EK		 4452 goto err_setup_rx;
4453 }
25946ddb 4454
41c445ff
JB		 4455 err = i40e_up_complete(vsi);
4456 if (err)
4457 goto err_up_complete;
4458
41c445ff
JB		 4459 return 0;
4460
4461err_up_complete:
4462 i40e_down(vsi);
25946ddb 4463err_set_queues:
41c445ff
JB		 4464 i40e_vsi_free_irq(vsi);
4465err_setup_rx:
4466 i40e_vsi_free_rx_resources(vsi);
4467err_setup_tx:
4468 i40e_vsi_free_tx_resources(vsi);
4469 if (vsi == pf->vsi[pf->lan_vsi])
4470 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
4471
4472 return err;
4473}
4474
17a73f6b
JG		 4475/**
4476 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
4477 * @pf: Pointer to pf
4478 *
4479 * This function destroys the hlist where all the Flow Director
4480 * filters were saved.
4481 **/
4482static void i40e_fdir_filter_exit(struct i40e_pf *pf)
4483{
4484 struct i40e_fdir_filter *filter;
4485 struct hlist_node *node2;
4486
4487 hlist_for_each_entry_safe(filter, node2,
4488 &pf->fdir_filter_list, fdir_node) {
4489 hlist_del(&filter->fdir_node);
4490 kfree(filter);
4491 }
4492 pf->fdir_pf_active_filters = 0;
4493}
4494
41c445ff
JB		 4495/**
4496 * i40e_close - Disables a network interface
4497 * @netdev: network interface device structure
4498 *
4499 * The close entry point is called when an interface is de-activated
4500 * by the OS. The hardware is still under the driver's control, but
4501 * this netdev interface is disabled.
4502 *
4503 * Returns 0, this is not allowed to fail
4504 **/
4505static int i40e_close(struct net_device *netdev)
4506{
4507 struct i40e_netdev_priv *np = netdev_priv(netdev);
4508 struct i40e_vsi *vsi = np->vsi;
4509
90ef8d47 4510 i40e_vsi_close(vsi);
41c445ff
JB		 4511
4512 return 0;
4513}
4514
4515/**
4516 * i40e_do_reset - Start a PF or Core Reset sequence
4517 * @pf: board private structure
4518 * @reset_flags: which reset is requested
4519 *
4520 * The essential difference in resets is that the PF Reset
4521 * doesn't clear the packet buffers, doesn't reset the PE
4522 * firmware, and doesn't bother the other PFs on the chip.
4523 **/
4524void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
4525{
4526 u32 val;
4527
4528 WARN_ON(in_interrupt());
4529
263fc48f
MW		 4530 if (i40e_check_asq_alive(&pf->hw))
4531 i40e_vc_notify_reset(pf);
4532
41c445ff
JB		 4533 /* do the biggest reset indicated */
4534 if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
4535
4536 /* Request a Global Reset
4537 *
4538 * This will start the chip's countdown to the actual full
4539 * chip reset event, and a warning interrupt to be sent
4540 * to all PFs, including the requestor. Our handler
4541 * for the warning interrupt will deal with the shutdown
4542 * and recovery of the switch setup.
4543 */
69bfb110 4544 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 4545 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4546 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
4547 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4548
4549 } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
4550
4551 /* Request a Core Reset
4552 *
4553 * Same as Global Reset, except does *not* include the MAC/PHY
4554 */
69bfb110 4555 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 4556 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4557 val |= I40E_GLGEN_RTRIG_CORER_MASK;
4558 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4559 i40e_flush(&pf->hw);
4560
7823fe34
SN		 4561 } else if (reset_flags & (1 << __I40E_EMP_RESET_REQUESTED)) {
4562
4563 /* Request a Firmware Reset
4564 *
4565 * Same as Global reset, plus restarting the
4566 * embedded firmware engine.
4567 */
4568 /* enable EMP Reset */
4569 val = rd32(&pf->hw, I40E_GLGEN_RSTENA_EMP);
4570 val |= I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK;
4571 wr32(&pf->hw, I40E_GLGEN_RSTENA_EMP, val);
4572
4573 /* force the reset */
4574 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
4575 val |= I40E_GLGEN_RTRIG_EMPFWR_MASK;
4576 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
4577 i40e_flush(&pf->hw);
4578
41c445ff
JB		 4579 } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
4580
4581 /* Request a PF Reset
4582 *
4583 * Resets only the PF-specific registers
4584 *
4585 * This goes directly to the tear-down and rebuild of
4586 * the switch, since we need to do all the recovery as
4587 * for the Core Reset.
4588 */
69bfb110 4589 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 4590 i40e_handle_reset_warning(pf);
4591
4592 } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
4593 int v;
4594
4595 /* Find the VSI(s) that requested a re-init */
4596 dev_info(&pf->pdev->dev,
4597 "VSI reinit requested\n");
505682cd 4598 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4599 struct i40e_vsi *vsi = pf->vsi[v];
4600 if (vsi != NULL &&
4601 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
4602 i40e_vsi_reinit_locked(pf->vsi[v]);
4603 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
4604 }
4605 }
4606
4607 /* no further action needed, so return now */
4608 return;
4609 } else {
4610 dev_info(&pf->pdev->dev,
4611 "bad reset request 0x%08x\n", reset_flags);
4612 return;
4613 }
4614}
4615
4e3b35b0
NP		 4616#ifdef CONFIG_I40E_DCB
4617/**
4618 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
4619 * @pf: board private structure
4620 * @old_cfg: current DCB config
4621 * @new_cfg: new DCB config
4622 **/
4623bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
4624 struct i40e_dcbx_config *old_cfg,
4625 struct i40e_dcbx_config *new_cfg)
4626{
4627 bool need_reconfig = false;
4628
4629 /* Check if ETS configuration has changed */
4630 if (memcmp(&new_cfg->etscfg,
4631 &old_cfg->etscfg,
4632 sizeof(new_cfg->etscfg))) {
4633 /* If Priority Table has changed reconfig is needed */
4634 if (memcmp(&new_cfg->etscfg.prioritytable,
4635 &old_cfg->etscfg.prioritytable,
4636 sizeof(new_cfg->etscfg.prioritytable))) {
4637 need_reconfig = true;
69bfb110 4638 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 4639 }
4640
4641 if (memcmp(&new_cfg->etscfg.tcbwtable,
4642 &old_cfg->etscfg.tcbwtable,
4643 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 4644 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 4645
4646 if (memcmp(&new_cfg->etscfg.tsatable,
4647 &old_cfg->etscfg.tsatable,
4648 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 4649 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 4650 }
4651
4652 /* Check if PFC configuration has changed */
4653 if (memcmp(&new_cfg->pfc,
4654 &old_cfg->pfc,
4655 sizeof(new_cfg->pfc))) {
4656 need_reconfig = true;
69bfb110 4657 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 4658 }
4659
4660 /* Check if APP Table has changed */
4661 if (memcmp(&new_cfg->app,
4662 &old_cfg->app,
3d9667a9 4663 sizeof(new_cfg->app))) {
4e3b35b0 4664 need_reconfig = true;
69bfb110 4665 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 4666 }
4e3b35b0
NP		 4667
4668 return need_reconfig;
4669}
4670
4671/**
4672 * i40e_handle_lldp_event - Handle LLDP Change MIB event
4673 * @pf: board private structure
4674 * @e: event info posted on ARQ
4675 **/
4676static int i40e_handle_lldp_event(struct i40e_pf *pf,
4677 struct i40e_arq_event_info *e)
4678{
4679 struct i40e_aqc_lldp_get_mib *mib =
4680 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
4681 struct i40e_hw *hw = &pf->hw;
4682 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
4683 struct i40e_dcbx_config tmp_dcbx_cfg;
4684 bool need_reconfig = false;
4685 int ret = 0;
4686 u8 type;
4687
4688 /* Ignore if event is not for Nearest Bridge */
4689 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
4690 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4691 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
4692 return ret;
4693
4694 /* Check MIB Type and return if event for Remote MIB update */
4695 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4696 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
4697 /* Update the remote cached instance and return */
4698 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
4699 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
4700 &hw->remote_dcbx_config);
4701 goto exit;
4702 }
4703
4704 /* Convert/store the DCBX data from LLDPDU temporarily */
4705 memset(&tmp_dcbx_cfg, 0, sizeof(tmp_dcbx_cfg));
4706 ret = i40e_lldp_to_dcb_config(e->msg_buf, &tmp_dcbx_cfg);
4707 if (ret) {
4708 /* Error in LLDPDU parsing return */
4709 dev_info(&pf->pdev->dev, "Failed parsing LLDPDU from event buffer\n");
4710 goto exit;
4711 }
4712
4713 /* No change detected in DCBX configs */
4714 if (!memcmp(&tmp_dcbx_cfg, dcbx_cfg, sizeof(tmp_dcbx_cfg))) {
69bfb110 4715 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 4716 goto exit;
4717 }
4718
4719 need_reconfig = i40e_dcb_need_reconfig(pf, dcbx_cfg, &tmp_dcbx_cfg);
4720
4721 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg);
4722
4723 /* Overwrite the new configuration */
4724 *dcbx_cfg = tmp_dcbx_cfg;
4725
4726 if (!need_reconfig)
4727 goto exit;
4728
4729 /* Reconfiguration needed quiesce all VSIs */
4730 i40e_pf_quiesce_all_vsi(pf);
4731
4732 /* Changes in configuration update VEB/VSI */
4733 i40e_dcb_reconfigure(pf);
4734
4735 i40e_pf_unquiesce_all_vsi(pf);
4736exit:
4737 return ret;
4738}
4739#endif /* CONFIG_I40E_DCB */
4740
23326186
ASJ		 4741/**
4742 * i40e_do_reset_safe - Protected reset path for userland calls.
4743 * @pf: board private structure
4744 * @reset_flags: which reset is requested
4745 *
4746 **/
4747void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
4748{
4749 rtnl_lock();
4750 i40e_do_reset(pf, reset_flags);
4751 rtnl_unlock();
4752}
4753
41c445ff
JB		 4754/**
4755 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
4756 * @pf: board private structure
4757 * @e: event info posted on ARQ
4758 *
4759 * Handler for LAN Queue Overflow Event generated by the firmware for PF
4760 * and VF queues
4761 **/
4762static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
4763 struct i40e_arq_event_info *e)
4764{
4765 struct i40e_aqc_lan_overflow *data =
4766 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
4767 u32 queue = le32_to_cpu(data->prtdcb_rupto);
4768 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
4769 struct i40e_hw *hw = &pf->hw;
4770 struct i40e_vf *vf;
4771 u16 vf_id;
4772
69bfb110
JB		 4773 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
4774 queue, qtx_ctl);
41c445ff
JB		 4775
4776 /* Queue belongs to VF, find the VF and issue VF reset */
4777 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
4778 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
4779 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
4780 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
4781 vf_id -= hw->func_caps.vf_base_id;
4782 vf = &pf->vf[vf_id];
4783 i40e_vc_notify_vf_reset(vf);
4784 /* Allow VF to process pending reset notification */
4785 msleep(20);
4786 i40e_reset_vf(vf, false);
4787 }
4788}
4789
4790/**
4791 * i40e_service_event_complete - Finish up the service event
4792 * @pf: board private structure
4793 **/
4794static void i40e_service_event_complete(struct i40e_pf *pf)
4795{
4796 BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
4797
4798 /* flush memory to make sure state is correct before next watchog */
4799 smp_mb__before_clear_bit();
4800 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
4801}
4802
55a5e60b
ASJ		 4803/**
4804 * i40e_get_current_fd_count - Get the count of FD filters programmed in the HW
4805 * @pf: board private structure
4806 **/
4807int i40e_get_current_fd_count(struct i40e_pf *pf)
4808{
4809 int val, fcnt_prog;
4810 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
4811 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
4812 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
4813 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
4814 return fcnt_prog;
4815}
4816
4817/**
4818 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
4819 * @pf: board private structure
4820 **/
4821void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
4822{
4823 u32 fcnt_prog, fcnt_avail;
4824
4825 /* Check if, FD SB or ATR was auto disabled and if there is enough room
4826 * to re-enable
4827 */
4828 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4829 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4830 return;
4831 fcnt_prog = i40e_get_current_fd_count(pf);
89132783 4832 fcnt_avail = i40e_get_fd_cnt_all(pf);
55a5e60b
ASJ		 4833 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
4834 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
4835 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
4836 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
4837 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
4838 }
4839 }
4840 /* Wait for some more space to be available to turn on ATR */
4841 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
4842 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4843 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
4844 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
4845 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
4846 }
4847 }
4848}
4849
41c445ff
JB		 4850/**
4851 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
4852 * @pf: board private structure
4853 **/
4854static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
4855{
4856 if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
4857 return;
4858
41c445ff
JB		 4859 /* if interface is down do nothing */
4860 if (test_bit(__I40E_DOWN, &pf->state))
4861 return;
55a5e60b
ASJ		 4862 i40e_fdir_check_and_reenable(pf);
4863
4864 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
4865 (pf->flags & I40E_FLAG_FD_SB_ENABLED))
4866 pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
41c445ff
JB		 4867}
4868
4869/**
4870 * i40e_vsi_link_event - notify VSI of a link event
4871 * @vsi: vsi to be notified
4872 * @link_up: link up or down
4873 **/
4874static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
4875{
4876 if (!vsi)
4877 return;
4878
4879 switch (vsi->type) {
4880 case I40E_VSI_MAIN:
4881 if (!vsi->netdev || !vsi->netdev_registered)
4882 break;
4883
4884 if (link_up) {
4885 netif_carrier_on(vsi->netdev);
4886 netif_tx_wake_all_queues(vsi->netdev);
4887 } else {
4888 netif_carrier_off(vsi->netdev);
4889 netif_tx_stop_all_queues(vsi->netdev);
4890 }
4891 break;
4892
4893 case I40E_VSI_SRIOV:
4894 break;
4895
4896 case I40E_VSI_VMDQ2:
4897 case I40E_VSI_CTRL:
4898 case I40E_VSI_MIRROR:
4899 default:
4900 /* there is no notification for other VSIs */
4901 break;
4902 }
4903}
4904
4905/**
4906 * i40e_veb_link_event - notify elements on the veb of a link event
4907 * @veb: veb to be notified
4908 * @link_up: link up or down
4909 **/
4910static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
4911{
4912 struct i40e_pf *pf;
4913 int i;
4914
4915 if (!veb || !veb->pf)
4916 return;
4917 pf = veb->pf;
4918
4919 /* depth first... */
4920 for (i = 0; i < I40E_MAX_VEB; i++)
4921 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
4922 i40e_veb_link_event(pf->veb[i], link_up);
4923
4924 /* ... now the local VSIs */
505682cd 4925 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4926 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
4927 i40e_vsi_link_event(pf->vsi[i], link_up);
4928}
4929
4930/**
4931 * i40e_link_event - Update netif_carrier status
4932 * @pf: board private structure
4933 **/
4934static void i40e_link_event(struct i40e_pf *pf)
4935{
4936 bool new_link, old_link;
4937
4938 new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
4939 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
4940
4941 if (new_link == old_link)
4942 return;
6d779b41 4943 if (!test_bit(__I40E_DOWN, &pf->vsi[pf->lan_vsi]->state))
cf05ed08 4944 i40e_print_link_message(pf->vsi[pf->lan_vsi], new_link);
41c445ff
JB		 4945
4946 /* Notify the base of the switch tree connected to
4947 * the link. Floating VEBs are not notified.
4948 */
4949 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
4950 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
4951 else
4952 i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
4953
4954 if (pf->vf)
4955 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 4956
4957 if (pf->flags & I40E_FLAG_PTP)
4958 i40e_ptp_set_increment(pf);
41c445ff
JB		 4959}
4960
4961/**
4962 * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
4963 * @pf: board private structure
4964 *
4965 * Set the per-queue flags to request a check for stuck queues in the irq
4966 * clean functions, then force interrupts to be sure the irq clean is called.
4967 **/
4968static void i40e_check_hang_subtask(struct i40e_pf *pf)
4969{
4970 int i, v;
4971
4972 /* If we're down or resetting, just bail */
4973 if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
4974 return;
4975
4976 /* for each VSI/netdev
4977 * for each Tx queue
4978 * set the check flag
4979 * for each q_vector
4980 * force an interrupt
4981 */
505682cd 4982 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4983 struct i40e_vsi *vsi = pf->vsi[v];
4984 int armed = 0;
4985
4986 if (!pf->vsi[v] ||
4987 test_bit(__I40E_DOWN, &vsi->state) ||
4988 (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
4989 continue;
4990
4991 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b 4992 set_check_for_tx_hang(vsi->tx_rings[i]);
41c445ff 4993 if (test_bit(__I40E_HANG_CHECK_ARMED,
9f65e15b 4994 &vsi->tx_rings[i]->state))
41c445ff
JB		 4995 armed++;
4996 }
4997
4998 if (armed) {
4999 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
5000 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
5001 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
5002 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
5003 } else {
5004 u16 vec = vsi->base_vector - 1;
5005 u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
5006 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
5007 for (i = 0; i < vsi->num_q_vectors; i++, vec++)
5008 wr32(&vsi->back->hw,
5009 I40E_PFINT_DYN_CTLN(vec), val);
5010 }
5011 i40e_flush(&vsi->back->hw);
5012 }
5013 }
5014}
5015
5016/**
5017 * i40e_watchdog_subtask - Check and bring link up
5018 * @pf: board private structure
5019 **/
5020static void i40e_watchdog_subtask(struct i40e_pf *pf)
5021{
5022 int i;
5023
5024 /* if interface is down do nothing */
5025 if (test_bit(__I40E_DOWN, &pf->state) ||
5026 test_bit(__I40E_CONFIG_BUSY, &pf->state))
5027 return;
5028
5029 /* Update the stats for active netdevs so the network stack
5030 * can look at updated numbers whenever it cares to
5031 */
505682cd 5032 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5033 if (pf->vsi[i] && pf->vsi[i]->netdev)
5034 i40e_update_stats(pf->vsi[i]);
5035
5036 /* Update the stats for the active switching components */
5037 for (i = 0; i < I40E_MAX_VEB; i++)
5038 if (pf->veb[i])
5039 i40e_update_veb_stats(pf->veb[i]);
beb0dff1
JK		 5040
5041 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 5042}
5043
5044/**
5045 * i40e_reset_subtask - Set up for resetting the device and driver
5046 * @pf: board private structure
5047 **/
5048static void i40e_reset_subtask(struct i40e_pf *pf)
5049{
5050 u32 reset_flags = 0;
5051
23326186 5052 rtnl_lock();
41c445ff
JB		 5053 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
5054 reset_flags |= (1 << __I40E_REINIT_REQUESTED);
5055 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
5056 }
5057 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
5058 reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
5059 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5060 }
5061 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
5062 reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
5063 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
5064 }
5065 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
5066 reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
5067 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
5068 }
5069
5070 /* If there's a recovery already waiting, it takes
5071 * precedence before starting a new reset sequence.
5072 */
5073 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
5074 i40e_handle_reset_warning(pf);
23326186 5075 goto unlock;
41c445ff
JB		 5076 }
5077
5078 /* If we're already down or resetting, just bail */
5079 if (reset_flags &&
5080 !test_bit(__I40E_DOWN, &pf->state) &&
5081 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
5082 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 5083
5084unlock:
5085 rtnl_unlock();
41c445ff
JB		 5086}
5087
5088/**
5089 * i40e_handle_link_event - Handle link event
5090 * @pf: board private structure
5091 * @e: event info posted on ARQ
5092 **/
5093static void i40e_handle_link_event(struct i40e_pf *pf,
5094 struct i40e_arq_event_info *e)
5095{
5096 struct i40e_hw *hw = &pf->hw;
5097 struct i40e_aqc_get_link_status *status =
5098 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
5099 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
5100
5101 /* save off old link status information */
5102 memcpy(&pf->hw.phy.link_info_old, hw_link_info,
5103 sizeof(pf->hw.phy.link_info_old));
5104
5105 /* update link status */
5106 hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
5107 hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
5108 hw_link_info->link_info = status->link_info;
5109 hw_link_info->an_info = status->an_info;
5110 hw_link_info->ext_info = status->ext_info;
5111 hw_link_info->lse_enable =
5112 le16_to_cpu(status->command_flags) &
5113 I40E_AQ_LSE_ENABLE;
5114
5115 /* process the event */
5116 i40e_link_event(pf);
5117
5118 /* Do a new status request to re-enable LSE reporting
5119 * and load new status information into the hw struct,
5120 * then see if the status changed while processing the
5121 * initial event.
5122 */
5123 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
5124 i40e_link_event(pf);
5125}
5126
5127/**
5128 * i40e_clean_adminq_subtask - Clean the AdminQ rings
5129 * @pf: board private structure
5130 **/
5131static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
5132{
5133 struct i40e_arq_event_info event;
5134 struct i40e_hw *hw = &pf->hw;
5135 u16 pending, i = 0;
5136 i40e_status ret;
5137 u16 opcode;
86df242b 5138 u32 oldval;
41c445ff
JB		 5139 u32 val;
5140
5141 if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
5142 return;
5143
86df242b
SN		 5144 /* check for error indications */
5145 val = rd32(&pf->hw, pf->hw.aq.arq.len);
5146 oldval = val;
5147 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
5148 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
5149 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
5150 }
5151 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
5152 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
5153 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
5154 }
5155 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
5156 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
5157 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
5158 }
5159 if (oldval != val)
5160 wr32(&pf->hw, pf->hw.aq.arq.len, val);
5161
5162 val = rd32(&pf->hw, pf->hw.aq.asq.len);
5163 oldval = val;
5164 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
5165 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
5166 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
5167 }
5168 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
5169 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
5170 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
5171 }
5172 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
5173 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
5174 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
5175 }
5176 if (oldval != val)
5177 wr32(&pf->hw, pf->hw.aq.asq.len, val);
5178
3197ce22 5179 event.msg_size = I40E_MAX_AQ_BUF_SIZE;
41c445ff
JB		 5180 event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
5181 if (!event.msg_buf)
5182 return;
5183
5184 do {
2f019123 5185 event.msg_size = I40E_MAX_AQ_BUF_SIZE; /* reinit each time */
41c445ff
JB		 5186 ret = i40e_clean_arq_element(hw, &event, &pending);
5187 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
5188 dev_info(&pf->pdev->dev, "No ARQ event found\n");
5189 break;
5190 } else if (ret) {
5191 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
5192 break;
5193 }
5194
5195 opcode = le16_to_cpu(event.desc.opcode);
5196 switch (opcode) {
5197
5198 case i40e_aqc_opc_get_link_status:
5199 i40e_handle_link_event(pf, &event);
5200 break;
5201 case i40e_aqc_opc_send_msg_to_pf:
5202 ret = i40e_vc_process_vf_msg(pf,
5203 le16_to_cpu(event.desc.retval),
5204 le32_to_cpu(event.desc.cookie_high),
5205 le32_to_cpu(event.desc.cookie_low),
5206 event.msg_buf,
5207 event.msg_size);
5208 break;
5209 case i40e_aqc_opc_lldp_update_mib:
69bfb110 5210 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 5211#ifdef CONFIG_I40E_DCB
5212 rtnl_lock();
5213 ret = i40e_handle_lldp_event(pf, &event);
5214 rtnl_unlock();
5215#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 5216 break;
5217 case i40e_aqc_opc_event_lan_overflow:
69bfb110 5218 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 5219 i40e_handle_lan_overflow_event(pf, &event);
5220 break;
0467bc91
SN		 5221 case i40e_aqc_opc_send_msg_to_peer:
5222 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
5223 break;
41c445ff
JB		 5224 default:
5225 dev_info(&pf->pdev->dev,
0467bc91
SN		 5226 "ARQ Error: Unknown event 0x%04x received\n",
5227 opcode);
41c445ff
JB		 5228 break;
5229 }
5230 } while (pending && (i++ < pf->adminq_work_limit));
5231
5232 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
5233 /* re-enable Admin queue interrupt cause */
5234 val = rd32(hw, I40E_PFINT_ICR0_ENA);
5235 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
5236 wr32(hw, I40E_PFINT_ICR0_ENA, val);
5237 i40e_flush(hw);
5238
5239 kfree(event.msg_buf);
5240}
5241
4eb3f768
SN		 5242/**
5243 * i40e_verify_eeprom - make sure eeprom is good to use
5244 * @pf: board private structure
5245 **/
5246static void i40e_verify_eeprom(struct i40e_pf *pf)
5247{
5248 int err;
5249
5250 err = i40e_diag_eeprom_test(&pf->hw);
5251 if (err) {
5252 /* retry in case of garbage read */
5253 err = i40e_diag_eeprom_test(&pf->hw);
5254 if (err) {
5255 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
5256 err);
5257 set_bit(__I40E_BAD_EEPROM, &pf->state);
5258 }
5259 }
5260
5261 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
5262 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
5263 clear_bit(__I40E_BAD_EEPROM, &pf->state);
5264 }
5265}
5266
41c445ff
JB		 5267/**
5268 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
5269 * @veb: pointer to the VEB instance
5270 *
5271 * This is a recursive function that first builds the attached VSIs then
5272 * recurses in to build the next layer of VEB. We track the connections
5273 * through our own index numbers because the seid's from the HW could
5274 * change across the reset.
5275 **/
5276static int i40e_reconstitute_veb(struct i40e_veb *veb)
5277{
5278 struct i40e_vsi *ctl_vsi = NULL;
5279 struct i40e_pf *pf = veb->pf;
5280 int v, veb_idx;
5281 int ret;
5282
5283 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 5284 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 5285 if (pf->vsi[v] &&
5286 pf->vsi[v]->veb_idx == veb->idx &&
5287 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
5288 ctl_vsi = pf->vsi[v];
5289 break;
5290 }
5291 }
5292 if (!ctl_vsi) {
5293 dev_info(&pf->pdev->dev,
5294 "missing owner VSI for veb_idx %d\n", veb->idx);
5295 ret = -ENOENT;
5296 goto end_reconstitute;
5297 }
5298 if (ctl_vsi != pf->vsi[pf->lan_vsi])
5299 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5300 ret = i40e_add_vsi(ctl_vsi);
5301 if (ret) {
5302 dev_info(&pf->pdev->dev,
5303 "rebuild of owner VSI failed: %d\n", ret);
5304 goto end_reconstitute;
5305 }
5306 i40e_vsi_reset_stats(ctl_vsi);
5307
5308 /* create the VEB in the switch and move the VSI onto the VEB */
5309 ret = i40e_add_veb(veb, ctl_vsi);
5310 if (ret)
5311 goto end_reconstitute;
5312
5313 /* create the remaining VSIs attached to this VEB */
505682cd 5314 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5315 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
5316 continue;
5317
5318 if (pf->vsi[v]->veb_idx == veb->idx) {
5319 struct i40e_vsi *vsi = pf->vsi[v];
5320 vsi->uplink_seid = veb->seid;
5321 ret = i40e_add_vsi(vsi);
5322 if (ret) {
5323 dev_info(&pf->pdev->dev,
5324 "rebuild of vsi_idx %d failed: %d\n",
5325 v, ret);
5326 goto end_reconstitute;
5327 }
5328 i40e_vsi_reset_stats(vsi);
5329 }
5330 }
5331
5332 /* create any VEBs attached to this VEB - RECURSION */
5333 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
5334 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
5335 pf->veb[veb_idx]->uplink_seid = veb->seid;
5336 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
5337 if (ret)
5338 break;
5339 }
5340 }
5341
5342end_reconstitute:
5343 return ret;
5344}
5345
5346/**
5347 * i40e_get_capabilities - get info about the HW
5348 * @pf: the PF struct
5349 **/
5350static int i40e_get_capabilities(struct i40e_pf *pf)
5351{
5352 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
5353 u16 data_size;
5354 int buf_len;
5355 int err;
5356
5357 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
5358 do {
5359 cap_buf = kzalloc(buf_len, GFP_KERNEL);
5360 if (!cap_buf)
5361 return -ENOMEM;
5362
5363 /* this loads the data into the hw struct for us */
5364 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
5365 &data_size,
5366 i40e_aqc_opc_list_func_capabilities,
5367 NULL);
5368 /* data loaded, buffer no longer needed */
5369 kfree(cap_buf);
5370
5371 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
5372 /* retry with a larger buffer */
5373 buf_len = data_size;
5374 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
5375 dev_info(&pf->pdev->dev,
5376 "capability discovery failed: aq=%d\n",
5377 pf->hw.aq.asq_last_status);
5378 return -ENODEV;
5379 }
5380 } while (err);
5381
ac71b7ba
ASJ		 5382 if (((pf->hw.aq.fw_maj_ver == 2) && (pf->hw.aq.fw_min_ver < 22)) ||
5383 (pf->hw.aq.fw_maj_ver < 2)) {
5384 pf->hw.func_caps.num_msix_vectors++;
5385 pf->hw.func_caps.num_msix_vectors_vf++;
5386 }
5387
41c445ff
JB		 5388 if (pf->hw.debug_mask & I40E_DEBUG_USER)
5389 dev_info(&pf->pdev->dev,
5390 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
5391 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
5392 pf->hw.func_caps.num_msix_vectors,
5393 pf->hw.func_caps.num_msix_vectors_vf,
5394 pf->hw.func_caps.fd_filters_guaranteed,
5395 pf->hw.func_caps.fd_filters_best_effort,
5396 pf->hw.func_caps.num_tx_qp,
5397 pf->hw.func_caps.num_vsis);
5398
7134f9ce
JB		 5399#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
5400 + pf->hw.func_caps.num_vfs)
5401 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
5402 dev_info(&pf->pdev->dev,
5403 "got num_vsis %d, setting num_vsis to %d\n",
5404 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
5405 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
5406 }
5407
41c445ff
JB		 5408 return 0;
5409}
5410
cbf61325
ASJ		 5411static int i40e_vsi_clear(struct i40e_vsi *vsi);
5412
41c445ff 5413/**
cbf61325 5414 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 5415 * @pf: board private structure
5416 **/
cbf61325 5417static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 5418{
5419 struct i40e_vsi *vsi;
8a9eb7d3 5420 int i;
41c445ff 5421
cbf61325 5422 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 5423 return;
5424
cbf61325 5425 /* find existing VSI and see if it needs configuring */
41c445ff 5426 vsi = NULL;
505682cd 5427 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 5428 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 5429 vsi = pf->vsi[i];
cbf61325
ASJ		 5430 break;
5431 }
5432 }
5433
5434 /* create a new VSI if none exists */
41c445ff 5435 if (!vsi) {
cbf61325
ASJ		 5436 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
5437 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 5438 if (!vsi) {
5439 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 5440 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
5441 return;
41c445ff 5442 }
41c445ff 5443 }
cbf61325 5444
8a9eb7d3 5445 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 5446}
5447
5448/**
5449 * i40e_fdir_teardown - release the Flow Director resources
5450 * @pf: board private structure
5451 **/
5452static void i40e_fdir_teardown(struct i40e_pf *pf)
5453{
5454 int i;
5455
17a73f6b 5456 i40e_fdir_filter_exit(pf);
505682cd 5457 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 5458 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
5459 i40e_vsi_release(pf->vsi[i]);
5460 break;
5461 }
5462 }
5463}
5464
5465/**
f650a38b 5466 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 5467 * @pf: board private structure
5468 *
f650a38b
ASJ		 5469 * Close up the VFs and other things in prep for pf Reset.
5470 **/
5471static int i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 5472{
41c445ff 5473 struct i40e_hw *hw = &pf->hw;
60442dea 5474 i40e_status ret = 0;
41c445ff
JB		 5475 u32 v;
5476
5477 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
5478 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
f650a38b 5479 return 0;
41c445ff 5480
69bfb110 5481 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 5482
41c445ff
JB		 5483 /* quiesce the VSIs and their queues that are not already DOWN */
5484 i40e_pf_quiesce_all_vsi(pf);
5485
505682cd 5486 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 5487 if (pf->vsi[v])
5488 pf->vsi[v]->seid = 0;
5489 }
5490
5491 i40e_shutdown_adminq(&pf->hw);
5492
f650a38b 5493 /* call shutdown HMC */
60442dea
SN		 5494 if (hw->hmc.hmc_obj) {
5495 ret = i40e_shutdown_lan_hmc(hw);
5496 if (ret) {
5497 dev_warn(&pf->pdev->dev,
5498 "shutdown_lan_hmc failed: %d\n", ret);
5499 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5500 }
f650a38b
ASJ		 5501 }
5502 return ret;
5503}
5504
44033fac
JB		 5505/**
5506 * i40e_send_version - update firmware with driver version
5507 * @pf: PF struct
5508 */
5509static void i40e_send_version(struct i40e_pf *pf)
5510{
5511 struct i40e_driver_version dv;
5512
5513 dv.major_version = DRV_VERSION_MAJOR;
5514 dv.minor_version = DRV_VERSION_MINOR;
5515 dv.build_version = DRV_VERSION_BUILD;
5516 dv.subbuild_version = 0;
5517 strncpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
5518 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
5519}
5520
f650a38b 5521/**
4dda12e6 5522 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 5523 * @pf: board private structure
bc7d338f 5524 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 5525 **/
bc7d338f 5526static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 5527{
f650a38b
ASJ		 5528 struct i40e_hw *hw = &pf->hw;
5529 i40e_status ret;
5530 u32 v;
5531
41c445ff
JB		 5532 /* Now we wait for GRST to settle out.
5533 * We don't have to delete the VEBs or VSIs from the hw switch
5534 * because the reset will make them disappear.
5535 */
5536 ret = i40e_pf_reset(hw);
b5565400 5537 if (ret) {
41c445ff 5538 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
b5565400
AA		 5539 goto end_core_reset;
5540 }
41c445ff
JB		 5541 pf->pfr_count++;
5542
5543 if (test_bit(__I40E_DOWN, &pf->state))
5544 goto end_core_reset;
69bfb110 5545 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 5546
5547 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
5548 ret = i40e_init_adminq(&pf->hw);
5549 if (ret) {
5550 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
5551 goto end_core_reset;
5552 }
5553
4eb3f768
SN		 5554 /* re-verify the eeprom if we just had an EMP reset */
5555 if (test_bit(__I40E_EMP_RESET_REQUESTED, &pf->state)) {
5556 clear_bit(__I40E_EMP_RESET_REQUESTED, &pf->state);
5557 i40e_verify_eeprom(pf);
5558 }
5559
e78ac4bf 5560 i40e_clear_pxe_mode(hw);
41c445ff
JB		 5561 ret = i40e_get_capabilities(pf);
5562 if (ret) {
5563 dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
5564 ret);
5565 goto end_core_reset;
5566 }
5567
41c445ff
JB		 5568 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
5569 hw->func_caps.num_rx_qp,
5570 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
5571 if (ret) {
5572 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
5573 goto end_core_reset;
5574 }
5575 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
5576 if (ret) {
5577 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
5578 goto end_core_reset;
5579 }
5580
4e3b35b0
NP		 5581#ifdef CONFIG_I40E_DCB
5582 ret = i40e_init_pf_dcb(pf);
5583 if (ret) {
5584 dev_info(&pf->pdev->dev, "init_pf_dcb failed: %d\n", ret);
5585 goto end_core_reset;
5586 }
5587#endif /* CONFIG_I40E_DCB */
5588
41c445ff 5589 /* do basic switch setup */
bc7d338f 5590 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 5591 if (ret)
5592 goto end_core_reset;
5593
5594 /* Rebuild the VSIs and VEBs that existed before reset.
5595 * They are still in our local switch element arrays, so only
5596 * need to rebuild the switch model in the HW.
5597 *
5598 * If there were VEBs but the reconstitution failed, we'll try
5599 * try to recover minimal use by getting the basic PF VSI working.
5600 */
5601 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 5602 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 5603 /* find the one VEB connected to the MAC, and find orphans */
5604 for (v = 0; v < I40E_MAX_VEB; v++) {
5605 if (!pf->veb[v])
5606 continue;
5607
5608 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
5609 pf->veb[v]->uplink_seid == 0) {
5610 ret = i40e_reconstitute_veb(pf->veb[v]);
5611
5612 if (!ret)
5613 continue;
5614
5615 /* If Main VEB failed, we're in deep doodoo,
5616 * so give up rebuilding the switch and set up
5617 * for minimal rebuild of PF VSI.
5618 * If orphan failed, we'll report the error
5619 * but try to keep going.
5620 */
5621 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
5622 dev_info(&pf->pdev->dev,
5623 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
5624 ret);
5625 pf->vsi[pf->lan_vsi]->uplink_seid
5626 = pf->mac_seid;
5627 break;
5628 } else if (pf->veb[v]->uplink_seid == 0) {
5629 dev_info(&pf->pdev->dev,
5630 "rebuild of orphan VEB failed: %d\n",
5631 ret);
5632 }
5633 }
5634 }
5635 }
5636
5637 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
5638 dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
5639 /* no VEB, so rebuild only the Main VSI */
5640 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
5641 if (ret) {
5642 dev_info(&pf->pdev->dev,
5643 "rebuild of Main VSI failed: %d\n", ret);
5644 goto end_core_reset;
5645 }
5646 }
5647
5648 /* reinit the misc interrupt */
5649 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5650 ret = i40e_setup_misc_vector(pf);
5651
5652 /* restart the VSIs that were rebuilt and running before the reset */
5653 i40e_pf_unquiesce_all_vsi(pf);
5654
69f64b2b
MW		 5655 if (pf->num_alloc_vfs) {
5656 for (v = 0; v < pf->num_alloc_vfs; v++)
5657 i40e_reset_vf(&pf->vf[v], true);
5658 }
5659
41c445ff 5660 /* tell the firmware that we're starting */
44033fac 5661 i40e_send_version(pf);
41c445ff 5662
41c445ff
JB		 5663end_core_reset:
5664 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
5665}
5666
f650a38b
ASJ		 5667/**
5668 * i40e_handle_reset_warning - prep for the pf to reset, reset and rebuild
5669 * @pf: board private structure
5670 *
5671 * Close up the VFs and other things in prep for a Core Reset,
5672 * then get ready to rebuild the world.
5673 **/
5674static void i40e_handle_reset_warning(struct i40e_pf *pf)
5675{
5676 i40e_status ret;
5677
5678 ret = i40e_prep_for_reset(pf);
5679 if (!ret)
bc7d338f 5680 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 5681}
5682
41c445ff
JB		 5683/**
5684 * i40e_handle_mdd_event
5685 * @pf: pointer to the pf structure
5686 *
5687 * Called from the MDD irq handler to identify possibly malicious vfs
5688 **/
5689static void i40e_handle_mdd_event(struct i40e_pf *pf)
5690{
5691 struct i40e_hw *hw = &pf->hw;
5692 bool mdd_detected = false;
5693 struct i40e_vf *vf;
5694 u32 reg;
5695 int i;
5696
5697 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
5698 return;
5699
5700 /* find what triggered the MDD event */
5701 reg = rd32(hw, I40E_GL_MDET_TX);
5702 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
5703 u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
5704 >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
5705 u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
5706 >> I40E_GL_MDET_TX_EVENT_SHIFT;
5707 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
5708 >> I40E_GL_MDET_TX_QUEUE_SHIFT;
5709 dev_info(&pf->pdev->dev,
f29eaa3d 5710 "Malicious Driver Detection event 0x%02x on TX queue %d of function 0x%02x\n",
41c445ff
JB		 5711 event, queue, func);
5712 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
5713 mdd_detected = true;
5714 }
5715 reg = rd32(hw, I40E_GL_MDET_RX);
5716 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
5717 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
5718 >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
5719 u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
5720 >> I40E_GL_MDET_RX_EVENT_SHIFT;
5721 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
5722 >> I40E_GL_MDET_RX_QUEUE_SHIFT;
5723 dev_info(&pf->pdev->dev,
f29eaa3d 5724 "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
41c445ff
JB		 5725 event, queue, func);
5726 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
5727 mdd_detected = true;
5728 }
5729
5730 /* see if one of the VFs needs its hand slapped */
5731 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
5732 vf = &(pf->vf[i]);
5733 reg = rd32(hw, I40E_VP_MDET_TX(i));
5734 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
5735 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
5736 vf->num_mdd_events++;
5737 dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
5738 }
5739
5740 reg = rd32(hw, I40E_VP_MDET_RX(i));
5741 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
5742 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
5743 vf->num_mdd_events++;
5744 dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
5745 }
5746
5747 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
5748 dev_info(&pf->pdev->dev,
5749 "Too many MDD events on VF %d, disabled\n", i);
5750 dev_info(&pf->pdev->dev,
5751 "Use PF Control I/F to re-enable the VF\n");
5752 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
5753 }
5754 }
5755
5756 /* re-enable mdd interrupt cause */
5757 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
5758 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
5759 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
5760 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
5761 i40e_flush(hw);
5762}
5763
a1c9a9d9
JK		 5764#ifdef CONFIG_I40E_VXLAN
5765/**
5766 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
5767 * @pf: board private structure
5768 **/
5769static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
5770{
a1c9a9d9
JK		 5771 struct i40e_hw *hw = &pf->hw;
5772 i40e_status ret;
5773 u8 filter_index;
5774 __be16 port;
5775 int i;
5776
5777 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
5778 return;
5779
5780 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
5781
5782 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5783 if (pf->pending_vxlan_bitmap & (1 << i)) {
5784 pf->pending_vxlan_bitmap &= ~(1 << i);
5785 port = pf->vxlan_ports[i];
5786 ret = port ?
5787 i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9
JK		 5788 I40E_AQC_TUNNEL_TYPE_VXLAN,
5789 &filter_index, NULL)
5790 : i40e_aq_del_udp_tunnel(hw, i, NULL);
5791
5792 if (ret) {
5793 dev_info(&pf->pdev->dev, "Failed to execute AQ command for %s port %d with index %d\n",
5794 port ? "adding" : "deleting",
5795 ntohs(port), port ? i : i);
5796
5797 pf->vxlan_ports[i] = 0;
5798 } else {
5799 dev_info(&pf->pdev->dev, "%s port %d with AQ command with index %d\n",
5800 port ? "Added" : "Deleted",
5801 ntohs(port), port ? i : filter_index);
5802 }
5803 }
5804 }
5805}
5806
5807#endif
41c445ff
JB		 5808/**
5809 * i40e_service_task - Run the driver's async subtasks
5810 * @work: pointer to work_struct containing our data
5811 **/
5812static void i40e_service_task(struct work_struct *work)
5813{
5814 struct i40e_pf *pf = container_of(work,
5815 struct i40e_pf,
5816 service_task);
5817 unsigned long start_time = jiffies;
5818
5819 i40e_reset_subtask(pf);
5820 i40e_handle_mdd_event(pf);
5821 i40e_vc_process_vflr_event(pf);
5822 i40e_watchdog_subtask(pf);
5823 i40e_fdir_reinit_subtask(pf);
5824 i40e_check_hang_subtask(pf);
5825 i40e_sync_filters_subtask(pf);
a1c9a9d9
JK		 5826#ifdef CONFIG_I40E_VXLAN
5827 i40e_sync_vxlan_filters_subtask(pf);
5828#endif
41c445ff
JB		 5829 i40e_clean_adminq_subtask(pf);
5830
5831 i40e_service_event_complete(pf);
5832
5833 /* If the tasks have taken longer than one timer cycle or there
5834 * is more work to be done, reschedule the service task now
5835 * rather than wait for the timer to tick again.
5836 */
5837 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
5838 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
5839 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
5840 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
5841 i40e_service_event_schedule(pf);
5842}
5843
5844/**
5845 * i40e_service_timer - timer callback
5846 * @data: pointer to PF struct
5847 **/
5848static void i40e_service_timer(unsigned long data)
5849{
5850 struct i40e_pf *pf = (struct i40e_pf *)data;
5851
5852 mod_timer(&pf->service_timer,
5853 round_jiffies(jiffies + pf->service_timer_period));
5854 i40e_service_event_schedule(pf);
5855}
5856
5857/**
5858 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
5859 * @vsi: the VSI being configured
5860 **/
5861static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
5862{
5863 struct i40e_pf *pf = vsi->back;
5864
5865 switch (vsi->type) {
5866 case I40E_VSI_MAIN:
5867 vsi->alloc_queue_pairs = pf->num_lan_qps;
5868 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5869 I40E_REQ_DESCRIPTOR_MULTIPLE);
5870 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5871 vsi->num_q_vectors = pf->num_lan_msix;
5872 else
5873 vsi->num_q_vectors = 1;
5874
5875 break;
5876
5877 case I40E_VSI_FDIR:
5878 vsi->alloc_queue_pairs = 1;
5879 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
5880 I40E_REQ_DESCRIPTOR_MULTIPLE);
5881 vsi->num_q_vectors = 1;
5882 break;
5883
5884 case I40E_VSI_VMDQ2:
5885 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
5886 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5887 I40E_REQ_DESCRIPTOR_MULTIPLE);
5888 vsi->num_q_vectors = pf->num_vmdq_msix;
5889 break;
5890
5891 case I40E_VSI_SRIOV:
5892 vsi->alloc_queue_pairs = pf->num_vf_qps;
5893 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
5894 I40E_REQ_DESCRIPTOR_MULTIPLE);
5895 break;
5896
5897 default:
5898 WARN_ON(1);
5899 return -ENODATA;
5900 }
5901
5902 return 0;
5903}
5904
f650a38b
ASJ		 5905/**
5906 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
5907 * @type: VSI pointer
bc7d338f 5908 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 5909 *
5910 * On error: returns error code (negative)
5911 * On success: returns 0
5912 **/
bc7d338f 5913static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 5914{
5915 int size;
5916 int ret = 0;
5917
ac6c5e3d 5918 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 5919 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
5920 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
5921 if (!vsi->tx_rings)
5922 return -ENOMEM;
f650a38b
ASJ		 5923 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
5924
bc7d338f
ASJ		 5925 if (alloc_qvectors) {
5926 /* allocate memory for q_vector pointers */
5927 size = sizeof(struct i40e_q_vectors *) * vsi->num_q_vectors;
5928 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
5929 if (!vsi->q_vectors) {
5930 ret = -ENOMEM;
5931 goto err_vectors;
5932 }
f650a38b
ASJ		 5933 }
5934 return ret;
5935
5936err_vectors:
5937 kfree(vsi->tx_rings);
5938 return ret;
5939}
5940
41c445ff
JB		 5941/**
5942 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
5943 * @pf: board private structure
5944 * @type: type of VSI
5945 *
5946 * On error: returns error code (negative)
5947 * On success: returns vsi index in PF (positive)
5948 **/
5949static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
5950{
5951 int ret = -ENODEV;
5952 struct i40e_vsi *vsi;
5953 int vsi_idx;
5954 int i;
5955
5956 /* Need to protect the allocation of the VSIs at the PF level */
5957 mutex_lock(&pf->switch_mutex);
5958
5959 /* VSI list may be fragmented if VSI creation/destruction has
5960 * been happening. We can afford to do a quick scan to look
5961 * for any free VSIs in the list.
5962 *
5963 * find next empty vsi slot, looping back around if necessary
5964 */
5965 i = pf->next_vsi;
505682cd 5966 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 5967 i++;
505682cd 5968 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 5969 i = 0;
5970 while (i < pf->next_vsi && pf->vsi[i])
5971 i++;
5972 }
5973
505682cd 5974 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 5975 vsi_idx = i; /* Found one! */
5976 } else {
5977 ret = -ENODEV;
493fb300 5978 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 5979 }
5980 pf->next_vsi = ++i;
5981
5982 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
5983 if (!vsi) {
5984 ret = -ENOMEM;
493fb300 5985 goto unlock_pf;
41c445ff
JB		 5986 }
5987 vsi->type = type;
5988 vsi->back = pf;
5989 set_bit(__I40E_DOWN, &vsi->state);
5990 vsi->flags = 0;
5991 vsi->idx = vsi_idx;
5992 vsi->rx_itr_setting = pf->rx_itr_default;
5993 vsi->tx_itr_setting = pf->tx_itr_default;
5994 vsi->netdev_registered = false;
5995 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
5996 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 5997 vsi->irqs_ready = false;
41c445ff 5998
9f65e15b
AD		 5999 ret = i40e_set_num_rings_in_vsi(vsi);
6000 if (ret)
6001 goto err_rings;
6002
bc7d338f 6003 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 6004 if (ret)
9f65e15b 6005 goto err_rings;
493fb300 6006
41c445ff
JB		 6007 /* Setup default MSIX irq handler for VSI */
6008 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
6009
6010 pf->vsi[vsi_idx] = vsi;
6011 ret = vsi_idx;
493fb300
AD		 6012 goto unlock_pf;
6013
9f65e15b 6014err_rings:
493fb300
AD		 6015 pf->next_vsi = i - 1;
6016 kfree(vsi);
6017unlock_pf:
41c445ff
JB		 6018 mutex_unlock(&pf->switch_mutex);
6019 return ret;
6020}
6021
f650a38b
ASJ		 6022/**
6023 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
6024 * @type: VSI pointer
bc7d338f 6025 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 6026 *
6027 * On error: returns error code (negative)
6028 * On success: returns 0
6029 **/
bc7d338f 6030static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 6031{
6032 /* free the ring and vector containers */
bc7d338f
ASJ		 6033 if (free_qvectors) {
6034 kfree(vsi->q_vectors);
6035 vsi->q_vectors = NULL;
6036 }
f650a38b
ASJ		 6037 kfree(vsi->tx_rings);
6038 vsi->tx_rings = NULL;
6039 vsi->rx_rings = NULL;
6040}
6041
41c445ff
JB		 6042/**
6043 * i40e_vsi_clear - Deallocate the VSI provided
6044 * @vsi: the VSI being un-configured
6045 **/
6046static int i40e_vsi_clear(struct i40e_vsi *vsi)
6047{
6048 struct i40e_pf *pf;
6049
6050 if (!vsi)
6051 return 0;
6052
6053 if (!vsi->back)
6054 goto free_vsi;
6055 pf = vsi->back;
6056
6057 mutex_lock(&pf->switch_mutex);
6058 if (!pf->vsi[vsi->idx]) {
6059 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
6060 vsi->idx, vsi->idx, vsi, vsi->type);
6061 goto unlock_vsi;
6062 }
6063
6064 if (pf->vsi[vsi->idx] != vsi) {
6065 dev_err(&pf->pdev->dev,
6066 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
6067 pf->vsi[vsi->idx]->idx,
6068 pf->vsi[vsi->idx],
6069 pf->vsi[vsi->idx]->type,
6070 vsi->idx, vsi, vsi->type);
6071 goto unlock_vsi;
6072 }
6073
6074 /* updates the pf for this cleared vsi */
6075 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
6076 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
6077
bc7d338f 6078 i40e_vsi_free_arrays(vsi, true);
493fb300 6079
41c445ff
JB		 6080 pf->vsi[vsi->idx] = NULL;
6081 if (vsi->idx < pf->next_vsi)
6082 pf->next_vsi = vsi->idx;
6083
6084unlock_vsi:
6085 mutex_unlock(&pf->switch_mutex);
6086free_vsi:
6087 kfree(vsi);
6088
6089 return 0;
6090}
6091
9f65e15b
AD		 6092/**
6093 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
6094 * @vsi: the VSI being cleaned
6095 **/
be1d5eea 6096static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 6097{
6098 int i;
6099
8e9dca53 6100 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 6101 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 6102 kfree_rcu(vsi->tx_rings[i], rcu);
6103 vsi->tx_rings[i] = NULL;
6104 vsi->rx_rings[i] = NULL;
6105 }
be1d5eea 6106 }
9f65e15b
AD		 6107}
6108
41c445ff
JB		 6109/**
6110 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
6111 * @vsi: the VSI being configured
6112 **/
6113static int i40e_alloc_rings(struct i40e_vsi *vsi)
6114{
e7046ee1 6115 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 6116 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 6117 int i;
6118
41c445ff 6119 /* Set basic values in the rings to be used later during open() */
d7397644 6120 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 6121 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 6122 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
6123 if (!tx_ring)
6124 goto err_out;
41c445ff
JB		 6125
6126 tx_ring->queue_index = i;
6127 tx_ring->reg_idx = vsi->base_queue + i;
6128 tx_ring->ring_active = false;
6129 tx_ring->vsi = vsi;
6130 tx_ring->netdev = vsi->netdev;
6131 tx_ring->dev = &pf->pdev->dev;
6132 tx_ring->count = vsi->num_desc;
6133 tx_ring->size = 0;
6134 tx_ring->dcb_tc = 0;
9f65e15b 6135 vsi->tx_rings[i] = tx_ring;
41c445ff 6136
9f65e15b 6137 rx_ring = &tx_ring[1];
41c445ff
JB		 6138 rx_ring->queue_index = i;
6139 rx_ring->reg_idx = vsi->base_queue + i;
6140 rx_ring->ring_active = false;
6141 rx_ring->vsi = vsi;
6142 rx_ring->netdev = vsi->netdev;
6143 rx_ring->dev = &pf->pdev->dev;
6144 rx_ring->count = vsi->num_desc;
6145 rx_ring->size = 0;
6146 rx_ring->dcb_tc = 0;
6147 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
6148 set_ring_16byte_desc_enabled(rx_ring);
6149 else
6150 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 6151 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 6152 }
6153
6154 return 0;
9f65e15b
AD		 6155
6156err_out:
6157 i40e_vsi_clear_rings(vsi);
6158 return -ENOMEM;
41c445ff
JB		 6159}
6160
6161/**
6162 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
6163 * @pf: board private structure
6164 * @vectors: the number of MSI-X vectors to request
6165 *
6166 * Returns the number of vectors reserved, or error
6167 **/
6168static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
6169{
7b37f376
AG		 6170 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
6171 I40E_MIN_MSIX, vectors);
6172 if (vectors < 0) {
41c445ff 6173 dev_info(&pf->pdev->dev,
7b37f376 6174 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 6175 vectors = 0;
6176 }
6177
6178 return vectors;
6179}
6180
6181/**
6182 * i40e_init_msix - Setup the MSIX capability
6183 * @pf: board private structure
6184 *
6185 * Work with the OS to set up the MSIX vectors needed.
6186 *
6187 * Returns 0 on success, negative on failure
6188 **/
6189static int i40e_init_msix(struct i40e_pf *pf)
6190{
6191 i40e_status err = 0;
6192 struct i40e_hw *hw = &pf->hw;
6193 int v_budget, i;
6194 int vec;
6195
6196 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6197 return -ENODEV;
6198
6199 /* The number of vectors we'll request will be comprised of:
6200 * - Add 1 for "other" cause for Admin Queue events, etc.
6201 * - The number of LAN queue pairs
f8ff1464
ASJ		 6202 * - Queues being used for RSS.
6203 * We don't need as many as max_rss_size vectors.
6204 * use rss_size instead in the calculation since that
6205 * is governed by number of cpus in the system.
6206 * - assumes symmetric Tx/Rx pairing
41c445ff
JB		 6207 * - The number of VMDq pairs
6208 * Once we count this up, try the request.
6209 *
6210 * If we can't get what we want, we'll simplify to nearly nothing
6211 * and try again. If that still fails, we punt.
6212 */
f8ff1464 6213 pf->num_lan_msix = pf->num_lan_qps - (pf->rss_size_max - pf->rss_size);
41c445ff
JB		 6214 pf->num_vmdq_msix = pf->num_vmdq_qps;
6215 v_budget = 1 + pf->num_lan_msix;
6216 v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
60ea5f83 6217 if (pf->flags & I40E_FLAG_FD_SB_ENABLED)
41c445ff
JB		 6218 v_budget++;
6219
6220 /* Scale down if necessary, and the rings will share vectors */
6221 v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
6222
6223 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
6224 GFP_KERNEL);
6225 if (!pf->msix_entries)
6226 return -ENOMEM;
6227
6228 for (i = 0; i < v_budget; i++)
6229 pf->msix_entries[i].entry = i;
6230 vec = i40e_reserve_msix_vectors(pf, v_budget);
6231 if (vec < I40E_MIN_MSIX) {
6232 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
6233 kfree(pf->msix_entries);
6234 pf->msix_entries = NULL;
6235 return -ENODEV;
6236
6237 } else if (vec == I40E_MIN_MSIX) {
6238 /* Adjust for minimal MSIX use */
77fa28be 6239 dev_info(&pf->pdev->dev, "Features disabled, not enough MSI-X vectors\n");
41c445ff
JB		 6240 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
6241 pf->num_vmdq_vsis = 0;
6242 pf->num_vmdq_qps = 0;
6243 pf->num_vmdq_msix = 0;
6244 pf->num_lan_qps = 1;
6245 pf->num_lan_msix = 1;
6246
6247 } else if (vec != v_budget) {
6248 /* Scale vector usage down */
6249 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
6250 vec--; /* reserve the misc vector */
6251
6252 /* partition out the remaining vectors */
6253 switch (vec) {
6254 case 2:
6255 pf->num_vmdq_vsis = 1;
6256 pf->num_lan_msix = 1;
6257 break;
6258 case 3:
6259 pf->num_vmdq_vsis = 1;
6260 pf->num_lan_msix = 2;
6261 break;
6262 default:
6263 pf->num_lan_msix = min_t(int, (vec / 2),
6264 pf->num_lan_qps);
6265 pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
6266 I40E_DEFAULT_NUM_VMDQ_VSI);
6267 break;
6268 }
6269 }
6270
6271 return err;
6272}
6273
493fb300 6274/**
90e04070 6275 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 6276 * @vsi: the VSI being configured
6277 * @v_idx: index of the vector in the vsi struct
6278 *
6279 * We allocate one q_vector. If allocation fails we return -ENOMEM.
6280 **/
90e04070 6281static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 6282{
6283 struct i40e_q_vector *q_vector;
6284
6285 /* allocate q_vector */
6286 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
6287 if (!q_vector)
6288 return -ENOMEM;
6289
6290 q_vector->vsi = vsi;
6291 q_vector->v_idx = v_idx;
6292 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
6293 if (vsi->netdev)
6294 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 6295 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 6296
cd0b6fa6
AD		 6297 q_vector->rx.latency_range = I40E_LOW_LATENCY;
6298 q_vector->tx.latency_range = I40E_LOW_LATENCY;
6299
493fb300
AD		 6300 /* tie q_vector and vsi together */
6301 vsi->q_vectors[v_idx] = q_vector;
6302
6303 return 0;
6304}
6305
41c445ff 6306/**
90e04070 6307 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 6308 * @vsi: the VSI being configured
6309 *
6310 * We allocate one q_vector per queue interrupt. If allocation fails we
6311 * return -ENOMEM.
6312 **/
90e04070 6313static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 6314{
6315 struct i40e_pf *pf = vsi->back;
6316 int v_idx, num_q_vectors;
493fb300 6317 int err;
41c445ff
JB		 6318
6319 /* if not MSIX, give the one vector only to the LAN VSI */
6320 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6321 num_q_vectors = vsi->num_q_vectors;
6322 else if (vsi == pf->vsi[pf->lan_vsi])
6323 num_q_vectors = 1;
6324 else
6325 return -EINVAL;
6326
41c445ff 6327 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 6328 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 6329 if (err)
6330 goto err_out;
41c445ff
JB		 6331 }
6332
6333 return 0;
493fb300
AD		 6334
6335err_out:
6336 while (v_idx--)
6337 i40e_free_q_vector(vsi, v_idx);
6338
6339 return err;
41c445ff
JB		 6340}
6341
6342/**
6343 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
6344 * @pf: board private structure to initialize
6345 **/
6346static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
6347{
6348 int err = 0;
6349
6350 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
6351 err = i40e_init_msix(pf);
6352 if (err) {
60ea5f83
JB		 6353 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
6354 I40E_FLAG_RSS_ENABLED |
6355 I40E_FLAG_DCB_ENABLED |
6356 I40E_FLAG_SRIOV_ENABLED |
6357 I40E_FLAG_FD_SB_ENABLED |
6358 I40E_FLAG_FD_ATR_ENABLED |
6359 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 6360
6361 /* rework the queue expectations without MSIX */
6362 i40e_determine_queue_usage(pf);
6363 }
6364 }
6365
6366 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
6367 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 6368 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
41c445ff
JB		 6369 err = pci_enable_msi(pf->pdev);
6370 if (err) {
958a3e3b 6371 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", err);
41c445ff
JB		 6372 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
6373 }
6374 }
6375
958a3e3b 6376 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 6377 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 6378
41c445ff
JB		 6379 /* track first vector for misc interrupts */
6380 err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
6381}
6382
6383/**
6384 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
6385 * @pf: board private structure
6386 *
6387 * This sets up the handler for MSIX 0, which is used to manage the
6388 * non-queue interrupts, e.g. AdminQ and errors. This is not used
6389 * when in MSI or Legacy interrupt mode.
6390 **/
6391static int i40e_setup_misc_vector(struct i40e_pf *pf)
6392{
6393 struct i40e_hw *hw = &pf->hw;
6394 int err = 0;
6395
6396 /* Only request the irq if this is the first time through, and
6397 * not when we're rebuilding after a Reset
6398 */
6399 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
6400 err = request_irq(pf->msix_entries[0].vector,
6401 i40e_intr, 0, pf->misc_int_name, pf);
6402 if (err) {
6403 dev_info(&pf->pdev->dev,
77fa28be
CS		 6404 "request_irq for %s failed: %d\n",
6405 pf->misc_int_name, err);
41c445ff
JB		 6406 return -EFAULT;
6407 }
6408 }
6409
6410 i40e_enable_misc_int_causes(hw);
6411
6412 /* associate no queues to the misc vector */
6413 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
6414 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
6415
6416 i40e_flush(hw);
6417
6418 i40e_irq_dynamic_enable_icr0(pf);
6419
6420 return err;
6421}
6422
6423/**
6424 * i40e_config_rss - Prepare for RSS if used
6425 * @pf: board private structure
6426 **/
6427static int i40e_config_rss(struct i40e_pf *pf)
6428{
41c445ff
JB		 6429 /* Set of random keys generated using kernel random number generator */
6430 static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
6431 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
6432 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
6433 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
4617e8c0
ASJ		 6434 struct i40e_hw *hw = &pf->hw;
6435 u32 lut = 0;
6436 int i, j;
6437 u64 hena;
41c445ff
JB		 6438
6439 /* Fill out hash function seed */
6440 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6441 wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
6442
6443 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
6444 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
6445 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
12dc4fe3 6446 hena |= I40E_DEFAULT_RSS_HENA;
41c445ff
JB		 6447 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
6448 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
6449
6450 /* Populate the LUT with max no. of queues in round robin fashion */
6451 for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
6452
6453 /* The assumption is that lan qp count will be the highest
6454 * qp count for any PF VSI that needs RSS.
6455 * If multiple VSIs need RSS support, all the qp counts
6456 * for those VSIs should be a power of 2 for RSS to work.
6457 * If LAN VSI is the only consumer for RSS then this requirement
6458 * is not necessary.
6459 */
6460 if (j == pf->rss_size)
6461 j = 0;
6462 /* lut = 4-byte sliding window of 4 lut entries */
6463 lut = (lut << 8) | (j &
6464 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
6465 /* On i = 3, we have 4 entries in lut; write to the register */
6466 if ((i & 3) == 3)
6467 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
6468 }
6469 i40e_flush(hw);
6470
6471 return 0;
6472}
6473
f8ff1464
ASJ		 6474/**
6475 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
6476 * @pf: board private structure
6477 * @queue_count: the requested queue count for rss.
6478 *
6479 * returns 0 if rss is not enabled, if enabled returns the final rss queue
6480 * count which may be different from the requested queue count.
6481 **/
6482int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
6483{
6484 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
6485 return 0;
6486
6487 queue_count = min_t(int, queue_count, pf->rss_size_max);
6488 queue_count = rounddown_pow_of_two(queue_count);
6489
6490 if (queue_count != pf->rss_size) {
f8ff1464
ASJ		 6491 i40e_prep_for_reset(pf);
6492
f8ff1464
ASJ		 6493 pf->rss_size = queue_count;
6494
6495 i40e_reset_and_rebuild(pf, true);
6496 i40e_config_rss(pf);
6497 }
6498 dev_info(&pf->pdev->dev, "RSS count: %d\n", pf->rss_size);
6499 return pf->rss_size;
6500}
6501
41c445ff
JB		 6502/**
6503 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
6504 * @pf: board private structure to initialize
6505 *
6506 * i40e_sw_init initializes the Adapter private data structure.
6507 * Fields are initialized based on PCI device information and
6508 * OS network device settings (MTU size).
6509 **/
6510static int i40e_sw_init(struct i40e_pf *pf)
6511{
6512 int err = 0;
6513 int size;
6514
6515 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
6516 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 6517 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 6518 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
6519 if (I40E_DEBUG_USER & debug)
6520 pf->hw.debug_mask = debug;
6521 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
6522 I40E_DEFAULT_MSG_ENABLE);
6523 }
6524
6525 /* Set default capability flags */
6526 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
6527 I40E_FLAG_MSI_ENABLED |
6528 I40E_FLAG_MSIX_ENABLED |
41c445ff
JB		 6529 I40E_FLAG_RX_1BUF_ENABLED;
6530
ca99eb99
MW		 6531 /* Set default ITR */
6532 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
6533 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
6534
7134f9ce
JB		 6535 /* Depending on PF configurations, it is possible that the RSS
6536 * maximum might end up larger than the available queues
6537 */
41c445ff 6538 pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
7134f9ce
JB		 6539 pf->rss_size_max = min_t(int, pf->rss_size_max,
6540 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 6541 if (pf->hw.func_caps.rss) {
6542 pf->flags |= I40E_FLAG_RSS_ENABLED;
bf051a3b 6543 pf->rss_size = min_t(int, pf->rss_size_max, num_online_cpus());
cbf61325 6544 pf->rss_size = rounddown_pow_of_two(pf->rss_size);
41c445ff
JB		 6545 } else {
6546 pf->rss_size = 1;
6547 }
6548
2050bc65
CS		 6549 /* MFP mode enabled */
6550 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
6551 pf->flags |= I40E_FLAG_MFP_ENABLED;
6552 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
6553 }
6554
cbf61325
ASJ		 6555 /* FW/NVM is not yet fixed in this regard */
6556 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
6557 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
6558 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6559 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
cbf61325 6560 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) {
60ea5f83 6561 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 6562 } else {
6563 dev_info(&pf->pdev->dev,
0b67584f 6564 "Flow Director Sideband mode Disabled in MFP mode\n");
41c445ff 6565 }
cbf61325
ASJ		 6566 pf->fdir_pf_filter_count =
6567 pf->hw.func_caps.fd_filters_guaranteed;
6568 pf->hw.fdir_shared_filter_count =
6569 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 6570 }
6571
6572 if (pf->hw.func_caps.vmdq) {
6573 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
6574 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
6575 pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
6576 }
6577
41c445ff
JB		 6578#ifdef CONFIG_PCI_IOV
6579 if (pf->hw.func_caps.num_vfs) {
6580 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
6581 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
6582 pf->num_req_vfs = min_t(int,
6583 pf->hw.func_caps.num_vfs,
6584 I40E_MAX_VF_COUNT);
6585 }
6586#endif /* CONFIG_PCI_IOV */
6587 pf->eeprom_version = 0xDEAD;
6588 pf->lan_veb = I40E_NO_VEB;
6589 pf->lan_vsi = I40E_NO_VSI;
6590
6591 /* set up queue assignment tracking */
6592 size = sizeof(struct i40e_lump_tracking)
6593 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
6594 pf->qp_pile = kzalloc(size, GFP_KERNEL);
6595 if (!pf->qp_pile) {
6596 err = -ENOMEM;
6597 goto sw_init_done;
6598 }
6599 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
6600 pf->qp_pile->search_hint = 0;
6601
6602 /* set up vector assignment tracking */
6603 size = sizeof(struct i40e_lump_tracking)
6604 + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
6605 pf->irq_pile = kzalloc(size, GFP_KERNEL);
6606 if (!pf->irq_pile) {
6607 kfree(pf->qp_pile);
6608 err = -ENOMEM;
6609 goto sw_init_done;
6610 }
6611 pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
6612 pf->irq_pile->search_hint = 0;
6613
6614 mutex_init(&pf->switch_mutex);
6615
6616sw_init_done:
6617 return err;
6618}
6619
7c3c288b
ASJ		 6620/**
6621 * i40e_set_ntuple - set the ntuple feature flag and take action
6622 * @pf: board private structure to initialize
6623 * @features: the feature set that the stack is suggesting
6624 *
6625 * returns a bool to indicate if reset needs to happen
6626 **/
6627bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
6628{
6629 bool need_reset = false;
6630
6631 /* Check if Flow Director n-tuple support was enabled or disabled. If
6632 * the state changed, we need to reset.
6633 */
6634 if (features & NETIF_F_NTUPLE) {
6635 /* Enable filters and mark for reset */
6636 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
6637 need_reset = true;
6638 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
6639 } else {
6640 /* turn off filters, mark for reset and clear SW filter list */
6641 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
6642 need_reset = true;
6643 i40e_fdir_filter_exit(pf);
6644 }
6645 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6646 /* if ATR was disabled it can be re-enabled. */
6647 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
6648 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
6649 }
6650 return need_reset;
6651}
6652
41c445ff
JB		 6653/**
6654 * i40e_set_features - set the netdev feature flags
6655 * @netdev: ptr to the netdev being adjusted
6656 * @features: the feature set that the stack is suggesting
6657 **/
6658static int i40e_set_features(struct net_device *netdev,
6659 netdev_features_t features)
6660{
6661 struct i40e_netdev_priv *np = netdev_priv(netdev);
6662 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 6663 struct i40e_pf *pf = vsi->back;
6664 bool need_reset;
41c445ff
JB		 6665
6666 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6667 i40e_vlan_stripping_enable(vsi);
6668 else
6669 i40e_vlan_stripping_disable(vsi);
6670
7c3c288b
ASJ		 6671 need_reset = i40e_set_ntuple(pf, features);
6672
6673 if (need_reset)
6674 i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
6675
41c445ff
JB		 6676 return 0;
6677}
6678
a1c9a9d9
JK		 6679#ifdef CONFIG_I40E_VXLAN
6680/**
6681 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
6682 * @pf: board private structure
6683 * @port: The UDP port to look up
6684 *
6685 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
6686 **/
6687static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
6688{
6689 u8 i;
6690
6691 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6692 if (pf->vxlan_ports[i] == port)
6693 return i;
6694 }
6695
6696 return i;
6697}
6698
6699/**
6700 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
6701 * @netdev: This physical port's netdev
6702 * @sa_family: Socket Family that VXLAN is notifying us about
6703 * @port: New UDP port number that VXLAN started listening to
6704 **/
6705static void i40e_add_vxlan_port(struct net_device *netdev,
6706 sa_family_t sa_family, __be16 port)
6707{
6708 struct i40e_netdev_priv *np = netdev_priv(netdev);
6709 struct i40e_vsi *vsi = np->vsi;
6710 struct i40e_pf *pf = vsi->back;
6711 u8 next_idx;
6712 u8 idx;
6713
6714 if (sa_family == AF_INET6)
6715 return;
6716
6717 idx = i40e_get_vxlan_port_idx(pf, port);
6718
6719 /* Check if port already exists */
6720 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6721 netdev_info(netdev, "Port %d already offloaded\n", ntohs(port));
6722 return;
6723 }
6724
6725 /* Now check if there is space to add the new port */
6726 next_idx = i40e_get_vxlan_port_idx(pf, 0);
6727
6728 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6729 netdev_info(netdev, "Maximum number of UDP ports reached, not adding port %d\n",
6730 ntohs(port));
6731 return;
6732 }
6733
6734 /* New port: add it and mark its index in the bitmap */
6735 pf->vxlan_ports[next_idx] = port;
6736 pf->pending_vxlan_bitmap |= (1 << next_idx);
6737
6738 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6739}
6740
6741/**
6742 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
6743 * @netdev: This physical port's netdev
6744 * @sa_family: Socket Family that VXLAN is notifying us about
6745 * @port: UDP port number that VXLAN stopped listening to
6746 **/
6747static void i40e_del_vxlan_port(struct net_device *netdev,
6748 sa_family_t sa_family, __be16 port)
6749{
6750 struct i40e_netdev_priv *np = netdev_priv(netdev);
6751 struct i40e_vsi *vsi = np->vsi;
6752 struct i40e_pf *pf = vsi->back;
6753 u8 idx;
6754
6755 if (sa_family == AF_INET6)
6756 return;
6757
6758 idx = i40e_get_vxlan_port_idx(pf, port);
6759
6760 /* Check if port already exists */
6761 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
6762 /* if port exists, set it to 0 (mark for deletion)
6763 * and make it pending
6764 */
6765 pf->vxlan_ports[idx] = 0;
6766
6767 pf->pending_vxlan_bitmap |= (1 << idx);
6768
6769 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
6770 } else {
6771 netdev_warn(netdev, "Port %d was not found, not deleting\n",
6772 ntohs(port));
6773 }
6774}
6775
6776#endif
4ba0dea5
GR		 6777#ifdef HAVE_FDB_OPS
6778#ifdef USE_CONST_DEV_UC_CHAR
6779static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6780 struct net_device *dev,
6781 const unsigned char *addr,
6782 u16 flags)
6783#else
6784static int i40e_ndo_fdb_add(struct ndmsg *ndm,
6785 struct net_device *dev,
6786 unsigned char *addr,
6787 u16 flags)
6788#endif
6789{
6790 struct i40e_netdev_priv *np = netdev_priv(dev);
6791 struct i40e_pf *pf = np->vsi->back;
6792 int err = 0;
6793
6794 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
6795 return -EOPNOTSUPP;
6796
6797 /* Hardware does not support aging addresses so if a
6798 * ndm_state is given only allow permanent addresses
6799 */
6800 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
6801 netdev_info(dev, "FDB only supports static addresses\n");
6802 return -EINVAL;
6803 }
6804
6805 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
6806 err = dev_uc_add_excl(dev, addr);
6807 else if (is_multicast_ether_addr(addr))
6808 err = dev_mc_add_excl(dev, addr);
6809 else
6810 err = -EINVAL;
6811
6812 /* Only return duplicate errors if NLM_F_EXCL is set */
6813 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6814 err = 0;
6815
6816 return err;
6817}
6818
6819#ifndef USE_DEFAULT_FDB_DEL_DUMP
6820#ifdef USE_CONST_DEV_UC_CHAR
6821static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6822 struct net_device *dev,
6823 const unsigned char *addr)
6824#else
6825static int i40e_ndo_fdb_del(struct ndmsg *ndm,
6826 struct net_device *dev,
6827 unsigned char *addr)
6828#endif
6829{
6830 struct i40e_netdev_priv *np = netdev_priv(dev);
6831 struct i40e_pf *pf = np->vsi->back;
6832 int err = -EOPNOTSUPP;
6833
6834 if (ndm->ndm_state & NUD_PERMANENT) {
6835 netdev_info(dev, "FDB only supports static addresses\n");
6836 return -EINVAL;
6837 }
6838
6839 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
6840 if (is_unicast_ether_addr(addr))
6841 err = dev_uc_del(dev, addr);
6842 else if (is_multicast_ether_addr(addr))
6843 err = dev_mc_del(dev, addr);
6844 else
6845 err = -EINVAL;
6846 }
6847
6848 return err;
6849}
6850
6851static int i40e_ndo_fdb_dump(struct sk_buff *skb,
6852 struct netlink_callback *cb,
6853 struct net_device *dev,
6854 int idx)
6855{
6856 struct i40e_netdev_priv *np = netdev_priv(dev);
6857 struct i40e_pf *pf = np->vsi->back;
6858
6859 if (pf->flags & I40E_FLAG_SRIOV_ENABLED)
6860 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6861
6862 return idx;
6863}
6864
6865#endif /* USE_DEFAULT_FDB_DEL_DUMP */
6866#endif /* HAVE_FDB_OPS */
41c445ff
JB		 6867static const struct net_device_ops i40e_netdev_ops = {
6868 .ndo_open = i40e_open,
6869 .ndo_stop = i40e_close,
6870 .ndo_start_xmit = i40e_lan_xmit_frame,
6871 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
6872 .ndo_set_rx_mode = i40e_set_rx_mode,
6873 .ndo_validate_addr = eth_validate_addr,
6874 .ndo_set_mac_address = i40e_set_mac,
6875 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 6876 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 6877 .ndo_tx_timeout = i40e_tx_timeout,
6878 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
6879 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
6880#ifdef CONFIG_NET_POLL_CONTROLLER
6881 .ndo_poll_controller = i40e_netpoll,
6882#endif
6883 .ndo_setup_tc = i40e_setup_tc,
6884 .ndo_set_features = i40e_set_features,
6885 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
6886 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 6887 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 6888 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 6889 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
a1c9a9d9
JK		 6890#ifdef CONFIG_I40E_VXLAN
6891 .ndo_add_vxlan_port = i40e_add_vxlan_port,
6892 .ndo_del_vxlan_port = i40e_del_vxlan_port,
6893#endif
4ba0dea5
GR		 6894#ifdef HAVE_FDB_OPS
6895 .ndo_fdb_add = i40e_ndo_fdb_add,
6896#ifndef USE_DEFAULT_FDB_DEL_DUMP
6897 .ndo_fdb_del = i40e_ndo_fdb_del,
6898 .ndo_fdb_dump = i40e_ndo_fdb_dump,
6899#endif
6900#endif
41c445ff
JB		 6901};
6902
6903/**
6904 * i40e_config_netdev - Setup the netdev flags
6905 * @vsi: the VSI being configured
6906 *
6907 * Returns 0 on success, negative value on failure
6908 **/
6909static int i40e_config_netdev(struct i40e_vsi *vsi)
6910{
1a10370a 6911 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 6912 struct i40e_pf *pf = vsi->back;
6913 struct i40e_hw *hw = &pf->hw;
6914 struct i40e_netdev_priv *np;
6915 struct net_device *netdev;
6916 u8 mac_addr[ETH_ALEN];
6917 int etherdev_size;
6918
6919 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 6920 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 6921 if (!netdev)
6922 return -ENOMEM;
6923
6924 vsi->netdev = netdev;
6925 np = netdev_priv(netdev);
6926 np->vsi = vsi;
6927
d70e941b 6928 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 6929 NETIF_F_GSO_UDP_TUNNEL |
d70e941b 6930 NETIF_F_TSO;
41c445ff
JB		 6931
6932 netdev->features = NETIF_F_SG |
6933 NETIF_F_IP_CSUM |
6934 NETIF_F_SCTP_CSUM |
6935 NETIF_F_HIGHDMA |
6936 NETIF_F_GSO_UDP_TUNNEL |
6937 NETIF_F_HW_VLAN_CTAG_TX |
6938 NETIF_F_HW_VLAN_CTAG_RX |
6939 NETIF_F_HW_VLAN_CTAG_FILTER |
6940 NETIF_F_IPV6_CSUM |
6941 NETIF_F_TSO |
059dab69 6942 NETIF_F_TSO_ECN |
41c445ff
JB		 6943 NETIF_F_TSO6 |
6944 NETIF_F_RXCSUM |
6945 NETIF_F_RXHASH |
6946 0;
6947
2e86a0b6
ASJ		 6948 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
6949 netdev->features |= NETIF_F_NTUPLE;
6950
41c445ff
JB		 6951 /* copy netdev features into list of user selectable features */
6952 netdev->hw_features |= netdev->features;
6953
6954 if (vsi->type == I40E_VSI_MAIN) {
6955 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
6956 memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
6957 } else {
6958 /* relate the VSI_VMDQ name to the VSI_MAIN name */
6959 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
6960 pf->vsi[pf->lan_vsi]->netdev->name);
6961 random_ether_addr(mac_addr);
6962 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
6963 }
1a10370a 6964 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
41c445ff
JB		 6965
6966 memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
6967 memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
6968 /* vlan gets same features (except vlan offload)
6969 * after any tweaks for specific VSI types
6970 */
6971 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
6972 NETIF_F_HW_VLAN_CTAG_RX |
6973 NETIF_F_HW_VLAN_CTAG_FILTER);
6974 netdev->priv_flags |= IFF_UNICAST_FLT;
6975 netdev->priv_flags |= IFF_SUPP_NOFCS;
6976 /* Setup netdev TC information */
6977 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
6978
6979 netdev->netdev_ops = &i40e_netdev_ops;
6980 netdev->watchdog_timeo = 5 * HZ;
6981 i40e_set_ethtool_ops(netdev);
6982
6983 return 0;
6984}
6985
6986/**
6987 * i40e_vsi_delete - Delete a VSI from the switch
6988 * @vsi: the VSI being removed
6989 *
6990 * Returns 0 on success, negative value on failure
6991 **/
6992static void i40e_vsi_delete(struct i40e_vsi *vsi)
6993{
6994 /* remove default VSI is not allowed */
6995 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
6996 return;
6997
41c445ff 6998 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 6999}
7000
7001/**
7002 * i40e_add_vsi - Add a VSI to the switch
7003 * @vsi: the VSI being configured
7004 *
7005 * This initializes a VSI context depending on the VSI type to be added and
7006 * passes it down to the add_vsi aq command.
7007 **/
7008static int i40e_add_vsi(struct i40e_vsi *vsi)
7009{
7010 int ret = -ENODEV;
7011 struct i40e_mac_filter *f, *ftmp;
7012 struct i40e_pf *pf = vsi->back;
7013 struct i40e_hw *hw = &pf->hw;
7014 struct i40e_vsi_context ctxt;
7015 u8 enabled_tc = 0x1; /* TC0 enabled */
7016 int f_count = 0;
7017
7018 memset(&ctxt, 0, sizeof(ctxt));
7019 switch (vsi->type) {
7020 case I40E_VSI_MAIN:
7021 /* The PF's main VSI is already setup as part of the
7022 * device initialization, so we'll not bother with
7023 * the add_vsi call, but we will retrieve the current
7024 * VSI context.
7025 */
7026 ctxt.seid = pf->main_vsi_seid;
7027 ctxt.pf_num = pf->hw.pf_id;
7028 ctxt.vf_num = 0;
7029 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
7030 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
7031 if (ret) {
7032 dev_info(&pf->pdev->dev,
7033 "couldn't get pf vsi config, err %d, aq_err %d\n",
7034 ret, pf->hw.aq.asq_last_status);
7035 return -ENOENT;
7036 }
7037 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7038 vsi->info.valid_sections = 0;
7039
7040 vsi->seid = ctxt.seid;
7041 vsi->id = ctxt.vsi_number;
7042
7043 enabled_tc = i40e_pf_get_tc_map(pf);
7044
7045 /* MFP mode setup queue map and update VSI */
7046 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
7047 memset(&ctxt, 0, sizeof(ctxt));
7048 ctxt.seid = pf->main_vsi_seid;
7049 ctxt.pf_num = pf->hw.pf_id;
7050 ctxt.vf_num = 0;
7051 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
7052 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7053 if (ret) {
7054 dev_info(&pf->pdev->dev,
7055 "update vsi failed, aq_err=%d\n",
7056 pf->hw.aq.asq_last_status);
7057 ret = -ENOENT;
7058 goto err;
7059 }
7060 /* update the local VSI info queue map */
7061 i40e_vsi_update_queue_map(vsi, &ctxt);
7062 vsi->info.valid_sections = 0;
7063 } else {
7064 /* Default/Main VSI is only enabled for TC0
7065 * reconfigure it to enable all TCs that are
7066 * available on the port in SFP mode.
7067 */
7068 ret = i40e_vsi_config_tc(vsi, enabled_tc);
7069 if (ret) {
7070 dev_info(&pf->pdev->dev,
7071 "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
7072 enabled_tc, ret,
7073 pf->hw.aq.asq_last_status);
7074 ret = -ENOENT;
7075 }
7076 }
7077 break;
7078
7079 case I40E_VSI_FDIR:
cbf61325
ASJ		 7080 ctxt.pf_num = hw->pf_id;
7081 ctxt.vf_num = 0;
7082 ctxt.uplink_seid = vsi->uplink_seid;
7083 ctxt.connection_type = 0x1; /* regular data port */
7084 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
41c445ff 7085 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 7086 break;
7087
7088 case I40E_VSI_VMDQ2:
7089 ctxt.pf_num = hw->pf_id;
7090 ctxt.vf_num = 0;
7091 ctxt.uplink_seid = vsi->uplink_seid;
7092 ctxt.connection_type = 0x1; /* regular data port */
7093 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
7094
7095 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7096
7097 /* This VSI is connected to VEB so the switch_id
7098 * should be set to zero by default.
7099 */
7100 ctxt.info.switch_id = 0;
7101 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
7102 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7103
7104 /* Setup the VSI tx/rx queue map for TC0 only for now */
7105 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7106 break;
7107
7108 case I40E_VSI_SRIOV:
7109 ctxt.pf_num = hw->pf_id;
7110 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
7111 ctxt.uplink_seid = vsi->uplink_seid;
7112 ctxt.connection_type = 0x1; /* regular data port */
7113 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
7114
7115 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
7116
7117 /* This VSI is connected to VEB so the switch_id
7118 * should be set to zero by default.
7119 */
7120 ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
7121
7122 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
7123 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
7124 /* Setup the VSI tx/rx queue map for TC0 only for now */
7125 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
7126 break;
7127
7128 default:
7129 return -ENODEV;
7130 }
7131
7132 if (vsi->type != I40E_VSI_MAIN) {
7133 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
7134 if (ret) {
7135 dev_info(&vsi->back->pdev->dev,
7136 "add vsi failed, aq_err=%d\n",
7137 vsi->back->hw.aq.asq_last_status);
7138 ret = -ENOENT;
7139 goto err;
7140 }
7141 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
7142 vsi->info.valid_sections = 0;
7143 vsi->seid = ctxt.seid;
7144 vsi->id = ctxt.vsi_number;
7145 }
7146
7147 /* If macvlan filters already exist, force them to get loaded */
7148 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
7149 f->changed = true;
7150 f_count++;
7151 }
7152 if (f_count) {
7153 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
7154 pf->flags |= I40E_FLAG_FILTER_SYNC;
7155 }
7156
7157 /* Update VSI BW information */
7158 ret = i40e_vsi_get_bw_info(vsi);
7159 if (ret) {
7160 dev_info(&pf->pdev->dev,
7161 "couldn't get vsi bw info, err %d, aq_err %d\n",
7162 ret, pf->hw.aq.asq_last_status);
7163 /* VSI is already added so not tearing that up */
7164 ret = 0;
7165 }
7166
7167err:
7168 return ret;
7169}
7170
7171/**
7172 * i40e_vsi_release - Delete a VSI and free its resources
7173 * @vsi: the VSI being removed
7174 *
7175 * Returns 0 on success or < 0 on error
7176 **/
7177int i40e_vsi_release(struct i40e_vsi *vsi)
7178{
7179 struct i40e_mac_filter *f, *ftmp;
7180 struct i40e_veb *veb = NULL;
7181 struct i40e_pf *pf;
7182 u16 uplink_seid;
7183 int i, n;
7184
7185 pf = vsi->back;
7186
7187 /* release of a VEB-owner or last VSI is not allowed */
7188 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
7189 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
7190 vsi->seid, vsi->uplink_seid);
7191 return -ENODEV;
7192 }
7193 if (vsi == pf->vsi[pf->lan_vsi] &&
7194 !test_bit(__I40E_DOWN, &pf->state)) {
7195 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
7196 return -ENODEV;
7197 }
7198
7199 uplink_seid = vsi->uplink_seid;
7200 if (vsi->type != I40E_VSI_SRIOV) {
7201 if (vsi->netdev_registered) {
7202 vsi->netdev_registered = false;
7203 if (vsi->netdev) {
7204 /* results in a call to i40e_close() */
7205 unregister_netdev(vsi->netdev);
41c445ff
JB		 7206 }
7207 } else {
90ef8d47 7208 i40e_vsi_close(vsi);
41c445ff
JB		 7209 }
7210 i40e_vsi_disable_irq(vsi);
7211 }
7212
7213 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
7214 i40e_del_filter(vsi, f->macaddr, f->vlan,
7215 f->is_vf, f->is_netdev);
7216 i40e_sync_vsi_filters(vsi);
7217
7218 i40e_vsi_delete(vsi);
7219 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 7220 if (vsi->netdev) {
7221 free_netdev(vsi->netdev);
7222 vsi->netdev = NULL;
7223 }
41c445ff
JB		 7224 i40e_vsi_clear_rings(vsi);
7225 i40e_vsi_clear(vsi);
7226
7227 /* If this was the last thing on the VEB, except for the
7228 * controlling VSI, remove the VEB, which puts the controlling
7229 * VSI onto the next level down in the switch.
7230 *
7231 * Well, okay, there's one more exception here: don't remove
7232 * the orphan VEBs yet. We'll wait for an explicit remove request
7233 * from up the network stack.
7234 */
505682cd 7235 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7236 if (pf->vsi[i] &&
7237 pf->vsi[i]->uplink_seid == uplink_seid &&
7238 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7239 n++; /* count the VSIs */
7240 }
7241 }
7242 for (i = 0; i < I40E_MAX_VEB; i++) {
7243 if (!pf->veb[i])
7244 continue;
7245 if (pf->veb[i]->uplink_seid == uplink_seid)
7246 n++; /* count the VEBs */
7247 if (pf->veb[i]->seid == uplink_seid)
7248 veb = pf->veb[i];
7249 }
7250 if (n == 0 && veb && veb->uplink_seid != 0)
7251 i40e_veb_release(veb);
7252
7253 return 0;
7254}
7255
7256/**
7257 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
7258 * @vsi: ptr to the VSI
7259 *
7260 * This should only be called after i40e_vsi_mem_alloc() which allocates the
7261 * corresponding SW VSI structure and initializes num_queue_pairs for the
7262 * newly allocated VSI.
7263 *
7264 * Returns 0 on success or negative on failure
7265 **/
7266static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
7267{
7268 int ret = -ENOENT;
7269 struct i40e_pf *pf = vsi->back;
7270
493fb300 7271 if (vsi->q_vectors[0]) {
41c445ff
JB		 7272 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
7273 vsi->seid);
7274 return -EEXIST;
7275 }
7276
7277 if (vsi->base_vector) {
f29eaa3d 7278 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 7279 vsi->seid, vsi->base_vector);
7280 return -EEXIST;
7281 }
7282
90e04070 7283 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 7284 if (ret) {
7285 dev_info(&pf->pdev->dev,
7286 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
7287 vsi->num_q_vectors, vsi->seid, ret);
7288 vsi->num_q_vectors = 0;
7289 goto vector_setup_out;
7290 }
7291
958a3e3b
SN		 7292 if (vsi->num_q_vectors)
7293 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
7294 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 7295 if (vsi->base_vector < 0) {
7296 dev_info(&pf->pdev->dev,
f29eaa3d 7297 "failed to get queue tracking for VSI %d, err=%d\n",
41c445ff
JB		 7298 vsi->seid, vsi->base_vector);
7299 i40e_vsi_free_q_vectors(vsi);
7300 ret = -ENOENT;
7301 goto vector_setup_out;
7302 }
7303
7304vector_setup_out:
7305 return ret;
7306}
7307
bc7d338f
ASJ		 7308/**
7309 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
7310 * @vsi: pointer to the vsi.
7311 *
7312 * This re-allocates a vsi's queue resources.
7313 *
7314 * Returns pointer to the successfully allocated and configured VSI sw struct
7315 * on success, otherwise returns NULL on failure.
7316 **/
7317static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
7318{
7319 struct i40e_pf *pf = vsi->back;
7320 u8 enabled_tc;
7321 int ret;
7322
7323 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7324 i40e_vsi_clear_rings(vsi);
7325
7326 i40e_vsi_free_arrays(vsi, false);
7327 i40e_set_num_rings_in_vsi(vsi);
7328 ret = i40e_vsi_alloc_arrays(vsi, false);
7329 if (ret)
7330 goto err_vsi;
7331
7332 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
7333 if (ret < 0) {
7334 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7335 vsi->seid, ret);
7336 goto err_vsi;
7337 }
7338 vsi->base_queue = ret;
7339
7340 /* Update the FW view of the VSI. Force a reset of TC and queue
7341 * layout configurations.
7342 */
7343 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
7344 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
7345 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
7346 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
7347
7348 /* assign it some queues */
7349 ret = i40e_alloc_rings(vsi);
7350 if (ret)
7351 goto err_rings;
7352
7353 /* map all of the rings to the q_vectors */
7354 i40e_vsi_map_rings_to_vectors(vsi);
7355 return vsi;
7356
7357err_rings:
7358 i40e_vsi_free_q_vectors(vsi);
7359 if (vsi->netdev_registered) {
7360 vsi->netdev_registered = false;
7361 unregister_netdev(vsi->netdev);
7362 free_netdev(vsi->netdev);
7363 vsi->netdev = NULL;
7364 }
7365 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7366err_vsi:
7367 i40e_vsi_clear(vsi);
7368 return NULL;
7369}
7370
41c445ff
JB		 7371/**
7372 * i40e_vsi_setup - Set up a VSI by a given type
7373 * @pf: board private structure
7374 * @type: VSI type
7375 * @uplink_seid: the switch element to link to
7376 * @param1: usage depends upon VSI type. For VF types, indicates VF id
7377 *
7378 * This allocates the sw VSI structure and its queue resources, then add a VSI
7379 * to the identified VEB.
7380 *
7381 * Returns pointer to the successfully allocated and configure VSI sw struct on
7382 * success, otherwise returns NULL on failure.
7383 **/
7384struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
7385 u16 uplink_seid, u32 param1)
7386{
7387 struct i40e_vsi *vsi = NULL;
7388 struct i40e_veb *veb = NULL;
7389 int ret, i;
7390 int v_idx;
7391
7392 /* The requested uplink_seid must be either
7393 * - the PF's port seid
7394 * no VEB is needed because this is the PF
7395 * or this is a Flow Director special case VSI
7396 * - seid of an existing VEB
7397 * - seid of a VSI that owns an existing VEB
7398 * - seid of a VSI that doesn't own a VEB
7399 * a new VEB is created and the VSI becomes the owner
7400 * - seid of the PF VSI, which is what creates the first VEB
7401 * this is a special case of the previous
7402 *
7403 * Find which uplink_seid we were given and create a new VEB if needed
7404 */
7405 for (i = 0; i < I40E_MAX_VEB; i++) {
7406 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
7407 veb = pf->veb[i];
7408 break;
7409 }
7410 }
7411
7412 if (!veb && uplink_seid != pf->mac_seid) {
7413
505682cd 7414 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7415 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
7416 vsi = pf->vsi[i];
7417 break;
7418 }
7419 }
7420 if (!vsi) {
7421 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
7422 uplink_seid);
7423 return NULL;
7424 }
7425
7426 if (vsi->uplink_seid == pf->mac_seid)
7427 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
7428 vsi->tc_config.enabled_tc);
7429 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
7430 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
7431 vsi->tc_config.enabled_tc);
7432
7433 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
7434 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
7435 veb = pf->veb[i];
7436 }
7437 if (!veb) {
7438 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
7439 return NULL;
7440 }
7441
7442 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7443 uplink_seid = veb->seid;
7444 }
7445
7446 /* get vsi sw struct */
7447 v_idx = i40e_vsi_mem_alloc(pf, type);
7448 if (v_idx < 0)
7449 goto err_alloc;
7450 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 7451 if (!vsi)
7452 goto err_alloc;
41c445ff
JB		 7453 vsi->type = type;
7454 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
7455
7456 if (type == I40E_VSI_MAIN)
7457 pf->lan_vsi = v_idx;
7458 else if (type == I40E_VSI_SRIOV)
7459 vsi->vf_id = param1;
7460 /* assign it some queues */
cbf61325
ASJ		 7461 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
7462 vsi->idx);
41c445ff
JB		 7463 if (ret < 0) {
7464 dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
7465 vsi->seid, ret);
7466 goto err_vsi;
7467 }
7468 vsi->base_queue = ret;
7469
7470 /* get a VSI from the hardware */
7471 vsi->uplink_seid = uplink_seid;
7472 ret = i40e_add_vsi(vsi);
7473 if (ret)
7474 goto err_vsi;
7475
7476 switch (vsi->type) {
7477 /* setup the netdev if needed */
7478 case I40E_VSI_MAIN:
7479 case I40E_VSI_VMDQ2:
7480 ret = i40e_config_netdev(vsi);
7481 if (ret)
7482 goto err_netdev;
7483 ret = register_netdev(vsi->netdev);
7484 if (ret)
7485 goto err_netdev;
7486 vsi->netdev_registered = true;
7487 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 7488#ifdef CONFIG_I40E_DCB
7489 /* Setup DCB netlink interface */
7490 i40e_dcbnl_setup(vsi);
7491#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 7492 /* fall through */
7493
7494 case I40E_VSI_FDIR:
7495 /* set up vectors and rings if needed */
7496 ret = i40e_vsi_setup_vectors(vsi);
7497 if (ret)
7498 goto err_msix;
7499
7500 ret = i40e_alloc_rings(vsi);
7501 if (ret)
7502 goto err_rings;
7503
7504 /* map all of the rings to the q_vectors */
7505 i40e_vsi_map_rings_to_vectors(vsi);
7506
7507 i40e_vsi_reset_stats(vsi);
7508 break;
7509
7510 default:
7511 /* no netdev or rings for the other VSI types */
7512 break;
7513 }
7514
7515 return vsi;
7516
7517err_rings:
7518 i40e_vsi_free_q_vectors(vsi);
7519err_msix:
7520 if (vsi->netdev_registered) {
7521 vsi->netdev_registered = false;
7522 unregister_netdev(vsi->netdev);
7523 free_netdev(vsi->netdev);
7524 vsi->netdev = NULL;
7525 }
7526err_netdev:
7527 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
7528err_vsi:
7529 i40e_vsi_clear(vsi);
7530err_alloc:
7531 return NULL;
7532}
7533
7534/**
7535 * i40e_veb_get_bw_info - Query VEB BW information
7536 * @veb: the veb to query
7537 *
7538 * Query the Tx scheduler BW configuration data for given VEB
7539 **/
7540static int i40e_veb_get_bw_info(struct i40e_veb *veb)
7541{
7542 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
7543 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
7544 struct i40e_pf *pf = veb->pf;
7545 struct i40e_hw *hw = &pf->hw;
7546 u32 tc_bw_max;
7547 int ret = 0;
7548 int i;
7549
7550 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
7551 &bw_data, NULL);
7552 if (ret) {
7553 dev_info(&pf->pdev->dev,
7554 "query veb bw config failed, aq_err=%d\n",
7555 hw->aq.asq_last_status);
7556 goto out;
7557 }
7558
7559 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
7560 &ets_data, NULL);
7561 if (ret) {
7562 dev_info(&pf->pdev->dev,
7563 "query veb bw ets config failed, aq_err=%d\n",
7564 hw->aq.asq_last_status);
7565 goto out;
7566 }
7567
7568 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
7569 veb->bw_max_quanta = ets_data.tc_bw_max;
7570 veb->is_abs_credits = bw_data.absolute_credits_enable;
7571 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
7572 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
7573 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7574 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
7575 veb->bw_tc_limit_credits[i] =
7576 le16_to_cpu(bw_data.tc_bw_limits[i]);
7577 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
7578 }
7579
7580out:
7581 return ret;
7582}
7583
7584/**
7585 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
7586 * @pf: board private structure
7587 *
7588 * On error: returns error code (negative)
7589 * On success: returns vsi index in PF (positive)
7590 **/
7591static int i40e_veb_mem_alloc(struct i40e_pf *pf)
7592{
7593 int ret = -ENOENT;
7594 struct i40e_veb *veb;
7595 int i;
7596
7597 /* Need to protect the allocation of switch elements at the PF level */
7598 mutex_lock(&pf->switch_mutex);
7599
7600 /* VEB list may be fragmented if VEB creation/destruction has
7601 * been happening. We can afford to do a quick scan to look
7602 * for any free slots in the list.
7603 *
7604 * find next empty veb slot, looping back around if necessary
7605 */
7606 i = 0;
7607 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
7608 i++;
7609 if (i >= I40E_MAX_VEB) {
7610 ret = -ENOMEM;
7611 goto err_alloc_veb; /* out of VEB slots! */
7612 }
7613
7614 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
7615 if (!veb) {
7616 ret = -ENOMEM;
7617 goto err_alloc_veb;
7618 }
7619 veb->pf = pf;
7620 veb->idx = i;
7621 veb->enabled_tc = 1;
7622
7623 pf->veb[i] = veb;
7624 ret = i;
7625err_alloc_veb:
7626 mutex_unlock(&pf->switch_mutex);
7627 return ret;
7628}
7629
7630/**
7631 * i40e_switch_branch_release - Delete a branch of the switch tree
7632 * @branch: where to start deleting
7633 *
7634 * This uses recursion to find the tips of the branch to be
7635 * removed, deleting until we get back to and can delete this VEB.
7636 **/
7637static void i40e_switch_branch_release(struct i40e_veb *branch)
7638{
7639 struct i40e_pf *pf = branch->pf;
7640 u16 branch_seid = branch->seid;
7641 u16 veb_idx = branch->idx;
7642 int i;
7643
7644 /* release any VEBs on this VEB - RECURSION */
7645 for (i = 0; i < I40E_MAX_VEB; i++) {
7646 if (!pf->veb[i])
7647 continue;
7648 if (pf->veb[i]->uplink_seid == branch->seid)
7649 i40e_switch_branch_release(pf->veb[i]);
7650 }
7651
7652 /* Release the VSIs on this VEB, but not the owner VSI.
7653 *
7654 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
7655 * the VEB itself, so don't use (*branch) after this loop.
7656 */
505682cd 7657 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7658 if (!pf->vsi[i])
7659 continue;
7660 if (pf->vsi[i]->uplink_seid == branch_seid &&
7661 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
7662 i40e_vsi_release(pf->vsi[i]);
7663 }
7664 }
7665
7666 /* There's one corner case where the VEB might not have been
7667 * removed, so double check it here and remove it if needed.
7668 * This case happens if the veb was created from the debugfs
7669 * commands and no VSIs were added to it.
7670 */
7671 if (pf->veb[veb_idx])
7672 i40e_veb_release(pf->veb[veb_idx]);
7673}
7674
7675/**
7676 * i40e_veb_clear - remove veb struct
7677 * @veb: the veb to remove
7678 **/
7679static void i40e_veb_clear(struct i40e_veb *veb)
7680{
7681 if (!veb)
7682 return;
7683
7684 if (veb->pf) {
7685 struct i40e_pf *pf = veb->pf;
7686
7687 mutex_lock(&pf->switch_mutex);
7688 if (pf->veb[veb->idx] == veb)
7689 pf->veb[veb->idx] = NULL;
7690 mutex_unlock(&pf->switch_mutex);
7691 }
7692
7693 kfree(veb);
7694}
7695
7696/**
7697 * i40e_veb_release - Delete a VEB and free its resources
7698 * @veb: the VEB being removed
7699 **/
7700void i40e_veb_release(struct i40e_veb *veb)
7701{
7702 struct i40e_vsi *vsi = NULL;
7703 struct i40e_pf *pf;
7704 int i, n = 0;
7705
7706 pf = veb->pf;
7707
7708 /* find the remaining VSI and check for extras */
505682cd 7709 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 7710 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
7711 n++;
7712 vsi = pf->vsi[i];
7713 }
7714 }
7715 if (n != 1) {
7716 dev_info(&pf->pdev->dev,
7717 "can't remove VEB %d with %d VSIs left\n",
7718 veb->seid, n);
7719 return;
7720 }
7721
7722 /* move the remaining VSI to uplink veb */
7723 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
7724 if (veb->uplink_seid) {
7725 vsi->uplink_seid = veb->uplink_seid;
7726 if (veb->uplink_seid == pf->mac_seid)
7727 vsi->veb_idx = I40E_NO_VEB;
7728 else
7729 vsi->veb_idx = veb->veb_idx;
7730 } else {
7731 /* floating VEB */
7732 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
7733 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
7734 }
7735
7736 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
7737 i40e_veb_clear(veb);
41c445ff
JB		 7738}
7739
7740/**
7741 * i40e_add_veb - create the VEB in the switch
7742 * @veb: the VEB to be instantiated
7743 * @vsi: the controlling VSI
7744 **/
7745static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
7746{
56747264 7747 bool is_default = false;
e1c51b95 7748 bool is_cloud = false;
41c445ff
JB		 7749 int ret;
7750
7751 /* get a VEB from the hardware */
7752 ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 7753 veb->enabled_tc, is_default,
7754 is_cloud, &veb->seid, NULL);
41c445ff
JB		 7755 if (ret) {
7756 dev_info(&veb->pf->pdev->dev,
7757 "couldn't add VEB, err %d, aq_err %d\n",
7758 ret, veb->pf->hw.aq.asq_last_status);
7759 return -EPERM;
7760 }
7761
7762 /* get statistics counter */
7763 ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
7764 &veb->stats_idx, NULL, NULL, NULL);
7765 if (ret) {
7766 dev_info(&veb->pf->pdev->dev,
7767 "couldn't get VEB statistics idx, err %d, aq_err %d\n",
7768 ret, veb->pf->hw.aq.asq_last_status);
7769 return -EPERM;
7770 }
7771 ret = i40e_veb_get_bw_info(veb);
7772 if (ret) {
7773 dev_info(&veb->pf->pdev->dev,
7774 "couldn't get VEB bw info, err %d, aq_err %d\n",
7775 ret, veb->pf->hw.aq.asq_last_status);
7776 i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
7777 return -ENOENT;
7778 }
7779
7780 vsi->uplink_seid = veb->seid;
7781 vsi->veb_idx = veb->idx;
7782 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
7783
7784 return 0;
7785}
7786
7787/**
7788 * i40e_veb_setup - Set up a VEB
7789 * @pf: board private structure
7790 * @flags: VEB setup flags
7791 * @uplink_seid: the switch element to link to
7792 * @vsi_seid: the initial VSI seid
7793 * @enabled_tc: Enabled TC bit-map
7794 *
7795 * This allocates the sw VEB structure and links it into the switch
7796 * It is possible and legal for this to be a duplicate of an already
7797 * existing VEB. It is also possible for both uplink and vsi seids
7798 * to be zero, in order to create a floating VEB.
7799 *
7800 * Returns pointer to the successfully allocated VEB sw struct on
7801 * success, otherwise returns NULL on failure.
7802 **/
7803struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
7804 u16 uplink_seid, u16 vsi_seid,
7805 u8 enabled_tc)
7806{
7807 struct i40e_veb *veb, *uplink_veb = NULL;
7808 int vsi_idx, veb_idx;
7809 int ret;
7810
7811 /* if one seid is 0, the other must be 0 to create a floating relay */
7812 if ((uplink_seid == 0 || vsi_seid == 0) &&
7813 (uplink_seid + vsi_seid != 0)) {
7814 dev_info(&pf->pdev->dev,
7815 "one, not both seid's are 0: uplink=%d vsi=%d\n",
7816 uplink_seid, vsi_seid);
7817 return NULL;
7818 }
7819
7820 /* make sure there is such a vsi and uplink */
505682cd 7821 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 7822 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
7823 break;
505682cd 7824 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 7825 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
7826 vsi_seid);
7827 return NULL;
7828 }
7829
7830 if (uplink_seid && uplink_seid != pf->mac_seid) {
7831 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
7832 if (pf->veb[veb_idx] &&
7833 pf->veb[veb_idx]->seid == uplink_seid) {
7834 uplink_veb = pf->veb[veb_idx];
7835 break;
7836 }
7837 }
7838 if (!uplink_veb) {
7839 dev_info(&pf->pdev->dev,
7840 "uplink seid %d not found\n", uplink_seid);
7841 return NULL;
7842 }
7843 }
7844
7845 /* get veb sw struct */
7846 veb_idx = i40e_veb_mem_alloc(pf);
7847 if (veb_idx < 0)
7848 goto err_alloc;
7849 veb = pf->veb[veb_idx];
7850 veb->flags = flags;
7851 veb->uplink_seid = uplink_seid;
7852 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
7853 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
7854
7855 /* create the VEB in the switch */
7856 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
7857 if (ret)
7858 goto err_veb;
1bb8b935
SN		 7859 if (vsi_idx == pf->lan_vsi)
7860 pf->lan_veb = veb->idx;
41c445ff
JB		 7861
7862 return veb;
7863
7864err_veb:
7865 i40e_veb_clear(veb);
7866err_alloc:
7867 return NULL;
7868}
7869
7870/**
7871 * i40e_setup_pf_switch_element - set pf vars based on switch type
7872 * @pf: board private structure
7873 * @ele: element we are building info from
7874 * @num_reported: total number of elements
7875 * @printconfig: should we print the contents
7876 *
7877 * helper function to assist in extracting a few useful SEID values.
7878 **/
7879static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
7880 struct i40e_aqc_switch_config_element_resp *ele,
7881 u16 num_reported, bool printconfig)
7882{
7883 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
7884 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
7885 u8 element_type = ele->element_type;
7886 u16 seid = le16_to_cpu(ele->seid);
7887
7888 if (printconfig)
7889 dev_info(&pf->pdev->dev,
7890 "type=%d seid=%d uplink=%d downlink=%d\n",
7891 element_type, seid, uplink_seid, downlink_seid);
7892
7893 switch (element_type) {
7894 case I40E_SWITCH_ELEMENT_TYPE_MAC:
7895 pf->mac_seid = seid;
7896 break;
7897 case I40E_SWITCH_ELEMENT_TYPE_VEB:
7898 /* Main VEB? */
7899 if (uplink_seid != pf->mac_seid)
7900 break;
7901 if (pf->lan_veb == I40E_NO_VEB) {
7902 int v;
7903
7904 /* find existing or else empty VEB */
7905 for (v = 0; v < I40E_MAX_VEB; v++) {
7906 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
7907 pf->lan_veb = v;
7908 break;
7909 }
7910 }
7911 if (pf->lan_veb == I40E_NO_VEB) {
7912 v = i40e_veb_mem_alloc(pf);
7913 if (v < 0)
7914 break;
7915 pf->lan_veb = v;
7916 }
7917 }
7918
7919 pf->veb[pf->lan_veb]->seid = seid;
7920 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
7921 pf->veb[pf->lan_veb]->pf = pf;
7922 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
7923 break;
7924 case I40E_SWITCH_ELEMENT_TYPE_VSI:
7925 if (num_reported != 1)
7926 break;
7927 /* This is immediately after a reset so we can assume this is
7928 * the PF's VSI
7929 */
7930 pf->mac_seid = uplink_seid;
7931 pf->pf_seid = downlink_seid;
7932 pf->main_vsi_seid = seid;
7933 if (printconfig)
7934 dev_info(&pf->pdev->dev,
7935 "pf_seid=%d main_vsi_seid=%d\n",
7936 pf->pf_seid, pf->main_vsi_seid);
7937 break;
7938 case I40E_SWITCH_ELEMENT_TYPE_PF:
7939 case I40E_SWITCH_ELEMENT_TYPE_VF:
7940 case I40E_SWITCH_ELEMENT_TYPE_EMP:
7941 case I40E_SWITCH_ELEMENT_TYPE_BMC:
7942 case I40E_SWITCH_ELEMENT_TYPE_PE:
7943 case I40E_SWITCH_ELEMENT_TYPE_PA:
7944 /* ignore these for now */
7945 break;
7946 default:
7947 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
7948 element_type, seid);
7949 break;
7950 }
7951}
7952
7953/**
7954 * i40e_fetch_switch_configuration - Get switch config from firmware
7955 * @pf: board private structure
7956 * @printconfig: should we print the contents
7957 *
7958 * Get the current switch configuration from the device and
7959 * extract a few useful SEID values.
7960 **/
7961int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
7962{
7963 struct i40e_aqc_get_switch_config_resp *sw_config;
7964 u16 next_seid = 0;
7965 int ret = 0;
7966 u8 *aq_buf;
7967 int i;
7968
7969 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
7970 if (!aq_buf)
7971 return -ENOMEM;
7972
7973 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
7974 do {
7975 u16 num_reported, num_total;
7976
7977 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
7978 I40E_AQ_LARGE_BUF,
7979 &next_seid, NULL);
7980 if (ret) {
7981 dev_info(&pf->pdev->dev,
7982 "get switch config failed %d aq_err=%x\n",
7983 ret, pf->hw.aq.asq_last_status);
7984 kfree(aq_buf);
7985 return -ENOENT;
7986 }
7987
7988 num_reported = le16_to_cpu(sw_config->header.num_reported);
7989 num_total = le16_to_cpu(sw_config->header.num_total);
7990
7991 if (printconfig)
7992 dev_info(&pf->pdev->dev,
7993 "header: %d reported %d total\n",
7994 num_reported, num_total);
7995
41c445ff
JB		 7996 for (i = 0; i < num_reported; i++) {
7997 struct i40e_aqc_switch_config_element_resp *ele =
7998 &sw_config->element[i];
7999
8000 i40e_setup_pf_switch_element(pf, ele, num_reported,
8001 printconfig);
8002 }
8003 } while (next_seid != 0);
8004
8005 kfree(aq_buf);
8006 return ret;
8007}
8008
8009/**
8010 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
8011 * @pf: board private structure
bc7d338f 8012 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 8013 *
8014 * Returns 0 on success, negative value on failure
8015 **/
bc7d338f 8016static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 8017{
895106a5 8018 u32 rxfc = 0, txfc = 0, rxfc_reg;
41c445ff
JB		 8019 int ret;
8020
8021 /* find out what's out there already */
8022 ret = i40e_fetch_switch_configuration(pf, false);
8023 if (ret) {
8024 dev_info(&pf->pdev->dev,
8025 "couldn't fetch switch config, err %d, aq_err %d\n",
8026 ret, pf->hw.aq.asq_last_status);
8027 return ret;
8028 }
8029 i40e_pf_reset_stats(pf);
8030
41c445ff 8031 /* first time setup */
bc7d338f 8032 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 8033 struct i40e_vsi *vsi = NULL;
8034 u16 uplink_seid;
8035
8036 /* Set up the PF VSI associated with the PF's main VSI
8037 * that is already in the HW switch
8038 */
8039 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8040 uplink_seid = pf->veb[pf->lan_veb]->seid;
8041 else
8042 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 8043 if (pf->lan_vsi == I40E_NO_VSI)
8044 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
8045 else if (reinit)
8046 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 8047 if (!vsi) {
8048 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
8049 i40e_fdir_teardown(pf);
8050 return -EAGAIN;
8051 }
41c445ff
JB		 8052 } else {
8053 /* force a reset of TC and queue layout configurations */
8054 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
8055 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
8056 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
8057 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
8058 }
8059 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
8060
cbf61325
ASJ		 8061 i40e_fdir_sb_setup(pf);
8062
41c445ff
JB		 8063 /* Setup static PF queue filter control settings */
8064 ret = i40e_setup_pf_filter_control(pf);
8065 if (ret) {
8066 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
8067 ret);
8068 /* Failure here should not stop continuing other steps */
8069 }
8070
8071 /* enable RSS in the HW, even for only one queue, as the stack can use
8072 * the hash
8073 */
8074 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
8075 i40e_config_rss(pf);
8076
8077 /* fill in link information and enable LSE reporting */
8078 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
8079 i40e_link_event(pf);
8080
d52c20b7 8081 /* Initialize user-specific link properties */
41c445ff
JB		 8082 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
8083 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7
JB		 8084 /* requested_mode is set in probe or by ethtool */
8085 if (!pf->fc_autoneg_status)
8086 goto no_autoneg;
8087
8088 if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
8089 (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
41c445ff
JB		 8090 pf->hw.fc.current_mode = I40E_FC_FULL;
8091 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
8092 pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
8093 else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
8094 pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
8095 else
d52c20b7
JB		 8096 pf->hw.fc.current_mode = I40E_FC_NONE;
8097
8098 /* sync the flow control settings with the auto-neg values */
8099 switch (pf->hw.fc.current_mode) {
8100 case I40E_FC_FULL:
8101 txfc = 1;
8102 rxfc = 1;
8103 break;
8104 case I40E_FC_TX_PAUSE:
8105 txfc = 1;
8106 rxfc = 0;
8107 break;
8108 case I40E_FC_RX_PAUSE:
8109 txfc = 0;
8110 rxfc = 1;
8111 break;
8112 case I40E_FC_NONE:
8113 case I40E_FC_DEFAULT:
8114 txfc = 0;
8115 rxfc = 0;
8116 break;
8117 case I40E_FC_PFC:
8118 /* TBD */
8119 break;
8120 /* no default case, we have to handle all possibilities here */
8121 }
8122
8123 wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
8124
8125 rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8126 ~I40E_PRTDCB_MFLCN_RFCE_MASK;
8127 rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
8128
8129 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
41c445ff 8130
d52c20b7
JB		 8131 goto fc_complete;
8132
8133no_autoneg:
8134 /* disable L2 flow control, user can turn it on if they wish */
8135 wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
8136 wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
8137 ~I40E_PRTDCB_MFLCN_RFCE_MASK);
8138
8139fc_complete:
beb0dff1
JK		 8140 i40e_ptp_init(pf);
8141
41c445ff
JB		 8142 return ret;
8143}
8144
41c445ff
JB		 8145/**
8146 * i40e_determine_queue_usage - Work out queue distribution
8147 * @pf: board private structure
8148 **/
8149static void i40e_determine_queue_usage(struct i40e_pf *pf)
8150{
41c445ff
JB		 8151 int queues_left;
8152
8153 pf->num_lan_qps = 0;
41c445ff
JB		 8154
8155 /* Find the max queues to be put into basic use. We'll always be
8156 * using TC0, whether or not DCB is running, and TC0 will get the
8157 * big RSS set.
8158 */
8159 queues_left = pf->hw.func_caps.num_tx_qp;
8160
cbf61325
ASJ		 8161 if ((queues_left == 1) ||
8162 !(pf->flags & I40E_FLAG_MSIX_ENABLED) ||
8163 !(pf->flags & (I40E_FLAG_RSS_ENABLED | I40E_FLAG_FD_SB_ENABLED |
8164 I40E_FLAG_DCB_ENABLED))) {
41c445ff
JB		 8165 /* one qp for PF, no queues for anything else */
8166 queues_left = 0;
8167 pf->rss_size = pf->num_lan_qps = 1;
8168
8169 /* make sure all the fancies are disabled */
60ea5f83
JB		 8170 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
8171 I40E_FLAG_FD_SB_ENABLED |
8172 I40E_FLAG_FD_ATR_ENABLED |
8173 I40E_FLAG_DCB_ENABLED |
8174 I40E_FLAG_SRIOV_ENABLED |
8175 I40E_FLAG_VMDQ_ENABLED);
41c445ff 8176 } else {
cbf61325
ASJ		 8177 /* Not enough queues for all TCs */
8178 if ((pf->flags & I40E_FLAG_DCB_ENABLED) &&
8179 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
8180 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8181 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
8182 }
8183 pf->num_lan_qps = pf->rss_size_max;
8184 queues_left -= pf->num_lan_qps;
8185 }
8186
8187 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8188 if (queues_left > 1) {
8189 queues_left -= 1; /* save 1 queue for FD */
8190 } else {
8191 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8192 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
8193 }
41c445ff
JB		 8194 }
8195
8196 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
8197 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 8198 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
8199 (queues_left / pf->num_vf_qps));
41c445ff
JB		 8200 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
8201 }
8202
8203 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
8204 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
8205 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
8206 (queues_left / pf->num_vmdq_qps));
8207 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
8208 }
8209
f8ff1464 8210 pf->queues_left = queues_left;
41c445ff
JB		 8211}
8212
8213/**
8214 * i40e_setup_pf_filter_control - Setup PF static filter control
8215 * @pf: PF to be setup
8216 *
8217 * i40e_setup_pf_filter_control sets up a pf's initial filter control
8218 * settings. If PE/FCoE are enabled then it will also set the per PF
8219 * based filter sizes required for them. It also enables Flow director,
8220 * ethertype and macvlan type filter settings for the pf.
8221 *
8222 * Returns 0 on success, negative on failure
8223 **/
8224static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
8225{
8226 struct i40e_filter_control_settings *settings = &pf->filter_settings;
8227
8228 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
8229
8230 /* Flow Director is enabled */
60ea5f83 8231 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 8232 settings->enable_fdir = true;
8233
8234 /* Ethtype and MACVLAN filters enabled for PF */
8235 settings->enable_ethtype = true;
8236 settings->enable_macvlan = true;
8237
8238 if (i40e_set_filter_control(&pf->hw, settings))
8239 return -ENOENT;
8240
8241 return 0;
8242}
8243
0c22b3dd
JB		 8244#define INFO_STRING_LEN 255
8245static void i40e_print_features(struct i40e_pf *pf)
8246{
8247 struct i40e_hw *hw = &pf->hw;
8248 char *buf, *string;
8249
8250 string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);
8251 if (!string) {
8252 dev_err(&pf->pdev->dev, "Features string allocation failed\n");
8253 return;
8254 }
8255
8256 buf = string;
8257
8258 buf += sprintf(string, "Features: PF-id[%d] ", hw->pf_id);
8259#ifdef CONFIG_PCI_IOV
8260 buf += sprintf(buf, "VFs: %d ", pf->num_req_vfs);
8261#endif
8262 buf += sprintf(buf, "VSIs: %d QP: %d ", pf->hw.func_caps.num_vsis,
8263 pf->vsi[pf->lan_vsi]->num_queue_pairs);
8264
8265 if (pf->flags & I40E_FLAG_RSS_ENABLED)
8266 buf += sprintf(buf, "RSS ");
0c22b3dd 8267 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
c6423ff1
AA		 8268 buf += sprintf(buf, "FD_ATR ");
8269 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8270 buf += sprintf(buf, "FD_SB ");
0c22b3dd 8271 buf += sprintf(buf, "NTUPLE ");
c6423ff1 8272 }
0c22b3dd
JB		 8273 if (pf->flags & I40E_FLAG_DCB_ENABLED)
8274 buf += sprintf(buf, "DCB ");
8275 if (pf->flags & I40E_FLAG_PTP)
8276 buf += sprintf(buf, "PTP ");
8277
8278 BUG_ON(buf > (string + INFO_STRING_LEN));
8279 dev_info(&pf->pdev->dev, "%s\n", string);
8280 kfree(string);
8281}
8282
41c445ff
JB		 8283/**
8284 * i40e_probe - Device initialization routine
8285 * @pdev: PCI device information struct
8286 * @ent: entry in i40e_pci_tbl
8287 *
8288 * i40e_probe initializes a pf identified by a pci_dev structure.
8289 * The OS initialization, configuring of the pf private structure,
8290 * and a hardware reset occur.
8291 *
8292 * Returns 0 on success, negative on failure
8293 **/
8294static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8295{
41c445ff
JB		 8296 struct i40e_pf *pf;
8297 struct i40e_hw *hw;
93cd765b 8298 static u16 pfs_found;
d4dfb81a 8299 u16 link_status;
41c445ff
JB		 8300 int err = 0;
8301 u32 len;
8a9eb7d3 8302 u32 i;
41c445ff
JB		 8303
8304 err = pci_enable_device_mem(pdev);
8305 if (err)
8306 return err;
8307
8308 /* set up for high or low dma */
6494294f 8309 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 8310 if (err) {
e3e3bfdd
JS		 8311 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8312 if (err) {
8313 dev_err(&pdev->dev,
8314 "DMA configuration failed: 0x%x\n", err);
8315 goto err_dma;
8316 }
41c445ff
JB		 8317 }
8318
8319 /* set up pci connections */
8320 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8321 IORESOURCE_MEM), i40e_driver_name);
8322 if (err) {
8323 dev_info(&pdev->dev,
8324 "pci_request_selected_regions failed %d\n", err);
8325 goto err_pci_reg;
8326 }
8327
8328 pci_enable_pcie_error_reporting(pdev);
8329 pci_set_master(pdev);
8330
8331 /* Now that we have a PCI connection, we need to do the
8332 * low level device setup. This is primarily setting up
8333 * the Admin Queue structures and then querying for the
8334 * device's current profile information.
8335 */
8336 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
8337 if (!pf) {
8338 err = -ENOMEM;
8339 goto err_pf_alloc;
8340 }
8341 pf->next_vsi = 0;
8342 pf->pdev = pdev;
8343 set_bit(__I40E_DOWN, &pf->state);
8344
8345 hw = &pf->hw;
8346 hw->back = pf;
8347 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8348 pci_resource_len(pdev, 0));
8349 if (!hw->hw_addr) {
8350 err = -EIO;
8351 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
8352 (unsigned int)pci_resource_start(pdev, 0),
8353 (unsigned int)pci_resource_len(pdev, 0), err);
8354 goto err_ioremap;
8355 }
8356 hw->vendor_id = pdev->vendor;
8357 hw->device_id = pdev->device;
8358 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
8359 hw->subsystem_vendor_id = pdev->subsystem_vendor;
8360 hw->subsystem_device_id = pdev->subsystem_device;
8361 hw->bus.device = PCI_SLOT(pdev->devfn);
8362 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 8363 pf->instance = pfs_found;
41c445ff 8364
7134f9ce
JB		 8365 /* do a special CORER for clearing PXE mode once at init */
8366 if (hw->revision_id == 0 &&
8367 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
8368 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
8369 i40e_flush(hw);
8370 msleep(200);
8371 pf->corer_count++;
8372
8373 i40e_clear_pxe_mode(hw);
8374 }
8375
41c445ff
JB		 8376 /* Reset here to make sure all is clean and to define PF 'n' */
8377 err = i40e_pf_reset(hw);
8378 if (err) {
8379 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
8380 goto err_pf_reset;
8381 }
8382 pf->pfr_count++;
8383
8384 hw->aq.num_arq_entries = I40E_AQ_LEN;
8385 hw->aq.num_asq_entries = I40E_AQ_LEN;
8386 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8387 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
8388 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
8389 snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
8390 "%s-pf%d:misc",
8391 dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
8392
8393 err = i40e_init_shared_code(hw);
8394 if (err) {
8395 dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
8396 goto err_pf_reset;
8397 }
8398
d52c20b7
JB		 8399 /* set up a default setting for link flow control */
8400 pf->hw.fc.requested_mode = I40E_FC_NONE;
8401
41c445ff
JB		 8402 err = i40e_init_adminq(hw);
8403 dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
8404 if (err) {
8405 dev_info(&pdev->dev,
8406 "init_adminq failed: %d expecting API %02x.%02x\n",
8407 err,
8408 I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
8409 goto err_pf_reset;
8410 }
8411
4eb3f768
SN		 8412 i40e_verify_eeprom(pf);
8413
2c5fe33b
JB		 8414 /* Rev 0 hardware was never productized */
8415 if (hw->revision_id < 1)
8416 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
8417
6ff4ef86 8418 i40e_clear_pxe_mode(hw);
41c445ff
JB		 8419 err = i40e_get_capabilities(pf);
8420 if (err)
8421 goto err_adminq_setup;
8422
8423 err = i40e_sw_init(pf);
8424 if (err) {
8425 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
8426 goto err_sw_init;
8427 }
8428
8429 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
8430 hw->func_caps.num_rx_qp,
8431 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
8432 if (err) {
8433 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
8434 goto err_init_lan_hmc;
8435 }
8436
8437 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
8438 if (err) {
8439 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
8440 err = -ENOENT;
8441 goto err_configure_lan_hmc;
8442 }
8443
8444 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 8445 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 8446 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
8447 err = -EIO;
8448 goto err_mac_addr;
8449 }
8450 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
8451 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
8452
8453 pci_set_drvdata(pdev, pf);
8454 pci_save_state(pdev);
4e3b35b0
NP		 8455#ifdef CONFIG_I40E_DCB
8456 err = i40e_init_pf_dcb(pf);
8457 if (err) {
8458 dev_info(&pdev->dev, "init_pf_dcb failed: %d\n", err);
8459 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
014269ff 8460 /* Continue without DCB enabled */
4e3b35b0
NP		 8461 }
8462#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 8463
8464 /* set up periodic task facility */
8465 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
8466 pf->service_timer_period = HZ;
8467
8468 INIT_WORK(&pf->service_task, i40e_service_task);
8469 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
8470 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
8471 pf->link_check_timeout = jiffies;
8472
8e2773ae
SN		 8473 /* WoL defaults to disabled */
8474 pf->wol_en = false;
8475 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
8476
41c445ff
JB		 8477 /* set up the main switch operations */
8478 i40e_determine_queue_usage(pf);
8479 i40e_init_interrupt_scheme(pf);
8480
505682cd
MW		 8481 /* The number of VSIs reported by the FW is the minimum guaranteed
8482 * to us; HW supports far more and we share the remaining pool with
8483 * the other PFs. We allocate space for more than the guarantee with
8484 * the understanding that we might not get them all later.
41c445ff 8485 */
505682cd
MW		 8486 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
8487 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
8488 else
8489 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
8490
8491 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
8492 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 8493 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 8494 if (!pf->vsi) {
8495 err = -ENOMEM;
41c445ff 8496 goto err_switch_setup;
ed87ac09 8497 }
41c445ff 8498
bc7d338f 8499 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 8500 if (err) {
8501 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
8502 goto err_vsis;
8503 }
8a9eb7d3 8504 /* if FDIR VSI was set up, start it now */
505682cd 8505 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 8506 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
8507 i40e_vsi_open(pf->vsi[i]);
8508 break;
8509 }
8510 }
41c445ff
JB		 8511
8512 /* The main driver is (mostly) up and happy. We need to set this state
8513 * before setting up the misc vector or we get a race and the vector
8514 * ends up disabled forever.
8515 */
8516 clear_bit(__I40E_DOWN, &pf->state);
8517
8518 /* In case of MSIX we are going to setup the misc vector right here
8519 * to handle admin queue events etc. In case of legacy and MSI
8520 * the misc functionality and queue processing is combined in
8521 * the same vector and that gets setup at open.
8522 */
8523 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8524 err = i40e_setup_misc_vector(pf);
8525 if (err) {
8526 dev_info(&pdev->dev,
8527 "setup of misc vector failed: %d\n", err);
8528 goto err_vsis;
8529 }
8530 }
8531
df805f62 8532#ifdef CONFIG_PCI_IOV
41c445ff
JB		 8533 /* prep for VF support */
8534 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 8535 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
8536 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 8537 u32 val;
8538
8539 /* disable link interrupts for VFs */
8540 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
8541 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
8542 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
8543 i40e_flush(hw);
4aeec010
MW		 8544
8545 if (pci_num_vf(pdev)) {
8546 dev_info(&pdev->dev,
8547 "Active VFs found, allocating resources.\n");
8548 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
8549 if (err)
8550 dev_info(&pdev->dev,
8551 "Error %d allocating resources for existing VFs\n",
8552 err);
8553 }
41c445ff 8554 }
df805f62 8555#endif /* CONFIG_PCI_IOV */
41c445ff 8556
93cd765b
ASJ		 8557 pfs_found++;
8558
41c445ff
JB		 8559 i40e_dbg_pf_init(pf);
8560
8561 /* tell the firmware that we're starting */
44033fac 8562 i40e_send_version(pf);
41c445ff
JB		 8563
8564 /* since everything's happy, start the service_task timer */
8565 mod_timer(&pf->service_timer,
8566 round_jiffies(jiffies + pf->service_timer_period));
8567
d4dfb81a
CS		 8568 /* Get the negotiated link width and speed from PCI config space */
8569 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);
8570
8571 i40e_set_pci_config_data(hw, link_status);
8572
69bfb110 8573 dev_info(&pdev->dev, "PCI-Express: %s %s\n",
d4dfb81a
CS		 8574 (hw->bus.speed == i40e_bus_speed_8000 ? "Speed 8.0GT/s" :
8575 hw->bus.speed == i40e_bus_speed_5000 ? "Speed 5.0GT/s" :
8576 hw->bus.speed == i40e_bus_speed_2500 ? "Speed 2.5GT/s" :
8577 "Unknown"),
8578 (hw->bus.width == i40e_bus_width_pcie_x8 ? "Width x8" :
8579 hw->bus.width == i40e_bus_width_pcie_x4 ? "Width x4" :
8580 hw->bus.width == i40e_bus_width_pcie_x2 ? "Width x2" :
8581 hw->bus.width == i40e_bus_width_pcie_x1 ? "Width x1" :
8582 "Unknown"));
8583
8584 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
8585 hw->bus.speed < i40e_bus_speed_8000) {
8586 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
8587 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
8588 }
8589
0c22b3dd
JB		 8590 /* print a string summarizing features */
8591 i40e_print_features(pf);
8592
41c445ff
JB		 8593 return 0;
8594
8595 /* Unwind what we've done if something failed in the setup */
8596err_vsis:
8597 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 8598 i40e_clear_interrupt_scheme(pf);
8599 kfree(pf->vsi);
04b03013
SN		 8600err_switch_setup:
8601 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 8602 del_timer_sync(&pf->service_timer);
8603err_mac_addr:
8604err_configure_lan_hmc:
8605 (void)i40e_shutdown_lan_hmc(hw);
8606err_init_lan_hmc:
8607 kfree(pf->qp_pile);
8608 kfree(pf->irq_pile);
8609err_sw_init:
8610err_adminq_setup:
8611 (void)i40e_shutdown_adminq(hw);
8612err_pf_reset:
8613 iounmap(hw->hw_addr);
8614err_ioremap:
8615 kfree(pf);
8616err_pf_alloc:
8617 pci_disable_pcie_error_reporting(pdev);
8618 pci_release_selected_regions(pdev,
8619 pci_select_bars(pdev, IORESOURCE_MEM));
8620err_pci_reg:
8621err_dma:
8622 pci_disable_device(pdev);
8623 return err;
8624}
8625
8626/**
8627 * i40e_remove - Device removal routine
8628 * @pdev: PCI device information struct
8629 *
8630 * i40e_remove is called by the PCI subsystem to alert the driver
8631 * that is should release a PCI device. This could be caused by a
8632 * Hot-Plug event, or because the driver is going to be removed from
8633 * memory.
8634 **/
8635static void i40e_remove(struct pci_dev *pdev)
8636{
8637 struct i40e_pf *pf = pci_get_drvdata(pdev);
8638 i40e_status ret_code;
8639 u32 reg;
8640 int i;
8641
8642 i40e_dbg_pf_exit(pf);
8643
beb0dff1
JK		 8644 i40e_ptp_stop(pf);
8645
41c445ff
JB		 8646 /* no more scheduling of any task */
8647 set_bit(__I40E_DOWN, &pf->state);
8648 del_timer_sync(&pf->service_timer);
8649 cancel_work_sync(&pf->service_task);
8650
eb2d80bc
MW		 8651 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
8652 i40e_free_vfs(pf);
8653 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
8654 }
8655
41c445ff
JB		 8656 i40e_fdir_teardown(pf);
8657
8658 /* If there is a switch structure or any orphans, remove them.
8659 * This will leave only the PF's VSI remaining.
8660 */
8661 for (i = 0; i < I40E_MAX_VEB; i++) {
8662 if (!pf->veb[i])
8663 continue;
8664
8665 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
8666 pf->veb[i]->uplink_seid == 0)
8667 i40e_switch_branch_release(pf->veb[i]);
8668 }
8669
8670 /* Now we can shutdown the PF's VSI, just before we kill
8671 * adminq and hmc.
8672 */
8673 if (pf->vsi[pf->lan_vsi])
8674 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
8675
8676 i40e_stop_misc_vector(pf);
8677 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
8678 synchronize_irq(pf->msix_entries[0].vector);
8679 free_irq(pf->msix_entries[0].vector, pf);
8680 }
8681
8682 /* shutdown and destroy the HMC */
60442dea
SN		 8683 if (pf->hw.hmc.hmc_obj) {
8684 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
8685 if (ret_code)
8686 dev_warn(&pdev->dev,
8687 "Failed to destroy the HMC resources: %d\n",
8688 ret_code);
8689 }
41c445ff
JB		 8690
8691 /* shutdown the adminq */
41c445ff
JB		 8692 ret_code = i40e_shutdown_adminq(&pf->hw);
8693 if (ret_code)
8694 dev_warn(&pdev->dev,
8695 "Failed to destroy the Admin Queue resources: %d\n",
8696 ret_code);
8697
8698 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
8699 i40e_clear_interrupt_scheme(pf);
505682cd 8700 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 8701 if (pf->vsi[i]) {
8702 i40e_vsi_clear_rings(pf->vsi[i]);
8703 i40e_vsi_clear(pf->vsi[i]);
8704 pf->vsi[i] = NULL;
8705 }
8706 }
8707
8708 for (i = 0; i < I40E_MAX_VEB; i++) {
8709 kfree(pf->veb[i]);
8710 pf->veb[i] = NULL;
8711 }
8712
8713 kfree(pf->qp_pile);
8714 kfree(pf->irq_pile);
41c445ff
JB		 8715 kfree(pf->vsi);
8716
8717 /* force a PF reset to clean anything leftover */
8718 reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
8719 wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
8720 i40e_flush(&pf->hw);
8721
8722 iounmap(pf->hw.hw_addr);
8723 kfree(pf);
8724 pci_release_selected_regions(pdev,
8725 pci_select_bars(pdev, IORESOURCE_MEM));
8726
8727 pci_disable_pcie_error_reporting(pdev);
8728 pci_disable_device(pdev);
8729}
8730
8731/**
8732 * i40e_pci_error_detected - warning that something funky happened in PCI land
8733 * @pdev: PCI device information struct
8734 *
8735 * Called to warn that something happened and the error handling steps
8736 * are in progress. Allows the driver to quiesce things, be ready for
8737 * remediation.
8738 **/
8739static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
8740 enum pci_channel_state error)
8741{
8742 struct i40e_pf *pf = pci_get_drvdata(pdev);
8743
8744 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
8745
8746 /* shutdown all operations */
9007bccd
SN		 8747 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
8748 rtnl_lock();
8749 i40e_prep_for_reset(pf);
8750 rtnl_unlock();
8751 }
41c445ff
JB		 8752
8753 /* Request a slot reset */
8754 return PCI_ERS_RESULT_NEED_RESET;
8755}
8756
8757/**
8758 * i40e_pci_error_slot_reset - a PCI slot reset just happened
8759 * @pdev: PCI device information struct
8760 *
8761 * Called to find if the driver can work with the device now that
8762 * the pci slot has been reset. If a basic connection seems good
8763 * (registers are readable and have sane content) then return a
8764 * happy little PCI_ERS_RESULT_xxx.
8765 **/
8766static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
8767{
8768 struct i40e_pf *pf = pci_get_drvdata(pdev);
8769 pci_ers_result_t result;
8770 int err;
8771 u32 reg;
8772
8773 dev_info(&pdev->dev, "%s\n", __func__);
8774 if (pci_enable_device_mem(pdev)) {
8775 dev_info(&pdev->dev,
8776 "Cannot re-enable PCI device after reset.\n");
8777 result = PCI_ERS_RESULT_DISCONNECT;
8778 } else {
8779 pci_set_master(pdev);
8780 pci_restore_state(pdev);
8781 pci_save_state(pdev);
8782 pci_wake_from_d3(pdev, false);
8783
8784 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
8785 if (reg == 0)
8786 result = PCI_ERS_RESULT_RECOVERED;
8787 else
8788 result = PCI_ERS_RESULT_DISCONNECT;
8789 }
8790
8791 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8792 if (err) {
8793 dev_info(&pdev->dev,
8794 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8795 err);
8796 /* non-fatal, continue */
8797 }
8798
8799 return result;
8800}
8801
8802/**
8803 * i40e_pci_error_resume - restart operations after PCI error recovery
8804 * @pdev: PCI device information struct
8805 *
8806 * Called to allow the driver to bring things back up after PCI error
8807 * and/or reset recovery has finished.
8808 **/
8809static void i40e_pci_error_resume(struct pci_dev *pdev)
8810{
8811 struct i40e_pf *pf = pci_get_drvdata(pdev);
8812
8813 dev_info(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 8814 if (test_bit(__I40E_SUSPENDED, &pf->state))
8815 return;
8816
8817 rtnl_lock();
41c445ff 8818 i40e_handle_reset_warning(pf);
9007bccd
SN		 8819 rtnl_lock();
8820}
8821
8822/**
8823 * i40e_shutdown - PCI callback for shutting down
8824 * @pdev: PCI device information struct
8825 **/
8826static void i40e_shutdown(struct pci_dev *pdev)
8827{
8828 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8829 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8830
8831 set_bit(__I40E_SUSPENDED, &pf->state);
8832 set_bit(__I40E_DOWN, &pf->state);
8833 rtnl_lock();
8834 i40e_prep_for_reset(pf);
8835 rtnl_unlock();
8836
8e2773ae
SN		 8837 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8838 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8839
9007bccd 8840 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 8841 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8842 pci_set_power_state(pdev, PCI_D3hot);
8843 }
8844}
8845
8846#ifdef CONFIG_PM
8847/**
8848 * i40e_suspend - PCI callback for moving to D3
8849 * @pdev: PCI device information struct
8850 **/
8851static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
8852{
8853 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 8854 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 8855
8856 set_bit(__I40E_SUSPENDED, &pf->state);
8857 set_bit(__I40E_DOWN, &pf->state);
8858 rtnl_lock();
8859 i40e_prep_for_reset(pf);
8860 rtnl_unlock();
8861
8e2773ae
SN		 8862 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
8863 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
8864
8865 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 8866 pci_set_power_state(pdev, PCI_D3hot);
8867
8868 return 0;
41c445ff
JB		 8869}
8870
9007bccd
SN		 8871/**
8872 * i40e_resume - PCI callback for waking up from D3
8873 * @pdev: PCI device information struct
8874 **/
8875static int i40e_resume(struct pci_dev *pdev)
8876{
8877 struct i40e_pf *pf = pci_get_drvdata(pdev);
8878 u32 err;
8879
8880 pci_set_power_state(pdev, PCI_D0);
8881 pci_restore_state(pdev);
8882 /* pci_restore_state() clears dev->state_saves, so
8883 * call pci_save_state() again to restore it.
8884 */
8885 pci_save_state(pdev);
8886
8887 err = pci_enable_device_mem(pdev);
8888 if (err) {
8889 dev_err(&pdev->dev,
8890 "%s: Cannot enable PCI device from suspend\n",
8891 __func__);
8892 return err;
8893 }
8894 pci_set_master(pdev);
8895
8896 /* no wakeup events while running */
8897 pci_wake_from_d3(pdev, false);
8898
8899 /* handling the reset will rebuild the device state */
8900 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
8901 clear_bit(__I40E_DOWN, &pf->state);
8902 rtnl_lock();
8903 i40e_reset_and_rebuild(pf, false);
8904 rtnl_unlock();
8905 }
8906
8907 return 0;
8908}
8909
8910#endif
41c445ff
JB		 8911static const struct pci_error_handlers i40e_err_handler = {
8912 .error_detected = i40e_pci_error_detected,
8913 .slot_reset = i40e_pci_error_slot_reset,
8914 .resume = i40e_pci_error_resume,
8915};
8916
8917static struct pci_driver i40e_driver = {
8918 .name = i40e_driver_name,
8919 .id_table = i40e_pci_tbl,
8920 .probe = i40e_probe,
8921 .remove = i40e_remove,
9007bccd
SN		 8922#ifdef CONFIG_PM
8923 .suspend = i40e_suspend,
8924 .resume = i40e_resume,
8925#endif
8926 .shutdown = i40e_shutdown,
41c445ff
JB		 8927 .err_handler = &i40e_err_handler,
8928 .sriov_configure = i40e_pci_sriov_configure,
8929};
8930
8931/**
8932 * i40e_init_module - Driver registration routine
8933 *
8934 * i40e_init_module is the first routine called when the driver is
8935 * loaded. All it does is register with the PCI subsystem.
8936 **/
8937static int __init i40e_init_module(void)
8938{
8939 pr_info("%s: %s - version %s\n", i40e_driver_name,
8940 i40e_driver_string, i40e_driver_version_str);
8941 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
8942 i40e_dbg_init();
8943 return pci_register_driver(&i40e_driver);
8944}
8945module_init(i40e_init_module);
8946
8947/**
8948 * i40e_exit_module - Driver exit cleanup routine
8949 *
8950 * i40e_exit_module is called just before the driver is removed
8951 * from memory.
8952 **/
8953static void __exit i40e_exit_module(void)
8954{
8955 pci_unregister_driver(&i40e_driver);
8956 i40e_dbg_exit();
8957}
8958module_exit(i40e_exit_module);
Linux kernel - Deliverables
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