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7f12ad74 GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
af1a2a9c | 4 | * Copyright(c) 2013 - 2014 Intel Corporation. |
7f12ad74 GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
7f12ad74 GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
7ed3f5f0 PG |
27 | #include <linux/prefetch.h> |
28 | ||
7f12ad74 | 29 | #include "i40evf.h" |
206812b5 | 30 | #include "i40e_prototype.h" |
7f12ad74 GR |
31 | |
32 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
33 | u32 td_tag) | |
34 | { | |
35 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
36 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
37 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
38 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
39 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
40 | } | |
41 | ||
42 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) | |
43 | ||
44 | /** | |
45 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer | |
46 | * @ring: the ring that owns the buffer | |
47 | * @tx_buffer: the buffer to free | |
48 | **/ | |
49 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, | |
50 | struct i40e_tx_buffer *tx_buffer) | |
51 | { | |
52 | if (tx_buffer->skb) { | |
49d7d933 ASJ |
53 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
54 | kfree(tx_buffer->raw_buf); | |
55 | else | |
56 | dev_kfree_skb_any(tx_buffer->skb); | |
57 | ||
7f12ad74 GR |
58 | if (dma_unmap_len(tx_buffer, len)) |
59 | dma_unmap_single(ring->dev, | |
60 | dma_unmap_addr(tx_buffer, dma), | |
61 | dma_unmap_len(tx_buffer, len), | |
62 | DMA_TO_DEVICE); | |
63 | } else if (dma_unmap_len(tx_buffer, len)) { | |
64 | dma_unmap_page(ring->dev, | |
65 | dma_unmap_addr(tx_buffer, dma), | |
66 | dma_unmap_len(tx_buffer, len), | |
67 | DMA_TO_DEVICE); | |
68 | } | |
69 | tx_buffer->next_to_watch = NULL; | |
70 | tx_buffer->skb = NULL; | |
71 | dma_unmap_len_set(tx_buffer, len, 0); | |
72 | /* tx_buffer must be completely set up in the transmit path */ | |
73 | } | |
74 | ||
75 | /** | |
76 | * i40evf_clean_tx_ring - Free any empty Tx buffers | |
77 | * @tx_ring: ring to be cleaned | |
78 | **/ | |
79 | void i40evf_clean_tx_ring(struct i40e_ring *tx_ring) | |
80 | { | |
81 | unsigned long bi_size; | |
82 | u16 i; | |
83 | ||
84 | /* ring already cleared, nothing to do */ | |
85 | if (!tx_ring->tx_bi) | |
86 | return; | |
87 | ||
88 | /* Free all the Tx ring sk_buffs */ | |
89 | for (i = 0; i < tx_ring->count; i++) | |
90 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
91 | ||
92 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
93 | memset(tx_ring->tx_bi, 0, bi_size); | |
94 | ||
95 | /* Zero out the descriptor ring */ | |
96 | memset(tx_ring->desc, 0, tx_ring->size); | |
97 | ||
98 | tx_ring->next_to_use = 0; | |
99 | tx_ring->next_to_clean = 0; | |
100 | ||
101 | if (!tx_ring->netdev) | |
102 | return; | |
103 | ||
104 | /* cleanup Tx queue statistics */ | |
105 | netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, | |
106 | tx_ring->queue_index)); | |
107 | } | |
108 | ||
109 | /** | |
110 | * i40evf_free_tx_resources - Free Tx resources per queue | |
111 | * @tx_ring: Tx descriptor ring for a specific queue | |
112 | * | |
113 | * Free all transmit software resources | |
114 | **/ | |
115 | void i40evf_free_tx_resources(struct i40e_ring *tx_ring) | |
116 | { | |
117 | i40evf_clean_tx_ring(tx_ring); | |
118 | kfree(tx_ring->tx_bi); | |
119 | tx_ring->tx_bi = NULL; | |
120 | ||
121 | if (tx_ring->desc) { | |
122 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
123 | tx_ring->desc, tx_ring->dma); | |
124 | tx_ring->desc = NULL; | |
125 | } | |
126 | } | |
127 | ||
128 | /** | |
129 | * i40e_get_tx_pending - how many tx descriptors not processed | |
130 | * @tx_ring: the ring of descriptors | |
131 | * | |
132 | * Since there is no access to the ring head register | |
133 | * in XL710, we need to use our local copies | |
134 | **/ | |
135 | static u32 i40e_get_tx_pending(struct i40e_ring *ring) | |
136 | { | |
137 | u32 ntu = ((ring->next_to_clean <= ring->next_to_use) | |
138 | ? ring->next_to_use | |
139 | : ring->next_to_use + ring->count); | |
140 | return ntu - ring->next_to_clean; | |
141 | } | |
142 | ||
143 | /** | |
144 | * i40e_check_tx_hang - Is there a hang in the Tx queue | |
145 | * @tx_ring: the ring of descriptors | |
146 | **/ | |
147 | static bool i40e_check_tx_hang(struct i40e_ring *tx_ring) | |
148 | { | |
149 | u32 tx_pending = i40e_get_tx_pending(tx_ring); | |
150 | bool ret = false; | |
151 | ||
152 | clear_check_for_tx_hang(tx_ring); | |
153 | ||
154 | /* Check for a hung queue, but be thorough. This verifies | |
155 | * that a transmit has been completed since the previous | |
156 | * check AND there is at least one packet pending. The | |
157 | * ARMED bit is set to indicate a potential hang. The | |
158 | * bit is cleared if a pause frame is received to remove | |
159 | * false hang detection due to PFC or 802.3x frames. By | |
160 | * requiring this to fail twice we avoid races with | |
161 | * PFC clearing the ARMED bit and conditions where we | |
162 | * run the check_tx_hang logic with a transmit completion | |
163 | * pending but without time to complete it yet. | |
164 | */ | |
165 | if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) && | |
810b3ae4 | 166 | (tx_pending >= I40E_MIN_DESC_PENDING)) { |
7f12ad74 GR |
167 | /* make sure it is true for two checks in a row */ |
168 | ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED, | |
169 | &tx_ring->state); | |
810b3ae4 ASJ |
170 | } else if (!(tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) || |
171 | !(tx_pending < I40E_MIN_DESC_PENDING) || | |
172 | !(tx_pending > 0)) { | |
7f12ad74 GR |
173 | /* update completed stats and disarm the hang check */ |
174 | tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets; | |
175 | clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state); | |
176 | } | |
177 | ||
178 | return ret; | |
179 | } | |
180 | ||
1943d8ba JB |
181 | /** |
182 | * i40e_get_head - Retrieve head from head writeback | |
183 | * @tx_ring: tx ring to fetch head of | |
184 | * | |
185 | * Returns value of Tx ring head based on value stored | |
186 | * in head write-back location | |
187 | **/ | |
188 | static inline u32 i40e_get_head(struct i40e_ring *tx_ring) | |
189 | { | |
190 | void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; | |
191 | ||
192 | return le32_to_cpu(*(volatile __le32 *)head); | |
193 | } | |
194 | ||
c29af37f ASJ |
195 | #define WB_STRIDE 0x3 |
196 | ||
7f12ad74 GR |
197 | /** |
198 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
199 | * @tx_ring: tx ring to clean | |
200 | * @budget: how many cleans we're allowed | |
201 | * | |
202 | * Returns true if there's any budget left (e.g. the clean is finished) | |
203 | **/ | |
204 | static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) | |
205 | { | |
206 | u16 i = tx_ring->next_to_clean; | |
207 | struct i40e_tx_buffer *tx_buf; | |
1943d8ba | 208 | struct i40e_tx_desc *tx_head; |
7f12ad74 GR |
209 | struct i40e_tx_desc *tx_desc; |
210 | unsigned int total_packets = 0; | |
211 | unsigned int total_bytes = 0; | |
212 | ||
213 | tx_buf = &tx_ring->tx_bi[i]; | |
214 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
215 | i -= tx_ring->count; | |
216 | ||
1943d8ba JB |
217 | tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); |
218 | ||
7f12ad74 GR |
219 | do { |
220 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
221 | ||
222 | /* if next_to_watch is not set then there is no work pending */ | |
223 | if (!eop_desc) | |
224 | break; | |
225 | ||
226 | /* prevent any other reads prior to eop_desc */ | |
227 | read_barrier_depends(); | |
228 | ||
1943d8ba JB |
229 | /* we have caught up to head, no work left to do */ |
230 | if (tx_head == tx_desc) | |
7f12ad74 GR |
231 | break; |
232 | ||
233 | /* clear next_to_watch to prevent false hangs */ | |
234 | tx_buf->next_to_watch = NULL; | |
235 | ||
236 | /* update the statistics for this packet */ | |
237 | total_bytes += tx_buf->bytecount; | |
238 | total_packets += tx_buf->gso_segs; | |
239 | ||
240 | /* free the skb */ | |
241 | dev_kfree_skb_any(tx_buf->skb); | |
242 | ||
243 | /* unmap skb header data */ | |
244 | dma_unmap_single(tx_ring->dev, | |
245 | dma_unmap_addr(tx_buf, dma), | |
246 | dma_unmap_len(tx_buf, len), | |
247 | DMA_TO_DEVICE); | |
248 | ||
249 | /* clear tx_buffer data */ | |
250 | tx_buf->skb = NULL; | |
251 | dma_unmap_len_set(tx_buf, len, 0); | |
252 | ||
253 | /* unmap remaining buffers */ | |
254 | while (tx_desc != eop_desc) { | |
255 | ||
256 | tx_buf++; | |
257 | tx_desc++; | |
258 | i++; | |
259 | if (unlikely(!i)) { | |
260 | i -= tx_ring->count; | |
261 | tx_buf = tx_ring->tx_bi; | |
262 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
263 | } | |
264 | ||
265 | /* unmap any remaining paged data */ | |
266 | if (dma_unmap_len(tx_buf, len)) { | |
267 | dma_unmap_page(tx_ring->dev, | |
268 | dma_unmap_addr(tx_buf, dma), | |
269 | dma_unmap_len(tx_buf, len), | |
270 | DMA_TO_DEVICE); | |
271 | dma_unmap_len_set(tx_buf, len, 0); | |
272 | } | |
273 | } | |
274 | ||
275 | /* move us one more past the eop_desc for start of next pkt */ | |
276 | tx_buf++; | |
277 | tx_desc++; | |
278 | i++; | |
279 | if (unlikely(!i)) { | |
280 | i -= tx_ring->count; | |
281 | tx_buf = tx_ring->tx_bi; | |
282 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
283 | } | |
284 | ||
285 | /* update budget accounting */ | |
286 | budget--; | |
287 | } while (likely(budget)); | |
288 | ||
289 | i += tx_ring->count; | |
290 | tx_ring->next_to_clean = i; | |
291 | u64_stats_update_begin(&tx_ring->syncp); | |
292 | tx_ring->stats.bytes += total_bytes; | |
293 | tx_ring->stats.packets += total_packets; | |
294 | u64_stats_update_end(&tx_ring->syncp); | |
295 | tx_ring->q_vector->tx.total_bytes += total_bytes; | |
296 | tx_ring->q_vector->tx.total_packets += total_packets; | |
297 | ||
c29af37f ASJ |
298 | if (budget && |
299 | !((i & WB_STRIDE) == WB_STRIDE) && | |
300 | !test_bit(__I40E_DOWN, &tx_ring->vsi->state) && | |
301 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) | |
302 | tx_ring->arm_wb = true; | |
303 | else | |
304 | tx_ring->arm_wb = false; | |
305 | ||
7f12ad74 GR |
306 | if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) { |
307 | /* schedule immediate reset if we believe we hung */ | |
308 | dev_info(tx_ring->dev, "Detected Tx Unit Hang\n" | |
309 | " VSI <%d>\n" | |
310 | " Tx Queue <%d>\n" | |
311 | " next_to_use <%x>\n" | |
312 | " next_to_clean <%x>\n", | |
313 | tx_ring->vsi->seid, | |
314 | tx_ring->queue_index, | |
315 | tx_ring->next_to_use, i); | |
316 | dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n" | |
317 | " time_stamp <%lx>\n" | |
318 | " jiffies <%lx>\n", | |
319 | tx_ring->tx_bi[i].time_stamp, jiffies); | |
320 | ||
321 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
322 | ||
323 | dev_info(tx_ring->dev, | |
324 | "tx hang detected on queue %d, resetting adapter\n", | |
325 | tx_ring->queue_index); | |
326 | ||
327 | tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev); | |
328 | ||
329 | /* the adapter is about to reset, no point in enabling stuff */ | |
330 | return true; | |
331 | } | |
332 | ||
333 | netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, | |
334 | tx_ring->queue_index), | |
335 | total_packets, total_bytes); | |
336 | ||
337 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) | |
338 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
339 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
340 | /* Make sure that anybody stopping the queue after this | |
341 | * sees the new next_to_clean. | |
342 | */ | |
343 | smp_mb(); | |
344 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
345 | tx_ring->queue_index) && | |
346 | !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) { | |
347 | netif_wake_subqueue(tx_ring->netdev, | |
348 | tx_ring->queue_index); | |
349 | ++tx_ring->tx_stats.restart_queue; | |
350 | } | |
351 | } | |
352 | ||
353 | return budget > 0; | |
354 | } | |
355 | ||
c29af37f ASJ |
356 | /** |
357 | * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors | |
358 | * @vsi: the VSI we care about | |
359 | * @q_vector: the vector on which to force writeback | |
360 | * | |
361 | **/ | |
362 | static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
363 | { | |
364 | u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK | | |
365 | I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK | | |
366 | I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; | |
367 | /* allow 00 to be written to the index */ | |
368 | ||
369 | wr32(&vsi->back->hw, | |
370 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1), | |
371 | val); | |
372 | } | |
373 | ||
7f12ad74 GR |
374 | /** |
375 | * i40e_set_new_dynamic_itr - Find new ITR level | |
376 | * @rc: structure containing ring performance data | |
377 | * | |
378 | * Stores a new ITR value based on packets and byte counts during | |
379 | * the last interrupt. The advantage of per interrupt computation | |
380 | * is faster updates and more accurate ITR for the current traffic | |
381 | * pattern. Constants in this function were computed based on | |
382 | * theoretical maximum wire speed and thresholds were set based on | |
383 | * testing data as well as attempting to minimize response time | |
384 | * while increasing bulk throughput. | |
385 | **/ | |
386 | static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) | |
387 | { | |
388 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
389 | u32 new_itr = rc->itr; | |
390 | int bytes_per_int; | |
391 | ||
392 | if (rc->total_packets == 0 || !rc->itr) | |
393 | return; | |
394 | ||
395 | /* simple throttlerate management | |
396 | * 0-10MB/s lowest (100000 ints/s) | |
397 | * 10-20MB/s low (20000 ints/s) | |
398 | * 20-1249MB/s bulk (8000 ints/s) | |
399 | */ | |
400 | bytes_per_int = rc->total_bytes / rc->itr; | |
401 | switch (rc->itr) { | |
402 | case I40E_LOWEST_LATENCY: | |
403 | if (bytes_per_int > 10) | |
404 | new_latency_range = I40E_LOW_LATENCY; | |
405 | break; | |
406 | case I40E_LOW_LATENCY: | |
407 | if (bytes_per_int > 20) | |
408 | new_latency_range = I40E_BULK_LATENCY; | |
409 | else if (bytes_per_int <= 10) | |
410 | new_latency_range = I40E_LOWEST_LATENCY; | |
411 | break; | |
412 | case I40E_BULK_LATENCY: | |
413 | if (bytes_per_int <= 20) | |
414 | rc->latency_range = I40E_LOW_LATENCY; | |
415 | break; | |
416 | } | |
417 | ||
418 | switch (new_latency_range) { | |
419 | case I40E_LOWEST_LATENCY: | |
420 | new_itr = I40E_ITR_100K; | |
421 | break; | |
422 | case I40E_LOW_LATENCY: | |
423 | new_itr = I40E_ITR_20K; | |
424 | break; | |
425 | case I40E_BULK_LATENCY: | |
426 | new_itr = I40E_ITR_8K; | |
427 | break; | |
428 | default: | |
429 | break; | |
430 | } | |
431 | ||
432 | if (new_itr != rc->itr) { | |
433 | /* do an exponential smoothing */ | |
434 | new_itr = (10 * new_itr * rc->itr) / | |
435 | ((9 * new_itr) + rc->itr); | |
436 | rc->itr = new_itr & I40E_MAX_ITR; | |
437 | } | |
438 | ||
439 | rc->total_bytes = 0; | |
440 | rc->total_packets = 0; | |
441 | } | |
442 | ||
443 | /** | |
444 | * i40e_update_dynamic_itr - Adjust ITR based on bytes per int | |
445 | * @q_vector: the vector to adjust | |
446 | **/ | |
447 | static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector) | |
448 | { | |
449 | u16 vector = q_vector->vsi->base_vector + q_vector->v_idx; | |
450 | struct i40e_hw *hw = &q_vector->vsi->back->hw; | |
451 | u32 reg_addr; | |
452 | u16 old_itr; | |
453 | ||
454 | reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1); | |
455 | old_itr = q_vector->rx.itr; | |
456 | i40e_set_new_dynamic_itr(&q_vector->rx); | |
457 | if (old_itr != q_vector->rx.itr) | |
458 | wr32(hw, reg_addr, q_vector->rx.itr); | |
459 | ||
460 | reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1); | |
461 | old_itr = q_vector->tx.itr; | |
462 | i40e_set_new_dynamic_itr(&q_vector->tx); | |
463 | if (old_itr != q_vector->tx.itr) | |
464 | wr32(hw, reg_addr, q_vector->tx.itr); | |
465 | } | |
466 | ||
467 | /** | |
468 | * i40evf_setup_tx_descriptors - Allocate the Tx descriptors | |
469 | * @tx_ring: the tx ring to set up | |
470 | * | |
471 | * Return 0 on success, negative on error | |
472 | **/ | |
473 | int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
474 | { | |
475 | struct device *dev = tx_ring->dev; | |
476 | int bi_size; | |
477 | ||
478 | if (!dev) | |
479 | return -ENOMEM; | |
480 | ||
481 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
482 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
483 | if (!tx_ring->tx_bi) | |
484 | goto err; | |
485 | ||
486 | /* round up to nearest 4K */ | |
487 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
1943d8ba JB |
488 | /* add u32 for head writeback, align after this takes care of |
489 | * guaranteeing this is at least one cache line in size | |
490 | */ | |
491 | tx_ring->size += sizeof(u32); | |
7f12ad74 GR |
492 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
493 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
494 | &tx_ring->dma, GFP_KERNEL); | |
495 | if (!tx_ring->desc) { | |
496 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
497 | tx_ring->size); | |
498 | goto err; | |
499 | } | |
500 | ||
501 | tx_ring->next_to_use = 0; | |
502 | tx_ring->next_to_clean = 0; | |
503 | return 0; | |
504 | ||
505 | err: | |
506 | kfree(tx_ring->tx_bi); | |
507 | tx_ring->tx_bi = NULL; | |
508 | return -ENOMEM; | |
509 | } | |
510 | ||
511 | /** | |
512 | * i40evf_clean_rx_ring - Free Rx buffers | |
513 | * @rx_ring: ring to be cleaned | |
514 | **/ | |
515 | void i40evf_clean_rx_ring(struct i40e_ring *rx_ring) | |
516 | { | |
517 | struct device *dev = rx_ring->dev; | |
518 | struct i40e_rx_buffer *rx_bi; | |
519 | unsigned long bi_size; | |
520 | u16 i; | |
521 | ||
522 | /* ring already cleared, nothing to do */ | |
523 | if (!rx_ring->rx_bi) | |
524 | return; | |
525 | ||
526 | /* Free all the Rx ring sk_buffs */ | |
527 | for (i = 0; i < rx_ring->count; i++) { | |
528 | rx_bi = &rx_ring->rx_bi[i]; | |
529 | if (rx_bi->dma) { | |
530 | dma_unmap_single(dev, | |
531 | rx_bi->dma, | |
532 | rx_ring->rx_buf_len, | |
533 | DMA_FROM_DEVICE); | |
534 | rx_bi->dma = 0; | |
535 | } | |
536 | if (rx_bi->skb) { | |
537 | dev_kfree_skb(rx_bi->skb); | |
538 | rx_bi->skb = NULL; | |
539 | } | |
540 | if (rx_bi->page) { | |
541 | if (rx_bi->page_dma) { | |
542 | dma_unmap_page(dev, | |
543 | rx_bi->page_dma, | |
544 | PAGE_SIZE / 2, | |
545 | DMA_FROM_DEVICE); | |
546 | rx_bi->page_dma = 0; | |
547 | } | |
548 | __free_page(rx_bi->page); | |
549 | rx_bi->page = NULL; | |
550 | rx_bi->page_offset = 0; | |
551 | } | |
552 | } | |
553 | ||
554 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
555 | memset(rx_ring->rx_bi, 0, bi_size); | |
556 | ||
557 | /* Zero out the descriptor ring */ | |
558 | memset(rx_ring->desc, 0, rx_ring->size); | |
559 | ||
560 | rx_ring->next_to_clean = 0; | |
561 | rx_ring->next_to_use = 0; | |
562 | } | |
563 | ||
564 | /** | |
565 | * i40evf_free_rx_resources - Free Rx resources | |
566 | * @rx_ring: ring to clean the resources from | |
567 | * | |
568 | * Free all receive software resources | |
569 | **/ | |
570 | void i40evf_free_rx_resources(struct i40e_ring *rx_ring) | |
571 | { | |
572 | i40evf_clean_rx_ring(rx_ring); | |
573 | kfree(rx_ring->rx_bi); | |
574 | rx_ring->rx_bi = NULL; | |
575 | ||
576 | if (rx_ring->desc) { | |
577 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
578 | rx_ring->desc, rx_ring->dma); | |
579 | rx_ring->desc = NULL; | |
580 | } | |
581 | } | |
582 | ||
583 | /** | |
584 | * i40evf_setup_rx_descriptors - Allocate Rx descriptors | |
585 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
586 | * | |
587 | * Returns 0 on success, negative on failure | |
588 | **/ | |
589 | int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
590 | { | |
591 | struct device *dev = rx_ring->dev; | |
592 | int bi_size; | |
593 | ||
594 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
595 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
596 | if (!rx_ring->rx_bi) | |
597 | goto err; | |
598 | ||
599 | /* Round up to nearest 4K */ | |
600 | rx_ring->size = ring_is_16byte_desc_enabled(rx_ring) | |
601 | ? rx_ring->count * sizeof(union i40e_16byte_rx_desc) | |
602 | : rx_ring->count * sizeof(union i40e_32byte_rx_desc); | |
603 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
604 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
605 | &rx_ring->dma, GFP_KERNEL); | |
606 | ||
607 | if (!rx_ring->desc) { | |
608 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
609 | rx_ring->size); | |
610 | goto err; | |
611 | } | |
612 | ||
613 | rx_ring->next_to_clean = 0; | |
614 | rx_ring->next_to_use = 0; | |
615 | ||
616 | return 0; | |
617 | err: | |
618 | kfree(rx_ring->rx_bi); | |
619 | rx_ring->rx_bi = NULL; | |
620 | return -ENOMEM; | |
621 | } | |
622 | ||
623 | /** | |
624 | * i40e_release_rx_desc - Store the new tail and head values | |
625 | * @rx_ring: ring to bump | |
626 | * @val: new head index | |
627 | **/ | |
628 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
629 | { | |
630 | rx_ring->next_to_use = val; | |
631 | /* Force memory writes to complete before letting h/w | |
632 | * know there are new descriptors to fetch. (Only | |
633 | * applicable for weak-ordered memory model archs, | |
634 | * such as IA-64). | |
635 | */ | |
636 | wmb(); | |
637 | writel(val, rx_ring->tail); | |
638 | } | |
639 | ||
640 | /** | |
641 | * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split | |
642 | * @rx_ring: ring to place buffers on | |
643 | * @cleaned_count: number of buffers to replace | |
644 | **/ | |
645 | void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) | |
646 | { | |
647 | u16 i = rx_ring->next_to_use; | |
648 | union i40e_rx_desc *rx_desc; | |
649 | struct i40e_rx_buffer *bi; | |
650 | struct sk_buff *skb; | |
651 | ||
652 | /* do nothing if no valid netdev defined */ | |
653 | if (!rx_ring->netdev || !cleaned_count) | |
654 | return; | |
655 | ||
656 | while (cleaned_count--) { | |
657 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
658 | bi = &rx_ring->rx_bi[i]; | |
659 | skb = bi->skb; | |
660 | ||
661 | if (!skb) { | |
662 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
663 | rx_ring->rx_buf_len); | |
664 | if (!skb) { | |
665 | rx_ring->rx_stats.alloc_buff_failed++; | |
666 | goto no_buffers; | |
667 | } | |
668 | /* initialize queue mapping */ | |
669 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
670 | bi->skb = skb; | |
671 | } | |
672 | ||
673 | if (!bi->dma) { | |
674 | bi->dma = dma_map_single(rx_ring->dev, | |
675 | skb->data, | |
676 | rx_ring->rx_buf_len, | |
677 | DMA_FROM_DEVICE); | |
678 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { | |
679 | rx_ring->rx_stats.alloc_buff_failed++; | |
680 | bi->dma = 0; | |
681 | goto no_buffers; | |
682 | } | |
683 | } | |
684 | ||
685 | if (ring_is_ps_enabled(rx_ring)) { | |
686 | if (!bi->page) { | |
687 | bi->page = alloc_page(GFP_ATOMIC); | |
688 | if (!bi->page) { | |
689 | rx_ring->rx_stats.alloc_page_failed++; | |
690 | goto no_buffers; | |
691 | } | |
692 | } | |
693 | ||
694 | if (!bi->page_dma) { | |
695 | /* use a half page if we're re-using */ | |
696 | bi->page_offset ^= PAGE_SIZE / 2; | |
697 | bi->page_dma = dma_map_page(rx_ring->dev, | |
698 | bi->page, | |
699 | bi->page_offset, | |
700 | PAGE_SIZE / 2, | |
701 | DMA_FROM_DEVICE); | |
702 | if (dma_mapping_error(rx_ring->dev, | |
703 | bi->page_dma)) { | |
704 | rx_ring->rx_stats.alloc_page_failed++; | |
705 | bi->page_dma = 0; | |
706 | goto no_buffers; | |
707 | } | |
708 | } | |
709 | ||
710 | /* Refresh the desc even if buffer_addrs didn't change | |
711 | * because each write-back erases this info. | |
712 | */ | |
713 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); | |
714 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
715 | } else { | |
716 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); | |
717 | rx_desc->read.hdr_addr = 0; | |
718 | } | |
719 | i++; | |
720 | if (i == rx_ring->count) | |
721 | i = 0; | |
722 | } | |
723 | ||
724 | no_buffers: | |
725 | if (rx_ring->next_to_use != i) | |
726 | i40e_release_rx_desc(rx_ring, i); | |
727 | } | |
728 | ||
729 | /** | |
730 | * i40e_receive_skb - Send a completed packet up the stack | |
731 | * @rx_ring: rx ring in play | |
732 | * @skb: packet to send up | |
733 | * @vlan_tag: vlan tag for packet | |
734 | **/ | |
735 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
736 | struct sk_buff *skb, u16 vlan_tag) | |
737 | { | |
738 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
739 | struct i40e_vsi *vsi = rx_ring->vsi; | |
740 | u64 flags = vsi->back->flags; | |
741 | ||
742 | if (vlan_tag & VLAN_VID_MASK) | |
743 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
744 | ||
745 | if (flags & I40E_FLAG_IN_NETPOLL) | |
746 | netif_rx(skb); | |
747 | else | |
748 | napi_gro_receive(&q_vector->napi, skb); | |
749 | } | |
750 | ||
751 | /** | |
752 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
753 | * @vsi: the VSI we care about | |
754 | * @skb: skb currently being received and modified | |
755 | * @rx_status: status value of last descriptor in packet | |
756 | * @rx_error: error value of last descriptor in packet | |
757 | * @rx_ptype: ptype value of last descriptor in packet | |
758 | **/ | |
759 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
760 | struct sk_buff *skb, | |
761 | u32 rx_status, | |
762 | u32 rx_error, | |
763 | u16 rx_ptype) | |
764 | { | |
8a3c91cc JB |
765 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype); |
766 | bool ipv4 = false, ipv6 = false; | |
7f12ad74 GR |
767 | bool ipv4_tunnel, ipv6_tunnel; |
768 | __wsum rx_udp_csum; | |
7f12ad74 | 769 | struct iphdr *iph; |
8a3c91cc | 770 | __sum16 csum; |
7f12ad74 GR |
771 | |
772 | ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) && | |
773 | (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4); | |
774 | ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) && | |
775 | (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4); | |
776 | ||
7f12ad74 GR |
777 | skb->ip_summed = CHECKSUM_NONE; |
778 | ||
779 | /* Rx csum enabled and ip headers found? */ | |
8a3c91cc JB |
780 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
781 | return; | |
782 | ||
783 | /* did the hardware decode the packet and checksum? */ | |
784 | if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT))) | |
785 | return; | |
786 | ||
787 | /* both known and outer_ip must be set for the below code to work */ | |
788 | if (!(decoded.known && decoded.outer_ip)) | |
7f12ad74 GR |
789 | return; |
790 | ||
8a3c91cc JB |
791 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && |
792 | decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4) | |
793 | ipv4 = true; | |
794 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
795 | decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6) | |
796 | ipv6 = true; | |
797 | ||
798 | if (ipv4 && | |
799 | (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) | | |
800 | (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
801 | goto checksum_fail; | |
802 | ||
ddf1d0d7 | 803 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 804 | if (ipv6 && |
8a3c91cc JB |
805 | rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
806 | /* don't increment checksum err here, non-fatal err */ | |
7f12ad74 GR |
807 | return; |
808 | ||
8a3c91cc JB |
809 | /* there was some L4 error, count error and punt packet to the stack */ |
810 | if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)) | |
811 | goto checksum_fail; | |
812 | ||
813 | /* handle packets that were not able to be checksummed due | |
814 | * to arrival speed, in this case the stack can compute | |
815 | * the csum. | |
816 | */ | |
817 | if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT)) | |
7f12ad74 | 818 | return; |
7f12ad74 | 819 | |
8a3c91cc JB |
820 | /* If VXLAN traffic has an outer UDPv4 checksum we need to check |
821 | * it in the driver, hardware does not do it for us. | |
822 | * Since L3L4P bit was set we assume a valid IHL value (>=5) | |
823 | * so the total length of IPv4 header is IHL*4 bytes | |
824 | * The UDP_0 bit *may* bet set if the *inner* header is UDP | |
825 | */ | |
7f12ad74 | 826 | if (ipv4_tunnel && |
8a3c91cc | 827 | (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) && |
7f12ad74 | 828 | !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) { |
7f12ad74 GR |
829 | skb->transport_header = skb->mac_header + |
830 | sizeof(struct ethhdr) + | |
831 | (ip_hdr(skb)->ihl * 4); | |
832 | ||
833 | /* Add 4 bytes for VLAN tagged packets */ | |
834 | skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) || | |
835 | skb->protocol == htons(ETH_P_8021AD)) | |
836 | ? VLAN_HLEN : 0; | |
837 | ||
838 | rx_udp_csum = udp_csum(skb); | |
839 | iph = ip_hdr(skb); | |
840 | csum = csum_tcpudp_magic( | |
841 | iph->saddr, iph->daddr, | |
842 | (skb->len - skb_transport_offset(skb)), | |
843 | IPPROTO_UDP, rx_udp_csum); | |
844 | ||
8a3c91cc JB |
845 | if (udp_hdr(skb)->check != csum) |
846 | goto checksum_fail; | |
7f12ad74 GR |
847 | } |
848 | ||
849 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
407fa085 | 850 | skb->csum_level = ipv4_tunnel || ipv6_tunnel; |
8a3c91cc JB |
851 | |
852 | return; | |
853 | ||
854 | checksum_fail: | |
855 | vsi->back->hw_csum_rx_error++; | |
7f12ad74 GR |
856 | } |
857 | ||
858 | /** | |
859 | * i40e_rx_hash - returns the hash value from the Rx descriptor | |
860 | * @ring: descriptor ring | |
861 | * @rx_desc: specific descriptor | |
862 | **/ | |
863 | static inline u32 i40e_rx_hash(struct i40e_ring *ring, | |
864 | union i40e_rx_desc *rx_desc) | |
865 | { | |
866 | const __le64 rss_mask = | |
867 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << | |
868 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
869 | ||
870 | if ((ring->netdev->features & NETIF_F_RXHASH) && | |
871 | (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) | |
872 | return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
873 | else | |
874 | return 0; | |
875 | } | |
876 | ||
206812b5 JB |
877 | /** |
878 | * i40e_ptype_to_hash - get a hash type | |
879 | * @ptype: the ptype value from the descriptor | |
880 | * | |
881 | * Returns a hash type to be used by skb_set_hash | |
882 | **/ | |
883 | static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype) | |
884 | { | |
885 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
886 | ||
887 | if (!decoded.known) | |
888 | return PKT_HASH_TYPE_NONE; | |
889 | ||
890 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
891 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
892 | return PKT_HASH_TYPE_L4; | |
893 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
894 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
895 | return PKT_HASH_TYPE_L3; | |
896 | else | |
897 | return PKT_HASH_TYPE_L2; | |
898 | } | |
899 | ||
7f12ad74 GR |
900 | /** |
901 | * i40e_clean_rx_irq - Reclaim resources after receive completes | |
902 | * @rx_ring: rx ring to clean | |
903 | * @budget: how many cleans we're allowed | |
904 | * | |
905 | * Returns true if there's any budget left (e.g. the clean is finished) | |
906 | **/ | |
907 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) | |
908 | { | |
909 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
910 | u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo; | |
911 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); | |
912 | const int current_node = numa_node_id(); | |
913 | struct i40e_vsi *vsi = rx_ring->vsi; | |
914 | u16 i = rx_ring->next_to_clean; | |
915 | union i40e_rx_desc *rx_desc; | |
916 | u32 rx_error, rx_status; | |
206812b5 | 917 | u8 rx_ptype; |
7f12ad74 | 918 | u64 qword; |
7f12ad74 GR |
919 | |
920 | rx_desc = I40E_RX_DESC(rx_ring, i); | |
921 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
af1a2a9c JB |
922 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> |
923 | I40E_RXD_QW1_STATUS_SHIFT; | |
7f12ad74 GR |
924 | |
925 | while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) { | |
926 | union i40e_rx_desc *next_rxd; | |
927 | struct i40e_rx_buffer *rx_bi; | |
928 | struct sk_buff *skb; | |
929 | u16 vlan_tag; | |
930 | rx_bi = &rx_ring->rx_bi[i]; | |
931 | skb = rx_bi->skb; | |
932 | prefetch(skb->data); | |
933 | ||
934 | rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
935 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
936 | rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >> | |
937 | I40E_RXD_QW1_LENGTH_HBUF_SHIFT; | |
938 | rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >> | |
939 | I40E_RXD_QW1_LENGTH_SPH_SHIFT; | |
940 | ||
941 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
942 | I40E_RXD_QW1_ERROR_SHIFT; | |
943 | rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT); | |
944 | rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT); | |
945 | ||
946 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
947 | I40E_RXD_QW1_PTYPE_SHIFT; | |
948 | rx_bi->skb = NULL; | |
949 | ||
950 | /* This memory barrier is needed to keep us from reading | |
951 | * any other fields out of the rx_desc until we know the | |
952 | * STATUS_DD bit is set | |
953 | */ | |
954 | rmb(); | |
955 | ||
956 | /* Get the header and possibly the whole packet | |
957 | * If this is an skb from previous receive dma will be 0 | |
958 | */ | |
959 | if (rx_bi->dma) { | |
960 | u16 len; | |
961 | ||
962 | if (rx_hbo) | |
963 | len = I40E_RX_HDR_SIZE; | |
964 | else if (rx_sph) | |
965 | len = rx_header_len; | |
966 | else if (rx_packet_len) | |
967 | len = rx_packet_len; /* 1buf/no split found */ | |
968 | else | |
969 | len = rx_header_len; /* split always mode */ | |
970 | ||
971 | skb_put(skb, len); | |
972 | dma_unmap_single(rx_ring->dev, | |
973 | rx_bi->dma, | |
974 | rx_ring->rx_buf_len, | |
975 | DMA_FROM_DEVICE); | |
976 | rx_bi->dma = 0; | |
977 | } | |
978 | ||
979 | /* Get the rest of the data if this was a header split */ | |
980 | if (ring_is_ps_enabled(rx_ring) && rx_packet_len) { | |
981 | ||
982 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
983 | rx_bi->page, | |
984 | rx_bi->page_offset, | |
985 | rx_packet_len); | |
986 | ||
987 | skb->len += rx_packet_len; | |
988 | skb->data_len += rx_packet_len; | |
989 | skb->truesize += rx_packet_len; | |
990 | ||
991 | if ((page_count(rx_bi->page) == 1) && | |
992 | (page_to_nid(rx_bi->page) == current_node)) | |
993 | get_page(rx_bi->page); | |
994 | else | |
995 | rx_bi->page = NULL; | |
996 | ||
997 | dma_unmap_page(rx_ring->dev, | |
998 | rx_bi->page_dma, | |
999 | PAGE_SIZE / 2, | |
1000 | DMA_FROM_DEVICE); | |
1001 | rx_bi->page_dma = 0; | |
1002 | } | |
1003 | I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd); | |
1004 | ||
1005 | if (unlikely( | |
1006 | !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) { | |
1007 | struct i40e_rx_buffer *next_buffer; | |
1008 | ||
1009 | next_buffer = &rx_ring->rx_bi[i]; | |
1010 | ||
1011 | if (ring_is_ps_enabled(rx_ring)) { | |
1012 | rx_bi->skb = next_buffer->skb; | |
1013 | rx_bi->dma = next_buffer->dma; | |
1014 | next_buffer->skb = skb; | |
1015 | next_buffer->dma = 0; | |
1016 | } | |
1017 | rx_ring->rx_stats.non_eop_descs++; | |
1018 | goto next_desc; | |
1019 | } | |
1020 | ||
1021 | /* ERR_MASK will only have valid bits if EOP set */ | |
1022 | if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) { | |
1023 | dev_kfree_skb_any(skb); | |
8a3c91cc JB |
1024 | /* TODO: shouldn't we increment a counter indicating the |
1025 | * drop? | |
1026 | */ | |
7f12ad74 GR |
1027 | goto next_desc; |
1028 | } | |
1029 | ||
206812b5 JB |
1030 | skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc), |
1031 | i40e_ptype_to_hash(rx_ptype)); | |
7f12ad74 GR |
1032 | /* probably a little skewed due to removing CRC */ |
1033 | total_rx_bytes += skb->len; | |
1034 | total_rx_packets++; | |
1035 | ||
1036 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
1037 | ||
1038 | i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); | |
1039 | ||
1040 | vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) | |
1041 | ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) | |
1042 | : 0; | |
1043 | i40e_receive_skb(rx_ring, skb, vlan_tag); | |
1044 | ||
1045 | rx_ring->netdev->last_rx = jiffies; | |
1046 | budget--; | |
1047 | next_desc: | |
1048 | rx_desc->wb.qword1.status_error_len = 0; | |
1049 | if (!budget) | |
1050 | break; | |
1051 | ||
1052 | cleaned_count++; | |
1053 | /* return some buffers to hardware, one at a time is too slow */ | |
1054 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
1055 | i40evf_alloc_rx_buffers(rx_ring, cleaned_count); | |
1056 | cleaned_count = 0; | |
1057 | } | |
1058 | ||
1059 | /* use prefetched values */ | |
1060 | rx_desc = next_rxd; | |
1061 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
1062 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
1063 | I40E_RXD_QW1_STATUS_SHIFT; | |
1064 | } | |
1065 | ||
1066 | rx_ring->next_to_clean = i; | |
1067 | u64_stats_update_begin(&rx_ring->syncp); | |
1068 | rx_ring->stats.packets += total_rx_packets; | |
1069 | rx_ring->stats.bytes += total_rx_bytes; | |
1070 | u64_stats_update_end(&rx_ring->syncp); | |
1071 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
1072 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1073 | ||
1074 | if (cleaned_count) | |
1075 | i40evf_alloc_rx_buffers(rx_ring, cleaned_count); | |
1076 | ||
1077 | return budget > 0; | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1082 | * @napi: napi struct with our devices info in it | |
1083 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1084 | * | |
1085 | * This function will clean all queues associated with a q_vector. | |
1086 | * | |
1087 | * Returns the amount of work done | |
1088 | **/ | |
1089 | int i40evf_napi_poll(struct napi_struct *napi, int budget) | |
1090 | { | |
1091 | struct i40e_q_vector *q_vector = | |
1092 | container_of(napi, struct i40e_q_vector, napi); | |
1093 | struct i40e_vsi *vsi = q_vector->vsi; | |
1094 | struct i40e_ring *ring; | |
1095 | bool clean_complete = true; | |
c29af37f | 1096 | bool arm_wb = false; |
7f12ad74 GR |
1097 | int budget_per_ring; |
1098 | ||
1099 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
1100 | napi_complete(napi); | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | /* Since the actual Tx work is minimal, we can give the Tx a larger | |
1105 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1106 | */ | |
c29af37f | 1107 | i40e_for_each_ring(ring, q_vector->tx) { |
7f12ad74 | 1108 | clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit); |
c29af37f ASJ |
1109 | arm_wb |= ring->arm_wb; |
1110 | } | |
7f12ad74 GR |
1111 | |
1112 | /* We attempt to distribute budget to each Rx queue fairly, but don't | |
1113 | * allow the budget to go below 1 because that would exit polling early. | |
1114 | */ | |
1115 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
1116 | ||
1117 | i40e_for_each_ring(ring, q_vector->rx) | |
1118 | clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring); | |
1119 | ||
1120 | /* If work not completed, return budget and polling will return */ | |
c29af37f ASJ |
1121 | if (!clean_complete) { |
1122 | if (arm_wb) | |
1123 | i40e_force_wb(vsi, q_vector); | |
7f12ad74 | 1124 | return budget; |
c29af37f | 1125 | } |
7f12ad74 GR |
1126 | |
1127 | /* Work is done so exit the polling mode and re-enable the interrupt */ | |
1128 | napi_complete(napi); | |
1129 | if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) || | |
1130 | ITR_IS_DYNAMIC(vsi->tx_itr_setting)) | |
1131 | i40e_update_dynamic_itr(q_vector); | |
1132 | ||
1133 | if (!test_bit(__I40E_DOWN, &vsi->state)) | |
1134 | i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx); | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | /** | |
1140 | * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW | |
1141 | * @skb: send buffer | |
1142 | * @tx_ring: ring to send buffer on | |
1143 | * @flags: the tx flags to be set | |
1144 | * | |
1145 | * Checks the skb and set up correspondingly several generic transmit flags | |
1146 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
1147 | * | |
1148 | * Returns error code indicate the frame should be dropped upon error and the | |
1149 | * otherwise returns 0 to indicate the flags has been set properly. | |
1150 | **/ | |
1151 | static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, | |
1152 | struct i40e_ring *tx_ring, | |
1153 | u32 *flags) | |
1154 | { | |
1155 | __be16 protocol = skb->protocol; | |
1156 | u32 tx_flags = 0; | |
1157 | ||
1158 | /* if we have a HW VLAN tag being added, default to the HW one */ | |
df8a39de JP |
1159 | if (skb_vlan_tag_present(skb)) { |
1160 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
7f12ad74 GR |
1161 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
1162 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
1163 | } else if (protocol == htons(ETH_P_8021Q)) { | |
1164 | struct vlan_hdr *vhdr, _vhdr; | |
1165 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
1166 | if (!vhdr) | |
1167 | return -EINVAL; | |
1168 | ||
1169 | protocol = vhdr->h_vlan_encapsulated_proto; | |
1170 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
1171 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
1172 | } | |
1173 | ||
1174 | *flags = tx_flags; | |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * i40e_tso - set up the tso context descriptor | |
1180 | * @tx_ring: ptr to the ring to send | |
1181 | * @skb: ptr to the skb we're sending | |
1182 | * @tx_flags: the collected send information | |
1183 | * @protocol: the send protocol | |
1184 | * @hdr_len: ptr to the size of the packet header | |
1185 | * @cd_tunneling: ptr to context descriptor bits | |
1186 | * | |
1187 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
1188 | **/ | |
1189 | static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
1190 | u32 tx_flags, __be16 protocol, u8 *hdr_len, | |
1191 | u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling) | |
1192 | { | |
1193 | u32 cd_cmd, cd_tso_len, cd_mss; | |
fe6d4aa4 | 1194 | struct ipv6hdr *ipv6h; |
7f12ad74 GR |
1195 | struct tcphdr *tcph; |
1196 | struct iphdr *iph; | |
1197 | u32 l4len; | |
1198 | int err; | |
7f12ad74 GR |
1199 | |
1200 | if (!skb_is_gso(skb)) | |
1201 | return 0; | |
1202 | ||
fe6d4aa4 FR |
1203 | err = skb_cow_head(skb, 0); |
1204 | if (err < 0) | |
1205 | return err; | |
7f12ad74 GR |
1206 | |
1207 | if (protocol == htons(ETH_P_IP)) { | |
1208 | iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb); | |
1209 | tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); | |
1210 | iph->tot_len = 0; | |
1211 | iph->check = 0; | |
1212 | tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, | |
1213 | 0, IPPROTO_TCP, 0); | |
1214 | } else if (skb_is_gso_v6(skb)) { | |
1215 | ||
1216 | ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) | |
1217 | : ipv6_hdr(skb); | |
1218 | tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); | |
1219 | ipv6h->payload_len = 0; | |
1220 | tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, | |
1221 | 0, IPPROTO_TCP, 0); | |
1222 | } | |
1223 | ||
1224 | l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); | |
1225 | *hdr_len = (skb->encapsulation | |
1226 | ? (skb_inner_transport_header(skb) - skb->data) | |
1227 | : skb_transport_offset(skb)) + l4len; | |
1228 | ||
1229 | /* find the field values */ | |
1230 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
1231 | cd_tso_len = skb->len - *hdr_len; | |
1232 | cd_mss = skb_shinfo(skb)->gso_size; | |
1233 | *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | | |
1234 | ((u64)cd_tso_len << | |
1235 | I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
1236 | ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
1237 | return 1; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
1242 | * @skb: send buffer | |
1243 | * @tx_flags: Tx flags currently set | |
1244 | * @td_cmd: Tx descriptor command bits to set | |
1245 | * @td_offset: Tx descriptor header offsets to set | |
1246 | * @cd_tunneling: ptr to context desc bits | |
1247 | **/ | |
1248 | static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags, | |
1249 | u32 *td_cmd, u32 *td_offset, | |
1250 | struct i40e_ring *tx_ring, | |
1251 | u32 *cd_tunneling) | |
1252 | { | |
1253 | struct ipv6hdr *this_ipv6_hdr; | |
1254 | unsigned int this_tcp_hdrlen; | |
1255 | struct iphdr *this_ip_hdr; | |
1256 | u32 network_hdr_len; | |
1257 | u8 l4_hdr = 0; | |
1258 | ||
1259 | if (skb->encapsulation) { | |
1260 | network_hdr_len = skb_inner_network_header_len(skb); | |
1261 | this_ip_hdr = inner_ip_hdr(skb); | |
1262 | this_ipv6_hdr = inner_ipv6_hdr(skb); | |
1263 | this_tcp_hdrlen = inner_tcp_hdrlen(skb); | |
1264 | ||
1265 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
1266 | ||
1267 | if (tx_flags & I40E_TX_FLAGS_TSO) { | |
1268 | *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4; | |
1269 | ip_hdr(skb)->check = 0; | |
1270 | } else { | |
1271 | *cd_tunneling |= | |
1272 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1273 | } | |
1274 | } else if (tx_flags & I40E_TX_FLAGS_IPV6) { | |
1275 | if (tx_flags & I40E_TX_FLAGS_TSO) { | |
1276 | *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; | |
1277 | ip_hdr(skb)->check = 0; | |
1278 | } else { | |
1279 | *cd_tunneling |= | |
1280 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | /* Now set the ctx descriptor fields */ | |
1285 | *cd_tunneling |= (skb_network_header_len(skb) >> 2) << | |
1286 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT | | |
1287 | I40E_TXD_CTX_UDP_TUNNELING | | |
1288 | ((skb_inner_network_offset(skb) - | |
1289 | skb_transport_offset(skb)) >> 1) << | |
1290 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
1291 | ||
1292 | } else { | |
1293 | network_hdr_len = skb_network_header_len(skb); | |
1294 | this_ip_hdr = ip_hdr(skb); | |
1295 | this_ipv6_hdr = ipv6_hdr(skb); | |
1296 | this_tcp_hdrlen = tcp_hdrlen(skb); | |
1297 | } | |
1298 | ||
1299 | /* Enable IP checksum offloads */ | |
1300 | if (tx_flags & I40E_TX_FLAGS_IPV4) { | |
1301 | l4_hdr = this_ip_hdr->protocol; | |
1302 | /* the stack computes the IP header already, the only time we | |
1303 | * need the hardware to recompute it is in the case of TSO. | |
1304 | */ | |
1305 | if (tx_flags & I40E_TX_FLAGS_TSO) { | |
1306 | *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM; | |
1307 | this_ip_hdr->check = 0; | |
1308 | } else { | |
1309 | *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4; | |
1310 | } | |
1311 | /* Now set the td_offset for IP header length */ | |
1312 | *td_offset = (network_hdr_len >> 2) << | |
1313 | I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
1314 | } else if (tx_flags & I40E_TX_FLAGS_IPV6) { | |
1315 | l4_hdr = this_ipv6_hdr->nexthdr; | |
1316 | *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; | |
1317 | /* Now set the td_offset for IP header length */ | |
1318 | *td_offset = (network_hdr_len >> 2) << | |
1319 | I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
1320 | } | |
1321 | /* words in MACLEN + dwords in IPLEN + dwords in L4Len */ | |
1322 | *td_offset |= (skb_network_offset(skb) >> 1) << | |
1323 | I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
1324 | ||
1325 | /* Enable L4 checksum offloads */ | |
1326 | switch (l4_hdr) { | |
1327 | case IPPROTO_TCP: | |
1328 | /* enable checksum offloads */ | |
1329 | *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; | |
1330 | *td_offset |= (this_tcp_hdrlen >> 2) << | |
1331 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
1332 | break; | |
1333 | case IPPROTO_SCTP: | |
1334 | /* enable SCTP checksum offload */ | |
1335 | *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; | |
1336 | *td_offset |= (sizeof(struct sctphdr) >> 2) << | |
1337 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
1338 | break; | |
1339 | case IPPROTO_UDP: | |
1340 | /* enable UDP checksum offload */ | |
1341 | *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; | |
1342 | *td_offset |= (sizeof(struct udphdr) >> 2) << | |
1343 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
1344 | break; | |
1345 | default: | |
1346 | break; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | /** | |
1351 | * i40e_create_tx_ctx Build the Tx context descriptor | |
1352 | * @tx_ring: ring to create the descriptor on | |
1353 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
1354 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
1355 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
1356 | **/ | |
1357 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
1358 | const u64 cd_type_cmd_tso_mss, | |
1359 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
1360 | { | |
1361 | struct i40e_tx_context_desc *context_desc; | |
1362 | int i = tx_ring->next_to_use; | |
1363 | ||
ff40dd5d JB |
1364 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
1365 | !cd_tunneling && !cd_l2tag2) | |
7f12ad74 GR |
1366 | return; |
1367 | ||
1368 | /* grab the next descriptor */ | |
1369 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); | |
1370 | ||
1371 | i++; | |
1372 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
1373 | ||
1374 | /* cpu_to_le32 and assign to struct fields */ | |
1375 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
1376 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 1377 | context_desc->rsvd = cpu_to_le16(0); |
7f12ad74 GR |
1378 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
1379 | } | |
1380 | ||
1381 | /** | |
1382 | * i40e_tx_map - Build the Tx descriptor | |
1383 | * @tx_ring: ring to send buffer on | |
1384 | * @skb: send buffer | |
1385 | * @first: first buffer info buffer to use | |
1386 | * @tx_flags: collected send information | |
1387 | * @hdr_len: size of the packet header | |
1388 | * @td_cmd: the command field in the descriptor | |
1389 | * @td_offset: offset for checksum or crc | |
1390 | **/ | |
1391 | static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, | |
1392 | struct i40e_tx_buffer *first, u32 tx_flags, | |
1393 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
1394 | { | |
1395 | unsigned int data_len = skb->data_len; | |
1396 | unsigned int size = skb_headlen(skb); | |
1397 | struct skb_frag_struct *frag; | |
1398 | struct i40e_tx_buffer *tx_bi; | |
1399 | struct i40e_tx_desc *tx_desc; | |
1400 | u16 i = tx_ring->next_to_use; | |
1401 | u32 td_tag = 0; | |
1402 | dma_addr_t dma; | |
1403 | u16 gso_segs; | |
1404 | ||
1405 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { | |
1406 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
1407 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
1408 | I40E_TX_FLAGS_VLAN_SHIFT; | |
1409 | } | |
1410 | ||
1411 | if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) | |
1412 | gso_segs = skb_shinfo(skb)->gso_segs; | |
1413 | else | |
1414 | gso_segs = 1; | |
1415 | ||
1416 | /* multiply data chunks by size of headers */ | |
1417 | first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); | |
1418 | first->gso_segs = gso_segs; | |
1419 | first->skb = skb; | |
1420 | first->tx_flags = tx_flags; | |
1421 | ||
1422 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
1423 | ||
1424 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
1425 | tx_bi = first; | |
1426 | ||
1427 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
1428 | if (dma_mapping_error(tx_ring->dev, dma)) | |
1429 | goto dma_error; | |
1430 | ||
1431 | /* record length, and DMA address */ | |
1432 | dma_unmap_len_set(tx_bi, len, size); | |
1433 | dma_unmap_addr_set(tx_bi, dma, dma); | |
1434 | ||
1435 | tx_desc->buffer_addr = cpu_to_le64(dma); | |
1436 | ||
1437 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
1438 | tx_desc->cmd_type_offset_bsz = | |
1439 | build_ctob(td_cmd, td_offset, | |
1440 | I40E_MAX_DATA_PER_TXD, td_tag); | |
1441 | ||
1442 | tx_desc++; | |
1443 | i++; | |
1444 | if (i == tx_ring->count) { | |
1445 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
1446 | i = 0; | |
1447 | } | |
1448 | ||
1449 | dma += I40E_MAX_DATA_PER_TXD; | |
1450 | size -= I40E_MAX_DATA_PER_TXD; | |
1451 | ||
1452 | tx_desc->buffer_addr = cpu_to_le64(dma); | |
1453 | } | |
1454 | ||
1455 | if (likely(!data_len)) | |
1456 | break; | |
1457 | ||
1458 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, | |
1459 | size, td_tag); | |
1460 | ||
1461 | tx_desc++; | |
1462 | i++; | |
1463 | if (i == tx_ring->count) { | |
1464 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
1465 | i = 0; | |
1466 | } | |
1467 | ||
1468 | size = skb_frag_size(frag); | |
1469 | data_len -= size; | |
1470 | ||
1471 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, | |
1472 | DMA_TO_DEVICE); | |
1473 | ||
1474 | tx_bi = &tx_ring->tx_bi[i]; | |
1475 | } | |
1476 | ||
1943d8ba JB |
1477 | /* Place RS bit on last descriptor of any packet that spans across the |
1478 | * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline. | |
1479 | */ | |
1480 | #define WB_STRIDE 0x3 | |
1481 | if (((i & WB_STRIDE) != WB_STRIDE) && | |
1482 | (first <= &tx_ring->tx_bi[i]) && | |
1483 | (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) { | |
1484 | tx_desc->cmd_type_offset_bsz = | |
1485 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
1486 | cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP << | |
1487 | I40E_TXD_QW1_CMD_SHIFT); | |
1488 | } else { | |
1489 | tx_desc->cmd_type_offset_bsz = | |
1490 | build_ctob(td_cmd, td_offset, size, td_tag) | | |
1491 | cpu_to_le64((u64)I40E_TXD_CMD << | |
1492 | I40E_TXD_QW1_CMD_SHIFT); | |
1493 | } | |
7f12ad74 GR |
1494 | |
1495 | netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, | |
1496 | tx_ring->queue_index), | |
1497 | first->bytecount); | |
1498 | ||
1499 | /* set the timestamp */ | |
1500 | first->time_stamp = jiffies; | |
1501 | ||
1502 | /* Force memory writes to complete before letting h/w | |
1503 | * know there are new descriptors to fetch. (Only | |
1504 | * applicable for weak-ordered memory model archs, | |
1505 | * such as IA-64). | |
1506 | */ | |
1507 | wmb(); | |
1508 | ||
1509 | /* set next_to_watch value indicating a packet is present */ | |
1510 | first->next_to_watch = tx_desc; | |
1511 | ||
1512 | i++; | |
1513 | if (i == tx_ring->count) | |
1514 | i = 0; | |
1515 | ||
1516 | tx_ring->next_to_use = i; | |
1517 | ||
1518 | /* notify HW of packet */ | |
1519 | writel(i, tx_ring->tail); | |
1520 | ||
1521 | return; | |
1522 | ||
1523 | dma_error: | |
1524 | dev_info(tx_ring->dev, "TX DMA map failed\n"); | |
1525 | ||
1526 | /* clear dma mappings for failed tx_bi map */ | |
1527 | for (;;) { | |
1528 | tx_bi = &tx_ring->tx_bi[i]; | |
1529 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); | |
1530 | if (tx_bi == first) | |
1531 | break; | |
1532 | if (i == 0) | |
1533 | i = tx_ring->count; | |
1534 | i--; | |
1535 | } | |
1536 | ||
1537 | tx_ring->next_to_use = i; | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions | |
1542 | * @tx_ring: the ring to be checked | |
1543 | * @size: the size buffer we want to assure is available | |
1544 | * | |
1545 | * Returns -EBUSY if a stop is needed, else 0 | |
1546 | **/ | |
1547 | static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
1548 | { | |
1549 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1550 | /* Memory barrier before checking head and tail */ | |
1551 | smp_mb(); | |
1552 | ||
1553 | /* Check again in a case another CPU has just made room available. */ | |
1554 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
1555 | return -EBUSY; | |
1556 | ||
1557 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
1558 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1559 | ++tx_ring->tx_stats.restart_queue; | |
1560 | return 0; | |
1561 | } | |
1562 | ||
1563 | /** | |
1564 | * i40e_maybe_stop_tx - 1st level check for tx stop conditions | |
1565 | * @tx_ring: the ring to be checked | |
1566 | * @size: the size buffer we want to assure is available | |
1567 | * | |
1568 | * Returns 0 if stop is not needed | |
1569 | **/ | |
1570 | static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
1571 | { | |
1572 | if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) | |
1573 | return 0; | |
1574 | return __i40e_maybe_stop_tx(tx_ring, size); | |
1575 | } | |
1576 | ||
1577 | /** | |
1578 | * i40e_xmit_descriptor_count - calculate number of tx descriptors needed | |
1579 | * @skb: send buffer | |
1580 | * @tx_ring: ring to send buffer on | |
1581 | * | |
1582 | * Returns number of data descriptors needed for this skb. Returns 0 to indicate | |
1583 | * there is not enough descriptors available in this ring since we need at least | |
1584 | * one descriptor. | |
1585 | **/ | |
1586 | static int i40e_xmit_descriptor_count(struct sk_buff *skb, | |
1587 | struct i40e_ring *tx_ring) | |
1588 | { | |
7f12ad74 | 1589 | unsigned int f; |
7f12ad74 GR |
1590 | int count = 0; |
1591 | ||
1592 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
1593 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
be560521 | 1594 | * + 4 desc gap to avoid the cache line where head is, |
7f12ad74 GR |
1595 | * + 1 desc for context descriptor, |
1596 | * otherwise try next time | |
1597 | */ | |
7f12ad74 GR |
1598 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
1599 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
980093eb | 1600 | |
7f12ad74 | 1601 | count += TXD_USE_COUNT(skb_headlen(skb)); |
be560521 | 1602 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { |
7f12ad74 GR |
1603 | tx_ring->tx_stats.tx_busy++; |
1604 | return 0; | |
1605 | } | |
1606 | return count; | |
1607 | } | |
1608 | ||
1609 | /** | |
1610 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
1611 | * @skb: send buffer | |
1612 | * @tx_ring: ring to send buffer on | |
1613 | * | |
1614 | * Returns NETDEV_TX_OK if sent, else an error code | |
1615 | **/ | |
1616 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
1617 | struct i40e_ring *tx_ring) | |
1618 | { | |
1619 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
1620 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
1621 | struct i40e_tx_buffer *first; | |
1622 | u32 td_offset = 0; | |
1623 | u32 tx_flags = 0; | |
1624 | __be16 protocol; | |
1625 | u32 td_cmd = 0; | |
1626 | u8 hdr_len = 0; | |
1627 | int tso; | |
1628 | if (0 == i40e_xmit_descriptor_count(skb, tx_ring)) | |
1629 | return NETDEV_TX_BUSY; | |
1630 | ||
1631 | /* prepare the xmit flags */ | |
1632 | if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) | |
1633 | goto out_drop; | |
1634 | ||
1635 | /* obtain protocol of skb */ | |
a12c4158 | 1636 | protocol = vlan_get_protocol(skb); |
7f12ad74 GR |
1637 | |
1638 | /* record the location of the first descriptor for this packet */ | |
1639 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
1640 | ||
1641 | /* setup IPv4/IPv6 offloads */ | |
1642 | if (protocol == htons(ETH_P_IP)) | |
1643 | tx_flags |= I40E_TX_FLAGS_IPV4; | |
1644 | else if (protocol == htons(ETH_P_IPV6)) | |
1645 | tx_flags |= I40E_TX_FLAGS_IPV6; | |
1646 | ||
1647 | tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len, | |
1648 | &cd_type_cmd_tso_mss, &cd_tunneling); | |
1649 | ||
1650 | if (tso < 0) | |
1651 | goto out_drop; | |
1652 | else if (tso) | |
1653 | tx_flags |= I40E_TX_FLAGS_TSO; | |
1654 | ||
1655 | skb_tx_timestamp(skb); | |
1656 | ||
1657 | /* always enable CRC insertion offload */ | |
1658 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
1659 | ||
1660 | /* Always offload the checksum, since it's in the data descriptor */ | |
1661 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1662 | tx_flags |= I40E_TX_FLAGS_CSUM; | |
1663 | ||
1664 | i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset, | |
1665 | tx_ring, &cd_tunneling); | |
1666 | } | |
1667 | ||
1668 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, | |
1669 | cd_tunneling, cd_l2tag2); | |
1670 | ||
1671 | i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, | |
1672 | td_cmd, td_offset); | |
1673 | ||
1674 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
1675 | ||
1676 | return NETDEV_TX_OK; | |
1677 | ||
1678 | out_drop: | |
1679 | dev_kfree_skb_any(skb); | |
1680 | return NETDEV_TX_OK; | |
1681 | } | |
1682 | ||
1683 | /** | |
1684 | * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
1685 | * @skb: send buffer | |
1686 | * @netdev: network interface device structure | |
1687 | * | |
1688 | * Returns NETDEV_TX_OK if sent, else an error code | |
1689 | **/ | |
1690 | netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
1691 | { | |
1692 | struct i40evf_adapter *adapter = netdev_priv(netdev); | |
1693 | struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping]; | |
1694 | ||
1695 | /* hardware can't handle really short frames, hardware padding works | |
1696 | * beyond this point | |
1697 | */ | |
1698 | if (unlikely(skb->len < I40E_MIN_TX_LEN)) { | |
1699 | if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len)) | |
1700 | return NETDEV_TX_OK; | |
1701 | skb->len = I40E_MIN_TX_LEN; | |
1702 | skb_set_tail_pointer(skb, I40E_MIN_TX_LEN); | |
1703 | } | |
1704 | ||
1705 | return i40e_xmit_frame_ring(skb, tx_ring); | |
1706 | } |