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i40evf: detect reset more reliably
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
af1a2a9c 4 * Copyright(c) 2013 - 2014 Intel Corporation.
7f12ad74
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
7f12ad74
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
7ed3f5f0 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
7ed3f5f0 29
7f12ad74 30#include "i40evf.h"
206812b5 31#include "i40e_prototype.h"
7f12ad74
GR		 32
33static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35{
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41}
42
43#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45/**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52{
53 if (tx_buffer->skb) {
49d7d933
ASJ		 54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
56 else
57 dev_kfree_skb_any(tx_buffer->skb);
58
7f12ad74
GR		 59 if (dma_unmap_len(tx_buffer, len))
60 dma_unmap_single(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
63 DMA_TO_DEVICE);
64 } else if (dma_unmap_len(tx_buffer, len)) {
65 dma_unmap_page(ring->dev,
66 dma_unmap_addr(tx_buffer, dma),
67 dma_unmap_len(tx_buffer, len),
68 DMA_TO_DEVICE);
69 }
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74}
75
76/**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81{
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
107 tx_ring->queue_index));
108}
109
110/**
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
113 *
114 * Free all transmit software resources
115 **/
116void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117{
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
121
122 if (tx_ring->desc) {
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
126 }
127}
128
a68de58d
JB		 129/**
130 * i40e_get_head - Retrieve head from head writeback
131 * @tx_ring: tx ring to fetch head of
132 *
133 * Returns value of Tx ring head based on value stored
134 * in head write-back location
135 **/
136static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
137{
138 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
139
140 return le32_to_cpu(*(volatile __le32 *)head);
141}
142
c29af37f
ASJ		 143#define WB_STRIDE 0x3
144
7f12ad74
GR		 145/**
146 * i40e_clean_tx_irq - Reclaim resources after transmit completes
147 * @tx_ring: tx ring to clean
148 * @budget: how many cleans we're allowed
149 *
150 * Returns true if there's any budget left (e.g. the clean is finished)
151 **/
152static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
153{
154 u16 i = tx_ring->next_to_clean;
155 struct i40e_tx_buffer *tx_buf;
1943d8ba 156 struct i40e_tx_desc *tx_head;
7f12ad74
GR		 157 struct i40e_tx_desc *tx_desc;
158 unsigned int total_packets = 0;
159 unsigned int total_bytes = 0;
160
161 tx_buf = &tx_ring->tx_bi[i];
162 tx_desc = I40E_TX_DESC(tx_ring, i);
163 i -= tx_ring->count;
164
1943d8ba
JB		 165 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
166
7f12ad74
GR		 167 do {
168 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
169
170 /* if next_to_watch is not set then there is no work pending */
171 if (!eop_desc)
172 break;
173
174 /* prevent any other reads prior to eop_desc */
175 read_barrier_depends();
176
1943d8ba
JB		 177 /* we have caught up to head, no work left to do */
178 if (tx_head == tx_desc)
7f12ad74
GR		 179 break;
180
181 /* clear next_to_watch to prevent false hangs */
182 tx_buf->next_to_watch = NULL;
183
184 /* update the statistics for this packet */
185 total_bytes += tx_buf->bytecount;
186 total_packets += tx_buf->gso_segs;
187
188 /* free the skb */
189 dev_kfree_skb_any(tx_buf->skb);
190
191 /* unmap skb header data */
192 dma_unmap_single(tx_ring->dev,
193 dma_unmap_addr(tx_buf, dma),
194 dma_unmap_len(tx_buf, len),
195 DMA_TO_DEVICE);
196
197 /* clear tx_buffer data */
198 tx_buf->skb = NULL;
199 dma_unmap_len_set(tx_buf, len, 0);
200
201 /* unmap remaining buffers */
202 while (tx_desc != eop_desc) {
203
204 tx_buf++;
205 tx_desc++;
206 i++;
207 if (unlikely(!i)) {
208 i -= tx_ring->count;
209 tx_buf = tx_ring->tx_bi;
210 tx_desc = I40E_TX_DESC(tx_ring, 0);
211 }
212
213 /* unmap any remaining paged data */
214 if (dma_unmap_len(tx_buf, len)) {
215 dma_unmap_page(tx_ring->dev,
216 dma_unmap_addr(tx_buf, dma),
217 dma_unmap_len(tx_buf, len),
218 DMA_TO_DEVICE);
219 dma_unmap_len_set(tx_buf, len, 0);
220 }
221 }
222
223 /* move us one more past the eop_desc for start of next pkt */
224 tx_buf++;
225 tx_desc++;
226 i++;
227 if (unlikely(!i)) {
228 i -= tx_ring->count;
229 tx_buf = tx_ring->tx_bi;
230 tx_desc = I40E_TX_DESC(tx_ring, 0);
231 }
232
016890b9
JB		 233 prefetch(tx_desc);
234
7f12ad74
GR		 235 /* update budget accounting */
236 budget--;
237 } while (likely(budget));
238
239 i += tx_ring->count;
240 tx_ring->next_to_clean = i;
241 u64_stats_update_begin(&tx_ring->syncp);
242 tx_ring->stats.bytes += total_bytes;
243 tx_ring->stats.packets += total_packets;
244 u64_stats_update_end(&tx_ring->syncp);
245 tx_ring->q_vector->tx.total_bytes += total_bytes;
246 tx_ring->q_vector->tx.total_packets += total_packets;
247
b03a8c1f
KP		 248 /* check to see if there are any non-cache aligned descriptors
249 * waiting to be written back, and kick the hardware to force
250 * them to be written back in case of napi polling
251 */
c29af37f
ASJ		 252 if (budget &&
253 !((i & WB_STRIDE) == WB_STRIDE) &&
254 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
255 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
256 tx_ring->arm_wb = true;
c29af37f 257
7f12ad74
GR		 258 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
259 tx_ring->queue_index),
260 total_packets, total_bytes);
261
262#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
263 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
264 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
265 /* Make sure that anybody stopping the queue after this
266 * sees the new next_to_clean.
267 */
268 smp_mb();
269 if (__netif_subqueue_stopped(tx_ring->netdev,
270 tx_ring->queue_index) &&
271 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
272 netif_wake_subqueue(tx_ring->netdev,
273 tx_ring->queue_index);
274 ++tx_ring->tx_stats.restart_queue;
275 }
276 }
277
b03a8c1f 278 return !!budget;
7f12ad74
GR		 279}
280
c29af37f 281/**
b03a8c1f 282 * i40evf_force_wb -Arm hardware to do a wb on noncache aligned descriptors
c29af37f
ASJ		 283 * @vsi: the VSI we care about
284 * @q_vector: the vector on which to force writeback
285 *
286 **/
b03a8c1f 287static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
c29af37f 288{
8e0764b4
ASJ		 289 u16 flags = q_vector->tx.ring[0].flags;
290
291 if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
292 u32 val;
293
294 if (q_vector->arm_wb_state)
295 return;
296
297 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK;
298
299 wr32(&vsi->back->hw,
300 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
301 vsi->base_vector - 1),
302 val);
303 q_vector->arm_wb_state = true;
304 } else {
305 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
306 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
307 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
308 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK;
309 /* allow 00 to be written to the index */
310
311 wr32(&vsi->back->hw,
312 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
313 vsi->base_vector - 1), val);
314 }
c29af37f
ASJ		 315}
316
7f12ad74
GR		 317/**
318 * i40e_set_new_dynamic_itr - Find new ITR level
319 * @rc: structure containing ring performance data
320 *
321 * Stores a new ITR value based on packets and byte counts during
322 * the last interrupt. The advantage of per interrupt computation
323 * is faster updates and more accurate ITR for the current traffic
324 * pattern. Constants in this function were computed based on
325 * theoretical maximum wire speed and thresholds were set based on
326 * testing data as well as attempting to minimize response time
327 * while increasing bulk throughput.
328 **/
329static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
330{
331 enum i40e_latency_range new_latency_range = rc->latency_range;
332 u32 new_itr = rc->itr;
333 int bytes_per_int;
334
335 if (rc->total_packets == 0 || !rc->itr)
336 return;
337
338 /* simple throttlerate management
339 * 0-10MB/s lowest (100000 ints/s)
340 * 10-20MB/s low (20000 ints/s)
341 * 20-1249MB/s bulk (8000 ints/s)
342 */
343 bytes_per_int = rc->total_bytes / rc->itr;
de32e3ef 344 switch (new_latency_range) {
7f12ad74
GR		 345 case I40E_LOWEST_LATENCY:
346 if (bytes_per_int > 10)
347 new_latency_range = I40E_LOW_LATENCY;
348 break;
349 case I40E_LOW_LATENCY:
350 if (bytes_per_int > 20)
351 new_latency_range = I40E_BULK_LATENCY;
352 else if (bytes_per_int <= 10)
353 new_latency_range = I40E_LOWEST_LATENCY;
354 break;
355 case I40E_BULK_LATENCY:
356 if (bytes_per_int <= 20)
de32e3ef
CW		 357 new_latency_range = I40E_LOW_LATENCY;
358 break;
359 default:
360 if (bytes_per_int <= 20)
361 new_latency_range = I40E_LOW_LATENCY;
7f12ad74
GR		 362 break;
363 }
de32e3ef 364 rc->latency_range = new_latency_range;
7f12ad74
GR		 365
366 switch (new_latency_range) {
367 case I40E_LOWEST_LATENCY:
368 new_itr = I40E_ITR_100K;
369 break;
370 case I40E_LOW_LATENCY:
371 new_itr = I40E_ITR_20K;
372 break;
373 case I40E_BULK_LATENCY:
374 new_itr = I40E_ITR_8K;
375 break;
376 default:
377 break;
378 }
379
de32e3ef
CW		 380 if (new_itr != rc->itr)
381 rc->itr = new_itr;
7f12ad74
GR		 382
383 rc->total_bytes = 0;
384 rc->total_packets = 0;
385}
386
de32e3ef 387/*
7f12ad74
GR		 388 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
389 * @tx_ring: the tx ring to set up
390 *
391 * Return 0 on success, negative on error
392 **/
393int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
394{
395 struct device *dev = tx_ring->dev;
396 int bi_size;
397
398 if (!dev)
399 return -ENOMEM;
400
67c818a1
MW		 401 /* warn if we are about to overwrite the pointer */
402 WARN_ON(tx_ring->tx_bi);
7f12ad74
GR		 403 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
404 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
405 if (!tx_ring->tx_bi)
406 goto err;
407
408 /* round up to nearest 4K */
409 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 410 /* add u32 for head writeback, align after this takes care of
411 * guaranteeing this is at least one cache line in size
412 */
413 tx_ring->size += sizeof(u32);
7f12ad74
GR		 414 tx_ring->size = ALIGN(tx_ring->size, 4096);
415 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
416 &tx_ring->dma, GFP_KERNEL);
417 if (!tx_ring->desc) {
418 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
419 tx_ring->size);
420 goto err;
421 }
422
423 tx_ring->next_to_use = 0;
424 tx_ring->next_to_clean = 0;
425 return 0;
426
427err:
428 kfree(tx_ring->tx_bi);
429 tx_ring->tx_bi = NULL;
430 return -ENOMEM;
431}
432
433/**
434 * i40evf_clean_rx_ring - Free Rx buffers
435 * @rx_ring: ring to be cleaned
436 **/
437void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
438{
439 struct device *dev = rx_ring->dev;
440 struct i40e_rx_buffer *rx_bi;
441 unsigned long bi_size;
442 u16 i;
443
444 /* ring already cleared, nothing to do */
445 if (!rx_ring->rx_bi)
446 return;
447
a132af24
MW		 448 if (ring_is_ps_enabled(rx_ring)) {
449 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
450
451 rx_bi = &rx_ring->rx_bi[0];
452 if (rx_bi->hdr_buf) {
453 dma_free_coherent(dev,
454 bufsz,
455 rx_bi->hdr_buf,
456 rx_bi->dma);
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_bi = &rx_ring->rx_bi[i];
459 rx_bi->dma = 0;
37a2973a 460 rx_bi->hdr_buf = NULL;
a132af24
MW		 461 }
462 }
463 }
7f12ad74
GR		 464 /* Free all the Rx ring sk_buffs */
465 for (i = 0; i < rx_ring->count; i++) {
466 rx_bi = &rx_ring->rx_bi[i];
467 if (rx_bi->dma) {
468 dma_unmap_single(dev,
469 rx_bi->dma,
470 rx_ring->rx_buf_len,
471 DMA_FROM_DEVICE);
472 rx_bi->dma = 0;
473 }
474 if (rx_bi->skb) {
475 dev_kfree_skb(rx_bi->skb);
476 rx_bi->skb = NULL;
477 }
478 if (rx_bi->page) {
479 if (rx_bi->page_dma) {
480 dma_unmap_page(dev,
481 rx_bi->page_dma,
482 PAGE_SIZE / 2,
483 DMA_FROM_DEVICE);
484 rx_bi->page_dma = 0;
485 }
486 __free_page(rx_bi->page);
487 rx_bi->page = NULL;
488 rx_bi->page_offset = 0;
489 }
490 }
491
492 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
493 memset(rx_ring->rx_bi, 0, bi_size);
494
495 /* Zero out the descriptor ring */
496 memset(rx_ring->desc, 0, rx_ring->size);
497
498 rx_ring->next_to_clean = 0;
499 rx_ring->next_to_use = 0;
500}
501
502/**
503 * i40evf_free_rx_resources - Free Rx resources
504 * @rx_ring: ring to clean the resources from
505 *
506 * Free all receive software resources
507 **/
508void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
509{
510 i40evf_clean_rx_ring(rx_ring);
511 kfree(rx_ring->rx_bi);
512 rx_ring->rx_bi = NULL;
513
514 if (rx_ring->desc) {
515 dma_free_coherent(rx_ring->dev, rx_ring->size,
516 rx_ring->desc, rx_ring->dma);
517 rx_ring->desc = NULL;
518 }
519}
520
a132af24
MW		 521/**
522 * i40evf_alloc_rx_headers - allocate rx header buffers
523 * @rx_ring: ring to alloc buffers
524 *
525 * Allocate rx header buffers for the entire ring. As these are static,
526 * this is only called when setting up a new ring.
527 **/
528void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
529{
530 struct device *dev = rx_ring->dev;
531 struct i40e_rx_buffer *rx_bi;
532 dma_addr_t dma;
533 void *buffer;
534 int buf_size;
535 int i;
536
537 if (rx_ring->rx_bi[0].hdr_buf)
538 return;
539 /* Make sure the buffers don't cross cache line boundaries. */
540 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
541 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
542 &dma, GFP_KERNEL);
543 if (!buffer)
544 return;
545 for (i = 0; i < rx_ring->count; i++) {
546 rx_bi = &rx_ring->rx_bi[i];
547 rx_bi->dma = dma + (i * buf_size);
548 rx_bi->hdr_buf = buffer + (i * buf_size);
549 }
550}
551
7f12ad74
GR		 552/**
553 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
554 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
555 *
556 * Returns 0 on success, negative on failure
557 **/
558int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
559{
560 struct device *dev = rx_ring->dev;
561 int bi_size;
562
67c818a1
MW		 563 /* warn if we are about to overwrite the pointer */
564 WARN_ON(rx_ring->rx_bi);
7f12ad74
GR		 565 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
566 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
567 if (!rx_ring->rx_bi)
568 goto err;
569
f217d6ca 570 u64_stats_init(&rx_ring->syncp);
638702bd 571
7f12ad74
GR		 572 /* Round up to nearest 4K */
573 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
574 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
575 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
576 rx_ring->size = ALIGN(rx_ring->size, 4096);
577 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
578 &rx_ring->dma, GFP_KERNEL);
579
580 if (!rx_ring->desc) {
581 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
582 rx_ring->size);
583 goto err;
584 }
585
586 rx_ring->next_to_clean = 0;
587 rx_ring->next_to_use = 0;
588
589 return 0;
590err:
591 kfree(rx_ring->rx_bi);
592 rx_ring->rx_bi = NULL;
593 return -ENOMEM;
594}
595
596/**
597 * i40e_release_rx_desc - Store the new tail and head values
598 * @rx_ring: ring to bump
599 * @val: new head index
600 **/
601static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
602{
603 rx_ring->next_to_use = val;
604 /* Force memory writes to complete before letting h/w
605 * know there are new descriptors to fetch. (Only
606 * applicable for weak-ordered memory model archs,
607 * such as IA-64).
608 */
609 wmb();
610 writel(val, rx_ring->tail);
611}
612
613/**
a132af24
MW		 614 * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
615 * @rx_ring: ring to place buffers on
616 * @cleaned_count: number of buffers to replace
617 **/
618void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
619{
620 u16 i = rx_ring->next_to_use;
621 union i40e_rx_desc *rx_desc;
622 struct i40e_rx_buffer *bi;
623
624 /* do nothing if no valid netdev defined */
625 if (!rx_ring->netdev || !cleaned_count)
626 return;
627
628 while (cleaned_count--) {
629 rx_desc = I40E_RX_DESC(rx_ring, i);
630 bi = &rx_ring->rx_bi[i];
631
632 if (bi->skb) /* desc is in use */
633 goto no_buffers;
634 if (!bi->page) {
635 bi->page = alloc_page(GFP_ATOMIC);
636 if (!bi->page) {
637 rx_ring->rx_stats.alloc_page_failed++;
638 goto no_buffers;
639 }
640 }
641
642 if (!bi->page_dma) {
643 /* use a half page if we're re-using */
644 bi->page_offset ^= PAGE_SIZE / 2;
645 bi->page_dma = dma_map_page(rx_ring->dev,
646 bi->page,
647 bi->page_offset,
648 PAGE_SIZE / 2,
649 DMA_FROM_DEVICE);
650 if (dma_mapping_error(rx_ring->dev,
651 bi->page_dma)) {
652 rx_ring->rx_stats.alloc_page_failed++;
653 bi->page_dma = 0;
654 goto no_buffers;
655 }
656 }
657
658 dma_sync_single_range_for_device(rx_ring->dev,
659 bi->dma,
660 0,
661 rx_ring->rx_hdr_len,
662 DMA_FROM_DEVICE);
663 /* Refresh the desc even if buffer_addrs didn't change
664 * because each write-back erases this info.
665 */
666 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
667 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
668 i++;
669 if (i == rx_ring->count)
670 i = 0;
671 }
672
673no_buffers:
674 if (rx_ring->next_to_use != i)
675 i40e_release_rx_desc(rx_ring, i);
676}
677
678/**
679 * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
7f12ad74
GR		 680 * @rx_ring: ring to place buffers on
681 * @cleaned_count: number of buffers to replace
682 **/
a132af24 683void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
7f12ad74
GR		 684{
685 u16 i = rx_ring->next_to_use;
686 union i40e_rx_desc *rx_desc;
687 struct i40e_rx_buffer *bi;
688 struct sk_buff *skb;
689
690 /* do nothing if no valid netdev defined */
691 if (!rx_ring->netdev || !cleaned_count)
692 return;
693
694 while (cleaned_count--) {
695 rx_desc = I40E_RX_DESC(rx_ring, i);
696 bi = &rx_ring->rx_bi[i];
697 skb = bi->skb;
698
699 if (!skb) {
700 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
701 rx_ring->rx_buf_len);
702 if (!skb) {
703 rx_ring->rx_stats.alloc_buff_failed++;
704 goto no_buffers;
705 }
706 /* initialize queue mapping */
707 skb_record_rx_queue(skb, rx_ring->queue_index);
708 bi->skb = skb;
709 }
710
711 if (!bi->dma) {
712 bi->dma = dma_map_single(rx_ring->dev,
713 skb->data,
714 rx_ring->rx_buf_len,
715 DMA_FROM_DEVICE);
716 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
717 rx_ring->rx_stats.alloc_buff_failed++;
718 bi->dma = 0;
719 goto no_buffers;
720 }
721 }
722
a132af24
MW		 723 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
724 rx_desc->read.hdr_addr = 0;
7f12ad74
GR		 725 i++;
726 if (i == rx_ring->count)
727 i = 0;
728 }
729
730no_buffers:
731 if (rx_ring->next_to_use != i)
732 i40e_release_rx_desc(rx_ring, i);
733}
734
735/**
736 * i40e_receive_skb - Send a completed packet up the stack
737 * @rx_ring: rx ring in play
738 * @skb: packet to send up
739 * @vlan_tag: vlan tag for packet
740 **/
741static void i40e_receive_skb(struct i40e_ring *rx_ring,
742 struct sk_buff *skb, u16 vlan_tag)
743{
744 struct i40e_q_vector *q_vector = rx_ring->q_vector;
745 struct i40e_vsi *vsi = rx_ring->vsi;
746 u64 flags = vsi->back->flags;
747
748 if (vlan_tag & VLAN_VID_MASK)
749 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
750
751 if (flags & I40E_FLAG_IN_NETPOLL)
752 netif_rx(skb);
753 else
754 napi_gro_receive(&q_vector->napi, skb);
755}
756
757/**
758 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
759 * @vsi: the VSI we care about
760 * @skb: skb currently being received and modified
761 * @rx_status: status value of last descriptor in packet
762 * @rx_error: error value of last descriptor in packet
763 * @rx_ptype: ptype value of last descriptor in packet
764 **/
765static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
766 struct sk_buff *skb,
767 u32 rx_status,
768 u32 rx_error,
769 u16 rx_ptype)
770{
8a3c91cc
JB		 771 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
772 bool ipv4 = false, ipv6 = false;
7f12ad74
GR		 773 bool ipv4_tunnel, ipv6_tunnel;
774 __wsum rx_udp_csum;
7f12ad74 775 struct iphdr *iph;
8a3c91cc 776 __sum16 csum;
7f12ad74 777
f8faaa40
ASJ		 778 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
779 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
780 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
781 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
7f12ad74 782
7f12ad74
GR		 783 skb->ip_summed = CHECKSUM_NONE;
784
785 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 786 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
787 return;
788
789 /* did the hardware decode the packet and checksum? */
41a1d04b 790 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
8a3c91cc
JB		 791 return;
792
793 /* both known and outer_ip must be set for the below code to work */
794 if (!(decoded.known && decoded.outer_ip))
7f12ad74
GR		 795 return;
796
8a3c91cc
JB		 797 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
798 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
799 ipv4 = true;
800 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
801 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
802 ipv6 = true;
803
804 if (ipv4 &&
41a1d04b
JB		 805 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
806 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
8a3c91cc
JB		 807 goto checksum_fail;
808
ddf1d0d7 809 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 810 if (ipv6 &&
41a1d04b 811 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
8a3c91cc 812 /* don't increment checksum err here, non-fatal err */
7f12ad74
GR		 813 return;
814
8a3c91cc 815 /* there was some L4 error, count error and punt packet to the stack */
41a1d04b 816 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
8a3c91cc
JB		 817 goto checksum_fail;
818
819 /* handle packets that were not able to be checksummed due
820 * to arrival speed, in this case the stack can compute
821 * the csum.
822 */
41a1d04b 823 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
7f12ad74 824 return;
7f12ad74 825
8a3c91cc
JB		 826 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
827 * it in the driver, hardware does not do it for us.
828 * Since L3L4P bit was set we assume a valid IHL value (>=5)
829 * so the total length of IPv4 header is IHL*4 bytes
830 * The UDP_0 bit *may* bet set if the *inner* header is UDP
831 */
818f2e7b 832 if (ipv4_tunnel) {
7f12ad74
GR		 833 skb->transport_header = skb->mac_header +
834 sizeof(struct ethhdr) +
835 (ip_hdr(skb)->ihl * 4);
836
837 /* Add 4 bytes for VLAN tagged packets */
838 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
839 skb->protocol == htons(ETH_P_8021AD))
840 ? VLAN_HLEN : 0;
841
818f2e7b
ASJ		 842 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
843 (udp_hdr(skb)->check != 0)) {
844 rx_udp_csum = udp_csum(skb);
845 iph = ip_hdr(skb);
846 csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
847 (skb->len -
848 skb_transport_offset(skb)),
849 IPPROTO_UDP, rx_udp_csum);
7f12ad74 850
818f2e7b
ASJ		 851 if (udp_hdr(skb)->check != csum)
852 goto checksum_fail;
853
854 } /* else its GRE and so no outer UDP header */
7f12ad74
GR		 855 }
856
857 skb->ip_summed = CHECKSUM_UNNECESSARY;
407fa085 858 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 859
860 return;
861
862checksum_fail:
863 vsi->back->hw_csum_rx_error++;
7f12ad74
GR		 864}
865
866/**
867 * i40e_rx_hash - returns the hash value from the Rx descriptor
868 * @ring: descriptor ring
869 * @rx_desc: specific descriptor
870 **/
871static inline u32 i40e_rx_hash(struct i40e_ring *ring,
872 union i40e_rx_desc *rx_desc)
873{
874 const __le64 rss_mask =
875 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
876 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
877
878 if ((ring->netdev->features & NETIF_F_RXHASH) &&
879 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
880 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
881 else
882 return 0;
883}
884
206812b5
JB		 885/**
886 * i40e_ptype_to_hash - get a hash type
887 * @ptype: the ptype value from the descriptor
888 *
889 * Returns a hash type to be used by skb_set_hash
890 **/
891static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
892{
893 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
894
895 if (!decoded.known)
896 return PKT_HASH_TYPE_NONE;
897
898 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
899 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
900 return PKT_HASH_TYPE_L4;
901 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
902 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
903 return PKT_HASH_TYPE_L3;
904 else
905 return PKT_HASH_TYPE_L2;
906}
907
7f12ad74 908/**
a132af24 909 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
7f12ad74
GR		 910 * @rx_ring: rx ring to clean
911 * @budget: how many cleans we're allowed
912 *
913 * Returns true if there's any budget left (e.g. the clean is finished)
914 **/
a132af24 915static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
7f12ad74
GR		 916{
917 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
918 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
919 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
27ca2753 920 const int current_node = numa_mem_id();
7f12ad74
GR		 921 struct i40e_vsi *vsi = rx_ring->vsi;
922 u16 i = rx_ring->next_to_clean;
923 union i40e_rx_desc *rx_desc;
924 u32 rx_error, rx_status;
206812b5 925 u8 rx_ptype;
7f12ad74 926 u64 qword;
7f12ad74 927
a132af24 928 do {
7f12ad74
GR		 929 struct i40e_rx_buffer *rx_bi;
930 struct sk_buff *skb;
931 u16 vlan_tag;
a132af24
MW		 932 /* return some buffers to hardware, one at a time is too slow */
933 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
934 i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
935 cleaned_count = 0;
936 }
937
938 i = rx_ring->next_to_clean;
939 rx_desc = I40E_RX_DESC(rx_ring, i);
940 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
941 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
942 I40E_RXD_QW1_STATUS_SHIFT;
943
41a1d04b 944 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 945 break;
946
947 /* This memory barrier is needed to keep us from reading
948 * any other fields out of the rx_desc until we know the
949 * DD bit is set.
950 */
67317166 951 dma_rmb();
7f12ad74
GR		 952 rx_bi = &rx_ring->rx_bi[i];
953 skb = rx_bi->skb;
a132af24
MW		 954 if (likely(!skb)) {
955 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
956 rx_ring->rx_hdr_len);
8b6ed9c2 957 if (!skb) {
a132af24 958 rx_ring->rx_stats.alloc_buff_failed++;
8b6ed9c2
JB		 959 break;
960 }
961
a132af24
MW		 962 /* initialize queue mapping */
963 skb_record_rx_queue(skb, rx_ring->queue_index);
964 /* we are reusing so sync this buffer for CPU use */
965 dma_sync_single_range_for_cpu(rx_ring->dev,
966 rx_bi->dma,
967 0,
968 rx_ring->rx_hdr_len,
969 DMA_FROM_DEVICE);
970 }
7f12ad74
GR		 971 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
972 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
973 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
974 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
975 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
976 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
977
978 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
979 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b
JB		 980 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
981 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
7f12ad74
GR		 982
983 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
984 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 985 prefetch(rx_bi->page);
7f12ad74 986 rx_bi->skb = NULL;
a132af24
MW		 987 cleaned_count++;
988 if (rx_hbo || rx_sph) {
989 int len;
7f12ad74
GR		 990 if (rx_hbo)
991 len = I40E_RX_HDR_SIZE;
7f12ad74 992 else
a132af24
MW		 993 len = rx_header_len;
994 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
995 } else if (skb->len == 0) {
996 int len;
997
998 len = (rx_packet_len > skb_headlen(skb) ?
999 skb_headlen(skb) : rx_packet_len);
1000 memcpy(__skb_put(skb, len),
1001 rx_bi->page + rx_bi->page_offset,
1002 len);
1003 rx_bi->page_offset += len;
1004 rx_packet_len -= len;
7f12ad74
GR		 1005 }
1006
1007 /* Get the rest of the data if this was a header split */
a132af24 1008 if (rx_packet_len) {
7f12ad74
GR		 1009 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1010 rx_bi->page,
1011 rx_bi->page_offset,
1012 rx_packet_len);
1013
1014 skb->len += rx_packet_len;
1015 skb->data_len += rx_packet_len;
1016 skb->truesize += rx_packet_len;
1017
1018 if ((page_count(rx_bi->page) == 1) &&
1019 (page_to_nid(rx_bi->page) == current_node))
1020 get_page(rx_bi->page);
1021 else
1022 rx_bi->page = NULL;
1023
1024 dma_unmap_page(rx_ring->dev,
1025 rx_bi->page_dma,
1026 PAGE_SIZE / 2,
1027 DMA_FROM_DEVICE);
1028 rx_bi->page_dma = 0;
1029 }
a132af24 1030 I40E_RX_INCREMENT(rx_ring, i);
7f12ad74
GR		 1031
1032 if (unlikely(
41a1d04b 1033 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
7f12ad74
GR		 1034 struct i40e_rx_buffer *next_buffer;
1035
1036 next_buffer = &rx_ring->rx_bi[i];
a132af24 1037 next_buffer->skb = skb;
7f12ad74 1038 rx_ring->rx_stats.non_eop_descs++;
a132af24 1039 continue;
7f12ad74
GR		 1040 }
1041
1042 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1043 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
7f12ad74 1044 dev_kfree_skb_any(skb);
a132af24 1045 continue;
7f12ad74
GR		 1046 }
1047
206812b5
JB		 1048 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1049 i40e_ptype_to_hash(rx_ptype));
7f12ad74
GR		 1050 /* probably a little skewed due to removing CRC */
1051 total_rx_bytes += skb->len;
1052 total_rx_packets++;
1053
1054 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1055
1056 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1057
41a1d04b 1058 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
7f12ad74
GR		 1059 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1060 : 0;
a132af24
MW		 1061#ifdef I40E_FCOE
1062 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1063 dev_kfree_skb_any(skb);
1064 continue;
1065 }
1066#endif
1067 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
7f12ad74
GR		 1068 i40e_receive_skb(rx_ring, skb, vlan_tag);
1069
7f12ad74 1070 rx_desc->wb.qword1.status_error_len = 0;
7f12ad74 1071
a132af24
MW		 1072 } while (likely(total_rx_packets < budget));
1073
1074 u64_stats_update_begin(&rx_ring->syncp);
1075 rx_ring->stats.packets += total_rx_packets;
1076 rx_ring->stats.bytes += total_rx_bytes;
1077 u64_stats_update_end(&rx_ring->syncp);
1078 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1079 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1080
1081 return total_rx_packets;
1082}
1083
1084/**
1085 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1086 * @rx_ring: rx ring to clean
1087 * @budget: how many cleans we're allowed
1088 *
1089 * Returns number of packets cleaned
1090 **/
1091static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1092{
1093 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1094 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1095 struct i40e_vsi *vsi = rx_ring->vsi;
1096 union i40e_rx_desc *rx_desc;
1097 u32 rx_error, rx_status;
1098 u16 rx_packet_len;
1099 u8 rx_ptype;
1100 u64 qword;
1101 u16 i;
1102
1103 do {
1104 struct i40e_rx_buffer *rx_bi;
1105 struct sk_buff *skb;
1106 u16 vlan_tag;
7f12ad74
GR		 1107 /* return some buffers to hardware, one at a time is too slow */
1108 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1109 i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
7f12ad74
GR		 1110 cleaned_count = 0;
1111 }
1112
a132af24
MW		 1113 i = rx_ring->next_to_clean;
1114 rx_desc = I40E_RX_DESC(rx_ring, i);
7f12ad74
GR		 1115 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1116 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1117 I40E_RXD_QW1_STATUS_SHIFT;
1118
41a1d04b 1119 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1120 break;
1121
1122 /* This memory barrier is needed to keep us from reading
1123 * any other fields out of the rx_desc until we know the
1124 * DD bit is set.
1125 */
67317166 1126 dma_rmb();
a132af24
MW		 1127
1128 rx_bi = &rx_ring->rx_bi[i];
1129 skb = rx_bi->skb;
1130 prefetch(skb->data);
1131
1132 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1133 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1134
1135 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1136 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b 1137 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
a132af24
MW		 1138
1139 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1140 I40E_RXD_QW1_PTYPE_SHIFT;
1141 rx_bi->skb = NULL;
1142 cleaned_count++;
1143
1144 /* Get the header and possibly the whole packet
1145 * If this is an skb from previous receive dma will be 0
1146 */
1147 skb_put(skb, rx_packet_len);
1148 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1149 DMA_FROM_DEVICE);
1150 rx_bi->dma = 0;
1151
1152 I40E_RX_INCREMENT(rx_ring, i);
1153
1154 if (unlikely(
41a1d04b 1155 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
a132af24
MW		 1156 rx_ring->rx_stats.non_eop_descs++;
1157 continue;
1158 }
1159
1160 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1161 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
a132af24
MW		 1162 dev_kfree_skb_any(skb);
1163 /* TODO: shouldn't we increment a counter indicating the
1164 * drop?
1165 */
1166 continue;
1167 }
1168
1169 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1170 i40e_ptype_to_hash(rx_ptype));
1171 /* probably a little skewed due to removing CRC */
1172 total_rx_bytes += skb->len;
1173 total_rx_packets++;
1174
1175 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1176
1177 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1178
41a1d04b 1179 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
a132af24
MW		 1180 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1181 : 0;
1182 i40e_receive_skb(rx_ring, skb, vlan_tag);
1183
a132af24
MW		 1184 rx_desc->wb.qword1.status_error_len = 0;
1185 } while (likely(total_rx_packets < budget));
7f12ad74 1186
7f12ad74
GR		 1187 u64_stats_update_begin(&rx_ring->syncp);
1188 rx_ring->stats.packets += total_rx_packets;
1189 rx_ring->stats.bytes += total_rx_bytes;
1190 u64_stats_update_end(&rx_ring->syncp);
1191 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1192 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1193
a132af24 1194 return total_rx_packets;
7f12ad74
GR		 1195}
1196
de32e3ef
CW		 1197/**
1198 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1199 * @vsi: the VSI we care about
1200 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1201 *
1202 **/
1203static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1204 struct i40e_q_vector *q_vector)
1205{
1206 struct i40e_hw *hw = &vsi->back->hw;
1207 u16 old_itr;
1208 int vector;
1209 u32 val;
1210
1211 vector = (q_vector->v_idx + vsi->base_vector);
1212 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
1213 old_itr = q_vector->rx.itr;
1214 i40e_set_new_dynamic_itr(&q_vector->rx);
1215 if (old_itr != q_vector->rx.itr) {
b1f3366b
ASJ		 1216 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1217 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
de32e3ef 1218 (I40E_RX_ITR <<
b1f3366b 1219 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
de32e3ef 1220 (q_vector->rx.itr <<
b1f3366b 1221 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
de32e3ef 1222 } else {
b1f3366b
ASJ		 1223 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1224 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
de32e3ef 1225 (I40E_ITR_NONE <<
b1f3366b 1226 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
de32e3ef
CW		 1227 }
1228 if (!test_bit(__I40E_DOWN, &vsi->state))
1229 wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1230 } else {
1231 i40evf_irq_enable_queues(vsi->back, 1
1232 << q_vector->v_idx);
1233 }
1234 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
1235 old_itr = q_vector->tx.itr;
1236 i40e_set_new_dynamic_itr(&q_vector->tx);
1237 if (old_itr != q_vector->tx.itr) {
b1f3366b
ASJ		 1238 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1239 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
de32e3ef 1240 (I40E_TX_ITR <<
b1f3366b 1241 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
de32e3ef 1242 (q_vector->tx.itr <<
b1f3366b 1243 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
de32e3ef
CW		 1244
1245 } else {
b1f3366b
ASJ		 1246 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1247 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
de32e3ef 1248 (I40E_ITR_NONE <<
b1f3366b 1249 I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);
de32e3ef
CW		 1250 }
1251 if (!test_bit(__I40E_DOWN, &vsi->state))
1252 wr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);
1253 } else {
41a1d04b 1254 i40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));
de32e3ef
CW		 1255 }
1256}
1257
7f12ad74
GR		 1258/**
1259 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1260 * @napi: napi struct with our devices info in it
1261 * @budget: amount of work driver is allowed to do this pass, in packets
1262 *
1263 * This function will clean all queues associated with a q_vector.
1264 *
1265 * Returns the amount of work done
1266 **/
1267int i40evf_napi_poll(struct napi_struct *napi, int budget)
1268{
1269 struct i40e_q_vector *q_vector =
1270 container_of(napi, struct i40e_q_vector, napi);
1271 struct i40e_vsi *vsi = q_vector->vsi;
1272 struct i40e_ring *ring;
1273 bool clean_complete = true;
c29af37f 1274 bool arm_wb = false;
7f12ad74 1275 int budget_per_ring;
a132af24 1276 int cleaned;
7f12ad74
GR		 1277
1278 if (test_bit(__I40E_DOWN, &vsi->state)) {
1279 napi_complete(napi);
1280 return 0;
1281 }
1282
1283 /* Since the actual Tx work is minimal, we can give the Tx a larger
1284 * budget and be more aggressive about cleaning up the Tx descriptors.
1285 */
c29af37f 1286 i40e_for_each_ring(ring, q_vector->tx) {
7f12ad74 1287 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
c29af37f 1288 arm_wb |= ring->arm_wb;
0deda868 1289 ring->arm_wb = false;
c29af37f 1290 }
7f12ad74
GR		 1291
1292 /* We attempt to distribute budget to each Rx queue fairly, but don't
1293 * allow the budget to go below 1 because that would exit polling early.
1294 */
1295 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1296
a132af24
MW		 1297 i40e_for_each_ring(ring, q_vector->rx) {
1298 if (ring_is_ps_enabled(ring))
1299 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1300 else
1301 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1302 /* if we didn't clean as many as budgeted, we must be done */
1303 clean_complete &= (budget_per_ring != cleaned);
1304 }
7f12ad74
GR		 1305
1306 /* If work not completed, return budget and polling will return */
c29af37f
ASJ		 1307 if (!clean_complete) {
1308 if (arm_wb)
b03a8c1f 1309 i40evf_force_wb(vsi, q_vector);
7f12ad74 1310 return budget;
c29af37f 1311 }
7f12ad74 1312
8e0764b4
ASJ		 1313 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1314 q_vector->arm_wb_state = false;
1315
7f12ad74
GR		 1316 /* Work is done so exit the polling mode and re-enable the interrupt */
1317 napi_complete(napi);
de32e3ef 1318 i40e_update_enable_itr(vsi, q_vector);
7f12ad74
GR		 1319 return 0;
1320}
1321
1322/**
3e587cf3 1323 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
7f12ad74
GR		 1324 * @skb: send buffer
1325 * @tx_ring: ring to send buffer on
1326 * @flags: the tx flags to be set
1327 *
1328 * Checks the skb and set up correspondingly several generic transmit flags
1329 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1330 *
1331 * Returns error code indicate the frame should be dropped upon error and the
1332 * otherwise returns 0 to indicate the flags has been set properly.
1333 **/
3e587cf3
JB		 1334static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1335 struct i40e_ring *tx_ring,
1336 u32 *flags)
7f12ad74
GR		 1337{
1338 __be16 protocol = skb->protocol;
1339 u32 tx_flags = 0;
1340
31eaaccf
GR		 1341 if (protocol == htons(ETH_P_8021Q) &&
1342 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1343 /* When HW VLAN acceleration is turned off by the user the
1344 * stack sets the protocol to 8021q so that the driver
1345 * can take any steps required to support the SW only
1346 * VLAN handling. In our case the driver doesn't need
1347 * to take any further steps so just set the protocol
1348 * to the encapsulated ethertype.
1349 */
1350 skb->protocol = vlan_get_protocol(skb);
1351 goto out;
1352 }
1353
7f12ad74 1354 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 1355 if (skb_vlan_tag_present(skb)) {
1356 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
7f12ad74
GR		 1357 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1358 /* else if it is a SW VLAN, check the next protocol and store the tag */
1359 } else if (protocol == htons(ETH_P_8021Q)) {
1360 struct vlan_hdr *vhdr, _vhdr;
1361 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1362 if (!vhdr)
1363 return -EINVAL;
1364
1365 protocol = vhdr->h_vlan_encapsulated_proto;
1366 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1367 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1368 }
1369
31eaaccf 1370out:
7f12ad74
GR		 1371 *flags = tx_flags;
1372 return 0;
1373}
1374
1375/**
1376 * i40e_tso - set up the tso context descriptor
1377 * @tx_ring: ptr to the ring to send
1378 * @skb: ptr to the skb we're sending
7f12ad74
GR		 1379 * @hdr_len: ptr to the size of the packet header
1380 * @cd_tunneling: ptr to context descriptor bits
1381 *
1382 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1383 **/
1384static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
89232c3b
ASJ		 1385 u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1386 u32 *cd_tunneling)
7f12ad74
GR		 1387{
1388 u32 cd_cmd, cd_tso_len, cd_mss;
fe6d4aa4 1389 struct ipv6hdr *ipv6h;
7f12ad74
GR		 1390 struct tcphdr *tcph;
1391 struct iphdr *iph;
1392 u32 l4len;
1393 int err;
7f12ad74
GR		 1394
1395 if (!skb_is_gso(skb))
1396 return 0;
1397
fe6d4aa4
FR		 1398 err = skb_cow_head(skb, 0);
1399 if (err < 0)
1400 return err;
7f12ad74 1401
85e76d03
AS		 1402 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1403 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1404
1405 if (iph->version == 4) {
7f12ad74
GR		 1406 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1407 iph->tot_len = 0;
1408 iph->check = 0;
1409 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1410 0, IPPROTO_TCP, 0);
85e76d03 1411 } else if (ipv6h->version == 6) {
7f12ad74
GR		 1412 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1413 ipv6h->payload_len = 0;
1414 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1415 0, IPPROTO_TCP, 0);
1416 }
1417
1418 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1419 *hdr_len = (skb->encapsulation
1420 ? (skb_inner_transport_header(skb) - skb->data)
1421 : skb_transport_offset(skb)) + l4len;
1422
1423 /* find the field values */
1424 cd_cmd = I40E_TX_CTX_DESC_TSO;
1425 cd_tso_len = skb->len - *hdr_len;
1426 cd_mss = skb_shinfo(skb)->gso_size;
1427 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1428 ((u64)cd_tso_len <<
1429 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1430 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1431 return 1;
1432}
1433
1434/**
1435 * i40e_tx_enable_csum - Enable Tx checksum offloads
1436 * @skb: send buffer
89232c3b 1437 * @tx_flags: pointer to Tx flags currently set
7f12ad74
GR		 1438 * @td_cmd: Tx descriptor command bits to set
1439 * @td_offset: Tx descriptor header offsets to set
1440 * @cd_tunneling: ptr to context desc bits
1441 **/
89232c3b 1442static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
7f12ad74
GR		 1443 u32 *td_cmd, u32 *td_offset,
1444 struct i40e_ring *tx_ring,
1445 u32 *cd_tunneling)
1446{
1447 struct ipv6hdr *this_ipv6_hdr;
1448 unsigned int this_tcp_hdrlen;
1449 struct iphdr *this_ip_hdr;
1450 u32 network_hdr_len;
1451 u8 l4_hdr = 0;
527274c7
ASJ		 1452 struct udphdr *oudph;
1453 struct iphdr *oiph;
45991204 1454 u32 l4_tunnel = 0;
7f12ad74
GR		 1455
1456 if (skb->encapsulation) {
45991204
ASJ		 1457 switch (ip_hdr(skb)->protocol) {
1458 case IPPROTO_UDP:
527274c7
ASJ		 1459 oudph = udp_hdr(skb);
1460 oiph = ip_hdr(skb);
45991204 1461 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
89232c3b 1462 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
45991204
ASJ		 1463 break;
1464 default:
1465 return;
1466 }
7f12ad74
GR		 1467 network_hdr_len = skb_inner_network_header_len(skb);
1468 this_ip_hdr = inner_ip_hdr(skb);
1469 this_ipv6_hdr = inner_ipv6_hdr(skb);
1470 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1471
89232c3b
ASJ		 1472 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1473 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1474 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1475 ip_hdr(skb)->check = 0;
1476 } else {
1477 *cd_tunneling |=
1478 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1479 }
89232c3b 1480 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
85e76d03 1481 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
89232c3b 1482 if (*tx_flags & I40E_TX_FLAGS_TSO)
7f12ad74 1483 ip_hdr(skb)->check = 0;
7f12ad74
GR		 1484 }
1485
1486 /* Now set the ctx descriptor fields */
1487 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
45991204
ASJ		 1488 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1489 l4_tunnel |
7f12ad74
GR		 1490 ((skb_inner_network_offset(skb) -
1491 skb_transport_offset(skb)) >> 1) <<
1492 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
85e76d03 1493 if (this_ip_hdr->version == 6) {
89232c3b
ASJ		 1494 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1495 *tx_flags |= I40E_TX_FLAGS_IPV6;
85e76d03
AS		 1496 }
1497
7f12ad74 1498
527274c7
ASJ		 1499 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
1500 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
1501 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
1502 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
1503 oiph->daddr,
1504 (skb->len - skb_transport_offset(skb)),
1505 IPPROTO_UDP, 0);
1506 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1507 }
7f12ad74
GR		 1508 } else {
1509 network_hdr_len = skb_network_header_len(skb);
1510 this_ip_hdr = ip_hdr(skb);
1511 this_ipv6_hdr = ipv6_hdr(skb);
1512 this_tcp_hdrlen = tcp_hdrlen(skb);
1513 }
1514
1515 /* Enable IP checksum offloads */
89232c3b 1516 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
7f12ad74
GR		 1517 l4_hdr = this_ip_hdr->protocol;
1518 /* the stack computes the IP header already, the only time we
1519 * need the hardware to recompute it is in the case of TSO.
1520 */
89232c3b 1521 if (*tx_flags & I40E_TX_FLAGS_TSO) {
7f12ad74
GR		 1522 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1523 this_ip_hdr->check = 0;
1524 } else {
1525 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1526 }
1527 /* Now set the td_offset for IP header length */
1528 *td_offset = (network_hdr_len >> 2) <<
1529 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
89232c3b 1530 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
7f12ad74
GR		 1531 l4_hdr = this_ipv6_hdr->nexthdr;
1532 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1533 /* Now set the td_offset for IP header length */
1534 *td_offset = (network_hdr_len >> 2) <<
1535 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1536 }
1537 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1538 *td_offset |= (skb_network_offset(skb) >> 1) <<
1539 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1540
1541 /* Enable L4 checksum offloads */
1542 switch (l4_hdr) {
1543 case IPPROTO_TCP:
1544 /* enable checksum offloads */
1545 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1546 *td_offset |= (this_tcp_hdrlen >> 2) <<
1547 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1548 break;
1549 case IPPROTO_SCTP:
1550 /* enable SCTP checksum offload */
1551 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1552 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1553 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1554 break;
1555 case IPPROTO_UDP:
1556 /* enable UDP checksum offload */
1557 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1558 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1559 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1560 break;
1561 default:
1562 break;
1563 }
1564}
1565
1566/**
1567 * i40e_create_tx_ctx Build the Tx context descriptor
1568 * @tx_ring: ring to create the descriptor on
1569 * @cd_type_cmd_tso_mss: Quad Word 1
1570 * @cd_tunneling: Quad Word 0 - bits 0-31
1571 * @cd_l2tag2: Quad Word 0 - bits 32-63
1572 **/
1573static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1574 const u64 cd_type_cmd_tso_mss,
1575 const u32 cd_tunneling, const u32 cd_l2tag2)
1576{
1577 struct i40e_tx_context_desc *context_desc;
1578 int i = tx_ring->next_to_use;
1579
ff40dd5d
JB		 1580 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1581 !cd_tunneling && !cd_l2tag2)
7f12ad74
GR		 1582 return;
1583
1584 /* grab the next descriptor */
1585 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1586
1587 i++;
1588 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1589
1590 /* cpu_to_le32 and assign to struct fields */
1591 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1592 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 1593 context_desc->rsvd = cpu_to_le16(0);
7f12ad74
GR		 1594 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1595}
1596
71da6197
AS		 1597 /**
1598 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1599 * @skb: send buffer
1600 * @tx_flags: collected send information
71da6197
AS		 1601 *
1602 * Note: Our HW can't scatter-gather more than 8 fragments to build
1603 * a packet on the wire and so we need to figure out the cases where we
1604 * need to linearize the skb.
1605 **/
30520831 1606static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
71da6197
AS		 1607{
1608 struct skb_frag_struct *frag;
1609 bool linearize = false;
1610 unsigned int size = 0;
1611 u16 num_frags;
1612 u16 gso_segs;
1613
1614 num_frags = skb_shinfo(skb)->nr_frags;
1615 gso_segs = skb_shinfo(skb)->gso_segs;
1616
1617 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
30520831 1618 u16 j = 0;
71da6197
AS		 1619
1620 if (num_frags < (I40E_MAX_BUFFER_TXD))
1621 goto linearize_chk_done;
1622 /* try the simple math, if we have too many frags per segment */
1623 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1624 I40E_MAX_BUFFER_TXD) {
1625 linearize = true;
1626 goto linearize_chk_done;
1627 }
1628 frag = &skb_shinfo(skb)->frags[0];
71da6197
AS		 1629 /* we might still have more fragments per segment */
1630 do {
1631 size += skb_frag_size(frag);
1632 frag++; j++;
30520831
ASJ		 1633 if ((size >= skb_shinfo(skb)->gso_size) &&
1634 (j < I40E_MAX_BUFFER_TXD)) {
1635 size = (size % skb_shinfo(skb)->gso_size);
1636 j = (size) ? 1 : 0;
1637 }
71da6197 1638 if (j == I40E_MAX_BUFFER_TXD) {
30520831
ASJ		 1639 linearize = true;
1640 break;
71da6197
AS		 1641 }
1642 num_frags--;
1643 } while (num_frags);
1644 } else {
1645 if (num_frags >= I40E_MAX_BUFFER_TXD)
1646 linearize = true;
1647 }
1648
1649linearize_chk_done:
1650 return linearize;
1651}
1652
8f6a2b05
JB		 1653/**
1654 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1655 * @tx_ring: the ring to be checked
1656 * @size: the size buffer we want to assure is available
1657 *
1658 * Returns -EBUSY if a stop is needed, else 0
1659 **/
1660static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1661{
1662 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1663 /* Memory barrier before checking head and tail */
1664 smp_mb();
1665
1666 /* Check again in a case another CPU has just made room available. */
1667 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1668 return -EBUSY;
1669
1670 /* A reprieve! - use start_queue because it doesn't call schedule */
1671 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1672 ++tx_ring->tx_stats.restart_queue;
1673 return 0;
1674}
1675
1676/**
1677 * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1678 * @tx_ring: the ring to be checked
1679 * @size: the size buffer we want to assure is available
1680 *
1681 * Returns 0 if stop is not needed
1682 **/
3e587cf3 1683static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
8f6a2b05
JB		 1684{
1685 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1686 return 0;
1687 return __i40evf_maybe_stop_tx(tx_ring, size);
1688}
1689
7f12ad74 1690/**
3e587cf3 1691 * i40evf_tx_map - Build the Tx descriptor
7f12ad74
GR		 1692 * @tx_ring: ring to send buffer on
1693 * @skb: send buffer
1694 * @first: first buffer info buffer to use
1695 * @tx_flags: collected send information
1696 * @hdr_len: size of the packet header
1697 * @td_cmd: the command field in the descriptor
1698 * @td_offset: offset for checksum or crc
1699 **/
3e587cf3
JB		 1700static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1701 struct i40e_tx_buffer *first, u32 tx_flags,
1702 const u8 hdr_len, u32 td_cmd, u32 td_offset)
7f12ad74
GR		 1703{
1704 unsigned int data_len = skb->data_len;
1705 unsigned int size = skb_headlen(skb);
1706 struct skb_frag_struct *frag;
1707 struct i40e_tx_buffer *tx_bi;
1708 struct i40e_tx_desc *tx_desc;
1709 u16 i = tx_ring->next_to_use;
1710 u32 td_tag = 0;
1711 dma_addr_t dma;
1712 u16 gso_segs;
1713
1714 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1715 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1716 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1717 I40E_TX_FLAGS_VLAN_SHIFT;
1718 }
1719
1720 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1721 gso_segs = skb_shinfo(skb)->gso_segs;
1722 else
1723 gso_segs = 1;
1724
1725 /* multiply data chunks by size of headers */
1726 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1727 first->gso_segs = gso_segs;
1728 first->skb = skb;
1729 first->tx_flags = tx_flags;
1730
1731 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1732
1733 tx_desc = I40E_TX_DESC(tx_ring, i);
1734 tx_bi = first;
1735
1736 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1737 if (dma_mapping_error(tx_ring->dev, dma))
1738 goto dma_error;
1739
1740 /* record length, and DMA address */
1741 dma_unmap_len_set(tx_bi, len, size);
1742 dma_unmap_addr_set(tx_bi, dma, dma);
1743
1744 tx_desc->buffer_addr = cpu_to_le64(dma);
1745
1746 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1747 tx_desc->cmd_type_offset_bsz =
1748 build_ctob(td_cmd, td_offset,
1749 I40E_MAX_DATA_PER_TXD, td_tag);
1750
1751 tx_desc++;
1752 i++;
1753 if (i == tx_ring->count) {
1754 tx_desc = I40E_TX_DESC(tx_ring, 0);
1755 i = 0;
1756 }
1757
1758 dma += I40E_MAX_DATA_PER_TXD;
1759 size -= I40E_MAX_DATA_PER_TXD;
1760
1761 tx_desc->buffer_addr = cpu_to_le64(dma);
1762 }
1763
1764 if (likely(!data_len))
1765 break;
1766
1767 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1768 size, td_tag);
1769
1770 tx_desc++;
1771 i++;
1772 if (i == tx_ring->count) {
1773 tx_desc = I40E_TX_DESC(tx_ring, 0);
1774 i = 0;
1775 }
1776
1777 size = skb_frag_size(frag);
1778 data_len -= size;
1779
1780 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1781 DMA_TO_DEVICE);
1782
1783 tx_bi = &tx_ring->tx_bi[i];
1784 }
1785
1943d8ba
JB		 1786 /* Place RS bit on last descriptor of any packet that spans across the
1787 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1788 */
1789#define WB_STRIDE 0x3
1790 if (((i & WB_STRIDE) != WB_STRIDE) &&
1791 (first <= &tx_ring->tx_bi[i]) &&
1792 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1793 tx_desc->cmd_type_offset_bsz =
1794 build_ctob(td_cmd, td_offset, size, td_tag) |
1795 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1796 I40E_TXD_QW1_CMD_SHIFT);
1797 } else {
1798 tx_desc->cmd_type_offset_bsz =
1799 build_ctob(td_cmd, td_offset, size, td_tag) |
1800 cpu_to_le64((u64)I40E_TXD_CMD <<
1801 I40E_TXD_QW1_CMD_SHIFT);
1802 }
7f12ad74
GR		 1803
1804 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1805 tx_ring->queue_index),
1806 first->bytecount);
1807
7f12ad74
GR		 1808 /* Force memory writes to complete before letting h/w
1809 * know there are new descriptors to fetch. (Only
1810 * applicable for weak-ordered memory model archs,
1811 * such as IA-64).
1812 */
1813 wmb();
1814
1815 /* set next_to_watch value indicating a packet is present */
1816 first->next_to_watch = tx_desc;
1817
1818 i++;
1819 if (i == tx_ring->count)
1820 i = 0;
1821
1822 tx_ring->next_to_use = i;
1823
8f6a2b05 1824 i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
7f12ad74 1825 /* notify HW of packet */
8f6a2b05
JB		 1826 if (!skb->xmit_more ||
1827 netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1828 tx_ring->queue_index)))
1829 writel(i, tx_ring->tail);
489ce7a4
JB		 1830 else
1831 prefetchw(tx_desc + 1);
7f12ad74
GR		 1832
1833 return;
1834
1835dma_error:
1836 dev_info(tx_ring->dev, "TX DMA map failed\n");
1837
1838 /* clear dma mappings for failed tx_bi map */
1839 for (;;) {
1840 tx_bi = &tx_ring->tx_bi[i];
1841 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1842 if (tx_bi == first)
1843 break;
1844 if (i == 0)
1845 i = tx_ring->count;
1846 i--;
1847 }
1848
1849 tx_ring->next_to_use = i;
1850}
1851
7f12ad74 1852/**
3e587cf3 1853 * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
7f12ad74
GR		 1854 * @skb: send buffer
1855 * @tx_ring: ring to send buffer on
1856 *
1857 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1858 * there is not enough descriptors available in this ring since we need at least
1859 * one descriptor.
1860 **/
3e587cf3
JB		 1861static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1862 struct i40e_ring *tx_ring)
7f12ad74 1863{
7f12ad74 1864 unsigned int f;
7f12ad74
GR		 1865 int count = 0;
1866
1867 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1868 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 1869 * + 4 desc gap to avoid the cache line where head is,
7f12ad74
GR		 1870 * + 1 desc for context descriptor,
1871 * otherwise try next time
1872 */
7f12ad74
GR		 1873 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1874 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 1875
7f12ad74 1876 count += TXD_USE_COUNT(skb_headlen(skb));
8f6a2b05 1877 if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
7f12ad74
GR		 1878 tx_ring->tx_stats.tx_busy++;
1879 return 0;
1880 }
1881 return count;
1882}
1883
1884/**
1885 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1886 * @skb: send buffer
1887 * @tx_ring: ring to send buffer on
1888 *
1889 * Returns NETDEV_TX_OK if sent, else an error code
1890 **/
1891static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1892 struct i40e_ring *tx_ring)
1893{
1894 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1895 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1896 struct i40e_tx_buffer *first;
1897 u32 td_offset = 0;
1898 u32 tx_flags = 0;
1899 __be16 protocol;
1900 u32 td_cmd = 0;
1901 u8 hdr_len = 0;
1902 int tso;
3e587cf3 1903 if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
7f12ad74
GR		 1904 return NETDEV_TX_BUSY;
1905
1906 /* prepare the xmit flags */
3e587cf3 1907 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
7f12ad74
GR		 1908 goto out_drop;
1909
1910 /* obtain protocol of skb */
a12c4158 1911 protocol = vlan_get_protocol(skb);
7f12ad74
GR		 1912
1913 /* record the location of the first descriptor for this packet */
1914 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1915
1916 /* setup IPv4/IPv6 offloads */
1917 if (protocol == htons(ETH_P_IP))
1918 tx_flags |= I40E_TX_FLAGS_IPV4;
1919 else if (protocol == htons(ETH_P_IPV6))
1920 tx_flags |= I40E_TX_FLAGS_IPV6;
1921
89232c3b 1922 tso = i40e_tso(tx_ring, skb, &hdr_len,
7f12ad74
GR		 1923 &cd_type_cmd_tso_mss, &cd_tunneling);
1924
1925 if (tso < 0)
1926 goto out_drop;
1927 else if (tso)
1928 tx_flags |= I40E_TX_FLAGS_TSO;
1929
2fc3d715 1930 if (i40e_chk_linearize(skb, tx_flags)) {
71da6197
AS		 1931 if (skb_linearize(skb))
1932 goto out_drop;
2fc3d715
ASJ		 1933 tx_ring->tx_stats.tx_linearize++;
1934 }
7f12ad74
GR		 1935 skb_tx_timestamp(skb);
1936
1937 /* always enable CRC insertion offload */
1938 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1939
1940 /* Always offload the checksum, since it's in the data descriptor */
1941 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1942 tx_flags |= I40E_TX_FLAGS_CSUM;
1943
89232c3b 1944 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
7f12ad74
GR		 1945 tx_ring, &cd_tunneling);
1946 }
1947
1948 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1949 cd_tunneling, cd_l2tag2);
1950
3e587cf3
JB		 1951 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1952 td_cmd, td_offset);
7f12ad74 1953
7f12ad74
GR		 1954 return NETDEV_TX_OK;
1955
1956out_drop:
1957 dev_kfree_skb_any(skb);
1958 return NETDEV_TX_OK;
1959}
1960
1961/**
1962 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1963 * @skb: send buffer
1964 * @netdev: network interface device structure
1965 *
1966 * Returns NETDEV_TX_OK if sent, else an error code
1967 **/
1968netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1969{
1970 struct i40evf_adapter *adapter = netdev_priv(netdev);
1971 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1972
1973 /* hardware can't handle really short frames, hardware padding works
1974 * beyond this point
1975 */
1976 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1977 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1978 return NETDEV_TX_OK;
1979 skb->len = I40E_MIN_TX_LEN;
1980 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1981 }
1982
1983 return i40e_xmit_frame_ring(skb, tx_ring);
1984}
Linux kernel - Deliverables
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