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igb: Support to read and export SFF-8472/8079 data
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
82bbcdeb
JP		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
9d5c8243 34#include <linux/types.h>
2d064c06 35#include <linux/if_ether.h>
441fc6fd 36#include <linux/i2c.h>
9d5c8243
AK		 37
38#include "e1000_mac.h"
39#include "e1000_82575.h"
f96a8a0b 40#include "e1000_i210.h"
9d5c8243
AK		 41
42static s32 igb_get_invariants_82575(struct e1000_hw *);
43static s32 igb_acquire_phy_82575(struct e1000_hw *);
44static void igb_release_phy_82575(struct e1000_hw *);
45static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46static void igb_release_nvm_82575(struct e1000_hw *);
47static s32 igb_check_for_link_82575(struct e1000_hw *);
48static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49static s32 igb_init_hw_82575(struct e1000_hw *);
50static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 52static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 54static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 55static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243 56static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
da02cde1
CW		 57static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
9d5c8243 59static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 60static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 61static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 64static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66static s32 igb_get_phy_id_82575(struct e1000_hw *);
67static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68static bool igb_sgmii_active_82575(struct e1000_hw *);
69static s32 igb_reset_init_script_82575(struct e1000_hw *);
70static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 71static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 72static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 73static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 75static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 77static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80#define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
4085f746
NN		 83/**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91{
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
f96a8a0b
CW		 103 case e1000_i210:
104 case e1000_i211:
4085f746
NN		 105 reg = rd32(E1000_MDICNFG);
106 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
107 break;
108 default:
109 break;
110 }
111 return ext_mdio;
112}
113
73bfcd9a
AA		 114/**
115 * igb_init_phy_params_82575 - Init PHY func ptrs.
116 * @hw: pointer to the HW structure
117 **/
118static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
119{
120 struct e1000_phy_info *phy = &hw->phy;
121 s32 ret_val = 0;
122 u32 ctrl_ext;
123
124 if (hw->phy.media_type != e1000_media_type_copper) {
125 phy->type = e1000_phy_none;
126 goto out;
127 }
128
129 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
130 phy->reset_delay_us = 100;
131
132 ctrl_ext = rd32(E1000_CTRL_EXT);
133
134 if (igb_sgmii_active_82575(hw)) {
135 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
136 ctrl_ext |= E1000_CTRL_I2C_ENA;
137 } else {
138 phy->ops.reset = igb_phy_hw_reset;
139 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
140 }
141
142 wr32(E1000_CTRL_EXT, ctrl_ext);
143 igb_reset_mdicnfg_82580(hw);
144
145 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
146 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
147 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
148 } else {
149 switch (hw->mac.type) {
150 case e1000_82580:
151 case e1000_i350:
152 phy->ops.read_reg = igb_read_phy_reg_82580;
153 phy->ops.write_reg = igb_write_phy_reg_82580;
154 break;
155 case e1000_i210:
156 case e1000_i211:
157 phy->ops.read_reg = igb_read_phy_reg_gs40g;
158 phy->ops.write_reg = igb_write_phy_reg_gs40g;
159 break;
160 default:
161 phy->ops.read_reg = igb_read_phy_reg_igp;
162 phy->ops.write_reg = igb_write_phy_reg_igp;
163 }
164 }
165
166 /* set lan id */
167 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
168 E1000_STATUS_FUNC_SHIFT;
169
170 /* Set phy->phy_addr and phy->id. */
171 ret_val = igb_get_phy_id_82575(hw);
172 if (ret_val)
173 return ret_val;
174
175 /* Verify phy id and set remaining function pointers */
176 switch (phy->id) {
177 case I347AT4_E_PHY_ID:
178 case M88E1112_E_PHY_ID:
179 case M88E1111_I_PHY_ID:
180 phy->type = e1000_phy_m88;
181 phy->ops.get_phy_info = igb_get_phy_info_m88;
182 if (phy->id == I347AT4_E_PHY_ID ||
183 phy->id == M88E1112_E_PHY_ID)
184 phy->ops.get_cable_length =
185 igb_get_cable_length_m88_gen2;
186 else
187 phy->ops.get_cable_length = igb_get_cable_length_m88;
188 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
189 break;
190 case IGP03E1000_E_PHY_ID:
191 phy->type = e1000_phy_igp_3;
192 phy->ops.get_phy_info = igb_get_phy_info_igp;
193 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
194 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
195 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
196 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
197 break;
198 case I82580_I_PHY_ID:
199 case I350_I_PHY_ID:
200 phy->type = e1000_phy_82580;
201 phy->ops.force_speed_duplex =
202 igb_phy_force_speed_duplex_82580;
203 phy->ops.get_cable_length = igb_get_cable_length_82580;
204 phy->ops.get_phy_info = igb_get_phy_info_82580;
205 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
206 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
207 break;
208 case I210_I_PHY_ID:
209 phy->type = e1000_phy_i210;
210 phy->ops.check_polarity = igb_check_polarity_m88;
211 phy->ops.get_phy_info = igb_get_phy_info_m88;
212 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
213 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
214 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
215 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
216 break;
217 default:
218 ret_val = -E1000_ERR_PHY;
219 goto out;
220 }
221
222out:
223 return ret_val;
224}
225
56d8c27f
AA		 226/**
227 * igb_init_nvm_params_82575 - Init NVM func ptrs.
228 * @hw: pointer to the HW structure
229 **/
230s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
231{
232 struct e1000_nvm_info *nvm = &hw->nvm;
233 u32 eecd = rd32(E1000_EECD);
234 u16 size;
235
236 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
237 E1000_EECD_SIZE_EX_SHIFT);
238 /* Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
240 */
241 size += NVM_WORD_SIZE_BASE_SHIFT;
242
243 /* Just in case size is out of range, cap it to the largest
244 * EEPROM size supported
245 */
246 if (size > 15)
247 size = 15;
248
249 nvm->word_size = 1 << size;
250 if (hw->mac.type < e1000_i210) {
251 nvm->opcode_bits = 8;
252 nvm->delay_usec = 1;
253
254 switch (nvm->override) {
255 case e1000_nvm_override_spi_large:
256 nvm->page_size = 32;
257 nvm->address_bits = 16;
258 break;
259 case e1000_nvm_override_spi_small:
260 nvm->page_size = 8;
261 nvm->address_bits = 8;
262 break;
263 default:
264 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
265 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
266 16 : 8;
267 break;
268 }
269 if (nvm->word_size == (1 << 15))
270 nvm->page_size = 128;
271
272 nvm->type = e1000_nvm_eeprom_spi;
273 } else {
274 nvm->type = e1000_nvm_flash_hw;
275 }
276
277 /* NVM Function Pointers */
278 switch (hw->mac.type) {
279 case e1000_82580:
280 nvm->ops.validate = igb_validate_nvm_checksum_82580;
281 nvm->ops.update = igb_update_nvm_checksum_82580;
282 nvm->ops.acquire = igb_acquire_nvm_82575;
283 nvm->ops.release = igb_release_nvm_82575;
284 if (nvm->word_size < (1 << 15))
285 nvm->ops.read = igb_read_nvm_eerd;
286 else
287 nvm->ops.read = igb_read_nvm_spi;
288 nvm->ops.write = igb_write_nvm_spi;
289 break;
290 case e1000_i350:
291 nvm->ops.validate = igb_validate_nvm_checksum_i350;
292 nvm->ops.update = igb_update_nvm_checksum_i350;
293 nvm->ops.acquire = igb_acquire_nvm_82575;
294 nvm->ops.release = igb_release_nvm_82575;
295 if (nvm->word_size < (1 << 15))
296 nvm->ops.read = igb_read_nvm_eerd;
297 else
298 nvm->ops.read = igb_read_nvm_spi;
299 nvm->ops.write = igb_write_nvm_spi;
300 break;
301 case e1000_i210:
302 nvm->ops.validate = igb_validate_nvm_checksum_i210;
303 nvm->ops.update = igb_update_nvm_checksum_i210;
304 nvm->ops.acquire = igb_acquire_nvm_i210;
305 nvm->ops.release = igb_release_nvm_i210;
306 nvm->ops.read = igb_read_nvm_srrd_i210;
307 nvm->ops.write = igb_write_nvm_srwr_i210;
308 nvm->ops.valid_led_default = igb_valid_led_default_i210;
309 break;
310 case e1000_i211:
311 nvm->ops.acquire = igb_acquire_nvm_i210;
312 nvm->ops.release = igb_release_nvm_i210;
313 nvm->ops.read = igb_read_nvm_i211;
314 nvm->ops.valid_led_default = igb_valid_led_default_i210;
315 nvm->ops.validate = NULL;
316 nvm->ops.update = NULL;
317 nvm->ops.write = NULL;
318 break;
319 default:
320 nvm->ops.validate = igb_validate_nvm_checksum;
321 nvm->ops.update = igb_update_nvm_checksum;
322 nvm->ops.acquire = igb_acquire_nvm_82575;
323 nvm->ops.release = igb_release_nvm_82575;
324 if (nvm->word_size < (1 << 15))
325 nvm->ops.read = igb_read_nvm_eerd;
326 else
327 nvm->ops.read = igb_read_nvm_spi;
328 nvm->ops.write = igb_write_nvm_spi;
329 break;
330 }
331
332 return 0;
333}
334
a1bf1f44
AA		 335/**
336 * igb_init_mac_params_82575 - Init MAC func ptrs.
337 * @hw: pointer to the HW structure
338 **/
339static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
340{
341 struct e1000_mac_info *mac = &hw->mac;
342 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
343
344 /* Set mta register count */
345 mac->mta_reg_count = 128;
346 /* Set rar entry count */
347 switch (mac->type) {
348 case e1000_82576:
349 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
350 break;
351 case e1000_82580:
352 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
353 break;
354 case e1000_i350:
355 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
356 break;
357 default:
358 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
359 break;
360 }
361 /* reset */
362 if (mac->type >= e1000_82580)
363 mac->ops.reset_hw = igb_reset_hw_82580;
364 else
365 mac->ops.reset_hw = igb_reset_hw_82575;
366
367 if (mac->type >= e1000_i210) {
368 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
369 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
370
371 } else {
372 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
373 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
374 }
375
376 /* Set if part includes ASF firmware */
377 mac->asf_firmware_present = true;
378 /* Set if manageability features are enabled. */
379 mac->arc_subsystem_valid =
380 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
381 ? true : false;
382 /* enable EEE on i350 parts and later parts */
383 if (mac->type >= e1000_i350)
384 dev_spec->eee_disable = false;
385 else
386 dev_spec->eee_disable = true;
387 /* physical interface link setup */
388 mac->ops.setup_physical_interface =
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? igb_setup_copper_link_82575
391 : igb_setup_serdes_link_82575;
392
393 return 0;
394}
395
9d5c8243
AK		 396static s32 igb_get_invariants_82575(struct e1000_hw *hw)
397{
9d5c8243 398 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 399 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243 400 s32 ret_val;
9d5c8243
AK		 401 u32 ctrl_ext = 0;
402
403 switch (hw->device_id) {
404 case E1000_DEV_ID_82575EB_COPPER:
405 case E1000_DEV_ID_82575EB_FIBER_SERDES:
406 case E1000_DEV_ID_82575GB_QUAD_COPPER:
407 mac->type = e1000_82575;
408 break;
2d064c06 409 case E1000_DEV_ID_82576:
9eb2341d 410 case E1000_DEV_ID_82576_NS:
747d49ba 411 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 412 case E1000_DEV_ID_82576_FIBER:
413 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 414 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 415 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 416 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 417 mac->type = e1000_82576;
418 break;
bb2ac47b
AD		 419 case E1000_DEV_ID_82580_COPPER:
420 case E1000_DEV_ID_82580_FIBER:
6493d24f 421 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 422 case E1000_DEV_ID_82580_SERDES:
423 case E1000_DEV_ID_82580_SGMII:
424 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 425 case E1000_DEV_ID_DH89XXCC_SGMII:
426 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 427 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
428 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 429 mac->type = e1000_82580;
430 break;
d2ba2ed8
AD		 431 case E1000_DEV_ID_I350_COPPER:
432 case E1000_DEV_ID_I350_FIBER:
433 case E1000_DEV_ID_I350_SERDES:
434 case E1000_DEV_ID_I350_SGMII:
435 mac->type = e1000_i350;
436 break;
f96a8a0b
CW		 437 case E1000_DEV_ID_I210_COPPER:
438 case E1000_DEV_ID_I210_COPPER_OEM1:
439 case E1000_DEV_ID_I210_COPPER_IT:
440 case E1000_DEV_ID_I210_FIBER:
441 case E1000_DEV_ID_I210_SERDES:
442 case E1000_DEV_ID_I210_SGMII:
443 mac->type = e1000_i210;
444 break;
445 case E1000_DEV_ID_I211_COPPER:
446 mac->type = e1000_i211;
447 break;
9d5c8243
AK		 448 default:
449 return -E1000_ERR_MAC_INIT;
450 break;
451 }
452
9d5c8243
AK		 453 /* Set media type */
454 /*
455 * The 82575 uses bits 22:23 for link mode. The mode can be changed
456 * based on the EEPROM. We cannot rely upon device ID. There
457 * is no distinguishable difference between fiber and internal
458 * SerDes mode on the 82575. There can be an external PHY attached
459 * on the SGMII interface. For this, we'll set sgmii_active to true.
460 */
a6053d76 461 hw->phy.media_type = e1000_media_type_copper;
9d5c8243
AK		 462 dev_spec->sgmii_active = false;
463
464 ctrl_ext = rd32(E1000_CTRL_EXT);
2fb02a26
AD		 465 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
466 case E1000_CTRL_EXT_LINK_MODE_SGMII:
9d5c8243 467 dev_spec->sgmii_active = true;
2fb02a26 468 break;
bb2ac47b 469 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26
AD		 470 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
471 hw->phy.media_type = e1000_media_type_internal_serdes;
2fb02a26
AD		 472 break;
473 default:
2fb02a26 474 break;
9d5c8243 475 }
2fb02a26 476
a6053d76
AA		 477 /* mac initialization and operations */
478 ret_val = igb_init_mac_params_82575(hw);
479 if (ret_val)
480 goto out;
9d5c8243
AK		 481
482 /* NVM initialization */
a6053d76
AA		 483 ret_val = igb_init_nvm_params_82575(hw);
484 if (ret_val)
485 goto out;
9d5c8243 486
6b78bb1d
CW		 487 /* if part supports SR-IOV then initialize mailbox parameters */
488 switch (mac->type) {
489 case e1000_82576:
490 case e1000_i350:
a0c98605 491 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 492 break;
493 default:
494 break;
495 }
a0c98605 496
9d5c8243 497 /* setup PHY parameters */
a6053d76 498 ret_val = igb_init_phy_params_82575(hw);
19e588e7 499
a6053d76
AA		 500out:
501 return ret_val;
9d5c8243
AK		 502}
503
504/**
733596be 505 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 506 * @hw: pointer to the HW structure
507 *
508 * Acquire access rights to the correct PHY. This is a
509 * function pointer entry point called by the api module.
510 **/
511static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
512{
008c3422 513 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 514
008c3422
AD		 515 if (hw->bus.func == E1000_FUNC_1)
516 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 517 else if (hw->bus.func == E1000_FUNC_2)
518 mask = E1000_SWFW_PHY2_SM;
519 else if (hw->bus.func == E1000_FUNC_3)
520 mask = E1000_SWFW_PHY3_SM;
9d5c8243 521
f96a8a0b 522 return hw->mac.ops.acquire_swfw_sync(hw, mask);
9d5c8243
AK		 523}
524
525/**
733596be 526 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 527 * @hw: pointer to the HW structure
528 *
529 * A wrapper to release access rights to the correct PHY. This is a
530 * function pointer entry point called by the api module.
531 **/
532static void igb_release_phy_82575(struct e1000_hw *hw)
533{
008c3422
AD		 534 u16 mask = E1000_SWFW_PHY0_SM;
535
536 if (hw->bus.func == E1000_FUNC_1)
537 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 538 else if (hw->bus.func == E1000_FUNC_2)
539 mask = E1000_SWFW_PHY2_SM;
540 else if (hw->bus.func == E1000_FUNC_3)
541 mask = E1000_SWFW_PHY3_SM;
9d5c8243 542
f96a8a0b 543 hw->mac.ops.release_swfw_sync(hw, mask);
9d5c8243
AK		 544}
545
546/**
733596be 547 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 548 * @hw: pointer to the HW structure
549 * @offset: register offset to be read
550 * @data: pointer to the read data
551 *
552 * Reads the PHY register at offset using the serial gigabit media independent
553 * interface and stores the retrieved information in data.
554 **/
555static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
556 u16 *data)
557{
bf6f7a92 558 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 559
560 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 561 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 562 goto out;
9d5c8243
AK		 563 }
564
bf6f7a92
AD		 565 ret_val = hw->phy.ops.acquire(hw);
566 if (ret_val)
567 goto out;
9d5c8243 568
bf6f7a92 569 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 570
bf6f7a92
AD		 571 hw->phy.ops.release(hw);
572
573out:
574 return ret_val;
9d5c8243
AK		 575}
576
577/**
733596be 578 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 579 * @hw: pointer to the HW structure
580 * @offset: register offset to write to
581 * @data: data to write at register offset
582 *
583 * Writes the data to PHY register at the offset using the serial gigabit
584 * media independent interface.
585 **/
586static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
587 u16 data)
588{
bf6f7a92
AD		 589 s32 ret_val = -E1000_ERR_PARAM;
590
9d5c8243
AK		 591
592 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 593 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 594 goto out;
9d5c8243
AK		 595 }
596
bf6f7a92
AD		 597 ret_val = hw->phy.ops.acquire(hw);
598 if (ret_val)
599 goto out;
9d5c8243 600
bf6f7a92 601 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 602
bf6f7a92
AD		 603 hw->phy.ops.release(hw);
604
605out:
606 return ret_val;
9d5c8243
AK		 607}
608
609/**
733596be 610 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 611 * @hw: pointer to the HW structure
612 *
652fff32 613 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 614 * sgmi interface.
615 **/
616static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
617{
618 struct e1000_phy_info *phy = &hw->phy;
619 s32 ret_val = 0;
620 u16 phy_id;
2fb02a26 621 u32 ctrl_ext;
4085f746 622 u32 mdic;
9d5c8243
AK		 623
624 /*
625 * For SGMII PHYs, we try the list of possible addresses until
626 * we find one that works. For non-SGMII PHYs
627 * (e.g. integrated copper PHYs), an address of 1 should
628 * work. The result of this function should mean phy->phy_addr
629 * and phy->id are set correctly.
630 */
631 if (!(igb_sgmii_active_82575(hw))) {
632 phy->addr = 1;
633 ret_val = igb_get_phy_id(hw);
634 goto out;
635 }
636
4085f746
NN		 637 if (igb_sgmii_uses_mdio_82575(hw)) {
638 switch (hw->mac.type) {
639 case e1000_82575:
640 case e1000_82576:
641 mdic = rd32(E1000_MDIC);
642 mdic &= E1000_MDIC_PHY_MASK;
643 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
644 break;
645 case e1000_82580:
646 case e1000_i350:
f96a8a0b
CW		 647 case e1000_i210:
648 case e1000_i211:
4085f746
NN		 649 mdic = rd32(E1000_MDICNFG);
650 mdic &= E1000_MDICNFG_PHY_MASK;
651 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
652 break;
653 default:
654 ret_val = -E1000_ERR_PHY;
655 goto out;
656 break;
657 }
658 ret_val = igb_get_phy_id(hw);
659 goto out;
660 }
661
2fb02a26
AD		 662 /* Power on sgmii phy if it is disabled */
663 ctrl_ext = rd32(E1000_CTRL_EXT);
664 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
665 wrfl();
666 msleep(300);
667
9d5c8243
AK		 668 /*
669 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
670 * Therefore, we need to test 1-7
671 */
672 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
673 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
674 if (ret_val == 0) {
652fff32
AK		 675 hw_dbg("Vendor ID 0x%08X read at address %u\n",
676 phy_id, phy->addr);
9d5c8243
AK		 677 /*
678 * At the time of this writing, The M88 part is
679 * the only supported SGMII PHY product.
680 */
681 if (phy_id == M88_VENDOR)
682 break;
683 } else {
652fff32 684 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 685 }
686 }
687
688 /* A valid PHY type couldn't be found. */
689 if (phy->addr == 8) {
690 phy->addr = 0;
691 ret_val = -E1000_ERR_PHY;
692 goto out;
2fb02a26
AD		 693 } else {
694 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 695 }
696
2fb02a26
AD		 697 /* restore previous sfp cage power state */
698 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 699
700out:
701 return ret_val;
702}
703
704/**
733596be 705 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 706 * @hw: pointer to the HW structure
707 *
708 * Resets the PHY using the serial gigabit media independent interface.
709 **/
710static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
711{
712 s32 ret_val;
713
714 /*
715 * This isn't a true "hard" reset, but is the only reset
716 * available to us at this time.
717 */
718
652fff32 719 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 720
721 /*
722 * SFP documentation requires the following to configure the SPF module
723 * to work on SGMII. No further documentation is given.
724 */
a8d2a0c2 725 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 726 if (ret_val)
727 goto out;
728
729 ret_val = igb_phy_sw_reset(hw);
730
731out:
732 return ret_val;
733}
734
735/**
733596be 736 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 737 * @hw: pointer to the HW structure
738 * @active: true to enable LPLU, false to disable
739 *
740 * Sets the LPLU D0 state according to the active flag. When
741 * activating LPLU this function also disables smart speed
742 * and vice versa. LPLU will not be activated unless the
743 * device autonegotiation advertisement meets standards of
744 * either 10 or 10/100 or 10/100/1000 at all duplexes.
745 * This is a function pointer entry point only called by
746 * PHY setup routines.
747 **/
748static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
749{
750 struct e1000_phy_info *phy = &hw->phy;
751 s32 ret_val;
752 u16 data;
753
a8d2a0c2 754 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 755 if (ret_val)
756 goto out;
757
758 if (active) {
759 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 760 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 761 data);
9d5c8243
AK		 762 if (ret_val)
763 goto out;
764
765 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 766 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 767 &data);
9d5c8243 768 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 769 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 770 data);
9d5c8243
AK		 771 if (ret_val)
772 goto out;
773 } else {
774 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 776 data);
9d5c8243
AK		 777 /*
778 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
779 * during Dx states where the power conservation is most
780 * important. During driver activity we should enable
781 * SmartSpeed, so performance is maintained.
782 */
783 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 784 ret_val = phy->ops.read_reg(hw,
652fff32 785 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 786 if (ret_val)
787 goto out;
788
789 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 790 ret_val = phy->ops.write_reg(hw,
652fff32 791 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 792 if (ret_val)
793 goto out;
794 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 795 ret_val = phy->ops.read_reg(hw,
652fff32 796 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 797 if (ret_val)
798 goto out;
799
800 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 801 ret_val = phy->ops.write_reg(hw,
652fff32 802 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 803 if (ret_val)
804 goto out;
805 }
806 }
807
808out:
809 return ret_val;
810}
811
da02cde1
CW		 812/**
813 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
814 * @hw: pointer to the HW structure
815 * @active: true to enable LPLU, false to disable
816 *
817 * Sets the LPLU D0 state according to the active flag. When
818 * activating LPLU this function also disables smart speed
819 * and vice versa. LPLU will not be activated unless the
820 * device autonegotiation advertisement meets standards of
821 * either 10 or 10/100 or 10/100/1000 at all duplexes.
822 * This is a function pointer entry point only called by
823 * PHY setup routines.
824 **/
825static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
826{
827 struct e1000_phy_info *phy = &hw->phy;
828 s32 ret_val = 0;
829 u16 data;
830
831 data = rd32(E1000_82580_PHY_POWER_MGMT);
832
833 if (active) {
834 data |= E1000_82580_PM_D0_LPLU;
835
836 /* When LPLU is enabled, we should disable SmartSpeed */
837 data &= ~E1000_82580_PM_SPD;
838 } else {
839 data &= ~E1000_82580_PM_D0_LPLU;
840
841 /*
842 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
843 * during Dx states where the power conservation is most
844 * important. During driver activity we should enable
845 * SmartSpeed, so performance is maintained.
846 */
847 if (phy->smart_speed == e1000_smart_speed_on)
848 data |= E1000_82580_PM_SPD;
849 else if (phy->smart_speed == e1000_smart_speed_off)
850 data &= ~E1000_82580_PM_SPD; }
851
852 wr32(E1000_82580_PHY_POWER_MGMT, data);
853 return ret_val;
854}
855
856/**
857 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
858 * @hw: pointer to the HW structure
859 * @active: boolean used to enable/disable lplu
860 *
861 * Success returns 0, Failure returns 1
862 *
863 * The low power link up (lplu) state is set to the power management level D3
864 * and SmartSpeed is disabled when active is true, else clear lplu for D3
865 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
866 * is used during Dx states where the power conservation is most important.
867 * During driver activity, SmartSpeed should be enabled so performance is
868 * maintained.
869 **/
870s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
871{
872 struct e1000_phy_info *phy = &hw->phy;
873 s32 ret_val = 0;
874 u16 data;
875
876 data = rd32(E1000_82580_PHY_POWER_MGMT);
877
878 if (!active) {
879 data &= ~E1000_82580_PM_D3_LPLU;
880 /*
881 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
882 * during Dx states where the power conservation is most
883 * important. During driver activity we should enable
884 * SmartSpeed, so performance is maintained.
885 */
886 if (phy->smart_speed == e1000_smart_speed_on)
887 data |= E1000_82580_PM_SPD;
888 else if (phy->smart_speed == e1000_smart_speed_off)
889 data &= ~E1000_82580_PM_SPD;
890 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
891 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
892 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
893 data |= E1000_82580_PM_D3_LPLU;
894 /* When LPLU is enabled, we should disable SmartSpeed */
895 data &= ~E1000_82580_PM_SPD;
896 }
897
898 wr32(E1000_82580_PHY_POWER_MGMT, data);
899 return ret_val;
900}
901
9d5c8243 902/**
733596be 903 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 904 * @hw: pointer to the HW structure
905 *
652fff32 906 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 907 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
908 * Return successful if access grant bit set, else clear the request for
909 * EEPROM access and return -E1000_ERR_NVM (-1).
910 **/
911static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
912{
913 s32 ret_val;
914
f96a8a0b 915 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 916 if (ret_val)
917 goto out;
918
919 ret_val = igb_acquire_nvm(hw);
920
921 if (ret_val)
f96a8a0b 922 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 923
924out:
925 return ret_val;
926}
927
928/**
733596be 929 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 930 * @hw: pointer to the HW structure
931 *
932 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
933 * then release the semaphores acquired.
934 **/
935static void igb_release_nvm_82575(struct e1000_hw *hw)
936{
937 igb_release_nvm(hw);
f96a8a0b 938 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 939}
940
941/**
733596be 942 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 943 * @hw: pointer to the HW structure
944 * @mask: specifies which semaphore to acquire
945 *
946 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
947 * will also specify which port we're acquiring the lock for.
948 **/
949static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
950{
951 u32 swfw_sync;
952 u32 swmask = mask;
953 u32 fwmask = mask << 16;
954 s32 ret_val = 0;
955 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
956
957 while (i < timeout) {
958 if (igb_get_hw_semaphore(hw)) {
959 ret_val = -E1000_ERR_SWFW_SYNC;
960 goto out;
961 }
962
963 swfw_sync = rd32(E1000_SW_FW_SYNC);
964 if (!(swfw_sync & (fwmask | swmask)))
965 break;
966
967 /*
968 * Firmware currently using resource (fwmask)
969 * or other software thread using resource (swmask)
970 */
971 igb_put_hw_semaphore(hw);
972 mdelay(5);
973 i++;
974 }
975
976 if (i == timeout) {
652fff32 977 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 978 ret_val = -E1000_ERR_SWFW_SYNC;
979 goto out;
980 }
981
982 swfw_sync |= swmask;
983 wr32(E1000_SW_FW_SYNC, swfw_sync);
984
985 igb_put_hw_semaphore(hw);
986
987out:
988 return ret_val;
989}
990
991/**
733596be 992 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 993 * @hw: pointer to the HW structure
994 * @mask: specifies which semaphore to acquire
995 *
996 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
997 * will also specify which port we're releasing the lock for.
998 **/
999static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1000{
1001 u32 swfw_sync;
1002
1003 while (igb_get_hw_semaphore(hw) != 0);
1004 /* Empty */
1005
1006 swfw_sync = rd32(E1000_SW_FW_SYNC);
1007 swfw_sync &= ~mask;
1008 wr32(E1000_SW_FW_SYNC, swfw_sync);
1009
1010 igb_put_hw_semaphore(hw);
1011}
1012
1013/**
733596be 1014 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 1015 * @hw: pointer to the HW structure
1016 *
1017 * Read the management control register for the config done bit for
1018 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1019 * to read the config done bit, so an error is *ONLY* logged and returns
1020 * 0. If we were to return with error, EEPROM-less silicon
1021 * would not be able to be reset or change link.
1022 **/
1023static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1024{
1025 s32 timeout = PHY_CFG_TIMEOUT;
1026 s32 ret_val = 0;
1027 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1028
1029 if (hw->bus.func == 1)
1030 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 1031 else if (hw->bus.func == E1000_FUNC_2)
1032 mask = E1000_NVM_CFG_DONE_PORT_2;
1033 else if (hw->bus.func == E1000_FUNC_3)
1034 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 1035
1036 while (timeout) {
1037 if (rd32(E1000_EEMNGCTL) & mask)
1038 break;
1039 msleep(1);
1040 timeout--;
1041 }
1042 if (!timeout)
652fff32 1043 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 1044
1045 /* If EEPROM is not marked present, init the PHY manually */
1046 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1047 (hw->phy.type == e1000_phy_igp_3))
1048 igb_phy_init_script_igp3(hw);
1049
1050 return ret_val;
1051}
1052
1053/**
733596be 1054 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 1055 * @hw: pointer to the HW structure
1056 *
1057 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1058 * use the generic interface for determining link.
1059 **/
1060static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1061{
1062 s32 ret_val;
1063 u16 speed, duplex;
1064
70d92f86 1065 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 1066 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 1067 &duplex);
5d0932a5
AD		 1068 /*
1069 * Use this flag to determine if link needs to be checked or
1070 * not. If we have link clear the flag so that we do not
1071 * continue to check for link.
1072 */
1073 hw->mac.get_link_status = !hw->mac.serdes_has_link;
daf56e40
CW		 1074
1075 /* Configure Flow Control now that Auto-Neg has completed.
1076 * First, we need to restore the desired flow control
1077 * settings because we may have had to re-autoneg with a
1078 * different link partner.
1079 */
1080 ret_val = igb_config_fc_after_link_up(hw);
1081 if (ret_val)
1082 hw_dbg("Error configuring flow control\n");
5d0932a5 1083 } else {
9d5c8243 1084 ret_val = igb_check_for_copper_link(hw);
5d0932a5 1085 }
9d5c8243
AK		 1086
1087 return ret_val;
1088}
70d92f86 1089
88a268c1
NN		 1090/**
1091 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1092 * @hw: pointer to the HW structure
1093 **/
1094void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1095{
1096 u32 reg;
1097
1098
1099 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1100 !igb_sgmii_active_82575(hw))
1101 return;
1102
1103 /* Enable PCS to turn on link */
1104 reg = rd32(E1000_PCS_CFG0);
1105 reg |= E1000_PCS_CFG_PCS_EN;
1106 wr32(E1000_PCS_CFG0, reg);
1107
1108 /* Power up the laser */
1109 reg = rd32(E1000_CTRL_EXT);
1110 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1111 wr32(E1000_CTRL_EXT, reg);
1112
1113 /* flush the write to verify completion */
1114 wrfl();
1115 msleep(1);
1116}
1117
9d5c8243 1118/**
733596be 1119 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 1120 * @hw: pointer to the HW structure
1121 * @speed: stores the current speed
1122 * @duplex: stores the current duplex
1123 *
652fff32 1124 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 1125 * duplex, then store the values in the pointers provided.
1126 **/
1127static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1128 u16 *duplex)
1129{
1130 struct e1000_mac_info *mac = &hw->mac;
1131 u32 pcs;
1132
1133 /* Set up defaults for the return values of this function */
1134 mac->serdes_has_link = false;
1135 *speed = 0;
1136 *duplex = 0;
1137
1138 /*
1139 * Read the PCS Status register for link state. For non-copper mode,
1140 * the status register is not accurate. The PCS status register is
1141 * used instead.
1142 */
1143 pcs = rd32(E1000_PCS_LSTAT);
1144
1145 /*
1146 * The link up bit determines when link is up on autoneg. The sync ok
1147 * gets set once both sides sync up and agree upon link. Stable link
1148 * can be determined by checking for both link up and link sync ok
1149 */
1150 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1151 mac->serdes_has_link = true;
1152
1153 /* Detect and store PCS speed */
1154 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1155 *speed = SPEED_1000;
1156 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1157 *speed = SPEED_100;
1158 } else {
1159 *speed = SPEED_10;
1160 }
1161
1162 /* Detect and store PCS duplex */
1163 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1164 *duplex = FULL_DUPLEX;
1165 } else {
1166 *duplex = HALF_DUPLEX;
1167 }
1168 }
1169
1170 return 0;
1171}
1172
2d064c06 1173/**
2fb02a26 1174 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 1175 * @hw: pointer to the HW structure
9d5c8243 1176 *
2d064c06
AD		 1177 * In the case of fiber serdes, shut down optics and PCS on driver unload
1178 * when management pass thru is not enabled.
9d5c8243 1179 **/
2fb02a26 1180void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1181{
2d064c06
AD		 1182 u32 reg;
1183
53c992fa 1184 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 1185 igb_sgmii_active_82575(hw))
2d064c06
AD		 1186 return;
1187
53c992fa 1188 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 1189 /* Disable PCS to turn off link */
1190 reg = rd32(E1000_PCS_CFG0);
1191 reg &= ~E1000_PCS_CFG_PCS_EN;
1192 wr32(E1000_PCS_CFG0, reg);
1193
1194 /* shutdown the laser */
1195 reg = rd32(E1000_CTRL_EXT);
2fb02a26 1196 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 1197 wr32(E1000_CTRL_EXT, reg);
1198
1199 /* flush the write to verify completion */
1200 wrfl();
1201 msleep(1);
1202 }
9d5c8243
AK		 1203}
1204
1205/**
733596be 1206 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 1207 * @hw: pointer to the HW structure
1208 *
1209 * This resets the hardware into a known state. This is a
1210 * function pointer entry point called by the api module.
1211 **/
1212static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1213{
1214 u32 ctrl, icr;
1215 s32 ret_val;
1216
1217 /*
1218 * Prevent the PCI-E bus from sticking if there is no TLP connection
1219 * on the last TLP read/write transaction when MAC is reset.
1220 */
1221 ret_val = igb_disable_pcie_master(hw);
1222 if (ret_val)
652fff32 1223 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 1224
009bc06e
AD		 1225 /* set the completion timeout for interface */
1226 ret_val = igb_set_pcie_completion_timeout(hw);
1227 if (ret_val) {
1228 hw_dbg("PCI-E Set completion timeout has failed.\n");
1229 }
1230
652fff32 1231 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 1232 wr32(E1000_IMC, 0xffffffff);
1233
1234 wr32(E1000_RCTL, 0);
1235 wr32(E1000_TCTL, E1000_TCTL_PSP);
1236 wrfl();
1237
1238 msleep(10);
1239
1240 ctrl = rd32(E1000_CTRL);
1241
652fff32 1242 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1243 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1244
1245 ret_val = igb_get_auto_rd_done(hw);
1246 if (ret_val) {
1247 /*
1248 * When auto config read does not complete, do not
1249 * return with an error. This can happen in situations
1250 * where there is no eeprom and prevents getting link.
1251 */
652fff32 1252 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1253 }
1254
1255 /* If EEPROM is not present, run manual init scripts */
1256 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1257 igb_reset_init_script_82575(hw);
1258
1259 /* Clear any pending interrupt events. */
1260 wr32(E1000_IMC, 0xffffffff);
1261 icr = rd32(E1000_ICR);
1262
5ac16659
AD		 1263 /* Install any alternate MAC address into RAR0 */
1264 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1265
1266 return ret_val;
1267}
1268
1269/**
733596be 1270 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1271 * @hw: pointer to the HW structure
1272 *
1273 * This inits the hardware readying it for operation.
1274 **/
1275static s32 igb_init_hw_82575(struct e1000_hw *hw)
1276{
1277 struct e1000_mac_info *mac = &hw->mac;
1278 s32 ret_val;
1279 u16 i, rar_count = mac->rar_entry_count;
1280
1281 /* Initialize identification LED */
1282 ret_val = igb_id_led_init(hw);
1283 if (ret_val) {
652fff32 1284 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1285 /* This is not fatal and we should not stop init due to this */
1286 }
1287
1288 /* Disabling VLAN filtering */
652fff32 1289 hw_dbg("Initializing the IEEE VLAN\n");
1128c756
CW		 1290 if (hw->mac.type == e1000_i350)
1291 igb_clear_vfta_i350(hw);
1292 else
1293 igb_clear_vfta(hw);
9d5c8243
AK		 1294
1295 /* Setup the receive address */
5ac16659
AD		 1296 igb_init_rx_addrs(hw, rar_count);
1297
9d5c8243 1298 /* Zero out the Multicast HASH table */
652fff32 1299 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1300 for (i = 0; i < mac->mta_reg_count; i++)
1301 array_wr32(E1000_MTA, i, 0);
1302
68d480c4
AD		 1303 /* Zero out the Unicast HASH table */
1304 hw_dbg("Zeroing the UTA\n");
1305 for (i = 0; i < mac->uta_reg_count; i++)
1306 array_wr32(E1000_UTA, i, 0);
1307
9d5c8243
AK		 1308 /* Setup link and flow control */
1309 ret_val = igb_setup_link(hw);
1310
1311 /*
1312 * Clear all of the statistics registers (clear on read). It is
1313 * important that we do this after we have tried to establish link
1314 * because the symbol error count will increment wildly if there
1315 * is no link.
1316 */
1317 igb_clear_hw_cntrs_82575(hw);
9d5c8243
AK		 1318 return ret_val;
1319}
1320
1321/**
733596be 1322 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1323 * @hw: pointer to the HW structure
1324 *
1325 * Configures the link for auto-neg or forced speed and duplex. Then we check
1326 * for link, once link is established calls to configure collision distance
1327 * and flow control are called.
1328 **/
1329static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1330{
12645a19 1331 u32 ctrl;
9d5c8243 1332 s32 ret_val;
867eb39e 1333 u32 phpm_reg;
9d5c8243
AK		 1334
1335 ctrl = rd32(E1000_CTRL);
1336 ctrl |= E1000_CTRL_SLU;
1337 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1338 wr32(E1000_CTRL, ctrl);
1339
867eb39e
CW		 1340 /* Clear Go Link Disconnect bit */
1341 if (hw->mac.type >= e1000_82580) {
1342 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1343 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1344 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1345 }
1346
2fb02a26
AD		 1347 ret_val = igb_setup_serdes_link_82575(hw);
1348 if (ret_val)
1349 goto out;
1350
1351 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1352 /* allow time for SFP cage time to power up phy */
1353 msleep(300);
1354
2fb02a26
AD		 1355 ret_val = hw->phy.ops.reset(hw);
1356 if (ret_val) {
1357 hw_dbg("Error resetting the PHY.\n");
1358 goto out;
1359 }
1360 }
9d5c8243 1361 switch (hw->phy.type) {
f96a8a0b 1362 case e1000_phy_i210:
9d5c8243 1363 case e1000_phy_m88:
ed65bdd8
CW		 1364 switch (hw->phy.id) {
1365 case I347AT4_E_PHY_ID:
1366 case M88E1112_E_PHY_ID:
1367 case I210_I_PHY_ID:
308fb39a 1368 ret_val = igb_copper_link_setup_m88_gen2(hw);
ed65bdd8
CW		 1369 break;
1370 default:
308fb39a 1371 ret_val = igb_copper_link_setup_m88(hw);
ed65bdd8
CW		 1372 break;
1373 }
9d5c8243
AK		 1374 break;
1375 case e1000_phy_igp_3:
1376 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1377 break;
bb2ac47b
AD		 1378 case e1000_phy_82580:
1379 ret_val = igb_copper_link_setup_82580(hw);
1380 break;
9d5c8243
AK		 1381 default:
1382 ret_val = -E1000_ERR_PHY;
1383 break;
1384 }
1385
1386 if (ret_val)
1387 goto out;
1388
81fadd81 1389 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1390out:
1391 return ret_val;
1392}
1393
1394/**
70d92f86 1395 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1396 * @hw: pointer to the HW structure
1397 *
70d92f86
AD		 1398 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1399 * used on copper connections where the serialized gigabit media independent
1400 * interface (sgmii), or serdes fiber is being used. Configures the link
1401 * for auto-negotiation or forces speed/duplex.
9d5c8243 1402 **/
2fb02a26 1403static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1404{
daf56e40 1405 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bb2ac47b 1406 bool pcs_autoneg;
2c670b5b
CW		 1407 s32 ret_val = E1000_SUCCESS;
1408 u16 data;
2fb02a26
AD		 1409
1410 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1411 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1412 return ret_val;
1413
9d5c8243
AK		 1414
1415 /*
1416 * On the 82575, SerDes loopback mode persists until it is
1417 * explicitly turned off or a power cycle is performed. A read to
1418 * the register does not indicate its status. Therefore, we ensure
1419 * loopback mode is disabled during initialization.
1420 */
1421 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1422
2fb02a26 1423 /* power on the sfp cage if present */
bb2ac47b
AD		 1424 ctrl_ext = rd32(E1000_CTRL_EXT);
1425 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1426 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1427
1428 ctrl_reg = rd32(E1000_CTRL);
1429 ctrl_reg |= E1000_CTRL_SLU;
1430
1431 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1432 /* set both sw defined pins */
1433 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1434
1435 /* Set switch control to serdes energy detect */
1436 reg = rd32(E1000_CONNSW);
1437 reg |= E1000_CONNSW_ENRGSRC;
1438 wr32(E1000_CONNSW, reg);
1439 }
1440
1441 reg = rd32(E1000_PCS_LCTL);
1442
bb2ac47b
AD		 1443 /* default pcs_autoneg to the same setting as mac autoneg */
1444 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1445
bb2ac47b
AD		 1446 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1447 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1448 /* sgmii mode lets the phy handle forcing speed/duplex */
1449 pcs_autoneg = true;
1450 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1451 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1452 break;
1453 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1454 /* disable PCS autoneg and support parallel detect only */
1455 pcs_autoneg = false;
1456 default:
2c670b5b
CW		 1457 if (hw->mac.type == e1000_82575 ||
1458 hw->mac.type == e1000_82576) {
1459 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1460 if (ret_val) {
1461 printk(KERN_DEBUG "NVM Read Error\n\n");
1462 return ret_val;
1463 }
1464
1465 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1466 pcs_autoneg = false;
1467 }
1468
bb2ac47b
AD		 1469 /*
1470 * non-SGMII modes only supports a speed of 1000/Full for the
1471 * link so it is best to just force the MAC and let the pcs
1472 * link either autoneg or be forced to 1000/Full
1473 */
2fb02a26
AD		 1474 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1475 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1476
1477 /* set speed of 1000/Full if speed/duplex is forced */
1478 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1479 break;
921aa749
AD		 1480 }
1481
2fb02a26 1482 wr32(E1000_CTRL, ctrl_reg);
9d5c8243
AK		 1483
1484 /*
1485 * New SerDes mode allows for forcing speed or autonegotiating speed
1486 * at 1gb. Autoneg should be default set by most drivers. This is the
1487 * mode that will be compatible with older link partners and switches.
1488 * However, both are supported by the hardware and some drivers/tools.
1489 */
9d5c8243
AK		 1490 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1491 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1492
bb2ac47b 1493 if (pcs_autoneg) {
9d5c8243 1494 /* Set PCS register for autoneg */
bb2ac47b 1495 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1496 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
daf56e40
CW		 1497
1498 /* Disable force flow control for autoneg */
1499 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1500
1501 /* Configure flow control advertisement for autoneg */
1502 anadv_reg = rd32(E1000_PCS_ANADV);
1503 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1504 switch (hw->fc.requested_mode) {
1505 case e1000_fc_full:
1506 case e1000_fc_rx_pause:
1507 anadv_reg |= E1000_TXCW_ASM_DIR;
1508 anadv_reg |= E1000_TXCW_PAUSE;
1509 break;
1510 case e1000_fc_tx_pause:
1511 anadv_reg |= E1000_TXCW_ASM_DIR;
1512 break;
1513 default:
1514 break;
1515 }
1516 wr32(E1000_PCS_ANADV, anadv_reg);
1517
bb2ac47b 1518 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1519 } else {
bb2ac47b 1520 /* Set PCS register for forced link */
d68caec6 1521 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b 1522
daf56e40
CW		 1523 /* Force flow control for forced link */
1524 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1525
bb2ac47b 1526 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1527 }
726c09e7 1528
9d5c8243
AK		 1529 wr32(E1000_PCS_LCTL, reg);
1530
daf56e40 1531 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
2fb02a26 1532 igb_force_mac_fc(hw);
9d5c8243 1533
2c670b5b 1534 return ret_val;
9d5c8243
AK		 1535}
1536
1537/**
733596be 1538 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1539 * @hw: pointer to the HW structure
1540 *
1541 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1542 * which can be enabled for use in the embedded applications. Simply
1543 * return the current state of the sgmii interface.
1544 **/
1545static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1546{
c1889bfe 1547 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1548 return dev_spec->sgmii_active;
9d5c8243
AK		 1549}
1550
1551/**
733596be 1552 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1553 * @hw: pointer to the HW structure
1554 *
1555 * Inits recommended HW defaults after a reset when there is no EEPROM
1556 * detected. This is only for the 82575.
1557 **/
1558static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1559{
1560 if (hw->mac.type == e1000_82575) {
652fff32 1561 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1562 /* SerDes configuration via SERDESCTRL */
1563 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1564 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1565 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1566 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1567
1568 /* CCM configuration via CCMCTL register */
1569 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1570 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1571
1572 /* PCIe lanes configuration */
1573 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1574 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1575 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1576 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1577
1578 /* PCIe PLL Configuration */
1579 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1580 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1581 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1582 }
1583
1584 return 0;
1585}
1586
1587/**
733596be 1588 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1589 * @hw: pointer to the HW structure
1590 **/
1591static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1592{
1593 s32 ret_val = 0;
1594
22896639
AD		 1595 /*
1596 * If there's an alternate MAC address place it in RAR0
1597 * so that it will override the Si installed default perm
1598 * address.
1599 */
1600 ret_val = igb_check_alt_mac_addr(hw);
1601 if (ret_val)
1602 goto out;
1603
1604 ret_val = igb_read_mac_addr(hw);
9d5c8243 1605
22896639 1606out:
9d5c8243
AK		 1607 return ret_val;
1608}
1609
88a268c1
NN		 1610/**
1611 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1612 * @hw: pointer to the HW structure
1613 *
1614 * In the case of a PHY power down to save power, or to turn off link during a
1615 * driver unload, or wake on lan is not enabled, remove the link.
1616 **/
1617void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1618{
1619 /* If the management interface is not enabled, then power down */
1620 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1621 igb_power_down_phy_copper(hw);
88a268c1
NN		 1622}
1623
9d5c8243 1624/**
733596be 1625 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1626 * @hw: pointer to the HW structure
1627 *
1628 * Clears the hardware counters by reading the counter registers.
1629 **/
1630static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1631{
9d5c8243
AK		 1632 igb_clear_hw_cntrs_base(hw);
1633
cc9073bb
AD		 1634 rd32(E1000_PRC64);
1635 rd32(E1000_PRC127);
1636 rd32(E1000_PRC255);
1637 rd32(E1000_PRC511);
1638 rd32(E1000_PRC1023);
1639 rd32(E1000_PRC1522);
1640 rd32(E1000_PTC64);
1641 rd32(E1000_PTC127);
1642 rd32(E1000_PTC255);
1643 rd32(E1000_PTC511);
1644 rd32(E1000_PTC1023);
1645 rd32(E1000_PTC1522);
1646
1647 rd32(E1000_ALGNERRC);
1648 rd32(E1000_RXERRC);
1649 rd32(E1000_TNCRS);
1650 rd32(E1000_CEXTERR);
1651 rd32(E1000_TSCTC);
1652 rd32(E1000_TSCTFC);
1653
1654 rd32(E1000_MGTPRC);
1655 rd32(E1000_MGTPDC);
1656 rd32(E1000_MGTPTC);
1657
1658 rd32(E1000_IAC);
1659 rd32(E1000_ICRXOC);
1660
1661 rd32(E1000_ICRXPTC);
1662 rd32(E1000_ICRXATC);
1663 rd32(E1000_ICTXPTC);
1664 rd32(E1000_ICTXATC);
1665 rd32(E1000_ICTXQEC);
1666 rd32(E1000_ICTXQMTC);
1667 rd32(E1000_ICRXDMTC);
1668
1669 rd32(E1000_CBTMPC);
1670 rd32(E1000_HTDPMC);
1671 rd32(E1000_CBRMPC);
1672 rd32(E1000_RPTHC);
1673 rd32(E1000_HGPTC);
1674 rd32(E1000_HTCBDPC);
1675 rd32(E1000_HGORCL);
1676 rd32(E1000_HGORCH);
1677 rd32(E1000_HGOTCL);
1678 rd32(E1000_HGOTCH);
1679 rd32(E1000_LENERRS);
9d5c8243
AK		 1680
1681 /* This register should not be read in copper configurations */
2fb02a26
AD		 1682 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1683 igb_sgmii_active_82575(hw))
cc9073bb 1684 rd32(E1000_SCVPC);
9d5c8243
AK		 1685}
1686
662d7205
AD		 1687/**
1688 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1689 * @hw: pointer to the HW structure
1690 *
1691 * After rx enable if managability is enabled then there is likely some
1692 * bad data at the start of the fifo and possibly in the DMA fifo. This
1693 * function clears the fifos and flushes any packets that came in as rx was
1694 * being enabled.
1695 **/
1696void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1697{
1698 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1699 int i, ms_wait;
1700
1701 if (hw->mac.type != e1000_82575 ||
1702 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1703 return;
1704
1705 /* Disable all RX queues */
1706 for (i = 0; i < 4; i++) {
1707 rxdctl[i] = rd32(E1000_RXDCTL(i));
1708 wr32(E1000_RXDCTL(i),
1709 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1710 }
1711 /* Poll all queues to verify they have shut down */
1712 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1713 msleep(1);
1714 rx_enabled = 0;
1715 for (i = 0; i < 4; i++)
1716 rx_enabled |= rd32(E1000_RXDCTL(i));
1717 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1718 break;
1719 }
1720
1721 if (ms_wait == 10)
1722 hw_dbg("Queue disable timed out after 10ms\n");
1723
1724 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1725 * incoming packets are rejected. Set enable and wait 2ms so that
1726 * any packet that was coming in as RCTL.EN was set is flushed
1727 */
1728 rfctl = rd32(E1000_RFCTL);
1729 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1730
1731 rlpml = rd32(E1000_RLPML);
1732 wr32(E1000_RLPML, 0);
1733
1734 rctl = rd32(E1000_RCTL);
1735 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1736 temp_rctl |= E1000_RCTL_LPE;
1737
1738 wr32(E1000_RCTL, temp_rctl);
1739 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1740 wrfl();
1741 msleep(2);
1742
1743 /* Enable RX queues that were previously enabled and restore our
1744 * previous state
1745 */
1746 for (i = 0; i < 4; i++)
1747 wr32(E1000_RXDCTL(i), rxdctl[i]);
1748 wr32(E1000_RCTL, rctl);
1749 wrfl();
1750
1751 wr32(E1000_RLPML, rlpml);
1752 wr32(E1000_RFCTL, rfctl);
1753
1754 /* Flush receive errors generated by workaround */
1755 rd32(E1000_ROC);
1756 rd32(E1000_RNBC);
1757 rd32(E1000_MPC);
1758}
1759
009bc06e
AD		 1760/**
1761 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1762 * @hw: pointer to the HW structure
1763 *
1764 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1765 * however the hardware default for these parts is 500us to 1ms which is less
1766 * than the 10ms recommended by the pci-e spec. To address this we need to
1767 * increase the value to either 10ms to 200ms for capability version 1 config,
1768 * or 16ms to 55ms for version 2.
1769 **/
1770static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1771{
1772 u32 gcr = rd32(E1000_GCR);
1773 s32 ret_val = 0;
1774 u16 pcie_devctl2;
1775
1776 /* only take action if timeout value is defaulted to 0 */
1777 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1778 goto out;
1779
1780 /*
1781 * if capababilities version is type 1 we can write the
1782 * timeout of 10ms to 200ms through the GCR register
1783 */
1784 if (!(gcr & E1000_GCR_CAP_VER2)) {
1785 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1786 goto out;
1787 }
1788
1789 /*
1790 * for version 2 capabilities we need to write the config space
1791 * directly in order to set the completion timeout value for
1792 * 16ms to 55ms
1793 */
1794 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1795 &pcie_devctl2);
1796 if (ret_val)
1797 goto out;
1798
1799 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1800
1801 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1802 &pcie_devctl2);
1803out:
1804 /* disable completion timeout resend */
1805 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1806
1807 wr32(E1000_GCR, gcr);
1808 return ret_val;
1809}
1810
13800469
GR		 1811/**
1812 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1813 * @hw: pointer to the hardware struct
1814 * @enable: state to enter, either enabled or disabled
1815 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1816 *
1817 * enables/disables L2 switch anti-spoofing functionality.
1818 **/
1819void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1820{
22c12752 1821 u32 reg_val, reg_offset;
13800469
GR		 1822
1823 switch (hw->mac.type) {
1824 case e1000_82576:
22c12752
LL		 1825 reg_offset = E1000_DTXSWC;
1826 break;
13800469 1827 case e1000_i350:
22c12752 1828 reg_offset = E1000_TXSWC;
13800469
GR		 1829 break;
1830 default:
22c12752
LL		 1831 return;
1832 }
1833
1834 reg_val = rd32(reg_offset);
1835 if (enable) {
1836 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1837 E1000_DTXSWC_VLAN_SPOOF_MASK);
1838 /* The PF can spoof - it has to in order to
1839 * support emulation mode NICs
1840 */
1841 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1842 } else {
1843 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1844 E1000_DTXSWC_VLAN_SPOOF_MASK);
13800469 1845 }
22c12752 1846 wr32(reg_offset, reg_val);
13800469
GR		 1847}
1848
4ae196df
AD		 1849/**
1850 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1851 * @hw: pointer to the hardware struct
1852 * @enable: state to enter, either enabled or disabled
1853 *
1854 * enables/disables L2 switch loopback functionality.
1855 **/
1856void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1857{
ca2e3e7e
AA		 1858 u32 dtxswc;
1859
1860 switch (hw->mac.type) {
1861 case e1000_82576:
1862 dtxswc = rd32(E1000_DTXSWC);
1863 if (enable)
1864 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1865 else
1866 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1867 wr32(E1000_DTXSWC, dtxswc);
1868 break;
1869 case e1000_i350:
1870 dtxswc = rd32(E1000_TXSWC);
1871 if (enable)
1872 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1873 else
1874 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1875 wr32(E1000_TXSWC, dtxswc);
1876 break;
1877 default:
1878 /* Currently no other hardware supports loopback */
1879 break;
1880 }
4ae196df 1881
4ae196df 1882
4ae196df
AD		 1883}
1884
1885/**
1886 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1887 * @hw: pointer to the hardware struct
1888 * @enable: state to enter, either enabled or disabled
1889 *
1890 * enables/disables replication of packets across multiple pools.
1891 **/
1892void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1893{
1894 u32 vt_ctl = rd32(E1000_VT_CTL);
1895
1896 if (enable)
1897 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1898 else
1899 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1900
1901 wr32(E1000_VT_CTL, vt_ctl);
1902}
1903
bb2ac47b
AD		 1904/**
1905 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1906 * @hw: pointer to the HW structure
1907 * @offset: register offset to be read
1908 * @data: pointer to the read data
1909 *
1910 * Reads the MDI control register in the PHY at offset and stores the
1911 * information read to data.
1912 **/
1913static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1914{
bb2ac47b
AD		 1915 s32 ret_val;
1916
1917
1918 ret_val = hw->phy.ops.acquire(hw);
1919 if (ret_val)
1920 goto out;
1921
bb2ac47b
AD		 1922 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1923
1924 hw->phy.ops.release(hw);
1925
1926out:
1927 return ret_val;
1928}
1929
1930/**
1931 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1932 * @hw: pointer to the HW structure
1933 * @offset: register offset to write to
1934 * @data: data to write to register at offset
1935 *
1936 * Writes data to MDI control register in the PHY at offset.
1937 **/
1938static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1939{
bb2ac47b
AD		 1940 s32 ret_val;
1941
1942
1943 ret_val = hw->phy.ops.acquire(hw);
1944 if (ret_val)
1945 goto out;
1946
bb2ac47b
AD		 1947 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1948
1949 hw->phy.ops.release(hw);
1950
1951out:
1952 return ret_val;
1953}
1954
08451e25
NN		 1955/**
1956 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1957 * @hw: pointer to the HW structure
1958 *
1959 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1960 * the values found in the EEPROM. This addresses an issue in which these
1961 * bits are not restored from EEPROM after reset.
1962 **/
1963static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1964{
1965 s32 ret_val = 0;
1966 u32 mdicnfg;
1b5dda33 1967 u16 nvm_data = 0;
08451e25
NN		 1968
1969 if (hw->mac.type != e1000_82580)
1970 goto out;
1971 if (!igb_sgmii_active_82575(hw))
1972 goto out;
1973
1974 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1975 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1976 &nvm_data);
1977 if (ret_val) {
1978 hw_dbg("NVM Read Error\n");
1979 goto out;
1980 }
1981
1982 mdicnfg = rd32(E1000_MDICNFG);
1983 if (nvm_data & NVM_WORD24_EXT_MDIO)
1984 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1985 if (nvm_data & NVM_WORD24_COM_MDIO)
1986 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1987 wr32(E1000_MDICNFG, mdicnfg);
1988out:
1989 return ret_val;
1990}
1991
bb2ac47b
AD		 1992/**
1993 * igb_reset_hw_82580 - Reset hardware
1994 * @hw: pointer to the HW structure
1995 *
1996 * This resets function or entire device (all ports, etc.)
1997 * to a known state.
1998 **/
1999static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2000{
2001 s32 ret_val = 0;
2002 /* BH SW mailbox bit in SW_FW_SYNC */
2003 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2004 u32 ctrl, icr;
2005 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2006
2007
2008 hw->dev_spec._82575.global_device_reset = false;
2009
a0483e2e
CW		 2010 /* due to hw errata, global device reset doesn't always
2011 * work on 82580
2012 */
2013 if (hw->mac.type == e1000_82580)
2014 global_device_reset = false;
2015
bb2ac47b
AD		 2016 /* Get current control state. */
2017 ctrl = rd32(E1000_CTRL);
2018
2019 /*
2020 * Prevent the PCI-E bus from sticking if there is no TLP connection
2021 * on the last TLP read/write transaction when MAC is reset.
2022 */
2023 ret_val = igb_disable_pcie_master(hw);
2024 if (ret_val)
2025 hw_dbg("PCI-E Master disable polling has failed.\n");
2026
2027 hw_dbg("Masking off all interrupts\n");
2028 wr32(E1000_IMC, 0xffffffff);
2029 wr32(E1000_RCTL, 0);
2030 wr32(E1000_TCTL, E1000_TCTL_PSP);
2031 wrfl();
2032
2033 msleep(10);
2034
2035 /* Determine whether or not a global dev reset is requested */
2036 if (global_device_reset &&
f96a8a0b 2037 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
bb2ac47b
AD		 2038 global_device_reset = false;
2039
2040 if (global_device_reset &&
2041 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2042 ctrl |= E1000_CTRL_DEV_RST;
2043 else
2044 ctrl |= E1000_CTRL_RST;
2045
2046 wr32(E1000_CTRL, ctrl);
064b4330 2047 wrfl();
bb2ac47b
AD		 2048
2049 /* Add delay to insure DEV_RST has time to complete */
2050 if (global_device_reset)
2051 msleep(5);
2052
2053 ret_val = igb_get_auto_rd_done(hw);
2054 if (ret_val) {
2055 /*
2056 * When auto config read does not complete, do not
2057 * return with an error. This can happen in situations
2058 * where there is no eeprom and prevents getting link.
2059 */
2060 hw_dbg("Auto Read Done did not complete\n");
2061 }
2062
2063 /* If EEPROM is not present, run manual init scripts */
2064 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
2065 igb_reset_init_script_82575(hw);
2066
2067 /* clear global device reset status bit */
2068 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2069
2070 /* Clear any pending interrupt events. */
2071 wr32(E1000_IMC, 0xffffffff);
2072 icr = rd32(E1000_ICR);
2073
08451e25
NN		 2074 ret_val = igb_reset_mdicnfg_82580(hw);
2075 if (ret_val)
2076 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2077
bb2ac47b
AD		 2078 /* Install any alternate MAC address into RAR0 */
2079 ret_val = igb_check_alt_mac_addr(hw);
2080
2081 /* Release semaphore */
2082 if (global_device_reset)
f96a8a0b 2083 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
bb2ac47b
AD		 2084
2085 return ret_val;
2086}
2087
2088/**
2089 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2090 * @data: data received by reading RXPBS register
2091 *
2092 * The 82580 uses a table based approach for packet buffer allocation sizes.
2093 * This function converts the retrieved value into the correct table value
2094 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2095 * 0x0 36 72 144 1 2 4 8 16
2096 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2097 */
2098u16 igb_rxpbs_adjust_82580(u32 data)
2099{
2100 u16 ret_val = 0;
2101
2102 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2103 ret_val = e1000_82580_rxpbs_table[data];
2104
2105 return ret_val;
2106}
2107
4322e561
CW		 2108/**
2109 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2110 * checksum
2111 * @hw: pointer to the HW structure
2112 * @offset: offset in words of the checksum protected region
2113 *
2114 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2115 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2116 **/
bed45a6e
ET		 2117static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2118 u16 offset)
4322e561
CW		 2119{
2120 s32 ret_val = 0;
2121 u16 checksum = 0;
2122 u16 i, nvm_data;
2123
2124 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2125 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2126 if (ret_val) {
2127 hw_dbg("NVM Read Error\n");
2128 goto out;
2129 }
2130 checksum += nvm_data;
2131 }
2132
2133 if (checksum != (u16) NVM_SUM) {
2134 hw_dbg("NVM Checksum Invalid\n");
2135 ret_val = -E1000_ERR_NVM;
2136 goto out;
2137 }
2138
2139out:
2140 return ret_val;
2141}
2142
2143/**
2144 * igb_update_nvm_checksum_with_offset - Update EEPROM
2145 * checksum
2146 * @hw: pointer to the HW structure
2147 * @offset: offset in words of the checksum protected region
2148 *
2149 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2150 * up to the checksum. Then calculates the EEPROM checksum and writes the
2151 * value to the EEPROM.
2152 **/
bed45a6e 2153static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 2154{
2155 s32 ret_val;
2156 u16 checksum = 0;
2157 u16 i, nvm_data;
2158
2159 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2160 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2161 if (ret_val) {
2162 hw_dbg("NVM Read Error while updating checksum.\n");
2163 goto out;
2164 }
2165 checksum += nvm_data;
2166 }
2167 checksum = (u16) NVM_SUM - checksum;
2168 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2169 &checksum);
2170 if (ret_val)
2171 hw_dbg("NVM Write Error while updating checksum.\n");
2172
2173out:
2174 return ret_val;
2175}
2176
2177/**
2178 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2179 * @hw: pointer to the HW structure
2180 *
2181 * Calculates the EEPROM section checksum by reading/adding each word of
2182 * the EEPROM and then verifies that the sum of the EEPROM is
2183 * equal to 0xBABA.
2184 **/
2185static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2186{
2187 s32 ret_val = 0;
2188 u16 eeprom_regions_count = 1;
2189 u16 j, nvm_data;
2190 u16 nvm_offset;
2191
2192 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2193 if (ret_val) {
2194 hw_dbg("NVM Read Error\n");
2195 goto out;
2196 }
2197
2198 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 2199 /* if checksums compatibility bit is set validate checksums
4322e561
CW		 2200 * for all 4 ports. */
2201 eeprom_regions_count = 4;
2202 }
2203
2204 for (j = 0; j < eeprom_regions_count; j++) {
2205 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2206 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2207 nvm_offset);
2208 if (ret_val != 0)
2209 goto out;
2210 }
2211
2212out:
2213 return ret_val;
2214}
2215
2216/**
2217 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2218 * @hw: pointer to the HW structure
2219 *
2220 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2221 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2222 * checksum and writes the value to the EEPROM.
2223 **/
2224static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2225{
2226 s32 ret_val;
2227 u16 j, nvm_data;
2228 u16 nvm_offset;
2229
2230 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2231 if (ret_val) {
2232 hw_dbg("NVM Read Error while updating checksum"
2233 " compatibility bit.\n");
2234 goto out;
2235 }
2236
2237 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2238 /* set compatibility bit to validate checksums appropriately */
2239 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2240 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2241 &nvm_data);
2242 if (ret_val) {
2243 hw_dbg("NVM Write Error while updating checksum"
2244 " compatibility bit.\n");
2245 goto out;
2246 }
2247 }
2248
2249 for (j = 0; j < 4; j++) {
2250 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2251 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2252 if (ret_val)
2253 goto out;
2254 }
2255
2256out:
2257 return ret_val;
2258}
2259
2260/**
2261 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2262 * @hw: pointer to the HW structure
2263 *
2264 * Calculates the EEPROM section checksum by reading/adding each word of
2265 * the EEPROM and then verifies that the sum of the EEPROM is
2266 * equal to 0xBABA.
2267 **/
2268static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2269{
2270 s32 ret_val = 0;
2271 u16 j;
2272 u16 nvm_offset;
2273
2274 for (j = 0; j < 4; j++) {
2275 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2276 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2277 nvm_offset);
2278 if (ret_val != 0)
2279 goto out;
2280 }
2281
2282out:
2283 return ret_val;
2284}
2285
2286/**
2287 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2288 * @hw: pointer to the HW structure
2289 *
2290 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2291 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2292 * checksum and writes the value to the EEPROM.
2293 **/
2294static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2295{
2296 s32 ret_val = 0;
2297 u16 j;
2298 u16 nvm_offset;
2299
2300 for (j = 0; j < 4; j++) {
2301 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2302 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2303 if (ret_val != 0)
2304 goto out;
2305 }
2306
2307out:
2308 return ret_val;
2309}
34a0326e 2310
09b068d4
CW		 2311/**
2312 * igb_set_eee_i350 - Enable/disable EEE support
2313 * @hw: pointer to the HW structure
2314 *
2315 * Enable/disable EEE based on setting in dev_spec structure.
2316 *
2317 **/
2318s32 igb_set_eee_i350(struct e1000_hw *hw)
2319{
2320 s32 ret_val = 0;
e5461112 2321 u32 ipcnfg, eeer;
09b068d4 2322
e5461112
AA		 2323 if ((hw->mac.type < e1000_i350) ||
2324 (hw->phy.media_type != e1000_media_type_copper))
09b068d4
CW		 2325 goto out;
2326 ipcnfg = rd32(E1000_IPCNFG);
2327 eeer = rd32(E1000_EEER);
2328
2329 /* enable or disable per user setting */
2330 if (!(hw->dev_spec._82575.eee_disable)) {
40b20122
CW		 2331 u32 eee_su = rd32(E1000_EEE_SU);
2332
2333 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2334 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
09b068d4
CW		 2335 E1000_EEER_LPI_FC);
2336
40b20122
CW		 2337 /* This bit should not be set in normal operation. */
2338 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2339 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2340
e5461112 2341
09b068d4
CW		 2342 } else {
2343 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2344 E1000_IPCNFG_EEE_100M_AN);
2345 eeer &= ~(E1000_EEER_TX_LPI_EN |
2346 E1000_EEER_RX_LPI_EN |
2347 E1000_EEER_LPI_FC);
2348 }
2349 wr32(E1000_IPCNFG, ipcnfg);
2350 wr32(E1000_EEER, eeer);
e5461112
AA		 2351 rd32(E1000_IPCNFG);
2352 rd32(E1000_EEER);
09b068d4
CW		 2353out:
2354
2355 return ret_val;
2356}
4322e561 2357
e428893b
CW		 2358static const u8 e1000_emc_temp_data[4] = {
2359 E1000_EMC_INTERNAL_DATA,
2360 E1000_EMC_DIODE1_DATA,
2361 E1000_EMC_DIODE2_DATA,
2362 E1000_EMC_DIODE3_DATA
2363};
2364static const u8 e1000_emc_therm_limit[4] = {
2365 E1000_EMC_INTERNAL_THERM_LIMIT,
2366 E1000_EMC_DIODE1_THERM_LIMIT,
2367 E1000_EMC_DIODE2_THERM_LIMIT,
2368 E1000_EMC_DIODE3_THERM_LIMIT
2369};
2370
2371/* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2372 * @hw: pointer to hardware structure
2373 *
2374 * Updates the temperatures in mac.thermal_sensor_data
2375 */
2376s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2377{
2378 s32 status = E1000_SUCCESS;
2379 u16 ets_offset;
2380 u16 ets_cfg;
2381 u16 ets_sensor;
2382 u8 num_sensors;
2383 u8 sensor_index;
2384 u8 sensor_location;
2385 u8 i;
2386 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2387
2388 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2389 return E1000_NOT_IMPLEMENTED;
2390
2391 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2392
2393 /* Return the internal sensor only if ETS is unsupported */
2394 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2395 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2396 return status;
2397
2398 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2399 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2400 != NVM_ETS_TYPE_EMC)
2401 return E1000_NOT_IMPLEMENTED;
2402
2403 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2404 if (num_sensors > E1000_MAX_SENSORS)
2405 num_sensors = E1000_MAX_SENSORS;
2406
2407 for (i = 1; i < num_sensors; i++) {
2408 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2409 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2410 NVM_ETS_DATA_INDEX_SHIFT);
2411 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2412 NVM_ETS_DATA_LOC_SHIFT);
2413
2414 if (sensor_location != 0)
2415 hw->phy.ops.read_i2c_byte(hw,
2416 e1000_emc_temp_data[sensor_index],
2417 E1000_I2C_THERMAL_SENSOR_ADDR,
2418 &data->sensor[i].temp);
2419 }
2420 return status;
2421}
2422
2423/* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2424 * @hw: pointer to hardware structure
2425 *
2426 * Sets the thermal sensor thresholds according to the NVM map
2427 * and save off the threshold and location values into mac.thermal_sensor_data
2428 */
2429s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2430{
2431 s32 status = E1000_SUCCESS;
2432 u16 ets_offset;
2433 u16 ets_cfg;
2434 u16 ets_sensor;
2435 u8 low_thresh_delta;
2436 u8 num_sensors;
2437 u8 sensor_index;
2438 u8 sensor_location;
2439 u8 therm_limit;
2440 u8 i;
2441 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2442
2443 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2444 return E1000_NOT_IMPLEMENTED;
2445
2446 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2447
2448 data->sensor[0].location = 0x1;
2449 data->sensor[0].caution_thresh =
2450 (rd32(E1000_THHIGHTC) & 0xFF);
2451 data->sensor[0].max_op_thresh =
2452 (rd32(E1000_THLOWTC) & 0xFF);
2453
2454 /* Return the internal sensor only if ETS is unsupported */
2455 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2456 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2457 return status;
2458
2459 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2460 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2461 != NVM_ETS_TYPE_EMC)
2462 return E1000_NOT_IMPLEMENTED;
2463
2464 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2465 NVM_ETS_LTHRES_DELTA_SHIFT);
2466 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2467
2468 for (i = 1; i <= num_sensors; i++) {
2469 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2470 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2471 NVM_ETS_DATA_INDEX_SHIFT);
2472 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2473 NVM_ETS_DATA_LOC_SHIFT);
2474 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2475
2476 hw->phy.ops.write_i2c_byte(hw,
2477 e1000_emc_therm_limit[sensor_index],
2478 E1000_I2C_THERMAL_SENSOR_ADDR,
2479 therm_limit);
2480
2481 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2482 data->sensor[i].location = sensor_location;
2483 data->sensor[i].caution_thresh = therm_limit;
2484 data->sensor[i].max_op_thresh = therm_limit -
2485 low_thresh_delta;
2486 }
2487 }
2488 return status;
2489}
2490
9d5c8243 2491static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2492 .init_hw = igb_init_hw_82575,
2493 .check_for_link = igb_check_for_link_82575,
2d064c06 2494 .rar_set = igb_rar_set,
9d5c8243
AK		 2495 .read_mac_addr = igb_read_mac_addr_82575,
2496 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
e428893b
CW		 2497#ifdef CONFIG_IGB_HWMON
2498 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2499 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2500#endif
9d5c8243
AK		 2501};
2502
2503static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2504 .acquire = igb_acquire_phy_82575,
9d5c8243 2505 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2506 .release = igb_release_phy_82575,
441fc6fd
CW		 2507 .write_i2c_byte = igb_write_i2c_byte,
2508 .read_i2c_byte = igb_read_i2c_byte,
9d5c8243
AK		 2509};
2510
2511static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2512 .acquire = igb_acquire_nvm_82575,
2513 .read = igb_read_nvm_eerd,
2514 .release = igb_release_nvm_82575,
2515 .write = igb_write_nvm_spi,
9d5c8243
AK		 2516};
2517
2518const struct e1000_info e1000_82575_info = {
2519 .get_invariants = igb_get_invariants_82575,
2520 .mac_ops = &e1000_mac_ops_82575,
2521 .phy_ops = &e1000_phy_ops_82575,
2522 .nvm_ops = &e1000_nvm_ops_82575,
2523};
2524
Linux kernel - Deliverables
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