projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e52c0f96 CW |
1 | /* Intel(R) Gigabit Ethernet Linux driver |
| 2 | * Copyright(c) 2007-2014 Intel Corporation. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License along with | |
| 14 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
| 15 | * | |
| 16 | * The full GNU General Public License is included in this distribution in | |
| 17 | * the file called "COPYING". | |
| 18 | * | |
| 19 | * Contact Information: | |
| 20 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
| 21 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 22 | */ | |
| 9d5c8243 AK |
23 | |
| 24 | #ifndef _E1000_REGS_H_ | |
| 25 | #define _E1000_REGS_H_ | |
| 26 | ||
| 27 | #define E1000_CTRL 0x00000 /* Device Control - RW */ | |
| 28 | #define E1000_STATUS 0x00008 /* Device Status - RO */ | |
| 29 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ | |
| 30 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ | |
| 31 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ | |
| 32 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ | |
| bb2ac47b | 33 | #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ |
| 9d5c8243 AK |
34 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ |
| 35 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ | |
| 36 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ | |
| 37 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ | |
| 38 | #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ | |
| 39 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ | |
| 0c375ac1 | 40 | #define E1000_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */ |
| 9d5c8243 AK |
41 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ |
| 42 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ | |
| 43 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ | |
| 44 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ | |
| 45 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ | |
| 46 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ | |
| 47 | #define E1000_RCTL 0x00100 /* RX Control - RW */ | |
| 48 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ | |
| 49 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ | |
| 50 | #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ | |
| 51 | #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) | |
| 52 | #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ | |
| 53 | #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ | |
| 54 | #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ | |
| 55 | #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ | |
| 56 | #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ | |
| 2d064c06 AD |
57 | #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ |
| 58 | #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ | |
| 59 | #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ | |
| 9d5c8243 AK |
60 | #define E1000_TCTL 0x00400 /* TX Control - RW */ |
| 61 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ | |
| 62 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ | |
| 63 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ | |
| 64 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ | |
| ceb5f13b | 65 | #define E1000_LEDMUX 0x08130 /* LED MUX Control */ |
| 9d5c8243 AK |
66 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ |
| 67 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ | |
| 68 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ | |
| 08c99129 | 69 | #define E1000_EEMNGCTL_I210 0x12030 /* MNG EEprom Control */ |
| 94826487 | 70 | #define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */ |
| 9d5c8243 AK |
71 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
| 72 | #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ | |
| 73 | #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ | |
| 74 | #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ | |
| 75 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | |
| 76 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | |
| 9d5c8243 | 77 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
| 441fc6fd CW |
78 | #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */ |
| 79 | #define E1000_I2CBB_EN 0x00000100 /* I2C - Bit Bang Enable */ | |
| 80 | #define E1000_I2C_CLK_OUT 0x00000200 /* I2C- Clock */ | |
| 81 | #define E1000_I2C_DATA_OUT 0x00000400 /* I2C- Data Out */ | |
| 82 | #define E1000_I2C_DATA_OE_N 0x00000800 /* I2C- Data Output Enable */ | |
| 83 | #define E1000_I2C_DATA_IN 0x00001000 /* I2C- Data In */ | |
| 84 | #define E1000_I2C_CLK_OE_N 0x00002000 /* I2C- Clock Output Enable */ | |
| 85 | #define E1000_I2C_CLK_IN 0x00004000 /* I2C- Clock In */ | |
| ceb5f13b CW |
86 | #define E1000_MPHY_ADDR_CTRL 0x0024 /* GbE MPHY Address Control */ |
| 87 | #define E1000_MPHY_DATA 0x0E10 /* GBE MPHY Data */ | |
| 88 | #define E1000_MPHY_STAT 0x0E0C /* GBE MPHY Statistics */ | |
| 38c845c7 PO |
89 | |
| 90 | /* IEEE 1588 TIMESYNCH */ | |
| c5b9bd5e AD |
91 | #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ |
| 92 | #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ | |
| 93 | #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ | |
| 94 | #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ | |
| 95 | #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ | |
| 96 | #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ | |
| 97 | #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ | |
| 98 | #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ | |
| 99 | #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ | |
| 100 | #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ | |
| 101 | #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ | |
| 102 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ | |
| 55cac248 | 103 | #define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */ |
| 0c375ac1 CW |
104 | #define E1000_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */ |
| 105 | #define E1000_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */ | |
| 106 | #define E1000_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */ | |
| 107 | #define E1000_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */ | |
| 30c72916 RC |
108 | #define E1000_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */ |
| 109 | #define E1000_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */ | |
| 0c375ac1 CW |
110 | #define E1000_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Register Low - RO */ |
| 111 | #define E1000_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */ | |
| 112 | #define E1000_AUXSTMPL1 0x0B664 /* Auxiliary Time Stamp 1 Register Low - RO */ | |
| 113 | #define E1000_AUXSTMPH1 0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */ | |
| 55cac248 | 114 | #define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */ |
| 1f6e8178 MV |
115 | #define E1000_TSICR 0x0B66C /* Interrupt Cause Register */ |
| 116 | #define E1000_TSIM 0x0B674 /* Interrupt Mask Register */ | |
| 38c845c7 | 117 | |
| 33af6bcc PO |
118 | /* Filtering Registers */ |
| 119 | #define E1000_SAQF(_n) (0x5980 + 4 * (_n)) | |
| 120 | #define E1000_DAQF(_n) (0x59A0 + 4 * (_n)) | |
| 121 | #define E1000_SPQF(_n) (0x59C0 + 4 * (_n)) | |
| 122 | #define E1000_FTQF(_n) (0x59E0 + 4 * (_n)) | |
| 123 | #define E1000_SAQF0 E1000_SAQF(0) | |
| 124 | #define E1000_DAQF0 E1000_DAQF(0) | |
| 125 | #define E1000_SPQF0 E1000_SPQF(0) | |
| 126 | #define E1000_FTQF0 E1000_FTQF(0) | |
| 127 | #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ | |
| 128 | #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ | |
| 129 | ||
| 3c514ce2 | 130 | #define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40)) |
| d249be54 | 131 | |
| 831ec0b4 | 132 | /* DMA Coalescing registers */ |
| b980ac18 JK |
133 | #define E1000_DMACR 0x02508 /* Control Register */ |
| 134 | #define E1000_DMCTXTH 0x03550 /* Transmit Threshold */ | |
| 135 | #define E1000_DMCTLX 0x02514 /* Time to Lx Request */ | |
| 136 | #define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ | |
| 137 | #define E1000_DMCCNT 0x05DD4 /* Current Rx Count */ | |
| 138 | #define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ | |
| 139 | #define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ | |
| 831ec0b4 | 140 | |
| 17dc566c | 141 | /* TX Rate Limit Registers */ |
| b980ac18 JK |
142 | #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select - WO */ |
| 143 | #define E1000_RTTBCNRM 0x3690 /* Tx BCN Rate-scheduler MMW */ | |
| 144 | #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config - WO */ | |
| 17dc566c | 145 | |
| 9d5c8243 | 146 | /* Split and Replication RX Control - RW */ |
| b980ac18 | 147 | #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ |
| aca5dae8 CW |
148 | |
| 149 | /* Thermal sensor configuration and status registers */ | |
| 150 | #define E1000_THMJT 0x08100 /* Junction Temperature */ | |
| 151 | #define E1000_THLOWTC 0x08104 /* Low Threshold Control */ | |
| 152 | #define E1000_THMIDTC 0x08108 /* Mid Threshold Control */ | |
| 153 | #define E1000_THHIGHTC 0x0810C /* High Threshold Control */ | |
| 154 | #define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ | |
| 155 | ||
| b980ac18 | 156 | /* Convenience macros |
| 9d5c8243 AK |
157 | * |
| 158 | * Note: "_n" is the queue number of the register to be written to. | |
| 159 | * | |
| 160 | * Example usage: | |
| 161 | * E1000_RDBAL_REG(current_rx_queue) | |
| 162 | */ | |
| 163 | #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) \ | |
| 164 | : (0x0C000 + ((_n) * 0x40))) | |
| 165 | #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) \ | |
| 166 | : (0x0C004 + ((_n) * 0x40))) | |
| 167 | #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) \ | |
| 168 | : (0x0C008 + ((_n) * 0x40))) | |
| 169 | #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) \ | |
| 170 | : (0x0C00C + ((_n) * 0x40))) | |
| 171 | #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) \ | |
| 172 | : (0x0C010 + ((_n) * 0x40))) | |
| 173 | #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) \ | |
| 174 | : (0x0C018 + ((_n) * 0x40))) | |
| 175 | #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) \ | |
| 176 | : (0x0C028 + ((_n) * 0x40))) | |
| 177 | #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) \ | |
| 178 | : (0x0E000 + ((_n) * 0x40))) | |
| 179 | #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) \ | |
| 180 | : (0x0E004 + ((_n) * 0x40))) | |
| 181 | #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) \ | |
| 182 | : (0x0E008 + ((_n) * 0x40))) | |
| 183 | #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) \ | |
| 184 | : (0x0E010 + ((_n) * 0x40))) | |
| 185 | #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) \ | |
| 186 | : (0x0E018 + ((_n) * 0x40))) | |
| 187 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ | |
| 188 | : (0x0E028 + ((_n) * 0x40))) | |
| a2d6a1d5 AD |
189 | #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \ |
| 190 | (0x0C014 + ((_n) * 0x40))) | |
| 191 | #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n) | |
| 192 | #define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \ | |
| 193 | (0x0E014 + ((_n) * 0x40))) | |
| 194 | #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n) | |
| 9d5c8243 AK |
195 | #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ |
| 196 | : (0x0E038 + ((_n) * 0x40))) | |
| 197 | #define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) \ | |
| 198 | : (0x0E03C + ((_n) * 0x40))) | |
| 27dff8b2 TF |
199 | |
| 200 | #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ | |
| 201 | #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ | |
| 202 | ||
| 9d5c8243 AK |
203 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ |
| 204 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ | |
| 205 | #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ | |
| 206 | #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ | |
| 207 | #define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */ | |
| 208 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ | |
| 209 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | |
| 210 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | |
| 211 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ | |
| 212 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ | |
| 213 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ | |
| 214 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ | |
| 215 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ | |
| 216 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ | |
| 217 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ | |
| 218 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ | |
| 219 | #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ | |
| 220 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ | |
| 221 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ | |
| 222 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ | |
| 223 | #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ | |
| 224 | #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ | |
| 225 | #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ | |
| 226 | #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ | |
| 227 | #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ | |
| 228 | #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ | |
| 229 | #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ | |
| 230 | #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ | |
| 231 | #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ | |
| 232 | #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ | |
| 233 | #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ | |
| 234 | #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ | |
| 235 | #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ | |
| 236 | #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ | |
| 237 | #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ | |
| 238 | #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ | |
| 239 | #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ | |
| 240 | #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ | |
| 241 | #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ | |
| 242 | #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ | |
| 243 | #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ | |
| 244 | #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ | |
| 245 | #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ | |
| 246 | #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ | |
| 247 | #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ | |
| 248 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ | |
| 249 | #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ | |
| 250 | #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ | |
| 251 | #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ | |
| 252 | #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ | |
| 253 | #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ | |
| 254 | #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ | |
| 255 | #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ | |
| 256 | #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ | |
| 257 | #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ | |
| 258 | #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ | |
| 259 | #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ | |
| 260 | #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ | |
| 261 | #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ | |
| 262 | #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ | |
| 263 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ | |
| 264 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ | |
| 265 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ | |
| 266 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ | |
| 267 | /* Interrupt Cause Rx Packet Timer Expire Count */ | |
| 268 | #define E1000_ICRXPTC 0x04104 | |
| 269 | /* Interrupt Cause Rx Absolute Timer Expire Count */ | |
| 270 | #define E1000_ICRXATC 0x04108 | |
| 271 | /* Interrupt Cause Tx Packet Timer Expire Count */ | |
| 272 | #define E1000_ICTXPTC 0x0410C | |
| 273 | /* Interrupt Cause Tx Absolute Timer Expire Count */ | |
| 274 | #define E1000_ICTXATC 0x04110 | |
| 275 | /* Interrupt Cause Tx Queue Empty Count */ | |
| 276 | #define E1000_ICTXQEC 0x04118 | |
| 277 | /* Interrupt Cause Tx Queue Minimum Threshold Count */ | |
| 278 | #define E1000_ICTXQMTC 0x0411C | |
| 279 | /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ | |
| 280 | #define E1000_ICRXDMTC 0x04120 | |
| 281 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ | |
| 282 | #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ | |
| 283 | #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ | |
| 284 | #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ | |
| 285 | #define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */ | |
| 286 | #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */ | |
| 287 | #define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */ | |
| 288 | #define E1000_RPTHC 0x04104 /* Rx Packets To Host */ | |
| 289 | #define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */ | |
| 290 | #define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */ | |
| 291 | #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */ | |
| 292 | #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */ | |
| 293 | #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */ | |
| 294 | #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */ | |
| 295 | #define E1000_LENERRS 0x04138 /* Length Errors Count */ | |
| 296 | #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */ | |
| 297 | #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ | |
| 298 | #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ | |
| 299 | #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */ | |
| 300 | #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */ | |
| 301 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ | |
| 302 | #define E1000_RLPML 0x05004 /* RX Long Packet Max Length */ | |
| 303 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | |
| 304 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ | |
| 305 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ | |
| b980ac18 | 306 | #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ |
| 83ab50a5 | 307 | #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) |
| 5e8427e5 | 308 | #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ |
| 9005df38 | 309 | (0x054E0 + ((_i - 16) * 8))) |
| 5e8427e5 | 310 | #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ |
| 9005df38 | 311 | (0x054E4 + ((_i - 16) * 8))) |
| 7a277a96 | 312 | #define E1000_VLAPQF 0x055B0 /* VLAN Priority Queue Filter VLAPQF */ |
| 83ab50a5 AD |
313 | #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8)) |
| 314 | #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4)) | |
| 315 | #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4)) | |
| 316 | #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8)) | |
| 317 | #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8)) | |
| 318 | #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8)) | |
| 9d5c8243 | 319 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
| e1739522 | 320 | #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ |
| 9d5c8243 AK |
321 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ |
| 322 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ | |
| 323 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ | |
| 324 | #define E1000_MANC 0x05820 /* Management Control - RW */ | |
| 325 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | |
| 326 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | |
| 9d5c8243 | 327 | |
| 9d5c8243 AK |
328 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
| 329 | #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ | |
| 330 | #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ | |
| 331 | #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ | |
| 009bc06e | 332 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ |
| 9d5c8243 AK |
333 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
| 334 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ | |
| 335 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ | |
| fe4506b6 | 336 | #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ |
| 9d5c8243 AK |
337 | |
| 338 | /* RSS registers */ | |
| 339 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | |
| 340 | #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */ | |
| 341 | #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* Immediate Interrupt Ext*/ | |
| 342 | #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ | |
| 343 | /* MSI-X Allocation Register (_i) - RW */ | |
| 344 | #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) | |
| 9d5c8243 AK |
345 | /* Redirection Table - RW Array */ |
| 346 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) | |
| 347 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ | |
| 348 | ||
| e1739522 | 349 | /* VT Registers */ |
| 4ae196df AD |
350 | #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ |
| 351 | #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ | |
| 352 | #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ | |
| 353 | #define E1000_VFRE 0x00C8C /* VF Receive Enables */ | |
| 354 | #define E1000_VFTE 0x00C90 /* VF Transmit Enables */ | |
| e1739522 | 355 | #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ |
| 4ae196df | 356 | #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ |
| 13800469 | 357 | #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */ |
| 4ae196df | 358 | #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ |
| 68d480c4 | 359 | #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ |
| 4ae196df | 360 | #define E1000_IOVTCL 0x05BBC /* IOV Control Register */ |
| ca2e3e7e | 361 | #define E1000_TXSWC 0x05ACC /* Tx Switch Control */ |
| 1516f0a6 | 362 | #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */ |
| e1739522 | 363 | /* These act per VF so an array friendly macro is used */ |
| 4ae196df AD |
364 | #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) |
| 365 | #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) | |
| e1739522 | 366 | #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) |
| dc1edc67 | 367 | #define E1000_DVMOLR(_n) (0x0C038 + (64 * (_n))) |
| 9005df38 | 368 | #define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN VM Filter */ |
| 8151d294 | 369 | #define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) |
| e1739522 | 370 | |
| 22a8b291 FT |
371 | struct e1000_hw; |
| 372 | ||
| 373 | u32 igb_rd32(struct e1000_hw *hw, u32 reg); | |
| 374 | ||
| 375 | /* write operations, indexed using DWORDS */ | |
| 376 | #define wr32(reg, val) \ | |
| 377 | do { \ | |
| 378 | u8 __iomem *hw_addr = ACCESS_ONCE((hw)->hw_addr); \ | |
| 379 | if (!E1000_REMOVED(hw_addr)) \ | |
| 380 | writel((val), &hw_addr[(reg)]); \ | |
| 381 | } while (0) | |
| 382 | ||
| 383 | #define rd32(reg) (igb_rd32(hw, reg)) | |
| 384 | ||
| 9d5c8243 AK |
385 | #define wrfl() ((void)rd32(E1000_STATUS)) |
| 386 | ||
| 387 | #define array_wr32(reg, offset, value) \ | |
| 22a8b291 FT |
388 | wr32((reg) + ((offset) << 2), (value)) |
| 389 | ||
| 7b06a690 | 390 | #define array_rd32(reg, offset) (igb_rd32(hw, reg + ((offset) << 2))) |
| 9d5c8243 | 391 | |
| 55cac248 | 392 | /* DMA Coalescing registers */ |
| b980ac18 | 393 | #define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ |
| 0a915b95 | 394 | |
| 09b068d4 | 395 | /* Energy Efficient Ethernet "EEE" register */ |
| b980ac18 JK |
396 | #define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ |
| 397 | #define E1000_EEER 0x0E30 /* Energy Efficient Ethernet */ | |
| 398 | #define E1000_EEE_SU 0X0E34 /* EEE Setup */ | |
| 87371b9d MV |
399 | #define E1000_EMIADD 0x10 /* Extended Memory Indirect Address */ |
| 400 | #define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */ | |
| 401 | #define E1000_MMDAC 13 /* MMD Access Control */ | |
| 402 | #define E1000_MMDAAD 14 /* MMD Access Address/Data */ | |
| 09b068d4 | 403 | |
| 7ef5ed1c | 404 | /* Thermal Sensor Register */ |
| b980ac18 | 405 | #define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ |
| 7ef5ed1c | 406 | |
| 0a915b95 | 407 | /* OS2BMC Registers */ |
| b980ac18 JK |
408 | #define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ |
| 409 | #define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ | |
| 410 | #define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ | |
| 411 | #define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ | |
| 0a915b95 | 412 | |
| f96a8a0b CW |
413 | #define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */ |
| 414 | #define E1000_I210_FLMNGCTL 0x12038 | |
| 415 | #define E1000_I210_FLMNGDATA 0x1203C | |
| 416 | #define E1000_I210_FLMNGCNT 0x12040 | |
| 417 | ||
| 418 | #define E1000_I210_FLSWCTL 0x12048 | |
| 419 | #define E1000_I210_FLSWDATA 0x1204C | |
| 420 | #define E1000_I210_FLSWCNT 0x12050 | |
| 421 | ||
| 422 | #define E1000_I210_FLA 0x1201C | |
| 423 | ||
| 424 | #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) | |
| 425 | #define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */ | |
| 426 | ||
| 22a8b291 FT |
427 | #define E1000_REMOVED(h) unlikely(!(h)) |
| 428 | ||
| 9d5c8243 | 429 | #endif |