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Merge remote-tracking branch 'block/for-next'
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243
AK		 23
24/* ethtool support for igb */
25
26#include <linux/vmalloc.h>
27#include <linux/netdevice.h>
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
31#include <linux/if_ether.h>
32#include <linux/ethtool.h>
d43c36dc 33#include <linux/sched.h>
5a0e3ad6 34#include <linux/slab.h>
749ab2cd 35#include <linux/pm_runtime.h>
1a1c225b 36#include <linux/highmem.h>
87371b9d 37#include <linux/mdio.h>
9d5c8243
AK		 38
39#include "igb.h"
40
41struct igb_stats {
42 char stat_string[ETH_GSTRING_LEN];
43 int sizeof_stat;
44 int stat_offset;
45};
46
128e45eb
AD		 47#define IGB_STAT(_name, _stat) { \
48 .stat_string = _name, \
49 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
50 .stat_offset = offsetof(struct igb_adapter, _stat) \
51}
9d5c8243 52static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 53 IGB_STAT("rx_packets", stats.gprc),
54 IGB_STAT("tx_packets", stats.gptc),
55 IGB_STAT("rx_bytes", stats.gorc),
56 IGB_STAT("tx_bytes", stats.gotc),
57 IGB_STAT("rx_broadcast", stats.bprc),
58 IGB_STAT("tx_broadcast", stats.bptc),
59 IGB_STAT("rx_multicast", stats.mprc),
60 IGB_STAT("tx_multicast", stats.mptc),
61 IGB_STAT("multicast", stats.mprc),
62 IGB_STAT("collisions", stats.colc),
63 IGB_STAT("rx_crc_errors", stats.crcerrs),
64 IGB_STAT("rx_no_buffer_count", stats.rnbc),
65 IGB_STAT("rx_missed_errors", stats.mpc),
66 IGB_STAT("tx_aborted_errors", stats.ecol),
67 IGB_STAT("tx_carrier_errors", stats.tncrs),
68 IGB_STAT("tx_window_errors", stats.latecol),
69 IGB_STAT("tx_abort_late_coll", stats.latecol),
70 IGB_STAT("tx_deferred_ok", stats.dc),
71 IGB_STAT("tx_single_coll_ok", stats.scc),
72 IGB_STAT("tx_multi_coll_ok", stats.mcc),
73 IGB_STAT("tx_timeout_count", tx_timeout_count),
74 IGB_STAT("rx_long_length_errors", stats.roc),
75 IGB_STAT("rx_short_length_errors", stats.ruc),
76 IGB_STAT("rx_align_errors", stats.algnerrc),
77 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
78 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
79 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
80 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
81 IGB_STAT("tx_flow_control_xon", stats.xontxc),
82 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
83 IGB_STAT("rx_long_byte_count", stats.gorc),
84 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
85 IGB_STAT("tx_smbus", stats.mgptc),
86 IGB_STAT("rx_smbus", stats.mgprc),
87 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 88 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
89 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
90 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
91 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
428f1f71 92 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
fc580751 93 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
128e45eb
AD		 94};
95
96#define IGB_NETDEV_STAT(_net_stat) { \
97 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 100}
101static const struct igb_stats igb_gstrings_net_stats[] = {
102 IGB_NETDEV_STAT(rx_errors),
103 IGB_NETDEV_STAT(tx_errors),
104 IGB_NETDEV_STAT(tx_dropped),
105 IGB_NETDEV_STAT(rx_length_errors),
106 IGB_NETDEV_STAT(rx_over_errors),
107 IGB_NETDEV_STAT(rx_frame_errors),
108 IGB_NETDEV_STAT(rx_fifo_errors),
109 IGB_NETDEV_STAT(tx_fifo_errors),
110 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 111};
112
128e45eb
AD		 113#define IGB_GLOBAL_STATS_LEN \
114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
115#define IGB_NETDEV_STATS_LEN \
116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
117#define IGB_RX_QUEUE_STATS_LEN \
118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 119
120#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
121
9d5c8243 122#define IGB_QUEUE_STATS_LEN \
317f66bd 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 124 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 126 IGB_TX_QUEUE_STATS_LEN))
127#define IGB_STATS_LEN \
128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
129
d602de05
JS		 130enum igb_diagnostics_results {
131 TEST_REG = 0,
132 TEST_EEP,
133 TEST_IRQ,
134 TEST_LOOP,
135 TEST_LINK
136};
137
9d5c8243 138static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
d602de05
JS		 139 [TEST_REG] = "Register test (offline)",
140 [TEST_EEP] = "Eeprom test (offline)",
141 [TEST_IRQ] = "Interrupt test (offline)",
142 [TEST_LOOP] = "Loopback test (offline)",
143 [TEST_LINK] = "Link test (on/offline)"
9d5c8243 144};
317f66bd 145#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 146
147static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
148{
149 struct igb_adapter *adapter = netdev_priv(netdev);
150 struct e1000_hw *hw = &adapter->hw;
641ac5c0
AA		 151 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
152 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
317f66bd 153 u32 status;
d4f3cd49 154 u32 speed;
9d5c8243 155
01237139 156 status = rd32(E1000_STATUS);
9d5c8243
AK		 157 if (hw->phy.media_type == e1000_media_type_copper) {
158
159 ecmd->supported = (SUPPORTED_10baseT_Half |
160 SUPPORTED_10baseT_Full |
161 SUPPORTED_100baseT_Half |
162 SUPPORTED_100baseT_Full |
163 SUPPORTED_1000baseT_Full|
164 SUPPORTED_Autoneg |
42f3c43b
AA		 165 SUPPORTED_TP |
166 SUPPORTED_Pause);
167 ecmd->advertising = ADVERTISED_TP;
9d5c8243
AK		 168
169 if (hw->mac.autoneg == 1) {
170 ecmd->advertising |= ADVERTISED_Autoneg;
171 /* the e1000 autoneg seems to match ethtool nicely */
172 ecmd->advertising |= hw->phy.autoneg_advertised;
173 }
174
175 ecmd->port = PORT_TP;
176 ecmd->phy_address = hw->phy.addr;
f502ef7d 177 ecmd->transceiver = XCVR_INTERNAL;
9d5c8243 178 } else {
641ac5c0 179 ecmd->supported = (SUPPORTED_FIBRE |
01237139 180 SUPPORTED_1000baseKX_Full |
ceb5f13b
CW		 181 SUPPORTED_Autoneg |
182 SUPPORTED_Pause);
01237139
CW		 183 ecmd->advertising = (ADVERTISED_FIBRE |
184 ADVERTISED_1000baseKX_Full);
185 if (hw->mac.type == e1000_i354) {
186 if ((hw->device_id ==
187 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
188 !(status & E1000_STATUS_2P5_SKU_OVER)) {
189 ecmd->supported |= SUPPORTED_2500baseX_Full;
190 ecmd->supported &=
191 ~SUPPORTED_1000baseKX_Full;
192 ecmd->advertising |= ADVERTISED_2500baseX_Full;
193 ecmd->advertising &=
194 ~ADVERTISED_1000baseKX_Full;
195 }
641ac5c0
AA		 196 }
197 if (eth_flags->e100_base_fx) {
198 ecmd->supported |= SUPPORTED_100baseT_Full;
199 ecmd->advertising |= ADVERTISED_100baseT_Full;
ceb5f13b 200 }
f502ef7d
AA		 201 if (hw->mac.autoneg == 1)
202 ecmd->advertising |= ADVERTISED_Autoneg;
9d5c8243
AK		 203
204 ecmd->port = PORT_FIBRE;
f502ef7d 205 ecmd->transceiver = XCVR_EXTERNAL;
9d5c8243 206 }
373e6978
AA		 207 if (hw->mac.autoneg != 1)
208 ecmd->advertising &= ~(ADVERTISED_Pause |
209 ADVERTISED_Asym_Pause);
210
01237139
CW		 211 switch (hw->fc.requested_mode) {
212 case e1000_fc_full:
373e6978 213 ecmd->advertising |= ADVERTISED_Pause;
01237139
CW		 214 break;
215 case e1000_fc_rx_pause:
373e6978
AA		 216 ecmd->advertising |= (ADVERTISED_Pause |
217 ADVERTISED_Asym_Pause);
01237139
CW		 218 break;
219 case e1000_fc_tx_pause:
373e6978 220 ecmd->advertising |= ADVERTISED_Asym_Pause;
01237139
CW		 221 break;
222 default:
373e6978
AA		 223 ecmd->advertising &= ~(ADVERTISED_Pause |
224 ADVERTISED_Asym_Pause);
01237139 225 }
317f66bd 226 if (status & E1000_STATUS_LU) {
01237139
CW		 227 if ((status & E1000_STATUS_2P5_SKU) &&
228 !(status & E1000_STATUS_2P5_SKU_OVER)) {
d4f3cd49 229 speed = SPEED_2500;
41fcfbea 230 } else if (status & E1000_STATUS_SPEED_1000) {
d4f3cd49 231 speed = SPEED_1000;
41fcfbea 232 } else if (status & E1000_STATUS_SPEED_100) {
d4f3cd49 233 speed = SPEED_100;
41fcfbea 234 } else {
d4f3cd49 235 speed = SPEED_10;
41fcfbea 236 }
317f66bd
AD		 237 if ((status & E1000_STATUS_FD) ||
238 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 239 ecmd->duplex = DUPLEX_FULL;
240 else
241 ecmd->duplex = DUPLEX_HALF;
242 } else {
d4f3cd49 243 speed = SPEED_UNKNOWN;
537fae01 244 ecmd->duplex = DUPLEX_UNKNOWN;
9d5c8243 245 }
d4f3cd49 246 ethtool_cmd_speed_set(ecmd, speed);
f502ef7d
AA		 247 if ((hw->phy.media_type == e1000_media_type_fiber) ||
248 hw->mac.autoneg)
249 ecmd->autoneg = AUTONEG_ENABLE;
250 else
251 ecmd->autoneg = AUTONEG_DISABLE;
8376dad0
JB		 252
253 /* MDI-X => 2; MDI =>1; Invalid =>0 */
254 if (hw->phy.media_type == e1000_media_type_copper)
255 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
256 ETH_TP_MDI;
257 else
258 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
259
260 if (hw->phy.mdix == AUTO_ALL_MODES)
261 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
262 else
263 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
264
9d5c8243
AK		 265 return 0;
266}
267
268static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
269{
270 struct igb_adapter *adapter = netdev_priv(netdev);
271 struct e1000_hw *hw = &adapter->hw;
272
273 /* When SoL/IDER sessions are active, autoneg/speed/duplex
b980ac18
JK		 274 * cannot be changed
275 */
9d5c8243 276 if (igb_check_reset_block(hw)) {
d836200a
JJ		 277 dev_err(&adapter->pdev->dev,
278 "Cannot change link characteristics when SoL/IDER is active.\n");
9d5c8243
AK		 279 return -EINVAL;
280 }
281
b980ac18 282 /* MDI setting is only allowed when autoneg enabled because
8376dad0
JB		 283 * some hardware doesn't allow MDI setting when speed or
284 * duplex is forced.
285 */
286 if (ecmd->eth_tp_mdix_ctrl) {
287 if (hw->phy.media_type != e1000_media_type_copper)
288 return -EOPNOTSUPP;
289
290 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
291 (ecmd->autoneg != AUTONEG_ENABLE)) {
292 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
293 return -EINVAL;
294 }
295 }
296
9d5c8243 297 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 298 usleep_range(1000, 2000);
9d5c8243
AK		 299
300 if (ecmd->autoneg == AUTONEG_ENABLE) {
301 hw->mac.autoneg = 1;
f502ef7d
AA		 302 if (hw->phy.media_type == e1000_media_type_fiber) {
303 hw->phy.autoneg_advertised = ecmd->advertising |
304 ADVERTISED_FIBRE |
305 ADVERTISED_Autoneg;
ceb5f13b
CW		 306 switch (adapter->link_speed) {
307 case SPEED_2500:
308 hw->phy.autoneg_advertised =
309 ADVERTISED_2500baseX_Full;
310 break;
311 case SPEED_1000:
f502ef7d
AA		 312 hw->phy.autoneg_advertised =
313 ADVERTISED_1000baseT_Full;
ceb5f13b
CW		 314 break;
315 case SPEED_100:
f502ef7d
AA		 316 hw->phy.autoneg_advertised =
317 ADVERTISED_100baseT_Full;
ceb5f13b
CW		 318 break;
319 default:
320 break;
321 }
f502ef7d
AA		 322 } else {
323 hw->phy.autoneg_advertised = ecmd->advertising |
324 ADVERTISED_TP |
325 ADVERTISED_Autoneg;
326 }
9d5c8243 327 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 328 if (adapter->fc_autoneg)
329 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 330 } else {
25db0338 331 u32 speed = ethtool_cmd_speed(ecmd);
8376dad0 332 /* calling this overrides forced MDI setting */
14ad2513 333 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 334 clear_bit(__IGB_RESETTING, &adapter->state);
335 return -EINVAL;
336 }
dcc3ae9a 337 }
9d5c8243 338
8376dad0
JB		 339 /* MDI-X => 2; MDI => 1; Auto => 3 */
340 if (ecmd->eth_tp_mdix_ctrl) {
b980ac18 341 /* fix up the value for auto (3 => 0) as zero is mapped
8376dad0
JB		 342 * internally to auto
343 */
344 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
345 hw->phy.mdix = AUTO_ALL_MODES;
346 else
347 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
348 }
349
9d5c8243 350 /* reset the link */
9d5c8243
AK		 351 if (netif_running(adapter->netdev)) {
352 igb_down(adapter);
353 igb_up(adapter);
354 } else
355 igb_reset(adapter);
356
357 clear_bit(__IGB_RESETTING, &adapter->state);
358 return 0;
359}
360
3145535a
NN		 361static u32 igb_get_link(struct net_device *netdev)
362{
363 struct igb_adapter *adapter = netdev_priv(netdev);
364 struct e1000_mac_info *mac = &adapter->hw.mac;
365
b980ac18 366 /* If the link is not reported up to netdev, interrupts are disabled,
3145535a
NN		 367 * and so the physical link state may have changed since we last
368 * looked. Set get_link_status to make sure that the true link
369 * state is interrogated, rather than pulling a cached and possibly
370 * stale link state from the driver.
371 */
372 if (!netif_carrier_ok(netdev))
373 mac->get_link_status = 1;
374
375 return igb_has_link(adapter);
376}
377
9d5c8243
AK		 378static void igb_get_pauseparam(struct net_device *netdev,
379 struct ethtool_pauseparam *pause)
380{
381 struct igb_adapter *adapter = netdev_priv(netdev);
382 struct e1000_hw *hw = &adapter->hw;
383
384 pause->autoneg =
385 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
386
0cce119a 387 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 388 pause->rx_pause = 1;
0cce119a 389 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 390 pause->tx_pause = 1;
0cce119a 391 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 392 pause->rx_pause = 1;
393 pause->tx_pause = 1;
394 }
395}
396
397static int igb_set_pauseparam(struct net_device *netdev,
398 struct ethtool_pauseparam *pause)
399{
400 struct igb_adapter *adapter = netdev_priv(netdev);
401 struct e1000_hw *hw = &adapter->hw;
402 int retval = 0;
403
373e6978
AA		 404 /* 100basefx does not support setting link flow control */
405 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
406 return -EINVAL;
407
9d5c8243
AK		 408 adapter->fc_autoneg = pause->autoneg;
409
410 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 411 usleep_range(1000, 2000);
9d5c8243 412
9d5c8243 413 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 414 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 415 if (netif_running(adapter->netdev)) {
416 igb_down(adapter);
417 igb_up(adapter);
317f66bd 418 } else {
9d5c8243 419 igb_reset(adapter);
317f66bd 420 }
0cce119a
AD		 421 } else {
422 if (pause->rx_pause && pause->tx_pause)
423 hw->fc.requested_mode = e1000_fc_full;
424 else if (pause->rx_pause && !pause->tx_pause)
425 hw->fc.requested_mode = e1000_fc_rx_pause;
426 else if (!pause->rx_pause && pause->tx_pause)
427 hw->fc.requested_mode = e1000_fc_tx_pause;
428 else if (!pause->rx_pause && !pause->tx_pause)
429 hw->fc.requested_mode = e1000_fc_none;
430
431 hw->fc.current_mode = hw->fc.requested_mode;
432
dcc3ae9a
AD		 433 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
434 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 435 }
9d5c8243
AK		 436
437 clear_bit(__IGB_RESETTING, &adapter->state);
438 return retval;
439}
440
9d5c8243
AK		 441static u32 igb_get_msglevel(struct net_device *netdev)
442{
443 struct igb_adapter *adapter = netdev_priv(netdev);
444 return adapter->msg_enable;
445}
446
447static void igb_set_msglevel(struct net_device *netdev, u32 data)
448{
449 struct igb_adapter *adapter = netdev_priv(netdev);
450 adapter->msg_enable = data;
451}
452
453static int igb_get_regs_len(struct net_device *netdev)
454{
7e3b4ffb 455#define IGB_REGS_LEN 739
9d5c8243
AK		 456 return IGB_REGS_LEN * sizeof(u32);
457}
458
459static void igb_get_regs(struct net_device *netdev,
460 struct ethtool_regs *regs, void *p)
461{
462 struct igb_adapter *adapter = netdev_priv(netdev);
463 struct e1000_hw *hw = &adapter->hw;
464 u32 *regs_buff = p;
465 u8 i;
466
467 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
468
a51d8c21 469 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
9d5c8243
AK		 470
471 /* General Registers */
472 regs_buff[0] = rd32(E1000_CTRL);
473 regs_buff[1] = rd32(E1000_STATUS);
474 regs_buff[2] = rd32(E1000_CTRL_EXT);
475 regs_buff[3] = rd32(E1000_MDIC);
476 regs_buff[4] = rd32(E1000_SCTL);
477 regs_buff[5] = rd32(E1000_CONNSW);
478 regs_buff[6] = rd32(E1000_VET);
479 regs_buff[7] = rd32(E1000_LEDCTL);
480 regs_buff[8] = rd32(E1000_PBA);
481 regs_buff[9] = rd32(E1000_PBS);
482 regs_buff[10] = rd32(E1000_FRTIMER);
483 regs_buff[11] = rd32(E1000_TCPTIMER);
484
485 /* NVM Register */
486 regs_buff[12] = rd32(E1000_EECD);
487
488 /* Interrupt */
fe59de38 489 /* Reading EICS for EICR because they read the
b980ac18
JK		 490 * same but EICS does not clear on read
491 */
fe59de38 492 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 493 regs_buff[14] = rd32(E1000_EICS);
494 regs_buff[15] = rd32(E1000_EIMS);
495 regs_buff[16] = rd32(E1000_EIMC);
496 regs_buff[17] = rd32(E1000_EIAC);
497 regs_buff[18] = rd32(E1000_EIAM);
fe59de38 498 /* Reading ICS for ICR because they read the
b980ac18
JK		 499 * same but ICS does not clear on read
500 */
fe59de38 501 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 502 regs_buff[20] = rd32(E1000_ICS);
503 regs_buff[21] = rd32(E1000_IMS);
504 regs_buff[22] = rd32(E1000_IMC);
505 regs_buff[23] = rd32(E1000_IAC);
506 regs_buff[24] = rd32(E1000_IAM);
507 regs_buff[25] = rd32(E1000_IMIRVP);
508
509 /* Flow Control */
510 regs_buff[26] = rd32(E1000_FCAL);
511 regs_buff[27] = rd32(E1000_FCAH);
512 regs_buff[28] = rd32(E1000_FCTTV);
513 regs_buff[29] = rd32(E1000_FCRTL);
514 regs_buff[30] = rd32(E1000_FCRTH);
515 regs_buff[31] = rd32(E1000_FCRTV);
516
517 /* Receive */
518 regs_buff[32] = rd32(E1000_RCTL);
519 regs_buff[33] = rd32(E1000_RXCSUM);
520 regs_buff[34] = rd32(E1000_RLPML);
521 regs_buff[35] = rd32(E1000_RFCTL);
522 regs_buff[36] = rd32(E1000_MRQC);
e1739522 523 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 524
525 /* Transmit */
526 regs_buff[38] = rd32(E1000_TCTL);
527 regs_buff[39] = rd32(E1000_TCTL_EXT);
528 regs_buff[40] = rd32(E1000_TIPG);
529 regs_buff[41] = rd32(E1000_DTXCTL);
530
531 /* Wake Up */
532 regs_buff[42] = rd32(E1000_WUC);
533 regs_buff[43] = rd32(E1000_WUFC);
534 regs_buff[44] = rd32(E1000_WUS);
535 regs_buff[45] = rd32(E1000_IPAV);
536 regs_buff[46] = rd32(E1000_WUPL);
537
538 /* MAC */
539 regs_buff[47] = rd32(E1000_PCS_CFG0);
540 regs_buff[48] = rd32(E1000_PCS_LCTL);
541 regs_buff[49] = rd32(E1000_PCS_LSTAT);
542 regs_buff[50] = rd32(E1000_PCS_ANADV);
543 regs_buff[51] = rd32(E1000_PCS_LPAB);
544 regs_buff[52] = rd32(E1000_PCS_NPTX);
545 regs_buff[53] = rd32(E1000_PCS_LPABNP);
546
547 /* Statistics */
548 regs_buff[54] = adapter->stats.crcerrs;
549 regs_buff[55] = adapter->stats.algnerrc;
550 regs_buff[56] = adapter->stats.symerrs;
551 regs_buff[57] = adapter->stats.rxerrc;
552 regs_buff[58] = adapter->stats.mpc;
553 regs_buff[59] = adapter->stats.scc;
554 regs_buff[60] = adapter->stats.ecol;
555 regs_buff[61] = adapter->stats.mcc;
556 regs_buff[62] = adapter->stats.latecol;
557 regs_buff[63] = adapter->stats.colc;
558 regs_buff[64] = adapter->stats.dc;
559 regs_buff[65] = adapter->stats.tncrs;
560 regs_buff[66] = adapter->stats.sec;
561 regs_buff[67] = adapter->stats.htdpmc;
562 regs_buff[68] = adapter->stats.rlec;
563 regs_buff[69] = adapter->stats.xonrxc;
564 regs_buff[70] = adapter->stats.xontxc;
565 regs_buff[71] = adapter->stats.xoffrxc;
566 regs_buff[72] = adapter->stats.xofftxc;
567 regs_buff[73] = adapter->stats.fcruc;
568 regs_buff[74] = adapter->stats.prc64;
569 regs_buff[75] = adapter->stats.prc127;
570 regs_buff[76] = adapter->stats.prc255;
571 regs_buff[77] = adapter->stats.prc511;
572 regs_buff[78] = adapter->stats.prc1023;
573 regs_buff[79] = adapter->stats.prc1522;
574 regs_buff[80] = adapter->stats.gprc;
575 regs_buff[81] = adapter->stats.bprc;
576 regs_buff[82] = adapter->stats.mprc;
577 regs_buff[83] = adapter->stats.gptc;
578 regs_buff[84] = adapter->stats.gorc;
579 regs_buff[86] = adapter->stats.gotc;
580 regs_buff[88] = adapter->stats.rnbc;
581 regs_buff[89] = adapter->stats.ruc;
582 regs_buff[90] = adapter->stats.rfc;
583 regs_buff[91] = adapter->stats.roc;
584 regs_buff[92] = adapter->stats.rjc;
585 regs_buff[93] = adapter->stats.mgprc;
586 regs_buff[94] = adapter->stats.mgpdc;
587 regs_buff[95] = adapter->stats.mgptc;
588 regs_buff[96] = adapter->stats.tor;
589 regs_buff[98] = adapter->stats.tot;
590 regs_buff[100] = adapter->stats.tpr;
591 regs_buff[101] = adapter->stats.tpt;
592 regs_buff[102] = adapter->stats.ptc64;
593 regs_buff[103] = adapter->stats.ptc127;
594 regs_buff[104] = adapter->stats.ptc255;
595 regs_buff[105] = adapter->stats.ptc511;
596 regs_buff[106] = adapter->stats.ptc1023;
597 regs_buff[107] = adapter->stats.ptc1522;
598 regs_buff[108] = adapter->stats.mptc;
599 regs_buff[109] = adapter->stats.bptc;
600 regs_buff[110] = adapter->stats.tsctc;
601 regs_buff[111] = adapter->stats.iac;
602 regs_buff[112] = adapter->stats.rpthc;
603 regs_buff[113] = adapter->stats.hgptc;
604 regs_buff[114] = adapter->stats.hgorc;
605 regs_buff[116] = adapter->stats.hgotc;
606 regs_buff[118] = adapter->stats.lenerrs;
607 regs_buff[119] = adapter->stats.scvpc;
608 regs_buff[120] = adapter->stats.hrmpc;
609
9d5c8243
AK		 610 for (i = 0; i < 4; i++)
611 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
612 for (i = 0; i < 4; i++)
83ab50a5 613 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 614 for (i = 0; i < 4; i++)
615 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
616 for (i = 0; i < 4; i++)
617 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
618 for (i = 0; i < 4; i++)
619 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
620 for (i = 0; i < 4; i++)
621 regs_buff[141 + i] = rd32(E1000_RDH(i));
622 for (i = 0; i < 4; i++)
623 regs_buff[145 + i] = rd32(E1000_RDT(i));
624 for (i = 0; i < 4; i++)
625 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
626
627 for (i = 0; i < 10; i++)
628 regs_buff[153 + i] = rd32(E1000_EITR(i));
629 for (i = 0; i < 8; i++)
630 regs_buff[163 + i] = rd32(E1000_IMIR(i));
631 for (i = 0; i < 8; i++)
632 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
633 for (i = 0; i < 16; i++)
634 regs_buff[179 + i] = rd32(E1000_RAL(i));
635 for (i = 0; i < 16; i++)
636 regs_buff[195 + i] = rd32(E1000_RAH(i));
637
638 for (i = 0; i < 4; i++)
639 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
640 for (i = 0; i < 4; i++)
641 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
642 for (i = 0; i < 4; i++)
643 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
644 for (i = 0; i < 4; i++)
645 regs_buff[223 + i] = rd32(E1000_TDH(i));
646 for (i = 0; i < 4; i++)
647 regs_buff[227 + i] = rd32(E1000_TDT(i));
648 for (i = 0; i < 4; i++)
649 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
650 for (i = 0; i < 4; i++)
651 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
652 for (i = 0; i < 4; i++)
653 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
654 for (i = 0; i < 4; i++)
655 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
656
657 for (i = 0; i < 4; i++)
658 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
659 for (i = 0; i < 4; i++)
660 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
661 for (i = 0; i < 32; i++)
662 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
663 for (i = 0; i < 128; i++)
664 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
665 for (i = 0; i < 128; i++)
666 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
667 for (i = 0; i < 4; i++)
668 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
669
670 regs_buff[547] = rd32(E1000_TDFH);
671 regs_buff[548] = rd32(E1000_TDFT);
672 regs_buff[549] = rd32(E1000_TDFHS);
673 regs_buff[550] = rd32(E1000_TDFPC);
f96a8a0b
CW		 674
675 if (hw->mac.type > e1000_82580) {
676 regs_buff[551] = adapter->stats.o2bgptc;
677 regs_buff[552] = adapter->stats.b2ospc;
678 regs_buff[553] = adapter->stats.o2bspc;
679 regs_buff[554] = adapter->stats.b2ogprc;
680 }
7e3b4ffb
KS		 681
682 if (hw->mac.type != e1000_82576)
683 return;
684 for (i = 0; i < 12; i++)
685 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
686 for (i = 0; i < 4; i++)
687 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
688 for (i = 0; i < 12; i++)
689 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
690 for (i = 0; i < 12; i++)
691 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
692 for (i = 0; i < 12; i++)
693 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
694 for (i = 0; i < 12; i++)
695 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
696 for (i = 0; i < 12; i++)
697 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
698 for (i = 0; i < 12; i++)
699 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
700
701 for (i = 0; i < 12; i++)
702 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
703 for (i = 0; i < 12; i++)
704 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
705 for (i = 0; i < 12; i++)
706 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
707 for (i = 0; i < 12; i++)
708 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
709 for (i = 0; i < 12; i++)
710 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
711 for (i = 0; i < 12; i++)
712 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
713 for (i = 0; i < 12; i++)
714 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
715 for (i = 0; i < 12; i++)
716 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
9d5c8243
AK		 717}
718
719static int igb_get_eeprom_len(struct net_device *netdev)
720{
721 struct igb_adapter *adapter = netdev_priv(netdev);
722 return adapter->hw.nvm.word_size * 2;
723}
724
725static int igb_get_eeprom(struct net_device *netdev,
726 struct ethtool_eeprom *eeprom, u8 *bytes)
727{
728 struct igb_adapter *adapter = netdev_priv(netdev);
729 struct e1000_hw *hw = &adapter->hw;
730 u16 *eeprom_buff;
731 int first_word, last_word;
732 int ret_val = 0;
733 u16 i;
734
735 if (eeprom->len == 0)
736 return -EINVAL;
737
738 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
739
740 first_word = eeprom->offset >> 1;
741 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
742
743 eeprom_buff = kmalloc(sizeof(u16) *
744 (last_word - first_word + 1), GFP_KERNEL);
745 if (!eeprom_buff)
746 return -ENOMEM;
747
748 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 749 ret_val = hw->nvm.ops.read(hw, first_word,
b980ac18
JK		 750 last_word - first_word + 1,
751 eeprom_buff);
9d5c8243
AK		 752 else {
753 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 754 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
b980ac18 755 &eeprom_buff[i]);
9d5c8243
AK		 756 if (ret_val)
757 break;
758 }
759 }
760
761 /* Device's eeprom is always little-endian, word addressable */
762 for (i = 0; i < last_word - first_word + 1; i++)
763 le16_to_cpus(&eeprom_buff[i]);
764
765 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
766 eeprom->len);
767 kfree(eeprom_buff);
768
769 return ret_val;
770}
771
772static int igb_set_eeprom(struct net_device *netdev,
773 struct ethtool_eeprom *eeprom, u8 *bytes)
774{
775 struct igb_adapter *adapter = netdev_priv(netdev);
776 struct e1000_hw *hw = &adapter->hw;
777 u16 *eeprom_buff;
778 void *ptr;
779 int max_len, first_word, last_word, ret_val = 0;
780 u16 i;
781
782 if (eeprom->len == 0)
783 return -EOPNOTSUPP;
784
a71fc313
FT		 785 if ((hw->mac.type >= e1000_i210) &&
786 !igb_get_flash_presence_i210(hw)) {
f96a8a0b 787 return -EOPNOTSUPP;
a71fc313 788 }
f96a8a0b 789
9d5c8243
AK		 790 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
791 return -EFAULT;
792
793 max_len = hw->nvm.word_size * 2;
794
795 first_word = eeprom->offset >> 1;
796 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
797 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
798 if (!eeprom_buff)
799 return -ENOMEM;
800
801 ptr = (void *)eeprom_buff;
802
803 if (eeprom->offset & 1) {
b980ac18
JK		 804 /* need read/modify/write of first changed EEPROM word
805 * only the second byte of the word is being modified
806 */
312c75ae 807 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 808 &eeprom_buff[0]);
809 ptr++;
810 }
811 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
b980ac18
JK		 812 /* need read/modify/write of last changed EEPROM word
813 * only the first byte of the word is being modified
814 */
312c75ae 815 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 816 &eeprom_buff[last_word - first_word]);
817 }
818
819 /* Device's eeprom is always little-endian, word addressable */
820 for (i = 0; i < last_word - first_word + 1; i++)
821 le16_to_cpus(&eeprom_buff[i]);
822
823 memcpy(ptr, bytes, eeprom->len);
824
825 for (i = 0; i < last_word - first_word + 1; i++)
826 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
827
312c75ae 828 ret_val = hw->nvm.ops.write(hw, first_word,
b980ac18 829 last_word - first_word + 1, eeprom_buff);
9d5c8243 830
2a0a0f1e
CW		 831 /* Update the checksum if nvm write succeeded */
832 if (ret_val == 0)
4322e561 833 hw->nvm.ops.update(hw);
9d5c8243 834
d67974f0 835 igb_set_fw_version(adapter);
9d5c8243
AK		 836 kfree(eeprom_buff);
837 return ret_val;
838}
839
840static void igb_get_drvinfo(struct net_device *netdev,
841 struct ethtool_drvinfo *drvinfo)
842{
843 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 844
612a94d6
RJ		 845 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
846 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243 847
b980ac18 848 /* EEPROM image version # is reported as firmware version # for
d67974f0
CW		 849 * 82575 controllers
850 */
851 strlcpy(drvinfo->fw_version, adapter->fw_version,
852 sizeof(drvinfo->fw_version));
612a94d6
RJ		 853 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
854 sizeof(drvinfo->bus_info));
9d5c8243
AK		 855}
856
857static void igb_get_ringparam(struct net_device *netdev,
858 struct ethtool_ringparam *ring)
859{
860 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 861
862 ring->rx_max_pending = IGB_MAX_RXD;
863 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 864 ring->rx_pending = adapter->rx_ring_count;
865 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 866}
867
868static int igb_set_ringparam(struct net_device *netdev,
869 struct ethtool_ringparam *ring)
870{
871 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 872 struct igb_ring *temp_ring;
6d9f4fc4 873 int i, err = 0;
0e15439a 874 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 875
876 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
877 return -EINVAL;
878
0e15439a
AD		 879 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
880 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 881 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
882
0e15439a
AD		 883 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
884 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 885 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
886
68fd9910
AD		 887 if ((new_tx_count == adapter->tx_ring_count) &&
888 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 889 /* nothing to do */
890 return 0;
891 }
892
6d9f4fc4 893 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 894 usleep_range(1000, 2000);
6d9f4fc4
AD		 895
896 if (!netif_running(adapter->netdev)) {
897 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 898 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 899 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 900 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 901 adapter->tx_ring_count = new_tx_count;
902 adapter->rx_ring_count = new_rx_count;
903 goto clear_reset;
904 }
905
68fd9910 906 if (adapter->num_tx_queues > adapter->num_rx_queues)
b980ac18
JK		 907 temp_ring = vmalloc(adapter->num_tx_queues *
908 sizeof(struct igb_ring));
68fd9910 909 else
b980ac18
JK		 910 temp_ring = vmalloc(adapter->num_rx_queues *
911 sizeof(struct igb_ring));
68fd9910 912
6d9f4fc4
AD		 913 if (!temp_ring) {
914 err = -ENOMEM;
915 goto clear_reset;
916 }
9d5c8243 917
6d9f4fc4 918 igb_down(adapter);
9d5c8243 919
b980ac18 920 /* We can't just free everything and then setup again,
9d5c8243 921 * because the ISRs in MSI-X mode get passed pointers
b980ac18 922 * to the Tx and Rx ring structs.
9d5c8243 923 */
68fd9910 924 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 925 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 926 memcpy(&temp_ring[i], adapter->tx_ring[i],
927 sizeof(struct igb_ring));
928
68fd9910 929 temp_ring[i].count = new_tx_count;
80785298 930 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 931 if (err) {
68fd9910
AD		 932 while (i) {
933 i--;
934 igb_free_tx_resources(&temp_ring[i]);
935 }
9d5c8243
AK		 936 goto err_setup;
937 }
9d5c8243 938 }
68fd9910 939
3025a446
AD		 940 for (i = 0; i < adapter->num_tx_queues; i++) {
941 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 942
3025a446
AD		 943 memcpy(adapter->tx_ring[i], &temp_ring[i],
944 sizeof(struct igb_ring));
945 }
68fd9910
AD		 946
947 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 948 }
949
3025a446 950 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 951 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 952 memcpy(&temp_ring[i], adapter->rx_ring[i],
953 sizeof(struct igb_ring));
954
68fd9910 955 temp_ring[i].count = new_rx_count;
80785298 956 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 957 if (err) {
68fd9910
AD		 958 while (i) {
959 i--;
960 igb_free_rx_resources(&temp_ring[i]);
961 }
9d5c8243
AK		 962 goto err_setup;
963 }
964
9d5c8243 965 }
68fd9910 966
3025a446
AD		 967 for (i = 0; i < adapter->num_rx_queues; i++) {
968 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 969
3025a446
AD		 970 memcpy(adapter->rx_ring[i], &temp_ring[i],
971 sizeof(struct igb_ring));
972 }
68fd9910
AD		 973
974 adapter->rx_ring_count = new_rx_count;
9d5c8243 975 }
9d5c8243 976err_setup:
6d9f4fc4 977 igb_up(adapter);
68fd9910 978 vfree(temp_ring);
6d9f4fc4
AD		 979clear_reset:
980 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 981 return err;
982}
983
984/* ethtool register test data */
985struct igb_reg_test {
986 u16 reg;
2d064c06
AD		 987 u16 reg_offset;
988 u16 array_len;
989 u16 test_type;
9d5c8243
AK		 990 u32 mask;
991 u32 write;
992};
993
994/* In the hardware, registers are laid out either singly, in arrays
995 * spaced 0x100 bytes apart, or in contiguous tables. We assume
996 * most tests take place on arrays or single registers (handled
997 * as a single-element array) and special-case the tables.
998 * Table tests are always pattern tests.
999 *
1000 * We also make provision for some required setup steps by specifying
1001 * registers to be written without any read-back testing.
1002 */
1003
1004#define PATTERN_TEST 1
1005#define SET_READ_TEST 2
1006#define WRITE_NO_TEST 3
1007#define TABLE32_TEST 4
1008#define TABLE64_TEST_LO 5
1009#define TABLE64_TEST_HI 6
1010
f96a8a0b
CW		 1011/* i210 reg test */
1012static struct igb_reg_test reg_test_i210[] = {
1013 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1014 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1015 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1016 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1017 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1018 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1019 /* RDH is read-only for i210, only test RDT. */
1020 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1021 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1022 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1023 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1024 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1025 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1026 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1027 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1028 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1029 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1030 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1031 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1032 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1033 0xFFFFFFFF, 0xFFFFFFFF },
1034 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1035 0x900FFFFF, 0xFFFFFFFF },
1036 { E1000_MTA, 0, 128, TABLE32_TEST,
1037 0xFFFFFFFF, 0xFFFFFFFF },
1038 { 0, 0, 0, 0, 0 }
1039};
1040
d2ba2ed8
AD		 1041/* i350 reg test */
1042static struct igb_reg_test reg_test_i350[] = {
1043 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1044 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1045 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1046 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1047 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1048 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1049 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1050 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1051 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1052 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1053 /* RDH is read-only for i350, only test RDT. */
1054 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1055 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1056 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1057 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1058 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1059 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1060 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1061 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1062 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1063 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1064 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1065 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1066 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1067 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
9005df38
CW		 1068 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1069 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
d2ba2ed8
AD		 1070 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1071 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1072 0xFFFFFFFF, 0xFFFFFFFF },
1073 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1074 0xC3FFFFFF, 0xFFFFFFFF },
1075 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1076 0xFFFFFFFF, 0xFFFFFFFF },
1077 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1078 0xC3FFFFFF, 0xFFFFFFFF },
1079 { E1000_MTA, 0, 128, TABLE32_TEST,
1080 0xFFFFFFFF, 0xFFFFFFFF },
1081 { 0, 0, 0, 0 }
1082};
1083
55cac248
AD		 1084/* 82580 reg test */
1085static struct igb_reg_test reg_test_82580[] = {
1086 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1087 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1088 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1089 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1090 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1091 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1092 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1093 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1094 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1095 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1096 /* RDH is read-only for 82580, only test RDT. */
1097 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1098 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1099 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1100 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1101 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1102 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1103 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1104 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1105 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1106 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1107 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1108 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1109 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1110 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
9005df38
CW		 1111 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1112 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
55cac248
AD		 1113 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1114 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1115 0xFFFFFFFF, 0xFFFFFFFF },
1116 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1117 0x83FFFFFF, 0xFFFFFFFF },
1118 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1119 0xFFFFFFFF, 0xFFFFFFFF },
1120 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1121 0x83FFFFFF, 0xFFFFFFFF },
1122 { E1000_MTA, 0, 128, TABLE32_TEST,
1123 0xFFFFFFFF, 0xFFFFFFFF },
1124 { 0, 0, 0, 0 }
1125};
1126
2d064c06
AD		 1127/* 82576 reg test */
1128static struct igb_reg_test reg_test_82576[] = {
1129 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1130 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1131 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1132 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1133 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1134 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1135 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1136 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1137 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1138 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1139 /* Enable all RX queues before testing. */
c502ea2e
CW		 1140 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1141 E1000_RXDCTL_QUEUE_ENABLE },
1142 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1143 E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 1144 /* RDH is read-only for 82576, only test RDT. */
1145 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 1146 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 1147 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 1148 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 1149 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1150 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1151 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1152 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1153 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1154 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1155 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1156 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06 1158 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
9005df38
CW		 1159 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1160 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
2d064c06
AD		 1161 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1162 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1163 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1164 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1165 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
9005df38 1166 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
2d064c06
AD		 1167 { 0, 0, 0, 0 }
1168};
1169
1170/* 82575 register test */
9d5c8243 1171static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 1172 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1173 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1174 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1175 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1176 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1177 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1178 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 1179 /* Enable all four RX queues before testing. */
c502ea2e
CW		 1180 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1181 E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 1182 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1183 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1184 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1185 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1186 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1187 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1188 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1189 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1190 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1191 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1192 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1193 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1194 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1195 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1196 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1197 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1198 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1199 { 0, 0, 0, 0 }
1200};
1201
1202static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1203 int reg, u32 mask, u32 write)
1204{
2753f4ce 1205 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1206 u32 pat, val;
d34a15ab
CW		 1207 static const u32 _test[] = {
1208 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
9d5c8243 1209 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1210 wr32(reg, (_test[pat] & write));
93ed8359 1211 val = rd32(reg) & mask;
9d5c8243 1212 if (val != (_test[pat] & write & mask)) {
d836200a
JJ		 1213 dev_err(&adapter->pdev->dev,
1214 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
9d5c8243
AK		 1215 reg, val, (_test[pat] & write & mask));
1216 *data = reg;
f6f38e27 1217 return true;
9d5c8243
AK		 1218 }
1219 }
317f66bd 1220
f6f38e27 1221 return false;
9d5c8243
AK		 1222}
1223
1224static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1225 int reg, u32 mask, u32 write)
1226{
2753f4ce 1227 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1228 u32 val;
9005df38 1229
2753f4ce
AD		 1230 wr32(reg, write & mask);
1231 val = rd32(reg);
9d5c8243 1232 if ((write & mask) != (val & mask)) {
d836200a 1233 dev_err(&adapter->pdev->dev,
c502ea2e
CW		 1234 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1235 reg, (val & mask), (write & mask));
9d5c8243 1236 *data = reg;
f6f38e27 1237 return true;
9d5c8243 1238 }
317f66bd 1239
f6f38e27 1240 return false;
9d5c8243
AK		 1241}
1242
1243#define REG_PATTERN_TEST(reg, mask, write) \
1244 do { \
1245 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1246 return 1; \
1247 } while (0)
1248
1249#define REG_SET_AND_CHECK(reg, mask, write) \
1250 do { \
1251 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1252 return 1; \
1253 } while (0)
1254
1255static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1256{
1257 struct e1000_hw *hw = &adapter->hw;
1258 struct igb_reg_test *test;
1259 u32 value, before, after;
1260 u32 i, toggle;
1261
2d064c06 1262 switch (adapter->hw.mac.type) {
d2ba2ed8 1263 case e1000_i350:
ceb5f13b 1264 case e1000_i354:
d2ba2ed8
AD		 1265 test = reg_test_i350;
1266 toggle = 0x7FEFF3FF;
1267 break;
f96a8a0b
CW		 1268 case e1000_i210:
1269 case e1000_i211:
1270 test = reg_test_i210;
1271 toggle = 0x7FEFF3FF;
1272 break;
55cac248
AD		 1273 case e1000_82580:
1274 test = reg_test_82580;
1275 toggle = 0x7FEFF3FF;
1276 break;
2d064c06
AD		 1277 case e1000_82576:
1278 test = reg_test_82576;
317f66bd 1279 toggle = 0x7FFFF3FF;
2d064c06
AD		 1280 break;
1281 default:
1282 test = reg_test_82575;
317f66bd 1283 toggle = 0x7FFFF3FF;
2d064c06
AD		 1284 break;
1285 }
9d5c8243
AK		 1286
1287 /* Because the status register is such a special case,
1288 * we handle it separately from the rest of the register
1289 * tests. Some bits are read-only, some toggle, and some
1290 * are writable on newer MACs.
1291 */
1292 before = rd32(E1000_STATUS);
1293 value = (rd32(E1000_STATUS) & toggle);
1294 wr32(E1000_STATUS, toggle);
1295 after = rd32(E1000_STATUS) & toggle;
1296 if (value != after) {
d836200a
JJ		 1297 dev_err(&adapter->pdev->dev,
1298 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1299 after, value);
9d5c8243
AK		 1300 *data = 1;
1301 return 1;
1302 }
1303 /* restore previous status */
1304 wr32(E1000_STATUS, before);
1305
1306 /* Perform the remainder of the register test, looping through
1307 * the test table until we either fail or reach the null entry.
1308 */
1309 while (test->reg) {
1310 for (i = 0; i < test->array_len; i++) {
1311 switch (test->test_type) {
1312 case PATTERN_TEST:
2753f4ce
AD		 1313 REG_PATTERN_TEST(test->reg +
1314 (i * test->reg_offset),
9d5c8243
AK		 1315 test->mask,
1316 test->write);
1317 break;
1318 case SET_READ_TEST:
2753f4ce
AD		 1319 REG_SET_AND_CHECK(test->reg +
1320 (i * test->reg_offset),
9d5c8243
AK		 1321 test->mask,
1322 test->write);
1323 break;
1324 case WRITE_NO_TEST:
1325 writel(test->write,
1326 (adapter->hw.hw_addr + test->reg)
2d064c06 1327 + (i * test->reg_offset));
9d5c8243
AK		 1328 break;
1329 case TABLE32_TEST:
1330 REG_PATTERN_TEST(test->reg + (i * 4),
1331 test->mask,
1332 test->write);
1333 break;
1334 case TABLE64_TEST_LO:
1335 REG_PATTERN_TEST(test->reg + (i * 8),
1336 test->mask,
1337 test->write);
1338 break;
1339 case TABLE64_TEST_HI:
1340 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1341 test->mask,
1342 test->write);
1343 break;
1344 }
1345 }
1346 test++;
1347 }
1348
1349 *data = 0;
1350 return 0;
1351}
1352
1353static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1354{
53b87ce3
CW		 1355 struct e1000_hw *hw = &adapter->hw;
1356
9d5c8243 1357 *data = 0;
9d5c8243 1358
53b87ce3
CW		 1359 /* Validate eeprom on all parts but flashless */
1360 switch (hw->mac.type) {
1361 case e1000_i210:
1362 case e1000_i211:
1363 if (igb_get_flash_presence_i210(hw)) {
1364 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1365 *data = 2;
1366 }
1367 break;
1368 default:
f96a8a0b
CW		 1369 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1370 *data = 2;
53b87ce3 1371 break;
f96a8a0b 1372 }
9d5c8243
AK		 1373
1374 return *data;
1375}
1376
1377static irqreturn_t igb_test_intr(int irq, void *data)
1378{
317f66bd 1379 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1380 struct e1000_hw *hw = &adapter->hw;
1381
1382 adapter->test_icr |= rd32(E1000_ICR);
1383
1384 return IRQ_HANDLED;
1385}
1386
1387static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1388{
1389 struct e1000_hw *hw = &adapter->hw;
1390 struct net_device *netdev = adapter->netdev;
2753f4ce 1391 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1392 u32 irq = adapter->pdev->irq;
1393
1394 *data = 0;
1395
1396 /* Hook up test interrupt handler just for this test */
cd14ef54 1397 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4eefa8f0 1398 if (request_irq(adapter->msix_entries[0].vector,
9005df38 1399 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1400 *data = 1;
1401 return -1;
1402 }
4eefa8f0 1403 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1404 shared_int = false;
4eefa8f0 1405 if (request_irq(irq,
9005df38 1406 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1407 *data = 1;
1408 return -1;
1409 }
a0607fd3 1410 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1411 netdev->name, adapter)) {
9d5c8243 1412 shared_int = false;
a0607fd3 1413 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1414 netdev->name, adapter)) {
9d5c8243
AK		 1415 *data = 1;
1416 return -1;
1417 }
1418 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1419 (shared_int ? "shared" : "unshared"));
317f66bd 1420
9d5c8243 1421 /* Disable all the interrupts */
4eefa8f0 1422 wr32(E1000_IMC, ~0);
945a5151 1423 wrfl();
0d451e79 1424 usleep_range(10000, 11000);
9d5c8243 1425
2753f4ce 1426 /* Define all writable bits for ICS */
4eefa8f0 1427 switch (hw->mac.type) {
2753f4ce
AD		 1428 case e1000_82575:
1429 ics_mask = 0x37F47EDD;
1430 break;
1431 case e1000_82576:
1432 ics_mask = 0x77D4FBFD;
1433 break;
55cac248
AD		 1434 case e1000_82580:
1435 ics_mask = 0x77DCFED5;
1436 break;
d2ba2ed8 1437 case e1000_i350:
ceb5f13b 1438 case e1000_i354:
f96a8a0b
CW		 1439 case e1000_i210:
1440 case e1000_i211:
d2ba2ed8
AD		 1441 ics_mask = 0x77DCFED5;
1442 break;
2753f4ce
AD		 1443 default:
1444 ics_mask = 0x7FFFFFFF;
1445 break;
1446 }
1447
9d5c8243 1448 /* Test each interrupt */
2753f4ce 1449 for (; i < 31; i++) {
9d5c8243 1450 /* Interrupt to test */
a51d8c21 1451 mask = BIT(i);
9d5c8243 1452
2753f4ce
AD		 1453 if (!(mask & ics_mask))
1454 continue;
1455
9d5c8243
AK		 1456 if (!shared_int) {
1457 /* Disable the interrupt to be reported in
1458 * the cause register and then force the same
1459 * interrupt and see if one gets posted. If
1460 * an interrupt was posted to the bus, the
1461 * test failed.
1462 */
1463 adapter->test_icr = 0;
2753f4ce
AD		 1464
1465 /* Flush any pending interrupts */
1466 wr32(E1000_ICR, ~0);
1467
1468 wr32(E1000_IMC, mask);
1469 wr32(E1000_ICS, mask);
945a5151 1470 wrfl();
0d451e79 1471 usleep_range(10000, 11000);
9d5c8243
AK		 1472
1473 if (adapter->test_icr & mask) {
1474 *data = 3;
1475 break;
1476 }
1477 }
1478
1479 /* Enable the interrupt to be reported in
1480 * the cause register and then force the same
1481 * interrupt and see if one gets posted. If
1482 * an interrupt was not posted to the bus, the
1483 * test failed.
1484 */
1485 adapter->test_icr = 0;
2753f4ce
AD		 1486
1487 /* Flush any pending interrupts */
1488 wr32(E1000_ICR, ~0);
1489
9d5c8243
AK		 1490 wr32(E1000_IMS, mask);
1491 wr32(E1000_ICS, mask);
945a5151 1492 wrfl();
0d451e79 1493 usleep_range(10000, 11000);
9d5c8243
AK		 1494
1495 if (!(adapter->test_icr & mask)) {
1496 *data = 4;
1497 break;
1498 }
1499
1500 if (!shared_int) {
1501 /* Disable the other interrupts to be reported in
1502 * the cause register and then force the other
1503 * interrupts and see if any get posted. If
1504 * an interrupt was posted to the bus, the
1505 * test failed.
1506 */
1507 adapter->test_icr = 0;
2753f4ce
AD		 1508
1509 /* Flush any pending interrupts */
1510 wr32(E1000_ICR, ~0);
1511
1512 wr32(E1000_IMC, ~mask);
1513 wr32(E1000_ICS, ~mask);
945a5151 1514 wrfl();
0d451e79 1515 usleep_range(10000, 11000);
9d5c8243 1516
2753f4ce 1517 if (adapter->test_icr & mask) {
9d5c8243
AK		 1518 *data = 5;
1519 break;
1520 }
1521 }
1522 }
1523
1524 /* Disable all the interrupts */
2753f4ce 1525 wr32(E1000_IMC, ~0);
945a5151 1526 wrfl();
0d451e79 1527 usleep_range(10000, 11000);
9d5c8243
AK		 1528
1529 /* Unhook test interrupt handler */
cd14ef54 1530 if (adapter->flags & IGB_FLAG_HAS_MSIX)
4eefa8f0
AD		 1531 free_irq(adapter->msix_entries[0].vector, adapter);
1532 else
1533 free_irq(irq, adapter);
9d5c8243
AK		 1534
1535 return *data;
1536}
1537
1538static void igb_free_desc_rings(struct igb_adapter *adapter)
1539{
d7ee5b3a
AD		 1540 igb_free_tx_resources(&adapter->test_tx_ring);
1541 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1542}
1543
1544static int igb_setup_desc_rings(struct igb_adapter *adapter)
1545{
9d5c8243
AK		 1546 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1547 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1548 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1549 int ret_val;
9d5c8243
AK		 1550
1551 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1552 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1553 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1554 tx_ring->netdev = adapter->netdev;
1555 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1556
d7ee5b3a 1557 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1558 ret_val = 1;
1559 goto err_nomem;
1560 }
1561
d7ee5b3a
AD		 1562 igb_setup_tctl(adapter);
1563 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1564
9d5c8243 1565 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1566 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1567 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1568 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1569 rx_ring->reg_idx = adapter->vfs_allocated_count;
1570
1571 if (igb_setup_rx_resources(rx_ring)) {
1572 ret_val = 3;
9d5c8243
AK		 1573 goto err_nomem;
1574 }
9d5c8243 1575
d7ee5b3a
AD		 1576 /* set the default queue to queue 0 of PF */
1577 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1578
d7ee5b3a
AD		 1579 /* enable receive ring */
1580 igb_setup_rctl(adapter);
1581 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1582
cd392f5c 1583 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1584
1585 return 0;
1586
1587err_nomem:
1588 igb_free_desc_rings(adapter);
1589 return ret_val;
1590}
1591
1592static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1593{
1594 struct e1000_hw *hw = &adapter->hw;
1595
1596 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1597 igb_write_phy_reg(hw, 29, 0x001F);
1598 igb_write_phy_reg(hw, 30, 0x8FFC);
1599 igb_write_phy_reg(hw, 29, 0x001A);
1600 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1601}
1602
1603static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1604{
1605 struct e1000_hw *hw = &adapter->hw;
1606 u32 ctrl_reg = 0;
9d5c8243
AK		 1607
1608 hw->mac.autoneg = false;
1609
8aa23f0d
CW		 1610 if (hw->phy.type == e1000_phy_m88) {
1611 if (hw->phy.id != I210_I_PHY_ID) {
1612 /* Auto-MDI/MDIX Off */
1613 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1614 /* reset to update Auto-MDI/MDIX */
1615 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1616 /* autoneg off */
1617 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1618 } else {
1619 /* force 1000, set loopback */
1620 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1621 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1622 }
5aa3a449
TF		 1623 } else if (hw->phy.type == e1000_phy_82580) {
1624 /* enable MII loopback */
1625 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1626 }
1627
119b0e03
SA		 1628 /* add small delay to avoid loopback test failure */
1629 msleep(50);
1630
9d5c8243 1631 /* force 1000, set loopback */
f5f4cf08 1632 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1633
1634 /* Now set up the MAC to the same speed/duplex as the PHY. */
1635 ctrl_reg = rd32(E1000_CTRL);
1636 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1637 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1638 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1639 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1640 E1000_CTRL_FD | /* Force Duplex to FULL */
1641 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1642
8aa23f0d 1643 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1644 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1645
1646 wr32(E1000_CTRL, ctrl_reg);
1647
1648 /* Disable the receiver on the PHY so when a cable is plugged in, the
1649 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1650 */
8aa23f0d 1651 if (hw->phy.type == e1000_phy_m88)
9d5c8243
AK		 1652 igb_phy_disable_receiver(adapter);
1653
8aa23f0d 1654 mdelay(500);
9d5c8243
AK		 1655 return 0;
1656}
1657
1658static int igb_set_phy_loopback(struct igb_adapter *adapter)
1659{
1660 return igb_integrated_phy_loopback(adapter);
1661}
1662
1663static int igb_setup_loopback_test(struct igb_adapter *adapter)
1664{
1665 struct e1000_hw *hw = &adapter->hw;
2d064c06 1666 u32 reg;
9d5c8243 1667
317f66bd
AD		 1668 reg = rd32(E1000_CTRL_EXT);
1669
1670 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1671 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1672 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1673 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1674 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
a4e979a2 1675 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
3cfcf036
TF		 1676 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1677 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
a14bc2bb
RH		 1678 /* Enable DH89xxCC MPHY for near end loopback */
1679 reg = rd32(E1000_MPHY_ADDR_CTL);
1680 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1681 E1000_MPHY_PCS_CLK_REG_OFFSET;
1682 wr32(E1000_MPHY_ADDR_CTL, reg);
1683
1684 reg = rd32(E1000_MPHY_DATA);
1685 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1686 wr32(E1000_MPHY_DATA, reg);
1687 }
1688
2d064c06
AD		 1689 reg = rd32(E1000_RCTL);
1690 reg |= E1000_RCTL_LBM_TCVR;
1691 wr32(E1000_RCTL, reg);
1692
1693 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1694
1695 reg = rd32(E1000_CTRL);
1696 reg &= ~(E1000_CTRL_RFCE |
1697 E1000_CTRL_TFCE |
1698 E1000_CTRL_LRST);
1699 reg |= E1000_CTRL_SLU |
2753f4ce 1700 E1000_CTRL_FD;
2d064c06
AD		 1701 wr32(E1000_CTRL, reg);
1702
1703 /* Unset switch control to serdes energy detect */
1704 reg = rd32(E1000_CONNSW);
1705 reg &= ~E1000_CONNSW_ENRGSRC;
1706 wr32(E1000_CONNSW, reg);
1707
3860a0bf 1708 /* Unset sigdetect for SERDES loopback on
0ba96d3d 1709 * 82580 and newer devices.
3860a0bf 1710 */
0ba96d3d 1711 if (hw->mac.type >= e1000_82580) {
3860a0bf
CW		 1712 reg = rd32(E1000_PCS_CFG0);
1713 reg |= E1000_PCS_CFG_IGN_SD;
1714 wr32(E1000_PCS_CFG0, reg);
3860a0bf
CW		 1715 }
1716
2d064c06
AD		 1717 /* Set PCS register for forced speed */
1718 reg = rd32(E1000_PCS_LCTL);
1719 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1720 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1721 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1722 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1723 E1000_PCS_LCTL_FSD | /* Force Speed */
1724 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1725 wr32(E1000_PCS_LCTL, reg);
1726
9d5c8243 1727 return 0;
9d5c8243
AK		 1728 }
1729
317f66bd 1730 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1731}
1732
1733static void igb_loopback_cleanup(struct igb_adapter *adapter)
1734{
1735 struct e1000_hw *hw = &adapter->hw;
1736 u32 rctl;
1737 u16 phy_reg;
1738
a14bc2bb
RH		 1739 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1740 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1741 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
a4e979a2
FT		 1742 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1743 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
a14bc2bb
RH		 1744 u32 reg;
1745
1746 /* Disable near end loopback on DH89xxCC */
1747 reg = rd32(E1000_MPHY_ADDR_CTL);
1748 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1749 E1000_MPHY_PCS_CLK_REG_OFFSET;
1750 wr32(E1000_MPHY_ADDR_CTL, reg);
1751
1752 reg = rd32(E1000_MPHY_DATA);
1753 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1754 wr32(E1000_MPHY_DATA, reg);
1755 }
1756
9d5c8243
AK		 1757 rctl = rd32(E1000_RCTL);
1758 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1759 wr32(E1000_RCTL, rctl);
1760
1761 hw->mac.autoneg = true;
f5f4cf08 1762 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1763 if (phy_reg & MII_CR_LOOPBACK) {
1764 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1765 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1766 igb_phy_sw_reset(hw);
1767 }
1768}
1769
1770static void igb_create_lbtest_frame(struct sk_buff *skb,
1771 unsigned int frame_size)
1772{
1773 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1774 frame_size /= 2;
1775 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1776 memset(&skb->data[frame_size + 10], 0xBE, 1);
1777 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1778}
1779
1a1c225b
AD		 1780static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1781 unsigned int frame_size)
9d5c8243 1782{
1a1c225b
AD		 1783 unsigned char *data;
1784 bool match = true;
1785
1786 frame_size >>= 1;
1787
cbc8e55f 1788 data = kmap(rx_buffer->page);
1a1c225b
AD		 1789
1790 if (data[3] != 0xFF ||
1791 data[frame_size + 10] != 0xBE ||
1792 data[frame_size + 12] != 0xAF)
1793 match = false;
1794
1795 kunmap(rx_buffer->page);
1796
1797 return match;
9d5c8243
AK		 1798}
1799
ad93d17e 1800static int igb_clean_test_rings(struct igb_ring *rx_ring,
b980ac18
JK		 1801 struct igb_ring *tx_ring,
1802 unsigned int size)
ad93d17e
AD		 1803{
1804 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1805 struct igb_rx_buffer *rx_buffer_info;
1806 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1807 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1808
1809 /* initialize next to clean and descriptor values */
1810 rx_ntc = rx_ring->next_to_clean;
1811 tx_ntc = tx_ring->next_to_clean;
60136906 1812 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1813
3ceb90fd 1814 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
b980ac18 1815 /* check Rx buffer */
06034649 1816 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e 1817
cbc8e55f
AD		 1818 /* sync Rx buffer for CPU read */
1819 dma_sync_single_for_cpu(rx_ring->dev,
1820 rx_buffer_info->dma,
de78d1f9 1821 IGB_RX_BUFSZ,
cbc8e55f 1822 DMA_FROM_DEVICE);
ad93d17e
AD		 1823
1824 /* verify contents of skb */
1a1c225b 1825 if (igb_check_lbtest_frame(rx_buffer_info, size))
ad93d17e
AD		 1826 count++;
1827
cbc8e55f
AD		 1828 /* sync Rx buffer for device write */
1829 dma_sync_single_for_device(rx_ring->dev,
1830 rx_buffer_info->dma,
de78d1f9 1831 IGB_RX_BUFSZ,
cbc8e55f
AD		 1832 DMA_FROM_DEVICE);
1833
b980ac18 1834 /* unmap buffer on Tx side */
06034649
AD		 1835 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1836 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e 1837
b980ac18 1838 /* increment Rx/Tx next to clean counters */
ad93d17e
AD		 1839 rx_ntc++;
1840 if (rx_ntc == rx_ring->count)
1841 rx_ntc = 0;
1842 tx_ntc++;
1843 if (tx_ntc == tx_ring->count)
1844 tx_ntc = 0;
1845
1846 /* fetch next descriptor */
60136906 1847 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1848 }
1849
cbc8e55f 1850 netdev_tx_reset_queue(txring_txq(tx_ring));
51a76c30 1851
ad93d17e 1852 /* re-map buffers to ring, store next to clean values */
cd392f5c 1853 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1854 rx_ring->next_to_clean = rx_ntc;
1855 tx_ring->next_to_clean = tx_ntc;
1856
1857 return count;
1858}
1859
9d5c8243
AK		 1860static int igb_run_loopback_test(struct igb_adapter *adapter)
1861{
9d5c8243
AK		 1862 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1863 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1864 u16 i, j, lc, good_cnt;
1865 int ret_val = 0;
44390ca6 1866 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1867 netdev_tx_t tx_ret_val;
1868 struct sk_buff *skb;
1869
1870 /* allocate test skb */
1871 skb = alloc_skb(size, GFP_KERNEL);
1872 if (!skb)
1873 return 11;
9d5c8243 1874
ad93d17e
AD		 1875 /* place data into test skb */
1876 igb_create_lbtest_frame(skb, size);
1877 skb_put(skb, size);
9d5c8243 1878
b980ac18 1879 /* Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1880 * The idea is to wrap the largest ring a number of times using 64
1881 * send/receive pairs during each loop
1882 */
1883
1884 if (rx_ring->count <= tx_ring->count)
1885 lc = ((tx_ring->count / 64) * 2) + 1;
1886 else
1887 lc = ((rx_ring->count / 64) * 2) + 1;
1888
9d5c8243 1889 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1890 /* reset count of good packets */
9d5c8243 1891 good_cnt = 0;
ad93d17e
AD		 1892
1893 /* place 64 packets on the transmit queue*/
1894 for (i = 0; i < 64; i++) {
1895 skb_get(skb);
cd392f5c 1896 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1897 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1898 good_cnt++;
ad93d17e
AD		 1899 }
1900
9d5c8243 1901 if (good_cnt != 64) {
ad93d17e 1902 ret_val = 12;
9d5c8243
AK		 1903 break;
1904 }
ad93d17e 1905
b980ac18 1906 /* allow 200 milliseconds for packets to go from Tx to Rx */
ad93d17e
AD		 1907 msleep(200);
1908
1909 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1910 if (good_cnt != 64) {
1911 ret_val = 13;
9d5c8243
AK		 1912 break;
1913 }
1914 } /* end loop count loop */
ad93d17e
AD		 1915
1916 /* free the original skb */
1917 kfree_skb(skb);
1918
9d5c8243
AK		 1919 return ret_val;
1920}
1921
1922static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1923{
1924 /* PHY loopback cannot be performed if SoL/IDER
b980ac18
JK		 1925 * sessions are active
1926 */
9d5c8243
AK		 1927 if (igb_check_reset_block(&adapter->hw)) {
1928 dev_err(&adapter->pdev->dev,
d836200a 1929 "Cannot do PHY loopback test when SoL/IDER is active.\n");
f96a8a0b
CW		 1930 *data = 0;
1931 goto out;
1932 }
ceb5f13b
CW		 1933
1934 if (adapter->hw.mac.type == e1000_i354) {
1935 dev_info(&adapter->pdev->dev,
1936 "Loopback test not supported on i354.\n");
1937 *data = 0;
1938 goto out;
1939 }
9d5c8243
AK		 1940 *data = igb_setup_desc_rings(adapter);
1941 if (*data)
1942 goto out;
1943 *data = igb_setup_loopback_test(adapter);
1944 if (*data)
1945 goto err_loopback;
1946 *data = igb_run_loopback_test(adapter);
1947 igb_loopback_cleanup(adapter);
1948
1949err_loopback:
1950 igb_free_desc_rings(adapter);
1951out:
1952 return *data;
1953}
1954
1955static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1956{
1957 struct e1000_hw *hw = &adapter->hw;
1958 *data = 0;
1959 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1960 int i = 0;
9005df38 1961
9d5c8243
AK		 1962 hw->mac.serdes_has_link = false;
1963
1964 /* On some blade server designs, link establishment
b980ac18
JK		 1965 * could take as long as 2-3 minutes
1966 */
9d5c8243
AK		 1967 do {
1968 hw->mac.ops.check_for_link(&adapter->hw);
1969 if (hw->mac.serdes_has_link)
1970 return *data;
1971 msleep(20);
1972 } while (i++ < 3750);
1973
1974 *data = 1;
1975 } else {
1976 hw->mac.ops.check_for_link(&adapter->hw);
1977 if (hw->mac.autoneg)
4507dc9f 1978 msleep(5000);
9d5c8243 1979
317f66bd 1980 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1981 *data = 1;
1982 }
1983 return *data;
1984}
1985
1986static void igb_diag_test(struct net_device *netdev,
1987 struct ethtool_test *eth_test, u64 *data)
1988{
1989 struct igb_adapter *adapter = netdev_priv(netdev);
1990 u16 autoneg_advertised;
1991 u8 forced_speed_duplex, autoneg;
1992 bool if_running = netif_running(netdev);
1993
1994 set_bit(__IGB_TESTING, &adapter->state);
56cec249
CW		 1995
1996 /* can't do offline tests on media switching devices */
1997 if (adapter->hw.dev_spec._82575.mas_capable)
1998 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
9d5c8243
AK		 1999 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2000 /* Offline tests */
2001
2002 /* save speed, duplex, autoneg settings */
2003 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
2004 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
2005 autoneg = adapter->hw.mac.autoneg;
2006
2007 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2008
88a268c1
NN		 2009 /* power up link for link test */
2010 igb_power_up_link(adapter);
2011
9d5c8243 2012 /* Link test performed before hardware reset so autoneg doesn't
b980ac18
JK		 2013 * interfere with test result
2014 */
d602de05 2015 if (igb_link_test(adapter, &data[TEST_LINK]))
9d5c8243
AK		 2016 eth_test->flags |= ETH_TEST_FL_FAILED;
2017
2018 if (if_running)
2019 /* indicate we're in test mode */
46eafa59 2020 igb_close(netdev);
9d5c8243
AK		 2021 else
2022 igb_reset(adapter);
2023
d602de05 2024 if (igb_reg_test(adapter, &data[TEST_REG]))
9d5c8243
AK		 2025 eth_test->flags |= ETH_TEST_FL_FAILED;
2026
2027 igb_reset(adapter);
d602de05 2028 if (igb_eeprom_test(adapter, &data[TEST_EEP]))
9d5c8243
AK		 2029 eth_test->flags |= ETH_TEST_FL_FAILED;
2030
2031 igb_reset(adapter);
d602de05 2032 if (igb_intr_test(adapter, &data[TEST_IRQ]))
9d5c8243
AK		 2033 eth_test->flags |= ETH_TEST_FL_FAILED;
2034
2035 igb_reset(adapter);
88a268c1
NN		 2036 /* power up link for loopback test */
2037 igb_power_up_link(adapter);
d602de05 2038 if (igb_loopback_test(adapter, &data[TEST_LOOP]))
9d5c8243
AK		 2039 eth_test->flags |= ETH_TEST_FL_FAILED;
2040
2041 /* restore speed, duplex, autoneg settings */
2042 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2043 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2044 adapter->hw.mac.autoneg = autoneg;
2045
2046 /* force this routine to wait until autoneg complete/timeout */
2047 adapter->hw.phy.autoneg_wait_to_complete = true;
2048 igb_reset(adapter);
2049 adapter->hw.phy.autoneg_wait_to_complete = false;
2050
2051 clear_bit(__IGB_TESTING, &adapter->state);
2052 if (if_running)
46eafa59 2053 igb_open(netdev);
9d5c8243
AK		 2054 } else {
2055 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 2056
2057 /* PHY is powered down when interface is down */
d602de05 2058 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))
8d420a1b
AD		 2059 eth_test->flags |= ETH_TEST_FL_FAILED;
2060 else
d602de05 2061 data[TEST_LINK] = 0;
9d5c8243
AK		 2062
2063 /* Online tests aren't run; pass by default */
d602de05
JS		 2064 data[TEST_REG] = 0;
2065 data[TEST_EEP] = 0;
2066 data[TEST_IRQ] = 0;
2067 data[TEST_LOOP] = 0;
9d5c8243
AK		 2068
2069 clear_bit(__IGB_TESTING, &adapter->state);
2070 }
2071 msleep_interruptible(4 * 1000);
2072}
2073
9d5c8243
AK		 2074static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2075{
2076 struct igb_adapter *adapter = netdev_priv(netdev);
2077
9d5c8243
AK		 2078 wol->wolopts = 0;
2079
63d4a8f9 2080 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2081 return;
2082
42ce4126
AA		 2083 wol->supported = WAKE_UCAST | WAKE_MCAST |
2084 WAKE_BCAST | WAKE_MAGIC |
2085 WAKE_PHY;
2086
9d5c8243
AK		 2087 /* apply any specific unsupported masks here */
2088 switch (adapter->hw.device_id) {
2089 default:
2090 break;
2091 }
2092
2093 if (adapter->wol & E1000_WUFC_EX)
2094 wol->wolopts |= WAKE_UCAST;
2095 if (adapter->wol & E1000_WUFC_MC)
2096 wol->wolopts |= WAKE_MCAST;
2097 if (adapter->wol & E1000_WUFC_BC)
2098 wol->wolopts |= WAKE_BCAST;
2099 if (adapter->wol & E1000_WUFC_MAG)
2100 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 2101 if (adapter->wol & E1000_WUFC_LNKC)
2102 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 2103}
2104
2105static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2106{
2107 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 2108
22939f06 2109 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 2110 return -EOPNOTSUPP;
2111
63d4a8f9 2112 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2113 return wol->wolopts ? -EOPNOTSUPP : 0;
2114
9d5c8243
AK		 2115 /* these settings will always override what we currently have */
2116 adapter->wol = 0;
2117
2118 if (wol->wolopts & WAKE_UCAST)
2119 adapter->wol |= E1000_WUFC_EX;
2120 if (wol->wolopts & WAKE_MCAST)
2121 adapter->wol |= E1000_WUFC_MC;
2122 if (wol->wolopts & WAKE_BCAST)
2123 adapter->wol |= E1000_WUFC_BC;
2124 if (wol->wolopts & WAKE_MAGIC)
2125 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 2126 if (wol->wolopts & WAKE_PHY)
2127 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 2128 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2129
9d5c8243
AK		 2130 return 0;
2131}
2132
9d5c8243
AK		 2133/* bit defines for adapter->led_status */
2134#define IGB_LED_ON 0
2135
936db355
JK		 2136static int igb_set_phys_id(struct net_device *netdev,
2137 enum ethtool_phys_id_state state)
9d5c8243
AK		 2138{
2139 struct igb_adapter *adapter = netdev_priv(netdev);
2140 struct e1000_hw *hw = &adapter->hw;
2141
936db355
JK		 2142 switch (state) {
2143 case ETHTOOL_ID_ACTIVE:
2144 igb_blink_led(hw);
2145 return 2;
2146 case ETHTOOL_ID_ON:
2147 igb_blink_led(hw);
2148 break;
2149 case ETHTOOL_ID_OFF:
2150 igb_led_off(hw);
2151 break;
2152 case ETHTOOL_ID_INACTIVE:
2153 igb_led_off(hw);
2154 clear_bit(IGB_LED_ON, &adapter->led_status);
2155 igb_cleanup_led(hw);
2156 break;
2157 }
9d5c8243
AK		 2158
2159 return 0;
2160}
2161
2162static int igb_set_coalesce(struct net_device *netdev,
2163 struct ethtool_coalesce *ec)
2164{
2165 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 2166 int i;
9d5c8243 2167
0c5bbeb8
TF		 2168 if (ec->rx_max_coalesced_frames ||
2169 ec->rx_coalesce_usecs_irq ||
2170 ec->rx_max_coalesced_frames_irq ||
2171 ec->tx_max_coalesced_frames ||
2172 ec->tx_coalesce_usecs_irq ||
2173 ec->stats_block_coalesce_usecs ||
2174 ec->use_adaptive_rx_coalesce ||
2175 ec->use_adaptive_tx_coalesce ||
2176 ec->pkt_rate_low ||
2177 ec->rx_coalesce_usecs_low ||
2178 ec->rx_max_coalesced_frames_low ||
2179 ec->tx_coalesce_usecs_low ||
2180 ec->tx_max_coalesced_frames_low ||
2181 ec->pkt_rate_high ||
2182 ec->rx_coalesce_usecs_high ||
2183 ec->rx_max_coalesced_frames_high ||
2184 ec->tx_coalesce_usecs_high ||
2185 ec->tx_max_coalesced_frames_high ||
2186 ec->rate_sample_interval)
2187 return -ENOTSUPP;
2188
9d5c8243
AK		 2189 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2190 ((ec->rx_coalesce_usecs > 3) &&
2191 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2192 (ec->rx_coalesce_usecs == 2))
2193 return -EINVAL;
2194
4fc82adf
AD		 2195 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2196 ((ec->tx_coalesce_usecs > 3) &&
2197 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2198 (ec->tx_coalesce_usecs == 2))
2199 return -EINVAL;
2200
2201 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2202 return -EINVAL;
2203
831ec0b4
CW		 2204 /* If ITR is disabled, disable DMAC */
2205 if (ec->rx_coalesce_usecs == 0) {
2206 if (adapter->flags & IGB_FLAG_DMAC)
2207 adapter->flags &= ~IGB_FLAG_DMAC;
2208 }
2209
9d5c8243 2210 /* convert to rate of irq's per second */
4fc82adf
AD		 2211 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2212 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2213 else
2214 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2215
2216 /* convert to rate of irq's per second */
2217 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2218 adapter->tx_itr_setting = adapter->rx_itr_setting;
2219 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2220 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2221 else
2222 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2223
047e0030
AD		 2224 for (i = 0; i < adapter->num_q_vectors; i++) {
2225 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2226 q_vector->tx.work_limit = adapter->tx_work_limit;
2227 if (q_vector->rx.ring)
4fc82adf
AD		 2228 q_vector->itr_val = adapter->rx_itr_setting;
2229 else
2230 q_vector->itr_val = adapter->tx_itr_setting;
2231 if (q_vector->itr_val && q_vector->itr_val <= 3)
2232 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2233 q_vector->set_itr = 1;
2234 }
9d5c8243
AK		 2235
2236 return 0;
2237}
2238
2239static int igb_get_coalesce(struct net_device *netdev,
2240 struct ethtool_coalesce *ec)
2241{
2242 struct igb_adapter *adapter = netdev_priv(netdev);
2243
4fc82adf
AD		 2244 if (adapter->rx_itr_setting <= 3)
2245 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2246 else
4fc82adf
AD		 2247 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2248
2249 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2250 if (adapter->tx_itr_setting <= 3)
2251 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2252 else
2253 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2254 }
9d5c8243
AK		 2255
2256 return 0;
2257}
2258
9d5c8243
AK		 2259static int igb_nway_reset(struct net_device *netdev)
2260{
2261 struct igb_adapter *adapter = netdev_priv(netdev);
2262 if (netif_running(netdev))
2263 igb_reinit_locked(adapter);
2264 return 0;
2265}
2266
2267static int igb_get_sset_count(struct net_device *netdev, int sset)
2268{
2269 switch (sset) {
2270 case ETH_SS_STATS:
2271 return IGB_STATS_LEN;
2272 case ETH_SS_TEST:
2273 return IGB_TEST_LEN;
2274 default:
2275 return -ENOTSUPP;
2276 }
2277}
2278
2279static void igb_get_ethtool_stats(struct net_device *netdev,
2280 struct ethtool_stats *stats, u64 *data)
2281{
2282 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2283 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2284 unsigned int start;
2285 struct igb_ring *ring;
2286 int i, j;
128e45eb 2287 char *p;
9d5c8243 2288
12dcd86b
ED		 2289 spin_lock(&adapter->stats64_lock);
2290 igb_update_stats(adapter, net_stats);
317f66bd 2291
9d5c8243 2292 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2293 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2294 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2295 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2296 }
128e45eb
AD		 2297 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2298 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2299 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2300 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2301 }
e21ed353 2302 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2303 u64 restart2;
2304
2305 ring = adapter->tx_ring[j];
2306 do {
57a7744e 2307 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 2308 data[i] = ring->tx_stats.packets;
2309 data[i+1] = ring->tx_stats.bytes;
2310 data[i+2] = ring->tx_stats.restart_queue;
57a7744e 2311 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b 2312 do {
57a7744e 2313 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
12dcd86b 2314 restart2 = ring->tx_stats.restart_queue2;
57a7744e 2315 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
12dcd86b
ED		 2316 data[i+2] += restart2;
2317
2318 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2319 }
9d5c8243 2320 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2321 ring = adapter->rx_ring[j];
2322 do {
57a7744e 2323 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 2324 data[i] = ring->rx_stats.packets;
2325 data[i+1] = ring->rx_stats.bytes;
2326 data[i+2] = ring->rx_stats.drops;
2327 data[i+3] = ring->rx_stats.csum_err;
2328 data[i+4] = ring->rx_stats.alloc_failed;
57a7744e 2329 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b 2330 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2331 }
12dcd86b 2332 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2333}
2334
2335static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2336{
2337 struct igb_adapter *adapter = netdev_priv(netdev);
2338 u8 *p = data;
2339 int i;
2340
2341 switch (stringset) {
2342 case ETH_SS_TEST:
2343 memcpy(data, *igb_gstrings_test,
2344 IGB_TEST_LEN*ETH_GSTRING_LEN);
2345 break;
2346 case ETH_SS_STATS:
2347 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2348 memcpy(p, igb_gstrings_stats[i].stat_string,
2349 ETH_GSTRING_LEN);
2350 p += ETH_GSTRING_LEN;
2351 }
128e45eb
AD		 2352 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2353 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2354 ETH_GSTRING_LEN);
2355 p += ETH_GSTRING_LEN;
2356 }
9d5c8243
AK		 2357 for (i = 0; i < adapter->num_tx_queues; i++) {
2358 sprintf(p, "tx_queue_%u_packets", i);
2359 p += ETH_GSTRING_LEN;
2360 sprintf(p, "tx_queue_%u_bytes", i);
2361 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2362 sprintf(p, "tx_queue_%u_restart", i);
2363 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2364 }
2365 for (i = 0; i < adapter->num_rx_queues; i++) {
2366 sprintf(p, "rx_queue_%u_packets", i);
2367 p += ETH_GSTRING_LEN;
2368 sprintf(p, "rx_queue_%u_bytes", i);
2369 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2370 sprintf(p, "rx_queue_%u_drops", i);
2371 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2372 sprintf(p, "rx_queue_%u_csum_err", i);
2373 p += ETH_GSTRING_LEN;
2374 sprintf(p, "rx_queue_%u_alloc_failed", i);
2375 p += ETH_GSTRING_LEN;
9d5c8243 2376 }
b980ac18 2377 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
9d5c8243
AK		 2378 break;
2379 }
2380}
2381
a79f4f88 2382static int igb_get_ts_info(struct net_device *dev,
a9188028 2383 struct ethtool_ts_info *info)
cb41145e
CW		 2384{
2385 struct igb_adapter *adapter = netdev_priv(dev);
2386
0f49da0e
KI		 2387 if (adapter->ptp_clock)
2388 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2389 else
2390 info->phc_index = -1;
2391
a9188028 2392 switch (adapter->hw.mac.type) {
b66e2397
MV		 2393 case e1000_82575:
2394 info->so_timestamping =
2395 SOF_TIMESTAMPING_TX_SOFTWARE |
2396 SOF_TIMESTAMPING_RX_SOFTWARE |
2397 SOF_TIMESTAMPING_SOFTWARE;
2398 return 0;
a9188028
MV		 2399 case e1000_82576:
2400 case e1000_82580:
2401 case e1000_i350:
ceb5f13b 2402 case e1000_i354:
a9188028
MV		 2403 case e1000_i210:
2404 case e1000_i211:
2405 info->so_timestamping =
b66e2397
MV		 2406 SOF_TIMESTAMPING_TX_SOFTWARE |
2407 SOF_TIMESTAMPING_RX_SOFTWARE |
2408 SOF_TIMESTAMPING_SOFTWARE |
a9188028
MV		 2409 SOF_TIMESTAMPING_TX_HARDWARE |
2410 SOF_TIMESTAMPING_RX_HARDWARE |
2411 SOF_TIMESTAMPING_RAW_HARDWARE;
cb41145e 2412
a9188028 2413 info->tx_types =
a51d8c21
JK		 2414 BIT(HWTSTAMP_TX_OFF) |
2415 BIT(HWTSTAMP_TX_ON);
cb41145e 2416
a51d8c21 2417 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
cb41145e 2418
a9188028
MV		 2419 /* 82576 does not support timestamping all packets. */
2420 if (adapter->hw.mac.type >= e1000_82580)
a51d8c21 2421 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
a9188028
MV		 2422 else
2423 info->rx_filters |=
a51d8c21
JK		 2424 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2425 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2426 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
a9188028
MV		 2427
2428 return 0;
a9188028
MV		 2429 default:
2430 return -EOPNOTSUPP;
2431 }
2432}
cb41145e 2433
64c75d41 2434#define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
0e71def2
GH		 2435static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,
2436 struct ethtool_rxnfc *cmd)
2437{
2438 struct ethtool_rx_flow_spec *fsp = &cmd->fs;
2439 struct igb_nfc_filter *rule = NULL;
2440
2441 /* report total rule count */
2442 cmd->data = IGB_MAX_RXNFC_FILTERS;
2443
2444 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2445 if (fsp->location <= rule->sw_idx)
2446 break;
2447 }
2448
2449 if (!rule || fsp->location != rule->sw_idx)
2450 return -EINVAL;
2451
7a277a96 2452 if (rule->filter.match_flags) {
64c75d41
GH		 2453 fsp->flow_type = ETHER_FLOW;
2454 fsp->ring_cookie = rule->action;
7a277a96
GH		 2455 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2456 fsp->h_u.ether_spec.h_proto = rule->filter.etype;
2457 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;
2458 }
2459 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {
2460 fsp->flow_type |= FLOW_EXT;
2461 fsp->h_ext.vlan_tci = rule->filter.vlan_tci;
2462 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);
2463 }
64c75d41
GH		 2464 return 0;
2465 }
0e71def2
GH		 2466 return -EINVAL;
2467}
2468
2469static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,
2470 struct ethtool_rxnfc *cmd,
2471 u32 *rule_locs)
2472{
2473 struct igb_nfc_filter *rule;
2474 int cnt = 0;
2475
2476 /* report total rule count */
2477 cmd->data = IGB_MAX_RXNFC_FILTERS;
2478
2479 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2480 if (cnt == cmd->rule_cnt)
2481 return -EMSGSIZE;
2482 rule_locs[cnt] = rule->sw_idx;
2483 cnt++;
2484 }
2485
2486 cmd->rule_cnt = cnt;
2487
2488 return 0;
2489}
2490
039454a8
AA		 2491static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2492 struct ethtool_rxnfc *cmd)
2493{
2494 cmd->data = 0;
2495
2496 /* Report default options for RSS on igb */
2497 switch (cmd->flow_type) {
2498 case TCP_V4_FLOW:
2499 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2500 /* Fall through */
039454a8
AA		 2501 case UDP_V4_FLOW:
2502 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2503 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2504 /* Fall through */
039454a8
AA		 2505 case SCTP_V4_FLOW:
2506 case AH_ESP_V4_FLOW:
2507 case AH_V4_FLOW:
2508 case ESP_V4_FLOW:
2509 case IPV4_FLOW:
2510 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2511 break;
2512 case TCP_V6_FLOW:
2513 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2514 /* Fall through */
039454a8
AA		 2515 case UDP_V6_FLOW:
2516 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2517 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
b26141d4 2518 /* Fall through */
039454a8
AA		 2519 case SCTP_V6_FLOW:
2520 case AH_ESP_V6_FLOW:
2521 case AH_V6_FLOW:
2522 case ESP_V6_FLOW:
2523 case IPV6_FLOW:
2524 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2525 break;
2526 default:
2527 return -EINVAL;
2528 }
2529
2530 return 0;
2531}
2532
2533static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
b980ac18 2534 u32 *rule_locs)
039454a8
AA		 2535{
2536 struct igb_adapter *adapter = netdev_priv(dev);
2537 int ret = -EOPNOTSUPP;
2538
2539 switch (cmd->cmd) {
2540 case ETHTOOL_GRXRINGS:
2541 cmd->data = adapter->num_rx_queues;
2542 ret = 0;
2543 break;
0e71def2
GH		 2544 case ETHTOOL_GRXCLSRLCNT:
2545 cmd->rule_cnt = adapter->nfc_filter_count;
2546 ret = 0;
2547 break;
2548 case ETHTOOL_GRXCLSRULE:
2549 ret = igb_get_ethtool_nfc_entry(adapter, cmd);
2550 break;
2551 case ETHTOOL_GRXCLSRLALL:
2552 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);
2553 break;
039454a8
AA		 2554 case ETHTOOL_GRXFH:
2555 ret = igb_get_rss_hash_opts(adapter, cmd);
2556 break;
2557 default:
2558 break;
2559 }
2560
2561 return ret;
2562}
2563
2564#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2565 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2566static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2567 struct ethtool_rxnfc *nfc)
2568{
2569 u32 flags = adapter->flags;
2570
2571 /* RSS does not support anything other than hashing
2572 * to queues on src and dst IPs and ports
2573 */
2574 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2575 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2576 return -EINVAL;
2577
2578 switch (nfc->flow_type) {
2579 case TCP_V4_FLOW:
2580 case TCP_V6_FLOW:
2581 if (!(nfc->data & RXH_IP_SRC) ||
2582 !(nfc->data & RXH_IP_DST) ||
2583 !(nfc->data & RXH_L4_B_0_1) ||
2584 !(nfc->data & RXH_L4_B_2_3))
2585 return -EINVAL;
2586 break;
2587 case UDP_V4_FLOW:
2588 if (!(nfc->data & RXH_IP_SRC) ||
2589 !(nfc->data & RXH_IP_DST))
2590 return -EINVAL;
2591 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2592 case 0:
2593 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2594 break;
2595 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2596 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2597 break;
2598 default:
2599 return -EINVAL;
2600 }
2601 break;
2602 case UDP_V6_FLOW:
2603 if (!(nfc->data & RXH_IP_SRC) ||
2604 !(nfc->data & RXH_IP_DST))
2605 return -EINVAL;
2606 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2607 case 0:
2608 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2609 break;
2610 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2611 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2612 break;
2613 default:
2614 return -EINVAL;
2615 }
2616 break;
2617 case AH_ESP_V4_FLOW:
2618 case AH_V4_FLOW:
2619 case ESP_V4_FLOW:
2620 case SCTP_V4_FLOW:
2621 case AH_ESP_V6_FLOW:
2622 case AH_V6_FLOW:
2623 case ESP_V6_FLOW:
2624 case SCTP_V6_FLOW:
2625 if (!(nfc->data & RXH_IP_SRC) ||
2626 !(nfc->data & RXH_IP_DST) ||
2627 (nfc->data & RXH_L4_B_0_1) ||
2628 (nfc->data & RXH_L4_B_2_3))
2629 return -EINVAL;
2630 break;
2631 default:
2632 return -EINVAL;
2633 }
2634
2635 /* if we changed something we need to update flags */
2636 if (flags != adapter->flags) {
2637 struct e1000_hw *hw = &adapter->hw;
2638 u32 mrqc = rd32(E1000_MRQC);
2639
2640 if ((flags & UDP_RSS_FLAGS) &&
2641 !(adapter->flags & UDP_RSS_FLAGS))
2642 dev_err(&adapter->pdev->dev,
2643 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2644
2645 adapter->flags = flags;
2646
2647 /* Perform hash on these packet types */
2648 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2649 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2650 E1000_MRQC_RSS_FIELD_IPV6 |
2651 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2652
2653 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2654 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2655
2656 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2657 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2658
2659 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2660 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2661
2662 wr32(E1000_MRQC, mrqc);
2663 }
2664
2665 return 0;
2666}
2667
64c75d41
GH		 2668static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,
2669 struct igb_nfc_filter *input)
2670{
2671 struct e1000_hw *hw = &adapter->hw;
2672 u8 i;
2673 u32 etqf;
2674 u16 etype;
2675
2676 /* find an empty etype filter register */
2677 for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
2678 if (!adapter->etype_bitmap[i])
2679 break;
2680 }
2681 if (i == MAX_ETYPE_FILTER) {
2682 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");
2683 return -EINVAL;
2684 }
2685
2686 adapter->etype_bitmap[i] = true;
2687
2688 etqf = rd32(E1000_ETQF(i));
2689 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
2690
2691 etqf |= E1000_ETQF_FILTER_ENABLE;
2692 etqf &= ~E1000_ETQF_ETYPE_MASK;
2693 etqf |= (etype & E1000_ETQF_ETYPE_MASK);
2694
2695 etqf &= ~E1000_ETQF_QUEUE_MASK;
2696 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT)
2697 & E1000_ETQF_QUEUE_MASK);
2698 etqf |= E1000_ETQF_QUEUE_ENABLE;
2699
2700 wr32(E1000_ETQF(i), etqf);
2701
2702 input->etype_reg_index = i;
2703
2704 return 0;
2705}
2706
7a277a96
GH		 2707int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,
2708 struct igb_nfc_filter *input)
2709{
2710 struct e1000_hw *hw = &adapter->hw;
2711 u8 vlan_priority;
2712 u16 queue_index;
2713 u32 vlapqf;
2714
2715 vlapqf = rd32(E1000_VLAPQF);
2716 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
2717 >> VLAN_PRIO_SHIFT;
2718 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;
2719
2720 /* check whether this vlan prio is already set */
2721 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&
2722 (queue_index != input->action)) {
2723 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");
2724 return -EEXIST;
2725 }
2726
2727 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);
2728 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
2729
2730 wr32(E1000_VLAPQF, vlapqf);
2731
2732 return 0;
2733}
2734
0e71def2
GH		 2735int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2736{
64c75d41
GH		 2737 int err = -EINVAL;
2738
7a277a96 2739 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
64c75d41 2740 err = igb_rxnfc_write_etype_filter(adapter, input);
7a277a96
GH		 2741 if (err)
2742 return err;
2743 }
2744
2745 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2746 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);
64c75d41
GH		 2747
2748 return err;
2749}
2750
2751static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,
2752 u16 reg_index)
2753{
2754 struct e1000_hw *hw = &adapter->hw;
2755 u32 etqf = rd32(E1000_ETQF(reg_index));
2756
2757 etqf &= ~E1000_ETQF_QUEUE_ENABLE;
2758 etqf &= ~E1000_ETQF_QUEUE_MASK;
2759 etqf &= ~E1000_ETQF_FILTER_ENABLE;
2760
2761 wr32(E1000_ETQF(reg_index), etqf);
2762
2763 adapter->etype_bitmap[reg_index] = false;
0e71def2
GH		 2764}
2765
7a277a96
GH		 2766static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,
2767 u16 vlan_tci)
2768{
2769 struct e1000_hw *hw = &adapter->hw;
2770 u8 vlan_priority;
2771 u32 vlapqf;
2772
2773 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
2774
2775 vlapqf = rd32(E1000_VLAPQF);
2776 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);
2777 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,
2778 E1000_VLAPQF_QUEUE_MASK);
2779
2780 wr32(E1000_VLAPQF, vlapqf);
2781}
2782
0e71def2
GH		 2783int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2784{
64c75d41
GH		 2785 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)
2786 igb_clear_etype_filter_regs(adapter,
2787 input->etype_reg_index);
7a277a96
GH		 2788
2789 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2790 igb_clear_vlan_prio_filter(adapter,
2791 ntohs(input->filter.vlan_tci));
2792
0e71def2
GH		 2793 return 0;
2794}
2795
2796static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,
2797 struct igb_nfc_filter *input,
2798 u16 sw_idx)
2799{
2800 struct igb_nfc_filter *rule, *parent;
2801 int err = -EINVAL;
2802
2803 parent = NULL;
2804 rule = NULL;
2805
2806 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2807 /* hash found, or no matching entry */
2808 if (rule->sw_idx >= sw_idx)
2809 break;
2810 parent = rule;
2811 }
2812
2813 /* if there is an old rule occupying our place remove it */
2814 if (rule && (rule->sw_idx == sw_idx)) {
2815 if (!input)
2816 err = igb_erase_filter(adapter, rule);
2817
2818 hlist_del(&rule->nfc_node);
2819 kfree(rule);
2820 adapter->nfc_filter_count--;
2821 }
2822
2823 /* If no input this was a delete, err should be 0 if a rule was
2824 * successfully found and removed from the list else -EINVAL
2825 */
2826 if (!input)
2827 return err;
2828
2829 /* initialize node */
2830 INIT_HLIST_NODE(&input->nfc_node);
2831
2832 /* add filter to the list */
2833 if (parent)
2834 hlist_add_behind(&parent->nfc_node, &input->nfc_node);
2835 else
2836 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);
2837
2838 /* update counts */
2839 adapter->nfc_filter_count++;
2840
2841 return 0;
2842}
2843
2844static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,
2845 struct ethtool_rxnfc *cmd)
2846{
2847 struct net_device *netdev = adapter->netdev;
2848 struct ethtool_rx_flow_spec *fsp =
2849 (struct ethtool_rx_flow_spec *)&cmd->fs;
2850 struct igb_nfc_filter *input, *rule;
2851 int err = 0;
2852
2853 if (!(netdev->hw_features & NETIF_F_NTUPLE))
54be8132 2854 return -EOPNOTSUPP;
0e71def2
GH		 2855
2856 /* Don't allow programming if the action is a queue greater than
2857 * the number of online Rx queues.
2858 */
2859 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||
2860 (fsp->ring_cookie >= adapter->num_rx_queues)) {
2861 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");
2862 return -EINVAL;
2863 }
2864
2865 /* Don't allow indexes to exist outside of available space */
2866 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {
2867 dev_err(&adapter->pdev->dev, "Location out of range\n");
2868 return -EINVAL;
2869 }
2870
2871 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)
2872 return -EINVAL;
2873
7a277a96
GH		 2874 if (fsp->m_u.ether_spec.h_proto != ETHER_TYPE_FULL_MASK &&
2875 fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK))
64c75d41
GH		 2876 return -EINVAL;
2877
0e71def2
GH		 2878 input = kzalloc(sizeof(*input), GFP_KERNEL);
2879 if (!input)
2880 return -ENOMEM;
2881
7a277a96
GH		 2882 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {
2883 input->filter.etype = fsp->h_u.ether_spec.h_proto;
2884 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;
2885 }
2886
2887 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
2888 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
2889 err = -EINVAL;
2890 goto err_out;
2891 }
2892 input->filter.vlan_tci = fsp->h_ext.vlan_tci;
2893 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2894 }
2895
0e71def2
GH		 2896 input->action = fsp->ring_cookie;
2897 input->sw_idx = fsp->location;
2898
2899 spin_lock(&adapter->nfc_lock);
2900
2901 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2902 if (!memcmp(&input->filter, &rule->filter,
2903 sizeof(input->filter))) {
2904 err = -EEXIST;
2905 dev_err(&adapter->pdev->dev,
2906 "ethtool: this filter is already set\n");
2907 goto err_out_w_lock;
2908 }
2909 }
2910
2911 err = igb_add_filter(adapter, input);
2912 if (err)
2913 goto err_out_w_lock;
2914
2915 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);
2916
2917 spin_unlock(&adapter->nfc_lock);
2918 return 0;
2919
2920err_out_w_lock:
2921 spin_unlock(&adapter->nfc_lock);
7a277a96 2922err_out:
0e71def2
GH		 2923 kfree(input);
2924 return err;
2925}
2926
2927static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,
2928 struct ethtool_rxnfc *cmd)
2929{
2930 struct ethtool_rx_flow_spec *fsp =
2931 (struct ethtool_rx_flow_spec *)&cmd->fs;
2932 int err;
2933
2934 spin_lock(&adapter->nfc_lock);
2935 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);
2936 spin_unlock(&adapter->nfc_lock);
2937
2938 return err;
2939}
2940
039454a8
AA		 2941static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2942{
2943 struct igb_adapter *adapter = netdev_priv(dev);
2944 int ret = -EOPNOTSUPP;
2945
2946 switch (cmd->cmd) {
2947 case ETHTOOL_SRXFH:
2948 ret = igb_set_rss_hash_opt(adapter, cmd);
2949 break;
0e71def2
GH		 2950 case ETHTOOL_SRXCLSRLINS:
2951 ret = igb_add_ethtool_nfc_entry(adapter, cmd);
2952 break;
2953 case ETHTOOL_SRXCLSRLDEL:
2954 ret = igb_del_ethtool_nfc_entry(adapter, cmd);
039454a8
AA		 2955 default:
2956 break;
2957 }
2958
2959 return ret;
2960}
2961
24a372cd
AA		 2962static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2963{
2964 struct igb_adapter *adapter = netdev_priv(netdev);
2965 struct e1000_hw *hw = &adapter->hw;
f4c01e96 2966 u32 ret_val;
87371b9d 2967 u16 phy_data;
24a372cd
AA		 2968
2969 if ((hw->mac.type < e1000_i350) ||
2970 (hw->phy.media_type != e1000_media_type_copper))
2971 return -EOPNOTSUPP;
2972
2973 edata->supported = (SUPPORTED_1000baseT_Full |
2974 SUPPORTED_100baseT_Full);
f4c01e96
CW		 2975 if (!hw->dev_spec._82575.eee_disable)
2976 edata->advertised =
2977 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
24a372cd 2978
f4c01e96
CW		 2979 /* The IPCNFG and EEER registers are not supported on I354. */
2980 if (hw->mac.type == e1000_i354) {
2981 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
2982 } else {
2983 u32 eeer;
2984
2985 eeer = rd32(E1000_EEER);
24a372cd 2986
f4c01e96
CW		 2987 /* EEE status on negotiated link */
2988 if (eeer & E1000_EEER_EEE_NEG)
2989 edata->eee_active = true;
24a372cd 2990
f4c01e96
CW		 2991 if (eeer & E1000_EEER_TX_LPI_EN)
2992 edata->tx_lpi_enabled = true;
2993 }
24a372cd 2994
87371b9d
MV		 2995 /* EEE Link Partner Advertised */
2996 switch (hw->mac.type) {
2997 case e1000_i350:
2998 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2999 &phy_data);
3000 if (ret_val)
3001 return -ENODATA;
3002
3003 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
87371b9d 3004 break;
f4c01e96 3005 case e1000_i354:
87371b9d
MV		 3006 case e1000_i210:
3007 case e1000_i211:
3008 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
3009 E1000_EEE_LP_ADV_DEV_I210,
3010 &phy_data);
3011 if (ret_val)
3012 return -ENODATA;
3013
3014 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3015
3016 break;
3017 default:
3018 break;
3019 }
3020
24a372cd
AA		 3021 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
3022
f4c01e96
CW		 3023 if ((hw->mac.type == e1000_i354) &&
3024 (edata->eee_enabled))
24a372cd
AA		 3025 edata->tx_lpi_enabled = true;
3026
3027 /* Report correct negotiated EEE status for devices that
3028 * wrongly report EEE at half-duplex
3029 */
3030 if (adapter->link_duplex == HALF_DUPLEX) {
3031 edata->eee_enabled = false;
3032 edata->eee_active = false;
3033 edata->tx_lpi_enabled = false;
3034 edata->advertised &= ~edata->advertised;
3035 }
3036
3037 return 0;
3038}
3039
3040static int igb_set_eee(struct net_device *netdev,
3041 struct ethtool_eee *edata)
3042{
3043 struct igb_adapter *adapter = netdev_priv(netdev);
3044 struct e1000_hw *hw = &adapter->hw;
3045 struct ethtool_eee eee_curr;
c4c112f1 3046 bool adv1g_eee = true, adv100m_eee = true;
24a372cd
AA		 3047 s32 ret_val;
3048
3049 if ((hw->mac.type < e1000_i350) ||
3050 (hw->phy.media_type != e1000_media_type_copper))
3051 return -EOPNOTSUPP;
3052
58e4e1f6
AK		 3053 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
3054
24a372cd
AA		 3055 ret_val = igb_get_eee(netdev, &eee_curr);
3056 if (ret_val)
3057 return ret_val;
3058
3059 if (eee_curr.eee_enabled) {
3060 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
3061 dev_err(&adapter->pdev->dev,
3062 "Setting EEE tx-lpi is not supported\n");
3063 return -EINVAL;
3064 }
3065
3066 /* Tx LPI timer is not implemented currently */
3067 if (edata->tx_lpi_timer) {
3068 dev_err(&adapter->pdev->dev,
3069 "Setting EEE Tx LPI timer is not supported\n");
3070 return -EINVAL;
3071 }
3072
c4c112f1
TF		 3073 if (!edata->advertised || (edata->advertised &
3074 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
24a372cd 3075 dev_err(&adapter->pdev->dev,
c4c112f1 3076 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
24a372cd
AA		 3077 return -EINVAL;
3078 }
c4c112f1
TF		 3079 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
3080 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
24a372cd
AA		 3081
3082 } else if (!edata->eee_enabled) {
3083 dev_err(&adapter->pdev->dev,
3084 "Setting EEE options are not supported with EEE disabled\n");
3085 return -EINVAL;
3086 }
3087
f4c01e96 3088 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
24a372cd
AA		 3089 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
3090 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
f4c01e96 3091 adapter->flags |= IGB_FLAG_EEE;
24a372cd
AA		 3092
3093 /* reset link */
8a650aa2
AA		 3094 if (netif_running(netdev))
3095 igb_reinit_locked(adapter);
3096 else
24a372cd
AA		 3097 igb_reset(adapter);
3098 }
3099
c4c112f1
TF		 3100 if (hw->mac.type == e1000_i354)
3101 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
3102 else
3103 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
3104
3105 if (ret_val) {
3106 dev_err(&adapter->pdev->dev,
3107 "Problem setting EEE advertisement options\n");
3108 return -EINVAL;
3109 }
3110
24a372cd
AA		 3111 return 0;
3112}
3113
f69aa390
AA		 3114static int igb_get_module_info(struct net_device *netdev,
3115 struct ethtool_modinfo *modinfo)
3116{
3117 struct igb_adapter *adapter = netdev_priv(netdev);
3118 struct e1000_hw *hw = &adapter->hw;
23d87824 3119 u32 status = 0;
f69aa390
AA		 3120 u16 sff8472_rev, addr_mode;
3121 bool page_swap = false;
3122
3123 if ((hw->phy.media_type == e1000_media_type_copper) ||
3124 (hw->phy.media_type == e1000_media_type_unknown))
3125 return -EOPNOTSUPP;
3126
3127 /* Check whether we support SFF-8472 or not */
3128 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
23d87824 3129 if (status)
f69aa390
AA		 3130 return -EIO;
3131
3132 /* addressing mode is not supported */
3133 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
23d87824 3134 if (status)
f69aa390
AA		 3135 return -EIO;
3136
3137 /* addressing mode is not supported */
3138 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
3139 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3140 page_swap = true;
3141 }
3142
3143 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
3144 /* We have an SFP, but it does not support SFF-8472 */
3145 modinfo->type = ETH_MODULE_SFF_8079;
3146 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3147 } else {
3148 /* We have an SFP which supports a revision of SFF-8472 */
3149 modinfo->type = ETH_MODULE_SFF_8472;
3150 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3151 }
3152
3153 return 0;
3154}
3155
3156static int igb_get_module_eeprom(struct net_device *netdev,
3157 struct ethtool_eeprom *ee, u8 *data)
3158{
3159 struct igb_adapter *adapter = netdev_priv(netdev);
3160 struct e1000_hw *hw = &adapter->hw;
23d87824 3161 u32 status = 0;
f69aa390
AA		 3162 u16 *dataword;
3163 u16 first_word, last_word;
3164 int i = 0;
3165
3166 if (ee->len == 0)
3167 return -EINVAL;
3168
3169 first_word = ee->offset >> 1;
3170 last_word = (ee->offset + ee->len - 1) >> 1;
3171
3172 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
3173 GFP_KERNEL);
3174 if (!dataword)
3175 return -ENOMEM;
3176
3177 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
3178 for (i = 0; i < last_word - first_word + 1; i++) {
efea95d4
DS		 3179 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,
3180 &dataword[i]);
23d87824 3181 if (status) {
f69aa390 3182 /* Error occurred while reading module */
db41b87d 3183 kfree(dataword);
f69aa390 3184 return -EIO;
db41b87d 3185 }
f69aa390
AA		 3186
3187 be16_to_cpus(&dataword[i]);
3188 }
3189
3190 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
3191 kfree(dataword);
3192
3193 return 0;
3194}
3195
a79f4f88
MV		 3196static int igb_ethtool_begin(struct net_device *netdev)
3197{
3198 struct igb_adapter *adapter = netdev_priv(netdev);
3199 pm_runtime_get_sync(&adapter->pdev->dev);
3200 return 0;
3201}
3202
3203static void igb_ethtool_complete(struct net_device *netdev)
3204{
3205 struct igb_adapter *adapter = netdev_priv(netdev);
3206 pm_runtime_put(&adapter->pdev->dev);
3207}
3208
ed12cc9a
LMV		 3209static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
3210{
3211 return IGB_RETA_SIZE;
3212}
3213
892311f6
EP		 3214static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3215 u8 *hfunc)
ed12cc9a
LMV		 3216{
3217 struct igb_adapter *adapter = netdev_priv(netdev);
3218 int i;
3219
892311f6
EP		 3220 if (hfunc)
3221 *hfunc = ETH_RSS_HASH_TOP;
3222 if (!indir)
3223 return 0;
ed12cc9a
LMV		 3224 for (i = 0; i < IGB_RETA_SIZE; i++)
3225 indir[i] = adapter->rss_indir_tbl[i];
3226
3227 return 0;
3228}
3229
3230void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
3231{
3232 struct e1000_hw *hw = &adapter->hw;
3233 u32 reg = E1000_RETA(0);
3234 u32 shift = 0;
3235 int i = 0;
3236
3237 switch (hw->mac.type) {
3238 case e1000_82575:
3239 shift = 6;
3240 break;
3241 case e1000_82576:
3242 /* 82576 supports 2 RSS queues for SR-IOV */
3243 if (adapter->vfs_allocated_count)
3244 shift = 3;
3245 break;
3246 default:
3247 break;
3248 }
3249
3250 while (i < IGB_RETA_SIZE) {
3251 u32 val = 0;
3252 int j;
3253
3254 for (j = 3; j >= 0; j--) {
3255 val <<= 8;
3256 val |= adapter->rss_indir_tbl[i + j];
3257 }
3258
3259 wr32(reg, val << shift);
3260 reg += 4;
3261 i += 4;
3262 }
3263}
3264
fe62d001 3265static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
892311f6 3266 const u8 *key, const u8 hfunc)
ed12cc9a
LMV		 3267{
3268 struct igb_adapter *adapter = netdev_priv(netdev);
3269 struct e1000_hw *hw = &adapter->hw;
3270 int i;
3271 u32 num_queues;
3272
892311f6
EP		 3273 /* We do not allow change in unsupported parameters */
3274 if (key ||
3275 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3276 return -EOPNOTSUPP;
3277 if (!indir)
3278 return 0;
3279
ed12cc9a
LMV		 3280 num_queues = adapter->rss_queues;
3281
3282 switch (hw->mac.type) {
3283 case e1000_82576:
3284 /* 82576 supports 2 RSS queues for SR-IOV */
3285 if (adapter->vfs_allocated_count)
3286 num_queues = 2;
3287 break;
3288 default:
3289 break;
3290 }
3291
3292 /* Verify user input. */
3293 for (i = 0; i < IGB_RETA_SIZE; i++)
3294 if (indir[i] >= num_queues)
3295 return -EINVAL;
3296
3297
3298 for (i = 0; i < IGB_RETA_SIZE; i++)
3299 adapter->rss_indir_tbl[i] = indir[i];
3300
3301 igb_write_rss_indir_tbl(adapter);
3302
3303 return 0;
3304}
3305
907b7835
LMV		 3306static unsigned int igb_max_channels(struct igb_adapter *adapter)
3307{
3308 struct e1000_hw *hw = &adapter->hw;
3309 unsigned int max_combined = 0;
3310
3311 switch (hw->mac.type) {
3312 case e1000_i211:
3313 max_combined = IGB_MAX_RX_QUEUES_I211;
3314 break;
3315 case e1000_82575:
3316 case e1000_i210:
3317 max_combined = IGB_MAX_RX_QUEUES_82575;
3318 break;
3319 case e1000_i350:
3320 if (!!adapter->vfs_allocated_count) {
3321 max_combined = 1;
3322 break;
3323 }
3324 /* fall through */
3325 case e1000_82576:
3326 if (!!adapter->vfs_allocated_count) {
3327 max_combined = 2;
3328 break;
3329 }
3330 /* fall through */
3331 case e1000_82580:
3332 case e1000_i354:
3333 default:
3334 max_combined = IGB_MAX_RX_QUEUES;
3335 break;
3336 }
3337
3338 return max_combined;
3339}
3340
3341static void igb_get_channels(struct net_device *netdev,
3342 struct ethtool_channels *ch)
3343{
3344 struct igb_adapter *adapter = netdev_priv(netdev);
3345
3346 /* Report maximum channels */
3347 ch->max_combined = igb_max_channels(adapter);
3348
3349 /* Report info for other vector */
cd14ef54 3350 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
907b7835
LMV		 3351 ch->max_other = NON_Q_VECTORS;
3352 ch->other_count = NON_Q_VECTORS;
3353 }
3354
3355 ch->combined_count = adapter->rss_queues;
3356}
3357
3358static int igb_set_channels(struct net_device *netdev,
3359 struct ethtool_channels *ch)
3360{
3361 struct igb_adapter *adapter = netdev_priv(netdev);
3362 unsigned int count = ch->combined_count;
72ddef05 3363 unsigned int max_combined = 0;
907b7835
LMV		 3364
3365 /* Verify they are not requesting separate vectors */
3366 if (!count || ch->rx_count || ch->tx_count)
3367 return -EINVAL;
3368
3369 /* Verify other_count is valid and has not been changed */
3370 if (ch->other_count != NON_Q_VECTORS)
3371 return -EINVAL;
3372
3373 /* Verify the number of channels doesn't exceed hw limits */
72ddef05
SS		 3374 max_combined = igb_max_channels(adapter);
3375 if (count > max_combined)
907b7835
LMV		 3376 return -EINVAL;
3377
3378 if (count != adapter->rss_queues) {
3379 adapter->rss_queues = count;
72ddef05 3380 igb_set_flag_queue_pairs(adapter, max_combined);
907b7835
LMV		 3381
3382 /* Hardware has to reinitialize queues and interrupts to
3383 * match the new configuration.
3384 */
3385 return igb_reinit_queues(adapter);
3386 }
3387
3388 return 0;
3389}
3390
0fc0b732 3391static const struct ethtool_ops igb_ethtool_ops = {
b980ac18
JK		 3392 .get_settings = igb_get_settings,
3393 .set_settings = igb_set_settings,
3394 .get_drvinfo = igb_get_drvinfo,
3395 .get_regs_len = igb_get_regs_len,
3396 .get_regs = igb_get_regs,
3397 .get_wol = igb_get_wol,
3398 .set_wol = igb_set_wol,
3399 .get_msglevel = igb_get_msglevel,
3400 .set_msglevel = igb_set_msglevel,
3401 .nway_reset = igb_nway_reset,
3402 .get_link = igb_get_link,
3403 .get_eeprom_len = igb_get_eeprom_len,
3404 .get_eeprom = igb_get_eeprom,
3405 .set_eeprom = igb_set_eeprom,
3406 .get_ringparam = igb_get_ringparam,
3407 .set_ringparam = igb_set_ringparam,
3408 .get_pauseparam = igb_get_pauseparam,
3409 .set_pauseparam = igb_set_pauseparam,
3410 .self_test = igb_diag_test,
3411 .get_strings = igb_get_strings,
3412 .set_phys_id = igb_set_phys_id,
3413 .get_sset_count = igb_get_sset_count,
3414 .get_ethtool_stats = igb_get_ethtool_stats,
3415 .get_coalesce = igb_get_coalesce,
3416 .set_coalesce = igb_set_coalesce,
3417 .get_ts_info = igb_get_ts_info,
039454a8
AA		 3418 .get_rxnfc = igb_get_rxnfc,
3419 .set_rxnfc = igb_set_rxnfc,
24a372cd
AA		 3420 .get_eee = igb_get_eee,
3421 .set_eee = igb_set_eee,
f69aa390
AA		 3422 .get_module_info = igb_get_module_info,
3423 .get_module_eeprom = igb_get_module_eeprom,
ed12cc9a 3424 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
fe62d001
BH		 3425 .get_rxfh = igb_get_rxfh,
3426 .set_rxfh = igb_set_rxfh,
907b7835
LMV		 3427 .get_channels = igb_get_channels,
3428 .set_channels = igb_set_channels,
a79f4f88
MV		 3429 .begin = igb_ethtool_begin,
3430 .complete = igb_ethtool_complete,
9d5c8243
AK		 3431};
3432
3433void igb_set_ethtool_ops(struct net_device *netdev)
3434{
7ad24ea4 3435 netdev->ethtool_ops = &igb_ethtool_ops;
9d5c8243 3436}
Linux kernel - Deliverables
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