Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
37689010 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #ifndef _IXGBE_H_ | |
30 | #define _IXGBE_H_ | |
31 | ||
f62bbb5e | 32 | #include <linux/bitops.h> |
9a799d71 AK |
33 | #include <linux/types.h> |
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
b25ebfd2 | 36 | #include <linux/cpumask.h> |
6fabd715 | 37 | #include <linux/aer.h> |
f62bbb5e | 38 | #include <linux/if_vlan.h> |
6cb562d6 | 39 | #include <linux/jiffies.h> |
9a799d71 | 40 | |
74d23cc7 | 41 | #include <linux/timecounter.h> |
3a6a4eda JK |
42 | #include <linux/net_tstamp.h> |
43 | #include <linux/ptp_clock_kernel.h> | |
3a6a4eda | 44 | |
9a799d71 AK |
45 | #include "ixgbe_type.h" |
46 | #include "ixgbe_common.h" | |
2f90b865 | 47 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
48 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
49 | #define IXGBE_FCOE | |
50 | #include "ixgbe_fcoe.h" | |
51 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 52 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
53 | #include <linux/dca.h> |
54 | #endif | |
9a799d71 | 55 | |
076bb0c8 | 56 | #include <net/busy_poll.h> |
5a85e737 | 57 | |
e0d1095a | 58 | #ifdef CONFIG_NET_RX_BUSY_POLL |
b4640030 | 59 | #define BP_EXTENDED_STATS |
7e15b90f | 60 | #endif |
849c4542 ET |
61 | /* common prefix used by pr_<> macros */ |
62 | #undef pr_fmt | |
63 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
64 | |
65 | /* TX/RX descriptor defines */ | |
6bacb300 | 66 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 67 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
68 | #define IXGBE_MAX_TXD 4096 |
69 | #define IXGBE_MIN_TXD 64 | |
70 | ||
fb44519d | 71 | #if (PAGE_SIZE < 8192) |
6bacb300 | 72 | #define IXGBE_DEFAULT_RXD 512 |
fb44519d AB |
73 | #else |
74 | #define IXGBE_DEFAULT_RXD 128 | |
75 | #endif | |
9a799d71 AK |
76 | #define IXGBE_MAX_RXD 4096 |
77 | #define IXGBE_MIN_RXD 64 | |
78 | ||
5b7f000f DS |
79 | #define IXGBE_ETH_P_LLDP 0x88CC |
80 | ||
9a799d71 | 81 | /* flow control */ |
2b9ade93 | 82 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 83 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 84 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 85 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 86 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
87 | #define IXGBE_MIN_FCPAUSE 0 |
88 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
89 | ||
90 | /* Supported Rx Buffer Sizes */ | |
252562c2 | 91 | #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ |
09816fbe AD |
92 | #define IXGBE_RXBUFFER_2K 2048 |
93 | #define IXGBE_RXBUFFER_3K 3072 | |
94 | #define IXGBE_RXBUFFER_4K 4096 | |
919e78a6 | 95 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 96 | |
13958070 | 97 | /* |
252562c2 AD |
98 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we |
99 | * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, | |
100 | * this adds up to 448 bytes of extra data. | |
101 | * | |
102 | * Since netdev_alloc_skb now allocates a page fragment we can use a value | |
103 | * of 256 and the resultant skb will have a truesize of 960 or less. | |
13958070 | 104 | */ |
252562c2 | 105 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 |
9a799d71 | 106 | |
9a799d71 AK |
107 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
108 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
109 | ||
472148c3 AD |
110 | enum ixgbe_tx_flags { |
111 | /* cmd_type flags */ | |
112 | IXGBE_TX_FLAGS_HW_VLAN = 0x01, | |
113 | IXGBE_TX_FLAGS_TSO = 0x02, | |
114 | IXGBE_TX_FLAGS_TSTAMP = 0x04, | |
115 | ||
116 | /* olinfo flags */ | |
117 | IXGBE_TX_FLAGS_CC = 0x08, | |
118 | IXGBE_TX_FLAGS_IPV4 = 0x10, | |
119 | IXGBE_TX_FLAGS_CSUM = 0x20, | |
120 | ||
121 | /* software defined flags */ | |
122 | IXGBE_TX_FLAGS_SW_VLAN = 0x40, | |
123 | IXGBE_TX_FLAGS_FCOE = 0x80, | |
124 | }; | |
125 | ||
126 | /* VLAN info */ | |
9a799d71 | 127 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
128 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
129 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
130 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
131 | ||
7f870475 GR |
132 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
133 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
134 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
135 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 136 | #define IXGBE_MAX_PF_MACVLANS 15 |
1d9c0bfd | 137 | #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) |
83c61fa9 GR |
138 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
139 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
140 | |
141 | struct vf_data_storage { | |
988d1307 | 142 | struct pci_dev *vfdev; |
7f870475 GR |
143 | unsigned char vf_mac_addresses[ETH_ALEN]; |
144 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
145 | u16 num_vf_mc_hashes; | |
7f870475 | 146 | bool clear_to_send; |
7f01648a | 147 | bool pf_set_mac; |
7f01648a GR |
148 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
149 | u16 pf_qos; | |
ff4ab206 | 150 | u16 tx_rate; |
de4c7f65 | 151 | u8 spoofchk_enabled; |
e65ce0d3 | 152 | bool rss_query_enabled; |
54011e4d | 153 | u8 trusted; |
8443c1a4 | 154 | int xcast_mode; |
374c65d6 | 155 | unsigned int vf_api; |
7f870475 GR |
156 | }; |
157 | ||
8443c1a4 HS |
158 | enum ixgbevf_xcast_modes { |
159 | IXGBEVF_XCAST_MODE_NONE = 0, | |
160 | IXGBEVF_XCAST_MODE_MULTI, | |
161 | IXGBEVF_XCAST_MODE_ALLMULTI, | |
162 | }; | |
163 | ||
a1cbb15c GR |
164 | struct vf_macvlans { |
165 | struct list_head l; | |
166 | int vf; | |
a1cbb15c GR |
167 | bool free; |
168 | bool is_macvlan; | |
169 | u8 vf_macvlan[ETH_ALEN]; | |
170 | }; | |
171 | ||
a535c30e | 172 | #define IXGBE_MAX_TXD_PWR 14 |
b4f47a48 | 173 | #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) |
a535c30e AD |
174 | |
175 | /* Tx Descriptors needed, worst case */ | |
176 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
990a3158 | 177 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
a535c30e | 178 | |
9a799d71 AK |
179 | /* wrapper around a pointer to a socket buffer, |
180 | * so a DMA handle can be stored along with the buffer */ | |
181 | struct ixgbe_tx_buffer { | |
d3d00239 | 182 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 183 | unsigned long time_stamp; |
fd0db0ed AD |
184 | struct sk_buff *skb; |
185 | unsigned int bytecount; | |
186 | unsigned short gso_segs; | |
244e27ad | 187 | __be16 protocol; |
729739b7 AD |
188 | DEFINE_DMA_UNMAP_ADDR(dma); |
189 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 190 | u32 tx_flags; |
9a799d71 AK |
191 | }; |
192 | ||
193 | struct ixgbe_rx_buffer { | |
194 | struct sk_buff *skb; | |
195 | dma_addr_t dma; | |
196 | struct page *page; | |
762f4c57 | 197 | unsigned int page_offset; |
9a799d71 AK |
198 | }; |
199 | ||
200 | struct ixgbe_queue_stats { | |
201 | u64 packets; | |
202 | u64 bytes; | |
b4640030 | 203 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
204 | u64 yields; |
205 | u64 misses; | |
206 | u64 cleaned; | |
b4640030 | 207 | #endif /* BP_EXTENDED_STATS */ |
9a799d71 AK |
208 | }; |
209 | ||
5b7da515 AD |
210 | struct ixgbe_tx_queue_stats { |
211 | u64 restart_queue; | |
212 | u64 tx_busy; | |
c84d324c | 213 | u64 tx_done_old; |
5b7da515 AD |
214 | }; |
215 | ||
216 | struct ixgbe_rx_queue_stats { | |
217 | u64 rsc_count; | |
218 | u64 rsc_flush; | |
219 | u64 non_eop_descs; | |
220 | u64 alloc_rx_page_failed; | |
221 | u64 alloc_rx_buff_failed; | |
8a0da21b | 222 | u64 csum_err; |
5b7da515 AD |
223 | }; |
224 | ||
a9763f3c MR |
225 | #define IXGBE_TS_HDR_LEN 8 |
226 | ||
f800326d | 227 | enum ixgbe_ring_state_t { |
7d637bcc | 228 | __IXGBE_TX_FDIR_INIT_DONE, |
fd786b7b | 229 | __IXGBE_TX_XPS_INIT_DONE, |
7d637bcc | 230 | __IXGBE_TX_DETECT_HANG, |
c84d324c | 231 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 232 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 233 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
57efd44c | 234 | __IXGBE_RX_FCOE, |
7d637bcc AD |
235 | }; |
236 | ||
2a47fa45 JF |
237 | struct ixgbe_fwd_adapter { |
238 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
239 | struct net_device *netdev; | |
240 | struct ixgbe_adapter *real_adapter; | |
241 | unsigned int tx_base_queue; | |
242 | unsigned int rx_base_queue; | |
243 | int pool; | |
244 | }; | |
245 | ||
7d637bcc AD |
246 | #define check_for_tx_hang(ring) \ |
247 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
248 | #define set_check_for_tx_hang(ring) \ | |
249 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
250 | #define clear_check_for_tx_hang(ring) \ | |
251 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
252 | #define ring_is_rsc_enabled(ring) \ | |
253 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
254 | #define set_ring_rsc_enabled(ring) \ | |
255 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
256 | #define clear_ring_rsc_enabled(ring) \ | |
257 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 258 | struct ixgbe_ring { |
efe3d3c8 | 259 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
d3ee4294 AD |
260 | struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ |
261 | struct net_device *netdev; /* netdev ring belongs to */ | |
262 | struct device *dev; /* device for DMA mapping */ | |
2a47fa45 | 263 | struct ixgbe_fwd_adapter *l2_accel_priv; |
9a799d71 | 264 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
265 | union { |
266 | struct ixgbe_tx_buffer *tx_buffer_info; | |
267 | struct ixgbe_rx_buffer *rx_buffer_info; | |
268 | }; | |
7d637bcc | 269 | unsigned long state; |
bd198058 | 270 | u8 __iomem *tail; |
d3ee4294 AD |
271 | dma_addr_t dma; /* phys. address of descriptor ring */ |
272 | unsigned int size; /* length in bytes */ | |
bd198058 | 273 | |
ae540af1 | 274 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
275 | |
276 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
277 | u8 reg_idx; /* holds the special value that gets |
278 | * the hardware register offset | |
279 | * associated with this ring, which is | |
280 | * different for DCB and RSS modes | |
281 | */ | |
d3ee4294 AD |
282 | u16 next_to_use; |
283 | u16 next_to_clean; | |
284 | ||
a9763f3c MR |
285 | unsigned long last_rx_timestamp; |
286 | ||
f800326d | 287 | union { |
d3ee4294 | 288 | u16 next_to_alloc; |
f800326d AD |
289 | struct { |
290 | u8 atr_sample_rate; | |
291 | u8 atr_count; | |
292 | }; | |
f800326d | 293 | }; |
9a799d71 | 294 | |
bd198058 | 295 | u8 dcb_tc; |
9a799d71 | 296 | struct ixgbe_queue_stats stats; |
de1036b1 | 297 | struct u64_stats_sync syncp; |
5b7da515 AD |
298 | union { |
299 | struct ixgbe_tx_queue_stats tx_stats; | |
300 | struct ixgbe_rx_queue_stats rx_stats; | |
301 | }; | |
7ca3bc58 | 302 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 303 | |
c7e4358a SN |
304 | enum ixgbe_ring_f_enum { |
305 | RING_F_NONE = 0, | |
7f870475 | 306 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 307 | RING_F_RSS, |
c4cf55e5 | 308 | RING_F_FDIR, |
0331a832 YZ |
309 | #ifdef IXGBE_FCOE |
310 | RING_F_FCOE, | |
311 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
312 | |
313 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
314 | }; | |
315 | ||
0f9b232b | 316 | #define IXGBE_MAX_RSS_INDICES 16 |
e9ee3238 | 317 | #define IXGBE_MAX_RSS_INDICES_X550 63 |
0f9b232b DS |
318 | #define IXGBE_MAX_VMDQ_INDICES 64 |
319 | #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ | |
320 | #define IXGBE_MAX_FCOE_INDICES 8 | |
321 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
322 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) | |
323 | #define IXGBE_MAX_L2A_QUEUES 4 | |
324 | #define IXGBE_BAD_L2A_QUEUE 3 | |
325 | #define IXGBE_MAX_MACVLANS 31 | |
326 | #define IXGBE_MAX_DCBMACVLANS 8 | |
2a47fa45 | 327 | |
021230d4 | 328 | struct ixgbe_ring_feature { |
c087663e AD |
329 | u16 limit; /* upper limit on feature indices */ |
330 | u16 indices; /* current value of indices */ | |
e4b317e9 AD |
331 | u16 mask; /* Mask used for feature to ring mapping */ |
332 | u16 offset; /* offset to start of feature */ | |
7ca3bc58 | 333 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 334 | |
73079ea0 AD |
335 | #define IXGBE_82599_VMDQ_8Q_MASK 0x78 |
336 | #define IXGBE_82599_VMDQ_4Q_MASK 0x7C | |
337 | #define IXGBE_82599_VMDQ_2Q_MASK 0x7E | |
338 | ||
f800326d AD |
339 | /* |
340 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
341 | * this is twice the size of a half page we need to double the page order | |
342 | * for FCoE enabled Rx queues. | |
343 | */ | |
09816fbe | 344 | static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) |
f800326d | 345 | { |
09816fbe AD |
346 | #ifdef IXGBE_FCOE |
347 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
348 | return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K : | |
349 | IXGBE_RXBUFFER_3K; | |
350 | #endif | |
351 | return IXGBE_RXBUFFER_2K; | |
f800326d | 352 | } |
09816fbe AD |
353 | |
354 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
355 | { | |
356 | #ifdef IXGBE_FCOE | |
357 | if (test_bit(__IXGBE_RX_FCOE, &ring->state)) | |
358 | return (PAGE_SIZE < 8192) ? 1 : 0; | |
f800326d | 359 | #endif |
09816fbe AD |
360 | return 0; |
361 | } | |
f800326d | 362 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) |
f800326d | 363 | |
08c8833b | 364 | struct ixgbe_ring_container { |
efe3d3c8 | 365 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
366 | unsigned int total_bytes; /* total bytes processed this int */ |
367 | unsigned int total_packets; /* total packets processed this int */ | |
368 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
369 | u8 count; /* total number of rings in vector */ |
370 | u8 itr; /* current ITR setting for ring */ | |
371 | }; | |
021230d4 | 372 | |
a557928e AD |
373 | /* iterator for handling rings in ring container */ |
374 | #define ixgbe_for_each_ring(pos, head) \ | |
375 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
376 | ||
2f90b865 | 377 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
e7cf745b | 378 | ? 8 : 1) |
2f90b865 AD |
379 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS |
380 | ||
49c7ffbe | 381 | /* MAX_Q_VECTORS of these are allocated, |
021230d4 AV |
382 | * but we only use one per queue-specific vector. |
383 | */ | |
384 | struct ixgbe_q_vector { | |
385 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
386 | #ifdef CONFIG_IXGBE_DCA |
387 | int cpu; /* CPU for DCA */ | |
388 | #endif | |
d5bf4f67 ET |
389 | u16 v_idx; /* index of q_vector within array, also used for |
390 | * finding the bit in EICR and friends that | |
391 | * represents the vector for this ring */ | |
392 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 393 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
394 | |
395 | struct napi_struct napi; | |
de88eeeb AD |
396 | cpumask_t affinity_mask; |
397 | int numa_node; | |
398 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 399 | char name[IFNAMSIZ + 9]; |
de88eeeb | 400 | |
e0d1095a | 401 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 | 402 | atomic_t state; |
e0d1095a | 403 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 404 | |
de88eeeb AD |
405 | /* for dynamic allocation of rings associated with this q_vector */ |
406 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 | 407 | }; |
adc81090 | 408 | |
e0d1095a | 409 | #ifdef CONFIG_NET_RX_BUSY_POLL |
adc81090 AD |
410 | enum ixgbe_qv_state_t { |
411 | IXGBE_QV_STATE_IDLE = 0, | |
412 | IXGBE_QV_STATE_NAPI, | |
413 | IXGBE_QV_STATE_POLL, | |
414 | IXGBE_QV_STATE_DISABLE | |
415 | }; | |
416 | ||
5a85e737 ET |
417 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
418 | { | |
adc81090 AD |
419 | /* reset state to idle */ |
420 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
421 | } |
422 | ||
423 | /* called from the device poll routine to get ownership of a q_vector */ | |
424 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
425 | { | |
adc81090 AD |
426 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
427 | IXGBE_QV_STATE_NAPI); | |
b4640030 | 428 | #ifdef BP_EXTENDED_STATS |
adc81090 | 429 | if (rc != IXGBE_QV_STATE_IDLE) |
7e15b90f ET |
430 | q_vector->tx.ring->stats.yields++; |
431 | #endif | |
adc81090 AD |
432 | |
433 | return rc == IXGBE_QV_STATE_IDLE; | |
5a85e737 ET |
434 | } |
435 | ||
436 | /* returns true is someone tried to get the qv while napi had it */ | |
adc81090 | 437 | static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) |
5a85e737 | 438 | { |
adc81090 AD |
439 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI); |
440 | ||
441 | /* flush any outstanding Rx frames */ | |
442 | if (q_vector->napi.gro_list) | |
443 | napi_gro_flush(&q_vector->napi, false); | |
444 | ||
445 | /* reset state to idle */ | |
446 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
447 | } |
448 | ||
449 | /* called from ixgbe_low_latency_poll() */ | |
450 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
451 | { | |
adc81090 AD |
452 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
453 | IXGBE_QV_STATE_POLL); | |
b4640030 | 454 | #ifdef BP_EXTENDED_STATS |
adc81090 | 455 | if (rc != IXGBE_QV_STATE_IDLE) |
75b6462e | 456 | q_vector->rx.ring->stats.yields++; |
7e15b90f | 457 | #endif |
adc81090 | 458 | return rc == IXGBE_QV_STATE_IDLE; |
5a85e737 ET |
459 | } |
460 | ||
461 | /* returns true if someone tried to get the qv while it was locked */ | |
adc81090 | 462 | static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) |
5a85e737 | 463 | { |
adc81090 AD |
464 | WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL); |
465 | ||
466 | /* reset state to idle */ | |
467 | atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE); | |
5a85e737 ET |
468 | } |
469 | ||
470 | /* true if a socket is polling, even if it did not get the lock */ | |
b4640030 | 471 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 | 472 | { |
adc81090 | 473 | return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL; |
5a85e737 | 474 | } |
27d9ce4f JK |
475 | |
476 | /* false if QV is currently owned */ | |
477 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
478 | { | |
adc81090 AD |
479 | int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE, |
480 | IXGBE_QV_STATE_DISABLE); | |
481 | ||
482 | return rc == IXGBE_QV_STATE_IDLE; | |
27d9ce4f JK |
483 | } |
484 | ||
e0d1095a | 485 | #else /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 ET |
486 | static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector) |
487 | { | |
488 | } | |
489 | ||
490 | static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector) | |
491 | { | |
492 | return true; | |
493 | } | |
494 | ||
495 | static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector) | |
496 | { | |
497 | return false; | |
498 | } | |
499 | ||
500 | static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector) | |
501 | { | |
502 | return false; | |
503 | } | |
504 | ||
505 | static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector) | |
506 | { | |
507 | return false; | |
508 | } | |
509 | ||
b4640030 | 510 | static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector) |
5a85e737 ET |
511 | { |
512 | return false; | |
513 | } | |
27d9ce4f JK |
514 | |
515 | static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector) | |
516 | { | |
517 | return true; | |
518 | } | |
519 | ||
e0d1095a | 520 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 521 | |
3ca8bc6d DS |
522 | #ifdef CONFIG_IXGBE_HWMON |
523 | ||
524 | #define IXGBE_HWMON_TYPE_LOC 0 | |
525 | #define IXGBE_HWMON_TYPE_TEMP 1 | |
526 | #define IXGBE_HWMON_TYPE_CAUTION 2 | |
527 | #define IXGBE_HWMON_TYPE_MAX 3 | |
528 | ||
529 | struct hwmon_attr { | |
530 | struct device_attribute dev_attr; | |
531 | struct ixgbe_hw *hw; | |
532 | struct ixgbe_thermal_diode_data *sensor; | |
533 | char name[12]; | |
534 | }; | |
535 | ||
536 | struct hwmon_buff { | |
03b77d81 GR |
537 | struct attribute_group group; |
538 | const struct attribute_group *groups[2]; | |
539 | struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; | |
540 | struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; | |
3ca8bc6d DS |
541 | unsigned int n_hwmon; |
542 | }; | |
543 | #endif /* CONFIG_IXGBE_HWMON */ | |
021230d4 | 544 | |
d5bf4f67 ET |
545 | /* |
546 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
547 | * with the first 3 bits reserved 0 | |
9a799d71 | 548 | */ |
d5bf4f67 ET |
549 | #define IXGBE_MIN_RSC_ITR 24 |
550 | #define IXGBE_100K_ITR 40 | |
551 | #define IXGBE_20K_ITR 200 | |
8ac34f10 | 552 | #define IXGBE_12K_ITR 336 |
9a799d71 | 553 | |
f56e0cb1 AD |
554 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
555 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
556 | const u32 stat_err_bits) | |
557 | { | |
558 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
559 | } | |
560 | ||
7d4987de AD |
561 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
562 | { | |
563 | u16 ntc = ring->next_to_clean; | |
564 | u16 ntu = ring->next_to_use; | |
565 | ||
566 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
567 | } | |
9a799d71 | 568 | |
e4f74028 | 569 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 570 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 571 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 572 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 573 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 574 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 | 575 | |
c88887e0 | 576 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
63f39bd1 YZ |
577 | #ifdef IXGBE_FCOE |
578 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
579 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
580 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 581 | |
021230d4 AV |
582 | #define OTHER_VECTOR 1 |
583 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
584 | ||
e8e26350 | 585 | #define MAX_MSIX_VECTORS_82599 64 |
49c7ffbe | 586 | #define MAX_Q_VECTORS_82599 64 |
eb7f139c | 587 | #define MAX_MSIX_VECTORS_82598 18 |
49c7ffbe | 588 | #define MAX_Q_VECTORS_82598 16 |
eb7f139c | 589 | |
5d7daa35 JK |
590 | struct ixgbe_mac_addr { |
591 | u8 addr[ETH_ALEN]; | |
c9f53e63 | 592 | u16 pool; |
5d7daa35 JK |
593 | u16 state; /* bitmask */ |
594 | }; | |
c9f53e63 | 595 | |
5d7daa35 JK |
596 | #define IXGBE_MAC_STATE_DEFAULT 0x1 |
597 | #define IXGBE_MAC_STATE_MODIFIED 0x2 | |
598 | #define IXGBE_MAC_STATE_IN_USE 0x4 | |
599 | ||
49c7ffbe | 600 | #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 |
e8e26350 | 601 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 |
eb7f139c | 602 | |
8f15486d | 603 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
604 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
605 | ||
46646e61 AD |
606 | /* default to trying for four seconds */ |
607 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
58e7cd24 | 608 | #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ |
46646e61 | 609 | |
9a799d71 AK |
610 | /* board specific private data structure */ |
611 | struct ixgbe_adapter { | |
46646e61 AD |
612 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
613 | /* OS defined structs */ | |
614 | struct net_device *netdev; | |
615 | struct pci_dev *pdev; | |
616 | ||
e606bfe7 AD |
617 | unsigned long state; |
618 | ||
619 | /* Some features need tri-state capability, | |
620 | * thus the additional *_CAPABLE flags. | |
621 | */ | |
622 | u32 flags; | |
b4f47a48 JK |
623 | #define IXGBE_FLAG_MSI_ENABLED BIT(1) |
624 | #define IXGBE_FLAG_MSIX_ENABLED BIT(3) | |
625 | #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) | |
626 | #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) | |
627 | #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) | |
628 | #define IXGBE_FLAG_DCA_ENABLED BIT(8) | |
629 | #define IXGBE_FLAG_DCA_CAPABLE BIT(9) | |
630 | #define IXGBE_FLAG_IMIR_ENABLED BIT(10) | |
631 | #define IXGBE_FLAG_MQ_CAPABLE BIT(11) | |
632 | #define IXGBE_FLAG_DCB_ENABLED BIT(12) | |
633 | #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) | |
634 | #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) | |
635 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) | |
636 | #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) | |
637 | #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) | |
638 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) | |
639 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) | |
640 | #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) | |
641 | #define IXGBE_FLAG_FCOE_ENABLED BIT(21) | |
642 | #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) | |
643 | #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) | |
67359c3c | 644 | #define IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE BIT(24) |
a9763f3c MR |
645 | #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) |
646 | #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) | |
8829009d | 647 | #define IXGBE_FLAG_DCB_CAPABLE BIT(27) |
a21d0822 | 648 | #define IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE BIT(28) |
e606bfe7 AD |
649 | |
650 | u32 flags2; | |
b4f47a48 JK |
651 | #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) |
652 | #define IXGBE_FLAG2_RSC_ENABLED BIT(1) | |
653 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) | |
654 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) | |
655 | #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) | |
656 | #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) | |
b4f47a48 JK |
657 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) |
658 | #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) | |
659 | #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) | |
660 | #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) | |
661 | #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) | |
a21d0822 | 662 | #define IXGBE_FLAG2_UDP_TUN_REREG_NEEDED BIT(12) |
16369564 | 663 | #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) |
d033d526 | 664 | |
46646e61 AD |
665 | /* Tx fast path data */ |
666 | int num_tx_queues; | |
667 | u16 tx_itr_setting; | |
bd198058 AD |
668 | u16 tx_work_limit; |
669 | ||
46646e61 AD |
670 | /* Rx fast path data */ |
671 | int num_rx_queues; | |
672 | u16 rx_itr_setting; | |
673 | ||
9f12df90 AD |
674 | /* Port number used to identify VXLAN traffic */ |
675 | __be16 vxlan_port; | |
a21d0822 | 676 | __be16 geneve_port; |
9f12df90 | 677 | |
9a799d71 | 678 | /* TX */ |
4a0b9ca0 | 679 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 680 | |
7ca3bc58 JB |
681 | u64 restart_queue; |
682 | u64 lsc_int; | |
46646e61 | 683 | u32 tx_timeout_count; |
7ca3bc58 | 684 | |
9a799d71 | 685 | /* RX */ |
46646e61 | 686 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
687 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
688 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 689 | u64 hw_csum_rx_error; |
e8e26350 | 690 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
691 | u64 rsc_total_count; |
692 | u64 rsc_total_flush; | |
9a799d71 | 693 | u64 non_eop_descs; |
9a799d71 AK |
694 | u32 alloc_rx_page_failed; |
695 | u32 alloc_rx_buff_failed; | |
696 | ||
49c7ffbe | 697 | struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; |
9a799d71 | 698 | |
46646e61 AD |
699 | /* DCB parameters */ |
700 | struct ieee_pfc *ixgbe_ieee_pfc; | |
701 | struct ieee_ets *ixgbe_ieee_ets; | |
702 | struct ixgbe_dcb_config dcb_cfg; | |
703 | struct ixgbe_dcb_config temp_dcb_cfg; | |
704 | u8 dcb_set_bitmap; | |
705 | u8 dcbx_cap; | |
706 | enum ixgbe_fc_mode last_lfc_mode; | |
707 | ||
49c7ffbe AD |
708 | int num_q_vectors; /* current number of q_vectors for device */ |
709 | int max_q_vectors; /* true count of q_vectors for device */ | |
46646e61 AD |
710 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
711 | struct msix_entry *msix_entries; | |
9a799d71 | 712 | |
da4dd0f7 PWJ |
713 | u32 test_icr; |
714 | struct ixgbe_ring test_tx_ring; | |
715 | struct ixgbe_ring test_rx_ring; | |
716 | ||
9a799d71 AK |
717 | /* structs defined in ixgbe_hw.h */ |
718 | struct ixgbe_hw hw; | |
719 | u16 msg_enable; | |
720 | struct ixgbe_hw_stats stats; | |
021230d4 | 721 | |
9a799d71 | 722 | u64 tx_busy; |
30efa5a3 JB |
723 | unsigned int tx_ring_count; |
724 | unsigned int rx_ring_count; | |
cf8280ee JB |
725 | |
726 | u32 link_speed; | |
727 | bool link_up; | |
58e7cd24 | 728 | unsigned long sfp_poll_time; |
cf8280ee JB |
729 | unsigned long link_check_timeout; |
730 | ||
7086400d | 731 | struct timer_list service_timer; |
46646e61 AD |
732 | struct work_struct service_task; |
733 | ||
734 | struct hlist_head fdir_filter_list; | |
735 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
736 | union ixgbe_atr_input fdir_mask; | |
737 | int fdir_filter_count; | |
c4cf55e5 PWJ |
738 | u32 fdir_pballoc; |
739 | u32 atr_sample_rate; | |
740 | spinlock_t fdir_perfect_lock; | |
46646e61 | 741 | |
d0ed8937 YZ |
742 | #ifdef IXGBE_FCOE |
743 | struct ixgbe_fcoe fcoe; | |
744 | #endif /* IXGBE_FCOE */ | |
2a1a091c | 745 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
e8e26350 | 746 | u32 wol; |
46646e61 | 747 | |
aa2bacb6 DS |
748 | u16 bridge_mode; |
749 | ||
15e5209f ET |
750 | u16 eeprom_verh; |
751 | u16 eeprom_verl; | |
c23f5b6b | 752 | u16 eeprom_cap; |
7f870475 | 753 | |
119fc60a | 754 | u32 interrupt_event; |
46646e61 | 755 | u32 led_reg; |
1a6c14a2 | 756 | |
3a6a4eda JK |
757 | struct ptp_clock *ptp_clock; |
758 | struct ptp_clock_info ptp_caps; | |
891dc082 JK |
759 | struct work_struct ptp_tx_work; |
760 | struct sk_buff *ptp_tx_skb; | |
93501d48 | 761 | struct hwtstamp_config tstamp_config; |
891dc082 | 762 | unsigned long ptp_tx_start; |
3a6a4eda | 763 | unsigned long last_overflow_check; |
6cb562d6 | 764 | unsigned long last_rx_ptp_check; |
eda183c2 | 765 | unsigned long last_rx_timestamp; |
3a6a4eda | 766 | spinlock_t tmreg_lock; |
a9763f3c MR |
767 | struct cyclecounter hw_cc; |
768 | struct timecounter hw_tc; | |
3a6a4eda | 769 | u32 base_incval; |
a9763f3c MR |
770 | u32 tx_hwtstamp_timeouts; |
771 | u32 rx_hwtstamp_cleared; | |
772 | void (*ptp_setup_sdp)(struct ixgbe_adapter *); | |
3a6a4eda | 773 | |
7f870475 GR |
774 | /* SR-IOV */ |
775 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
776 | unsigned int num_vfs; | |
777 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 778 | int vf_rate_link_speed; |
a1cbb15c GR |
779 | struct vf_macvlans vf_mvs; |
780 | struct vf_macvlans *mv_list; | |
3e05334f | 781 | |
83c61fa9 GR |
782 | u32 timer_event_accumulator; |
783 | u32 vferr_refcount; | |
5d7daa35 | 784 | struct ixgbe_mac_addr *mac_table; |
3ca8bc6d DS |
785 | struct kobject *info_kobj; |
786 | #ifdef CONFIG_IXGBE_HWMON | |
03b77d81 | 787 | struct hwmon_buff *ixgbe_hwmon_buff; |
3ca8bc6d | 788 | #endif /* CONFIG_IXGBE_HWMON */ |
00949167 CS |
789 | #ifdef CONFIG_DEBUG_FS |
790 | struct dentry *ixgbe_dbg_adapter; | |
791 | #endif /*CONFIG_DEBUG_FS*/ | |
107d3018 AD |
792 | |
793 | u8 default_up; | |
2a47fa45 | 794 | unsigned long fwd_bitmask; /* Bitmask indicating in use pools */ |
dfaf891d | 795 | |
b82b17d9 | 796 | #define IXGBE_MAX_LINK_HANDLE 10 |
1cdaaf54 | 797 | struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; |
db956ae8 | 798 | unsigned long tables; |
b82b17d9 | 799 | |
dfaf891d VZ |
800 | /* maximum number of RETA entries among all devices supported by ixgbe |
801 | * driver: currently it's x550 device in non-SRIOV mode | |
802 | */ | |
803 | #define IXGBE_MAX_RETA_ENTRIES 512 | |
804 | u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; | |
805 | ||
806 | #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ | |
807 | u32 rss_key[IXGBE_RSS_KEY_SIZE / sizeof(u32)]; | |
3e05334f AD |
808 | }; |
809 | ||
0f9b232b DS |
810 | static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) |
811 | { | |
812 | switch (adapter->hw.mac.type) { | |
813 | case ixgbe_mac_82598EB: | |
814 | case ixgbe_mac_82599EB: | |
815 | case ixgbe_mac_X540: | |
816 | return IXGBE_MAX_RSS_INDICES; | |
817 | case ixgbe_mac_X550: | |
818 | case ixgbe_mac_X550EM_x: | |
49425dfc | 819 | case ixgbe_mac_x550em_a: |
0f9b232b DS |
820 | return IXGBE_MAX_RSS_INDICES_X550; |
821 | default: | |
822 | return 0; | |
823 | } | |
824 | } | |
825 | ||
3e05334f AD |
826 | struct ixgbe_fdir_filter { |
827 | struct hlist_node fdir_node; | |
828 | union ixgbe_atr_input filter; | |
829 | u16 sw_idx; | |
2a9ed5d1 | 830 | u64 action; |
9a799d71 AK |
831 | }; |
832 | ||
70e5576c | 833 | enum ixgbe_state_t { |
9a799d71 AK |
834 | __IXGBE_TESTING, |
835 | __IXGBE_RESETTING, | |
c4900be0 | 836 | __IXGBE_DOWN, |
41c62843 | 837 | __IXGBE_DISABLED, |
09f40aed | 838 | __IXGBE_REMOVING, |
7086400d | 839 | __IXGBE_SERVICE_SCHED, |
58cf663f | 840 | __IXGBE_SERVICE_INITED, |
7086400d | 841 | __IXGBE_IN_SFP_INIT, |
8fecf67c | 842 | __IXGBE_PTP_RUNNING, |
151b260c | 843 | __IXGBE_PTP_TX_IN_PROGRESS, |
57ca2a4f | 844 | __IXGBE_RESET_REQUESTED, |
9a799d71 AK |
845 | }; |
846 | ||
4c1975d7 AD |
847 | struct ixgbe_cb { |
848 | union { /* Union defining head/tail partner */ | |
849 | struct sk_buff *head; | |
850 | struct sk_buff *tail; | |
851 | }; | |
aa80175a | 852 | dma_addr_t dma; |
4c1975d7 | 853 | u16 append_cnt; |
f800326d | 854 | bool page_released; |
aa80175a | 855 | }; |
4c1975d7 | 856 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 857 | |
9a799d71 | 858 | enum ixgbe_boards { |
3957d63d | 859 | board_82598, |
e8e26350 | 860 | board_82599, |
fe15e8e1 | 861 | board_X540, |
6a14ee0c DS |
862 | board_X550, |
863 | board_X550EM_x, | |
49425dfc | 864 | board_x550em_a, |
9a799d71 AK |
865 | }; |
866 | ||
37689010 MR |
867 | extern const struct ixgbe_info ixgbe_82598_info; |
868 | extern const struct ixgbe_info ixgbe_82599_info; | |
869 | extern const struct ixgbe_info ixgbe_X540_info; | |
870 | extern const struct ixgbe_info ixgbe_X550_info; | |
871 | extern const struct ixgbe_info ixgbe_X550EM_x_info; | |
49425dfc | 872 | extern const struct ixgbe_info ixgbe_x550em_a_info; |
7a6b6f51 | 873 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 874 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 | 875 | #endif |
9a799d71 AK |
876 | |
877 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 878 | extern const char ixgbe_driver_version[]; |
8af3c33f | 879 | #ifdef IXGBE_FCOE |
ea81875a | 880 | extern char ixgbe_default_device_descr[]; |
8af3c33f | 881 | #endif /* IXGBE_FCOE */ |
9a799d71 | 882 | |
6c211fe1 SA |
883 | int ixgbe_open(struct net_device *netdev); |
884 | int ixgbe_close(struct net_device *netdev); | |
5ccc921a JP |
885 | void ixgbe_up(struct ixgbe_adapter *adapter); |
886 | void ixgbe_down(struct ixgbe_adapter *adapter); | |
887 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); | |
888 | void ixgbe_reset(struct ixgbe_adapter *adapter); | |
889 | void ixgbe_set_ethtool_ops(struct net_device *netdev); | |
890 | int ixgbe_setup_rx_resources(struct ixgbe_ring *); | |
891 | int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
892 | void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
893 | void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
894 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
895 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); | |
896 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *); | |
897 | void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
898 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); | |
740234f0 ET |
899 | bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, |
900 | u16 subdevice_id); | |
5d7daa35 JK |
901 | #ifdef CONFIG_PCI_IOV |
902 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); | |
903 | #endif | |
904 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, | |
c9f53e63 | 905 | const u8 *addr, u16 queue); |
5d7daa35 | 906 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
c9f53e63 | 907 | const u8 *addr, u16 queue); |
e1d0a2af | 908 | void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); |
5ccc921a JP |
909 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
910 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, | |
911 | struct ixgbe_ring *); | |
912 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, | |
913 | struct ixgbe_tx_buffer *); | |
914 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); | |
915 | void ixgbe_write_eitr(struct ixgbe_q_vector *); | |
916 | int ixgbe_poll(struct napi_struct *napi, int budget); | |
917 | int ethtool_ioctl(struct ifreq *ifr); | |
918 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); | |
919 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
920 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
921 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
922 | union ixgbe_atr_hash_dword input, | |
923 | union ixgbe_atr_hash_dword common, | |
924 | u8 queue); | |
925 | s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, | |
926 | union ixgbe_atr_input *input_mask); | |
927 | s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
928 | union ixgbe_atr_input *input, | |
929 | u16 soft_id, u8 queue); | |
930 | s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
931 | union ixgbe_atr_input *input, | |
932 | u16 soft_id); | |
933 | void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
934 | union ixgbe_atr_input *mask); | |
b82b17d9 JF |
935 | int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, |
936 | struct ixgbe_fdir_filter *input, | |
937 | u16 sw_idx); | |
5ccc921a | 938 | void ixgbe_set_rx_mode(struct net_device *netdev); |
8af3c33f | 939 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a | 940 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); |
8af3c33f | 941 | #endif |
5ccc921a JP |
942 | int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
943 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); | |
944 | void ixgbe_do_reset(struct net_device *netdev); | |
1210982b | 945 | #ifdef CONFIG_IXGBE_HWMON |
5ccc921a JP |
946 | void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); |
947 | int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); | |
1210982b | 948 | #endif /* CONFIG_IXGBE_HWMON */ |
eacd73f7 | 949 | #ifdef IXGBE_FCOE |
5ccc921a JP |
950 | void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); |
951 | int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, | |
952 | u8 *hdr_len); | |
953 | int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
954 | union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); | |
955 | int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
956 | struct scatterlist *sgl, unsigned int sgc); | |
957 | int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, | |
958 | struct scatterlist *sgl, unsigned int sgc); | |
959 | int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
960 | int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
961 | void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); | |
962 | int ixgbe_fcoe_enable(struct net_device *netdev); | |
963 | int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 | 964 | #ifdef CONFIG_IXGBE_DCB |
5ccc921a JP |
965 | u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); |
966 | u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
6ee16520 | 967 | #endif /* CONFIG_IXGBE_DCB */ |
5ccc921a JP |
968 | int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
969 | int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, | |
970 | struct netdev_fcoe_hbainfo *info); | |
971 | u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); | |
eacd73f7 | 972 | #endif /* IXGBE_FCOE */ |
00949167 | 973 | #ifdef CONFIG_DEBUG_FS |
5ccc921a JP |
974 | void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); |
975 | void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); | |
976 | void ixgbe_dbg_init(void); | |
977 | void ixgbe_dbg_exit(void); | |
33243fb0 JP |
978 | #else |
979 | static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} | |
980 | static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} | |
981 | static inline void ixgbe_dbg_init(void) {} | |
982 | static inline void ixgbe_dbg_exit(void) {} | |
00949167 | 983 | #endif /* CONFIG_DEBUG_FS */ |
b2d96e0a AD |
984 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
985 | { | |
986 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
987 | } | |
988 | ||
5ccc921a | 989 | void ixgbe_ptp_init(struct ixgbe_adapter *adapter); |
9966d1ee | 990 | void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); |
5ccc921a JP |
991 | void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); |
992 | void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); | |
993 | void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); | |
a9763f3c MR |
994 | void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); |
995 | void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); | |
996 | static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, | |
997 | union ixgbe_adv_rx_desc *rx_desc, | |
998 | struct sk_buff *skb) | |
999 | { | |
1000 | if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { | |
1001 | ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); | |
1002 | return; | |
1003 | } | |
1004 | ||
1005 | if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) | |
1006 | return; | |
1007 | ||
1008 | ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); | |
1009 | ||
1010 | /* Update the last_rx_timestamp timer in order to enable watchdog check | |
1011 | * for error case of latched timestamp on a dropped packet. | |
1012 | */ | |
1013 | rx_ring->last_rx_timestamp = jiffies; | |
1014 | } | |
1015 | ||
93501d48 JK |
1016 | int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); |
1017 | int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); | |
5ccc921a JP |
1018 | void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); |
1019 | void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); | |
a9763f3c | 1020 | void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); |
da36b647 GR |
1021 | #ifdef CONFIG_PCI_IOV |
1022 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); | |
1023 | #endif | |
3a6a4eda | 1024 | |
2a47fa45 JF |
1025 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
1026 | struct ixgbe_adapter *adapter, | |
1027 | struct ixgbe_ring *tx_ring); | |
7f276efb | 1028 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); |
1c7cf078 | 1029 | void ixgbe_store_reta(struct ixgbe_adapter *adapter); |
9a799d71 | 1030 | #endif /* _IXGBE_H_ */ |