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ixgbe: fix checkpatch style of blank line after declaration
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
14438464 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
ccffad25 32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 44 u16 count);
c44ade9e
JB		 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 49
9a799d71 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
ff9d1a5a 58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 59
67a79df2
AD		 60/**
61 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * control
63 * @hw: pointer to hardware structure
64 *
65 * There are several phys that do not support autoneg flow control. This
66 * function check the device id to see if the associated phy supports
67 * autoneg flow control.
68 **/
73d80953 69bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2 70{
73d80953
DS		 71 bool supported = false;
72 ixgbe_link_speed speed;
73 bool link_up;
67a79df2 74
73d80953
DS		 75 switch (hw->phy.media_type) {
76 case ixgbe_media_type_fiber:
77 hw->mac.ops.check_link(hw, &speed, &link_up, false);
78 /* if link is down, assume supported */
79 if (link_up)
80 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
81 true : false;
82 else
83 supported = true;
84 break;
85 case ixgbe_media_type_backplane:
86 supported = true;
87 break;
88 case ixgbe_media_type_copper:
89 /* only some copper devices support flow control autoneg */
90 switch (hw->device_id) {
91 case IXGBE_DEV_ID_82599_T3_LOM:
92 case IXGBE_DEV_ID_X540T:
93 case IXGBE_DEV_ID_X540T1:
94 supported = true;
95 break;
96 default:
97 break;
98 }
67a79df2 99 default:
73d80953 100 break;
67a79df2 101 }
73d80953
DS		 102
103 return supported;
67a79df2
AD		 104}
105
106/**
107 * ixgbe_setup_fc - Set up flow control
108 * @hw: pointer to hardware structure
109 *
110 * Called at init time to set up flow control.
111 **/
041441d0 112static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 113{
114 s32 ret_val = 0;
115 u32 reg = 0, reg_bp = 0;
116 u16 reg_cu = 0;
429d6a3b 117 bool locked = false;
67a79df2 118
67a79df2
AD		 119 /*
120 * Validate the requested mode. Strict IEEE mode does not allow
121 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
122 */
123 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
124 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
125 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
126 goto out;
127 }
128
129 /*
130 * 10gig parts do not have a word in the EEPROM to determine the
131 * default flow control setting, so we explicitly set it to full.
132 */
133 if (hw->fc.requested_mode == ixgbe_fc_default)
134 hw->fc.requested_mode = ixgbe_fc_full;
135
136 /*
137 * Set up the 1G and 10G flow control advertisement registers so the
138 * HW will be able to do fc autoneg once the cable is plugged in. If
139 * we link at 10G, the 1G advertisement is harmless and vice versa.
140 */
67a79df2 141 switch (hw->phy.media_type) {
429d6a3b
DS		 142 case ixgbe_media_type_backplane:
143 /* some MAC's need RMW protection on AUTOC */
144 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
f8cf7a00 145 if (ret_val)
429d6a3b
DS		 146 goto out;
147
148 /* only backplane uses autoc so fall though */
67a79df2 149 case ixgbe_media_type_fiber:
67a79df2 150 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
429d6a3b 151
67a79df2 152 break;
67a79df2
AD		 153 case ixgbe_media_type_copper:
154 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
155 MDIO_MMD_AN, &reg_cu);
156 break;
67a79df2 157 default:
041441d0 158 break;
67a79df2
AD		 159 }
160
161 /*
162 * The possible values of fc.requested_mode are:
163 * 0: Flow control is completely disabled
164 * 1: Rx flow control is enabled (we can receive pause frames,
165 * but not send pause frames).
166 * 2: Tx flow control is enabled (we can send pause frames but
167 * we do not support receiving pause frames).
168 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 169 * other: Invalid.
170 */
171 switch (hw->fc.requested_mode) {
172 case ixgbe_fc_none:
173 /* Flow control completely disabled by software override. */
174 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
175 if (hw->phy.media_type == ixgbe_media_type_backplane)
176 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
177 IXGBE_AUTOC_ASM_PAUSE);
178 else if (hw->phy.media_type == ixgbe_media_type_copper)
179 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
180 break;
67a79df2
AD		 181 case ixgbe_fc_tx_pause:
182 /*
183 * Tx Flow control is enabled, and Rx Flow control is
184 * disabled by software override.
185 */
041441d0
AD		 186 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
187 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 188 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 189 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
190 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 191 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 192 reg_cu |= IXGBE_TAF_ASM_PAUSE;
193 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 194 }
195 break;
041441d0
AD		 196 case ixgbe_fc_rx_pause:
197 /*
198 * Rx Flow control is enabled and Tx Flow control is
199 * disabled by software override. Since there really
200 * isn't a way to advertise that we are capable of RX
201 * Pause ONLY, we will advertise that we support both
202 * symmetric and asymmetric Rx PAUSE, as such we fall
203 * through to the fc_full statement. Later, we will
204 * disable the adapter's ability to send PAUSE frames.
205 */
67a79df2
AD		 206 case ixgbe_fc_full:
207 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 208 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 209 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 210 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
211 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 212 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 213 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 214 break;
67a79df2
AD		 215 default:
216 hw_dbg(hw, "Flow control param set incorrectly\n");
217 ret_val = IXGBE_ERR_CONFIG;
218 goto out;
219 break;
220 }
221
222 if (hw->mac.type != ixgbe_mac_X540) {
223 /*
224 * Enable auto-negotiation between the MAC & PHY;
225 * the MAC will advertise clause 37 flow control.
226 */
227 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
228 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
229
230 /* Disable AN timeout */
231 if (hw->fc.strict_ieee)
232 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
233
234 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
235 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
236 }
237
238 /*
239 * AUTOC restart handles negotiation of 1G and 10G on backplane
240 * and copper. There is no need to set the PCS1GCTL register.
241 *
242 */
243 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 244 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
245 * LESM is on, likewise reset_pipeline requries the lock as
246 * it also writes AUTOC.
247 */
429d6a3b
DS		 248 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
249 if (ret_val)
250 goto out;
d7bbcd32 251
67a79df2 252 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
429d6a3b 253 ixgbe_device_supports_autoneg_fc(hw)) {
67a79df2
AD		 254 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
255 MDIO_MMD_AN, reg_cu);
256 }
257
258 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
259out:
260 return ret_val;
261}
262
9a799d71 263/**
c44ade9e 264 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 265 * @hw: pointer to hardware structure
266 *
267 * Starts the hardware by filling the bus info structure and media type, clears
268 * all on chip counters, initializes receive address registers, multicast
269 * table, VLAN filter table, calls routine to set up link and flow control
270 * settings, and leaves transmit and receive units disabled and uninitialized
271 **/
c44ade9e 272s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71 273{
e5776620 274 s32 ret_val;
9a799d71
AK		 275 u32 ctrl_ext;
276
277 /* Set the media type */
278 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
279
280 /* Identify the PHY */
c44ade9e 281 hw->phy.ops.identify(hw);
9a799d71 282
9a799d71 283 /* Clear the VLAN filter table */
c44ade9e 284 hw->mac.ops.clear_vfta(hw);
9a799d71 285
9a799d71 286 /* Clear statistics registers */
c44ade9e 287 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 288
289 /* Set No Snoop Disable */
290 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
291 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
292 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 293 IXGBE_WRITE_FLUSH(hw);
9a799d71 294
620fa036 295 /* Setup flow control */
e5776620
JK		 296 ret_val = ixgbe_setup_fc(hw);
297 if (!ret_val)
298 goto out;
620fa036 299
9a799d71
AK		 300 /* Clear adapter stopped flag */
301 hw->adapter_stopped = false;
302
e5776620
JK		 303out:
304 return ret_val;
9a799d71
AK		 305}
306
7184b7cf
ET		 307/**
308 * ixgbe_start_hw_gen2 - Init sequence for common device family
309 * @hw: pointer to hw structure
310 *
311 * Performs the init sequence common to the second generation
312 * of 10 GbE devices.
313 * Devices in the second generation:
314 * 82599
315 * X540
316 **/
317s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
318{
319 u32 i;
3d5c5207 320 u32 regval;
7184b7cf
ET		 321
322 /* Clear the rate limiters */
323 for (i = 0; i < hw->mac.max_tx_queues; i++) {
324 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
325 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
326 }
327 IXGBE_WRITE_FLUSH(hw);
328
3d5c5207
ET		 329 /* Disable relaxed ordering */
330 for (i = 0; i < hw->mac.max_tx_queues; i++) {
331 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 332 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 333 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
334 }
335
336 for (i = 0; i < hw->mac.max_rx_queues; i++) {
337 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 338 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
339 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 340 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
341 }
342
7184b7cf
ET		 343 return 0;
344}
345
9a799d71 346/**
c44ade9e 347 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 348 * @hw: pointer to hardware structure
349 *
c44ade9e 350 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 351 * structure and media type, clears all on chip counters, initializes receive
352 * address registers, multicast table, VLAN filter table, calls routine to set
353 * up link and flow control settings, and leaves transmit and receive units
354 * disabled and uninitialized
355 **/
c44ade9e 356s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 357{
794caeb2
PWJ		 358 s32 status;
359
9a799d71 360 /* Reset the hardware */
794caeb2 361 status = hw->mac.ops.reset_hw(hw);
9a799d71 362
794caeb2
PWJ		 363 if (status == 0) {
364 /* Start the HW */
365 status = hw->mac.ops.start_hw(hw);
366 }
9a799d71 367
794caeb2 368 return status;
9a799d71
AK		 369}
370
371/**
c44ade9e 372 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 373 * @hw: pointer to hardware structure
374 *
375 * Clears all hardware statistics counters by reading them from the hardware
376 * Statistics counters are clear on read.
377 **/
c44ade9e 378s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 379{
380 u16 i = 0;
381
382 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
383 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
384 IXGBE_READ_REG(hw, IXGBE_ERRBC);
385 IXGBE_READ_REG(hw, IXGBE_MSPDC);
386 for (i = 0; i < 8; i++)
387 IXGBE_READ_REG(hw, IXGBE_MPC(i));
388
389 IXGBE_READ_REG(hw, IXGBE_MLFC);
390 IXGBE_READ_REG(hw, IXGBE_MRFC);
391 IXGBE_READ_REG(hw, IXGBE_RLEC);
392 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 393 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 394 if (hw->mac.type >= ixgbe_mac_82599EB) {
395 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
396 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
397 } else {
398 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
399 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
400 }
9a799d71
AK		 401
402 for (i = 0; i < 8; i++) {
403 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 404 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 405 if (hw->mac.type >= ixgbe_mac_82599EB) {
406 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
407 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
408 } else {
409 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
410 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
411 }
9a799d71 412 }
667c7565
ET		 413 if (hw->mac.type >= ixgbe_mac_82599EB)
414 for (i = 0; i < 8; i++)
415 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 416 IXGBE_READ_REG(hw, IXGBE_PRC64);
417 IXGBE_READ_REG(hw, IXGBE_PRC127);
418 IXGBE_READ_REG(hw, IXGBE_PRC255);
419 IXGBE_READ_REG(hw, IXGBE_PRC511);
420 IXGBE_READ_REG(hw, IXGBE_PRC1023);
421 IXGBE_READ_REG(hw, IXGBE_PRC1522);
422 IXGBE_READ_REG(hw, IXGBE_GPRC);
423 IXGBE_READ_REG(hw, IXGBE_BPRC);
424 IXGBE_READ_REG(hw, IXGBE_MPRC);
425 IXGBE_READ_REG(hw, IXGBE_GPTC);
426 IXGBE_READ_REG(hw, IXGBE_GORCL);
427 IXGBE_READ_REG(hw, IXGBE_GORCH);
428 IXGBE_READ_REG(hw, IXGBE_GOTCL);
429 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 430 if (hw->mac.type == ixgbe_mac_82598EB)
431 for (i = 0; i < 8; i++)
432 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 433 IXGBE_READ_REG(hw, IXGBE_RUC);
434 IXGBE_READ_REG(hw, IXGBE_RFC);
435 IXGBE_READ_REG(hw, IXGBE_ROC);
436 IXGBE_READ_REG(hw, IXGBE_RJC);
437 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
438 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
439 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
440 IXGBE_READ_REG(hw, IXGBE_TORL);
441 IXGBE_READ_REG(hw, IXGBE_TORH);
442 IXGBE_READ_REG(hw, IXGBE_TPR);
443 IXGBE_READ_REG(hw, IXGBE_TPT);
444 IXGBE_READ_REG(hw, IXGBE_PTC64);
445 IXGBE_READ_REG(hw, IXGBE_PTC127);
446 IXGBE_READ_REG(hw, IXGBE_PTC255);
447 IXGBE_READ_REG(hw, IXGBE_PTC511);
448 IXGBE_READ_REG(hw, IXGBE_PTC1023);
449 IXGBE_READ_REG(hw, IXGBE_PTC1522);
450 IXGBE_READ_REG(hw, IXGBE_MPTC);
451 IXGBE_READ_REG(hw, IXGBE_BPTC);
452 for (i = 0; i < 16; i++) {
453 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 454 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 455 if (hw->mac.type >= ixgbe_mac_82599EB) {
456 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
457 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
458 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
459 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
460 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
461 } else {
462 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
463 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
464 }
9a799d71
AK		 465 }
466
a3aeea0e
ET		 467 if (hw->mac.type == ixgbe_mac_X540) {
468 if (hw->phy.id == 0)
469 hw->phy.ops.identify(hw);
c1085b10
ET		 470 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
471 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
472 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
473 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 474 }
475
9a799d71
AK		 476 return 0;
477}
478
479/**
289700db 480 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 481 * @hw: pointer to hardware structure
289700db
DS		 482 * @pba_num: stores the part number string from the EEPROM
483 * @pba_num_size: part number string buffer length
c44ade9e 484 *
289700db 485 * Reads the part number string from the EEPROM.
c44ade9e 486 **/
289700db 487s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 488 u32 pba_num_size)
c44ade9e
JB		 489{
490 s32 ret_val;
491 u16 data;
289700db
DS		 492 u16 pba_ptr;
493 u16 offset;
494 u16 length;
495
496 if (pba_num == NULL) {
497 hw_dbg(hw, "PBA string buffer was null\n");
498 return IXGBE_ERR_INVALID_ARGUMENT;
499 }
c44ade9e
JB		 500
501 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
502 if (ret_val) {
503 hw_dbg(hw, "NVM Read Error\n");
504 return ret_val;
505 }
c44ade9e 506
289700db 507 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 508 if (ret_val) {
509 hw_dbg(hw, "NVM Read Error\n");
510 return ret_val;
511 }
289700db
DS		 512
513 /*
514 * if data is not ptr guard the PBA must be in legacy format which
515 * means pba_ptr is actually our second data word for the PBA number
516 * and we can decode it into an ascii string
517 */
518 if (data != IXGBE_PBANUM_PTR_GUARD) {
519 hw_dbg(hw, "NVM PBA number is not stored as string\n");
520
521 /* we will need 11 characters to store the PBA */
522 if (pba_num_size < 11) {
523 hw_dbg(hw, "PBA string buffer too small\n");
524 return IXGBE_ERR_NO_SPACE;
525 }
526
527 /* extract hex string from data and pba_ptr */
528 pba_num[0] = (data >> 12) & 0xF;
529 pba_num[1] = (data >> 8) & 0xF;
530 pba_num[2] = (data >> 4) & 0xF;
531 pba_num[3] = data & 0xF;
532 pba_num[4] = (pba_ptr >> 12) & 0xF;
533 pba_num[5] = (pba_ptr >> 8) & 0xF;
534 pba_num[6] = '-';
535 pba_num[7] = 0;
536 pba_num[8] = (pba_ptr >> 4) & 0xF;
537 pba_num[9] = pba_ptr & 0xF;
538
539 /* put a null character on the end of our string */
540 pba_num[10] = '\0';
541
542 /* switch all the data but the '-' to hex char */
543 for (offset = 0; offset < 10; offset++) {
544 if (pba_num[offset] < 0xA)
545 pba_num[offset] += '0';
546 else if (pba_num[offset] < 0x10)
547 pba_num[offset] += 'A' - 0xA;
548 }
549
550 return 0;
551 }
552
553 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
554 if (ret_val) {
555 hw_dbg(hw, "NVM Read Error\n");
556 return ret_val;
557 }
558
559 if (length == 0xFFFF || length == 0) {
560 hw_dbg(hw, "NVM PBA number section invalid length\n");
561 return IXGBE_ERR_PBA_SECTION;
562 }
563
564 /* check if pba_num buffer is big enough */
565 if (pba_num_size < (((u32)length * 2) - 1)) {
566 hw_dbg(hw, "PBA string buffer too small\n");
567 return IXGBE_ERR_NO_SPACE;
568 }
569
570 /* trim pba length from start of string */
571 pba_ptr++;
572 length--;
573
574 for (offset = 0; offset < length; offset++) {
575 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
576 if (ret_val) {
577 hw_dbg(hw, "NVM Read Error\n");
578 return ret_val;
579 }
580 pba_num[offset * 2] = (u8)(data >> 8);
581 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
582 }
583 pba_num[offset * 2] = '\0';
c44ade9e
JB		 584
585 return 0;
586}
587
588/**
589 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 590 * @hw: pointer to hardware structure
591 * @mac_addr: Adapter MAC address
592 *
593 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
594 * A reset of the adapter must be performed prior to calling this function
595 * in order for the MAC address to have been loaded from the EEPROM into RAR0
596 **/
c44ade9e 597s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 598{
599 u32 rar_high;
600 u32 rar_low;
601 u16 i;
602
603 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
604 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
605
606 for (i = 0; i < 4; i++)
607 mac_addr[i] = (u8)(rar_low >> (i*8));
608
609 for (i = 0; i < 2; i++)
610 mac_addr[i+4] = (u8)(rar_high >> (i*8));
611
612 return 0;
613}
614
ef1889d5
JK		 615enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
616{
617 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
618 case IXGBE_PCI_LINK_WIDTH_1:
619 return ixgbe_bus_width_pcie_x1;
620 case IXGBE_PCI_LINK_WIDTH_2:
621 return ixgbe_bus_width_pcie_x2;
622 case IXGBE_PCI_LINK_WIDTH_4:
623 return ixgbe_bus_width_pcie_x4;
624 case IXGBE_PCI_LINK_WIDTH_8:
625 return ixgbe_bus_width_pcie_x8;
626 default:
627 return ixgbe_bus_width_unknown;
628 }
629}
630
631enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
632{
633 switch (link_status & IXGBE_PCI_LINK_SPEED) {
634 case IXGBE_PCI_LINK_SPEED_2500:
635 return ixgbe_bus_speed_2500;
636 case IXGBE_PCI_LINK_SPEED_5000:
637 return ixgbe_bus_speed_5000;
638 case IXGBE_PCI_LINK_SPEED_8000:
639 return ixgbe_bus_speed_8000;
640 default:
641 return ixgbe_bus_speed_unknown;
642 }
643}
644
11afc1b1
PW		 645/**
646 * ixgbe_get_bus_info_generic - Generic set PCI bus info
647 * @hw: pointer to hardware structure
648 *
649 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
650 **/
651s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
652{
11afc1b1
PW		 653 u16 link_status;
654
655 hw->bus.type = ixgbe_bus_type_pci_express;
656
657 /* Get the negotiated link width and speed from PCI config space */
0d7c6e00 658 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
11afc1b1 659
ef1889d5
JK		 660 hw->bus.width = ixgbe_convert_bus_width(link_status);
661 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1 662
0d7c6e00 663 hw->mac.ops.set_lan_id(hw);
11afc1b1
PW		 664
665 return 0;
666}
667
668/**
669 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
670 * @hw: pointer to the HW structure
671 *
672 * Determines the LAN function id by reading memory-mapped registers
673 * and swaps the port value if requested.
674 **/
675void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
676{
677 struct ixgbe_bus_info *bus = &hw->bus;
678 u32 reg;
679
680 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
681 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
682 bus->lan_id = bus->func;
683
684 /* check for a port swap */
685 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
686 if (reg & IXGBE_FACTPS_LFS)
687 bus->func ^= 0x1;
688}
689
9a799d71 690/**
c44ade9e 691 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 692 * @hw: pointer to hardware structure
693 *
694 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
695 * disables transmit and receive units. The adapter_stopped flag is used by
696 * the shared code and drivers to determine if the adapter is in a stopped
697 * state and should not touch the hardware.
698 **/
c44ade9e 699s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 700{
9a799d71
AK		 701 u32 reg_val;
702 u16 i;
703
704 /*
705 * Set the adapter_stopped flag so other driver functions stop touching
706 * the hardware
707 */
708 hw->adapter_stopped = true;
709
710 /* Disable the receive unit */
ff9d1a5a 711 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
9a799d71 712
ff9d1a5a 713 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 714 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
715
ff9d1a5a 716 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 717 IXGBE_READ_REG(hw, IXGBE_EICR);
718
719 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 720 for (i = 0; i < hw->mac.max_tx_queues; i++)
721 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
722
723 /* Disable the receive unit by stopping each queue */
724 for (i = 0; i < hw->mac.max_rx_queues; i++) {
725 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
726 reg_val &= ~IXGBE_RXDCTL_ENABLE;
727 reg_val |= IXGBE_RXDCTL_SWFLSH;
728 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 729 }
730
ff9d1a5a
ET		 731 /* flush all queues disables */
732 IXGBE_WRITE_FLUSH(hw);
733 usleep_range(1000, 2000);
734
c44ade9e
JB		 735 /*
736 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
737 * access and verify no pending requests
738 */
ff9d1a5a 739 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 740}
741
742/**
c44ade9e 743 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 744 * @hw: pointer to hardware structure
745 * @index: led number to turn on
746 **/
c44ade9e 747s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 748{
749 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
750
751 /* To turn on the LED, set mode to ON. */
752 led_reg &= ~IXGBE_LED_MODE_MASK(index);
753 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
754 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 755 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 756
757 return 0;
758}
759
760/**
c44ade9e 761 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 762 * @hw: pointer to hardware structure
763 * @index: led number to turn off
764 **/
c44ade9e 765s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 766{
767 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
768
769 /* To turn off the LED, set mode to OFF. */
770 led_reg &= ~IXGBE_LED_MODE_MASK(index);
771 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
772 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 773 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 774
775 return 0;
776}
777
9a799d71 778/**
c44ade9e 779 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 780 * @hw: pointer to hardware structure
781 *
782 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
783 * ixgbe_hw struct in order to set up EEPROM access.
784 **/
c44ade9e 785s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 786{
787 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
788 u32 eec;
789 u16 eeprom_size;
790
791 if (eeprom->type == ixgbe_eeprom_uninitialized) {
792 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 793 /* Set default semaphore delay to 10ms which is a well
794 * tested value */
795 eeprom->semaphore_delay = 10;
68c7005d
ET		 796 /* Clear EEPROM page size, it will be initialized as needed */
797 eeprom->word_page_size = 0;
9a799d71
AK		 798
799 /*
800 * Check for EEPROM present first.
801 * If not present leave as none
802 */
803 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
804 if (eec & IXGBE_EEC_PRES) {
805 eeprom->type = ixgbe_eeprom_spi;
806
807 /*
808 * SPI EEPROM is assumed here. This code would need to
809 * change if a future EEPROM is not SPI.
810 */
811 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
812 IXGBE_EEC_SIZE_SHIFT);
813 eeprom->word_size = 1 << (eeprom_size +
814 IXGBE_EEPROM_WORD_SIZE_SHIFT);
815 }
816
817 if (eec & IXGBE_EEC_ADDR_SIZE)
818 eeprom->address_bits = 16;
819 else
820 eeprom->address_bits = 8;
821 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
822 "%d\n", eeprom->type, eeprom->word_size,
823 eeprom->address_bits);
824 }
825
826 return 0;
827}
828
11afc1b1 829/**
68c7005d 830 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 831 * @hw: pointer to hardware structure
68c7005d
ET		 832 * @offset: offset within the EEPROM to write
833 * @words: number of words
834 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 835 *
68c7005d 836 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 837 **/
68c7005d
ET		 838s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
839 u16 words, u16 *data)
11afc1b1 840{
68c7005d
ET		 841 s32 status = 0;
842 u16 i, count;
11afc1b1
PW		 843
844 hw->eeprom.ops.init_params(hw);
845
68c7005d
ET		 846 if (words == 0) {
847 status = IXGBE_ERR_INVALID_ARGUMENT;
848 goto out;
849 }
850
851 if (offset + words > hw->eeprom.word_size) {
11afc1b1
PW		 852 status = IXGBE_ERR_EEPROM;
853 goto out;
854 }
855
68c7005d
ET		 856 /*
857 * The EEPROM page size cannot be queried from the chip. We do lazy
858 * initialization. It is worth to do that when we write large buffer.
859 */
860 if ((hw->eeprom.word_page_size == 0) &&
861 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
862 ixgbe_detect_eeprom_page_size_generic(hw, offset);
863
864 /*
865 * We cannot hold synchronization semaphores for too long
866 * to avoid other entity starvation. However it is more efficient
867 * to read in bursts than synchronizing access for each word.
868 */
869 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
870 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
871 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
872 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
873 count, &data[i]);
874
875 if (status != 0)
876 break;
877 }
878
879out:
880 return status;
881}
882
883/**
884 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
885 * @hw: pointer to hardware structure
886 * @offset: offset within the EEPROM to be written to
887 * @words: number of word(s)
888 * @data: 16 bit word(s) to be written to the EEPROM
889 *
890 * If ixgbe_eeprom_update_checksum is not called after this function, the
891 * EEPROM will most likely contain an invalid checksum.
892 **/
893static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
894 u16 words, u16 *data)
895{
896 s32 status;
897 u16 word;
898 u16 page_size;
899 u16 i;
900 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
901
11afc1b1
PW		 902 /* Prepare the EEPROM for writing */
903 status = ixgbe_acquire_eeprom(hw);
904
905 if (status == 0) {
906 if (ixgbe_ready_eeprom(hw) != 0) {
907 ixgbe_release_eeprom(hw);
908 status = IXGBE_ERR_EEPROM;
909 }
910 }
911
912 if (status == 0) {
68c7005d
ET		 913 for (i = 0; i < words; i++) {
914 ixgbe_standby_eeprom(hw);
11afc1b1 915
68c7005d
ET		 916 /* Send the WRITE ENABLE command (8 bit opcode ) */
917 ixgbe_shift_out_eeprom_bits(hw,
918 IXGBE_EEPROM_WREN_OPCODE_SPI,
919 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 920
68c7005d 921 ixgbe_standby_eeprom(hw);
11afc1b1 922
68c7005d
ET		 923 /*
924 * Some SPI eeproms use the 8th address bit embedded
925 * in the opcode
926 */
927 if ((hw->eeprom.address_bits == 8) &&
928 ((offset + i) >= 128))
929 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
930
931 /* Send the Write command (8-bit opcode + addr) */
932 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
933 IXGBE_EEPROM_OPCODE_BITS);
934 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
935 hw->eeprom.address_bits);
936
937 page_size = hw->eeprom.word_page_size;
938
939 /* Send the data in burst via SPI*/
940 do {
941 word = data[i];
942 word = (word >> 8) | (word << 8);
943 ixgbe_shift_out_eeprom_bits(hw, word, 16);
944
945 if (page_size == 0)
946 break;
947
948 /* do not wrap around page */
949 if (((offset + i) & (page_size - 1)) ==
950 (page_size - 1))
951 break;
952 } while (++i < words);
953
954 ixgbe_standby_eeprom(hw);
955 usleep_range(10000, 20000);
956 }
957 /* Done with writing - release the EEPROM */
958 ixgbe_release_eeprom(hw);
959 }
11afc1b1 960
68c7005d
ET		 961 return status;
962}
963
964/**
965 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
966 * @hw: pointer to hardware structure
967 * @offset: offset within the EEPROM to be written to
968 * @data: 16 bit word to be written to the EEPROM
969 *
970 * If ixgbe_eeprom_update_checksum is not called after this function, the
971 * EEPROM will most likely contain an invalid checksum.
972 **/
973s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
974{
975 s32 status;
11afc1b1 976
68c7005d 977 hw->eeprom.ops.init_params(hw);
11afc1b1 978
68c7005d
ET		 979 if (offset >= hw->eeprom.word_size) {
980 status = IXGBE_ERR_EEPROM;
981 goto out;
11afc1b1
PW		 982 }
983
68c7005d
ET		 984 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
985
11afc1b1
PW		 986out:
987 return status;
988}
989
9a799d71 990/**
68c7005d 991 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 992 * @hw: pointer to hardware structure
993 * @offset: offset within the EEPROM to be read
68c7005d
ET		 994 * @words: number of word(s)
995 * @data: read 16 bit words(s) from EEPROM
c44ade9e 996 *
68c7005d 997 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 998 **/
68c7005d
ET		 999s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1000 u16 words, u16 *data)
c44ade9e 1001{
68c7005d
ET		 1002 s32 status = 0;
1003 u16 i, count;
c44ade9e
JB		 1004
1005 hw->eeprom.ops.init_params(hw);
1006
68c7005d
ET		 1007 if (words == 0) {
1008 status = IXGBE_ERR_INVALID_ARGUMENT;
1009 goto out;
1010 }
1011
1012 if (offset + words > hw->eeprom.word_size) {
c44ade9e
JB		 1013 status = IXGBE_ERR_EEPROM;
1014 goto out;
1015 }
1016
68c7005d
ET		 1017 /*
1018 * We cannot hold synchronization semaphores for too long
1019 * to avoid other entity starvation. However it is more efficient
1020 * to read in bursts than synchronizing access for each word.
1021 */
1022 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1023 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1024 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1025
1026 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1027 count, &data[i]);
1028
1029 if (status != 0)
1030 break;
1031 }
1032
1033out:
1034 return status;
1035}
1036
1037/**
1038 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1039 * @hw: pointer to hardware structure
1040 * @offset: offset within the EEPROM to be read
1041 * @words: number of word(s)
1042 * @data: read 16 bit word(s) from EEPROM
1043 *
1044 * Reads 16 bit word(s) from EEPROM through bit-bang method
1045 **/
1046static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1047 u16 words, u16 *data)
1048{
1049 s32 status;
1050 u16 word_in;
1051 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1052 u16 i;
1053
c44ade9e
JB		 1054 /* Prepare the EEPROM for reading */
1055 status = ixgbe_acquire_eeprom(hw);
1056
1057 if (status == 0) {
1058 if (ixgbe_ready_eeprom(hw) != 0) {
1059 ixgbe_release_eeprom(hw);
1060 status = IXGBE_ERR_EEPROM;
1061 }
1062 }
1063
1064 if (status == 0) {
68c7005d
ET		 1065 for (i = 0; i < words; i++) {
1066 ixgbe_standby_eeprom(hw);
1067 /*
1068 * Some SPI eeproms use the 8th address bit embedded
1069 * in the opcode
1070 */
1071 if ((hw->eeprom.address_bits == 8) &&
1072 ((offset + i) >= 128))
1073 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1074
1075 /* Send the READ command (opcode + addr) */
1076 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1077 IXGBE_EEPROM_OPCODE_BITS);
1078 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1079 hw->eeprom.address_bits);
1080
1081 /* Read the data. */
1082 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1083 data[i] = (word_in >> 8) | (word_in << 8);
1084 }
c44ade9e 1085
68c7005d
ET		 1086 /* End this read operation */
1087 ixgbe_release_eeprom(hw);
1088 }
c44ade9e 1089
68c7005d
ET		 1090 return status;
1091}
c44ade9e 1092
68c7005d
ET		 1093/**
1094 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1095 * @hw: pointer to hardware structure
1096 * @offset: offset within the EEPROM to be read
1097 * @data: read 16 bit value from EEPROM
1098 *
1099 * Reads 16 bit value from EEPROM through bit-bang method
1100 **/
1101s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1102 u16 *data)
1103{
1104 s32 status;
c44ade9e 1105
68c7005d
ET		 1106 hw->eeprom.ops.init_params(hw);
1107
1108 if (offset >= hw->eeprom.word_size) {
1109 status = IXGBE_ERR_EEPROM;
1110 goto out;
c44ade9e
JB		 1111 }
1112
68c7005d
ET		 1113 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1114
c44ade9e
JB		 1115out:
1116 return status;
1117}
1118
1119/**
68c7005d 1120 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1121 * @hw: pointer to hardware structure
68c7005d
ET		 1122 * @offset: offset of word in the EEPROM to read
1123 * @words: number of word(s)
1124 * @data: 16 bit word(s) from the EEPROM
9a799d71 1125 *
68c7005d 1126 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1127 **/
68c7005d
ET		 1128s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1129 u16 words, u16 *data)
9a799d71
AK		 1130{
1131 u32 eerd;
68c7005d
ET		 1132 s32 status = 0;
1133 u32 i;
9a799d71 1134
c44ade9e
JB		 1135 hw->eeprom.ops.init_params(hw);
1136
68c7005d
ET		 1137 if (words == 0) {
1138 status = IXGBE_ERR_INVALID_ARGUMENT;
1139 goto out;
1140 }
1141
c44ade9e
JB		 1142 if (offset >= hw->eeprom.word_size) {
1143 status = IXGBE_ERR_EEPROM;
1144 goto out;
1145 }
1146
68c7005d 1147 for (i = 0; i < words; i++) {
d0111575 1148 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1149 IXGBE_EEPROM_RW_REG_START;
9a799d71 1150
68c7005d
ET		 1151 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1152 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1153
68c7005d
ET		 1154 if (status == 0) {
1155 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1156 IXGBE_EEPROM_RW_REG_DATA);
1157 } else {
1158 hw_dbg(hw, "Eeprom read timed out\n");
1159 goto out;
1160 }
1161 }
1162out:
1163 return status;
1164}
9a799d71 1165
68c7005d
ET		 1166/**
1167 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1168 * @hw: pointer to hardware structure
1169 * @offset: offset within the EEPROM to be used as a scratch pad
1170 *
1171 * Discover EEPROM page size by writing marching data at given offset.
1172 * This function is called only when we are writing a new large buffer
1173 * at given offset so the data would be overwritten anyway.
1174 **/
1175static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1176 u16 offset)
1177{
1178 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1179 s32 status = 0;
1180 u16 i;
1181
1182 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1183 data[i] = i;
1184
1185 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1186 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1187 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1188 hw->eeprom.word_page_size = 0;
1189 if (status != 0)
1190 goto out;
1191
1192 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1193 if (status != 0)
1194 goto out;
1195
1196 /*
1197 * When writing in burst more than the actual page size
1198 * EEPROM address wraps around current page.
1199 */
1200 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1201
c5ffe7e1 1202 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
68c7005d 1203 hw->eeprom.word_page_size);
c44ade9e 1204out:
9a799d71
AK		 1205 return status;
1206}
1207
eb9c3e3e 1208/**
68c7005d
ET		 1209 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1210 * @hw: pointer to hardware structure
1211 * @offset: offset of word in the EEPROM to read
1212 * @data: word read from the EEPROM
1213 *
1214 * Reads a 16 bit word from the EEPROM using the EERD register.
1215 **/
1216s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1217{
1218 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1219}
1220
1221/**
1222 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1223 * @hw: pointer to hardware structure
1224 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1225 * @words: number of words
1226 * @data: word(s) write to the EEPROM
eb9c3e3e 1227 *
68c7005d 1228 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1229 **/
68c7005d
ET		 1230s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1231 u16 words, u16 *data)
eb9c3e3e
ET		 1232{
1233 u32 eewr;
68c7005d
ET		 1234 s32 status = 0;
1235 u16 i;
eb9c3e3e
ET		 1236
1237 hw->eeprom.ops.init_params(hw);
1238
68c7005d
ET		 1239 if (words == 0) {
1240 status = IXGBE_ERR_INVALID_ARGUMENT;
1241 goto out;
1242 }
1243
eb9c3e3e
ET		 1244 if (offset >= hw->eeprom.word_size) {
1245 status = IXGBE_ERR_EEPROM;
1246 goto out;
1247 }
1248
68c7005d
ET		 1249 for (i = 0; i < words; i++) {
1250 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1251 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1252 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1253
68c7005d
ET		 1254 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1255 if (status != 0) {
1256 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1257 goto out;
1258 }
eb9c3e3e 1259
68c7005d 1260 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1261
68c7005d
ET		 1262 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1263 if (status != 0) {
1264 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1265 goto out;
1266 }
eb9c3e3e
ET		 1267 }
1268
1269out:
1270 return status;
1271}
1272
68c7005d
ET		 1273/**
1274 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1275 * @hw: pointer to hardware structure
1276 * @offset: offset of word in the EEPROM to write
1277 * @data: word write to the EEPROM
1278 *
1279 * Write a 16 bit word to the EEPROM using the EEWR register.
1280 **/
1281s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1282{
1283 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1284}
1285
9a799d71 1286/**
21ce849b 1287 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1288 * @hw: pointer to hardware structure
21ce849b 1289 * @ee_reg: EEPROM flag for polling
9a799d71 1290 *
21ce849b
MC		 1291 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1292 * read or write is done respectively.
9a799d71 1293 **/
eb9c3e3e 1294static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1295{
1296 u32 i;
1297 u32 reg;
1298 s32 status = IXGBE_ERR_EEPROM;
1299
21ce849b
MC		 1300 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1301 if (ee_reg == IXGBE_NVM_POLL_READ)
1302 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1303 else
1304 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1305
1306 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 1307 status = 0;
1308 break;
1309 }
1310 udelay(5);
1311 }
1312 return status;
1313}
1314
c44ade9e
JB		 1315/**
1316 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1317 * @hw: pointer to hardware structure
1318 *
1319 * Prepares EEPROM for access using bit-bang method. This function should
1320 * be called before issuing a command to the EEPROM.
1321 **/
1322static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1323{
1324 s32 status = 0;
dbf893ee 1325 u32 eec;
c44ade9e
JB		 1326 u32 i;
1327
5e655105 1328 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 1329 status = IXGBE_ERR_SWFW_SYNC;
1330
1331 if (status == 0) {
1332 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1333
1334 /* Request EEPROM Access */
1335 eec |= IXGBE_EEC_REQ;
1336 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1337
1338 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1339 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1340 if (eec & IXGBE_EEC_GNT)
1341 break;
1342 udelay(5);
1343 }
1344
1345 /* Release if grant not acquired */
1346 if (!(eec & IXGBE_EEC_GNT)) {
1347 eec &= ~IXGBE_EEC_REQ;
1348 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1349 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1350
5e655105 1351 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 1352 status = IXGBE_ERR_EEPROM;
1353 }
c44ade9e 1354
dbf893ee
ET		 1355 /* Setup EEPROM for Read/Write */
1356 if (status == 0) {
1357 /* Clear CS and SK */
1358 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1359 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1360 IXGBE_WRITE_FLUSH(hw);
1361 udelay(1);
1362 }
c44ade9e
JB		 1363 }
1364 return status;
1365}
1366
9a799d71
AK		 1367/**
1368 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1369 * @hw: pointer to hardware structure
1370 *
1371 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1372 **/
1373static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1374{
1375 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 1376 u32 timeout = 2000;
9a799d71
AK		 1377 u32 i;
1378 u32 swsm;
1379
9a799d71
AK		 1380 /* Get SMBI software semaphore between device drivers first */
1381 for (i = 0; i < timeout; i++) {
1382 /*
1383 * If the SMBI bit is 0 when we read it, then the bit will be
1384 * set and we have the semaphore
1385 */
1386 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1387 if (!(swsm & IXGBE_SWSM_SMBI)) {
1388 status = 0;
1389 break;
1390 }
dbf893ee 1391 udelay(50);
9a799d71
AK		 1392 }
1393
51275d37
ET		 1394 if (i == timeout) {
1395 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1396 "not granted.\n");
1397 /*
1398 * this release is particularly important because our attempts
1399 * above to get the semaphore may have succeeded, and if there
1400 * was a timeout, we should unconditionally clear the semaphore
1401 * bits to free the driver to make progress
1402 */
1403 ixgbe_release_eeprom_semaphore(hw);
1404
1405 udelay(50);
1406 /*
1407 * one last try
1408 * If the SMBI bit is 0 when we read it, then the bit will be
1409 * set and we have the semaphore
1410 */
1411 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1412 if (!(swsm & IXGBE_SWSM_SMBI))
1413 status = 0;
1414 }
1415
9a799d71
AK		 1416 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1417 if (status == 0) {
1418 for (i = 0; i < timeout; i++) {
1419 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1420
1421 /* Set the SW EEPROM semaphore bit to request access */
1422 swsm |= IXGBE_SWSM_SWESMBI;
1423 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1424
1425 /*
1426 * If we set the bit successfully then we got the
1427 * semaphore.
1428 */
1429 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1430 if (swsm & IXGBE_SWSM_SWESMBI)
1431 break;
1432
1433 udelay(50);
1434 }
1435
1436 /*
1437 * Release semaphores and return error if SW EEPROM semaphore
1438 * was not granted because we don't have access to the EEPROM
1439 */
1440 if (i >= timeout) {
dbf893ee 1441 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 1442 "not granted.\n");
9a799d71
AK		 1443 ixgbe_release_eeprom_semaphore(hw);
1444 status = IXGBE_ERR_EEPROM;
1445 }
dbf893ee
ET		 1446 } else {
1447 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1448 "not granted.\n");
9a799d71
AK		 1449 }
1450
1451 return status;
1452}
1453
1454/**
1455 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1456 * @hw: pointer to hardware structure
1457 *
1458 * This function clears hardware semaphore bits.
1459 **/
1460static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1461{
1462 u32 swsm;
1463
1464 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1465
1466 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1467 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1468 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1469 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1470}
1471
c44ade9e
JB		 1472/**
1473 * ixgbe_ready_eeprom - Polls for EEPROM ready
1474 * @hw: pointer to hardware structure
1475 **/
1476static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1477{
1478 s32 status = 0;
1479 u16 i;
1480 u8 spi_stat_reg;
1481
1482 /*
1483 * Read "Status Register" repeatedly until the LSB is cleared. The
1484 * EEPROM will signal that the command has been completed by clearing
1485 * bit 0 of the internal status register. If it's not cleared within
1486 * 5 milliseconds, then error out.
1487 */
1488 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1489 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
e7cf745b 1490 IXGBE_EEPROM_OPCODE_BITS);
c44ade9e
JB		 1491 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1492 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1493 break;
1494
1495 udelay(5);
1496 ixgbe_standby_eeprom(hw);
6403eab1 1497 }
c44ade9e
JB		 1498
1499 /*
1500 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1501 * devices (and only 0-5mSec on 5V devices)
1502 */
1503 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1504 hw_dbg(hw, "SPI EEPROM Status error\n");
1505 status = IXGBE_ERR_EEPROM;
1506 }
1507
1508 return status;
1509}
1510
1511/**
1512 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1513 * @hw: pointer to hardware structure
1514 **/
1515static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1516{
1517 u32 eec;
1518
1519 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1520
1521 /* Toggle CS to flush commands */
1522 eec |= IXGBE_EEC_CS;
1523 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1524 IXGBE_WRITE_FLUSH(hw);
1525 udelay(1);
1526 eec &= ~IXGBE_EEC_CS;
1527 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1528 IXGBE_WRITE_FLUSH(hw);
1529 udelay(1);
1530}
1531
1532/**
1533 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1534 * @hw: pointer to hardware structure
1535 * @data: data to send to the EEPROM
1536 * @count: number of bits to shift out
1537 **/
1538static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 1539 u16 count)
c44ade9e
JB		 1540{
1541 u32 eec;
1542 u32 mask;
1543 u32 i;
1544
1545 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1546
1547 /*
1548 * Mask is used to shift "count" bits of "data" out to the EEPROM
1549 * one bit at a time. Determine the starting bit based on count
1550 */
1551 mask = 0x01 << (count - 1);
1552
1553 for (i = 0; i < count; i++) {
1554 /*
1555 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1556 * "1", and then raising and then lowering the clock (the SK
1557 * bit controls the clock input to the EEPROM). A "0" is
1558 * shifted out to the EEPROM by setting "DI" to "0" and then
1559 * raising and then lowering the clock.
1560 */
1561 if (data & mask)
1562 eec |= IXGBE_EEC_DI;
1563 else
1564 eec &= ~IXGBE_EEC_DI;
1565
1566 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1567 IXGBE_WRITE_FLUSH(hw);
1568
1569 udelay(1);
1570
1571 ixgbe_raise_eeprom_clk(hw, &eec);
1572 ixgbe_lower_eeprom_clk(hw, &eec);
1573
1574 /*
1575 * Shift mask to signify next bit of data to shift in to the
1576 * EEPROM
1577 */
1578 mask = mask >> 1;
6403eab1 1579 }
c44ade9e
JB		 1580
1581 /* We leave the "DI" bit set to "0" when we leave this routine. */
1582 eec &= ~IXGBE_EEC_DI;
1583 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1584 IXGBE_WRITE_FLUSH(hw);
1585}
1586
1587/**
1588 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1589 * @hw: pointer to hardware structure
1590 **/
1591static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1592{
1593 u32 eec;
1594 u32 i;
1595 u16 data = 0;
1596
1597 /*
1598 * In order to read a register from the EEPROM, we need to shift
1599 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1600 * the clock input to the EEPROM (setting the SK bit), and then reading
1601 * the value of the "DO" bit. During this "shifting in" process the
1602 * "DI" bit should always be clear.
1603 */
1604 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1605
1606 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1607
1608 for (i = 0; i < count; i++) {
1609 data = data << 1;
1610 ixgbe_raise_eeprom_clk(hw, &eec);
1611
1612 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1613
1614 eec &= ~(IXGBE_EEC_DI);
1615 if (eec & IXGBE_EEC_DO)
1616 data |= 1;
1617
1618 ixgbe_lower_eeprom_clk(hw, &eec);
1619 }
1620
1621 return data;
1622}
1623
1624/**
1625 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1626 * @hw: pointer to hardware structure
1627 * @eec: EEC register's current value
1628 **/
1629static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1630{
1631 /*
1632 * Raise the clock input to the EEPROM
1633 * (setting the SK bit), then delay
1634 */
1635 *eec = *eec | IXGBE_EEC_SK;
1636 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1637 IXGBE_WRITE_FLUSH(hw);
1638 udelay(1);
1639}
1640
1641/**
1642 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1643 * @hw: pointer to hardware structure
1644 * @eecd: EECD's current value
1645 **/
1646static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1647{
1648 /*
1649 * Lower the clock input to the EEPROM (clearing the SK bit), then
1650 * delay
1651 */
1652 *eec = *eec & ~IXGBE_EEC_SK;
1653 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1654 IXGBE_WRITE_FLUSH(hw);
1655 udelay(1);
1656}
1657
1658/**
1659 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1660 * @hw: pointer to hardware structure
1661 **/
1662static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1663{
1664 u32 eec;
1665
1666 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1667
1668 eec |= IXGBE_EEC_CS; /* Pull CS high */
1669 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1670
1671 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1672 IXGBE_WRITE_FLUSH(hw);
1673
1674 udelay(1);
1675
1676 /* Stop requesting EEPROM access */
1677 eec &= ~IXGBE_EEC_REQ;
1678 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1679
90827996 1680 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1681
032b4325
DS		 1682 /*
1683 * Delay before attempt to obtain semaphore again to allow FW
1684 * access. semaphore_delay is in ms we need us for usleep_range
1685 */
1686 usleep_range(hw->eeprom.semaphore_delay * 1000,
1687 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1688}
1689
9a799d71 1690/**
dbf893ee 1691 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1692 * @hw: pointer to hardware structure
1693 **/
a391f1d5 1694u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1695{
1696 u16 i;
1697 u16 j;
1698 u16 checksum = 0;
1699 u16 length = 0;
1700 u16 pointer = 0;
1701 u16 word = 0;
1702
1703 /* Include 0x0-0x3F in the checksum */
1704 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1705 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1706 hw_dbg(hw, "EEPROM read failed\n");
1707 break;
1708 }
1709 checksum += word;
1710 }
1711
1712 /* Include all data from pointers except for the fw pointer */
1713 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1714 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1715
1716 /* Make sure the pointer seems valid */
1717 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1718 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1719
1720 if (length != 0xFFFF && length != 0) {
1721 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1722 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1723 checksum += word;
1724 }
1725 }
1726 }
1727 }
1728
1729 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1730
1731 return checksum;
1732}
1733
1734/**
c44ade9e 1735 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1736 * @hw: pointer to hardware structure
1737 * @checksum_val: calculated checksum
1738 *
1739 * Performs checksum calculation and validates the EEPROM checksum. If the
1740 * caller does not need checksum_val, the value can be NULL.
1741 **/
c44ade9e 1742s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 1743 u16 *checksum_val)
9a799d71
AK		 1744{
1745 s32 status;
1746 u16 checksum;
1747 u16 read_checksum = 0;
1748
1749 /*
1750 * Read the first word from the EEPROM. If this times out or fails, do
1751 * not continue or we could be in for a very long wait while every
1752 * EEPROM read fails
1753 */
c44ade9e 1754 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1755
1756 if (status == 0) {
a391f1d5 1757 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1758
c44ade9e 1759 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1760
1761 /*
1762 * Verify read checksum from EEPROM is the same as
1763 * calculated checksum
1764 */
1765 if (read_checksum != checksum)
1766 status = IXGBE_ERR_EEPROM_CHECKSUM;
1767
1768 /* If the user cares, return the calculated checksum */
1769 if (checksum_val)
1770 *checksum_val = checksum;
1771 } else {
1772 hw_dbg(hw, "EEPROM read failed\n");
1773 }
1774
1775 return status;
1776}
1777
c44ade9e
JB		 1778/**
1779 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1780 * @hw: pointer to hardware structure
1781 **/
1782s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1783{
1784 s32 status;
1785 u16 checksum;
1786
1787 /*
1788 * Read the first word from the EEPROM. If this times out or fails, do
1789 * not continue or we could be in for a very long wait while every
1790 * EEPROM read fails
1791 */
1792 status = hw->eeprom.ops.read(hw, 0, &checksum);
1793
1794 if (status == 0) {
a391f1d5 1795 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1796 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1797 checksum);
c44ade9e
JB		 1798 } else {
1799 hw_dbg(hw, "EEPROM read failed\n");
1800 }
1801
1802 return status;
1803}
1804
9a799d71 1805/**
c44ade9e 1806 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1807 * @hw: pointer to hardware structure
9a799d71 1808 * @index: Receive address register to write
c44ade9e
JB		 1809 * @addr: Address to put into receive address register
1810 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1811 * @enable_addr: set flag that address is active
1812 *
1813 * Puts an ethernet address into a receive address register.
1814 **/
c44ade9e 1815s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 1816 u32 enable_addr)
9a799d71
AK		 1817{
1818 u32 rar_low, rar_high;
c44ade9e
JB		 1819 u32 rar_entries = hw->mac.num_rar_entries;
1820
c700f4e6
ET		 1821 /* Make sure we are using a valid rar index range */
1822 if (index >= rar_entries) {
1823 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1824 return IXGBE_ERR_INVALID_ARGUMENT;
1825 }
1826
c44ade9e
JB		 1827 /* setup VMDq pool selection before this RAR gets enabled */
1828 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1829
c700f4e6
ET		 1830 /*
1831 * HW expects these in little endian so we reverse the byte
1832 * order from network order (big endian) to little endian
1833 */
1834 rar_low = ((u32)addr[0] |
1835 ((u32)addr[1] << 8) |
1836 ((u32)addr[2] << 16) |
1837 ((u32)addr[3] << 24));
1838 /*
1839 * Some parts put the VMDq setting in the extra RAH bits,
1840 * so save everything except the lower 16 bits that hold part
1841 * of the address and the address valid bit.
1842 */
1843 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1844 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1845 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1846
c700f4e6
ET		 1847 if (enable_addr != 0)
1848 rar_high |= IXGBE_RAH_AV;
9a799d71 1849
c700f4e6
ET		 1850 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1851 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1852
1853 return 0;
1854}
1855
1856/**
1857 * ixgbe_clear_rar_generic - Remove Rx address register
1858 * @hw: pointer to hardware structure
1859 * @index: Receive address register to write
1860 *
1861 * Clears an ethernet address from a receive address register.
1862 **/
1863s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1864{
1865 u32 rar_high;
1866 u32 rar_entries = hw->mac.num_rar_entries;
1867
1868 /* Make sure we are using a valid rar index range */
c700f4e6 1869 if (index >= rar_entries) {
c44ade9e 1870 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1871 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1872 }
1873
c700f4e6
ET		 1874 /*
1875 * Some parts put the VMDq setting in the extra RAH bits,
1876 * so save everything except the lower 16 bits that hold part
1877 * of the address and the address valid bit.
1878 */
1879 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1880 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1881
1882 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1883 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1884
c44ade9e
JB		 1885 /* clear VMDq pool/queue selection for this RAR */
1886 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1887
1888 return 0;
1889}
1890
c44ade9e
JB		 1891/**
1892 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1893 * @hw: pointer to hardware structure
1894 *
1895 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1896 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1897 * the receiver is in reset when the routine is called.
1898 **/
c44ade9e 1899s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1900{
1901 u32 i;
2c5645cf 1902 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1903
1904 /*
1905 * If the current mac address is valid, assume it is a software override
1906 * to the permanent address.
1907 * Otherwise, use the permanent address from the eeprom.
1908 */
f8ebc683 1909 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1910 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1911 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1912
ce7194d8 1913 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1914 } else {
1915 /* Setup the receive address. */
1916 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1917 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1918
c44ade9e 1919 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1920
1921 /* clear VMDq pool/queue selection for RAR 0 */
1922 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1923 }
c44ade9e 1924 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1925
1926 hw->addr_ctrl.rar_used_count = 1;
1927
1928 /* Zero out the other receive addresses. */
c44ade9e 1929 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1930 for (i = 1; i < rar_entries; i++) {
1931 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1932 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1933 }
1934
1935 /* Clear the MTA */
9a799d71
AK		 1936 hw->addr_ctrl.mta_in_use = 0;
1937 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1938
1939 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1940 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1941 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1942
c44ade9e
JB		 1943 if (hw->mac.ops.init_uta_tables)
1944 hw->mac.ops.init_uta_tables(hw);
1945
9a799d71
AK		 1946 return 0;
1947}
1948
1949/**
1950 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1951 * @hw: pointer to hardware structure
1952 * @mc_addr: the multicast address
1953 *
1954 * Extracts the 12 bits, from a multicast address, to determine which
1955 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1956 * incoming rx multicast addresses, to determine the bit-vector to check in
1957 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1958 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1959 * to mc_filter_type.
1960 **/
1961static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1962{
1963 u32 vector = 0;
1964
1965 switch (hw->mac.mc_filter_type) {
b4617240 1966 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1967 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1968 break;
b4617240 1969 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1970 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1971 break;
b4617240 1972 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1973 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1974 break;
b4617240 1975 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1976 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1977 break;
b4617240 1978 default: /* Invalid mc_filter_type */
9a799d71
AK		 1979 hw_dbg(hw, "MC filter type param set incorrectly\n");
1980 break;
1981 }
1982
1983 /* vector can only be 12-bits or boundary will be exceeded */
1984 vector &= 0xFFF;
1985 return vector;
1986}
1987
1988/**
1989 * ixgbe_set_mta - Set bit-vector in multicast table
1990 * @hw: pointer to hardware structure
1991 * @hash_value: Multicast address hash value
1992 *
1993 * Sets the bit-vector in the multicast table.
1994 **/
1995static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1996{
1997 u32 vector;
1998 u32 vector_bit;
1999 u32 vector_reg;
9a799d71
AK		 2000
2001 hw->addr_ctrl.mta_in_use++;
2002
2003 vector = ixgbe_mta_vector(hw, mc_addr);
2004 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2005
2006 /*
2007 * The MTA is a register array of 128 32-bit registers. It is treated
2008 * like an array of 4096 bits. We want to set bit
2009 * BitArray[vector_value]. So we figure out what register the bit is
2010 * in, read it, OR in the new bit, then write back the new value. The
2011 * register is determined by the upper 7 bits of the vector value and
2012 * the bit within that register are determined by the lower 5 bits of
2013 * the value.
2014 */
2015 vector_reg = (vector >> 5) & 0x7F;
2016 vector_bit = vector & 0x1F;
80960ab0 2017 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 2018}
2019
9a799d71 2020/**
c44ade9e 2021 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 2022 * @hw: pointer to hardware structure
2853eb89 2023 * @netdev: pointer to net device structure
9a799d71
AK		 2024 *
2025 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 2026 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 2027 * registers for the first multicast addresses, and hashes the rest into the
2028 * multicast table.
2029 **/
2853eb89
JP		 2030s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2031 struct net_device *netdev)
9a799d71 2032{
22bedad3 2033 struct netdev_hw_addr *ha;
9a799d71 2034 u32 i;
9a799d71
AK		 2035
2036 /*
2037 * Set the new number of MC addresses that we are being requested to
2038 * use.
2039 */
2853eb89 2040 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2041 hw->addr_ctrl.mta_in_use = 0;
2042
80960ab0 2043 /* Clear mta_shadow */
9a799d71 2044 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2045 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2046
80960ab0 2047 /* Update mta shadow */
22bedad3 2048 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2049 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2050 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2051 }
2052
2053 /* Enable mta */
80960ab0
ET		 2054 for (i = 0; i < hw->mac.mcft_size; i++)
2055 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2056 hw->mac.mta_shadow[i]);
2057
9a799d71
AK		 2058 if (hw->addr_ctrl.mta_in_use > 0)
2059 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
e7cf745b 2060 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2061
c44ade9e 2062 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2063 return 0;
2064}
2065
2066/**
c44ade9e 2067 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2068 * @hw: pointer to hardware structure
2069 *
c44ade9e 2070 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2071 **/
c44ade9e 2072s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2073{
c44ade9e 2074 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2075
c44ade9e
JB		 2076 if (a->mta_in_use > 0)
2077 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
e7cf745b 2078 hw->mac.mc_filter_type);
9a799d71
AK		 2079
2080 return 0;
2081}
2082
2083/**
c44ade9e 2084 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2085 * @hw: pointer to hardware structure
9a799d71 2086 *
c44ade9e 2087 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2088 **/
c44ade9e 2089s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2090{
c44ade9e 2091 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2092
c44ade9e
JB		 2093 if (a->mta_in_use > 0)
2094 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2095
2096 return 0;
2097}
2098
11afc1b1 2099/**
620fa036 2100 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2101 * @hw: pointer to hardware structure
11afc1b1
PW		 2102 *
2103 * Enable flow control according to the current settings.
2104 **/
041441d0 2105s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1
PW		 2106{
2107 s32 ret_val = 0;
620fa036 2108 u32 mflcn_reg, fccfg_reg;
11afc1b1 2109 u32 reg;
16b61beb 2110 u32 fcrtl, fcrth;
041441d0 2111 int i;
70b77628 2112
e5776620
JK		 2113 /* Validate the water mark configuration. */
2114 if (!hw->fc.pause_time) {
041441d0 2115 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2116 goto out;
041441d0 2117 }
70b77628 2118
e5776620
JK		 2119 /* Low water mark of zero causes XOFF floods */
2120 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2121 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2122 hw->fc.high_water[i]) {
2123 if (!hw->fc.low_water[i] ||
2124 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2125 hw_dbg(hw, "Invalid water mark configuration\n");
2126 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2127 goto out;
2128 }
2129 }
2130 }
2131
620fa036 2132 /* Negotiate the fc mode to use */
786e9a5f 2133 ixgbe_fc_autoneg(hw);
11afc1b1 2134
620fa036 2135 /* Disable any previous flow control settings */
11afc1b1 2136 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2137 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2138
2139 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2140 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2141
2142 /*
2143 * The possible values of fc.current_mode are:
2144 * 0: Flow control is completely disabled
2145 * 1: Rx flow control is enabled (we can receive pause frames,
2146 * but not send pause frames).
bb3daa4a
PW		 2147 * 2: Tx flow control is enabled (we can send pause frames but
2148 * we do not support receiving pause frames).
11afc1b1
PW		 2149 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2150 * other: Invalid.
2151 */
2152 switch (hw->fc.current_mode) {
2153 case ixgbe_fc_none:
620fa036
MC		 2154 /*
2155 * Flow control is disabled by software override or autoneg.
2156 * The code below will actually disable it in the HW.
2157 */
11afc1b1
PW		 2158 break;
2159 case ixgbe_fc_rx_pause:
2160 /*
2161 * Rx Flow control is enabled and Tx Flow control is
2162 * disabled by software override. Since there really
2163 * isn't a way to advertise that we are capable of RX
2164 * Pause ONLY, we will advertise that we support both
2165 * symmetric and asymmetric Rx PAUSE. Later, we will
2166 * disable the adapter's ability to send PAUSE frames.
2167 */
2168 mflcn_reg |= IXGBE_MFLCN_RFCE;
2169 break;
2170 case ixgbe_fc_tx_pause:
2171 /*
2172 * Tx Flow control is enabled, and Rx Flow control is
2173 * disabled by software override.
2174 */
2175 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2176 break;
2177 case ixgbe_fc_full:
2178 /* Flow control (both Rx and Tx) is enabled by SW override. */
2179 mflcn_reg |= IXGBE_MFLCN_RFCE;
2180 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2181 break;
2182 default:
2183 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2184 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 2185 goto out;
2186 break;
2187 }
2188
620fa036 2189 /* Set 802.3x based flow control settings. */
2132d381 2190 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2191 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2192 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2193
041441d0
AD		 2194 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2195 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2196 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2197 hw->fc.high_water[i]) {
e5776620 2198 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
041441d0
AD		 2199 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2200 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2201 } else {
2202 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2203 /*
2204 * In order to prevent Tx hangs when the internal Tx
2205 * switch is enabled we must set the high water mark
2206 * to the maximum FCRTH value. This allows the Tx
2207 * switch to function even under heavy Rx workloads.
2208 */
2209 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2210 }
11afc1b1 2211
041441d0
AD		 2212 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2213 }
16b61beb 2214
11afc1b1 2215 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2216 reg = hw->fc.pause_time * 0x00010001;
2217 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2218 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2219
2220 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1
PW		 2221
2222out:
2223 return ret_val;
2224}
2225
0ecc061d 2226/**
67a79df2 2227 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2228 * @hw: pointer to hardware structure
67a79df2
AD		 2229 * @adv_reg: flow control advertised settings
2230 * @lp_reg: link partner's flow control settings
2231 * @adv_sym: symmetric pause bit in advertisement
2232 * @adv_asm: asymmetric pause bit in advertisement
2233 * @lp_sym: symmetric pause bit in link partner advertisement
2234 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2235 *
67a79df2
AD		 2236 * Find the intersection between advertised settings and link partner's
2237 * advertised settings
0ecc061d 2238 **/
67a79df2
AD		 2239static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2240 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2241{
67a79df2
AD		 2242 if ((!(adv_reg)) || (!(lp_reg)))
2243 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2244
67a79df2
AD		 2245 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2246 /*
2247 * Now we need to check if the user selected Rx ONLY
2248 * of pause frames. In this case, we had to advertise
2249 * FULL flow control because we could not advertise RX
2250 * ONLY. Hence, we must now check to see if we need to
2251 * turn OFF the TRANSMISSION of PAUSE frames.
2252 */
2253 if (hw->fc.requested_mode == ixgbe_fc_full) {
2254 hw->fc.current_mode = ixgbe_fc_full;
2255 hw_dbg(hw, "Flow Control = FULL.\n");
2256 } else {
2257 hw->fc.current_mode = ixgbe_fc_rx_pause;
2258 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2259 }
2260 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2261 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2262 hw->fc.current_mode = ixgbe_fc_tx_pause;
2263 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2264 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2265 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2266 hw->fc.current_mode = ixgbe_fc_rx_pause;
2267 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2268 } else {
67a79df2
AD		 2269 hw->fc.current_mode = ixgbe_fc_none;
2270 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2271 }
67a79df2 2272 return 0;
0b0c2b31
ET		 2273}
2274
2275/**
2276 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2277 * @hw: pointer to hardware structure
2278 *
2279 * Enable flow control according on 1 gig fiber.
2280 **/
2281static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2282{
2283 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
786e9a5f 2284 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02
PWJ		 2285
2286 /*
2287 * On multispeed fiber at 1g, bail out if
2288 * - link is up but AN did not complete, or if
2289 * - link is up and AN completed but timed out
2290 */
0b0c2b31
ET		 2291
2292 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2293 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2294 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
0b0c2b31 2295 goto out;
539e5f02 2296
0b0c2b31
ET		 2297 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2298 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2299
2300 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2301 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2302 IXGBE_PCS1GANA_ASM_PAUSE,
2303 IXGBE_PCS1GANA_SYM_PAUSE,
2304 IXGBE_PCS1GANA_ASM_PAUSE);
2305
2306out:
2307 return ret_val;
2308}
2309
2310/**
2311 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2312 * @hw: pointer to hardware structure
2313 *
2314 * Enable flow control according to IEEE clause 37.
2315 **/
2316static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2317{
2318 u32 links2, anlp1_reg, autoc_reg, links;
786e9a5f 2319 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2320
9bbe3a57 2321 /*
0b0c2b31
ET		 2322 * On backplane, bail out if
2323 * - backplane autoneg was not completed, or if
2324 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2325 */
0b0c2b31 2326 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2327 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
9bbe3a57 2328 goto out;
9bbe3a57 2329
0b0c2b31
ET		 2330 if (hw->mac.type == ixgbe_mac_82599EB) {
2331 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2332 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
0b0c2b31 2333 goto out;
0b0c2b31 2334 }
0ecc061d 2335 /*
0b0c2b31 2336 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2337 * local flow control settings accordingly
2338 */
0b0c2b31
ET		 2339 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2340 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2341
0b0c2b31
ET		 2342 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2343 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2344 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2345
2346out:
2347 return ret_val;
2348}
2349
2350/**
2351 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2352 * @hw: pointer to hardware structure
2353 *
2354 * Enable flow control according to IEEE clause 37.
2355 **/
2356static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2357{
2358 u16 technology_ability_reg = 0;
2359 u16 lp_technology_ability_reg = 0;
2360
2361 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2362 MDIO_MMD_AN,
2363 &technology_ability_reg);
2364 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2365 MDIO_MMD_AN,
2366 &lp_technology_ability_reg);
2367
2368 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2369 (u32)lp_technology_ability_reg,
2370 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2371 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2372}
2373
2374/**
67a79df2 2375 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2376 * @hw: pointer to hardware structure
2377 *
67a79df2
AD		 2378 * Compares our advertised flow control capabilities to those advertised by
2379 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2380 **/
67a79df2 2381void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2382{
67a79df2
AD		 2383 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2384 ixgbe_link_speed speed;
2385 bool link_up;
11afc1b1
PW		 2386
2387 /*
67a79df2
AD		 2388 * AN should have completed when the cable was plugged in.
2389 * Look for reasons to bail out. Bail out if:
2390 * - FC autoneg is disabled, or if
2391 * - link is not up.
2392 *
2393 * Since we're being called from an LSC, link is already known to be up.
2394 * So use link_up_wait_to_complete=false.
11afc1b1 2395 */
67a79df2 2396 if (hw->fc.disable_fc_autoneg)
620fa036 2397 goto out;
11afc1b1 2398
67a79df2
AD		 2399 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2400 if (!link_up)
11afc1b1 2401 goto out;
0b0c2b31
ET		 2402
2403 switch (hw->phy.media_type) {
67a79df2 2404 /* Autoneg flow control on fiber adapters */
0b0c2b31 2405 case ixgbe_media_type_fiber:
67a79df2
AD		 2406 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2407 ret_val = ixgbe_fc_autoneg_fiber(hw);
2408 break;
2409
2410 /* Autoneg flow control on backplane adapters */
0b0c2b31 2411 case ixgbe_media_type_backplane:
67a79df2 2412 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2413 break;
2414
67a79df2 2415 /* Autoneg flow control on copper adapters */
0b0c2b31 2416 case ixgbe_media_type_copper:
73d80953 2417 if (ixgbe_device_supports_autoneg_fc(hw))
67a79df2 2418 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2419 break;
2420
2421 default:
620fa036 2422 break;
0b0c2b31 2423 }
539e5f02 2424
11afc1b1 2425out:
67a79df2
AD		 2426 if (ret_val == 0) {
2427 hw->fc.fc_was_autonegged = true;
2428 } else {
2429 hw->fc.fc_was_autonegged = false;
2430 hw->fc.current_mode = hw->fc.requested_mode;
2431 }
11afc1b1
PW		 2432}
2433
1f86c983
DS		 2434/**
2435 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2436 * @hw: pointer to hardware structure
2437 *
2438 * System-wide timeout range is encoded in PCIe Device Control2 register.
2439 *
2440 * Add 10% to specified maximum and return the number of times to poll for
2441 * completion timeout, in units of 100 microsec. Never return less than
2442 * 800 = 80 millisec.
2443 **/
2444static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2445{
1f86c983
DS		 2446 s16 devctl2;
2447 u32 pollcnt;
2448
0d7c6e00 2449 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
1f86c983
DS		 2450 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2451
2452 switch (devctl2) {
2453 case IXGBE_PCIDEVCTRL2_65_130ms:
2454 pollcnt = 1300; /* 130 millisec */
2455 break;
2456 case IXGBE_PCIDEVCTRL2_260_520ms:
2457 pollcnt = 5200; /* 520 millisec */
2458 break;
2459 case IXGBE_PCIDEVCTRL2_1_2s:
2460 pollcnt = 20000; /* 2 sec */
2461 break;
2462 case IXGBE_PCIDEVCTRL2_4_8s:
2463 pollcnt = 80000; /* 8 sec */
2464 break;
2465 case IXGBE_PCIDEVCTRL2_17_34s:
2466 pollcnt = 34000; /* 34 sec */
2467 break;
2468 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2469 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2470 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2471 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2472 default:
2473 pollcnt = 800; /* 80 millisec minimum */
2474 break;
2475 }
2476
2477 /* add 10% to spec maximum */
2478 return (pollcnt * 11) / 10;
2479}
2480
9a799d71
AK		 2481/**
2482 * ixgbe_disable_pcie_master - Disable PCI-express master access
2483 * @hw: pointer to hardware structure
2484 *
2485 * Disables PCI-Express master access and verifies there are no pending
2486 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2487 * bit hasn't caused the master requests to be disabled, else 0
2488 * is returned signifying master requests disabled.
2489 **/
ff9d1a5a 2490static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2491{
a4297dc2 2492 s32 status = 0;
1f86c983 2493 u32 i, poll;
ff9d1a5a
ET		 2494 u16 value;
2495
2496 /* Always set this bit to ensure any future transactions are blocked */
2497 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2498
ff9d1a5a 2499 /* Exit if master requests are blocked */
14438464
MR		 2500 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2501 ixgbe_removed(hw->hw_addr))
a4297dc2 2502 goto out;
9a799d71 2503
ff9d1a5a 2504 /* Poll for master request bit to clear */
9a799d71 2505 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2506 udelay(100);
ff9d1a5a
ET		 2507 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2508 goto out;
a4297dc2
ET		 2509 }
2510
ff9d1a5a
ET		 2511 /*
2512 * Two consecutive resets are required via CTRL.RST per datasheet
2513 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2514 * of this need. The first reset prevents new master requests from
2515 * being issued by our device. We then must wait 1usec or more for any
2516 * remaining completions from the PCIe bus to trickle in, and then reset
2517 * again to clear out any effects they may have had on our device.
2518 */
a4297dc2 2519 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2520 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2521
2522 /*
2523 * Before proceeding, make sure that the PCIe block does not have
2524 * transactions pending.
2525 */
1f86c983
DS		 2526 poll = ixgbe_pcie_timeout_poll(hw);
2527 for (i = 0; i < poll; i++) {
9a799d71 2528 udelay(100);
14438464
MR		 2529 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2530 if (ixgbe_removed(hw->hw_addr))
2531 goto out;
ff9d1a5a
ET		 2532 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2533 goto out;
9a799d71
AK		 2534 }
2535
ff9d1a5a
ET		 2536 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2537 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
a4297dc2
ET		 2538
2539out:
9a799d71
AK		 2540 return status;
2541}
2542
9a799d71 2543/**
c44ade9e 2544 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2545 * @hw: pointer to hardware structure
c44ade9e 2546 * @mask: Mask to specify which semaphore to acquire
9a799d71 2547 *
da74cd4a 2548 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2549 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2550 **/
2551s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2552{
674c18b2 2553 u32 gssr = 0;
9a799d71
AK		 2554 u32 swmask = mask;
2555 u32 fwmask = mask << 5;
674c18b2
ET		 2556 u32 timeout = 200;
2557 u32 i;
9a799d71 2558
674c18b2 2559 for (i = 0; i < timeout; i++) {
dbf893ee 2560 /*
674c18b2
ET		 2561 * SW NVM semaphore bit is used for access to all
2562 * SW_FW_SYNC bits (not just NVM)
dbf893ee 2563 */
9a799d71 2564 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2565 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2566
2567 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
674c18b2
ET		 2568 if (!(gssr & (fwmask | swmask))) {
2569 gssr |= swmask;
2570 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2571 ixgbe_release_eeprom_semaphore(hw);
2572 return 0;
2573 } else {
2574 /* Resource is currently in use by FW or SW */
2575 ixgbe_release_eeprom_semaphore(hw);
2576 usleep_range(5000, 10000);
2577 }
9a799d71
AK		 2578 }
2579
674c18b2
ET		 2580 /* If time expired clear the bits holding the lock and retry */
2581 if (gssr & (fwmask | swmask))
2582 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
9a799d71 2583
674c18b2
ET		 2584 usleep_range(5000, 10000);
2585 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2586}
2587
2588/**
2589 * ixgbe_release_swfw_sync - Release SWFW semaphore
2590 * @hw: pointer to hardware structure
c44ade9e 2591 * @mask: Mask to specify which semaphore to release
9a799d71 2592 *
da74cd4a 2593 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2594 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2595 **/
2596void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2597{
2598 u32 gssr;
2599 u32 swmask = mask;
2600
2601 ixgbe_get_eeprom_semaphore(hw);
2602
2603 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2604 gssr &= ~swmask;
2605 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2606
2607 ixgbe_release_eeprom_semaphore(hw);
2608}
2609
429d6a3b
DS		 2610/**
2611 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2612 * @hw: pointer to hardware structure
2613 * @reg_val: Value we read from AUTOC
2614 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2615 * true in this the generic case.
2616 *
2617 * The default case requires no protection so just to the register read.
2618 **/
2619s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2620{
2621 *locked = false;
2622 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2623 return 0;
2624}
2625
2626/**
2627 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2628 * @hw: pointer to hardware structure
2629 * @reg_val: value to write to AUTOC
2630 * @locked: bool to indicate whether the SW/FW lock was already taken by
2631 * previous read.
2632 **/
2633s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2634{
2635 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2636 return 0;
2637}
2638
d2f5e7f3
AS		 2639/**
2640 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2641 * @hw: pointer to hardware structure
2642 *
2643 * Stops the receive data path and waits for the HW to internally
2644 * empty the Rx security block.
2645 **/
2646s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2647{
2648#define IXGBE_MAX_SECRX_POLL 40
2649 int i;
2650 int secrxreg;
2651
2652 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2653 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2654 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2655 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2656 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2657 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2658 break;
2659 else
2660 /* Use interrupt-safe sleep just in case */
db76ad47 2661 udelay(1000);
d2f5e7f3
AS		 2662 }
2663
2664 /* For informational purposes only */
2665 if (i >= IXGBE_MAX_SECRX_POLL)
2666 hw_dbg(hw, "Rx unit being enabled before security "
2667 "path fully disabled. Continuing with init.\n");
2668
2669 return 0;
2670
2671}
2672
2673/**
2674 * ixgbe_enable_rx_buff - Enables the receive data path
2675 * @hw: pointer to hardware structure
2676 *
2677 * Enables the receive data path
2678 **/
2679s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2680{
2681 int secrxreg;
2682
2683 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2684 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2685 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2686 IXGBE_WRITE_FLUSH(hw);
2687
2688 return 0;
2689}
2690
11afc1b1
PW		 2691/**
2692 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2693 * @hw: pointer to hardware structure
2694 * @regval: register value to write to RXCTRL
2695 *
2696 * Enables the Rx DMA unit
2697 **/
2698s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2699{
2700 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2701
2702 return 0;
2703}
87c12017
PW		 2704
2705/**
2706 * ixgbe_blink_led_start_generic - Blink LED based on index.
2707 * @hw: pointer to hardware structure
2708 * @index: led number to blink
2709 **/
2710s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2711{
2712 ixgbe_link_speed speed = 0;
3db1cd5c 2713 bool link_up = false;
87c12017
PW		 2714 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2715 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
d7bbcd32 2716 s32 ret_val = 0;
429d6a3b 2717 bool locked = false;
87c12017
PW		 2718
2719 /*
2720 * Link must be up to auto-blink the LEDs;
2721 * Force it if link is down.
2722 */
2723 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2724
2725 if (!link_up) {
429d6a3b 2726 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2727 if (ret_val)
429d6a3b 2728 goto out;
d7bbcd32 2729
50ac58ba 2730 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2731 autoc_reg |= IXGBE_AUTOC_FLU;
429d6a3b
DS		 2732
2733 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2734 if (ret_val)
429d6a3b
DS		 2735 goto out;
2736
945a5151 2737 IXGBE_WRITE_FLUSH(hw);
d7bbcd32 2738
032b4325 2739 usleep_range(10000, 20000);
87c12017
PW		 2740 }
2741
2742 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2743 led_reg |= IXGBE_LED_BLINK(index);
2744 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2745 IXGBE_WRITE_FLUSH(hw);
2746
d7bbcd32
DS		 2747out:
2748 return ret_val;
87c12017
PW		 2749}
2750
2751/**
2752 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2753 * @hw: pointer to hardware structure
2754 * @index: led number to stop blinking
2755 **/
2756s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2757{
429d6a3b 2758 u32 autoc_reg = 0;
87c12017 2759 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
d7bbcd32 2760 s32 ret_val = 0;
429d6a3b 2761 bool locked = false;
d7bbcd32 2762
429d6a3b 2763 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2764 if (ret_val)
429d6a3b 2765 goto out;
87c12017
PW		 2766
2767 autoc_reg &= ~IXGBE_AUTOC_FLU;
2768 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2769
429d6a3b 2770 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2771 if (ret_val)
429d6a3b 2772 goto out;
d7bbcd32 2773
87c12017
PW		 2774 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2775 led_reg &= ~IXGBE_LED_BLINK(index);
2776 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2777 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2778 IXGBE_WRITE_FLUSH(hw);
2779
d7bbcd32
DS		 2780out:
2781 return ret_val;
87c12017 2782}
21ce849b
MC		 2783
2784/**
2785 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2786 * @hw: pointer to hardware structure
2787 * @san_mac_offset: SAN MAC address offset
2788 *
2789 * This function will read the EEPROM location for the SAN MAC address
2790 * pointer, and returns the value at that location. This is used in both
2791 * get and set mac_addr routines.
2792 **/
2793static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
e7cf745b 2794 u16 *san_mac_offset)
21ce849b 2795{
be0c27b4
MR		 2796 s32 ret_val;
2797
21ce849b
MC		 2798 /*
2799 * First read the EEPROM pointer to see if the MAC addresses are
2800 * available.
2801 */
be0c27b4
MR		 2802 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2803 san_mac_offset);
2804 if (ret_val)
2805 hw_err(hw, "eeprom read at offset %d failed\n",
2806 IXGBE_SAN_MAC_ADDR_PTR);
21ce849b 2807
be0c27b4 2808 return ret_val;
21ce849b
MC		 2809}
2810
2811/**
2812 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2813 * @hw: pointer to hardware structure
2814 * @san_mac_addr: SAN MAC address
2815 *
2816 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2817 * per-port, so set_lan_id() must be called before reading the addresses.
2818 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2819 * upon for non-SFP connections, so we must call it here.
2820 **/
2821s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2822{
2823 u16 san_mac_data, san_mac_offset;
2824 u8 i;
be0c27b4 2825 s32 ret_val;
21ce849b
MC		 2826
2827 /*
2828 * First read the EEPROM pointer to see if the MAC addresses are
2829 * available. If they're not, no point in calling set_lan_id() here.
2830 */
be0c27b4
MR		 2831 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2832 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
21ce849b 2833
be0c27b4 2834 goto san_mac_addr_clr;
21ce849b
MC		 2835
2836 /* make sure we know which port we need to program */
2837 hw->mac.ops.set_lan_id(hw);
2838 /* apply the port offset to the address offset */
2839 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
e7cf745b 2840 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
21ce849b 2841 for (i = 0; i < 3; i++) {
be0c27b4
MR		 2842 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2843 &san_mac_data);
2844 if (ret_val) {
2845 hw_err(hw, "eeprom read at offset %d failed\n",
2846 san_mac_offset);
2847 goto san_mac_addr_clr;
2848 }
21ce849b
MC		 2849 san_mac_addr[i * 2] = (u8)(san_mac_data);
2850 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2851 san_mac_offset++;
2852 }
21ce849b 2853 return 0;
be0c27b4
MR		 2854
2855san_mac_addr_clr:
2856 /* No addresses available in this EEPROM. It's not necessarily an
2857 * error though, so just wipe the local address and return.
2858 */
2859 for (i = 0; i < 6; i++)
2860 san_mac_addr[i] = 0xFF;
2861 return ret_val;
21ce849b
MC		 2862}
2863
2864/**
2865 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2866 * @hw: pointer to hardware structure
2867 *
2868 * Read PCIe configuration space, and get the MSI-X vector count from
2869 * the capabilities table.
2870 **/
71161302 2871u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b 2872{
71161302
ET		 2873 u16 msix_count = 1;
2874 u16 max_msix_count;
2875 u16 pcie_offset;
2876
2877 switch (hw->mac.type) {
2878 case ixgbe_mac_82598EB:
2879 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2880 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2881 break;
2882 case ixgbe_mac_82599EB:
2883 case ixgbe_mac_X540:
2884 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2885 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2886 break;
2887 default:
2888 return msix_count;
2889 }
2890
14438464
MR		 2891 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2892 if (ixgbe_removed(hw->hw_addr))
2893 msix_count = 0;
21ce849b
MC		 2894 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2895
71161302 2896 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2897 msix_count++;
2898
71161302
ET		 2899 if (msix_count > max_msix_count)
2900 msix_count = max_msix_count;
2901
21ce849b
MC		 2902 return msix_count;
2903}
2904
2905/**
2906 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2907 * @hw: pointer to hardware struct
2908 * @rar: receive address register index to disassociate
2909 * @vmdq: VMDq pool index to remove from the rar
2910 **/
2911s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2912{
2913 u32 mpsar_lo, mpsar_hi;
2914 u32 rar_entries = hw->mac.num_rar_entries;
2915
c700f4e6
ET		 2916 /* Make sure we are using a valid rar index range */
2917 if (rar >= rar_entries) {
2918 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2919 return IXGBE_ERR_INVALID_ARGUMENT;
2920 }
21ce849b 2921
c700f4e6
ET		 2922 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2923 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2924
19458bd4
MR		 2925 if (ixgbe_removed(hw->hw_addr))
2926 goto done;
2927
c700f4e6
ET		 2928 if (!mpsar_lo && !mpsar_hi)
2929 goto done;
21ce849b 2930
c700f4e6
ET		 2931 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2932 if (mpsar_lo) {
2933 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2934 mpsar_lo = 0;
2935 }
2936 if (mpsar_hi) {
2937 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2938 mpsar_hi = 0;
2939 }
2940 } else if (vmdq < 32) {
2941 mpsar_lo &= ~(1 << vmdq);
2942 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2943 } else {
c700f4e6
ET		 2944 mpsar_hi &= ~(1 << (vmdq - 32));
2945 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2946 }
2947
c700f4e6
ET		 2948 /* was that the last pool using this rar? */
2949 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2950 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2951done:
2952 return 0;
2953}
2954
2955/**
2956 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2957 * @hw: pointer to hardware struct
2958 * @rar: receive address register index to associate with a VMDq index
2959 * @vmdq: VMDq pool index
2960 **/
2961s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2962{
2963 u32 mpsar;
2964 u32 rar_entries = hw->mac.num_rar_entries;
2965
c700f4e6
ET		 2966 /* Make sure we are using a valid rar index range */
2967 if (rar >= rar_entries) {
21ce849b 2968 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2969 return IXGBE_ERR_INVALID_ARGUMENT;
2970 }
2971
2972 if (vmdq < 32) {
2973 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2974 mpsar |= 1 << vmdq;
2975 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2976 } else {
2977 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2978 mpsar |= 1 << (vmdq - 32);
2979 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2980 }
2981 return 0;
2982}
2983
7fa7c9dc
AD		 2984/**
2985 * This function should only be involved in the IOV mode.
2986 * In IOV mode, Default pool is next pool after the number of
2987 * VFs advertized and not 0.
2988 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2989 *
2990 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2991 * @hw: pointer to hardware struct
2992 * @vmdq: VMDq pool index
2993 **/
2994s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2995{
2996 u32 rar = hw->mac.san_mac_rar_index;
2997
2998 if (vmdq < 32) {
2999 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3000 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3001 } else {
3002 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3003 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3004 }
3005
3006 return 0;
3007}
3008
21ce849b
MC		 3009/**
3010 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3011 * @hw: pointer to hardware structure
3012 **/
3013s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3014{
3015 int i;
3016
21ce849b
MC		 3017 for (i = 0; i < 128; i++)
3018 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3019
3020 return 0;
3021}
3022
3023/**
3024 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3025 * @hw: pointer to hardware structure
3026 * @vlan: VLAN id to write to VLAN filter
3027 *
3028 * return the VLVF index where this VLAN id should be placed
3029 *
3030 **/
5d5b7c39 3031static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 3032{
3033 u32 bits = 0;
3034 u32 first_empty_slot = 0;
3035 s32 regindex;
3036
3037 /* short cut the special case */
3038 if (vlan == 0)
3039 return 0;
3040
3041 /*
3042 * Search for the vlan id in the VLVF entries. Save off the first empty
3043 * slot found along the way
3044 */
3045 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3046 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3047 if (!bits && !(first_empty_slot))
3048 first_empty_slot = regindex;
3049 else if ((bits & 0x0FFF) == vlan)
3050 break;
3051 }
3052
3053 /*
3054 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3055 * in the VLVF. Else use the first empty VLVF register for this
3056 * vlan id.
3057 */
3058 if (regindex >= IXGBE_VLVF_ENTRIES) {
3059 if (first_empty_slot)
3060 regindex = first_empty_slot;
3061 else {
3062 hw_dbg(hw, "No space in VLVF.\n");
3063 regindex = IXGBE_ERR_NO_SPACE;
3064 }
3065 }
3066
3067 return regindex;
3068}
3069
3070/**
3071 * ixgbe_set_vfta_generic - Set VLAN filter table
3072 * @hw: pointer to hardware structure
3073 * @vlan: VLAN id to write to VLAN filter
3074 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3075 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3076 *
3077 * Turn on/off specified VLAN in the VLAN filter table.
3078 **/
3079s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
e7cf745b 3080 bool vlan_on)
21ce849b
MC		 3081{
3082 s32 regindex;
3083 u32 bitindex;
3084 u32 vfta;
3085 u32 bits;
3086 u32 vt;
3087 u32 targetbit;
3088 bool vfta_changed = false;
3089
3090 if (vlan > 4095)
3091 return IXGBE_ERR_PARAM;
3092
3093 /*
3094 * this is a 2 part operation - first the VFTA, then the
3095 * VLVF and VLVFB if VT Mode is set
3096 * We don't write the VFTA until we know the VLVF part succeeded.
3097 */
3098
3099 /* Part 1
3100 * The VFTA is a bitstring made up of 128 32-bit registers
3101 * that enable the particular VLAN id, much like the MTA:
3102 * bits[11-5]: which register
3103 * bits[4-0]: which bit in the register
3104 */
3105 regindex = (vlan >> 5) & 0x7F;
3106 bitindex = vlan & 0x1F;
3107 targetbit = (1 << bitindex);
3108 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3109
3110 if (vlan_on) {
3111 if (!(vfta & targetbit)) {
3112 vfta |= targetbit;
3113 vfta_changed = true;
3114 }
3115 } else {
3116 if ((vfta & targetbit)) {
3117 vfta &= ~targetbit;
3118 vfta_changed = true;
3119 }
3120 }
3121
3122 /* Part 2
3123 * If VT Mode is set
3124 * Either vlan_on
3125 * make sure the vlan is in VLVF
3126 * set the vind bit in the matching VLVFB
3127 * Or !vlan_on
3128 * clear the pool bit and possibly the vind
3129 */
3130 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3131 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3132 s32 vlvf_index;
3133
3134 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3135 if (vlvf_index < 0)
3136 return vlvf_index;
3137
3138 if (vlan_on) {
3139 /* set the pool bit */
3140 if (vind < 32) {
3141 bits = IXGBE_READ_REG(hw,
3142 IXGBE_VLVFB(vlvf_index*2));
3143 bits |= (1 << vind);
3144 IXGBE_WRITE_REG(hw,
3145 IXGBE_VLVFB(vlvf_index*2),
3146 bits);
3147 } else {
3148 bits = IXGBE_READ_REG(hw,
3149 IXGBE_VLVFB((vlvf_index*2)+1));
3150 bits |= (1 << (vind-32));
3151 IXGBE_WRITE_REG(hw,
3152 IXGBE_VLVFB((vlvf_index*2)+1),
3153 bits);
3154 }
3155 } else {
3156 /* clear the pool bit */
3157 if (vind < 32) {
3158 bits = IXGBE_READ_REG(hw,
3159 IXGBE_VLVFB(vlvf_index*2));
3160 bits &= ~(1 << vind);
3161 IXGBE_WRITE_REG(hw,
3162 IXGBE_VLVFB(vlvf_index*2),
3163 bits);
3164 bits |= IXGBE_READ_REG(hw,
3165 IXGBE_VLVFB((vlvf_index*2)+1));
3166 } else {
3167 bits = IXGBE_READ_REG(hw,
3168 IXGBE_VLVFB((vlvf_index*2)+1));
3169 bits &= ~(1 << (vind-32));
3170 IXGBE_WRITE_REG(hw,
3171 IXGBE_VLVFB((vlvf_index*2)+1),
3172 bits);
3173 bits |= IXGBE_READ_REG(hw,
3174 IXGBE_VLVFB(vlvf_index*2));
3175 }
3176 }
3177
3178 /*
3179 * If there are still bits set in the VLVFB registers
3180 * for the VLAN ID indicated we need to see if the
3181 * caller is requesting that we clear the VFTA entry bit.
3182 * If the caller has requested that we clear the VFTA
3183 * entry bit but there are still pools/VFs using this VLAN
3184 * ID entry then ignore the request. We're not worried
3185 * about the case where we're turning the VFTA VLAN ID
3186 * entry bit on, only when requested to turn it off as
3187 * there may be multiple pools and/or VFs using the
3188 * VLAN ID entry. In that case we cannot clear the
3189 * VFTA bit until all pools/VFs using that VLAN ID have also
3190 * been cleared. This will be indicated by "bits" being
3191 * zero.
3192 */
3193 if (bits) {
3194 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3195 (IXGBE_VLVF_VIEN | vlan));
3196 if (!vlan_on) {
3197 /* someone wants to clear the vfta entry
3198 * but some pools/VFs are still using it.
3199 * Ignore it. */
3200 vfta_changed = false;
3201 }
3202 }
3203 else
3204 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3205 }
3206
3207 if (vfta_changed)
3208 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3209
3210 return 0;
3211}
3212
3213/**
3214 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3215 * @hw: pointer to hardware structure
3216 *
3217 * Clears the VLAN filer table, and the VMDq index associated with the filter
3218 **/
3219s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3220{
3221 u32 offset;
3222
3223 for (offset = 0; offset < hw->mac.vft_size; offset++)
3224 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3225
3226 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3227 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3228 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3229 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3230 }
3231
3232 return 0;
3233}
3234
3235/**
3236 * ixgbe_check_mac_link_generic - Determine link and speed status
3237 * @hw: pointer to hardware structure
3238 * @speed: pointer to link speed
3239 * @link_up: true when link is up
3240 * @link_up_wait_to_complete: bool used to wait for link up or not
3241 *
3242 * Reads the links register to determine if link is up and the current speed
3243 **/
3244s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3245 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3246{
48de36c5 3247 u32 links_reg, links_orig;
21ce849b
MC		 3248 u32 i;
3249
48de36c5
ET		 3250 /* clear the old state */
3251 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3252
21ce849b 3253 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3254
3255 if (links_orig != links_reg) {
3256 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3257 links_orig, links_reg);
3258 }
3259
21ce849b
MC		 3260 if (link_up_wait_to_complete) {
3261 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3262 if (links_reg & IXGBE_LINKS_UP) {
3263 *link_up = true;
3264 break;
3265 } else {
3266 *link_up = false;
3267 }
3268 msleep(100);
3269 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3270 }
3271 } else {
3272 if (links_reg & IXGBE_LINKS_UP)
3273 *link_up = true;
3274 else
3275 *link_up = false;
3276 }
3277
3278 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3279 IXGBE_LINKS_SPEED_10G_82599)
3280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3281 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 3282 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 3283 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 3284 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3285 IXGBE_LINKS_SPEED_100_82599)
21ce849b 3286 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 3287 else
3288 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b 3289
21ce849b
MC		 3290 return 0;
3291}
a391f1d5
DS		 3292
3293/**
49ce9c2c 3294 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3295 * the EEPROM
3296 * @hw: pointer to hardware structure
3297 * @wwnn_prefix: the alternative WWNN prefix
3298 * @wwpn_prefix: the alternative WWPN prefix
3299 *
3300 * This function will read the EEPROM from the alternative SAN MAC address
3301 * block to check the support for the alternative WWNN/WWPN prefix support.
3302 **/
3303s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 3304 u16 *wwpn_prefix)
a391f1d5
DS		 3305{
3306 u16 offset, caps;
3307 u16 alt_san_mac_blk_offset;
3308
3309 /* clear output first */
3310 *wwnn_prefix = 0xFFFF;
3311 *wwpn_prefix = 0xFFFF;
3312
3313 /* check if alternative SAN MAC is supported */
be0c27b4
MR		 3314 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3315 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3316 goto wwn_prefix_err;
a391f1d5
DS		 3317
3318 if ((alt_san_mac_blk_offset == 0) ||
3319 (alt_san_mac_blk_offset == 0xFFFF))
3320 goto wwn_prefix_out;
3321
3322 /* check capability in alternative san mac address block */
3323 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
be0c27b4
MR		 3324 if (hw->eeprom.ops.read(hw, offset, &caps))
3325 goto wwn_prefix_err;
a391f1d5
DS		 3326 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3327 goto wwn_prefix_out;
3328
3329 /* get the corresponding prefix for WWNN/WWPN */
3330 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
be0c27b4
MR		 3331 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3332 hw_err(hw, "eeprom read at offset %d failed\n", offset);
a391f1d5
DS		 3333
3334 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
be0c27b4
MR		 3335 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3336 goto wwn_prefix_err;
a391f1d5
DS		 3337
3338wwn_prefix_out:
3339 return 0;
be0c27b4
MR		 3340
3341wwn_prefix_err:
3342 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3343 return 0;
a391f1d5 3344}
a985b6c3
GR		 3345
3346/**
3347 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3348 * @hw: pointer to hardware structure
3349 * @enable: enable or disable switch for anti-spoofing
3350 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3351 *
3352 **/
3353void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3354{
3355 int j;
3356 int pf_target_reg = pf >> 3;
3357 int pf_target_shift = pf % 8;
3358 u32 pfvfspoof = 0;
3359
3360 if (hw->mac.type == ixgbe_mac_82598EB)
3361 return;
3362
3363 if (enable)
3364 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3365
3366 /*
3367 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3368 * MAC anti-spoof enables in each register array element.
3369 */
ef89e0a2 3370 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3371 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3372
a985b6c3
GR		 3373 /*
3374 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3375 * emulation mode NICs. Do not set the bits assigned to the PF
3376 */
3377 pfvfspoof &= (1 << pf_target_shift) - 1;
3378 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3379
3380 /*
3381 * Remaining pools belong to the PF so they do not need to have
3382 * anti-spoofing enabled.
a985b6c3 3383 */
ef89e0a2
AD		 3384 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3385 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3386}
3387
3388/**
3389 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3390 * @hw: pointer to hardware structure
3391 * @enable: enable or disable switch for VLAN anti-spoofing
3392 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3393 *
3394 **/
3395void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3396{
3397 int vf_target_reg = vf >> 3;
3398 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3399 u32 pfvfspoof;
3400
3401 if (hw->mac.type == ixgbe_mac_82598EB)
3402 return;
3403
3404 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3405 if (enable)
3406 pfvfspoof |= (1 << vf_target_shift);
3407 else
3408 pfvfspoof &= ~(1 << vf_target_shift);
3409 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3410}
b776d104
ET		 3411
3412/**
3413 * ixgbe_get_device_caps_generic - Get additional device capabilities
3414 * @hw: pointer to hardware structure
3415 * @device_caps: the EEPROM word with the extra device capabilities
3416 *
3417 * This function will read the EEPROM location for the device capabilities,
3418 * and return the word through device_caps.
3419 **/
3420s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3421{
3422 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3423
3424 return 0;
3425}
80605c65
JF		 3426
3427/**
3428 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3429 * @hw: pointer to hardware structure
3430 * @num_pb: number of packet buffers to allocate
3431 * @headroom: reserve n KB of headroom
3432 * @strategy: packet buffer allocation strategy
3433 **/
3434void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3435 int num_pb,
3436 u32 headroom,
3437 int strategy)
3438{
3439 u32 pbsize = hw->mac.rx_pb_size;
3440 int i = 0;
3441 u32 rxpktsize, txpktsize, txpbthresh;
3442
3443 /* Reserve headroom */
3444 pbsize -= headroom;
3445
3446 if (!num_pb)
3447 num_pb = 1;
3448
3449 /* Divide remaining packet buffer space amongst the number
3450 * of packet buffers requested using supplied strategy.
3451 */
3452 switch (strategy) {
3453 case (PBA_STRATEGY_WEIGHTED):
3454 /* pba_80_48 strategy weight first half of packet buffer with
3455 * 5/8 of the packet buffer space.
3456 */
3457 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3458 pbsize -= rxpktsize * (num_pb / 2);
3459 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3460 for (; i < (num_pb / 2); i++)
3461 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3462 /* Fall through to configure remaining packet buffers */
3463 case (PBA_STRATEGY_EQUAL):
3464 /* Divide the remaining Rx packet buffer evenly among the TCs */
3465 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3466 for (; i < num_pb; i++)
3467 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3468 break;
3469 default:
3470 break;
3471 }
3472
3473 /*
3474 * Setup Tx packet buffer and threshold equally for all TCs
3475 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3476 * 10 since the largest packet we support is just over 9K.
3477 */
3478 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3479 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3480 for (i = 0; i < num_pb; i++) {
3481 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3482 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3483 }
3484
3485 /* Clear unused TCs, if any, to zero buffer size*/
3486 for (; i < IXGBE_MAX_PB; i++) {
3487 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3488 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3489 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3490 }
3491}
9612de92
ET		 3492
3493/**
3494 * ixgbe_calculate_checksum - Calculate checksum for buffer
3495 * @buffer: pointer to EEPROM
3496 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3497 *
9612de92
ET		 3498 * Calculates the checksum for some buffer on a specified length. The
3499 * checksum calculated is returned.
3500 **/
3501static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3502{
3503 u32 i;
3504 u8 sum = 0;
3505
3506 if (!buffer)
3507 return 0;
3508
3509 for (i = 0; i < length; i++)
3510 sum += buffer[i];
3511
3512 return (u8) (0 - sum);
3513}
3514
3515/**
3516 * ixgbe_host_interface_command - Issue command to manageability block
3517 * @hw: pointer to the HW structure
3518 * @buffer: contains the command to write and where the return status will
3519 * be placed
c466d7a7 3520 * @length: length of buffer, must be multiple of 4 bytes
9612de92
ET		 3521 *
3522 * Communicates with the manageability block. On success return 0
3523 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3524 **/
79488c58 3525static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
9612de92
ET		 3526 u32 length)
3527{
331bcf45 3528 u32 hicr, i, bi;
9612de92
ET		 3529 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3530 u8 buf_len, dword_len;
3531
3532 s32 ret_val = 0;
3533
3534 if (length == 0 || length & 0x3 ||
3535 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3536 hw_dbg(hw, "Buffer length failure.\n");
3537 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3538 goto out;
3539 }
3540
3541 /* Check that the host interface is enabled. */
3542 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3543 if ((hicr & IXGBE_HICR_EN) == 0) {
3544 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3545 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3546 goto out;
3547 }
3548
3549 /* Calculate length in DWORDs */
3550 dword_len = length >> 2;
3551
3552 /*
3553 * The device driver writes the relevant command block
3554 * into the ram area.
3555 */
3556 for (i = 0; i < dword_len; i++)
3557 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3558 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3559
3560 /* Setting this bit tells the ARC that a new command is pending. */
3561 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3562
3563 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3564 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3565 if (!(hicr & IXGBE_HICR_C))
3566 break;
3567 usleep_range(1000, 2000);
3568 }
3569
3570 /* Check command successful completion. */
3571 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3572 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3573 hw_dbg(hw, "Command has failed with no status valid.\n");
3574 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3575 goto out;
3576 }
3577
3578 /* Calculate length in DWORDs */
3579 dword_len = hdr_size >> 2;
3580
3581 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3582 for (bi = 0; bi < dword_len; bi++) {
3583 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3584 le32_to_cpus(&buffer[bi]);
79488c58 3585 }
9612de92
ET		 3586
3587 /* If there is any thing in data position pull it in */
3588 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3589 if (buf_len == 0)
3590 goto out;
3591
3592 if (length < (buf_len + hdr_size)) {
3593 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3594 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3595 goto out;
3596 }
3597
331bcf45
ET		 3598 /* Calculate length in DWORDs, add 3 for odd lengths */
3599 dword_len = (buf_len + 3) >> 2;
9612de92 3600
331bcf45
ET		 3601 /* Pull in the rest of the buffer (bi is where we left off)*/
3602 for (; bi <= dword_len; bi++) {
3603 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3604 le32_to_cpus(&buffer[bi]);
3605 }
9612de92
ET		 3606
3607out:
3608 return ret_val;
3609}
3610
3611/**
3612 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3613 * @hw: pointer to the HW structure
3614 * @maj: driver version major number
3615 * @min: driver version minor number
3616 * @build: driver version build number
3617 * @sub: driver version sub build number
3618 *
3619 * Sends driver version number to firmware through the manageability
3620 * block. On success return 0
3621 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3622 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3623 **/
3624s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3625 u8 build, u8 sub)
3626{
3627 struct ixgbe_hic_drv_info fw_cmd;
3628 int i;
3629 s32 ret_val = 0;
3630
3631 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3632 ret_val = IXGBE_ERR_SWFW_SYNC;
3633 goto out;
3634 }
3635
3636 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3637 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3638 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3639 fw_cmd.port_num = (u8)hw->bus.func;
3640 fw_cmd.ver_maj = maj;
3641 fw_cmd.ver_min = min;
3642 fw_cmd.ver_build = build;
3643 fw_cmd.ver_sub = sub;
3644 fw_cmd.hdr.checksum = 0;
3645 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3646 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3647 fw_cmd.pad = 0;
3648 fw_cmd.pad2 = 0;
3649
3650 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3651 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
9612de92
ET		 3652 sizeof(fw_cmd));
3653 if (ret_val != 0)
3654 continue;
3655
3656 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3657 FW_CEM_RESP_STATUS_SUCCESS)
3658 ret_val = 0;
3659 else
3660 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3661
3662 break;
3663 }
3664
3665 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3666out:
3667 return ret_val;
3668}
ff9d1a5a
ET		 3669
3670/**
3671 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3672 * @hw: pointer to the hardware structure
3673 *
3674 * The 82599 and x540 MACs can experience issues if TX work is still pending
3675 * when a reset occurs. This function prevents this by flushing the PCIe
3676 * buffers on the system.
3677 **/
3678void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3679{
3680 u32 gcr_ext, hlreg0;
3681
3682 /*
3683 * If double reset is not requested then all transactions should
3684 * already be clear and as such there is no work to do
3685 */
3686 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3687 return;
3688
3689 /*
3690 * Set loopback enable to prevent any transmits from being sent
3691 * should the link come up. This assumes that the RXCTRL.RXEN bit
3692 * has already been cleared.
3693 */
3694 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3695 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3696
3697 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3698 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3699 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3700 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3701
3702 /* Flush all writes and allow 20usec for all transactions to clear */
3703 IXGBE_WRITE_FLUSH(hw);
3704 udelay(20);
3705
3706 /* restore previous register values */
3707 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3708 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3709}
e1ea9158
DS		 3710
3711static const u8 ixgbe_emc_temp_data[4] = {
3712 IXGBE_EMC_INTERNAL_DATA,
3713 IXGBE_EMC_DIODE1_DATA,
3714 IXGBE_EMC_DIODE2_DATA,
3715 IXGBE_EMC_DIODE3_DATA
3716};
3717static const u8 ixgbe_emc_therm_limit[4] = {
3718 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3719 IXGBE_EMC_DIODE1_THERM_LIMIT,
3720 IXGBE_EMC_DIODE2_THERM_LIMIT,
3721 IXGBE_EMC_DIODE3_THERM_LIMIT
3722};
3723
3724/**
3725 * ixgbe_get_ets_data - Extracts the ETS bit data
3726 * @hw: pointer to hardware structure
3727 * @ets_cfg: extected ETS data
3728 * @ets_offset: offset of ETS data
3729 *
3730 * Returns error code.
3731 **/
3732static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3733 u16 *ets_offset)
3734{
3735 s32 status = 0;
3736
3737 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3738 if (status)
3739 goto out;
3740
3741 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
3742 status = IXGBE_NOT_IMPLEMENTED;
3743 goto out;
3744 }
3745
3746 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3747 if (status)
3748 goto out;
3749
3750 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
3751 status = IXGBE_NOT_IMPLEMENTED;
3752 goto out;
3753 }
3754
3755out:
3756 return status;
3757}
3758
3759/**
3760 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3761 * @hw: pointer to hardware structure
3762 *
3763 * Returns the thermal sensor data structure
3764 **/
3765s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3766{
3767 s32 status = 0;
3768 u16 ets_offset;
3769 u16 ets_cfg;
3770 u16 ets_sensor;
3771 u8 num_sensors;
3772 u8 i;
3773 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3774
3ca8bc6d
DS		 3775 /* Only support thermal sensors attached to physical port 0 */
3776 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
e1ea9158
DS		 3777 status = IXGBE_NOT_IMPLEMENTED;
3778 goto out;
3779 }
3780
3781 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3782 if (status)
3783 goto out;
3784
3785 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3786 if (num_sensors > IXGBE_MAX_SENSORS)
3787 num_sensors = IXGBE_MAX_SENSORS;
3788
3789 for (i = 0; i < num_sensors; i++) {
3790 u8 sensor_index;
3791 u8 sensor_location;
3792
3793 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3794 &ets_sensor);
3795 if (status)
3796 goto out;
3797
3798 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3799 IXGBE_ETS_DATA_INDEX_SHIFT);
3800 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3801 IXGBE_ETS_DATA_LOC_SHIFT);
3802
3803 if (sensor_location != 0) {
3804 status = hw->phy.ops.read_i2c_byte(hw,
3805 ixgbe_emc_temp_data[sensor_index],
3806 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3807 &data->sensor[i].temp);
3808 if (status)
3809 goto out;
3810 }
3811 }
3812out:
3813 return status;
3814}
3815
3816/**
3817 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3818 * @hw: pointer to hardware structure
3819 *
3820 * Inits the thermal sensor thresholds according to the NVM map
3821 * and save off the threshold and location values into mac.thermal_sensor_data
3822 **/
3823s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3824{
3825 s32 status = 0;
3826 u16 ets_offset;
3827 u16 ets_cfg;
3828 u16 ets_sensor;
3829 u8 low_thresh_delta;
3830 u8 num_sensors;
3831 u8 therm_limit;
3832 u8 i;
3833 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3834
3835 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3836
3ca8bc6d
DS		 3837 /* Only support thermal sensors attached to physical port 0 */
3838 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
e1ea9158
DS		 3839 status = IXGBE_NOT_IMPLEMENTED;
3840 goto out;
3841 }
3842
3843 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3844 if (status)
3845 goto out;
3846
3847 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3848 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3849 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3850 if (num_sensors > IXGBE_MAX_SENSORS)
3851 num_sensors = IXGBE_MAX_SENSORS;
3852
3853 for (i = 0; i < num_sensors; i++) {
3854 u8 sensor_index;
3855 u8 sensor_location;
3856
be0c27b4
MR		 3857 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3858 hw_err(hw, "eeprom read at offset %d failed\n",
3859 ets_offset + 1 + i);
3860 continue;
3861 }
e1ea9158
DS		 3862 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3863 IXGBE_ETS_DATA_INDEX_SHIFT);
3864 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3865 IXGBE_ETS_DATA_LOC_SHIFT);
3866 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3867
3868 hw->phy.ops.write_i2c_byte(hw,
3869 ixgbe_emc_therm_limit[sensor_index],
3870 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3871
3872 if (sensor_location == 0)
3873 continue;
3874
3875 data->sensor[i].location = sensor_location;
3876 data->sensor[i].caution_thresh = therm_limit;
3877 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3878 }
3879out:
3880 return status;
3881}
3882
Linux kernel - Deliverables
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