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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
afdc71e4 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
ccffad25 32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 44 u16 count);
c44ade9e
JB		 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 49
9a799d71 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
ff9d1a5a 58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 59
9a900eca
DS		 60/* Base table for registers values that change by MAC */
61const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
62 IXGBE_MVALS_INIT(8259X)
63};
64
67a79df2
AD		 65/**
66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
67 * control
68 * @hw: pointer to hardware structure
69 *
70 * There are several phys that do not support autoneg flow control. This
71 * function check the device id to see if the associated phy supports
72 * autoneg flow control.
73 **/
73d80953 74bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2 75{
73d80953
DS		 76 bool supported = false;
77 ixgbe_link_speed speed;
78 bool link_up;
67a79df2 79
73d80953
DS		 80 switch (hw->phy.media_type) {
81 case ixgbe_media_type_fiber:
82 hw->mac.ops.check_link(hw, &speed, &link_up, false);
83 /* if link is down, assume supported */
84 if (link_up)
85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
86 true : false;
87 else
88 supported = true;
89 break;
90 case ixgbe_media_type_backplane:
91 supported = true;
92 break;
93 case ixgbe_media_type_copper:
94 /* only some copper devices support flow control autoneg */
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82599_T3_LOM:
97 case IXGBE_DEV_ID_X540T:
98 case IXGBE_DEV_ID_X540T1:
df8c26fd 99 case IXGBE_DEV_ID_X550T:
a711ad89 100 case IXGBE_DEV_ID_X550T1:
df8c26fd 101 case IXGBE_DEV_ID_X550EM_X_10G_T:
92ed8430 102 case IXGBE_DEV_ID_X550EM_A_10G_T:
73d80953
DS		 103 supported = true;
104 break;
105 default:
106 break;
107 }
67a79df2 108 default:
73d80953 109 break;
67a79df2 110 }
73d80953
DS		 111
112 return supported;
67a79df2
AD		 113}
114
115/**
afdc71e4 116 * ixgbe_setup_fc_generic - Set up flow control
67a79df2
AD		 117 * @hw: pointer to hardware structure
118 *
119 * Called at init time to set up flow control.
120 **/
afdc71e4 121s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
67a79df2
AD		 122{
123 s32 ret_val = 0;
124 u32 reg = 0, reg_bp = 0;
125 u16 reg_cu = 0;
429d6a3b 126 bool locked = false;
67a79df2 127
67a79df2
AD		 128 /*
129 * Validate the requested mode. Strict IEEE mode does not allow
130 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
131 */
132 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
133 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
e90dd264 134 return IXGBE_ERR_INVALID_LINK_SETTINGS;
67a79df2
AD		 135 }
136
137 /*
138 * 10gig parts do not have a word in the EEPROM to determine the
139 * default flow control setting, so we explicitly set it to full.
140 */
141 if (hw->fc.requested_mode == ixgbe_fc_default)
142 hw->fc.requested_mode = ixgbe_fc_full;
143
144 /*
145 * Set up the 1G and 10G flow control advertisement registers so the
146 * HW will be able to do fc autoneg once the cable is plugged in. If
147 * we link at 10G, the 1G advertisement is harmless and vice versa.
148 */
67a79df2 149 switch (hw->phy.media_type) {
429d6a3b
DS		 150 case ixgbe_media_type_backplane:
151 /* some MAC's need RMW protection on AUTOC */
152 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
f8cf7a00 153 if (ret_val)
e90dd264 154 return ret_val;
429d6a3b
DS		 155
156 /* only backplane uses autoc so fall though */
67a79df2 157 case ixgbe_media_type_fiber:
67a79df2 158 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
429d6a3b 159
67a79df2 160 break;
67a79df2
AD		 161 case ixgbe_media_type_copper:
162 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
163 MDIO_MMD_AN, &reg_cu);
164 break;
67a79df2 165 default:
041441d0 166 break;
67a79df2
AD		 167 }
168
169 /*
170 * The possible values of fc.requested_mode are:
171 * 0: Flow control is completely disabled
172 * 1: Rx flow control is enabled (we can receive pause frames,
173 * but not send pause frames).
174 * 2: Tx flow control is enabled (we can send pause frames but
175 * we do not support receiving pause frames).
176 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 177 * other: Invalid.
178 */
179 switch (hw->fc.requested_mode) {
180 case ixgbe_fc_none:
181 /* Flow control completely disabled by software override. */
182 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
183 if (hw->phy.media_type == ixgbe_media_type_backplane)
184 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
185 IXGBE_AUTOC_ASM_PAUSE);
186 else if (hw->phy.media_type == ixgbe_media_type_copper)
187 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
188 break;
67a79df2
AD		 189 case ixgbe_fc_tx_pause:
190 /*
191 * Tx Flow control is enabled, and Rx Flow control is
192 * disabled by software override.
193 */
041441d0
AD		 194 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
195 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 196 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 197 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
198 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 199 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 200 reg_cu |= IXGBE_TAF_ASM_PAUSE;
201 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 202 }
203 break;
041441d0
AD		 204 case ixgbe_fc_rx_pause:
205 /*
206 * Rx Flow control is enabled and Tx Flow control is
207 * disabled by software override. Since there really
208 * isn't a way to advertise that we are capable of RX
209 * Pause ONLY, we will advertise that we support both
210 * symmetric and asymmetric Rx PAUSE, as such we fall
211 * through to the fc_full statement. Later, we will
212 * disable the adapter's ability to send PAUSE frames.
213 */
67a79df2
AD		 214 case ixgbe_fc_full:
215 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 216 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 217 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 218 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
219 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 220 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 221 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 222 break;
67a79df2
AD		 223 default:
224 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 225 return IXGBE_ERR_CONFIG;
67a79df2
AD		 226 }
227
228 if (hw->mac.type != ixgbe_mac_X540) {
229 /*
230 * Enable auto-negotiation between the MAC & PHY;
231 * the MAC will advertise clause 37 flow control.
232 */
233 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
234 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
235
236 /* Disable AN timeout */
237 if (hw->fc.strict_ieee)
238 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
239
240 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
241 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
242 }
243
244 /*
245 * AUTOC restart handles negotiation of 1G and 10G on backplane
246 * and copper. There is no need to set the PCS1GCTL register.
247 *
248 */
249 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 250 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
251 * LESM is on, likewise reset_pipeline requries the lock as
252 * it also writes AUTOC.
253 */
429d6a3b
DS		 254 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
255 if (ret_val)
e90dd264 256 return ret_val;
d7bbcd32 257
67a79df2 258 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
429d6a3b 259 ixgbe_device_supports_autoneg_fc(hw)) {
67a79df2
AD		 260 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
261 MDIO_MMD_AN, reg_cu);
262 }
263
264 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
67a79df2
AD		 265 return ret_val;
266}
267
9a799d71 268/**
c44ade9e 269 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 270 * @hw: pointer to hardware structure
271 *
272 * Starts the hardware by filling the bus info structure and media type, clears
273 * all on chip counters, initializes receive address registers, multicast
274 * table, VLAN filter table, calls routine to set up link and flow control
275 * settings, and leaves transmit and receive units disabled and uninitialized
276 **/
c44ade9e 277s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71 278{
e5776620 279 s32 ret_val;
9a799d71 280 u32 ctrl_ext;
aac9e053 281 u16 device_caps;
9a799d71
AK		 282
283 /* Set the media type */
284 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
285
286 /* Identify the PHY */
c44ade9e 287 hw->phy.ops.identify(hw);
9a799d71 288
9a799d71 289 /* Clear the VLAN filter table */
c44ade9e 290 hw->mac.ops.clear_vfta(hw);
9a799d71 291
9a799d71 292 /* Clear statistics registers */
c44ade9e 293 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 294
295 /* Set No Snoop Disable */
296 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
297 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
298 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 299 IXGBE_WRITE_FLUSH(hw);
9a799d71 300
620fa036 301 /* Setup flow control */
afdc71e4 302 ret_val = hw->mac.ops.setup_fc(hw);
3507a9b8
MR		 303 if (ret_val)
304 return ret_val;
620fa036 305
aac9e053
DS		 306 /* Cashe bit indicating need for crosstalk fix */
307 switch (hw->mac.type) {
308 case ixgbe_mac_82599EB:
309 case ixgbe_mac_X550EM_x:
310 case ixgbe_mac_x550em_a:
311 hw->mac.ops.get_device_caps(hw, &device_caps);
312 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
313 hw->need_crosstalk_fix = false;
314 else
315 hw->need_crosstalk_fix = true;
316 break;
317 default:
318 hw->need_crosstalk_fix = false;
319 break;
320 }
321
9a799d71
AK		 322 /* Clear adapter stopped flag */
323 hw->adapter_stopped = false;
324
3507a9b8 325 return 0;
9a799d71
AK		 326}
327
7184b7cf
ET		 328/**
329 * ixgbe_start_hw_gen2 - Init sequence for common device family
330 * @hw: pointer to hw structure
331 *
332 * Performs the init sequence common to the second generation
333 * of 10 GbE devices.
334 * Devices in the second generation:
335 * 82599
336 * X540
337 **/
338s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
339{
340 u32 i;
341
342 /* Clear the rate limiters */
343 for (i = 0; i < hw->mac.max_tx_queues; i++) {
344 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
345 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
346 }
347 IXGBE_WRITE_FLUSH(hw);
348
887012e8 349#ifndef CONFIG_SPARC
3d5c5207
ET		 350 /* Disable relaxed ordering */
351 for (i = 0; i < hw->mac.max_tx_queues; i++) {
887012e8
JK		 352 u32 regval;
353
3d5c5207 354 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 355 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 356 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
357 }
358
359 for (i = 0; i < hw->mac.max_rx_queues; i++) {
887012e8
JK		 360 u32 regval;
361
3d5c5207 362 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 363 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
364 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 365 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
366 }
887012e8 367#endif
7184b7cf
ET		 368 return 0;
369}
370
9a799d71 371/**
c44ade9e 372 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 373 * @hw: pointer to hardware structure
374 *
c44ade9e 375 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 376 * structure and media type, clears all on chip counters, initializes receive
377 * address registers, multicast table, VLAN filter table, calls routine to set
378 * up link and flow control settings, and leaves transmit and receive units
379 * disabled and uninitialized
380 **/
c44ade9e 381s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 382{
794caeb2
PWJ		 383 s32 status;
384
9a799d71 385 /* Reset the hardware */
794caeb2 386 status = hw->mac.ops.reset_hw(hw);
9a799d71 387
794caeb2
PWJ		 388 if (status == 0) {
389 /* Start the HW */
390 status = hw->mac.ops.start_hw(hw);
391 }
9a799d71 392
794caeb2 393 return status;
9a799d71
AK		 394}
395
396/**
c44ade9e 397 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 398 * @hw: pointer to hardware structure
399 *
400 * Clears all hardware statistics counters by reading them from the hardware
401 * Statistics counters are clear on read.
402 **/
c44ade9e 403s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 404{
405 u16 i = 0;
406
407 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
408 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
409 IXGBE_READ_REG(hw, IXGBE_ERRBC);
410 IXGBE_READ_REG(hw, IXGBE_MSPDC);
411 for (i = 0; i < 8; i++)
412 IXGBE_READ_REG(hw, IXGBE_MPC(i));
413
414 IXGBE_READ_REG(hw, IXGBE_MLFC);
415 IXGBE_READ_REG(hw, IXGBE_MRFC);
416 IXGBE_READ_REG(hw, IXGBE_RLEC);
417 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 418 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 419 if (hw->mac.type >= ixgbe_mac_82599EB) {
420 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
421 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
422 } else {
423 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
424 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
425 }
9a799d71
AK		 426
427 for (i = 0; i < 8; i++) {
428 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 429 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 430 if (hw->mac.type >= ixgbe_mac_82599EB) {
431 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
432 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
433 } else {
434 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
435 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
436 }
9a799d71 437 }
667c7565
ET		 438 if (hw->mac.type >= ixgbe_mac_82599EB)
439 for (i = 0; i < 8; i++)
440 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 441 IXGBE_READ_REG(hw, IXGBE_PRC64);
442 IXGBE_READ_REG(hw, IXGBE_PRC127);
443 IXGBE_READ_REG(hw, IXGBE_PRC255);
444 IXGBE_READ_REG(hw, IXGBE_PRC511);
445 IXGBE_READ_REG(hw, IXGBE_PRC1023);
446 IXGBE_READ_REG(hw, IXGBE_PRC1522);
447 IXGBE_READ_REG(hw, IXGBE_GPRC);
448 IXGBE_READ_REG(hw, IXGBE_BPRC);
449 IXGBE_READ_REG(hw, IXGBE_MPRC);
450 IXGBE_READ_REG(hw, IXGBE_GPTC);
451 IXGBE_READ_REG(hw, IXGBE_GORCL);
452 IXGBE_READ_REG(hw, IXGBE_GORCH);
453 IXGBE_READ_REG(hw, IXGBE_GOTCL);
454 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 455 if (hw->mac.type == ixgbe_mac_82598EB)
456 for (i = 0; i < 8; i++)
457 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 458 IXGBE_READ_REG(hw, IXGBE_RUC);
459 IXGBE_READ_REG(hw, IXGBE_RFC);
460 IXGBE_READ_REG(hw, IXGBE_ROC);
461 IXGBE_READ_REG(hw, IXGBE_RJC);
462 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
463 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
464 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
465 IXGBE_READ_REG(hw, IXGBE_TORL);
466 IXGBE_READ_REG(hw, IXGBE_TORH);
467 IXGBE_READ_REG(hw, IXGBE_TPR);
468 IXGBE_READ_REG(hw, IXGBE_TPT);
469 IXGBE_READ_REG(hw, IXGBE_PTC64);
470 IXGBE_READ_REG(hw, IXGBE_PTC127);
471 IXGBE_READ_REG(hw, IXGBE_PTC255);
472 IXGBE_READ_REG(hw, IXGBE_PTC511);
473 IXGBE_READ_REG(hw, IXGBE_PTC1023);
474 IXGBE_READ_REG(hw, IXGBE_PTC1522);
475 IXGBE_READ_REG(hw, IXGBE_MPTC);
476 IXGBE_READ_REG(hw, IXGBE_BPTC);
477 for (i = 0; i < 16; i++) {
478 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 479 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 480 if (hw->mac.type >= ixgbe_mac_82599EB) {
481 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
482 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
483 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
484 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
485 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
486 } else {
487 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
488 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
489 }
9a799d71
AK		 490 }
491
e87ce1cd 492 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
a3aeea0e
ET		 493 if (hw->phy.id == 0)
494 hw->phy.ops.identify(hw);
c1085b10
ET		 495 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
496 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
497 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
498 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 499 }
500
9a799d71
AK		 501 return 0;
502}
503
504/**
289700db 505 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 506 * @hw: pointer to hardware structure
289700db
DS		 507 * @pba_num: stores the part number string from the EEPROM
508 * @pba_num_size: part number string buffer length
c44ade9e 509 *
289700db 510 * Reads the part number string from the EEPROM.
c44ade9e 511 **/
289700db 512s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 513 u32 pba_num_size)
c44ade9e
JB		 514{
515 s32 ret_val;
516 u16 data;
289700db
DS		 517 u16 pba_ptr;
518 u16 offset;
519 u16 length;
520
521 if (pba_num == NULL) {
522 hw_dbg(hw, "PBA string buffer was null\n");
523 return IXGBE_ERR_INVALID_ARGUMENT;
524 }
c44ade9e
JB		 525
526 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
527 if (ret_val) {
528 hw_dbg(hw, "NVM Read Error\n");
529 return ret_val;
530 }
c44ade9e 531
289700db 532 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 533 if (ret_val) {
534 hw_dbg(hw, "NVM Read Error\n");
535 return ret_val;
536 }
289700db
DS		 537
538 /*
539 * if data is not ptr guard the PBA must be in legacy format which
540 * means pba_ptr is actually our second data word for the PBA number
541 * and we can decode it into an ascii string
542 */
543 if (data != IXGBE_PBANUM_PTR_GUARD) {
544 hw_dbg(hw, "NVM PBA number is not stored as string\n");
545
546 /* we will need 11 characters to store the PBA */
547 if (pba_num_size < 11) {
548 hw_dbg(hw, "PBA string buffer too small\n");
549 return IXGBE_ERR_NO_SPACE;
550 }
551
552 /* extract hex string from data and pba_ptr */
553 pba_num[0] = (data >> 12) & 0xF;
554 pba_num[1] = (data >> 8) & 0xF;
555 pba_num[2] = (data >> 4) & 0xF;
556 pba_num[3] = data & 0xF;
557 pba_num[4] = (pba_ptr >> 12) & 0xF;
558 pba_num[5] = (pba_ptr >> 8) & 0xF;
559 pba_num[6] = '-';
560 pba_num[7] = 0;
561 pba_num[8] = (pba_ptr >> 4) & 0xF;
562 pba_num[9] = pba_ptr & 0xF;
563
564 /* put a null character on the end of our string */
565 pba_num[10] = '\0';
566
567 /* switch all the data but the '-' to hex char */
568 for (offset = 0; offset < 10; offset++) {
569 if (pba_num[offset] < 0xA)
570 pba_num[offset] += '0';
571 else if (pba_num[offset] < 0x10)
572 pba_num[offset] += 'A' - 0xA;
573 }
574
575 return 0;
576 }
577
578 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
579 if (ret_val) {
580 hw_dbg(hw, "NVM Read Error\n");
581 return ret_val;
582 }
583
584 if (length == 0xFFFF || length == 0) {
585 hw_dbg(hw, "NVM PBA number section invalid length\n");
586 return IXGBE_ERR_PBA_SECTION;
587 }
588
589 /* check if pba_num buffer is big enough */
590 if (pba_num_size < (((u32)length * 2) - 1)) {
591 hw_dbg(hw, "PBA string buffer too small\n");
592 return IXGBE_ERR_NO_SPACE;
593 }
594
595 /* trim pba length from start of string */
596 pba_ptr++;
597 length--;
598
599 for (offset = 0; offset < length; offset++) {
600 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
601 if (ret_val) {
602 hw_dbg(hw, "NVM Read Error\n");
603 return ret_val;
604 }
605 pba_num[offset * 2] = (u8)(data >> 8);
606 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
607 }
608 pba_num[offset * 2] = '\0';
c44ade9e
JB		 609
610 return 0;
611}
612
613/**
614 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 615 * @hw: pointer to hardware structure
616 * @mac_addr: Adapter MAC address
617 *
618 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
619 * A reset of the adapter must be performed prior to calling this function
620 * in order for the MAC address to have been loaded from the EEPROM into RAR0
621 **/
c44ade9e 622s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 623{
624 u32 rar_high;
625 u32 rar_low;
626 u16 i;
627
628 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
629 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
630
631 for (i = 0; i < 4; i++)
632 mac_addr[i] = (u8)(rar_low >> (i*8));
633
634 for (i = 0; i < 2; i++)
635 mac_addr[i+4] = (u8)(rar_high >> (i*8));
636
637 return 0;
638}
639
ef1889d5
JK		 640enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
641{
642 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
643 case IXGBE_PCI_LINK_WIDTH_1:
644 return ixgbe_bus_width_pcie_x1;
645 case IXGBE_PCI_LINK_WIDTH_2:
646 return ixgbe_bus_width_pcie_x2;
647 case IXGBE_PCI_LINK_WIDTH_4:
648 return ixgbe_bus_width_pcie_x4;
649 case IXGBE_PCI_LINK_WIDTH_8:
650 return ixgbe_bus_width_pcie_x8;
651 default:
652 return ixgbe_bus_width_unknown;
653 }
654}
655
656enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
657{
658 switch (link_status & IXGBE_PCI_LINK_SPEED) {
659 case IXGBE_PCI_LINK_SPEED_2500:
660 return ixgbe_bus_speed_2500;
661 case IXGBE_PCI_LINK_SPEED_5000:
662 return ixgbe_bus_speed_5000;
663 case IXGBE_PCI_LINK_SPEED_8000:
664 return ixgbe_bus_speed_8000;
665 default:
666 return ixgbe_bus_speed_unknown;
667 }
668}
669
11afc1b1
PW		 670/**
671 * ixgbe_get_bus_info_generic - Generic set PCI bus info
672 * @hw: pointer to hardware structure
673 *
674 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
675 **/
676s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
677{
11afc1b1
PW		 678 u16 link_status;
679
680 hw->bus.type = ixgbe_bus_type_pci_express;
681
682 /* Get the negotiated link width and speed from PCI config space */
0d7c6e00 683 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
11afc1b1 684
ef1889d5
JK		 685 hw->bus.width = ixgbe_convert_bus_width(link_status);
686 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1 687
0d7c6e00 688 hw->mac.ops.set_lan_id(hw);
11afc1b1
PW		 689
690 return 0;
691}
692
693/**
694 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
695 * @hw: pointer to the HW structure
696 *
697 * Determines the LAN function id by reading memory-mapped registers
698 * and swaps the port value if requested.
699 **/
700void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
701{
702 struct ixgbe_bus_info *bus = &hw->bus;
c898fe28 703 u16 ee_ctrl_4;
11afc1b1
PW		 704 u32 reg;
705
706 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
707 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
708 bus->lan_id = bus->func;
709
710 /* check for a port swap */
9a900eca 711 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
11afc1b1
PW		 712 if (reg & IXGBE_FACTPS_LFS)
713 bus->func ^= 0x1;
c898fe28
MR		 714
715 /* Get MAC instance from EEPROM for configuring CS4227 */
716 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
717 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
718 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
719 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
720 }
11afc1b1
PW		 721}
722
9a799d71 723/**
c44ade9e 724 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 725 * @hw: pointer to hardware structure
726 *
727 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
728 * disables transmit and receive units. The adapter_stopped flag is used by
729 * the shared code and drivers to determine if the adapter is in a stopped
730 * state and should not touch the hardware.
731 **/
c44ade9e 732s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 733{
9a799d71
AK		 734 u32 reg_val;
735 u16 i;
736
737 /*
738 * Set the adapter_stopped flag so other driver functions stop touching
739 * the hardware
740 */
741 hw->adapter_stopped = true;
742
743 /* Disable the receive unit */
1f9ac57c 744 hw->mac.ops.disable_rx(hw);
9a799d71 745
ff9d1a5a 746 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 747 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
748
ff9d1a5a 749 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 750 IXGBE_READ_REG(hw, IXGBE_EICR);
751
752 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 753 for (i = 0; i < hw->mac.max_tx_queues; i++)
754 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
755
756 /* Disable the receive unit by stopping each queue */
757 for (i = 0; i < hw->mac.max_rx_queues; i++) {
758 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
759 reg_val &= ~IXGBE_RXDCTL_ENABLE;
760 reg_val |= IXGBE_RXDCTL_SWFLSH;
761 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 762 }
763
ff9d1a5a
ET		 764 /* flush all queues disables */
765 IXGBE_WRITE_FLUSH(hw);
766 usleep_range(1000, 2000);
767
c44ade9e
JB		 768 /*
769 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
770 * access and verify no pending requests
771 */
ff9d1a5a 772 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 773}
774
775/**
c44ade9e 776 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 777 * @hw: pointer to hardware structure
778 * @index: led number to turn on
779 **/
c44ade9e 780s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 781{
782 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
783
003287e0
DS		 784 if (index > 3)
785 return IXGBE_ERR_PARAM;
786
9a799d71
AK		 787 /* To turn on the LED, set mode to ON. */
788 led_reg &= ~IXGBE_LED_MODE_MASK(index);
789 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
790 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 791 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 792
793 return 0;
794}
795
796/**
c44ade9e 797 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 798 * @hw: pointer to hardware structure
799 * @index: led number to turn off
800 **/
c44ade9e 801s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 802{
803 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
804
003287e0
DS		 805 if (index > 3)
806 return IXGBE_ERR_PARAM;
807
9a799d71
AK		 808 /* To turn off the LED, set mode to OFF. */
809 led_reg &= ~IXGBE_LED_MODE_MASK(index);
810 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
811 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 812 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 813
814 return 0;
815}
816
9a799d71 817/**
c44ade9e 818 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 819 * @hw: pointer to hardware structure
820 *
821 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
822 * ixgbe_hw struct in order to set up EEPROM access.
823 **/
c44ade9e 824s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 825{
826 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
827 u32 eec;
828 u16 eeprom_size;
829
830 if (eeprom->type == ixgbe_eeprom_uninitialized) {
831 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 832 /* Set default semaphore delay to 10ms which is a well
833 * tested value */
834 eeprom->semaphore_delay = 10;
68c7005d
ET		 835 /* Clear EEPROM page size, it will be initialized as needed */
836 eeprom->word_page_size = 0;
9a799d71
AK		 837
838 /*
839 * Check for EEPROM present first.
840 * If not present leave as none
841 */
9a900eca 842 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9a799d71
AK		 843 if (eec & IXGBE_EEC_PRES) {
844 eeprom->type = ixgbe_eeprom_spi;
845
846 /*
847 * SPI EEPROM is assumed here. This code would need to
848 * change if a future EEPROM is not SPI.
849 */
850 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
851 IXGBE_EEC_SIZE_SHIFT);
b4f47a48
JK		 852 eeprom->word_size = BIT(eeprom_size +
853 IXGBE_EEPROM_WORD_SIZE_SHIFT);
9a799d71
AK		 854 }
855
856 if (eec & IXGBE_EEC_ADDR_SIZE)
857 eeprom->address_bits = 16;
858 else
859 eeprom->address_bits = 8;
6ec1b71f
JK		 860 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
861 eeprom->type, eeprom->word_size, eeprom->address_bits);
9a799d71
AK		 862 }
863
864 return 0;
865}
866
11afc1b1 867/**
68c7005d 868 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 869 * @hw: pointer to hardware structure
68c7005d
ET		 870 * @offset: offset within the EEPROM to write
871 * @words: number of words
872 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 873 *
68c7005d 874 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 875 **/
68c7005d
ET		 876s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
877 u16 words, u16 *data)
11afc1b1 878{
e90dd264 879 s32 status;
68c7005d 880 u16 i, count;
11afc1b1
PW		 881
882 hw->eeprom.ops.init_params(hw);
883
e90dd264
MR		 884 if (words == 0)
885 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 886
e90dd264
MR		 887 if (offset + words > hw->eeprom.word_size)
888 return IXGBE_ERR_EEPROM;
11afc1b1 889
68c7005d
ET		 890 /*
891 * The EEPROM page size cannot be queried from the chip. We do lazy
892 * initialization. It is worth to do that when we write large buffer.
893 */
894 if ((hw->eeprom.word_page_size == 0) &&
895 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
896 ixgbe_detect_eeprom_page_size_generic(hw, offset);
897
898 /*
899 * We cannot hold synchronization semaphores for too long
900 * to avoid other entity starvation. However it is more efficient
901 * to read in bursts than synchronizing access for each word.
902 */
903 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
904 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
905 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
906 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
907 count, &data[i]);
908
909 if (status != 0)
910 break;
911 }
912
68c7005d
ET		 913 return status;
914}
915
916/**
917 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
918 * @hw: pointer to hardware structure
919 * @offset: offset within the EEPROM to be written to
920 * @words: number of word(s)
921 * @data: 16 bit word(s) to be written to the EEPROM
922 *
923 * If ixgbe_eeprom_update_checksum is not called after this function, the
924 * EEPROM will most likely contain an invalid checksum.
925 **/
926static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
927 u16 words, u16 *data)
928{
929 s32 status;
930 u16 word;
931 u16 page_size;
932 u16 i;
933 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
934
11afc1b1
PW		 935 /* Prepare the EEPROM for writing */
936 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 937 if (status)
938 return status;
11afc1b1 939
e90dd264
MR		 940 if (ixgbe_ready_eeprom(hw) != 0) {
941 ixgbe_release_eeprom(hw);
942 return IXGBE_ERR_EEPROM;
11afc1b1
PW		 943 }
944
e90dd264
MR		 945 for (i = 0; i < words; i++) {
946 ixgbe_standby_eeprom(hw);
947
948 /* Send the WRITE ENABLE command (8 bit opcode) */
949 ixgbe_shift_out_eeprom_bits(hw,
950 IXGBE_EEPROM_WREN_OPCODE_SPI,
951 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 952
e90dd264 953 ixgbe_standby_eeprom(hw);
11afc1b1 954
e90dd264
MR		 955 /* Some SPI eeproms use the 8th address bit embedded
956 * in the opcode
957 */
958 if ((hw->eeprom.address_bits == 8) &&
959 ((offset + i) >= 128))
960 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
11afc1b1 961
e90dd264
MR		 962 /* Send the Write command (8-bit opcode + addr) */
963 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
964 IXGBE_EEPROM_OPCODE_BITS);
965 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
966 hw->eeprom.address_bits);
967
968 page_size = hw->eeprom.word_page_size;
969
970 /* Send the data in burst via SPI */
971 do {
972 word = data[i];
973 word = (word >> 8) | (word << 8);
974 ixgbe_shift_out_eeprom_bits(hw, word, 16);
975
976 if (page_size == 0)
977 break;
978
979 /* do not wrap around page */
980 if (((offset + i) & (page_size - 1)) ==
981 (page_size - 1))
982 break;
983 } while (++i < words);
984
985 ixgbe_standby_eeprom(hw);
986 usleep_range(10000, 20000);
68c7005d 987 }
e90dd264
MR		 988 /* Done with writing - release the EEPROM */
989 ixgbe_release_eeprom(hw);
11afc1b1 990
e90dd264 991 return 0;
68c7005d
ET		 992}
993
994/**
995 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
996 * @hw: pointer to hardware structure
997 * @offset: offset within the EEPROM to be written to
998 * @data: 16 bit word to be written to the EEPROM
999 *
1000 * If ixgbe_eeprom_update_checksum is not called after this function, the
1001 * EEPROM will most likely contain an invalid checksum.
1002 **/
1003s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1004{
68c7005d 1005 hw->eeprom.ops.init_params(hw);
11afc1b1 1006
e90dd264
MR		 1007 if (offset >= hw->eeprom.word_size)
1008 return IXGBE_ERR_EEPROM;
11afc1b1 1009
e90dd264 1010 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
11afc1b1
PW		 1011}
1012
9a799d71 1013/**
68c7005d 1014 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 1015 * @hw: pointer to hardware structure
1016 * @offset: offset within the EEPROM to be read
68c7005d
ET		 1017 * @words: number of word(s)
1018 * @data: read 16 bit words(s) from EEPROM
c44ade9e 1019 *
68c7005d 1020 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 1021 **/
68c7005d
ET		 1022s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1023 u16 words, u16 *data)
c44ade9e 1024{
e90dd264 1025 s32 status;
68c7005d 1026 u16 i, count;
c44ade9e
JB		 1027
1028 hw->eeprom.ops.init_params(hw);
1029
e90dd264
MR		 1030 if (words == 0)
1031 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1032
e90dd264
MR		 1033 if (offset + words > hw->eeprom.word_size)
1034 return IXGBE_ERR_EEPROM;
c44ade9e 1035
68c7005d
ET		 1036 /*
1037 * We cannot hold synchronization semaphores for too long
1038 * to avoid other entity starvation. However it is more efficient
1039 * to read in bursts than synchronizing access for each word.
1040 */
1041 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1042 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1043 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1044
1045 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1046 count, &data[i]);
1047
e90dd264
MR		 1048 if (status)
1049 return status;
68c7005d
ET		 1050 }
1051
e90dd264 1052 return 0;
68c7005d
ET		 1053}
1054
1055/**
1056 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1057 * @hw: pointer to hardware structure
1058 * @offset: offset within the EEPROM to be read
1059 * @words: number of word(s)
1060 * @data: read 16 bit word(s) from EEPROM
1061 *
1062 * Reads 16 bit word(s) from EEPROM through bit-bang method
1063 **/
1064static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1065 u16 words, u16 *data)
1066{
1067 s32 status;
1068 u16 word_in;
1069 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1070 u16 i;
1071
c44ade9e
JB		 1072 /* Prepare the EEPROM for reading */
1073 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 1074 if (status)
1075 return status;
c44ade9e 1076
e90dd264
MR		 1077 if (ixgbe_ready_eeprom(hw) != 0) {
1078 ixgbe_release_eeprom(hw);
1079 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1080 }
1081
e90dd264
MR		 1082 for (i = 0; i < words; i++) {
1083 ixgbe_standby_eeprom(hw);
1084 /* Some SPI eeproms use the 8th address bit embedded
1085 * in the opcode
1086 */
1087 if ((hw->eeprom.address_bits == 8) &&
1088 ((offset + i) >= 128))
1089 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
c44ade9e 1090
e90dd264
MR		 1091 /* Send the READ command (opcode + addr) */
1092 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1093 IXGBE_EEPROM_OPCODE_BITS);
1094 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1095 hw->eeprom.address_bits);
1096
1097 /* Read the data. */
1098 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1099 data[i] = (word_in >> 8) | (word_in << 8);
68c7005d 1100 }
c44ade9e 1101
e90dd264
MR		 1102 /* End this read operation */
1103 ixgbe_release_eeprom(hw);
1104
1105 return 0;
68c7005d 1106}
c44ade9e 1107
68c7005d
ET		 1108/**
1109 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1110 * @hw: pointer to hardware structure
1111 * @offset: offset within the EEPROM to be read
1112 * @data: read 16 bit value from EEPROM
1113 *
1114 * Reads 16 bit value from EEPROM through bit-bang method
1115 **/
1116s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1117 u16 *data)
1118{
68c7005d
ET		 1119 hw->eeprom.ops.init_params(hw);
1120
e90dd264
MR		 1121 if (offset >= hw->eeprom.word_size)
1122 return IXGBE_ERR_EEPROM;
68c7005d 1123
e90dd264 1124 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
c44ade9e
JB		 1125}
1126
1127/**
68c7005d 1128 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1129 * @hw: pointer to hardware structure
68c7005d
ET		 1130 * @offset: offset of word in the EEPROM to read
1131 * @words: number of word(s)
1132 * @data: 16 bit word(s) from the EEPROM
9a799d71 1133 *
68c7005d 1134 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1135 **/
68c7005d
ET		 1136s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1137 u16 words, u16 *data)
9a799d71
AK		 1138{
1139 u32 eerd;
e90dd264 1140 s32 status;
68c7005d 1141 u32 i;
9a799d71 1142
c44ade9e
JB		 1143 hw->eeprom.ops.init_params(hw);
1144
e90dd264
MR		 1145 if (words == 0)
1146 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1147
e90dd264
MR		 1148 if (offset >= hw->eeprom.word_size)
1149 return IXGBE_ERR_EEPROM;
c44ade9e 1150
68c7005d 1151 for (i = 0; i < words; i++) {
d0111575 1152 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1153 IXGBE_EEPROM_RW_REG_START;
9a799d71 1154
68c7005d
ET		 1155 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1156 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1157
68c7005d
ET		 1158 if (status == 0) {
1159 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1160 IXGBE_EEPROM_RW_REG_DATA);
1161 } else {
1162 hw_dbg(hw, "Eeprom read timed out\n");
e90dd264 1163 return status;
68c7005d
ET		 1164 }
1165 }
e90dd264
MR		 1166
1167 return 0;
68c7005d 1168}
9a799d71 1169
68c7005d
ET		 1170/**
1171 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1172 * @hw: pointer to hardware structure
1173 * @offset: offset within the EEPROM to be used as a scratch pad
1174 *
1175 * Discover EEPROM page size by writing marching data at given offset.
1176 * This function is called only when we are writing a new large buffer
1177 * at given offset so the data would be overwritten anyway.
1178 **/
1179static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1180 u16 offset)
1181{
1182 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
e90dd264 1183 s32 status;
68c7005d
ET		 1184 u16 i;
1185
1186 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1187 data[i] = i;
1188
1189 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1190 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1191 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1192 hw->eeprom.word_page_size = 0;
e90dd264
MR		 1193 if (status)
1194 return status;
68c7005d
ET		 1195
1196 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
e90dd264
MR		 1197 if (status)
1198 return status;
68c7005d
ET		 1199
1200 /*
1201 * When writing in burst more than the actual page size
1202 * EEPROM address wraps around current page.
1203 */
1204 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1205
c5ffe7e1 1206 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
68c7005d 1207 hw->eeprom.word_page_size);
e90dd264 1208 return 0;
9a799d71
AK		 1209}
1210
eb9c3e3e 1211/**
68c7005d
ET		 1212 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1213 * @hw: pointer to hardware structure
1214 * @offset: offset of word in the EEPROM to read
1215 * @data: word read from the EEPROM
1216 *
1217 * Reads a 16 bit word from the EEPROM using the EERD register.
1218 **/
1219s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1220{
1221 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1222}
1223
1224/**
1225 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1226 * @hw: pointer to hardware structure
1227 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1228 * @words: number of words
1229 * @data: word(s) write to the EEPROM
eb9c3e3e 1230 *
68c7005d 1231 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1232 **/
68c7005d
ET		 1233s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1234 u16 words, u16 *data)
eb9c3e3e
ET		 1235{
1236 u32 eewr;
e90dd264 1237 s32 status;
68c7005d 1238 u16 i;
eb9c3e3e
ET		 1239
1240 hw->eeprom.ops.init_params(hw);
1241
e90dd264
MR		 1242 if (words == 0)
1243 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1244
e90dd264
MR		 1245 if (offset >= hw->eeprom.word_size)
1246 return IXGBE_ERR_EEPROM;
eb9c3e3e 1247
68c7005d
ET		 1248 for (i = 0; i < words; i++) {
1249 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1250 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1251 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1252
68c7005d 1253 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1254 if (status) {
68c7005d 1255 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1256 return status;
68c7005d 1257 }
eb9c3e3e 1258
68c7005d 1259 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1260
68c7005d 1261 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1262 if (status) {
68c7005d 1263 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1264 return status;
68c7005d 1265 }
eb9c3e3e
ET		 1266 }
1267
e90dd264 1268 return 0;
eb9c3e3e
ET		 1269}
1270
68c7005d
ET		 1271/**
1272 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1273 * @hw: pointer to hardware structure
1274 * @offset: offset of word in the EEPROM to write
1275 * @data: word write to the EEPROM
1276 *
1277 * Write a 16 bit word to the EEPROM using the EEWR register.
1278 **/
1279s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1280{
1281 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1282}
1283
9a799d71 1284/**
21ce849b 1285 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1286 * @hw: pointer to hardware structure
21ce849b 1287 * @ee_reg: EEPROM flag for polling
9a799d71 1288 *
21ce849b
MC		 1289 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1290 * read or write is done respectively.
9a799d71 1291 **/
eb9c3e3e 1292static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1293{
1294 u32 i;
1295 u32 reg;
9a799d71 1296
21ce849b
MC		 1297 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1298 if (ee_reg == IXGBE_NVM_POLL_READ)
1299 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1300 else
1301 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1302
1303 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
e90dd264 1304 return 0;
9a799d71
AK		 1305 }
1306 udelay(5);
1307 }
e90dd264 1308 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1309}
1310
c44ade9e
JB		 1311/**
1312 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1313 * @hw: pointer to hardware structure
1314 *
1315 * Prepares EEPROM for access using bit-bang method. This function should
1316 * be called before issuing a command to the EEPROM.
1317 **/
1318static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1319{
dbf893ee 1320 u32 eec;
c44ade9e
JB		 1321 u32 i;
1322
5e655105 1323 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
e90dd264 1324 return IXGBE_ERR_SWFW_SYNC;
c44ade9e 1325
9a900eca 1326 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e 1327
e90dd264
MR		 1328 /* Request EEPROM Access */
1329 eec |= IXGBE_EEC_REQ;
9a900eca 1330 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e 1331
e90dd264 1332 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
9a900eca 1333 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
e90dd264
MR		 1334 if (eec & IXGBE_EEC_GNT)
1335 break;
1336 udelay(5);
1337 }
c44ade9e 1338
e90dd264
MR		 1339 /* Release if grant not acquired */
1340 if (!(eec & IXGBE_EEC_GNT)) {
1341 eec &= ~IXGBE_EEC_REQ;
9a900eca 1342 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
e90dd264 1343 hw_dbg(hw, "Could not acquire EEPROM grant\n");
c44ade9e 1344
e90dd264
MR		 1345 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1346 return IXGBE_ERR_EEPROM;
c44ade9e 1347 }
e90dd264
MR		 1348
1349 /* Setup EEPROM for Read/Write */
1350 /* Clear CS and SK */
1351 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
9a900eca 1352 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
e90dd264
MR		 1353 IXGBE_WRITE_FLUSH(hw);
1354 udelay(1);
1355 return 0;
c44ade9e
JB		 1356}
1357
9a799d71
AK		 1358/**
1359 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1360 * @hw: pointer to hardware structure
1361 *
1362 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1363 **/
1364static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1365{
dbf893ee 1366 u32 timeout = 2000;
9a799d71
AK		 1367 u32 i;
1368 u32 swsm;
1369
9a799d71
AK		 1370 /* Get SMBI software semaphore between device drivers first */
1371 for (i = 0; i < timeout; i++) {
1372 /*
1373 * If the SMBI bit is 0 when we read it, then the bit will be
1374 * set and we have the semaphore
1375 */
9a900eca 1376 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264 1377 if (!(swsm & IXGBE_SWSM_SMBI))
9a799d71 1378 break;
d819fc52 1379 usleep_range(50, 100);
9a799d71
AK		 1380 }
1381
51275d37 1382 if (i == timeout) {
6ec1b71f 1383 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
e90dd264 1384 /* this release is particularly important because our attempts
51275d37
ET		 1385 * above to get the semaphore may have succeeded, and if there
1386 * was a timeout, we should unconditionally clear the semaphore
1387 * bits to free the driver to make progress
1388 */
1389 ixgbe_release_eeprom_semaphore(hw);
1390
d819fc52 1391 usleep_range(50, 100);
e90dd264 1392 /* one last try
51275d37
ET		 1393 * If the SMBI bit is 0 when we read it, then the bit will be
1394 * set and we have the semaphore
1395 */
9a900eca 1396 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264
MR		 1397 if (swsm & IXGBE_SWSM_SMBI) {
1398 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1399 return IXGBE_ERR_EEPROM;
1400 }
51275d37
ET		 1401 }
1402
9a799d71 1403 /* Now get the semaphore between SW/FW through the SWESMBI bit */
e90dd264 1404 for (i = 0; i < timeout; i++) {
9a900eca 1405 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
9a799d71 1406
e90dd264
MR		 1407 /* Set the SW EEPROM semaphore bit to request access */
1408 swsm |= IXGBE_SWSM_SWESMBI;
9a900eca 1409 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
9a799d71 1410
e90dd264
MR		 1411 /* If we set the bit successfully then we got the
1412 * semaphore.
1413 */
9a900eca 1414 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264
MR		 1415 if (swsm & IXGBE_SWSM_SWESMBI)
1416 break;
9a799d71 1417
e90dd264
MR		 1418 usleep_range(50, 100);
1419 }
9a799d71 1420
e90dd264
MR		 1421 /* Release semaphores and return error if SW EEPROM semaphore
1422 * was not granted because we don't have access to the EEPROM
1423 */
1424 if (i >= timeout) {
1425 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1426 ixgbe_release_eeprom_semaphore(hw);
1427 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1428 }
1429
e90dd264 1430 return 0;
9a799d71
AK		 1431}
1432
1433/**
1434 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1435 * @hw: pointer to hardware structure
1436 *
1437 * This function clears hardware semaphore bits.
1438 **/
1439static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1440{
1441 u32 swsm;
1442
9a900eca 1443 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
9a799d71
AK		 1444
1445 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1446 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
9a900eca 1447 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
3957d63d 1448 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1449}
1450
c44ade9e
JB		 1451/**
1452 * ixgbe_ready_eeprom - Polls for EEPROM ready
1453 * @hw: pointer to hardware structure
1454 **/
1455static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1456{
c44ade9e
JB		 1457 u16 i;
1458 u8 spi_stat_reg;
1459
1460 /*
1461 * Read "Status Register" repeatedly until the LSB is cleared. The
1462 * EEPROM will signal that the command has been completed by clearing
1463 * bit 0 of the internal status register. If it's not cleared within
1464 * 5 milliseconds, then error out.
1465 */
1466 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1467 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
e7cf745b 1468 IXGBE_EEPROM_OPCODE_BITS);
c44ade9e
JB		 1469 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1470 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1471 break;
1472
1473 udelay(5);
1474 ixgbe_standby_eeprom(hw);
6403eab1 1475 }
c44ade9e
JB		 1476
1477 /*
1478 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1479 * devices (and only 0-5mSec on 5V devices)
1480 */
1481 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1482 hw_dbg(hw, "SPI EEPROM Status error\n");
e90dd264 1483 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1484 }
1485
e90dd264 1486 return 0;
c44ade9e
JB		 1487}
1488
1489/**
1490 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1491 * @hw: pointer to hardware structure
1492 **/
1493static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1494{
1495 u32 eec;
1496
9a900eca 1497 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1498
1499 /* Toggle CS to flush commands */
1500 eec |= IXGBE_EEC_CS;
9a900eca 1501 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1502 IXGBE_WRITE_FLUSH(hw);
1503 udelay(1);
1504 eec &= ~IXGBE_EEC_CS;
9a900eca 1505 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1506 IXGBE_WRITE_FLUSH(hw);
1507 udelay(1);
1508}
1509
1510/**
1511 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1512 * @hw: pointer to hardware structure
1513 * @data: data to send to the EEPROM
1514 * @count: number of bits to shift out
1515 **/
1516static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 1517 u16 count)
c44ade9e
JB		 1518{
1519 u32 eec;
1520 u32 mask;
1521 u32 i;
1522
9a900eca 1523 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1524
1525 /*
1526 * Mask is used to shift "count" bits of "data" out to the EEPROM
1527 * one bit at a time. Determine the starting bit based on count
1528 */
b4f47a48 1529 mask = BIT(count - 1);
c44ade9e
JB		 1530
1531 for (i = 0; i < count; i++) {
1532 /*
1533 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1534 * "1", and then raising and then lowering the clock (the SK
1535 * bit controls the clock input to the EEPROM). A "0" is
1536 * shifted out to the EEPROM by setting "DI" to "0" and then
1537 * raising and then lowering the clock.
1538 */
1539 if (data & mask)
1540 eec |= IXGBE_EEC_DI;
1541 else
1542 eec &= ~IXGBE_EEC_DI;
1543
9a900eca 1544 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1545 IXGBE_WRITE_FLUSH(hw);
1546
1547 udelay(1);
1548
1549 ixgbe_raise_eeprom_clk(hw, &eec);
1550 ixgbe_lower_eeprom_clk(hw, &eec);
1551
1552 /*
1553 * Shift mask to signify next bit of data to shift in to the
1554 * EEPROM
1555 */
1556 mask = mask >> 1;
6403eab1 1557 }
c44ade9e
JB		 1558
1559 /* We leave the "DI" bit set to "0" when we leave this routine. */
1560 eec &= ~IXGBE_EEC_DI;
9a900eca 1561 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1562 IXGBE_WRITE_FLUSH(hw);
1563}
1564
1565/**
1566 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1567 * @hw: pointer to hardware structure
1568 **/
1569static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1570{
1571 u32 eec;
1572 u32 i;
1573 u16 data = 0;
1574
1575 /*
1576 * In order to read a register from the EEPROM, we need to shift
1577 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1578 * the clock input to the EEPROM (setting the SK bit), and then reading
1579 * the value of the "DO" bit. During this "shifting in" process the
1580 * "DI" bit should always be clear.
1581 */
9a900eca 1582 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1583
1584 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1585
1586 for (i = 0; i < count; i++) {
1587 data = data << 1;
1588 ixgbe_raise_eeprom_clk(hw, &eec);
1589
9a900eca 1590 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1591
1592 eec &= ~(IXGBE_EEC_DI);
1593 if (eec & IXGBE_EEC_DO)
1594 data |= 1;
1595
1596 ixgbe_lower_eeprom_clk(hw, &eec);
1597 }
1598
1599 return data;
1600}
1601
1602/**
1603 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1604 * @hw: pointer to hardware structure
1605 * @eec: EEC register's current value
1606 **/
1607static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1608{
1609 /*
1610 * Raise the clock input to the EEPROM
1611 * (setting the SK bit), then delay
1612 */
1613 *eec = *eec | IXGBE_EEC_SK;
9a900eca 1614 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
c44ade9e
JB		 1615 IXGBE_WRITE_FLUSH(hw);
1616 udelay(1);
1617}
1618
1619/**
1620 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1621 * @hw: pointer to hardware structure
1622 * @eecd: EECD's current value
1623 **/
1624static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1625{
1626 /*
1627 * Lower the clock input to the EEPROM (clearing the SK bit), then
1628 * delay
1629 */
1630 *eec = *eec & ~IXGBE_EEC_SK;
9a900eca 1631 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
c44ade9e
JB		 1632 IXGBE_WRITE_FLUSH(hw);
1633 udelay(1);
1634}
1635
1636/**
1637 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1638 * @hw: pointer to hardware structure
1639 **/
1640static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1641{
1642 u32 eec;
1643
9a900eca 1644 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1645
1646 eec |= IXGBE_EEC_CS; /* Pull CS high */
1647 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1648
9a900eca 1649 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1650 IXGBE_WRITE_FLUSH(hw);
1651
1652 udelay(1);
1653
1654 /* Stop requesting EEPROM access */
1655 eec &= ~IXGBE_EEC_REQ;
9a900eca 1656 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e 1657
90827996 1658 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1659
032b4325
DS		 1660 /*
1661 * Delay before attempt to obtain semaphore again to allow FW
1662 * access. semaphore_delay is in ms we need us for usleep_range
1663 */
1664 usleep_range(hw->eeprom.semaphore_delay * 1000,
1665 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1666}
1667
9a799d71 1668/**
dbf893ee 1669 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1670 * @hw: pointer to hardware structure
1671 **/
735c35af 1672s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1673{
1674 u16 i;
1675 u16 j;
1676 u16 checksum = 0;
1677 u16 length = 0;
1678 u16 pointer = 0;
1679 u16 word = 0;
1680
1681 /* Include 0x0-0x3F in the checksum */
1682 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
735c35af 1683 if (hw->eeprom.ops.read(hw, i, &word)) {
9a799d71
AK		 1684 hw_dbg(hw, "EEPROM read failed\n");
1685 break;
1686 }
1687 checksum += word;
1688 }
1689
1690 /* Include all data from pointers except for the fw pointer */
1691 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
735c35af
DS		 1692 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1693 hw_dbg(hw, "EEPROM read failed\n");
1694 return IXGBE_ERR_EEPROM;
1695 }
1696
1697 /* If the pointer seems invalid */
1698 if (pointer == 0xFFFF || pointer == 0)
1699 continue;
1700
1701 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1702 hw_dbg(hw, "EEPROM read failed\n");
1703 return IXGBE_ERR_EEPROM;
1704 }
9a799d71 1705
735c35af
DS		 1706 if (length == 0xFFFF || length == 0)
1707 continue;
9a799d71 1708
735c35af
DS		 1709 for (j = pointer + 1; j <= pointer + length; j++) {
1710 if (hw->eeprom.ops.read(hw, j, &word)) {
1711 hw_dbg(hw, "EEPROM read failed\n");
1712 return IXGBE_ERR_EEPROM;
9a799d71 1713 }
735c35af 1714 checksum += word;
9a799d71
AK		 1715 }
1716 }
1717
1718 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1719
735c35af 1720 return (s32)checksum;
9a799d71
AK		 1721}
1722
1723/**
c44ade9e 1724 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1725 * @hw: pointer to hardware structure
1726 * @checksum_val: calculated checksum
1727 *
1728 * Performs checksum calculation and validates the EEPROM checksum. If the
1729 * caller does not need checksum_val, the value can be NULL.
1730 **/
c44ade9e 1731s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 1732 u16 *checksum_val)
9a799d71
AK		 1733{
1734 s32 status;
1735 u16 checksum;
1736 u16 read_checksum = 0;
1737
1738 /*
1739 * Read the first word from the EEPROM. If this times out or fails, do
1740 * not continue or we could be in for a very long wait while every
1741 * EEPROM read fails
1742 */
c44ade9e 1743 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af
DS		 1744 if (status) {
1745 hw_dbg(hw, "EEPROM read failed\n");
1746 return status;
1747 }
9a799d71 1748
735c35af
DS		 1749 status = hw->eeprom.ops.calc_checksum(hw);
1750 if (status < 0)
1751 return status;
9a799d71 1752
735c35af 1753 checksum = (u16)(status & 0xffff);
9a799d71 1754
735c35af
DS		 1755 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1756 if (status) {
9a799d71 1757 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1758 return status;
9a799d71
AK		 1759 }
1760
735c35af
DS		 1761 /* Verify read checksum from EEPROM is the same as
1762 * calculated checksum
1763 */
1764 if (read_checksum != checksum)
1765 status = IXGBE_ERR_EEPROM_CHECKSUM;
1766
1767 /* If the user cares, return the calculated checksum */
1768 if (checksum_val)
1769 *checksum_val = checksum;
1770
9a799d71
AK		 1771 return status;
1772}
1773
c44ade9e
JB		 1774/**
1775 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1776 * @hw: pointer to hardware structure
1777 **/
1778s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1779{
1780 s32 status;
1781 u16 checksum;
1782
1783 /*
1784 * Read the first word from the EEPROM. If this times out or fails, do
1785 * not continue or we could be in for a very long wait while every
1786 * EEPROM read fails
1787 */
1788 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af 1789 if (status) {
c44ade9e 1790 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1791 return status;
c44ade9e
JB		 1792 }
1793
735c35af
DS		 1794 status = hw->eeprom.ops.calc_checksum(hw);
1795 if (status < 0)
1796 return status;
1797
1798 checksum = (u16)(status & 0xffff);
1799
1800 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1801
c44ade9e
JB		 1802 return status;
1803}
1804
9a799d71 1805/**
c44ade9e 1806 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1807 * @hw: pointer to hardware structure
9a799d71 1808 * @index: Receive address register to write
c44ade9e
JB		 1809 * @addr: Address to put into receive address register
1810 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1811 * @enable_addr: set flag that address is active
1812 *
1813 * Puts an ethernet address into a receive address register.
1814 **/
c44ade9e 1815s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 1816 u32 enable_addr)
9a799d71
AK		 1817{
1818 u32 rar_low, rar_high;
c44ade9e
JB		 1819 u32 rar_entries = hw->mac.num_rar_entries;
1820
c700f4e6
ET		 1821 /* Make sure we are using a valid rar index range */
1822 if (index >= rar_entries) {
1823 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1824 return IXGBE_ERR_INVALID_ARGUMENT;
1825 }
1826
c44ade9e
JB		 1827 /* setup VMDq pool selection before this RAR gets enabled */
1828 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1829
c700f4e6
ET		 1830 /*
1831 * HW expects these in little endian so we reverse the byte
1832 * order from network order (big endian) to little endian
1833 */
1834 rar_low = ((u32)addr[0] |
1835 ((u32)addr[1] << 8) |
1836 ((u32)addr[2] << 16) |
1837 ((u32)addr[3] << 24));
1838 /*
1839 * Some parts put the VMDq setting in the extra RAH bits,
1840 * so save everything except the lower 16 bits that hold part
1841 * of the address and the address valid bit.
1842 */
1843 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1844 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1845 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1846
c700f4e6
ET		 1847 if (enable_addr != 0)
1848 rar_high |= IXGBE_RAH_AV;
9a799d71 1849
c700f4e6
ET		 1850 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1851 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1852
1853 return 0;
1854}
1855
1856/**
1857 * ixgbe_clear_rar_generic - Remove Rx address register
1858 * @hw: pointer to hardware structure
1859 * @index: Receive address register to write
1860 *
1861 * Clears an ethernet address from a receive address register.
1862 **/
1863s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1864{
1865 u32 rar_high;
1866 u32 rar_entries = hw->mac.num_rar_entries;
1867
1868 /* Make sure we are using a valid rar index range */
c700f4e6 1869 if (index >= rar_entries) {
c44ade9e 1870 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1871 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1872 }
1873
c700f4e6
ET		 1874 /*
1875 * Some parts put the VMDq setting in the extra RAH bits,
1876 * so save everything except the lower 16 bits that hold part
1877 * of the address and the address valid bit.
1878 */
1879 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1880 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1881
1882 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1883 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1884
c44ade9e
JB		 1885 /* clear VMDq pool/queue selection for this RAR */
1886 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1887
1888 return 0;
1889}
1890
c44ade9e
JB		 1891/**
1892 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1893 * @hw: pointer to hardware structure
1894 *
1895 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1896 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1897 * the receiver is in reset when the routine is called.
1898 **/
c44ade9e 1899s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1900{
1901 u32 i;
2c5645cf 1902 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1903
1904 /*
1905 * If the current mac address is valid, assume it is a software override
1906 * to the permanent address.
1907 * Otherwise, use the permanent address from the eeprom.
1908 */
f8ebc683 1909 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1910 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1911 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1912
ce7194d8 1913 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1914 } else {
1915 /* Setup the receive address. */
1916 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1917 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1918
c44ade9e 1919 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71 1920 }
6e982aea
AD		 1921
1922 /* clear VMDq pool/queue selection for RAR 0 */
1923 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1924
c44ade9e 1925 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1926
1927 hw->addr_ctrl.rar_used_count = 1;
1928
1929 /* Zero out the other receive addresses. */
c44ade9e 1930 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1931 for (i = 1; i < rar_entries; i++) {
1932 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1933 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1934 }
1935
1936 /* Clear the MTA */
9a799d71
AK		 1937 hw->addr_ctrl.mta_in_use = 0;
1938 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1939
1940 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1941 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1942 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1943
c44ade9e
JB		 1944 if (hw->mac.ops.init_uta_tables)
1945 hw->mac.ops.init_uta_tables(hw);
1946
9a799d71
AK		 1947 return 0;
1948}
1949
1950/**
1951 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1952 * @hw: pointer to hardware structure
1953 * @mc_addr: the multicast address
1954 *
1955 * Extracts the 12 bits, from a multicast address, to determine which
1956 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1957 * incoming rx multicast addresses, to determine the bit-vector to check in
1958 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1959 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1960 * to mc_filter_type.
1961 **/
1962static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1963{
1964 u32 vector = 0;
1965
1966 switch (hw->mac.mc_filter_type) {
b4617240 1967 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1968 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1969 break;
b4617240 1970 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1971 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1972 break;
b4617240 1973 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1974 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1975 break;
b4617240 1976 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1977 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1978 break;
b4617240 1979 default: /* Invalid mc_filter_type */
9a799d71
AK		 1980 hw_dbg(hw, "MC filter type param set incorrectly\n");
1981 break;
1982 }
1983
1984 /* vector can only be 12-bits or boundary will be exceeded */
1985 vector &= 0xFFF;
1986 return vector;
1987}
1988
1989/**
1990 * ixgbe_set_mta - Set bit-vector in multicast table
1991 * @hw: pointer to hardware structure
1992 * @hash_value: Multicast address hash value
1993 *
1994 * Sets the bit-vector in the multicast table.
1995 **/
1996static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1997{
1998 u32 vector;
1999 u32 vector_bit;
2000 u32 vector_reg;
9a799d71
AK		 2001
2002 hw->addr_ctrl.mta_in_use++;
2003
2004 vector = ixgbe_mta_vector(hw, mc_addr);
2005 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2006
2007 /*
2008 * The MTA is a register array of 128 32-bit registers. It is treated
2009 * like an array of 4096 bits. We want to set bit
2010 * BitArray[vector_value]. So we figure out what register the bit is
2011 * in, read it, OR in the new bit, then write back the new value. The
2012 * register is determined by the upper 7 bits of the vector value and
2013 * the bit within that register are determined by the lower 5 bits of
2014 * the value.
2015 */
2016 vector_reg = (vector >> 5) & 0x7F;
2017 vector_bit = vector & 0x1F;
b4f47a48 2018 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);
9a799d71
AK		 2019}
2020
9a799d71 2021/**
c44ade9e 2022 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 2023 * @hw: pointer to hardware structure
2853eb89 2024 * @netdev: pointer to net device structure
9a799d71
AK		 2025 *
2026 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 2027 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 2028 * registers for the first multicast addresses, and hashes the rest into the
2029 * multicast table.
2030 **/
2853eb89
JP		 2031s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2032 struct net_device *netdev)
9a799d71 2033{
22bedad3 2034 struct netdev_hw_addr *ha;
9a799d71 2035 u32 i;
9a799d71
AK		 2036
2037 /*
2038 * Set the new number of MC addresses that we are being requested to
2039 * use.
2040 */
2853eb89 2041 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2042 hw->addr_ctrl.mta_in_use = 0;
2043
80960ab0 2044 /* Clear mta_shadow */
9a799d71 2045 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2046 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2047
80960ab0 2048 /* Update mta shadow */
22bedad3 2049 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2050 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2051 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2052 }
2053
2054 /* Enable mta */
80960ab0
ET		 2055 for (i = 0; i < hw->mac.mcft_size; i++)
2056 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2057 hw->mac.mta_shadow[i]);
2058
9a799d71
AK		 2059 if (hw->addr_ctrl.mta_in_use > 0)
2060 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
e7cf745b 2061 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2062
c44ade9e 2063 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2064 return 0;
2065}
2066
2067/**
c44ade9e 2068 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2069 * @hw: pointer to hardware structure
2070 *
c44ade9e 2071 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2072 **/
c44ade9e 2073s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2074{
c44ade9e 2075 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2076
c44ade9e
JB		 2077 if (a->mta_in_use > 0)
2078 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
e7cf745b 2079 hw->mac.mc_filter_type);
9a799d71
AK		 2080
2081 return 0;
2082}
2083
2084/**
c44ade9e 2085 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2086 * @hw: pointer to hardware structure
9a799d71 2087 *
c44ade9e 2088 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2089 **/
c44ade9e 2090s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2091{
c44ade9e 2092 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2093
c44ade9e
JB		 2094 if (a->mta_in_use > 0)
2095 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2096
2097 return 0;
2098}
2099
11afc1b1 2100/**
620fa036 2101 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2102 * @hw: pointer to hardware structure
11afc1b1
PW		 2103 *
2104 * Enable flow control according to the current settings.
2105 **/
041441d0 2106s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1 2107{
620fa036 2108 u32 mflcn_reg, fccfg_reg;
11afc1b1 2109 u32 reg;
16b61beb 2110 u32 fcrtl, fcrth;
041441d0 2111 int i;
70b77628 2112
e5776620 2113 /* Validate the water mark configuration. */
e90dd264
MR		 2114 if (!hw->fc.pause_time)
2115 return IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2116
e5776620
JK		 2117 /* Low water mark of zero causes XOFF floods */
2118 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2119 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2120 hw->fc.high_water[i]) {
2121 if (!hw->fc.low_water[i] ||
2122 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2123 hw_dbg(hw, "Invalid water mark configuration\n");
e90dd264 2124 return IXGBE_ERR_INVALID_LINK_SETTINGS;
e5776620
JK		 2125 }
2126 }
2127 }
2128
620fa036 2129 /* Negotiate the fc mode to use */
786e9a5f 2130 ixgbe_fc_autoneg(hw);
11afc1b1 2131
620fa036 2132 /* Disable any previous flow control settings */
11afc1b1 2133 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2134 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2135
2136 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2137 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2138
2139 /*
2140 * The possible values of fc.current_mode are:
2141 * 0: Flow control is completely disabled
2142 * 1: Rx flow control is enabled (we can receive pause frames,
2143 * but not send pause frames).
bb3daa4a
PW		 2144 * 2: Tx flow control is enabled (we can send pause frames but
2145 * we do not support receiving pause frames).
11afc1b1
PW		 2146 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2147 * other: Invalid.
2148 */
2149 switch (hw->fc.current_mode) {
2150 case ixgbe_fc_none:
620fa036
MC		 2151 /*
2152 * Flow control is disabled by software override or autoneg.
2153 * The code below will actually disable it in the HW.
2154 */
11afc1b1
PW		 2155 break;
2156 case ixgbe_fc_rx_pause:
2157 /*
2158 * Rx Flow control is enabled and Tx Flow control is
2159 * disabled by software override. Since there really
2160 * isn't a way to advertise that we are capable of RX
2161 * Pause ONLY, we will advertise that we support both
2162 * symmetric and asymmetric Rx PAUSE. Later, we will
2163 * disable the adapter's ability to send PAUSE frames.
2164 */
2165 mflcn_reg |= IXGBE_MFLCN_RFCE;
2166 break;
2167 case ixgbe_fc_tx_pause:
2168 /*
2169 * Tx Flow control is enabled, and Rx Flow control is
2170 * disabled by software override.
2171 */
2172 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2173 break;
2174 case ixgbe_fc_full:
2175 /* Flow control (both Rx and Tx) is enabled by SW override. */
2176 mflcn_reg |= IXGBE_MFLCN_RFCE;
2177 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2178 break;
2179 default:
2180 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 2181 return IXGBE_ERR_CONFIG;
11afc1b1
PW		 2182 }
2183
620fa036 2184 /* Set 802.3x based flow control settings. */
2132d381 2185 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2186 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2187 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2188
041441d0
AD		 2189 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2190 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2191 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2192 hw->fc.high_water[i]) {
e5776620 2193 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
041441d0
AD		 2194 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2195 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2196 } else {
2197 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2198 /*
2199 * In order to prevent Tx hangs when the internal Tx
2200 * switch is enabled we must set the high water mark
bc1fc64f
MR		 2201 * to the Rx packet buffer size - 24KB. This allows
2202 * the Tx switch to function even under heavy Rx
2203 * workloads.
041441d0 2204 */
bc1fc64f 2205 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
041441d0 2206 }
11afc1b1 2207
041441d0
AD		 2208 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2209 }
16b61beb 2210
11afc1b1 2211 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2212 reg = hw->fc.pause_time * 0x00010001;
2213 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2214 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2215
2216 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1 2217
e90dd264 2218 return 0;
11afc1b1
PW		 2219}
2220
0ecc061d 2221/**
67a79df2 2222 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2223 * @hw: pointer to hardware structure
67a79df2
AD		 2224 * @adv_reg: flow control advertised settings
2225 * @lp_reg: link partner's flow control settings
2226 * @adv_sym: symmetric pause bit in advertisement
2227 * @adv_asm: asymmetric pause bit in advertisement
2228 * @lp_sym: symmetric pause bit in link partner advertisement
2229 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2230 *
67a79df2
AD		 2231 * Find the intersection between advertised settings and link partner's
2232 * advertised settings
0ecc061d 2233 **/
67a79df2
AD		 2234static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2235 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2236{
67a79df2
AD		 2237 if ((!(adv_reg)) || (!(lp_reg)))
2238 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2239
67a79df2
AD		 2240 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2241 /*
2242 * Now we need to check if the user selected Rx ONLY
2243 * of pause frames. In this case, we had to advertise
2244 * FULL flow control because we could not advertise RX
2245 * ONLY. Hence, we must now check to see if we need to
2246 * turn OFF the TRANSMISSION of PAUSE frames.
2247 */
2248 if (hw->fc.requested_mode == ixgbe_fc_full) {
2249 hw->fc.current_mode = ixgbe_fc_full;
2250 hw_dbg(hw, "Flow Control = FULL.\n");
2251 } else {
2252 hw->fc.current_mode = ixgbe_fc_rx_pause;
2253 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2254 }
2255 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2256 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2257 hw->fc.current_mode = ixgbe_fc_tx_pause;
2258 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2259 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2260 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2261 hw->fc.current_mode = ixgbe_fc_rx_pause;
2262 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2263 } else {
67a79df2
AD		 2264 hw->fc.current_mode = ixgbe_fc_none;
2265 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2266 }
67a79df2 2267 return 0;
0b0c2b31
ET		 2268}
2269
2270/**
2271 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2272 * @hw: pointer to hardware structure
2273 *
2274 * Enable flow control according on 1 gig fiber.
2275 **/
2276static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2277{
2278 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
e90dd264 2279 s32 ret_val;
539e5f02
PWJ		 2280
2281 /*
2282 * On multispeed fiber at 1g, bail out if
2283 * - link is up but AN did not complete, or if
2284 * - link is up and AN completed but timed out
2285 */
0b0c2b31
ET		 2286
2287 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2288 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2289 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
e90dd264 2290 return IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02 2291
0b0c2b31
ET		 2292 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2293 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2294
2295 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2296 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2297 IXGBE_PCS1GANA_ASM_PAUSE,
2298 IXGBE_PCS1GANA_SYM_PAUSE,
2299 IXGBE_PCS1GANA_ASM_PAUSE);
2300
0b0c2b31
ET		 2301 return ret_val;
2302}
2303
2304/**
2305 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2306 * @hw: pointer to hardware structure
2307 *
2308 * Enable flow control according to IEEE clause 37.
2309 **/
2310static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2311{
2312 u32 links2, anlp1_reg, autoc_reg, links;
e90dd264 2313 s32 ret_val;
0b0c2b31 2314
9bbe3a57 2315 /*
0b0c2b31
ET		 2316 * On backplane, bail out if
2317 * - backplane autoneg was not completed, or if
2318 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2319 */
0b0c2b31 2320 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2321 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
e90dd264 2322 return IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57 2323
0b0c2b31
ET		 2324 if (hw->mac.type == ixgbe_mac_82599EB) {
2325 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2326 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
e90dd264 2327 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2328 }
0ecc061d 2329 /*
0b0c2b31 2330 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2331 * local flow control settings accordingly
2332 */
0b0c2b31
ET		 2333 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2334 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2335
0b0c2b31
ET		 2336 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2337 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2338 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2339
0b0c2b31
ET		 2340 return ret_val;
2341}
2342
2343/**
2344 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2345 * @hw: pointer to hardware structure
2346 *
2347 * Enable flow control according to IEEE clause 37.
2348 **/
2349static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2350{
2351 u16 technology_ability_reg = 0;
2352 u16 lp_technology_ability_reg = 0;
2353
2354 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2355 MDIO_MMD_AN,
2356 &technology_ability_reg);
2357 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2358 MDIO_MMD_AN,
2359 &lp_technology_ability_reg);
2360
2361 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2362 (u32)lp_technology_ability_reg,
2363 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2364 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2365}
2366
2367/**
67a79df2 2368 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2369 * @hw: pointer to hardware structure
2370 *
67a79df2
AD		 2371 * Compares our advertised flow control capabilities to those advertised by
2372 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2373 **/
67a79df2 2374void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2375{
67a79df2
AD		 2376 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2377 ixgbe_link_speed speed;
2378 bool link_up;
11afc1b1
PW		 2379
2380 /*
67a79df2
AD		 2381 * AN should have completed when the cable was plugged in.
2382 * Look for reasons to bail out. Bail out if:
2383 * - FC autoneg is disabled, or if
2384 * - link is not up.
2385 *
2386 * Since we're being called from an LSC, link is already known to be up.
2387 * So use link_up_wait_to_complete=false.
11afc1b1 2388 */
67a79df2 2389 if (hw->fc.disable_fc_autoneg)
620fa036 2390 goto out;
11afc1b1 2391
67a79df2
AD		 2392 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2393 if (!link_up)
11afc1b1 2394 goto out;
0b0c2b31
ET		 2395
2396 switch (hw->phy.media_type) {
67a79df2 2397 /* Autoneg flow control on fiber adapters */
0b0c2b31 2398 case ixgbe_media_type_fiber:
67a79df2
AD		 2399 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2400 ret_val = ixgbe_fc_autoneg_fiber(hw);
2401 break;
2402
2403 /* Autoneg flow control on backplane adapters */
0b0c2b31 2404 case ixgbe_media_type_backplane:
67a79df2 2405 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2406 break;
2407
67a79df2 2408 /* Autoneg flow control on copper adapters */
0b0c2b31 2409 case ixgbe_media_type_copper:
73d80953 2410 if (ixgbe_device_supports_autoneg_fc(hw))
67a79df2 2411 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2412 break;
2413
2414 default:
620fa036 2415 break;
0b0c2b31 2416 }
539e5f02 2417
11afc1b1 2418out:
67a79df2
AD		 2419 if (ret_val == 0) {
2420 hw->fc.fc_was_autonegged = true;
2421 } else {
2422 hw->fc.fc_was_autonegged = false;
2423 hw->fc.current_mode = hw->fc.requested_mode;
2424 }
11afc1b1
PW		 2425}
2426
1f86c983
DS		 2427/**
2428 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2429 * @hw: pointer to hardware structure
2430 *
2431 * System-wide timeout range is encoded in PCIe Device Control2 register.
2432 *
2433 * Add 10% to specified maximum and return the number of times to poll for
2434 * completion timeout, in units of 100 microsec. Never return less than
2435 * 800 = 80 millisec.
2436 **/
2437static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2438{
1f86c983
DS		 2439 s16 devctl2;
2440 u32 pollcnt;
2441
0d7c6e00 2442 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
1f86c983
DS		 2443 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2444
2445 switch (devctl2) {
2446 case IXGBE_PCIDEVCTRL2_65_130ms:
2447 pollcnt = 1300; /* 130 millisec */
2448 break;
2449 case IXGBE_PCIDEVCTRL2_260_520ms:
2450 pollcnt = 5200; /* 520 millisec */
2451 break;
2452 case IXGBE_PCIDEVCTRL2_1_2s:
2453 pollcnt = 20000; /* 2 sec */
2454 break;
2455 case IXGBE_PCIDEVCTRL2_4_8s:
2456 pollcnt = 80000; /* 8 sec */
2457 break;
2458 case IXGBE_PCIDEVCTRL2_17_34s:
2459 pollcnt = 34000; /* 34 sec */
2460 break;
2461 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2462 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2463 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2464 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2465 default:
2466 pollcnt = 800; /* 80 millisec minimum */
2467 break;
2468 }
2469
2470 /* add 10% to spec maximum */
2471 return (pollcnt * 11) / 10;
2472}
2473
9a799d71
AK		 2474/**
2475 * ixgbe_disable_pcie_master - Disable PCI-express master access
2476 * @hw: pointer to hardware structure
2477 *
2478 * Disables PCI-Express master access and verifies there are no pending
2479 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2480 * bit hasn't caused the master requests to be disabled, else 0
2481 * is returned signifying master requests disabled.
2482 **/
ff9d1a5a 2483static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2484{
1f86c983 2485 u32 i, poll;
ff9d1a5a
ET		 2486 u16 value;
2487
2488 /* Always set this bit to ensure any future transactions are blocked */
2489 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2490
48b44612
MR		 2491 /* Poll for bit to read as set */
2492 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2493 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
2494 break;
2495 usleep_range(100, 120);
2496 }
2497 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) {
2498 hw_dbg(hw, "GIO disable did not set - requesting resets\n");
2499 goto gio_disable_fail;
2500 }
2501
ff9d1a5a 2502 /* Exit if master requests are blocked */
14438464
MR		 2503 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2504 ixgbe_removed(hw->hw_addr))
e90dd264 2505 return 0;
9a799d71 2506
ff9d1a5a 2507 /* Poll for master request bit to clear */
9a799d71 2508 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2509 udelay(100);
ff9d1a5a 2510 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
e90dd264 2511 return 0;
a4297dc2
ET		 2512 }
2513
ff9d1a5a
ET		 2514 /*
2515 * Two consecutive resets are required via CTRL.RST per datasheet
2516 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2517 * of this need. The first reset prevents new master requests from
2518 * being issued by our device. We then must wait 1usec or more for any
2519 * remaining completions from the PCIe bus to trickle in, and then reset
2520 * again to clear out any effects they may have had on our device.
2521 */
a4297dc2 2522 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
48b44612 2523gio_disable_fail:
ff9d1a5a 2524 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2 2525
7fc15103
MR		 2526 if (hw->mac.type >= ixgbe_mac_X550)
2527 return 0;
2528
a4297dc2
ET		 2529 /*
2530 * Before proceeding, make sure that the PCIe block does not have
2531 * transactions pending.
2532 */
1f86c983
DS		 2533 poll = ixgbe_pcie_timeout_poll(hw);
2534 for (i = 0; i < poll; i++) {
9a799d71 2535 udelay(100);
14438464
MR		 2536 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2537 if (ixgbe_removed(hw->hw_addr))
e90dd264 2538 return 0;
ff9d1a5a 2539 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
e90dd264 2540 return 0;
9a799d71
AK		 2541 }
2542
ff9d1a5a 2543 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
e90dd264 2544 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
9a799d71
AK		 2545}
2546
9a799d71 2547/**
c44ade9e 2548 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2549 * @hw: pointer to hardware structure
c44ade9e 2550 * @mask: Mask to specify which semaphore to acquire
9a799d71 2551 *
da74cd4a 2552 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2553 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2554 **/
030eaece 2555s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71 2556{
674c18b2 2557 u32 gssr = 0;
9a799d71
AK		 2558 u32 swmask = mask;
2559 u32 fwmask = mask << 5;
674c18b2
ET		 2560 u32 timeout = 200;
2561 u32 i;
9a799d71 2562
674c18b2 2563 for (i = 0; i < timeout; i++) {
dbf893ee 2564 /*
674c18b2
ET		 2565 * SW NVM semaphore bit is used for access to all
2566 * SW_FW_SYNC bits (not just NVM)
dbf893ee 2567 */
9a799d71 2568 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2569 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2570
2571 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
674c18b2
ET		 2572 if (!(gssr & (fwmask | swmask))) {
2573 gssr |= swmask;
2574 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2575 ixgbe_release_eeprom_semaphore(hw);
2576 return 0;
2577 } else {
2578 /* Resource is currently in use by FW or SW */
2579 ixgbe_release_eeprom_semaphore(hw);
2580 usleep_range(5000, 10000);
2581 }
9a799d71
AK		 2582 }
2583
674c18b2
ET		 2584 /* If time expired clear the bits holding the lock and retry */
2585 if (gssr & (fwmask | swmask))
2586 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
9a799d71 2587
674c18b2
ET		 2588 usleep_range(5000, 10000);
2589 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2590}
2591
2592/**
2593 * ixgbe_release_swfw_sync - Release SWFW semaphore
2594 * @hw: pointer to hardware structure
c44ade9e 2595 * @mask: Mask to specify which semaphore to release
9a799d71 2596 *
da74cd4a 2597 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2598 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2599 **/
030eaece 2600void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71
AK		 2601{
2602 u32 gssr;
2603 u32 swmask = mask;
2604
2605 ixgbe_get_eeprom_semaphore(hw);
2606
2607 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2608 gssr &= ~swmask;
2609 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2610
2611 ixgbe_release_eeprom_semaphore(hw);
2612}
2613
429d6a3b
DS		 2614/**
2615 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2616 * @hw: pointer to hardware structure
2617 * @reg_val: Value we read from AUTOC
2618 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2619 * true in this the generic case.
2620 *
2621 * The default case requires no protection so just to the register read.
2622 **/
2623s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2624{
2625 *locked = false;
2626 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2627 return 0;
2628}
2629
2630/**
2631 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2632 * @hw: pointer to hardware structure
2633 * @reg_val: value to write to AUTOC
2634 * @locked: bool to indicate whether the SW/FW lock was already taken by
2635 * previous read.
2636 **/
2637s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2638{
2639 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2640 return 0;
2641}
2642
d2f5e7f3
AS		 2643/**
2644 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2645 * @hw: pointer to hardware structure
2646 *
2647 * Stops the receive data path and waits for the HW to internally
2648 * empty the Rx security block.
2649 **/
2650s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2651{
2652#define IXGBE_MAX_SECRX_POLL 40
2653 int i;
2654 int secrxreg;
2655
2656 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2657 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2658 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2659 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2660 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2661 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2662 break;
2663 else
2664 /* Use interrupt-safe sleep just in case */
db76ad47 2665 udelay(1000);
d2f5e7f3
AS		 2666 }
2667
2668 /* For informational purposes only */
2669 if (i >= IXGBE_MAX_SECRX_POLL)
6ec1b71f 2670 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
d2f5e7f3
AS		 2671
2672 return 0;
2673
2674}
2675
2676/**
2677 * ixgbe_enable_rx_buff - Enables the receive data path
2678 * @hw: pointer to hardware structure
2679 *
2680 * Enables the receive data path
2681 **/
2682s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2683{
310ea123 2684 u32 secrxreg;
d2f5e7f3
AS		 2685
2686 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2687 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2688 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2689 IXGBE_WRITE_FLUSH(hw);
2690
2691 return 0;
2692}
2693
11afc1b1
PW		 2694/**
2695 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2696 * @hw: pointer to hardware structure
2697 * @regval: register value to write to RXCTRL
2698 *
2699 * Enables the Rx DMA unit
2700 **/
2701s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2702{
1f9ac57c
DS		 2703 if (regval & IXGBE_RXCTRL_RXEN)
2704 hw->mac.ops.enable_rx(hw);
2705 else
2706 hw->mac.ops.disable_rx(hw);
11afc1b1
PW		 2707
2708 return 0;
2709}
87c12017
PW		 2710
2711/**
2712 * ixgbe_blink_led_start_generic - Blink LED based on index.
2713 * @hw: pointer to hardware structure
2714 * @index: led number to blink
2715 **/
2716s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2717{
2718 ixgbe_link_speed speed = 0;
3db1cd5c 2719 bool link_up = false;
87c12017
PW		 2720 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2721 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2722 bool locked = false;
e90dd264 2723 s32 ret_val;
87c12017 2724
003287e0
DS		 2725 if (index > 3)
2726 return IXGBE_ERR_PARAM;
2727
87c12017
PW		 2728 /*
2729 * Link must be up to auto-blink the LEDs;
2730 * Force it if link is down.
2731 */
2732 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2733
2734 if (!link_up) {
429d6a3b 2735 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2736 if (ret_val)
e90dd264 2737 return ret_val;
d7bbcd32 2738
50ac58ba 2739 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2740 autoc_reg |= IXGBE_AUTOC_FLU;
429d6a3b
DS		 2741
2742 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2743 if (ret_val)
e90dd264 2744 return ret_val;
429d6a3b 2745
945a5151 2746 IXGBE_WRITE_FLUSH(hw);
d7bbcd32 2747
032b4325 2748 usleep_range(10000, 20000);
87c12017
PW		 2749 }
2750
2751 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2752 led_reg |= IXGBE_LED_BLINK(index);
2753 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2754 IXGBE_WRITE_FLUSH(hw);
2755
e90dd264 2756 return 0;
87c12017
PW		 2757}
2758
2759/**
2760 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2761 * @hw: pointer to hardware structure
2762 * @index: led number to stop blinking
2763 **/
2764s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2765{
429d6a3b 2766 u32 autoc_reg = 0;
87c12017 2767 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2768 bool locked = false;
e90dd264 2769 s32 ret_val;
d7bbcd32 2770
003287e0
DS		 2771 if (index > 3)
2772 return IXGBE_ERR_PARAM;
2773
429d6a3b 2774 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2775 if (ret_val)
e90dd264 2776 return ret_val;
87c12017
PW		 2777
2778 autoc_reg &= ~IXGBE_AUTOC_FLU;
2779 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2780
429d6a3b 2781 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2782 if (ret_val)
e90dd264 2783 return ret_val;
d7bbcd32 2784
87c12017
PW		 2785 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2786 led_reg &= ~IXGBE_LED_BLINK(index);
2787 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2788 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2789 IXGBE_WRITE_FLUSH(hw);
2790
e90dd264 2791 return 0;
87c12017 2792}
21ce849b
MC		 2793
2794/**
2795 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2796 * @hw: pointer to hardware structure
2797 * @san_mac_offset: SAN MAC address offset
2798 *
2799 * This function will read the EEPROM location for the SAN MAC address
2800 * pointer, and returns the value at that location. This is used in both
2801 * get and set mac_addr routines.
2802 **/
2803static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
e7cf745b 2804 u16 *san_mac_offset)
21ce849b 2805{
be0c27b4
MR		 2806 s32 ret_val;
2807
21ce849b
MC		 2808 /*
2809 * First read the EEPROM pointer to see if the MAC addresses are
2810 * available.
2811 */
be0c27b4
MR		 2812 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2813 san_mac_offset);
2814 if (ret_val)
2815 hw_err(hw, "eeprom read at offset %d failed\n",
2816 IXGBE_SAN_MAC_ADDR_PTR);
21ce849b 2817
be0c27b4 2818 return ret_val;
21ce849b
MC		 2819}
2820
2821/**
2822 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2823 * @hw: pointer to hardware structure
2824 * @san_mac_addr: SAN MAC address
2825 *
2826 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2827 * per-port, so set_lan_id() must be called before reading the addresses.
2828 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2829 * upon for non-SFP connections, so we must call it here.
2830 **/
2831s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2832{
2833 u16 san_mac_data, san_mac_offset;
2834 u8 i;
be0c27b4 2835 s32 ret_val;
21ce849b
MC		 2836
2837 /*
2838 * First read the EEPROM pointer to see if the MAC addresses are
2839 * available. If they're not, no point in calling set_lan_id() here.
2840 */
be0c27b4
MR		 2841 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2842 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
21ce849b 2843
be0c27b4 2844 goto san_mac_addr_clr;
21ce849b
MC		 2845
2846 /* make sure we know which port we need to program */
2847 hw->mac.ops.set_lan_id(hw);
2848 /* apply the port offset to the address offset */
2849 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
e7cf745b 2850 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
21ce849b 2851 for (i = 0; i < 3; i++) {
be0c27b4
MR		 2852 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2853 &san_mac_data);
2854 if (ret_val) {
2855 hw_err(hw, "eeprom read at offset %d failed\n",
2856 san_mac_offset);
2857 goto san_mac_addr_clr;
2858 }
21ce849b
MC		 2859 san_mac_addr[i * 2] = (u8)(san_mac_data);
2860 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2861 san_mac_offset++;
2862 }
21ce849b 2863 return 0;
be0c27b4
MR		 2864
2865san_mac_addr_clr:
2866 /* No addresses available in this EEPROM. It's not necessarily an
2867 * error though, so just wipe the local address and return.
2868 */
2869 for (i = 0; i < 6; i++)
2870 san_mac_addr[i] = 0xFF;
2871 return ret_val;
21ce849b
MC		 2872}
2873
2874/**
2875 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2876 * @hw: pointer to hardware structure
2877 *
2878 * Read PCIe configuration space, and get the MSI-X vector count from
2879 * the capabilities table.
2880 **/
71161302 2881u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b 2882{
e90dd264 2883 u16 msix_count;
71161302
ET		 2884 u16 max_msix_count;
2885 u16 pcie_offset;
2886
2887 switch (hw->mac.type) {
2888 case ixgbe_mac_82598EB:
2889 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2890 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2891 break;
2892 case ixgbe_mac_82599EB:
2893 case ixgbe_mac_X540:
9a75a1ac
DS		 2894 case ixgbe_mac_X550:
2895 case ixgbe_mac_X550EM_x:
49425dfc 2896 case ixgbe_mac_x550em_a:
71161302
ET		 2897 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2898 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2899 break;
2900 default:
e90dd264 2901 return 1;
71161302
ET		 2902 }
2903
14438464
MR		 2904 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2905 if (ixgbe_removed(hw->hw_addr))
2906 msix_count = 0;
21ce849b
MC		 2907 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2908
71161302 2909 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2910 msix_count++;
2911
71161302
ET		 2912 if (msix_count > max_msix_count)
2913 msix_count = max_msix_count;
2914
21ce849b
MC		 2915 return msix_count;
2916}
2917
2918/**
2919 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2920 * @hw: pointer to hardware struct
2921 * @rar: receive address register index to disassociate
2922 * @vmdq: VMDq pool index to remove from the rar
2923 **/
2924s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2925{
2926 u32 mpsar_lo, mpsar_hi;
2927 u32 rar_entries = hw->mac.num_rar_entries;
2928
c700f4e6
ET		 2929 /* Make sure we are using a valid rar index range */
2930 if (rar >= rar_entries) {
2931 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2932 return IXGBE_ERR_INVALID_ARGUMENT;
2933 }
21ce849b 2934
c700f4e6
ET		 2935 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2936 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2937
19458bd4 2938 if (ixgbe_removed(hw->hw_addr))
e90dd264 2939 return 0;
19458bd4 2940
c700f4e6 2941 if (!mpsar_lo && !mpsar_hi)
e90dd264 2942 return 0;
21ce849b 2943
c700f4e6
ET		 2944 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2945 if (mpsar_lo) {
2946 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2947 mpsar_lo = 0;
2948 }
2949 if (mpsar_hi) {
2950 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2951 mpsar_hi = 0;
2952 }
2953 } else if (vmdq < 32) {
b4f47a48 2954 mpsar_lo &= ~BIT(vmdq);
c700f4e6 2955 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2956 } else {
b4f47a48 2957 mpsar_hi &= ~BIT(vmdq - 32);
c700f4e6 2958 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2959 }
2960
c700f4e6 2961 /* was that the last pool using this rar? */
c10ac75a
AD		 2962 if (mpsar_lo == 0 && mpsar_hi == 0 &&
2963 rar != 0 && rar != hw->mac.san_mac_rar_index)
c700f4e6 2964 hw->mac.ops.clear_rar(hw, rar);
c10ac75a 2965
21ce849b
MC		 2966 return 0;
2967}
2968
2969/**
2970 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2971 * @hw: pointer to hardware struct
2972 * @rar: receive address register index to associate with a VMDq index
2973 * @vmdq: VMDq pool index
2974 **/
2975s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2976{
2977 u32 mpsar;
2978 u32 rar_entries = hw->mac.num_rar_entries;
2979
c700f4e6
ET		 2980 /* Make sure we are using a valid rar index range */
2981 if (rar >= rar_entries) {
21ce849b 2982 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2983 return IXGBE_ERR_INVALID_ARGUMENT;
2984 }
2985
2986 if (vmdq < 32) {
2987 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
b4f47a48 2988 mpsar |= BIT(vmdq);
c700f4e6
ET		 2989 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2990 } else {
2991 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
b4f47a48 2992 mpsar |= BIT(vmdq - 32);
c700f4e6 2993 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2994 }
2995 return 0;
2996}
2997
7fa7c9dc
AD		 2998/**
2999 * This function should only be involved in the IOV mode.
3000 * In IOV mode, Default pool is next pool after the number of
3001 * VFs advertized and not 0.
3002 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3003 *
3004 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3005 * @hw: pointer to hardware struct
3006 * @vmdq: VMDq pool index
3007 **/
3008s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3009{
3010 u32 rar = hw->mac.san_mac_rar_index;
3011
3012 if (vmdq < 32) {
b4f47a48 3013 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));
7fa7c9dc
AD		 3014 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3015 } else {
3016 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
b4f47a48 3017 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));
7fa7c9dc
AD		 3018 }
3019
3020 return 0;
3021}
3022
21ce849b
MC		 3023/**
3024 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3025 * @hw: pointer to hardware structure
3026 **/
3027s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3028{
3029 int i;
3030
21ce849b
MC		 3031 for (i = 0; i < 128; i++)
3032 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3033
3034 return 0;
3035}
3036
3037/**
3038 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3039 * @hw: pointer to hardware structure
3040 * @vlan: VLAN id to write to VLAN filter
3041 *
3042 * return the VLVF index where this VLAN id should be placed
3043 *
3044 **/
b6488b66 3045static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
21ce849b 3046{
b6488b66 3047 s32 regindex, first_empty_slot;
c2bc9ce9 3048 u32 bits;
21ce849b
MC		 3049
3050 /* short cut the special case */
3051 if (vlan == 0)
3052 return 0;
3053
b6488b66
AD		 3054 /* if vlvf_bypass is set we don't want to use an empty slot, we
3055 * will simply bypass the VLVF if there are no entries present in the
3056 * VLVF that contain our VLAN
3057 */
3058 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3059
c2bc9ce9
AD		 3060 /* add VLAN enable bit for comparison */
3061 vlan |= IXGBE_VLVF_VIEN;
3062
3063 /* Search for the vlan id in the VLVF entries. Save off the first empty
3064 * slot found along the way.
3065 *
3066 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3067 */
3068 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
21ce849b 3069 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
c2bc9ce9
AD		 3070 if (bits == vlan)
3071 return regindex;
3072 if (!first_empty_slot && !bits)
21ce849b 3073 first_empty_slot = regindex;
21ce849b
MC		 3074 }
3075
c2bc9ce9
AD		 3076 /* If we are here then we didn't find the VLAN. Return first empty
3077 * slot we found during our search, else error.
3078 */
3079 if (!first_empty_slot)
3080 hw_dbg(hw, "No space in VLVF.\n");
21ce849b 3081
c2bc9ce9 3082 return first_empty_slot ? : IXGBE_ERR_NO_SPACE;
21ce849b
MC		 3083}
3084
3085/**
3086 * ixgbe_set_vfta_generic - Set VLAN filter table
3087 * @hw: pointer to hardware structure
3088 * @vlan: VLAN id to write to VLAN filter
3089 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3090 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
b6488b66 3091 * @vlvf_bypass: boolean flag indicating updating default pool is okay
21ce849b
MC		 3092 *
3093 * Turn on/off specified VLAN in the VLAN filter table.
3094 **/
3095s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
b6488b66 3096 bool vlan_on, bool vlvf_bypass)
21ce849b 3097{
5ac736a6 3098 u32 regidx, vfta_delta, vfta, bits;
63d9379a 3099 s32 vlvf_index;
21ce849b 3100
5ac736a6 3101 if ((vlan > 4095) || (vind > 63))
21ce849b
MC		 3102 return IXGBE_ERR_PARAM;
3103
3104 /*
3105 * this is a 2 part operation - first the VFTA, then the
3106 * VLVF and VLVFB if VT Mode is set
3107 * We don't write the VFTA until we know the VLVF part succeeded.
3108 */
3109
3110 /* Part 1
3111 * The VFTA is a bitstring made up of 128 32-bit registers
3112 * that enable the particular VLAN id, much like the MTA:
3113 * bits[11-5]: which register
3114 * bits[4-0]: which bit in the register
3115 */
c18fbd5f 3116 regidx = vlan / 32;
b4f47a48 3117 vfta_delta = BIT(vlan % 32);
c18fbd5f
AD		 3118 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3119
3120 /* vfta_delta represents the difference between the current value
3121 * of vfta and the value we want in the register. Since the diff
3122 * is an XOR mask we can just update vfta using an XOR.
3123 */
3124 vfta_delta &= vlan_on ? ~vfta : vfta;
3125 vfta ^= vfta_delta;
21ce849b
MC		 3126
3127 /* Part 2
3128 * If VT Mode is set
3129 * Either vlan_on
3130 * make sure the vlan is in VLVF
3131 * set the vind bit in the matching VLVFB
3132 * Or !vlan_on
3133 * clear the pool bit and possibly the vind
3134 */
63d9379a
AD		 3135 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3136 goto vfta_update;
3137
b6488b66
AD		 3138 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3139 if (vlvf_index < 0) {
3140 if (vlvf_bypass)
3141 goto vfta_update;
63d9379a 3142 return vlvf_index;
b6488b66 3143 }
63d9379a 3144
5ac736a6
AD		 3145 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3146
3147 /* set the pool bit */
b4f47a48 3148 bits |= BIT(vind % 32);
5ac736a6
AD		 3149 if (vlan_on)
3150 goto vlvf_update;
3151
3152 /* clear the pool bit */
b4f47a48 3153 bits ^= BIT(vind % 32);
5ac736a6
AD		 3154
3155 if (!bits &&
3156 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3157 /* Clear VFTA first, then disable VLVF. Otherwise
3158 * we run the risk of stray packets leaking into
3159 * the PF via the default pool
3160 */
3161 if (vfta_delta)
3162 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3163
3164 /* disable VLVF and clear remaining bit from pool */
3165 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3166 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
3167
3168 return 0;
21ce849b
MC		 3169 }
3170
63d9379a
AD		 3171 /* If there are still bits set in the VLVFB registers
3172 * for the VLAN ID indicated we need to see if the
3173 * caller is requesting that we clear the VFTA entry bit.
3174 * If the caller has requested that we clear the VFTA
3175 * entry bit but there are still pools/VFs using this VLAN
3176 * ID entry then ignore the request. We're not worried
3177 * about the case where we're turning the VFTA VLAN ID
3178 * entry bit on, only when requested to turn it off as
3179 * there may be multiple pools and/or VFs using the
3180 * VLAN ID entry. In that case we cannot clear the
3181 * VFTA bit until all pools/VFs using that VLAN ID have also
3182 * been cleared. This will be indicated by "bits" being
3183 * zero.
3184 */
5ac736a6 3185 vfta_delta = 0;
63d9379a 3186
5ac736a6
AD		 3187vlvf_update:
3188 /* record pool change and enable VLAN ID if not already enabled */
3189 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
3190 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
63d9379a
AD		 3191
3192vfta_update:
5ac736a6 3193 /* Update VFTA now that we are ready for traffic */
c18fbd5f
AD		 3194 if (vfta_delta)
3195 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
21ce849b
MC		 3196
3197 return 0;
3198}
3199
3200/**
3201 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3202 * @hw: pointer to hardware structure
3203 *
3204 * Clears the VLAN filer table, and the VMDq index associated with the filter
3205 **/
3206s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3207{
3208 u32 offset;
3209
3210 for (offset = 0; offset < hw->mac.vft_size; offset++)
3211 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3212
3213 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3214 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
5ac736a6
AD		 3215 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3216 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
21ce849b
MC		 3217 }
3218
3219 return 0;
3220}
3221
aac9e053
DS		 3222/**
3223 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
3224 * @hw: pointer to hardware structure
3225 *
3226 * Contains the logic to identify if we need to verify link for the
3227 * crosstalk fix
3228 **/
3229static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
3230{
3231 /* Does FW say we need the fix */
3232 if (!hw->need_crosstalk_fix)
3233 return false;
3234
3235 /* Only consider SFP+ PHYs i.e. media type fiber */
3236 switch (hw->mac.ops.get_media_type(hw)) {
3237 case ixgbe_media_type_fiber:
3238 case ixgbe_media_type_fiber_qsfp:
3239 break;
3240 default:
3241 return false;
3242 }
3243
3244 return true;
3245}
3246
21ce849b
MC		 3247/**
3248 * ixgbe_check_mac_link_generic - Determine link and speed status
3249 * @hw: pointer to hardware structure
3250 * @speed: pointer to link speed
3251 * @link_up: true when link is up
3252 * @link_up_wait_to_complete: bool used to wait for link up or not
3253 *
3254 * Reads the links register to determine if link is up and the current speed
3255 **/
3256s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3257 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3258{
48de36c5 3259 u32 links_reg, links_orig;
21ce849b
MC		 3260 u32 i;
3261
aac9e053
DS		 3262 /* If Crosstalk fix enabled do the sanity check of making sure
3263 * the SFP+ cage is full.
3264 */
3265 if (ixgbe_need_crosstalk_fix(hw)) {
3266 u32 sfp_cage_full;
3267
3268 switch (hw->mac.type) {
3269 case ixgbe_mac_82599EB:
3270 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3271 IXGBE_ESDP_SDP2;
3272 break;
3273 case ixgbe_mac_X550EM_x:
3274 case ixgbe_mac_x550em_a:
3275 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3276 IXGBE_ESDP_SDP0;
3277 break;
3278 default:
3279 /* sanity check - No SFP+ devices here */
3280 sfp_cage_full = false;
3281 break;
3282 }
3283
3284 if (!sfp_cage_full) {
3285 *link_up = false;
3286 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3287 return 0;
3288 }
3289 }
3290
48de36c5
ET		 3291 /* clear the old state */
3292 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3293
21ce849b 3294 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3295
3296 if (links_orig != links_reg) {
3297 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3298 links_orig, links_reg);
3299 }
3300
21ce849b
MC		 3301 if (link_up_wait_to_complete) {
3302 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3303 if (links_reg & IXGBE_LINKS_UP) {
3304 *link_up = true;
3305 break;
3306 } else {
3307 *link_up = false;
3308 }
3309 msleep(100);
3310 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3311 }
3312 } else {
3313 if (links_reg & IXGBE_LINKS_UP)
3314 *link_up = true;
3315 else
3316 *link_up = false;
3317 }
3318
9a75a1ac
DS		 3319 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3320 case IXGBE_LINKS_SPEED_10G_82599:
3321 if ((hw->mac.type >= ixgbe_mac_X550) &&
3322 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3323 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3324 else
3325 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3326 break;
3327 case IXGBE_LINKS_SPEED_1G_82599:
21ce849b 3328 *speed = IXGBE_LINK_SPEED_1GB_FULL;
9a75a1ac
DS		 3329 break;
3330 case IXGBE_LINKS_SPEED_100_82599:
3331 if ((hw->mac.type >= ixgbe_mac_X550) &&
3332 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3333 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3334 else
3335 *speed = IXGBE_LINK_SPEED_100_FULL;
3336 break;
3337 default:
63d778df 3338 *speed = IXGBE_LINK_SPEED_UNKNOWN;
9a75a1ac 3339 }
21ce849b 3340
21ce849b
MC		 3341 return 0;
3342}
a391f1d5
DS		 3343
3344/**
49ce9c2c 3345 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3346 * the EEPROM
3347 * @hw: pointer to hardware structure
3348 * @wwnn_prefix: the alternative WWNN prefix
3349 * @wwpn_prefix: the alternative WWPN prefix
3350 *
3351 * This function will read the EEPROM from the alternative SAN MAC address
3352 * block to check the support for the alternative WWNN/WWPN prefix support.
3353 **/
3354s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 3355 u16 *wwpn_prefix)
a391f1d5
DS		 3356{
3357 u16 offset, caps;
3358 u16 alt_san_mac_blk_offset;
3359
3360 /* clear output first */
3361 *wwnn_prefix = 0xFFFF;
3362 *wwpn_prefix = 0xFFFF;
3363
3364 /* check if alternative SAN MAC is supported */
be0c27b4
MR		 3365 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3366 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3367 goto wwn_prefix_err;
a391f1d5
DS		 3368
3369 if ((alt_san_mac_blk_offset == 0) ||
3370 (alt_san_mac_blk_offset == 0xFFFF))
e90dd264 3371 return 0;
a391f1d5
DS		 3372
3373 /* check capability in alternative san mac address block */
3374 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
be0c27b4
MR		 3375 if (hw->eeprom.ops.read(hw, offset, &caps))
3376 goto wwn_prefix_err;
a391f1d5 3377 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
e90dd264 3378 return 0;
a391f1d5
DS		 3379
3380 /* get the corresponding prefix for WWNN/WWPN */
3381 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
be0c27b4
MR		 3382 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3383 hw_err(hw, "eeprom read at offset %d failed\n", offset);
a391f1d5
DS		 3384
3385 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
be0c27b4
MR		 3386 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3387 goto wwn_prefix_err;
a391f1d5 3388
a391f1d5 3389 return 0;
be0c27b4
MR		 3390
3391wwn_prefix_err:
3392 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3393 return 0;
a391f1d5 3394}
a985b6c3
GR		 3395
3396/**
3397 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3398 * @hw: pointer to hardware structure
77f192af
ET		 3399 * @enable: enable or disable switch for MAC anti-spoofing
3400 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
a985b6c3
GR		 3401 *
3402 **/
77f192af 3403void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
a985b6c3 3404{
77f192af
ET		 3405 int vf_target_reg = vf >> 3;
3406 int vf_target_shift = vf % 8;
3407 u32 pfvfspoof;
a985b6c3
GR		 3408
3409 if (hw->mac.type == ixgbe_mac_82598EB)
3410 return;
3411
77f192af 3412 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
a985b6c3 3413 if (enable)
77f192af
ET		 3414 pfvfspoof |= BIT(vf_target_shift);
3415 else
3416 pfvfspoof &= ~BIT(vf_target_shift);
3417 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
a985b6c3
GR		 3418}
3419
3420/**
3421 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3422 * @hw: pointer to hardware structure
3423 * @enable: enable or disable switch for VLAN anti-spoofing
3424 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3425 *
3426 **/
3427void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3428{
3429 int vf_target_reg = vf >> 3;
3430 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3431 u32 pfvfspoof;
3432
3433 if (hw->mac.type == ixgbe_mac_82598EB)
3434 return;
3435
3436 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3437 if (enable)
b4f47a48 3438 pfvfspoof |= BIT(vf_target_shift);
a985b6c3 3439 else
b4f47a48 3440 pfvfspoof &= ~BIT(vf_target_shift);
a985b6c3
GR		 3441 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3442}
b776d104
ET		 3443
3444/**
3445 * ixgbe_get_device_caps_generic - Get additional device capabilities
3446 * @hw: pointer to hardware structure
3447 * @device_caps: the EEPROM word with the extra device capabilities
3448 *
3449 * This function will read the EEPROM location for the device capabilities,
3450 * and return the word through device_caps.
3451 **/
3452s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3453{
3454 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3455
3456 return 0;
3457}
80605c65
JF		 3458
3459/**
3460 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3461 * @hw: pointer to hardware structure
3462 * @num_pb: number of packet buffers to allocate
3463 * @headroom: reserve n KB of headroom
3464 * @strategy: packet buffer allocation strategy
3465 **/
3466void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3467 int num_pb,
3468 u32 headroom,
3469 int strategy)
3470{
3471 u32 pbsize = hw->mac.rx_pb_size;
3472 int i = 0;
3473 u32 rxpktsize, txpktsize, txpbthresh;
3474
3475 /* Reserve headroom */
3476 pbsize -= headroom;
3477
3478 if (!num_pb)
3479 num_pb = 1;
3480
3481 /* Divide remaining packet buffer space amongst the number
3482 * of packet buffers requested using supplied strategy.
3483 */
3484 switch (strategy) {
3485 case (PBA_STRATEGY_WEIGHTED):
3486 /* pba_80_48 strategy weight first half of packet buffer with
3487 * 5/8 of the packet buffer space.
3488 */
3489 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3490 pbsize -= rxpktsize * (num_pb / 2);
3491 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3492 for (; i < (num_pb / 2); i++)
3493 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3494 /* Fall through to configure remaining packet buffers */
3495 case (PBA_STRATEGY_EQUAL):
3496 /* Divide the remaining Rx packet buffer evenly among the TCs */
3497 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3498 for (; i < num_pb; i++)
3499 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3500 break;
3501 default:
3502 break;
3503 }
3504
3505 /*
3506 * Setup Tx packet buffer and threshold equally for all TCs
3507 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3508 * 10 since the largest packet we support is just over 9K.
3509 */
3510 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3511 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3512 for (i = 0; i < num_pb; i++) {
3513 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3514 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3515 }
3516
3517 /* Clear unused TCs, if any, to zero buffer size*/
3518 for (; i < IXGBE_MAX_PB; i++) {
3519 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3520 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3521 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3522 }
3523}
9612de92
ET		 3524
3525/**
3526 * ixgbe_calculate_checksum - Calculate checksum for buffer
3527 * @buffer: pointer to EEPROM
3528 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3529 *
9612de92
ET		 3530 * Calculates the checksum for some buffer on a specified length. The
3531 * checksum calculated is returned.
3532 **/
3533static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3534{
3535 u32 i;
3536 u8 sum = 0;
3537
3538 if (!buffer)
3539 return 0;
3540
3541 for (i = 0; i < length; i++)
3542 sum += buffer[i];
3543
3544 return (u8) (0 - sum);
3545}
3546
3547/**
3548 * ixgbe_host_interface_command - Issue command to manageability block
3549 * @hw: pointer to the HW structure
3550 * @buffer: contains the command to write and where the return status will
3551 * be placed
c466d7a7 3552 * @length: length of buffer, must be multiple of 4 bytes
b48e4aa3
DS		 3553 * @timeout: time in ms to wait for command completion
3554 * @return_data: read and return data from the buffer (true) or not (false)
3555 * Needed because FW structures are big endian and decoding of
3556 * these fields can be 8 bit or 16 bit based on command. Decoding
3557 * is not easily understood without making a table of commands.
3558 * So we will leave this up to the caller to read back the data
3559 * in these cases.
9612de92
ET		 3560 *
3561 * Communicates with the manageability block. On success return 0
3562 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3563 **/
5cffde30 3564s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,
6a14ee0c
DS		 3565 u32 length, u32 timeout,
3566 bool return_data)
9612de92 3567{
9612de92 3568 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
5cffde30 3569 u32 hicr, i, bi, fwsts;
b48e4aa3 3570 u16 buf_len, dword_len;
5cffde30
MR		 3571 union {
3572 struct ixgbe_hic_hdr hdr;
3573 u32 u32arr[1];
3574 } *bp = buffer;
af741901 3575 s32 status;
9612de92 3576
5cffde30 3577 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
b48e4aa3 3578 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
e90dd264 3579 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92 3580 }
af741901
MR		 3581 /* Take management host interface semaphore */
3582 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3583 if (status)
3584 return status;
9612de92 3585
b48e4aa3
DS		 3586 /* Set bit 9 of FWSTS clearing FW reset indication */
3587 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3588 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3589
9612de92
ET		 3590 /* Check that the host interface is enabled. */
3591 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
5cffde30 3592 if (!(hicr & IXGBE_HICR_EN)) {
9612de92 3593 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
af741901
MR		 3594 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3595 goto rel_out;
9612de92
ET		 3596 }
3597
b48e4aa3 3598 /* Calculate length in DWORDs. We must be DWORD aligned */
5cffde30 3599 if (length % sizeof(u32)) {
b48e4aa3 3600 hw_dbg(hw, "Buffer length failure, not aligned to dword");
af741901
MR		 3601 status = IXGBE_ERR_INVALID_ARGUMENT;
3602 goto rel_out;
b48e4aa3
DS		 3603 }
3604
9612de92
ET		 3605 dword_len = length >> 2;
3606
5cffde30 3607 /* The device driver writes the relevant command block
9612de92
ET		 3608 * into the ram area.
3609 */
3610 for (i = 0; i < dword_len; i++)
3611 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
5cffde30 3612 i, cpu_to_le32(bp->u32arr[i]));
9612de92
ET		 3613
3614 /* Setting this bit tells the ARC that a new command is pending. */
3615 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3616
b48e4aa3 3617 for (i = 0; i < timeout; i++) {
9612de92
ET		 3618 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3619 if (!(hicr & IXGBE_HICR_C))
3620 break;
3621 usleep_range(1000, 2000);
3622 }
3623
3624 /* Check command successful completion. */
5cffde30
MR		 3625 if ((timeout && i == timeout) ||
3626 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
9612de92 3627 hw_dbg(hw, "Command has failed with no status valid.\n");
af741901
MR		 3628 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3629 goto rel_out;
9612de92
ET		 3630 }
3631
b48e4aa3 3632 if (!return_data)
af741901 3633 goto rel_out;
b48e4aa3 3634
9612de92
ET		 3635 /* Calculate length in DWORDs */
3636 dword_len = hdr_size >> 2;
3637
3638 /* first pull in the header so we know the buffer length */
331bcf45 3639 for (bi = 0; bi < dword_len; bi++) {
5cffde30
MR		 3640 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3641 le32_to_cpus(&bp->u32arr[bi]);
79488c58 3642 }
9612de92
ET		 3643
3644 /* If there is any thing in data position pull it in */
5cffde30
MR		 3645 buf_len = bp->hdr.buf_len;
3646 if (!buf_len)
af741901 3647 goto rel_out;
9612de92 3648
73457165 3649 if (length < round_up(buf_len, 4) + hdr_size) {
9612de92 3650 hw_dbg(hw, "Buffer not large enough for reply message.\n");
af741901
MR		 3651 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3652 goto rel_out;
9612de92
ET		 3653 }
3654
331bcf45
ET		 3655 /* Calculate length in DWORDs, add 3 for odd lengths */
3656 dword_len = (buf_len + 3) >> 2;
9612de92 3657
5cffde30 3658 /* Pull in the rest of the buffer (bi is where we left off) */
331bcf45 3659 for (; bi <= dword_len; bi++) {
5cffde30
MR		 3660 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3661 le32_to_cpus(&bp->u32arr[bi]);
331bcf45 3662 }
9612de92 3663
af741901
MR		 3664rel_out:
3665 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3666
3667 return status;
9612de92
ET		 3668}
3669
3670/**
3671 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3672 * @hw: pointer to the HW structure
3673 * @maj: driver version major number
3674 * @min: driver version minor number
3675 * @build: driver version build number
3676 * @sub: driver version sub build number
3677 *
3678 * Sends driver version number to firmware through the manageability
3679 * block. On success return 0
3680 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3681 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3682 **/
3683s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3684 u8 build, u8 sub)
3685{
3686 struct ixgbe_hic_drv_info fw_cmd;
3687 int i;
e90dd264 3688 s32 ret_val;
9612de92 3689
9612de92
ET		 3690 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3691 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3692 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3775b814 3693 fw_cmd.port_num = hw->bus.func;
9612de92
ET		 3694 fw_cmd.ver_maj = maj;
3695 fw_cmd.ver_min = min;
3696 fw_cmd.ver_build = build;
3697 fw_cmd.ver_sub = sub;
3698 fw_cmd.hdr.checksum = 0;
3699 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3700 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3701 fw_cmd.pad = 0;
3702 fw_cmd.pad2 = 0;
3703
3704 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
5cffde30 3705 ret_val = ixgbe_host_interface_command(hw, &fw_cmd,
b48e4aa3
DS		 3706 sizeof(fw_cmd),
3707 IXGBE_HI_COMMAND_TIMEOUT,
3708 true);
9612de92
ET		 3709 if (ret_val != 0)
3710 continue;
3711
3712 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3713 FW_CEM_RESP_STATUS_SUCCESS)
3714 ret_val = 0;
3715 else
3716 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3717
3718 break;
3719 }
3720
9612de92
ET		 3721 return ret_val;
3722}
ff9d1a5a
ET		 3723
3724/**
3725 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3726 * @hw: pointer to the hardware structure
3727 *
3728 * The 82599 and x540 MACs can experience issues if TX work is still pending
3729 * when a reset occurs. This function prevents this by flushing the PCIe
3730 * buffers on the system.
3731 **/
3732void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3733{
71bde601
DS		 3734 u32 gcr_ext, hlreg0, i, poll;
3735 u16 value;
ff9d1a5a
ET		 3736
3737 /*
3738 * If double reset is not requested then all transactions should
3739 * already be clear and as such there is no work to do
3740 */
3741 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3742 return;
3743
3744 /*
3745 * Set loopback enable to prevent any transmits from being sent
3746 * should the link come up. This assumes that the RXCTRL.RXEN bit
3747 * has already been cleared.
3748 */
3749 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3750 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3751
71bde601
DS		 3752 /* wait for a last completion before clearing buffers */
3753 IXGBE_WRITE_FLUSH(hw);
3754 usleep_range(3000, 6000);
3755
3756 /* Before proceeding, make sure that the PCIe block does not have
3757 * transactions pending.
3758 */
3759 poll = ixgbe_pcie_timeout_poll(hw);
3760 for (i = 0; i < poll; i++) {
3761 usleep_range(100, 200);
3762 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3763 if (ixgbe_removed(hw->hw_addr))
3764 break;
3765 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3766 break;
3767 }
3768
ff9d1a5a
ET		 3769 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3770 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3771 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3772 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3773
3774 /* Flush all writes and allow 20usec for all transactions to clear */
3775 IXGBE_WRITE_FLUSH(hw);
3776 udelay(20);
3777
3778 /* restore previous register values */
3779 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3780 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3781}
e1ea9158
DS		 3782
3783static const u8 ixgbe_emc_temp_data[4] = {
3784 IXGBE_EMC_INTERNAL_DATA,
3785 IXGBE_EMC_DIODE1_DATA,
3786 IXGBE_EMC_DIODE2_DATA,
3787 IXGBE_EMC_DIODE3_DATA
3788};
3789static const u8 ixgbe_emc_therm_limit[4] = {
3790 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3791 IXGBE_EMC_DIODE1_THERM_LIMIT,
3792 IXGBE_EMC_DIODE2_THERM_LIMIT,
3793 IXGBE_EMC_DIODE3_THERM_LIMIT
3794};
3795
3796/**
3797 * ixgbe_get_ets_data - Extracts the ETS bit data
3798 * @hw: pointer to hardware structure
3799 * @ets_cfg: extected ETS data
3800 * @ets_offset: offset of ETS data
3801 *
3802 * Returns error code.
3803 **/
3804static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3805 u16 *ets_offset)
3806{
e90dd264 3807 s32 status;
e1ea9158
DS		 3808
3809 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3810 if (status)
e90dd264 3811 return status;
e1ea9158 3812
e90dd264
MR		 3813 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3814 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3815
3816 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3817 if (status)
e90dd264 3818 return status;
e1ea9158 3819
e90dd264
MR		 3820 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3821 return IXGBE_NOT_IMPLEMENTED;
e1ea9158 3822
e90dd264 3823 return 0;
e1ea9158
DS		 3824}
3825
3826/**
3827 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3828 * @hw: pointer to hardware structure
3829 *
3830 * Returns the thermal sensor data structure
3831 **/
3832s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3833{
e90dd264 3834 s32 status;
e1ea9158
DS		 3835 u16 ets_offset;
3836 u16 ets_cfg;
3837 u16 ets_sensor;
3838 u8 num_sensors;
3839 u8 i;
3840 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3841
3ca8bc6d 3842 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3843 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3844 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3845
3846 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3847 if (status)
e90dd264 3848 return status;
e1ea9158
DS		 3849
3850 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3851 if (num_sensors > IXGBE_MAX_SENSORS)
3852 num_sensors = IXGBE_MAX_SENSORS;
3853
3854 for (i = 0; i < num_sensors; i++) {
3855 u8 sensor_index;
3856 u8 sensor_location;
3857
3858 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3859 &ets_sensor);
3860 if (status)
e90dd264 3861 return status;
e1ea9158
DS		 3862
3863 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3864 IXGBE_ETS_DATA_INDEX_SHIFT);
3865 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3866 IXGBE_ETS_DATA_LOC_SHIFT);
3867
3868 if (sensor_location != 0) {
3869 status = hw->phy.ops.read_i2c_byte(hw,
3870 ixgbe_emc_temp_data[sensor_index],
3871 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3872 &data->sensor[i].temp);
3873 if (status)
e90dd264 3874 return status;
e1ea9158
DS		 3875 }
3876 }
e90dd264
MR		 3877
3878 return 0;
e1ea9158
DS		 3879}
3880
3881/**
3882 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3883 * @hw: pointer to hardware structure
3884 *
3885 * Inits the thermal sensor thresholds according to the NVM map
3886 * and save off the threshold and location values into mac.thermal_sensor_data
3887 **/
3888s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3889{
e90dd264 3890 s32 status;
e1ea9158
DS		 3891 u16 ets_offset;
3892 u16 ets_cfg;
3893 u16 ets_sensor;
3894 u8 low_thresh_delta;
3895 u8 num_sensors;
3896 u8 therm_limit;
3897 u8 i;
3898 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3899
3900 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3901
3ca8bc6d 3902 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3903 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3904 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3905
3906 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3907 if (status)
e90dd264 3908 return status;
e1ea9158
DS		 3909
3910 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3911 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3912 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3913 if (num_sensors > IXGBE_MAX_SENSORS)
3914 num_sensors = IXGBE_MAX_SENSORS;
3915
3916 for (i = 0; i < num_sensors; i++) {
3917 u8 sensor_index;
3918 u8 sensor_location;
3919
be0c27b4
MR		 3920 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3921 hw_err(hw, "eeprom read at offset %d failed\n",
3922 ets_offset + 1 + i);
3923 continue;
3924 }
e1ea9158
DS		 3925 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3926 IXGBE_ETS_DATA_INDEX_SHIFT);
3927 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3928 IXGBE_ETS_DATA_LOC_SHIFT);
3929 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3930
3931 hw->phy.ops.write_i2c_byte(hw,
3932 ixgbe_emc_therm_limit[sensor_index],
3933 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3934
3935 if (sensor_location == 0)
3936 continue;
3937
3938 data->sensor[i].location = sensor_location;
3939 data->sensor[i].caution_thresh = therm_limit;
3940 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3941 }
e90dd264
MR		 3942
3943 return 0;
e1ea9158
DS		 3944}
3945
1f9ac57c
DS		 3946void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
3947{
3948 u32 rxctrl;
3949
3950 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3951 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3952 if (hw->mac.type != ixgbe_mac_82598EB) {
3953 u32 pfdtxgswc;
3954
3955 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3956 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3957 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3958 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3959 hw->mac.set_lben = true;
3960 } else {
3961 hw->mac.set_lben = false;
3962 }
3963 }
3964 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3965 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3966 }
3967}
3968
3969void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
3970{
3971 u32 rxctrl;
3972
3973 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3974 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
3975
3976 if (hw->mac.type != ixgbe_mac_82598EB) {
3977 if (hw->mac.set_lben) {
3978 u32 pfdtxgswc;
3979
3980 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3981 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
3982 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3983 hw->mac.set_lben = false;
3984 }
3985 }
3986}
bd8069ac
DS		 3987
3988/** ixgbe_mng_present - returns true when management capability is present
3989 * @hw: pointer to hardware structure
3990 **/
3991bool ixgbe_mng_present(struct ixgbe_hw *hw)
3992{
3993 u32 fwsm;
3994
3995 if (hw->mac.type < ixgbe_mac_82599EB)
3996 return false;
3997
3998 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
3999 fwsm &= IXGBE_FWSM_MODE_MASK;
4000 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4001}
6d373a1b
MR		 4002
4003/**
4004 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
4005 * @hw: pointer to hardware structure
4006 * @speed: new link speed
4007 * @autoneg_wait_to_complete: true when waiting for completion is needed
4008 *
4009 * Set the link speed in the MAC and/or PHY register and restarts link.
4010 */
4011s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4012 ixgbe_link_speed speed,
4013 bool autoneg_wait_to_complete)
4014{
4015 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4016 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4017 s32 status = 0;
4018 u32 speedcnt = 0;
4019 u32 i = 0;
4020 bool autoneg, link_up = false;
4021
4022 /* Mask off requested but non-supported speeds */
4023 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
4024 if (status)
4025 return status;
4026
4027 speed &= link_speed;
4028
4029 /* Try each speed one by one, highest priority first. We do this in
4030 * software because 10Gb fiber doesn't support speed autonegotiation.
4031 */
4032 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4033 speedcnt++;
4034 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4035
4036 /* If we already have link at this speed, just jump out */
4037 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4038 false);
4039 if (status)
4040 return status;
4041
4042 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up)
4043 goto out;
4044
4045 /* Set the module link speed */
4046 switch (hw->phy.media_type) {
4047 case ixgbe_media_type_fiber:
4048 hw->mac.ops.set_rate_select_speed(hw,
4049 IXGBE_LINK_SPEED_10GB_FULL);
4050 break;
4051 case ixgbe_media_type_fiber_qsfp:
4052 /* QSFP module automatically detects MAC link speed */
4053 break;
4054 default:
4055 hw_dbg(hw, "Unexpected media type\n");
4056 break;
4057 }
4058
4059 /* Allow module to change analog characteristics (1G->10G) */
4060 msleep(40);
4061
4062 status = hw->mac.ops.setup_mac_link(hw,
4063 IXGBE_LINK_SPEED_10GB_FULL,
4064 autoneg_wait_to_complete);
4065 if (status)
4066 return status;
4067
4068 /* Flap the Tx laser if it has not already been done */
4069 if (hw->mac.ops.flap_tx_laser)
4070 hw->mac.ops.flap_tx_laser(hw);
4071
4072 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4073 * Section 73.10.2, we may have to wait up to 500ms if KR is
4074 * attempted. 82599 uses the same timing for 10g SFI.
4075 */
4076 for (i = 0; i < 5; i++) {
4077 /* Wait for the link partner to also set speed */
4078 msleep(100);
4079
4080 /* If we have link, just jump out */
4081 status = hw->mac.ops.check_link(hw, &link_speed,
4082 &link_up, false);
4083 if (status)
4084 return status;
4085
4086 if (link_up)
4087 goto out;
4088 }
4089 }
4090
4091 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4092 speedcnt++;
4093 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4094 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4095
4096 /* If we already have link at this speed, just jump out */
4097 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4098 false);
4099 if (status)
4100 return status;
4101
4102 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up)
4103 goto out;
4104
4105 /* Set the module link speed */
4106 switch (hw->phy.media_type) {
4107 case ixgbe_media_type_fiber:
4108 hw->mac.ops.set_rate_select_speed(hw,
4109 IXGBE_LINK_SPEED_1GB_FULL);
4110 break;
4111 case ixgbe_media_type_fiber_qsfp:
4112 /* QSFP module automatically detects link speed */
4113 break;
4114 default:
4115 hw_dbg(hw, "Unexpected media type\n");
4116 break;
4117 }
4118
4119 /* Allow module to change analog characteristics (10G->1G) */
4120 msleep(40);
4121
4122 status = hw->mac.ops.setup_mac_link(hw,
4123 IXGBE_LINK_SPEED_1GB_FULL,
4124 autoneg_wait_to_complete);
4125 if (status)
4126 return status;
4127
4128 /* Flap the Tx laser if it has not already been done */
4129 if (hw->mac.ops.flap_tx_laser)
4130 hw->mac.ops.flap_tx_laser(hw);
4131
4132 /* Wait for the link partner to also set speed */
4133 msleep(100);
4134
4135 /* If we have link, just jump out */
4136 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4137 false);
4138 if (status)
4139 return status;
4140
4141 if (link_up)
4142 goto out;
4143 }
4144
4145 /* We didn't get link. Configure back to the highest speed we tried,
4146 * (if there was more than one). We call ourselves back with just the
4147 * single highest speed that the user requested.
4148 */
4149 if (speedcnt > 1)
4150 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4151 highest_link_speed,
4152 autoneg_wait_to_complete);
4153
4154out:
4155 /* Set autoneg_advertised value based on input link speed */
4156 hw->phy.autoneg_advertised = 0;
4157
4158 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4159 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4160
4161 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4162 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4163
4164 return status;
4165}
4166
4167/**
4168 * ixgbe_set_soft_rate_select_speed - Set module link speed
4169 * @hw: pointer to hardware structure
4170 * @speed: link speed to set
4171 *
4172 * Set module link speed via the soft rate select.
4173 */
4174void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4175 ixgbe_link_speed speed)
4176{
4177 s32 status;
4178 u8 rs, eeprom_data;
4179
4180 switch (speed) {
4181 case IXGBE_LINK_SPEED_10GB_FULL:
4182 /* one bit mask same as setting on */
4183 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4184 break;
4185 case IXGBE_LINK_SPEED_1GB_FULL:
4186 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4187 break;
4188 default:
4189 hw_dbg(hw, "Invalid fixed module speed\n");
4190 return;
4191 }
4192
4193 /* Set RS0 */
4194 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4195 IXGBE_I2C_EEPROM_DEV_ADDR2,
4196 &eeprom_data);
4197 if (status) {
4198 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
4199 return;
4200 }
4201
4202 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4203
4204 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4205 IXGBE_I2C_EEPROM_DEV_ADDR2,
4206 eeprom_data);
4207 if (status) {
4208 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
4209 return;
4210 }
4211}
Linux kernel - Deliverables
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