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ixgbe: Fix compiler warnings
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
0b0c2b31
ET		 50static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
51static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
52static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
53static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
54static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
7b25cdba 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
eb9c3e3e 57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 58static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
61 u16 words, u16 *data);
62static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 u16 offset);
ff9d1a5a 64static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71
AK		 65
66/**
c44ade9e 67 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 68 * @hw: pointer to hardware structure
69 *
70 * Starts the hardware by filling the bus info structure and media type, clears
71 * all on chip counters, initializes receive address registers, multicast
72 * table, VLAN filter table, calls routine to set up link and flow control
73 * settings, and leaves transmit and receive units disabled and uninitialized
74 **/
c44ade9e 75s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 76{
77 u32 ctrl_ext;
78
79 /* Set the media type */
80 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
81
82 /* Identify the PHY */
c44ade9e 83 hw->phy.ops.identify(hw);
9a799d71 84
9a799d71 85 /* Clear the VLAN filter table */
c44ade9e 86 hw->mac.ops.clear_vfta(hw);
9a799d71 87
9a799d71 88 /* Clear statistics registers */
c44ade9e 89 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 90
91 /* Set No Snoop Disable */
92 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
93 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
94 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 95 IXGBE_WRITE_FLUSH(hw);
9a799d71 96
620fa036
MC		 97 /* Setup flow control */
98 ixgbe_setup_fc(hw, 0);
99
9a799d71
AK		 100 /* Clear adapter stopped flag */
101 hw->adapter_stopped = false;
102
103 return 0;
104}
105
7184b7cf
ET		 106/**
107 * ixgbe_start_hw_gen2 - Init sequence for common device family
108 * @hw: pointer to hw structure
109 *
110 * Performs the init sequence common to the second generation
111 * of 10 GbE devices.
112 * Devices in the second generation:
113 * 82599
114 * X540
115 **/
116s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
117{
118 u32 i;
3d5c5207 119 u32 regval;
7184b7cf
ET		 120
121 /* Clear the rate limiters */
122 for (i = 0; i < hw->mac.max_tx_queues; i++) {
123 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
124 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
125 }
126 IXGBE_WRITE_FLUSH(hw);
127
3d5c5207
ET		 128 /* Disable relaxed ordering */
129 for (i = 0; i < hw->mac.max_tx_queues; i++) {
130 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
131 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
132 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
133 }
134
135 for (i = 0; i < hw->mac.max_rx_queues; i++) {
136 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
137 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
138 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
139 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
140 }
141
7184b7cf
ET		 142 return 0;
143}
144
9a799d71 145/**
c44ade9e 146 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 147 * @hw: pointer to hardware structure
148 *
c44ade9e 149 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 150 * structure and media type, clears all on chip counters, initializes receive
151 * address registers, multicast table, VLAN filter table, calls routine to set
152 * up link and flow control settings, and leaves transmit and receive units
153 * disabled and uninitialized
154 **/
c44ade9e 155s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 156{
794caeb2
PWJ		 157 s32 status;
158
9a799d71 159 /* Reset the hardware */
794caeb2 160 status = hw->mac.ops.reset_hw(hw);
9a799d71 161
794caeb2
PWJ		 162 if (status == 0) {
163 /* Start the HW */
164 status = hw->mac.ops.start_hw(hw);
165 }
9a799d71 166
794caeb2 167 return status;
9a799d71
AK		 168}
169
170/**
c44ade9e 171 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 172 * @hw: pointer to hardware structure
173 *
174 * Clears all hardware statistics counters by reading them from the hardware
175 * Statistics counters are clear on read.
176 **/
c44ade9e 177s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 178{
179 u16 i = 0;
180
181 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
182 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
183 IXGBE_READ_REG(hw, IXGBE_ERRBC);
184 IXGBE_READ_REG(hw, IXGBE_MSPDC);
185 for (i = 0; i < 8; i++)
186 IXGBE_READ_REG(hw, IXGBE_MPC(i));
187
188 IXGBE_READ_REG(hw, IXGBE_MLFC);
189 IXGBE_READ_REG(hw, IXGBE_MRFC);
190 IXGBE_READ_REG(hw, IXGBE_RLEC);
191 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 192 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 193 if (hw->mac.type >= ixgbe_mac_82599EB) {
194 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
195 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
196 } else {
197 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
198 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
199 }
9a799d71
AK		 200
201 for (i = 0; i < 8; i++) {
202 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 203 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 204 if (hw->mac.type >= ixgbe_mac_82599EB) {
205 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
206 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
207 } else {
208 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
209 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
210 }
9a799d71 211 }
667c7565
ET		 212 if (hw->mac.type >= ixgbe_mac_82599EB)
213 for (i = 0; i < 8; i++)
214 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 215 IXGBE_READ_REG(hw, IXGBE_PRC64);
216 IXGBE_READ_REG(hw, IXGBE_PRC127);
217 IXGBE_READ_REG(hw, IXGBE_PRC255);
218 IXGBE_READ_REG(hw, IXGBE_PRC511);
219 IXGBE_READ_REG(hw, IXGBE_PRC1023);
220 IXGBE_READ_REG(hw, IXGBE_PRC1522);
221 IXGBE_READ_REG(hw, IXGBE_GPRC);
222 IXGBE_READ_REG(hw, IXGBE_BPRC);
223 IXGBE_READ_REG(hw, IXGBE_MPRC);
224 IXGBE_READ_REG(hw, IXGBE_GPTC);
225 IXGBE_READ_REG(hw, IXGBE_GORCL);
226 IXGBE_READ_REG(hw, IXGBE_GORCH);
227 IXGBE_READ_REG(hw, IXGBE_GOTCL);
228 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 229 if (hw->mac.type == ixgbe_mac_82598EB)
230 for (i = 0; i < 8; i++)
231 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 232 IXGBE_READ_REG(hw, IXGBE_RUC);
233 IXGBE_READ_REG(hw, IXGBE_RFC);
234 IXGBE_READ_REG(hw, IXGBE_ROC);
235 IXGBE_READ_REG(hw, IXGBE_RJC);
236 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
237 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
238 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
239 IXGBE_READ_REG(hw, IXGBE_TORL);
240 IXGBE_READ_REG(hw, IXGBE_TORH);
241 IXGBE_READ_REG(hw, IXGBE_TPR);
242 IXGBE_READ_REG(hw, IXGBE_TPT);
243 IXGBE_READ_REG(hw, IXGBE_PTC64);
244 IXGBE_READ_REG(hw, IXGBE_PTC127);
245 IXGBE_READ_REG(hw, IXGBE_PTC255);
246 IXGBE_READ_REG(hw, IXGBE_PTC511);
247 IXGBE_READ_REG(hw, IXGBE_PTC1023);
248 IXGBE_READ_REG(hw, IXGBE_PTC1522);
249 IXGBE_READ_REG(hw, IXGBE_MPTC);
250 IXGBE_READ_REG(hw, IXGBE_BPTC);
251 for (i = 0; i < 16; i++) {
252 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 253 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 254 if (hw->mac.type >= ixgbe_mac_82599EB) {
255 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
256 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
257 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
258 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
259 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
260 } else {
261 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
262 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
263 }
9a799d71
AK		 264 }
265
a3aeea0e
ET		 266 if (hw->mac.type == ixgbe_mac_X540) {
267 if (hw->phy.id == 0)
268 hw->phy.ops.identify(hw);
269 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
270 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
271 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
272 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
273 }
274
9a799d71
AK		 275 return 0;
276}
277
278/**
289700db 279 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 280 * @hw: pointer to hardware structure
289700db
DS		 281 * @pba_num: stores the part number string from the EEPROM
282 * @pba_num_size: part number string buffer length
c44ade9e 283 *
289700db 284 * Reads the part number string from the EEPROM.
c44ade9e 285 **/
289700db
DS		 286s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
287 u32 pba_num_size)
c44ade9e
JB		 288{
289 s32 ret_val;
290 u16 data;
289700db
DS		 291 u16 pba_ptr;
292 u16 offset;
293 u16 length;
294
295 if (pba_num == NULL) {
296 hw_dbg(hw, "PBA string buffer was null\n");
297 return IXGBE_ERR_INVALID_ARGUMENT;
298 }
c44ade9e
JB		 299
300 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
301 if (ret_val) {
302 hw_dbg(hw, "NVM Read Error\n");
303 return ret_val;
304 }
c44ade9e 305
289700db 306 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 307 if (ret_val) {
308 hw_dbg(hw, "NVM Read Error\n");
309 return ret_val;
310 }
289700db
DS		 311
312 /*
313 * if data is not ptr guard the PBA must be in legacy format which
314 * means pba_ptr is actually our second data word for the PBA number
315 * and we can decode it into an ascii string
316 */
317 if (data != IXGBE_PBANUM_PTR_GUARD) {
318 hw_dbg(hw, "NVM PBA number is not stored as string\n");
319
320 /* we will need 11 characters to store the PBA */
321 if (pba_num_size < 11) {
322 hw_dbg(hw, "PBA string buffer too small\n");
323 return IXGBE_ERR_NO_SPACE;
324 }
325
326 /* extract hex string from data and pba_ptr */
327 pba_num[0] = (data >> 12) & 0xF;
328 pba_num[1] = (data >> 8) & 0xF;
329 pba_num[2] = (data >> 4) & 0xF;
330 pba_num[3] = data & 0xF;
331 pba_num[4] = (pba_ptr >> 12) & 0xF;
332 pba_num[5] = (pba_ptr >> 8) & 0xF;
333 pba_num[6] = '-';
334 pba_num[7] = 0;
335 pba_num[8] = (pba_ptr >> 4) & 0xF;
336 pba_num[9] = pba_ptr & 0xF;
337
338 /* put a null character on the end of our string */
339 pba_num[10] = '\0';
340
341 /* switch all the data but the '-' to hex char */
342 for (offset = 0; offset < 10; offset++) {
343 if (pba_num[offset] < 0xA)
344 pba_num[offset] += '0';
345 else if (pba_num[offset] < 0x10)
346 pba_num[offset] += 'A' - 0xA;
347 }
348
349 return 0;
350 }
351
352 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
353 if (ret_val) {
354 hw_dbg(hw, "NVM Read Error\n");
355 return ret_val;
356 }
357
358 if (length == 0xFFFF || length == 0) {
359 hw_dbg(hw, "NVM PBA number section invalid length\n");
360 return IXGBE_ERR_PBA_SECTION;
361 }
362
363 /* check if pba_num buffer is big enough */
364 if (pba_num_size < (((u32)length * 2) - 1)) {
365 hw_dbg(hw, "PBA string buffer too small\n");
366 return IXGBE_ERR_NO_SPACE;
367 }
368
369 /* trim pba length from start of string */
370 pba_ptr++;
371 length--;
372
373 for (offset = 0; offset < length; offset++) {
374 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
375 if (ret_val) {
376 hw_dbg(hw, "NVM Read Error\n");
377 return ret_val;
378 }
379 pba_num[offset * 2] = (u8)(data >> 8);
380 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
381 }
382 pba_num[offset * 2] = '\0';
c44ade9e
JB		 383
384 return 0;
385}
386
387/**
388 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 389 * @hw: pointer to hardware structure
390 * @mac_addr: Adapter MAC address
391 *
392 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
393 * A reset of the adapter must be performed prior to calling this function
394 * in order for the MAC address to have been loaded from the EEPROM into RAR0
395 **/
c44ade9e 396s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 397{
398 u32 rar_high;
399 u32 rar_low;
400 u16 i;
401
402 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
403 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
404
405 for (i = 0; i < 4; i++)
406 mac_addr[i] = (u8)(rar_low >> (i*8));
407
408 for (i = 0; i < 2; i++)
409 mac_addr[i+4] = (u8)(rar_high >> (i*8));
410
411 return 0;
412}
413
11afc1b1
PW		 414/**
415 * ixgbe_get_bus_info_generic - Generic set PCI bus info
416 * @hw: pointer to hardware structure
417 *
418 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
419 **/
420s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423 struct ixgbe_mac_info *mac = &hw->mac;
424 u16 link_status;
425
426 hw->bus.type = ixgbe_bus_type_pci_express;
427
428 /* Get the negotiated link width and speed from PCI config space */
429 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
430 &link_status);
431
432 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
433 case IXGBE_PCI_LINK_WIDTH_1:
434 hw->bus.width = ixgbe_bus_width_pcie_x1;
435 break;
436 case IXGBE_PCI_LINK_WIDTH_2:
437 hw->bus.width = ixgbe_bus_width_pcie_x2;
438 break;
439 case IXGBE_PCI_LINK_WIDTH_4:
440 hw->bus.width = ixgbe_bus_width_pcie_x4;
441 break;
442 case IXGBE_PCI_LINK_WIDTH_8:
443 hw->bus.width = ixgbe_bus_width_pcie_x8;
444 break;
445 default:
446 hw->bus.width = ixgbe_bus_width_unknown;
447 break;
448 }
449
450 switch (link_status & IXGBE_PCI_LINK_SPEED) {
451 case IXGBE_PCI_LINK_SPEED_2500:
452 hw->bus.speed = ixgbe_bus_speed_2500;
453 break;
454 case IXGBE_PCI_LINK_SPEED_5000:
455 hw->bus.speed = ixgbe_bus_speed_5000;
456 break;
457 default:
458 hw->bus.speed = ixgbe_bus_speed_unknown;
459 break;
460 }
461
462 mac->ops.set_lan_id(hw);
463
464 return 0;
465}
466
467/**
468 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
469 * @hw: pointer to the HW structure
470 *
471 * Determines the LAN function id by reading memory-mapped registers
472 * and swaps the port value if requested.
473 **/
474void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
475{
476 struct ixgbe_bus_info *bus = &hw->bus;
477 u32 reg;
478
479 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
480 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
481 bus->lan_id = bus->func;
482
483 /* check for a port swap */
484 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
485 if (reg & IXGBE_FACTPS_LFS)
486 bus->func ^= 0x1;
487}
488
9a799d71 489/**
c44ade9e 490 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 491 * @hw: pointer to hardware structure
492 *
493 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
494 * disables transmit and receive units. The adapter_stopped flag is used by
495 * the shared code and drivers to determine if the adapter is in a stopped
496 * state and should not touch the hardware.
497 **/
c44ade9e 498s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 499{
9a799d71
AK		 500 u32 reg_val;
501 u16 i;
502
503 /*
504 * Set the adapter_stopped flag so other driver functions stop touching
505 * the hardware
506 */
507 hw->adapter_stopped = true;
508
509 /* Disable the receive unit */
ff9d1a5a 510 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
9a799d71 511
ff9d1a5a 512 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 513 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
514
ff9d1a5a 515 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 516 IXGBE_READ_REG(hw, IXGBE_EICR);
517
518 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 519 for (i = 0; i < hw->mac.max_tx_queues; i++)
520 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
521
522 /* Disable the receive unit by stopping each queue */
523 for (i = 0; i < hw->mac.max_rx_queues; i++) {
524 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
525 reg_val &= ~IXGBE_RXDCTL_ENABLE;
526 reg_val |= IXGBE_RXDCTL_SWFLSH;
527 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 528 }
529
ff9d1a5a
ET		 530 /* flush all queues disables */
531 IXGBE_WRITE_FLUSH(hw);
532 usleep_range(1000, 2000);
533
c44ade9e
JB		 534 /*
535 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
536 * access and verify no pending requests
537 */
ff9d1a5a 538 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 539}
540
541/**
c44ade9e 542 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 543 * @hw: pointer to hardware structure
544 * @index: led number to turn on
545 **/
c44ade9e 546s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 547{
548 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
549
550 /* To turn on the LED, set mode to ON. */
551 led_reg &= ~IXGBE_LED_MODE_MASK(index);
552 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
553 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 554 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 555
556 return 0;
557}
558
559/**
c44ade9e 560 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 561 * @hw: pointer to hardware structure
562 * @index: led number to turn off
563 **/
c44ade9e 564s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 565{
566 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
567
568 /* To turn off the LED, set mode to OFF. */
569 led_reg &= ~IXGBE_LED_MODE_MASK(index);
570 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
571 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 572 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 573
574 return 0;
575}
576
9a799d71 577/**
c44ade9e 578 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 579 * @hw: pointer to hardware structure
580 *
581 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
582 * ixgbe_hw struct in order to set up EEPROM access.
583 **/
c44ade9e 584s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 585{
586 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
587 u32 eec;
588 u16 eeprom_size;
589
590 if (eeprom->type == ixgbe_eeprom_uninitialized) {
591 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 592 /* Set default semaphore delay to 10ms which is a well
593 * tested value */
594 eeprom->semaphore_delay = 10;
68c7005d
ET		 595 /* Clear EEPROM page size, it will be initialized as needed */
596 eeprom->word_page_size = 0;
9a799d71
AK		 597
598 /*
599 * Check for EEPROM present first.
600 * If not present leave as none
601 */
602 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
603 if (eec & IXGBE_EEC_PRES) {
604 eeprom->type = ixgbe_eeprom_spi;
605
606 /*
607 * SPI EEPROM is assumed here. This code would need to
608 * change if a future EEPROM is not SPI.
609 */
610 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
611 IXGBE_EEC_SIZE_SHIFT);
612 eeprom->word_size = 1 << (eeprom_size +
613 IXGBE_EEPROM_WORD_SIZE_SHIFT);
614 }
615
616 if (eec & IXGBE_EEC_ADDR_SIZE)
617 eeprom->address_bits = 16;
618 else
619 eeprom->address_bits = 8;
620 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
621 "%d\n", eeprom->type, eeprom->word_size,
622 eeprom->address_bits);
623 }
624
625 return 0;
626}
627
11afc1b1 628/**
68c7005d 629 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 630 * @hw: pointer to hardware structure
68c7005d
ET		 631 * @offset: offset within the EEPROM to write
632 * @words: number of words
633 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 634 *
68c7005d 635 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 636 **/
68c7005d
ET		 637s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
638 u16 words, u16 *data)
11afc1b1 639{
68c7005d
ET		 640 s32 status = 0;
641 u16 i, count;
11afc1b1
PW		 642
643 hw->eeprom.ops.init_params(hw);
644
68c7005d
ET		 645 if (words == 0) {
646 status = IXGBE_ERR_INVALID_ARGUMENT;
647 goto out;
648 }
649
650 if (offset + words > hw->eeprom.word_size) {
11afc1b1
PW		 651 status = IXGBE_ERR_EEPROM;
652 goto out;
653 }
654
68c7005d
ET		 655 /*
656 * The EEPROM page size cannot be queried from the chip. We do lazy
657 * initialization. It is worth to do that when we write large buffer.
658 */
659 if ((hw->eeprom.word_page_size == 0) &&
660 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
661 ixgbe_detect_eeprom_page_size_generic(hw, offset);
662
663 /*
664 * We cannot hold synchronization semaphores for too long
665 * to avoid other entity starvation. However it is more efficient
666 * to read in bursts than synchronizing access for each word.
667 */
668 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
669 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
670 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
672 count, &data[i]);
673
674 if (status != 0)
675 break;
676 }
677
678out:
679 return status;
680}
681
682/**
683 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
684 * @hw: pointer to hardware structure
685 * @offset: offset within the EEPROM to be written to
686 * @words: number of word(s)
687 * @data: 16 bit word(s) to be written to the EEPROM
688 *
689 * If ixgbe_eeprom_update_checksum is not called after this function, the
690 * EEPROM will most likely contain an invalid checksum.
691 **/
692static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
693 u16 words, u16 *data)
694{
695 s32 status;
696 u16 word;
697 u16 page_size;
698 u16 i;
699 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
700
11afc1b1
PW		 701 /* Prepare the EEPROM for writing */
702 status = ixgbe_acquire_eeprom(hw);
703
704 if (status == 0) {
705 if (ixgbe_ready_eeprom(hw) != 0) {
706 ixgbe_release_eeprom(hw);
707 status = IXGBE_ERR_EEPROM;
708 }
709 }
710
711 if (status == 0) {
68c7005d
ET		 712 for (i = 0; i < words; i++) {
713 ixgbe_standby_eeprom(hw);
11afc1b1 714
68c7005d
ET		 715 /* Send the WRITE ENABLE command (8 bit opcode ) */
716 ixgbe_shift_out_eeprom_bits(hw,
717 IXGBE_EEPROM_WREN_OPCODE_SPI,
718 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 719
68c7005d 720 ixgbe_standby_eeprom(hw);
11afc1b1 721
68c7005d
ET		 722 /*
723 * Some SPI eeproms use the 8th address bit embedded
724 * in the opcode
725 */
726 if ((hw->eeprom.address_bits == 8) &&
727 ((offset + i) >= 128))
728 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
729
730 /* Send the Write command (8-bit opcode + addr) */
731 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
732 IXGBE_EEPROM_OPCODE_BITS);
733 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
734 hw->eeprom.address_bits);
735
736 page_size = hw->eeprom.word_page_size;
737
738 /* Send the data in burst via SPI*/
739 do {
740 word = data[i];
741 word = (word >> 8) | (word << 8);
742 ixgbe_shift_out_eeprom_bits(hw, word, 16);
743
744 if (page_size == 0)
745 break;
746
747 /* do not wrap around page */
748 if (((offset + i) & (page_size - 1)) ==
749 (page_size - 1))
750 break;
751 } while (++i < words);
752
753 ixgbe_standby_eeprom(hw);
754 usleep_range(10000, 20000);
755 }
756 /* Done with writing - release the EEPROM */
757 ixgbe_release_eeprom(hw);
758 }
11afc1b1 759
68c7005d
ET		 760 return status;
761}
762
763/**
764 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
765 * @hw: pointer to hardware structure
766 * @offset: offset within the EEPROM to be written to
767 * @data: 16 bit word to be written to the EEPROM
768 *
769 * If ixgbe_eeprom_update_checksum is not called after this function, the
770 * EEPROM will most likely contain an invalid checksum.
771 **/
772s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
773{
774 s32 status;
11afc1b1 775
68c7005d 776 hw->eeprom.ops.init_params(hw);
11afc1b1 777
68c7005d
ET		 778 if (offset >= hw->eeprom.word_size) {
779 status = IXGBE_ERR_EEPROM;
780 goto out;
11afc1b1
PW		 781 }
782
68c7005d
ET		 783 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
784
11afc1b1
PW		 785out:
786 return status;
787}
788
9a799d71 789/**
68c7005d 790 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 791 * @hw: pointer to hardware structure
792 * @offset: offset within the EEPROM to be read
68c7005d
ET		 793 * @words: number of word(s)
794 * @data: read 16 bit words(s) from EEPROM
c44ade9e 795 *
68c7005d 796 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 797 **/
68c7005d
ET		 798s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
799 u16 words, u16 *data)
c44ade9e 800{
68c7005d
ET		 801 s32 status = 0;
802 u16 i, count;
c44ade9e
JB		 803
804 hw->eeprom.ops.init_params(hw);
805
68c7005d
ET		 806 if (words == 0) {
807 status = IXGBE_ERR_INVALID_ARGUMENT;
808 goto out;
809 }
810
811 if (offset + words > hw->eeprom.word_size) {
c44ade9e
JB		 812 status = IXGBE_ERR_EEPROM;
813 goto out;
814 }
815
68c7005d
ET		 816 /*
817 * We cannot hold synchronization semaphores for too long
818 * to avoid other entity starvation. However it is more efficient
819 * to read in bursts than synchronizing access for each word.
820 */
821 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
822 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
823 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
824
825 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
826 count, &data[i]);
827
828 if (status != 0)
829 break;
830 }
831
832out:
833 return status;
834}
835
836/**
837 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
838 * @hw: pointer to hardware structure
839 * @offset: offset within the EEPROM to be read
840 * @words: number of word(s)
841 * @data: read 16 bit word(s) from EEPROM
842 *
843 * Reads 16 bit word(s) from EEPROM through bit-bang method
844 **/
845static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
846 u16 words, u16 *data)
847{
848 s32 status;
849 u16 word_in;
850 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
851 u16 i;
852
c44ade9e
JB		 853 /* Prepare the EEPROM for reading */
854 status = ixgbe_acquire_eeprom(hw);
855
856 if (status == 0) {
857 if (ixgbe_ready_eeprom(hw) != 0) {
858 ixgbe_release_eeprom(hw);
859 status = IXGBE_ERR_EEPROM;
860 }
861 }
862
863 if (status == 0) {
68c7005d
ET		 864 for (i = 0; i < words; i++) {
865 ixgbe_standby_eeprom(hw);
866 /*
867 * Some SPI eeproms use the 8th address bit embedded
868 * in the opcode
869 */
870 if ((hw->eeprom.address_bits == 8) &&
871 ((offset + i) >= 128))
872 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
873
874 /* Send the READ command (opcode + addr) */
875 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
876 IXGBE_EEPROM_OPCODE_BITS);
877 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
878 hw->eeprom.address_bits);
879
880 /* Read the data. */
881 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
882 data[i] = (word_in >> 8) | (word_in << 8);
883 }
c44ade9e 884
68c7005d
ET		 885 /* End this read operation */
886 ixgbe_release_eeprom(hw);
887 }
c44ade9e 888
68c7005d
ET		 889 return status;
890}
c44ade9e 891
68c7005d
ET		 892/**
893 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
894 * @hw: pointer to hardware structure
895 * @offset: offset within the EEPROM to be read
896 * @data: read 16 bit value from EEPROM
897 *
898 * Reads 16 bit value from EEPROM through bit-bang method
899 **/
900s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
901 u16 *data)
902{
903 s32 status;
c44ade9e 904
68c7005d
ET		 905 hw->eeprom.ops.init_params(hw);
906
907 if (offset >= hw->eeprom.word_size) {
908 status = IXGBE_ERR_EEPROM;
909 goto out;
c44ade9e
JB		 910 }
911
68c7005d
ET		 912 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
913
c44ade9e
JB		 914out:
915 return status;
916}
917
918/**
68c7005d 919 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 920 * @hw: pointer to hardware structure
68c7005d
ET		 921 * @offset: offset of word in the EEPROM to read
922 * @words: number of word(s)
923 * @data: 16 bit word(s) from the EEPROM
9a799d71 924 *
68c7005d 925 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 926 **/
68c7005d
ET		 927s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
928 u16 words, u16 *data)
9a799d71
AK		 929{
930 u32 eerd;
68c7005d
ET		 931 s32 status = 0;
932 u32 i;
9a799d71 933
c44ade9e
JB		 934 hw->eeprom.ops.init_params(hw);
935
68c7005d
ET		 936 if (words == 0) {
937 status = IXGBE_ERR_INVALID_ARGUMENT;
938 goto out;
939 }
940
c44ade9e
JB		 941 if (offset >= hw->eeprom.word_size) {
942 status = IXGBE_ERR_EEPROM;
943 goto out;
944 }
945
68c7005d
ET		 946 for (i = 0; i < words; i++) {
947 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
948 IXGBE_EEPROM_RW_REG_START;
9a799d71 949
68c7005d
ET		 950 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
951 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 952
68c7005d
ET		 953 if (status == 0) {
954 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
955 IXGBE_EEPROM_RW_REG_DATA);
956 } else {
957 hw_dbg(hw, "Eeprom read timed out\n");
958 goto out;
959 }
960 }
961out:
962 return status;
963}
9a799d71 964
68c7005d
ET		 965/**
966 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
967 * @hw: pointer to hardware structure
968 * @offset: offset within the EEPROM to be used as a scratch pad
969 *
970 * Discover EEPROM page size by writing marching data at given offset.
971 * This function is called only when we are writing a new large buffer
972 * at given offset so the data would be overwritten anyway.
973 **/
974static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
975 u16 offset)
976{
977 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
978 s32 status = 0;
979 u16 i;
980
981 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
982 data[i] = i;
983
984 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
985 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
986 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
987 hw->eeprom.word_page_size = 0;
988 if (status != 0)
989 goto out;
990
991 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
992 if (status != 0)
993 goto out;
994
995 /*
996 * When writing in burst more than the actual page size
997 * EEPROM address wraps around current page.
998 */
999 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1000
1001 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1002 hw->eeprom.word_page_size);
c44ade9e 1003out:
9a799d71
AK		 1004 return status;
1005}
1006
eb9c3e3e 1007/**
68c7005d
ET		 1008 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1009 * @hw: pointer to hardware structure
1010 * @offset: offset of word in the EEPROM to read
1011 * @data: word read from the EEPROM
1012 *
1013 * Reads a 16 bit word from the EEPROM using the EERD register.
1014 **/
1015s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1016{
1017 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1018}
1019
1020/**
1021 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1022 * @hw: pointer to hardware structure
1023 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1024 * @words: number of words
1025 * @data: word(s) write to the EEPROM
eb9c3e3e 1026 *
68c7005d 1027 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1028 **/
68c7005d
ET		 1029s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1030 u16 words, u16 *data)
eb9c3e3e
ET		 1031{
1032 u32 eewr;
68c7005d
ET		 1033 s32 status = 0;
1034 u16 i;
eb9c3e3e
ET		 1035
1036 hw->eeprom.ops.init_params(hw);
1037
68c7005d
ET		 1038 if (words == 0) {
1039 status = IXGBE_ERR_INVALID_ARGUMENT;
1040 goto out;
1041 }
1042
eb9c3e3e
ET		 1043 if (offset >= hw->eeprom.word_size) {
1044 status = IXGBE_ERR_EEPROM;
1045 goto out;
1046 }
1047
68c7005d
ET		 1048 for (i = 0; i < words; i++) {
1049 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1050 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1051 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1052
68c7005d
ET		 1053 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1054 if (status != 0) {
1055 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1056 goto out;
1057 }
eb9c3e3e 1058
68c7005d 1059 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1060
68c7005d
ET		 1061 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1062 if (status != 0) {
1063 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1064 goto out;
1065 }
eb9c3e3e
ET		 1066 }
1067
1068out:
1069 return status;
1070}
1071
68c7005d
ET		 1072/**
1073 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1074 * @hw: pointer to hardware structure
1075 * @offset: offset of word in the EEPROM to write
1076 * @data: word write to the EEPROM
1077 *
1078 * Write a 16 bit word to the EEPROM using the EEWR register.
1079 **/
1080s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1081{
1082 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1083}
1084
9a799d71 1085/**
21ce849b 1086 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1087 * @hw: pointer to hardware structure
21ce849b 1088 * @ee_reg: EEPROM flag for polling
9a799d71 1089 *
21ce849b
MC		 1090 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1091 * read or write is done respectively.
9a799d71 1092 **/
eb9c3e3e 1093static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1094{
1095 u32 i;
1096 u32 reg;
1097 s32 status = IXGBE_ERR_EEPROM;
1098
21ce849b
MC		 1099 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1100 if (ee_reg == IXGBE_NVM_POLL_READ)
1101 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1102 else
1103 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1104
1105 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 1106 status = 0;
1107 break;
1108 }
1109 udelay(5);
1110 }
1111 return status;
1112}
1113
c44ade9e
JB		 1114/**
1115 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1116 * @hw: pointer to hardware structure
1117 *
1118 * Prepares EEPROM for access using bit-bang method. This function should
1119 * be called before issuing a command to the EEPROM.
1120 **/
1121static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1122{
1123 s32 status = 0;
dbf893ee 1124 u32 eec;
c44ade9e
JB		 1125 u32 i;
1126
5e655105 1127 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 1128 status = IXGBE_ERR_SWFW_SYNC;
1129
1130 if (status == 0) {
1131 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1132
1133 /* Request EEPROM Access */
1134 eec |= IXGBE_EEC_REQ;
1135 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1136
1137 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1138 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1139 if (eec & IXGBE_EEC_GNT)
1140 break;
1141 udelay(5);
1142 }
1143
1144 /* Release if grant not acquired */
1145 if (!(eec & IXGBE_EEC_GNT)) {
1146 eec &= ~IXGBE_EEC_REQ;
1147 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1148 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1149
5e655105 1150 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 1151 status = IXGBE_ERR_EEPROM;
1152 }
c44ade9e 1153
dbf893ee
ET		 1154 /* Setup EEPROM for Read/Write */
1155 if (status == 0) {
1156 /* Clear CS and SK */
1157 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1158 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1159 IXGBE_WRITE_FLUSH(hw);
1160 udelay(1);
1161 }
c44ade9e
JB		 1162 }
1163 return status;
1164}
1165
9a799d71
AK		 1166/**
1167 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1168 * @hw: pointer to hardware structure
1169 *
1170 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1171 **/
1172static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1173{
1174 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 1175 u32 timeout = 2000;
9a799d71
AK		 1176 u32 i;
1177 u32 swsm;
1178
9a799d71
AK		 1179 /* Get SMBI software semaphore between device drivers first */
1180 for (i = 0; i < timeout; i++) {
1181 /*
1182 * If the SMBI bit is 0 when we read it, then the bit will be
1183 * set and we have the semaphore
1184 */
1185 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1186 if (!(swsm & IXGBE_SWSM_SMBI)) {
1187 status = 0;
1188 break;
1189 }
dbf893ee 1190 udelay(50);
9a799d71
AK		 1191 }
1192
51275d37
ET		 1193 if (i == timeout) {
1194 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1195 "not granted.\n");
1196 /*
1197 * this release is particularly important because our attempts
1198 * above to get the semaphore may have succeeded, and if there
1199 * was a timeout, we should unconditionally clear the semaphore
1200 * bits to free the driver to make progress
1201 */
1202 ixgbe_release_eeprom_semaphore(hw);
1203
1204 udelay(50);
1205 /*
1206 * one last try
1207 * If the SMBI bit is 0 when we read it, then the bit will be
1208 * set and we have the semaphore
1209 */
1210 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1211 if (!(swsm & IXGBE_SWSM_SMBI))
1212 status = 0;
1213 }
1214
9a799d71
AK		 1215 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1216 if (status == 0) {
1217 for (i = 0; i < timeout; i++) {
1218 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1219
1220 /* Set the SW EEPROM semaphore bit to request access */
1221 swsm |= IXGBE_SWSM_SWESMBI;
1222 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1223
1224 /*
1225 * If we set the bit successfully then we got the
1226 * semaphore.
1227 */
1228 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1229 if (swsm & IXGBE_SWSM_SWESMBI)
1230 break;
1231
1232 udelay(50);
1233 }
1234
1235 /*
1236 * Release semaphores and return error if SW EEPROM semaphore
1237 * was not granted because we don't have access to the EEPROM
1238 */
1239 if (i >= timeout) {
dbf893ee 1240 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 1241 "not granted.\n");
9a799d71
AK		 1242 ixgbe_release_eeprom_semaphore(hw);
1243 status = IXGBE_ERR_EEPROM;
1244 }
dbf893ee
ET		 1245 } else {
1246 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1247 "not granted.\n");
9a799d71
AK		 1248 }
1249
1250 return status;
1251}
1252
1253/**
1254 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1255 * @hw: pointer to hardware structure
1256 *
1257 * This function clears hardware semaphore bits.
1258 **/
1259static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1260{
1261 u32 swsm;
1262
1263 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1264
1265 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1266 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1267 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1268 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1269}
1270
c44ade9e
JB		 1271/**
1272 * ixgbe_ready_eeprom - Polls for EEPROM ready
1273 * @hw: pointer to hardware structure
1274 **/
1275static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1276{
1277 s32 status = 0;
1278 u16 i;
1279 u8 spi_stat_reg;
1280
1281 /*
1282 * Read "Status Register" repeatedly until the LSB is cleared. The
1283 * EEPROM will signal that the command has been completed by clearing
1284 * bit 0 of the internal status register. If it's not cleared within
1285 * 5 milliseconds, then error out.
1286 */
1287 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1288 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1289 IXGBE_EEPROM_OPCODE_BITS);
1290 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1291 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1292 break;
1293
1294 udelay(5);
1295 ixgbe_standby_eeprom(hw);
6403eab1 1296 }
c44ade9e
JB		 1297
1298 /*
1299 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1300 * devices (and only 0-5mSec on 5V devices)
1301 */
1302 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1303 hw_dbg(hw, "SPI EEPROM Status error\n");
1304 status = IXGBE_ERR_EEPROM;
1305 }
1306
1307 return status;
1308}
1309
1310/**
1311 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1312 * @hw: pointer to hardware structure
1313 **/
1314static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1315{
1316 u32 eec;
1317
1318 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1319
1320 /* Toggle CS to flush commands */
1321 eec |= IXGBE_EEC_CS;
1322 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1323 IXGBE_WRITE_FLUSH(hw);
1324 udelay(1);
1325 eec &= ~IXGBE_EEC_CS;
1326 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1327 IXGBE_WRITE_FLUSH(hw);
1328 udelay(1);
1329}
1330
1331/**
1332 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1333 * @hw: pointer to hardware structure
1334 * @data: data to send to the EEPROM
1335 * @count: number of bits to shift out
1336 **/
1337static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1338 u16 count)
1339{
1340 u32 eec;
1341 u32 mask;
1342 u32 i;
1343
1344 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1345
1346 /*
1347 * Mask is used to shift "count" bits of "data" out to the EEPROM
1348 * one bit at a time. Determine the starting bit based on count
1349 */
1350 mask = 0x01 << (count - 1);
1351
1352 for (i = 0; i < count; i++) {
1353 /*
1354 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1355 * "1", and then raising and then lowering the clock (the SK
1356 * bit controls the clock input to the EEPROM). A "0" is
1357 * shifted out to the EEPROM by setting "DI" to "0" and then
1358 * raising and then lowering the clock.
1359 */
1360 if (data & mask)
1361 eec |= IXGBE_EEC_DI;
1362 else
1363 eec &= ~IXGBE_EEC_DI;
1364
1365 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1366 IXGBE_WRITE_FLUSH(hw);
1367
1368 udelay(1);
1369
1370 ixgbe_raise_eeprom_clk(hw, &eec);
1371 ixgbe_lower_eeprom_clk(hw, &eec);
1372
1373 /*
1374 * Shift mask to signify next bit of data to shift in to the
1375 * EEPROM
1376 */
1377 mask = mask >> 1;
6403eab1 1378 }
c44ade9e
JB		 1379
1380 /* We leave the "DI" bit set to "0" when we leave this routine. */
1381 eec &= ~IXGBE_EEC_DI;
1382 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1383 IXGBE_WRITE_FLUSH(hw);
1384}
1385
1386/**
1387 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1388 * @hw: pointer to hardware structure
1389 **/
1390static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1391{
1392 u32 eec;
1393 u32 i;
1394 u16 data = 0;
1395
1396 /*
1397 * In order to read a register from the EEPROM, we need to shift
1398 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1399 * the clock input to the EEPROM (setting the SK bit), and then reading
1400 * the value of the "DO" bit. During this "shifting in" process the
1401 * "DI" bit should always be clear.
1402 */
1403 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1404
1405 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1406
1407 for (i = 0; i < count; i++) {
1408 data = data << 1;
1409 ixgbe_raise_eeprom_clk(hw, &eec);
1410
1411 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1412
1413 eec &= ~(IXGBE_EEC_DI);
1414 if (eec & IXGBE_EEC_DO)
1415 data |= 1;
1416
1417 ixgbe_lower_eeprom_clk(hw, &eec);
1418 }
1419
1420 return data;
1421}
1422
1423/**
1424 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1425 * @hw: pointer to hardware structure
1426 * @eec: EEC register's current value
1427 **/
1428static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1429{
1430 /*
1431 * Raise the clock input to the EEPROM
1432 * (setting the SK bit), then delay
1433 */
1434 *eec = *eec | IXGBE_EEC_SK;
1435 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1436 IXGBE_WRITE_FLUSH(hw);
1437 udelay(1);
1438}
1439
1440/**
1441 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1442 * @hw: pointer to hardware structure
1443 * @eecd: EECD's current value
1444 **/
1445static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1446{
1447 /*
1448 * Lower the clock input to the EEPROM (clearing the SK bit), then
1449 * delay
1450 */
1451 *eec = *eec & ~IXGBE_EEC_SK;
1452 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1453 IXGBE_WRITE_FLUSH(hw);
1454 udelay(1);
1455}
1456
1457/**
1458 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1459 * @hw: pointer to hardware structure
1460 **/
1461static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1462{
1463 u32 eec;
1464
1465 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1466
1467 eec |= IXGBE_EEC_CS; /* Pull CS high */
1468 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1469
1470 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1471 IXGBE_WRITE_FLUSH(hw);
1472
1473 udelay(1);
1474
1475 /* Stop requesting EEPROM access */
1476 eec &= ~IXGBE_EEC_REQ;
1477 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1478
90827996 1479 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1480
032b4325
DS		 1481 /*
1482 * Delay before attempt to obtain semaphore again to allow FW
1483 * access. semaphore_delay is in ms we need us for usleep_range
1484 */
1485 usleep_range(hw->eeprom.semaphore_delay * 1000,
1486 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1487}
1488
9a799d71 1489/**
dbf893ee 1490 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1491 * @hw: pointer to hardware structure
1492 **/
a391f1d5 1493u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1494{
1495 u16 i;
1496 u16 j;
1497 u16 checksum = 0;
1498 u16 length = 0;
1499 u16 pointer = 0;
1500 u16 word = 0;
1501
1502 /* Include 0x0-0x3F in the checksum */
1503 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1504 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1505 hw_dbg(hw, "EEPROM read failed\n");
1506 break;
1507 }
1508 checksum += word;
1509 }
1510
1511 /* Include all data from pointers except for the fw pointer */
1512 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1513 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1514
1515 /* Make sure the pointer seems valid */
1516 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1517 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1518
1519 if (length != 0xFFFF && length != 0) {
1520 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1521 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1522 checksum += word;
1523 }
1524 }
1525 }
1526 }
1527
1528 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1529
1530 return checksum;
1531}
1532
1533/**
c44ade9e 1534 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1535 * @hw: pointer to hardware structure
1536 * @checksum_val: calculated checksum
1537 *
1538 * Performs checksum calculation and validates the EEPROM checksum. If the
1539 * caller does not need checksum_val, the value can be NULL.
1540 **/
c44ade9e
JB		 1541s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1542 u16 *checksum_val)
9a799d71
AK		 1543{
1544 s32 status;
1545 u16 checksum;
1546 u16 read_checksum = 0;
1547
1548 /*
1549 * Read the first word from the EEPROM. If this times out or fails, do
1550 * not continue or we could be in for a very long wait while every
1551 * EEPROM read fails
1552 */
c44ade9e 1553 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1554
1555 if (status == 0) {
a391f1d5 1556 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1557
c44ade9e 1558 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1559
1560 /*
1561 * Verify read checksum from EEPROM is the same as
1562 * calculated checksum
1563 */
1564 if (read_checksum != checksum)
1565 status = IXGBE_ERR_EEPROM_CHECKSUM;
1566
1567 /* If the user cares, return the calculated checksum */
1568 if (checksum_val)
1569 *checksum_val = checksum;
1570 } else {
1571 hw_dbg(hw, "EEPROM read failed\n");
1572 }
1573
1574 return status;
1575}
1576
c44ade9e
JB		 1577/**
1578 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1579 * @hw: pointer to hardware structure
1580 **/
1581s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1582{
1583 s32 status;
1584 u16 checksum;
1585
1586 /*
1587 * Read the first word from the EEPROM. If this times out or fails, do
1588 * not continue or we could be in for a very long wait while every
1589 * EEPROM read fails
1590 */
1591 status = hw->eeprom.ops.read(hw, 0, &checksum);
1592
1593 if (status == 0) {
a391f1d5 1594 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1595 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1596 checksum);
c44ade9e
JB		 1597 } else {
1598 hw_dbg(hw, "EEPROM read failed\n");
1599 }
1600
1601 return status;
1602}
1603
9a799d71
AK		 1604/**
1605 * ixgbe_validate_mac_addr - Validate MAC address
1606 * @mac_addr: pointer to MAC address.
1607 *
1608 * Tests a MAC address to ensure it is a valid Individual Address
1609 **/
1610s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1611{
1612 s32 status = 0;
1613
1614 /* Make sure it is not a multicast address */
1615 if (IXGBE_IS_MULTICAST(mac_addr))
1616 status = IXGBE_ERR_INVALID_MAC_ADDR;
1617 /* Not a broadcast address */
1618 else if (IXGBE_IS_BROADCAST(mac_addr))
1619 status = IXGBE_ERR_INVALID_MAC_ADDR;
1620 /* Reject the zero address */
1621 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1622 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1623 status = IXGBE_ERR_INVALID_MAC_ADDR;
1624
1625 return status;
1626}
1627
1628/**
c44ade9e 1629 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1630 * @hw: pointer to hardware structure
9a799d71 1631 * @index: Receive address register to write
c44ade9e
JB		 1632 * @addr: Address to put into receive address register
1633 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1634 * @enable_addr: set flag that address is active
1635 *
1636 * Puts an ethernet address into a receive address register.
1637 **/
c44ade9e
JB		 1638s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1639 u32 enable_addr)
9a799d71
AK		 1640{
1641 u32 rar_low, rar_high;
c44ade9e
JB		 1642 u32 rar_entries = hw->mac.num_rar_entries;
1643
c700f4e6
ET		 1644 /* Make sure we are using a valid rar index range */
1645 if (index >= rar_entries) {
1646 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1647 return IXGBE_ERR_INVALID_ARGUMENT;
1648 }
1649
c44ade9e
JB		 1650 /* setup VMDq pool selection before this RAR gets enabled */
1651 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1652
c700f4e6
ET		 1653 /*
1654 * HW expects these in little endian so we reverse the byte
1655 * order from network order (big endian) to little endian
1656 */
1657 rar_low = ((u32)addr[0] |
1658 ((u32)addr[1] << 8) |
1659 ((u32)addr[2] << 16) |
1660 ((u32)addr[3] << 24));
1661 /*
1662 * Some parts put the VMDq setting in the extra RAH bits,
1663 * so save everything except the lower 16 bits that hold part
1664 * of the address and the address valid bit.
1665 */
1666 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1667 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1668 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1669
c700f4e6
ET		 1670 if (enable_addr != 0)
1671 rar_high |= IXGBE_RAH_AV;
9a799d71 1672
c700f4e6
ET		 1673 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1674 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1675
1676 return 0;
1677}
1678
1679/**
1680 * ixgbe_clear_rar_generic - Remove Rx address register
1681 * @hw: pointer to hardware structure
1682 * @index: Receive address register to write
1683 *
1684 * Clears an ethernet address from a receive address register.
1685 **/
1686s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1687{
1688 u32 rar_high;
1689 u32 rar_entries = hw->mac.num_rar_entries;
1690
1691 /* Make sure we are using a valid rar index range */
c700f4e6 1692 if (index >= rar_entries) {
c44ade9e 1693 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1694 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1695 }
1696
c700f4e6
ET		 1697 /*
1698 * Some parts put the VMDq setting in the extra RAH bits,
1699 * so save everything except the lower 16 bits that hold part
1700 * of the address and the address valid bit.
1701 */
1702 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1703 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1704
1705 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1706 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1707
c44ade9e
JB		 1708 /* clear VMDq pool/queue selection for this RAR */
1709 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1710
1711 return 0;
1712}
1713
c44ade9e
JB		 1714/**
1715 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1716 * @hw: pointer to hardware structure
1717 *
1718 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1719 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1720 * the receiver is in reset when the routine is called.
1721 **/
c44ade9e 1722s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1723{
1724 u32 i;
2c5645cf 1725 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1726
1727 /*
1728 * If the current mac address is valid, assume it is a software override
1729 * to the permanent address.
1730 * Otherwise, use the permanent address from the eeprom.
1731 */
1732 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1733 IXGBE_ERR_INVALID_MAC_ADDR) {
1734 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1735 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1736
ce7194d8 1737 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1738 } else {
1739 /* Setup the receive address. */
1740 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1741 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1742
c44ade9e 1743 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1744
1745 /* clear VMDq pool/queue selection for RAR 0 */
1746 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1747 }
c44ade9e 1748 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1749
1750 hw->addr_ctrl.rar_used_count = 1;
1751
1752 /* Zero out the other receive addresses. */
c44ade9e 1753 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1754 for (i = 1; i < rar_entries; i++) {
1755 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1756 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1757 }
1758
1759 /* Clear the MTA */
9a799d71
AK		 1760 hw->addr_ctrl.mta_in_use = 0;
1761 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1762
1763 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1764 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1765 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1766
c44ade9e
JB		 1767 if (hw->mac.ops.init_uta_tables)
1768 hw->mac.ops.init_uta_tables(hw);
1769
9a799d71
AK		 1770 return 0;
1771}
1772
1773/**
1774 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1775 * @hw: pointer to hardware structure
1776 * @mc_addr: the multicast address
1777 *
1778 * Extracts the 12 bits, from a multicast address, to determine which
1779 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1780 * incoming rx multicast addresses, to determine the bit-vector to check in
1781 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1782 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1783 * to mc_filter_type.
1784 **/
1785static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1786{
1787 u32 vector = 0;
1788
1789 switch (hw->mac.mc_filter_type) {
b4617240 1790 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1791 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1792 break;
b4617240 1793 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1794 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1795 break;
b4617240 1796 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1797 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1798 break;
b4617240 1799 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1800 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1801 break;
b4617240 1802 default: /* Invalid mc_filter_type */
9a799d71
AK		 1803 hw_dbg(hw, "MC filter type param set incorrectly\n");
1804 break;
1805 }
1806
1807 /* vector can only be 12-bits or boundary will be exceeded */
1808 vector &= 0xFFF;
1809 return vector;
1810}
1811
1812/**
1813 * ixgbe_set_mta - Set bit-vector in multicast table
1814 * @hw: pointer to hardware structure
1815 * @hash_value: Multicast address hash value
1816 *
1817 * Sets the bit-vector in the multicast table.
1818 **/
1819static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1820{
1821 u32 vector;
1822 u32 vector_bit;
1823 u32 vector_reg;
9a799d71
AK		 1824
1825 hw->addr_ctrl.mta_in_use++;
1826
1827 vector = ixgbe_mta_vector(hw, mc_addr);
1828 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1829
1830 /*
1831 * The MTA is a register array of 128 32-bit registers. It is treated
1832 * like an array of 4096 bits. We want to set bit
1833 * BitArray[vector_value]. So we figure out what register the bit is
1834 * in, read it, OR in the new bit, then write back the new value. The
1835 * register is determined by the upper 7 bits of the vector value and
1836 * the bit within that register are determined by the lower 5 bits of
1837 * the value.
1838 */
1839 vector_reg = (vector >> 5) & 0x7F;
1840 vector_bit = vector & 0x1F;
80960ab0 1841 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1842}
1843
9a799d71 1844/**
c44ade9e 1845 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1846 * @hw: pointer to hardware structure
2853eb89 1847 * @netdev: pointer to net device structure
9a799d71
AK		 1848 *
1849 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1850 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1851 * registers for the first multicast addresses, and hashes the rest into the
1852 * multicast table.
1853 **/
2853eb89
JP		 1854s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1855 struct net_device *netdev)
9a799d71 1856{
22bedad3 1857 struct netdev_hw_addr *ha;
9a799d71 1858 u32 i;
9a799d71
AK		 1859
1860 /*
1861 * Set the new number of MC addresses that we are being requested to
1862 * use.
1863 */
2853eb89 1864 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1865 hw->addr_ctrl.mta_in_use = 0;
1866
80960ab0 1867 /* Clear mta_shadow */
9a799d71 1868 hw_dbg(hw, " Clearing MTA\n");
80960ab0 1869 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 1870
80960ab0 1871 /* Update mta shadow */
22bedad3 1872 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1873 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1874 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1875 }
1876
1877 /* Enable mta */
80960ab0
ET		 1878 for (i = 0; i < hw->mac.mcft_size; i++)
1879 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1880 hw->mac.mta_shadow[i]);
1881
9a799d71
AK		 1882 if (hw->addr_ctrl.mta_in_use > 0)
1883 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1884 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1885
c44ade9e 1886 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1887 return 0;
1888}
1889
1890/**
c44ade9e 1891 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1892 * @hw: pointer to hardware structure
1893 *
c44ade9e 1894 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1895 **/
c44ade9e 1896s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1897{
c44ade9e 1898 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1899
c44ade9e
JB		 1900 if (a->mta_in_use > 0)
1901 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1902 hw->mac.mc_filter_type);
9a799d71
AK		 1903
1904 return 0;
1905}
1906
1907/**
c44ade9e 1908 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1909 * @hw: pointer to hardware structure
9a799d71 1910 *
c44ade9e 1911 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1912 **/
c44ade9e 1913s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1914{
c44ade9e 1915 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1916
c44ade9e
JB		 1917 if (a->mta_in_use > 0)
1918 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1919
1920 return 0;
1921}
1922
11afc1b1 1923/**
620fa036 1924 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1925 * @hw: pointer to hardware structure
1926 * @packetbuf_num: packet buffer number (0-7)
1927 *
1928 * Enable flow control according to the current settings.
1929 **/
620fa036 1930s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1931{
1932 s32 ret_val = 0;
620fa036 1933 u32 mflcn_reg, fccfg_reg;
11afc1b1 1934 u32 reg;
16b61beb 1935 u32 fcrtl, fcrth;
70b77628
PWJ		 1936
1937#ifdef CONFIG_DCB
1938 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1939 goto out;
1940
1941#endif /* CONFIG_DCB */
620fa036
MC		 1942 /* Negotiate the fc mode to use */
1943 ret_val = ixgbe_fc_autoneg(hw);
0b0c2b31 1944 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
620fa036 1945 goto out;
11afc1b1 1946
620fa036 1947 /* Disable any previous flow control settings */
11afc1b1
PW		 1948 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1949 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1950
1951 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1952 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1953
1954 /*
1955 * The possible values of fc.current_mode are:
1956 * 0: Flow control is completely disabled
1957 * 1: Rx flow control is enabled (we can receive pause frames,
1958 * but not send pause frames).
bb3daa4a
PW		 1959 * 2: Tx flow control is enabled (we can send pause frames but
1960 * we do not support receiving pause frames).
11afc1b1 1961 * 3: Both Rx and Tx flow control (symmetric) are enabled.
8c7bea32 1962#ifdef CONFIG_DCB
bb3daa4a 1963 * 4: Priority Flow Control is enabled.
8c7bea32 1964#endif
11afc1b1
PW		 1965 * other: Invalid.
1966 */
1967 switch (hw->fc.current_mode) {
1968 case ixgbe_fc_none:
620fa036
MC		 1969 /*
1970 * Flow control is disabled by software override or autoneg.
1971 * The code below will actually disable it in the HW.
1972 */
11afc1b1
PW		 1973 break;
1974 case ixgbe_fc_rx_pause:
1975 /*
1976 * Rx Flow control is enabled and Tx Flow control is
1977 * disabled by software override. Since there really
1978 * isn't a way to advertise that we are capable of RX
1979 * Pause ONLY, we will advertise that we support both
1980 * symmetric and asymmetric Rx PAUSE. Later, we will
1981 * disable the adapter's ability to send PAUSE frames.
1982 */
1983 mflcn_reg |= IXGBE_MFLCN_RFCE;
1984 break;
1985 case ixgbe_fc_tx_pause:
1986 /*
1987 * Tx Flow control is enabled, and Rx Flow control is
1988 * disabled by software override.
1989 */
1990 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1991 break;
1992 case ixgbe_fc_full:
1993 /* Flow control (both Rx and Tx) is enabled by SW override. */
1994 mflcn_reg |= IXGBE_MFLCN_RFCE;
1995 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1996 break;
bb3daa4a
PW		 1997#ifdef CONFIG_DCB
1998 case ixgbe_fc_pfc:
1999 goto out;
2000 break;
620fa036 2001#endif /* CONFIG_DCB */
11afc1b1
PW		 2002 default:
2003 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2004 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 2005 goto out;
2006 break;
2007 }
2008
620fa036 2009 /* Set 802.3x based flow control settings. */
2132d381 2010 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2011 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2012 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2013
9da712d2
JF		 2014 fcrth = hw->fc.high_water[packetbuf_num] << 10;
2015 fcrtl = hw->fc.low_water << 10;
264857b8 2016
16b61beb
JF		 2017 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2018 fcrth |= IXGBE_FCRTH_FCEN;
2019 if (hw->fc.send_xon)
2020 fcrtl |= IXGBE_FCRTL_XONE;
11afc1b1
PW		 2021 }
2022
16b61beb
JF		 2023 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2024 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2025
11afc1b1 2026 /* Configure pause time (2 TCs per register) */
70b77628 2027 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 2028 if ((packetbuf_num & 1) == 0)
2029 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2030 else
2031 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2032 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2033
2034 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2035
2036out:
2037 return ret_val;
2038}
2039
0ecc061d
PWJ		 2040/**
2041 * ixgbe_fc_autoneg - Configure flow control
2042 * @hw: pointer to hardware structure
2043 *
620fa036
MC		 2044 * Compares our advertised flow control capabilities to those advertised by
2045 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 2046 **/
2047s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2048{
0b0c2b31 2049 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
620fa036 2050 ixgbe_link_speed speed;
620fa036 2051 bool link_up;
0ecc061d 2052
0b0c2b31
ET		 2053 if (hw->fc.disable_fc_autoneg)
2054 goto out;
2055
0ecc061d 2056 /*
620fa036
MC		 2057 * AN should have completed when the cable was plugged in.
2058 * Look for reasons to bail out. Bail out if:
2059 * - FC autoneg is disabled, or if
539e5f02 2060 * - link is not up.
620fa036 2061 *
539e5f02 2062 * Since we're being called from an LSC, link is already known to be up.
620fa036 2063 * So use link_up_wait_to_complete=false.
0ecc061d 2064 */
620fa036 2065 hw->mac.ops.check_link(hw, &speed, &link_up, false);
0b0c2b31
ET		 2066 if (!link_up) {
2067 ret_val = IXGBE_ERR_FLOW_CONTROL;
0ecc061d
PWJ		 2068 goto out;
2069 }
2070
0b0c2b31
ET		 2071 switch (hw->phy.media_type) {
2072 /* Autoneg flow control on fiber adapters */
2073 case ixgbe_media_type_fiber:
2074 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2075 ret_val = ixgbe_fc_autoneg_fiber(hw);
2076 break;
000c486d 2077
0b0c2b31
ET		 2078 /* Autoneg flow control on backplane adapters */
2079 case ixgbe_media_type_backplane:
2080 ret_val = ixgbe_fc_autoneg_backplane(hw);
2081 break;
2082
2083 /* Autoneg flow control on copper adapters */
2084 case ixgbe_media_type_copper:
2085 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2086 ret_val = ixgbe_fc_autoneg_copper(hw);
2087 break;
2088
2089 default:
2090 break;
2091 }
2092
2093out:
2094 if (ret_val == 0) {
2095 hw->fc.fc_was_autonegged = true;
2096 } else {
2097 hw->fc.fc_was_autonegged = false;
2098 hw->fc.current_mode = hw->fc.requested_mode;
539e5f02 2099 }
0b0c2b31
ET		 2100 return ret_val;
2101}
2102
2103/**
2104 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2105 * @hw: pointer to hardware structure
2106 *
2107 * Enable flow control according on 1 gig fiber.
2108 **/
2109static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2110{
2111 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2112 s32 ret_val;
539e5f02
PWJ		 2113
2114 /*
2115 * On multispeed fiber at 1g, bail out if
2116 * - link is up but AN did not complete, or if
2117 * - link is up and AN completed but timed out
2118 */
0b0c2b31
ET		 2119
2120 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de
DS		 2121 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2122 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
0b0c2b31
ET		 2123 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2124 goto out;
539e5f02
PWJ		 2125 }
2126
0b0c2b31
ET		 2127 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2128 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2129
2130 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2131 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2132 IXGBE_PCS1GANA_ASM_PAUSE,
2133 IXGBE_PCS1GANA_SYM_PAUSE,
2134 IXGBE_PCS1GANA_ASM_PAUSE);
2135
2136out:
2137 return ret_val;
2138}
2139
2140/**
2141 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2142 * @hw: pointer to hardware structure
2143 *
2144 * Enable flow control according to IEEE clause 37.
2145 **/
2146static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2147{
2148 u32 links2, anlp1_reg, autoc_reg, links;
2149 s32 ret_val;
2150
9bbe3a57 2151 /*
0b0c2b31
ET		 2152 * On backplane, bail out if
2153 * - backplane autoneg was not completed, or if
2154 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2155 */
0b0c2b31
ET		 2156 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2157 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
9bbe3a57
PW		 2158 hw->fc.fc_was_autonegged = false;
2159 hw->fc.current_mode = hw->fc.requested_mode;
0b0c2b31 2160 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57
PW		 2161 goto out;
2162 }
2163
0b0c2b31
ET		 2164 if (hw->mac.type == ixgbe_mac_82599EB) {
2165 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2166 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2167 hw->fc.fc_was_autonegged = false;
2168 hw->fc.current_mode = hw->fc.requested_mode;
2169 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2170 goto out;
2171 }
2172 }
0ecc061d 2173 /*
0b0c2b31 2174 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2175 * local flow control settings accordingly
2176 */
0b0c2b31
ET		 2177 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2178 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2179
0b0c2b31
ET		 2180 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2181 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2182 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2183
2184out:
2185 return ret_val;
2186}
2187
2188/**
2189 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2190 * @hw: pointer to hardware structure
2191 *
2192 * Enable flow control according to IEEE clause 37.
2193 **/
2194static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2195{
2196 u16 technology_ability_reg = 0;
2197 u16 lp_technology_ability_reg = 0;
2198
2199 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2200 MDIO_MMD_AN,
2201 &technology_ability_reg);
2202 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2203 MDIO_MMD_AN,
2204 &lp_technology_ability_reg);
2205
2206 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2207 (u32)lp_technology_ability_reg,
2208 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2209 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2210}
2211
2212/**
2213 * ixgbe_negotiate_fc - Negotiate flow control
2214 * @hw: pointer to hardware structure
2215 * @adv_reg: flow control advertised settings
2216 * @lp_reg: link partner's flow control settings
2217 * @adv_sym: symmetric pause bit in advertisement
2218 * @adv_asm: asymmetric pause bit in advertisement
2219 * @lp_sym: symmetric pause bit in link partner advertisement
2220 * @lp_asm: asymmetric pause bit in link partner advertisement
2221 *
2222 * Find the intersection between advertised settings and link partner's
2223 * advertised settings
2224 **/
2225static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2226 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2227{
2228 if ((!(adv_reg)) || (!(lp_reg)))
2229 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2230
2231 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
0ecc061d 2232 /*
0b0c2b31
ET		 2233 * Now we need to check if the user selected Rx ONLY
2234 * of pause frames. In this case, we had to advertise
2235 * FULL flow control because we could not advertise RX
2236 * ONLY. Hence, we must now check to see if we need to
2237 * turn OFF the TRANSMISSION of PAUSE frames.
0ecc061d 2238 */
0b0c2b31
ET		 2239 if (hw->fc.requested_mode == ixgbe_fc_full) {
2240 hw->fc.current_mode = ixgbe_fc_full;
2241 hw_dbg(hw, "Flow Control = FULL.\n");
539e5f02 2242 } else {
0b0c2b31
ET		 2243 hw->fc.current_mode = ixgbe_fc_rx_pause;
2244 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
0ecc061d 2245 }
0b0c2b31
ET		 2246 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2247 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2248 hw->fc.current_mode = ixgbe_fc_tx_pause;
2249 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2250 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2251 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2252 hw->fc.current_mode = ixgbe_fc_rx_pause;
2253 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2254 } else {
2255 hw->fc.current_mode = ixgbe_fc_none;
2256 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 2257 }
0b0c2b31 2258 return 0;
0ecc061d
PWJ		 2259}
2260
11afc1b1 2261/**
620fa036 2262 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 2263 * @hw: pointer to hardware structure
2264 *
620fa036 2265 * Called at init time to set up flow control.
11afc1b1 2266 **/
7b25cdba 2267static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 2268{
2269 s32 ret_val = 0;
0b0c2b31
ET		 2270 u32 reg = 0, reg_bp = 0;
2271 u16 reg_cu = 0;
11afc1b1 2272
bb3daa4a
PW		 2273#ifdef CONFIG_DCB
2274 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
2275 hw->fc.current_mode = hw->fc.requested_mode;
2276 goto out;
2277 }
2278
0b0c2b31 2279#endif /* CONFIG_DCB */
11afc1b1
PW		 2280 /* Validate the packetbuf configuration */
2281 if (packetbuf_num < 0 || packetbuf_num > 7) {
2282 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
2283 "is 0-7\n", packetbuf_num);
2284 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2285 goto out;
2286 }
2287
2288 /*
2289 * Validate the water mark configuration. Zero water marks are invalid
2290 * because it causes the controller to just blast out fc packets.
2291 */
9da712d2
JF		 2292 if (!hw->fc.low_water ||
2293 !hw->fc.high_water[packetbuf_num] ||
2294 !hw->fc.pause_time) {
620fa036
MC		 2295 hw_dbg(hw, "Invalid water mark configuration\n");
2296 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2297 goto out;
11afc1b1
PW		 2298 }
2299
2300 /*
2301 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 2302 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 2303 */
2304 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2305 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
2306 "IEEE mode\n");
2307 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2308 goto out;
2309 }
2310
2311 /*
2312 * 10gig parts do not have a word in the EEPROM to determine the
2313 * default flow control setting, so we explicitly set it to full.
2314 */
2315 if (hw->fc.requested_mode == ixgbe_fc_default)
2316 hw->fc.requested_mode = ixgbe_fc_full;
2317
2318 /*
0b0c2b31
ET		 2319 * Set up the 1G and 10G flow control advertisement registers so the
2320 * HW will be able to do fc autoneg once the cable is plugged in. If
2321 * we link at 10G, the 1G advertisement is harmless and vice versa.
11afc1b1 2322 */
0b0c2b31
ET		 2323
2324 switch (hw->phy.media_type) {
2325 case ixgbe_media_type_fiber:
2326 case ixgbe_media_type_backplane:
2327 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2328 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2329 break;
2330
2331 case ixgbe_media_type_copper:
2332 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2333 MDIO_MMD_AN, &reg_cu);
2334 break;
2335
2336 default:
2337 ;
2338 }
11afc1b1 2339
620fa036
MC		 2340 /*
2341 * The possible values of fc.requested_mode are:
2342 * 0: Flow control is completely disabled
2343 * 1: Rx flow control is enabled (we can receive pause frames,
2344 * but not send pause frames).
2345 * 2: Tx flow control is enabled (we can send pause frames but
2346 * we do not support receiving pause frames).
2347 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2348#ifdef CONFIG_DCB
2349 * 4: Priority Flow Control is enabled.
2350#endif
2351 * other: Invalid.
2352 */
2353 switch (hw->fc.requested_mode) {
2354 case ixgbe_fc_none:
2355 /* Flow control completely disabled by software override. */
2356 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2357 if (hw->phy.media_type == ixgbe_media_type_backplane)
2358 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2359 IXGBE_AUTOC_ASM_PAUSE);
2360 else if (hw->phy.media_type == ixgbe_media_type_copper)
2361 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2362 break;
2363 case ixgbe_fc_rx_pause:
2364 /*
2365 * Rx Flow control is enabled and Tx Flow control is
2366 * disabled by software override. Since there really
2367 * isn't a way to advertise that we are capable of RX
2368 * Pause ONLY, we will advertise that we support both
2369 * symmetric and asymmetric Rx PAUSE. Later, we will
2370 * disable the adapter's ability to send PAUSE frames.
2371 */
2372 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2373 if (hw->phy.media_type == ixgbe_media_type_backplane)
2374 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2375 IXGBE_AUTOC_ASM_PAUSE);
2376 else if (hw->phy.media_type == ixgbe_media_type_copper)
2377 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2378 break;
2379 case ixgbe_fc_tx_pause:
2380 /*
2381 * Tx Flow control is enabled, and Rx Flow control is
2382 * disabled by software override.
2383 */
2384 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2385 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
0b0c2b31
ET		 2386 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2387 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2388 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2389 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2390 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2391 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2392 }
620fa036
MC		 2393 break;
2394 case ixgbe_fc_full:
2395 /* Flow control (both Rx and Tx) is enabled by SW override. */
2396 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2397 if (hw->phy.media_type == ixgbe_media_type_backplane)
2398 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2399 IXGBE_AUTOC_ASM_PAUSE);
2400 else if (hw->phy.media_type == ixgbe_media_type_copper)
2401 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2402 break;
2403#ifdef CONFIG_DCB
2404 case ixgbe_fc_pfc:
11afc1b1 2405 goto out;
620fa036
MC		 2406 break;
2407#endif /* CONFIG_DCB */
2408 default:
2409 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2410 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 2411 goto out;
2412 break;
2413 }
2414
0b0c2b31
ET		 2415 if (hw->mac.type != ixgbe_mac_X540) {
2416 /*
2417 * Enable auto-negotiation between the MAC & PHY;
2418 * the MAC will advertise clause 37 flow control.
2419 */
2420 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2421 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
620fa036 2422
0b0c2b31
ET		 2423 /* Disable AN timeout */
2424 if (hw->fc.strict_ieee)
2425 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
11afc1b1 2426
0b0c2b31
ET		 2427 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2428 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2429 }
539e5f02
PWJ		 2430
2431 /*
0b0c2b31
ET		 2432 * AUTOC restart handles negotiation of 1G and 10G on backplane
2433 * and copper. There is no need to set the PCS1GCTL register.
2434 *
539e5f02 2435 */
0b0c2b31
ET		 2436 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2437 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2438 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2439 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2440 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
2441 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
2442 MDIO_MMD_AN, reg_cu);
539e5f02 2443 }
539e5f02 2444
0b0c2b31 2445 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
11afc1b1
PW		 2446out:
2447 return ret_val;
2448}
2449
9a799d71
AK		 2450/**
2451 * ixgbe_disable_pcie_master - Disable PCI-express master access
2452 * @hw: pointer to hardware structure
2453 *
2454 * Disables PCI-Express master access and verifies there are no pending
2455 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2456 * bit hasn't caused the master requests to be disabled, else 0
2457 * is returned signifying master requests disabled.
2458 **/
ff9d1a5a 2459static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2460{
a4297dc2 2461 struct ixgbe_adapter *adapter = hw->back;
a4297dc2 2462 s32 status = 0;
ff9d1a5a
ET		 2463 u32 i;
2464 u16 value;
2465
2466 /* Always set this bit to ensure any future transactions are blocked */
2467 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2468
ff9d1a5a 2469 /* Exit if master requests are blocked */
a4297dc2
ET		 2470 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2471 goto out;
9a799d71 2472
ff9d1a5a 2473 /* Poll for master request bit to clear */
9a799d71 2474 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2475 udelay(100);
ff9d1a5a
ET		 2476 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2477 goto out;
a4297dc2
ET		 2478 }
2479
ff9d1a5a
ET		 2480 /*
2481 * Two consecutive resets are required via CTRL.RST per datasheet
2482 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2483 * of this need. The first reset prevents new master requests from
2484 * being issued by our device. We then must wait 1usec or more for any
2485 * remaining completions from the PCIe bus to trickle in, and then reset
2486 * again to clear out any effects they may have had on our device.
2487 */
a4297dc2 2488 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2489 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2490
2491 /*
2492 * Before proceeding, make sure that the PCIe block does not have
2493 * transactions pending.
2494 */
a4297dc2 2495 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
9a799d71 2496 udelay(100);
ff9d1a5a
ET		 2497 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2498 &value);
2499 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2500 goto out;
9a799d71
AK		 2501 }
2502
ff9d1a5a
ET		 2503 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2504 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
a4297dc2
ET		 2505
2506out:
9a799d71
AK		 2507 return status;
2508}
2509
9a799d71 2510/**
c44ade9e 2511 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2512 * @hw: pointer to hardware structure
c44ade9e 2513 * @mask: Mask to specify which semaphore to acquire
9a799d71 2514 *
da74cd4a 2515 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2516 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2517 **/
2518s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2519{
2520 u32 gssr;
2521 u32 swmask = mask;
2522 u32 fwmask = mask << 5;
2523 s32 timeout = 200;
2524
2525 while (timeout) {
dbf893ee
ET		 2526 /*
2527 * SW EEPROM semaphore bit is used for access to all
2528 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2529 */
9a799d71 2530 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2531 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2532
2533 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2534 if (!(gssr & (fwmask | swmask)))
2535 break;
2536
2537 /*
2538 * Firmware currently using resource (fwmask) or other software
2539 * thread currently using resource (swmask)
2540 */
2541 ixgbe_release_eeprom_semaphore(hw);
032b4325 2542 usleep_range(5000, 10000);
9a799d71
AK		 2543 timeout--;
2544 }
2545
2546 if (!timeout) {
dbf893ee 2547 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2548 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2549 }
2550
2551 gssr |= swmask;
2552 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2553
2554 ixgbe_release_eeprom_semaphore(hw);
2555 return 0;
2556}
2557
2558/**
2559 * ixgbe_release_swfw_sync - Release SWFW semaphore
2560 * @hw: pointer to hardware structure
c44ade9e 2561 * @mask: Mask to specify which semaphore to release
9a799d71 2562 *
da74cd4a 2563 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2564 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2565 **/
2566void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2567{
2568 u32 gssr;
2569 u32 swmask = mask;
2570
2571 ixgbe_get_eeprom_semaphore(hw);
2572
2573 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2574 gssr &= ~swmask;
2575 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2576
2577 ixgbe_release_eeprom_semaphore(hw);
2578}
2579
11afc1b1
PW		 2580/**
2581 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2582 * @hw: pointer to hardware structure
2583 * @regval: register value to write to RXCTRL
2584 *
2585 * Enables the Rx DMA unit
2586 **/
2587s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2588{
2589 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2590
2591 return 0;
2592}
87c12017
PW		 2593
2594/**
2595 * ixgbe_blink_led_start_generic - Blink LED based on index.
2596 * @hw: pointer to hardware structure
2597 * @index: led number to blink
2598 **/
2599s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2600{
2601 ixgbe_link_speed speed = 0;
2602 bool link_up = 0;
2603 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2604 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2605
2606 /*
2607 * Link must be up to auto-blink the LEDs;
2608 * Force it if link is down.
2609 */
2610 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2611
2612 if (!link_up) {
50ac58ba 2613 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2614 autoc_reg |= IXGBE_AUTOC_FLU;
2615 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
945a5151 2616 IXGBE_WRITE_FLUSH(hw);
032b4325 2617 usleep_range(10000, 20000);
87c12017
PW		 2618 }
2619
2620 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2621 led_reg |= IXGBE_LED_BLINK(index);
2622 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2623 IXGBE_WRITE_FLUSH(hw);
2624
2625 return 0;
2626}
2627
2628/**
2629 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2630 * @hw: pointer to hardware structure
2631 * @index: led number to stop blinking
2632 **/
2633s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2634{
2635 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2636 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2637
2638 autoc_reg &= ~IXGBE_AUTOC_FLU;
2639 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2640 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2641
2642 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2643 led_reg &= ~IXGBE_LED_BLINK(index);
2644 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2645 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2646 IXGBE_WRITE_FLUSH(hw);
2647
2648 return 0;
2649}
21ce849b
MC		 2650
2651/**
2652 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2653 * @hw: pointer to hardware structure
2654 * @san_mac_offset: SAN MAC address offset
2655 *
2656 * This function will read the EEPROM location for the SAN MAC address
2657 * pointer, and returns the value at that location. This is used in both
2658 * get and set mac_addr routines.
2659 **/
2660static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2661 u16 *san_mac_offset)
2662{
2663 /*
2664 * First read the EEPROM pointer to see if the MAC addresses are
2665 * available.
2666 */
2667 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2668
2669 return 0;
2670}
2671
2672/**
2673 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2674 * @hw: pointer to hardware structure
2675 * @san_mac_addr: SAN MAC address
2676 *
2677 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2678 * per-port, so set_lan_id() must be called before reading the addresses.
2679 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2680 * upon for non-SFP connections, so we must call it here.
2681 **/
2682s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2683{
2684 u16 san_mac_data, san_mac_offset;
2685 u8 i;
2686
2687 /*
2688 * First read the EEPROM pointer to see if the MAC addresses are
2689 * available. If they're not, no point in calling set_lan_id() here.
2690 */
2691 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2692
2693 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2694 /*
2695 * No addresses available in this EEPROM. It's not an
2696 * error though, so just wipe the local address and return.
2697 */
2698 for (i = 0; i < 6; i++)
2699 san_mac_addr[i] = 0xFF;
2700
2701 goto san_mac_addr_out;
2702 }
2703
2704 /* make sure we know which port we need to program */
2705 hw->mac.ops.set_lan_id(hw);
2706 /* apply the port offset to the address offset */
2707 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2708 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2709 for (i = 0; i < 3; i++) {
2710 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2711 san_mac_addr[i * 2] = (u8)(san_mac_data);
2712 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2713 san_mac_offset++;
2714 }
2715
2716san_mac_addr_out:
2717 return 0;
2718}
2719
2720/**
2721 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2722 * @hw: pointer to hardware structure
2723 *
2724 * Read PCIe configuration space, and get the MSI-X vector count from
2725 * the capabilities table.
2726 **/
2727u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2728{
2729 struct ixgbe_adapter *adapter = hw->back;
2730 u16 msix_count;
2731 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2732 &msix_count);
2733 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2734
2735 /* MSI-X count is zero-based in HW, so increment to give proper value */
2736 msix_count++;
2737
2738 return msix_count;
2739}
2740
2741/**
2742 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2743 * @hw: pointer to hardware struct
2744 * @rar: receive address register index to disassociate
2745 * @vmdq: VMDq pool index to remove from the rar
2746 **/
2747s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2748{
2749 u32 mpsar_lo, mpsar_hi;
2750 u32 rar_entries = hw->mac.num_rar_entries;
2751
c700f4e6
ET		 2752 /* Make sure we are using a valid rar index range */
2753 if (rar >= rar_entries) {
2754 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2755 return IXGBE_ERR_INVALID_ARGUMENT;
2756 }
21ce849b 2757
c700f4e6
ET		 2758 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2759 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2760
c700f4e6
ET		 2761 if (!mpsar_lo && !mpsar_hi)
2762 goto done;
21ce849b 2763
c700f4e6
ET		 2764 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2765 if (mpsar_lo) {
2766 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2767 mpsar_lo = 0;
2768 }
2769 if (mpsar_hi) {
2770 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2771 mpsar_hi = 0;
2772 }
2773 } else if (vmdq < 32) {
2774 mpsar_lo &= ~(1 << vmdq);
2775 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2776 } else {
c700f4e6
ET		 2777 mpsar_hi &= ~(1 << (vmdq - 32));
2778 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2779 }
2780
c700f4e6
ET		 2781 /* was that the last pool using this rar? */
2782 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2783 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2784done:
2785 return 0;
2786}
2787
2788/**
2789 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2790 * @hw: pointer to hardware struct
2791 * @rar: receive address register index to associate with a VMDq index
2792 * @vmdq: VMDq pool index
2793 **/
2794s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2795{
2796 u32 mpsar;
2797 u32 rar_entries = hw->mac.num_rar_entries;
2798
c700f4e6
ET		 2799 /* Make sure we are using a valid rar index range */
2800 if (rar >= rar_entries) {
21ce849b 2801 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2802 return IXGBE_ERR_INVALID_ARGUMENT;
2803 }
2804
2805 if (vmdq < 32) {
2806 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2807 mpsar |= 1 << vmdq;
2808 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2809 } else {
2810 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2811 mpsar |= 1 << (vmdq - 32);
2812 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2813 }
2814 return 0;
2815}
2816
2817/**
2818 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2819 * @hw: pointer to hardware structure
2820 **/
2821s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2822{
2823 int i;
2824
21ce849b
MC		 2825 for (i = 0; i < 128; i++)
2826 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2827
2828 return 0;
2829}
2830
2831/**
2832 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2833 * @hw: pointer to hardware structure
2834 * @vlan: VLAN id to write to VLAN filter
2835 *
2836 * return the VLVF index where this VLAN id should be placed
2837 *
2838 **/
5d5b7c39 2839static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2840{
2841 u32 bits = 0;
2842 u32 first_empty_slot = 0;
2843 s32 regindex;
2844
2845 /* short cut the special case */
2846 if (vlan == 0)
2847 return 0;
2848
2849 /*
2850 * Search for the vlan id in the VLVF entries. Save off the first empty
2851 * slot found along the way
2852 */
2853 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2854 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2855 if (!bits && !(first_empty_slot))
2856 first_empty_slot = regindex;
2857 else if ((bits & 0x0FFF) == vlan)
2858 break;
2859 }
2860
2861 /*
2862 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2863 * in the VLVF. Else use the first empty VLVF register for this
2864 * vlan id.
2865 */
2866 if (regindex >= IXGBE_VLVF_ENTRIES) {
2867 if (first_empty_slot)
2868 regindex = first_empty_slot;
2869 else {
2870 hw_dbg(hw, "No space in VLVF.\n");
2871 regindex = IXGBE_ERR_NO_SPACE;
2872 }
2873 }
2874
2875 return regindex;
2876}
2877
2878/**
2879 * ixgbe_set_vfta_generic - Set VLAN filter table
2880 * @hw: pointer to hardware structure
2881 * @vlan: VLAN id to write to VLAN filter
2882 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2883 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2884 *
2885 * Turn on/off specified VLAN in the VLAN filter table.
2886 **/
2887s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2888 bool vlan_on)
2889{
2890 s32 regindex;
2891 u32 bitindex;
2892 u32 vfta;
2893 u32 bits;
2894 u32 vt;
2895 u32 targetbit;
2896 bool vfta_changed = false;
2897
2898 if (vlan > 4095)
2899 return IXGBE_ERR_PARAM;
2900
2901 /*
2902 * this is a 2 part operation - first the VFTA, then the
2903 * VLVF and VLVFB if VT Mode is set
2904 * We don't write the VFTA until we know the VLVF part succeeded.
2905 */
2906
2907 /* Part 1
2908 * The VFTA is a bitstring made up of 128 32-bit registers
2909 * that enable the particular VLAN id, much like the MTA:
2910 * bits[11-5]: which register
2911 * bits[4-0]: which bit in the register
2912 */
2913 regindex = (vlan >> 5) & 0x7F;
2914 bitindex = vlan & 0x1F;
2915 targetbit = (1 << bitindex);
2916 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2917
2918 if (vlan_on) {
2919 if (!(vfta & targetbit)) {
2920 vfta |= targetbit;
2921 vfta_changed = true;
2922 }
2923 } else {
2924 if ((vfta & targetbit)) {
2925 vfta &= ~targetbit;
2926 vfta_changed = true;
2927 }
2928 }
2929
2930 /* Part 2
2931 * If VT Mode is set
2932 * Either vlan_on
2933 * make sure the vlan is in VLVF
2934 * set the vind bit in the matching VLVFB
2935 * Or !vlan_on
2936 * clear the pool bit and possibly the vind
2937 */
2938 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2939 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2940 s32 vlvf_index;
2941
2942 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2943 if (vlvf_index < 0)
2944 return vlvf_index;
2945
2946 if (vlan_on) {
2947 /* set the pool bit */
2948 if (vind < 32) {
2949 bits = IXGBE_READ_REG(hw,
2950 IXGBE_VLVFB(vlvf_index*2));
2951 bits |= (1 << vind);
2952 IXGBE_WRITE_REG(hw,
2953 IXGBE_VLVFB(vlvf_index*2),
2954 bits);
2955 } else {
2956 bits = IXGBE_READ_REG(hw,
2957 IXGBE_VLVFB((vlvf_index*2)+1));
2958 bits |= (1 << (vind-32));
2959 IXGBE_WRITE_REG(hw,
2960 IXGBE_VLVFB((vlvf_index*2)+1),
2961 bits);
2962 }
2963 } else {
2964 /* clear the pool bit */
2965 if (vind < 32) {
2966 bits = IXGBE_READ_REG(hw,
2967 IXGBE_VLVFB(vlvf_index*2));
2968 bits &= ~(1 << vind);
2969 IXGBE_WRITE_REG(hw,
2970 IXGBE_VLVFB(vlvf_index*2),
2971 bits);
2972 bits |= IXGBE_READ_REG(hw,
2973 IXGBE_VLVFB((vlvf_index*2)+1));
2974 } else {
2975 bits = IXGBE_READ_REG(hw,
2976 IXGBE_VLVFB((vlvf_index*2)+1));
2977 bits &= ~(1 << (vind-32));
2978 IXGBE_WRITE_REG(hw,
2979 IXGBE_VLVFB((vlvf_index*2)+1),
2980 bits);
2981 bits |= IXGBE_READ_REG(hw,
2982 IXGBE_VLVFB(vlvf_index*2));
2983 }
2984 }
2985
2986 /*
2987 * If there are still bits set in the VLVFB registers
2988 * for the VLAN ID indicated we need to see if the
2989 * caller is requesting that we clear the VFTA entry bit.
2990 * If the caller has requested that we clear the VFTA
2991 * entry bit but there are still pools/VFs using this VLAN
2992 * ID entry then ignore the request. We're not worried
2993 * about the case where we're turning the VFTA VLAN ID
2994 * entry bit on, only when requested to turn it off as
2995 * there may be multiple pools and/or VFs using the
2996 * VLAN ID entry. In that case we cannot clear the
2997 * VFTA bit until all pools/VFs using that VLAN ID have also
2998 * been cleared. This will be indicated by "bits" being
2999 * zero.
3000 */
3001 if (bits) {
3002 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3003 (IXGBE_VLVF_VIEN | vlan));
3004 if (!vlan_on) {
3005 /* someone wants to clear the vfta entry
3006 * but some pools/VFs are still using it.
3007 * Ignore it. */
3008 vfta_changed = false;
3009 }
3010 }
3011 else
3012 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3013 }
3014
3015 if (vfta_changed)
3016 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3017
3018 return 0;
3019}
3020
3021/**
3022 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3023 * @hw: pointer to hardware structure
3024 *
3025 * Clears the VLAN filer table, and the VMDq index associated with the filter
3026 **/
3027s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3028{
3029 u32 offset;
3030
3031 for (offset = 0; offset < hw->mac.vft_size; offset++)
3032 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3033
3034 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3035 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3036 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3037 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3038 }
3039
3040 return 0;
3041}
3042
3043/**
3044 * ixgbe_check_mac_link_generic - Determine link and speed status
3045 * @hw: pointer to hardware structure
3046 * @speed: pointer to link speed
3047 * @link_up: true when link is up
3048 * @link_up_wait_to_complete: bool used to wait for link up or not
3049 *
3050 * Reads the links register to determine if link is up and the current speed
3051 **/
3052s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3053 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3054{
48de36c5 3055 u32 links_reg, links_orig;
21ce849b
MC		 3056 u32 i;
3057
48de36c5
ET		 3058 /* clear the old state */
3059 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3060
21ce849b 3061 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3062
3063 if (links_orig != links_reg) {
3064 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3065 links_orig, links_reg);
3066 }
3067
21ce849b
MC		 3068 if (link_up_wait_to_complete) {
3069 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3070 if (links_reg & IXGBE_LINKS_UP) {
3071 *link_up = true;
3072 break;
3073 } else {
3074 *link_up = false;
3075 }
3076 msleep(100);
3077 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3078 }
3079 } else {
3080 if (links_reg & IXGBE_LINKS_UP)
3081 *link_up = true;
3082 else
3083 *link_up = false;
3084 }
3085
3086 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3087 IXGBE_LINKS_SPEED_10G_82599)
3088 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3089 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 3090 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 3091 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 3092 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3093 IXGBE_LINKS_SPEED_100_82599)
21ce849b 3094 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 3095 else
3096 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b 3097
21ce849b
MC		 3098 return 0;
3099}
a391f1d5
DS		 3100
3101/**
3102 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
3103 * the EEPROM
3104 * @hw: pointer to hardware structure
3105 * @wwnn_prefix: the alternative WWNN prefix
3106 * @wwpn_prefix: the alternative WWPN prefix
3107 *
3108 * This function will read the EEPROM from the alternative SAN MAC address
3109 * block to check the support for the alternative WWNN/WWPN prefix support.
3110 **/
3111s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3112 u16 *wwpn_prefix)
3113{
3114 u16 offset, caps;
3115 u16 alt_san_mac_blk_offset;
3116
3117 /* clear output first */
3118 *wwnn_prefix = 0xFFFF;
3119 *wwpn_prefix = 0xFFFF;
3120
3121 /* check if alternative SAN MAC is supported */
3122 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3123 &alt_san_mac_blk_offset);
3124
3125 if ((alt_san_mac_blk_offset == 0) ||
3126 (alt_san_mac_blk_offset == 0xFFFF))
3127 goto wwn_prefix_out;
3128
3129 /* check capability in alternative san mac address block */
3130 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3131 hw->eeprom.ops.read(hw, offset, &caps);
3132 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3133 goto wwn_prefix_out;
3134
3135 /* get the corresponding prefix for WWNN/WWPN */
3136 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3137 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3138
3139 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3140 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3141
3142wwn_prefix_out:
3143 return 0;
3144}
a985b6c3 3145
0b0c2b31
ET		 3146/**
3147 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
3148 * control
3149 * @hw: pointer to hardware structure
3150 *
3151 * There are several phys that do not support autoneg flow control. This
3152 * function check the device id to see if the associated phy supports
3153 * autoneg flow control.
3154 **/
3155static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
3156{
3157
3158 switch (hw->device_id) {
3159 case IXGBE_DEV_ID_X540T:
3160 return 0;
3161 case IXGBE_DEV_ID_82599_T3_LOM:
3162 return 0;
3163 default:
3164 return IXGBE_ERR_FC_NOT_SUPPORTED;
3165 }
3166}
3167
a985b6c3
GR		 3168/**
3169 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3170 * @hw: pointer to hardware structure
3171 * @enable: enable or disable switch for anti-spoofing
3172 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3173 *
3174 **/
3175void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3176{
3177 int j;
3178 int pf_target_reg = pf >> 3;
3179 int pf_target_shift = pf % 8;
3180 u32 pfvfspoof = 0;
3181
3182 if (hw->mac.type == ixgbe_mac_82598EB)
3183 return;
3184
3185 if (enable)
3186 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3187
3188 /*
3189 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3190 * MAC anti-spoof enables in each register array element.
3191 */
3192 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3193 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3194
3195 /* If not enabling anti-spoofing then done */
3196 if (!enable)
3197 return;
3198
3199 /*
3200 * The PF should be allowed to spoof so that it can support
3201 * emulation mode NICs. Reset the bit assigned to the PF
3202 */
3203 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3204 pfvfspoof ^= (1 << pf_target_shift);
3205 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3206}
3207
3208/**
3209 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3210 * @hw: pointer to hardware structure
3211 * @enable: enable or disable switch for VLAN anti-spoofing
3212 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3213 *
3214 **/
3215void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3216{
3217 int vf_target_reg = vf >> 3;
3218 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3219 u32 pfvfspoof;
3220
3221 if (hw->mac.type == ixgbe_mac_82598EB)
3222 return;
3223
3224 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3225 if (enable)
3226 pfvfspoof |= (1 << vf_target_shift);
3227 else
3228 pfvfspoof &= ~(1 << vf_target_shift);
3229 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3230}
b776d104
ET		 3231
3232/**
3233 * ixgbe_get_device_caps_generic - Get additional device capabilities
3234 * @hw: pointer to hardware structure
3235 * @device_caps: the EEPROM word with the extra device capabilities
3236 *
3237 * This function will read the EEPROM location for the device capabilities,
3238 * and return the word through device_caps.
3239 **/
3240s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3241{
3242 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3243
3244 return 0;
3245}
80605c65
JF		 3246
3247/**
3248 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3249 * @hw: pointer to hardware structure
3250 * @num_pb: number of packet buffers to allocate
3251 * @headroom: reserve n KB of headroom
3252 * @strategy: packet buffer allocation strategy
3253 **/
3254void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3255 int num_pb,
3256 u32 headroom,
3257 int strategy)
3258{
3259 u32 pbsize = hw->mac.rx_pb_size;
3260 int i = 0;
3261 u32 rxpktsize, txpktsize, txpbthresh;
3262
3263 /* Reserve headroom */
3264 pbsize -= headroom;
3265
3266 if (!num_pb)
3267 num_pb = 1;
3268
3269 /* Divide remaining packet buffer space amongst the number
3270 * of packet buffers requested using supplied strategy.
3271 */
3272 switch (strategy) {
3273 case (PBA_STRATEGY_WEIGHTED):
3274 /* pba_80_48 strategy weight first half of packet buffer with
3275 * 5/8 of the packet buffer space.
3276 */
3277 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3278 pbsize -= rxpktsize * (num_pb / 2);
3279 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3280 for (; i < (num_pb / 2); i++)
3281 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3282 /* Fall through to configure remaining packet buffers */
3283 case (PBA_STRATEGY_EQUAL):
3284 /* Divide the remaining Rx packet buffer evenly among the TCs */
3285 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3286 for (; i < num_pb; i++)
3287 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3288 break;
3289 default:
3290 break;
3291 }
3292
3293 /*
3294 * Setup Tx packet buffer and threshold equally for all TCs
3295 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3296 * 10 since the largest packet we support is just over 9K.
3297 */
3298 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3299 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3300 for (i = 0; i < num_pb; i++) {
3301 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3302 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3303 }
3304
3305 /* Clear unused TCs, if any, to zero buffer size*/
3306 for (; i < IXGBE_MAX_PB; i++) {
3307 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3308 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3309 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3310 }
3311}
9612de92
ET		 3312
3313/**
3314 * ixgbe_calculate_checksum - Calculate checksum for buffer
3315 * @buffer: pointer to EEPROM
3316 * @length: size of EEPROM to calculate a checksum for
3317 * Calculates the checksum for some buffer on a specified length. The
3318 * checksum calculated is returned.
3319 **/
3320static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3321{
3322 u32 i;
3323 u8 sum = 0;
3324
3325 if (!buffer)
3326 return 0;
3327
3328 for (i = 0; i < length; i++)
3329 sum += buffer[i];
3330
3331 return (u8) (0 - sum);
3332}
3333
3334/**
3335 * ixgbe_host_interface_command - Issue command to manageability block
3336 * @hw: pointer to the HW structure
3337 * @buffer: contains the command to write and where the return status will
3338 * be placed
3339 * @lenght: lenght of buffer, must be multiple of 4 bytes
3340 *
3341 * Communicates with the manageability block. On success return 0
3342 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3343 **/
79488c58 3344static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
9612de92
ET		 3345 u32 length)
3346{
3347 u32 hicr, i;
3348 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3349 u8 buf_len, dword_len;
3350
3351 s32 ret_val = 0;
3352
3353 if (length == 0 || length & 0x3 ||
3354 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3355 hw_dbg(hw, "Buffer length failure.\n");
3356 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3357 goto out;
3358 }
3359
3360 /* Check that the host interface is enabled. */
3361 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3362 if ((hicr & IXGBE_HICR_EN) == 0) {
3363 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3364 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3365 goto out;
3366 }
3367
3368 /* Calculate length in DWORDs */
3369 dword_len = length >> 2;
3370
3371 /*
3372 * The device driver writes the relevant command block
3373 * into the ram area.
3374 */
3375 for (i = 0; i < dword_len; i++)
3376 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3377 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3378
3379 /* Setting this bit tells the ARC that a new command is pending. */
3380 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3381
3382 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3383 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3384 if (!(hicr & IXGBE_HICR_C))
3385 break;
3386 usleep_range(1000, 2000);
3387 }
3388
3389 /* Check command successful completion. */
3390 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3391 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3392 hw_dbg(hw, "Command has failed with no status valid.\n");
3393 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3394 goto out;
3395 }
3396
3397 /* Calculate length in DWORDs */
3398 dword_len = hdr_size >> 2;
3399
3400 /* first pull in the header so we know the buffer length */
79488c58
ET		 3401 for (i = 0; i < dword_len; i++) {
3402 buffer[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3403 le32_to_cpus(&buffer[i]);
3404 }
9612de92
ET		 3405
3406 /* If there is any thing in data position pull it in */
3407 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3408 if (buf_len == 0)
3409 goto out;
3410
3411 if (length < (buf_len + hdr_size)) {
3412 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3413 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3414 goto out;
3415 }
3416
3417 /* Calculate length in DWORDs, add one for odd lengths */
3418 dword_len = (buf_len + 1) >> 2;
3419
3420 /* Pull in the rest of the buffer (i is where we left off)*/
3421 for (; i < buf_len; i++)
79488c58 3422 buffer[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
9612de92
ET		 3423
3424out:
3425 return ret_val;
3426}
3427
3428/**
3429 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3430 * @hw: pointer to the HW structure
3431 * @maj: driver version major number
3432 * @min: driver version minor number
3433 * @build: driver version build number
3434 * @sub: driver version sub build number
3435 *
3436 * Sends driver version number to firmware through the manageability
3437 * block. On success return 0
3438 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3439 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3440 **/
3441s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3442 u8 build, u8 sub)
3443{
3444 struct ixgbe_hic_drv_info fw_cmd;
3445 int i;
3446 s32 ret_val = 0;
3447
3448 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3449 ret_val = IXGBE_ERR_SWFW_SYNC;
3450 goto out;
3451 }
3452
3453 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3454 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3455 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3456 fw_cmd.port_num = (u8)hw->bus.func;
3457 fw_cmd.ver_maj = maj;
3458 fw_cmd.ver_min = min;
3459 fw_cmd.ver_build = build;
3460 fw_cmd.ver_sub = sub;
3461 fw_cmd.hdr.checksum = 0;
3462 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3463 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3464 fw_cmd.pad = 0;
3465 fw_cmd.pad2 = 0;
3466
3467 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3468 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
9612de92
ET		 3469 sizeof(fw_cmd));
3470 if (ret_val != 0)
3471 continue;
3472
3473 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3474 FW_CEM_RESP_STATUS_SUCCESS)
3475 ret_val = 0;
3476 else
3477 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3478
3479 break;
3480 }
3481
3482 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3483out:
3484 return ret_val;
3485}
ff9d1a5a
ET		 3486
3487/**
3488 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3489 * @hw: pointer to the hardware structure
3490 *
3491 * The 82599 and x540 MACs can experience issues if TX work is still pending
3492 * when a reset occurs. This function prevents this by flushing the PCIe
3493 * buffers on the system.
3494 **/
3495void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3496{
3497 u32 gcr_ext, hlreg0;
3498
3499 /*
3500 * If double reset is not requested then all transactions should
3501 * already be clear and as such there is no work to do
3502 */
3503 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3504 return;
3505
3506 /*
3507 * Set loopback enable to prevent any transmits from being sent
3508 * should the link come up. This assumes that the RXCTRL.RXEN bit
3509 * has already been cleared.
3510 */
3511 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3512 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3513
3514 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3515 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3516 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3517 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3518
3519 /* Flush all writes and allow 20usec for all transactions to clear */
3520 IXGBE_WRITE_FLUSH(hw);
3521 udelay(20);
3522
3523 /* restore previous register values */
3524 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3525 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3526}
Linux kernel - Deliverables
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