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ixgbe: add check for supported modes
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
0b0c2b31
ET		 50static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
51static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
52static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
53static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
54static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
7b25cdba 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
eb9c3e3e 57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 58static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
61 u16 words, u16 *data);
62static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 u16 offset);
9a799d71
AK		 64
65/**
c44ade9e 66 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 67 * @hw: pointer to hardware structure
68 *
69 * Starts the hardware by filling the bus info structure and media type, clears
70 * all on chip counters, initializes receive address registers, multicast
71 * table, VLAN filter table, calls routine to set up link and flow control
72 * settings, and leaves transmit and receive units disabled and uninitialized
73 **/
c44ade9e 74s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 75{
76 u32 ctrl_ext;
77
78 /* Set the media type */
79 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
80
81 /* Identify the PHY */
c44ade9e 82 hw->phy.ops.identify(hw);
9a799d71 83
9a799d71 84 /* Clear the VLAN filter table */
c44ade9e 85 hw->mac.ops.clear_vfta(hw);
9a799d71 86
9a799d71 87 /* Clear statistics registers */
c44ade9e 88 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 89
90 /* Set No Snoop Disable */
91 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
92 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
93 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 94 IXGBE_WRITE_FLUSH(hw);
9a799d71 95
620fa036
MC		 96 /* Setup flow control */
97 ixgbe_setup_fc(hw, 0);
98
9a799d71
AK		 99 /* Clear adapter stopped flag */
100 hw->adapter_stopped = false;
101
102 return 0;
103}
104
7184b7cf
ET		 105/**
106 * ixgbe_start_hw_gen2 - Init sequence for common device family
107 * @hw: pointer to hw structure
108 *
109 * Performs the init sequence common to the second generation
110 * of 10 GbE devices.
111 * Devices in the second generation:
112 * 82599
113 * X540
114 **/
115s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
116{
117 u32 i;
3d5c5207 118 u32 regval;
7184b7cf
ET		 119
120 /* Clear the rate limiters */
121 for (i = 0; i < hw->mac.max_tx_queues; i++) {
122 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
123 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
124 }
125 IXGBE_WRITE_FLUSH(hw);
126
3d5c5207
ET		 127 /* Disable relaxed ordering */
128 for (i = 0; i < hw->mac.max_tx_queues; i++) {
129 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
130 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
131 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
132 }
133
134 for (i = 0; i < hw->mac.max_rx_queues; i++) {
135 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
136 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
137 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
138 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
139 }
140
7184b7cf
ET		 141 return 0;
142}
143
9a799d71 144/**
c44ade9e 145 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 146 * @hw: pointer to hardware structure
147 *
c44ade9e 148 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 149 * structure and media type, clears all on chip counters, initializes receive
150 * address registers, multicast table, VLAN filter table, calls routine to set
151 * up link and flow control settings, and leaves transmit and receive units
152 * disabled and uninitialized
153 **/
c44ade9e 154s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 155{
794caeb2
PWJ		 156 s32 status;
157
9a799d71 158 /* Reset the hardware */
794caeb2 159 status = hw->mac.ops.reset_hw(hw);
9a799d71 160
794caeb2
PWJ		 161 if (status == 0) {
162 /* Start the HW */
163 status = hw->mac.ops.start_hw(hw);
164 }
9a799d71 165
794caeb2 166 return status;
9a799d71
AK		 167}
168
169/**
c44ade9e 170 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 171 * @hw: pointer to hardware structure
172 *
173 * Clears all hardware statistics counters by reading them from the hardware
174 * Statistics counters are clear on read.
175 **/
c44ade9e 176s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 177{
178 u16 i = 0;
179
180 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
181 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
182 IXGBE_READ_REG(hw, IXGBE_ERRBC);
183 IXGBE_READ_REG(hw, IXGBE_MSPDC);
184 for (i = 0; i < 8; i++)
185 IXGBE_READ_REG(hw, IXGBE_MPC(i));
186
187 IXGBE_READ_REG(hw, IXGBE_MLFC);
188 IXGBE_READ_REG(hw, IXGBE_MRFC);
189 IXGBE_READ_REG(hw, IXGBE_RLEC);
190 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 191 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 192 if (hw->mac.type >= ixgbe_mac_82599EB) {
193 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
194 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
195 } else {
196 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
197 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
198 }
9a799d71
AK		 199
200 for (i = 0; i < 8; i++) {
201 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 202 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 203 if (hw->mac.type >= ixgbe_mac_82599EB) {
204 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
205 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
206 } else {
207 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
208 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
209 }
9a799d71 210 }
667c7565
ET		 211 if (hw->mac.type >= ixgbe_mac_82599EB)
212 for (i = 0; i < 8; i++)
213 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 214 IXGBE_READ_REG(hw, IXGBE_PRC64);
215 IXGBE_READ_REG(hw, IXGBE_PRC127);
216 IXGBE_READ_REG(hw, IXGBE_PRC255);
217 IXGBE_READ_REG(hw, IXGBE_PRC511);
218 IXGBE_READ_REG(hw, IXGBE_PRC1023);
219 IXGBE_READ_REG(hw, IXGBE_PRC1522);
220 IXGBE_READ_REG(hw, IXGBE_GPRC);
221 IXGBE_READ_REG(hw, IXGBE_BPRC);
222 IXGBE_READ_REG(hw, IXGBE_MPRC);
223 IXGBE_READ_REG(hw, IXGBE_GPTC);
224 IXGBE_READ_REG(hw, IXGBE_GORCL);
225 IXGBE_READ_REG(hw, IXGBE_GORCH);
226 IXGBE_READ_REG(hw, IXGBE_GOTCL);
227 IXGBE_READ_REG(hw, IXGBE_GOTCH);
228 for (i = 0; i < 8; i++)
229 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
230 IXGBE_READ_REG(hw, IXGBE_RUC);
231 IXGBE_READ_REG(hw, IXGBE_RFC);
232 IXGBE_READ_REG(hw, IXGBE_ROC);
233 IXGBE_READ_REG(hw, IXGBE_RJC);
234 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
235 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
236 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
237 IXGBE_READ_REG(hw, IXGBE_TORL);
238 IXGBE_READ_REG(hw, IXGBE_TORH);
239 IXGBE_READ_REG(hw, IXGBE_TPR);
240 IXGBE_READ_REG(hw, IXGBE_TPT);
241 IXGBE_READ_REG(hw, IXGBE_PTC64);
242 IXGBE_READ_REG(hw, IXGBE_PTC127);
243 IXGBE_READ_REG(hw, IXGBE_PTC255);
244 IXGBE_READ_REG(hw, IXGBE_PTC511);
245 IXGBE_READ_REG(hw, IXGBE_PTC1023);
246 IXGBE_READ_REG(hw, IXGBE_PTC1522);
247 IXGBE_READ_REG(hw, IXGBE_MPTC);
248 IXGBE_READ_REG(hw, IXGBE_BPTC);
249 for (i = 0; i < 16; i++) {
250 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 251 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 252 if (hw->mac.type >= ixgbe_mac_82599EB) {
253 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
254 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
255 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
256 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
257 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
258 } else {
259 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
260 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
261 }
9a799d71
AK		 262 }
263
a3aeea0e
ET		 264 if (hw->mac.type == ixgbe_mac_X540) {
265 if (hw->phy.id == 0)
266 hw->phy.ops.identify(hw);
267 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
268 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
269 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
270 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
271 }
272
9a799d71
AK		 273 return 0;
274}
275
276/**
289700db 277 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 278 * @hw: pointer to hardware structure
289700db
DS		 279 * @pba_num: stores the part number string from the EEPROM
280 * @pba_num_size: part number string buffer length
c44ade9e 281 *
289700db 282 * Reads the part number string from the EEPROM.
c44ade9e 283 **/
289700db
DS		 284s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
285 u32 pba_num_size)
c44ade9e
JB		 286{
287 s32 ret_val;
288 u16 data;
289700db
DS		 289 u16 pba_ptr;
290 u16 offset;
291 u16 length;
292
293 if (pba_num == NULL) {
294 hw_dbg(hw, "PBA string buffer was null\n");
295 return IXGBE_ERR_INVALID_ARGUMENT;
296 }
c44ade9e
JB		 297
298 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
299 if (ret_val) {
300 hw_dbg(hw, "NVM Read Error\n");
301 return ret_val;
302 }
c44ade9e 303
289700db 304 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 305 if (ret_val) {
306 hw_dbg(hw, "NVM Read Error\n");
307 return ret_val;
308 }
289700db
DS		 309
310 /*
311 * if data is not ptr guard the PBA must be in legacy format which
312 * means pba_ptr is actually our second data word for the PBA number
313 * and we can decode it into an ascii string
314 */
315 if (data != IXGBE_PBANUM_PTR_GUARD) {
316 hw_dbg(hw, "NVM PBA number is not stored as string\n");
317
318 /* we will need 11 characters to store the PBA */
319 if (pba_num_size < 11) {
320 hw_dbg(hw, "PBA string buffer too small\n");
321 return IXGBE_ERR_NO_SPACE;
322 }
323
324 /* extract hex string from data and pba_ptr */
325 pba_num[0] = (data >> 12) & 0xF;
326 pba_num[1] = (data >> 8) & 0xF;
327 pba_num[2] = (data >> 4) & 0xF;
328 pba_num[3] = data & 0xF;
329 pba_num[4] = (pba_ptr >> 12) & 0xF;
330 pba_num[5] = (pba_ptr >> 8) & 0xF;
331 pba_num[6] = '-';
332 pba_num[7] = 0;
333 pba_num[8] = (pba_ptr >> 4) & 0xF;
334 pba_num[9] = pba_ptr & 0xF;
335
336 /* put a null character on the end of our string */
337 pba_num[10] = '\0';
338
339 /* switch all the data but the '-' to hex char */
340 for (offset = 0; offset < 10; offset++) {
341 if (pba_num[offset] < 0xA)
342 pba_num[offset] += '0';
343 else if (pba_num[offset] < 0x10)
344 pba_num[offset] += 'A' - 0xA;
345 }
346
347 return 0;
348 }
349
350 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
351 if (ret_val) {
352 hw_dbg(hw, "NVM Read Error\n");
353 return ret_val;
354 }
355
356 if (length == 0xFFFF || length == 0) {
357 hw_dbg(hw, "NVM PBA number section invalid length\n");
358 return IXGBE_ERR_PBA_SECTION;
359 }
360
361 /* check if pba_num buffer is big enough */
362 if (pba_num_size < (((u32)length * 2) - 1)) {
363 hw_dbg(hw, "PBA string buffer too small\n");
364 return IXGBE_ERR_NO_SPACE;
365 }
366
367 /* trim pba length from start of string */
368 pba_ptr++;
369 length--;
370
371 for (offset = 0; offset < length; offset++) {
372 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
373 if (ret_val) {
374 hw_dbg(hw, "NVM Read Error\n");
375 return ret_val;
376 }
377 pba_num[offset * 2] = (u8)(data >> 8);
378 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
379 }
380 pba_num[offset * 2] = '\0';
c44ade9e
JB		 381
382 return 0;
383}
384
385/**
386 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 387 * @hw: pointer to hardware structure
388 * @mac_addr: Adapter MAC address
389 *
390 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
391 * A reset of the adapter must be performed prior to calling this function
392 * in order for the MAC address to have been loaded from the EEPROM into RAR0
393 **/
c44ade9e 394s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 395{
396 u32 rar_high;
397 u32 rar_low;
398 u16 i;
399
400 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
401 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
402
403 for (i = 0; i < 4; i++)
404 mac_addr[i] = (u8)(rar_low >> (i*8));
405
406 for (i = 0; i < 2; i++)
407 mac_addr[i+4] = (u8)(rar_high >> (i*8));
408
409 return 0;
410}
411
11afc1b1
PW		 412/**
413 * ixgbe_get_bus_info_generic - Generic set PCI bus info
414 * @hw: pointer to hardware structure
415 *
416 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
417 **/
418s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
419{
420 struct ixgbe_adapter *adapter = hw->back;
421 struct ixgbe_mac_info *mac = &hw->mac;
422 u16 link_status;
423
424 hw->bus.type = ixgbe_bus_type_pci_express;
425
426 /* Get the negotiated link width and speed from PCI config space */
427 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
428 &link_status);
429
430 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
431 case IXGBE_PCI_LINK_WIDTH_1:
432 hw->bus.width = ixgbe_bus_width_pcie_x1;
433 break;
434 case IXGBE_PCI_LINK_WIDTH_2:
435 hw->bus.width = ixgbe_bus_width_pcie_x2;
436 break;
437 case IXGBE_PCI_LINK_WIDTH_4:
438 hw->bus.width = ixgbe_bus_width_pcie_x4;
439 break;
440 case IXGBE_PCI_LINK_WIDTH_8:
441 hw->bus.width = ixgbe_bus_width_pcie_x8;
442 break;
443 default:
444 hw->bus.width = ixgbe_bus_width_unknown;
445 break;
446 }
447
448 switch (link_status & IXGBE_PCI_LINK_SPEED) {
449 case IXGBE_PCI_LINK_SPEED_2500:
450 hw->bus.speed = ixgbe_bus_speed_2500;
451 break;
452 case IXGBE_PCI_LINK_SPEED_5000:
453 hw->bus.speed = ixgbe_bus_speed_5000;
454 break;
455 default:
456 hw->bus.speed = ixgbe_bus_speed_unknown;
457 break;
458 }
459
460 mac->ops.set_lan_id(hw);
461
462 return 0;
463}
464
465/**
466 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
467 * @hw: pointer to the HW structure
468 *
469 * Determines the LAN function id by reading memory-mapped registers
470 * and swaps the port value if requested.
471 **/
472void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
473{
474 struct ixgbe_bus_info *bus = &hw->bus;
475 u32 reg;
476
477 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
478 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
479 bus->lan_id = bus->func;
480
481 /* check for a port swap */
482 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
483 if (reg & IXGBE_FACTPS_LFS)
484 bus->func ^= 0x1;
485}
486
9a799d71 487/**
c44ade9e 488 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 489 * @hw: pointer to hardware structure
490 *
491 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
492 * disables transmit and receive units. The adapter_stopped flag is used by
493 * the shared code and drivers to determine if the adapter is in a stopped
494 * state and should not touch the hardware.
495 **/
c44ade9e 496s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 497{
498 u32 number_of_queues;
499 u32 reg_val;
500 u16 i;
501
502 /*
503 * Set the adapter_stopped flag so other driver functions stop touching
504 * the hardware
505 */
506 hw->adapter_stopped = true;
507
508 /* Disable the receive unit */
509 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
510 reg_val &= ~(IXGBE_RXCTRL_RXEN);
511 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 512 IXGBE_WRITE_FLUSH(hw);
032b4325 513 usleep_range(2000, 4000);
9a799d71
AK		 514
515 /* Clear interrupt mask to stop from interrupts being generated */
516 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
517
518 /* Clear any pending interrupts */
519 IXGBE_READ_REG(hw, IXGBE_EICR);
520
521 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 522 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 523 for (i = 0; i < number_of_queues; i++) {
524 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
525 if (reg_val & IXGBE_TXDCTL_ENABLE) {
526 reg_val &= ~IXGBE_TXDCTL_ENABLE;
527 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
528 }
529 }
530
c44ade9e
JB		 531 /*
532 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
533 * access and verify no pending requests
534 */
a4297dc2 535 ixgbe_disable_pcie_master(hw);
c44ade9e 536
9a799d71
AK		 537 return 0;
538}
539
540/**
c44ade9e 541 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 542 * @hw: pointer to hardware structure
543 * @index: led number to turn on
544 **/
c44ade9e 545s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 546{
547 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
548
549 /* To turn on the LED, set mode to ON. */
550 led_reg &= ~IXGBE_LED_MODE_MASK(index);
551 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
552 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 553 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 554
555 return 0;
556}
557
558/**
c44ade9e 559 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 560 * @hw: pointer to hardware structure
561 * @index: led number to turn off
562 **/
c44ade9e 563s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 564{
565 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
566
567 /* To turn off the LED, set mode to OFF. */
568 led_reg &= ~IXGBE_LED_MODE_MASK(index);
569 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
570 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 571 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 572
573 return 0;
574}
575
9a799d71 576/**
c44ade9e 577 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 578 * @hw: pointer to hardware structure
579 *
580 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
581 * ixgbe_hw struct in order to set up EEPROM access.
582 **/
c44ade9e 583s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 584{
585 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
586 u32 eec;
587 u16 eeprom_size;
588
589 if (eeprom->type == ixgbe_eeprom_uninitialized) {
590 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 591 /* Set default semaphore delay to 10ms which is a well
592 * tested value */
593 eeprom->semaphore_delay = 10;
68c7005d
ET		 594 /* Clear EEPROM page size, it will be initialized as needed */
595 eeprom->word_page_size = 0;
9a799d71
AK		 596
597 /*
598 * Check for EEPROM present first.
599 * If not present leave as none
600 */
601 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
602 if (eec & IXGBE_EEC_PRES) {
603 eeprom->type = ixgbe_eeprom_spi;
604
605 /*
606 * SPI EEPROM is assumed here. This code would need to
607 * change if a future EEPROM is not SPI.
608 */
609 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
610 IXGBE_EEC_SIZE_SHIFT);
611 eeprom->word_size = 1 << (eeprom_size +
612 IXGBE_EEPROM_WORD_SIZE_SHIFT);
613 }
614
615 if (eec & IXGBE_EEC_ADDR_SIZE)
616 eeprom->address_bits = 16;
617 else
618 eeprom->address_bits = 8;
619 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
620 "%d\n", eeprom->type, eeprom->word_size,
621 eeprom->address_bits);
622 }
623
624 return 0;
625}
626
11afc1b1 627/**
68c7005d 628 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 629 * @hw: pointer to hardware structure
68c7005d
ET		 630 * @offset: offset within the EEPROM to write
631 * @words: number of words
632 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 633 *
68c7005d 634 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 635 **/
68c7005d
ET		 636s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
637 u16 words, u16 *data)
11afc1b1 638{
68c7005d
ET		 639 s32 status = 0;
640 u16 i, count;
11afc1b1
PW		 641
642 hw->eeprom.ops.init_params(hw);
643
68c7005d
ET		 644 if (words == 0) {
645 status = IXGBE_ERR_INVALID_ARGUMENT;
646 goto out;
647 }
648
649 if (offset + words > hw->eeprom.word_size) {
11afc1b1
PW		 650 status = IXGBE_ERR_EEPROM;
651 goto out;
652 }
653
68c7005d
ET		 654 /*
655 * The EEPROM page size cannot be queried from the chip. We do lazy
656 * initialization. It is worth to do that when we write large buffer.
657 */
658 if ((hw->eeprom.word_page_size == 0) &&
659 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
660 ixgbe_detect_eeprom_page_size_generic(hw, offset);
661
662 /*
663 * We cannot hold synchronization semaphores for too long
664 * to avoid other entity starvation. However it is more efficient
665 * to read in bursts than synchronizing access for each word.
666 */
667 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
668 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
669 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
670 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
671 count, &data[i]);
672
673 if (status != 0)
674 break;
675 }
676
677out:
678 return status;
679}
680
681/**
682 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
683 * @hw: pointer to hardware structure
684 * @offset: offset within the EEPROM to be written to
685 * @words: number of word(s)
686 * @data: 16 bit word(s) to be written to the EEPROM
687 *
688 * If ixgbe_eeprom_update_checksum is not called after this function, the
689 * EEPROM will most likely contain an invalid checksum.
690 **/
691static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
692 u16 words, u16 *data)
693{
694 s32 status;
695 u16 word;
696 u16 page_size;
697 u16 i;
698 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
699
11afc1b1
PW		 700 /* Prepare the EEPROM for writing */
701 status = ixgbe_acquire_eeprom(hw);
702
703 if (status == 0) {
704 if (ixgbe_ready_eeprom(hw) != 0) {
705 ixgbe_release_eeprom(hw);
706 status = IXGBE_ERR_EEPROM;
707 }
708 }
709
710 if (status == 0) {
68c7005d
ET		 711 for (i = 0; i < words; i++) {
712 ixgbe_standby_eeprom(hw);
11afc1b1 713
68c7005d
ET		 714 /* Send the WRITE ENABLE command (8 bit opcode ) */
715 ixgbe_shift_out_eeprom_bits(hw,
716 IXGBE_EEPROM_WREN_OPCODE_SPI,
717 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 718
68c7005d 719 ixgbe_standby_eeprom(hw);
11afc1b1 720
68c7005d
ET		 721 /*
722 * Some SPI eeproms use the 8th address bit embedded
723 * in the opcode
724 */
725 if ((hw->eeprom.address_bits == 8) &&
726 ((offset + i) >= 128))
727 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
728
729 /* Send the Write command (8-bit opcode + addr) */
730 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
731 IXGBE_EEPROM_OPCODE_BITS);
732 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
733 hw->eeprom.address_bits);
734
735 page_size = hw->eeprom.word_page_size;
736
737 /* Send the data in burst via SPI*/
738 do {
739 word = data[i];
740 word = (word >> 8) | (word << 8);
741 ixgbe_shift_out_eeprom_bits(hw, word, 16);
742
743 if (page_size == 0)
744 break;
745
746 /* do not wrap around page */
747 if (((offset + i) & (page_size - 1)) ==
748 (page_size - 1))
749 break;
750 } while (++i < words);
751
752 ixgbe_standby_eeprom(hw);
753 usleep_range(10000, 20000);
754 }
755 /* Done with writing - release the EEPROM */
756 ixgbe_release_eeprom(hw);
757 }
11afc1b1 758
68c7005d
ET		 759 return status;
760}
761
762/**
763 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
764 * @hw: pointer to hardware structure
765 * @offset: offset within the EEPROM to be written to
766 * @data: 16 bit word to be written to the EEPROM
767 *
768 * If ixgbe_eeprom_update_checksum is not called after this function, the
769 * EEPROM will most likely contain an invalid checksum.
770 **/
771s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
772{
773 s32 status;
11afc1b1 774
68c7005d 775 hw->eeprom.ops.init_params(hw);
11afc1b1 776
68c7005d
ET		 777 if (offset >= hw->eeprom.word_size) {
778 status = IXGBE_ERR_EEPROM;
779 goto out;
11afc1b1
PW		 780 }
781
68c7005d
ET		 782 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
783
11afc1b1
PW		 784out:
785 return status;
786}
787
9a799d71 788/**
68c7005d 789 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 790 * @hw: pointer to hardware structure
791 * @offset: offset within the EEPROM to be read
68c7005d
ET		 792 * @words: number of word(s)
793 * @data: read 16 bit words(s) from EEPROM
c44ade9e 794 *
68c7005d 795 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 796 **/
68c7005d
ET		 797s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
798 u16 words, u16 *data)
c44ade9e 799{
68c7005d
ET		 800 s32 status = 0;
801 u16 i, count;
c44ade9e
JB		 802
803 hw->eeprom.ops.init_params(hw);
804
68c7005d
ET		 805 if (words == 0) {
806 status = IXGBE_ERR_INVALID_ARGUMENT;
807 goto out;
808 }
809
810 if (offset + words > hw->eeprom.word_size) {
c44ade9e
JB		 811 status = IXGBE_ERR_EEPROM;
812 goto out;
813 }
814
68c7005d
ET		 815 /*
816 * We cannot hold synchronization semaphores for too long
817 * to avoid other entity starvation. However it is more efficient
818 * to read in bursts than synchronizing access for each word.
819 */
820 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
821 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
822 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
823
824 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
825 count, &data[i]);
826
827 if (status != 0)
828 break;
829 }
830
831out:
832 return status;
833}
834
835/**
836 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
837 * @hw: pointer to hardware structure
838 * @offset: offset within the EEPROM to be read
839 * @words: number of word(s)
840 * @data: read 16 bit word(s) from EEPROM
841 *
842 * Reads 16 bit word(s) from EEPROM through bit-bang method
843 **/
844static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
845 u16 words, u16 *data)
846{
847 s32 status;
848 u16 word_in;
849 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
850 u16 i;
851
c44ade9e
JB		 852 /* Prepare the EEPROM for reading */
853 status = ixgbe_acquire_eeprom(hw);
854
855 if (status == 0) {
856 if (ixgbe_ready_eeprom(hw) != 0) {
857 ixgbe_release_eeprom(hw);
858 status = IXGBE_ERR_EEPROM;
859 }
860 }
861
862 if (status == 0) {
68c7005d
ET		 863 for (i = 0; i < words; i++) {
864 ixgbe_standby_eeprom(hw);
865 /*
866 * Some SPI eeproms use the 8th address bit embedded
867 * in the opcode
868 */
869 if ((hw->eeprom.address_bits == 8) &&
870 ((offset + i) >= 128))
871 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
872
873 /* Send the READ command (opcode + addr) */
874 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
875 IXGBE_EEPROM_OPCODE_BITS);
876 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
877 hw->eeprom.address_bits);
878
879 /* Read the data. */
880 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
881 data[i] = (word_in >> 8) | (word_in << 8);
882 }
c44ade9e 883
68c7005d
ET		 884 /* End this read operation */
885 ixgbe_release_eeprom(hw);
886 }
c44ade9e 887
68c7005d
ET		 888 return status;
889}
c44ade9e 890
68c7005d
ET		 891/**
892 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
893 * @hw: pointer to hardware structure
894 * @offset: offset within the EEPROM to be read
895 * @data: read 16 bit value from EEPROM
896 *
897 * Reads 16 bit value from EEPROM through bit-bang method
898 **/
899s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
900 u16 *data)
901{
902 s32 status;
c44ade9e 903
68c7005d
ET		 904 hw->eeprom.ops.init_params(hw);
905
906 if (offset >= hw->eeprom.word_size) {
907 status = IXGBE_ERR_EEPROM;
908 goto out;
c44ade9e
JB		 909 }
910
68c7005d
ET		 911 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
912
c44ade9e
JB		 913out:
914 return status;
915}
916
917/**
68c7005d 918 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 919 * @hw: pointer to hardware structure
68c7005d
ET		 920 * @offset: offset of word in the EEPROM to read
921 * @words: number of word(s)
922 * @data: 16 bit word(s) from the EEPROM
9a799d71 923 *
68c7005d 924 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 925 **/
68c7005d
ET		 926s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
927 u16 words, u16 *data)
9a799d71
AK		 928{
929 u32 eerd;
68c7005d
ET		 930 s32 status = 0;
931 u32 i;
9a799d71 932
c44ade9e
JB		 933 hw->eeprom.ops.init_params(hw);
934
68c7005d
ET		 935 if (words == 0) {
936 status = IXGBE_ERR_INVALID_ARGUMENT;
937 goto out;
938 }
939
c44ade9e
JB		 940 if (offset >= hw->eeprom.word_size) {
941 status = IXGBE_ERR_EEPROM;
942 goto out;
943 }
944
68c7005d
ET		 945 for (i = 0; i < words; i++) {
946 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
947 IXGBE_EEPROM_RW_REG_START;
9a799d71 948
68c7005d
ET		 949 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
950 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 951
68c7005d
ET		 952 if (status == 0) {
953 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
954 IXGBE_EEPROM_RW_REG_DATA);
955 } else {
956 hw_dbg(hw, "Eeprom read timed out\n");
957 goto out;
958 }
959 }
960out:
961 return status;
962}
9a799d71 963
68c7005d
ET		 964/**
965 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
966 * @hw: pointer to hardware structure
967 * @offset: offset within the EEPROM to be used as a scratch pad
968 *
969 * Discover EEPROM page size by writing marching data at given offset.
970 * This function is called only when we are writing a new large buffer
971 * at given offset so the data would be overwritten anyway.
972 **/
973static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
974 u16 offset)
975{
976 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
977 s32 status = 0;
978 u16 i;
979
980 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
981 data[i] = i;
982
983 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
984 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
985 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
986 hw->eeprom.word_page_size = 0;
987 if (status != 0)
988 goto out;
989
990 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
991 if (status != 0)
992 goto out;
993
994 /*
995 * When writing in burst more than the actual page size
996 * EEPROM address wraps around current page.
997 */
998 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
999
1000 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1001 hw->eeprom.word_page_size);
c44ade9e 1002out:
9a799d71
AK		 1003 return status;
1004}
1005
eb9c3e3e 1006/**
68c7005d
ET		 1007 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1008 * @hw: pointer to hardware structure
1009 * @offset: offset of word in the EEPROM to read
1010 * @data: word read from the EEPROM
1011 *
1012 * Reads a 16 bit word from the EEPROM using the EERD register.
1013 **/
1014s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1015{
1016 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1017}
1018
1019/**
1020 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1021 * @hw: pointer to hardware structure
1022 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1023 * @words: number of words
1024 * @data: word(s) write to the EEPROM
eb9c3e3e 1025 *
68c7005d 1026 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1027 **/
68c7005d
ET		 1028s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1029 u16 words, u16 *data)
eb9c3e3e
ET		 1030{
1031 u32 eewr;
68c7005d
ET		 1032 s32 status = 0;
1033 u16 i;
eb9c3e3e
ET		 1034
1035 hw->eeprom.ops.init_params(hw);
1036
68c7005d
ET		 1037 if (words == 0) {
1038 status = IXGBE_ERR_INVALID_ARGUMENT;
1039 goto out;
1040 }
1041
eb9c3e3e
ET		 1042 if (offset >= hw->eeprom.word_size) {
1043 status = IXGBE_ERR_EEPROM;
1044 goto out;
1045 }
1046
68c7005d
ET		 1047 for (i = 0; i < words; i++) {
1048 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1049 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1050 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1051
68c7005d
ET		 1052 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1053 if (status != 0) {
1054 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1055 goto out;
1056 }
eb9c3e3e 1057
68c7005d 1058 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1059
68c7005d
ET		 1060 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1061 if (status != 0) {
1062 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1063 goto out;
1064 }
eb9c3e3e
ET		 1065 }
1066
1067out:
1068 return status;
1069}
1070
68c7005d
ET		 1071/**
1072 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1073 * @hw: pointer to hardware structure
1074 * @offset: offset of word in the EEPROM to write
1075 * @data: word write to the EEPROM
1076 *
1077 * Write a 16 bit word to the EEPROM using the EEWR register.
1078 **/
1079s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1080{
1081 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1082}
1083
9a799d71 1084/**
21ce849b 1085 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1086 * @hw: pointer to hardware structure
21ce849b 1087 * @ee_reg: EEPROM flag for polling
9a799d71 1088 *
21ce849b
MC		 1089 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1090 * read or write is done respectively.
9a799d71 1091 **/
eb9c3e3e 1092static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1093{
1094 u32 i;
1095 u32 reg;
1096 s32 status = IXGBE_ERR_EEPROM;
1097
21ce849b
MC		 1098 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1099 if (ee_reg == IXGBE_NVM_POLL_READ)
1100 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1101 else
1102 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1103
1104 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 1105 status = 0;
1106 break;
1107 }
1108 udelay(5);
1109 }
1110 return status;
1111}
1112
c44ade9e
JB		 1113/**
1114 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1115 * @hw: pointer to hardware structure
1116 *
1117 * Prepares EEPROM for access using bit-bang method. This function should
1118 * be called before issuing a command to the EEPROM.
1119 **/
1120static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1121{
1122 s32 status = 0;
dbf893ee 1123 u32 eec;
c44ade9e
JB		 1124 u32 i;
1125
5e655105 1126 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 1127 status = IXGBE_ERR_SWFW_SYNC;
1128
1129 if (status == 0) {
1130 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1131
1132 /* Request EEPROM Access */
1133 eec |= IXGBE_EEC_REQ;
1134 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1135
1136 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1137 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1138 if (eec & IXGBE_EEC_GNT)
1139 break;
1140 udelay(5);
1141 }
1142
1143 /* Release if grant not acquired */
1144 if (!(eec & IXGBE_EEC_GNT)) {
1145 eec &= ~IXGBE_EEC_REQ;
1146 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1147 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1148
5e655105 1149 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 1150 status = IXGBE_ERR_EEPROM;
1151 }
c44ade9e 1152
dbf893ee
ET		 1153 /* Setup EEPROM for Read/Write */
1154 if (status == 0) {
1155 /* Clear CS and SK */
1156 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1157 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1158 IXGBE_WRITE_FLUSH(hw);
1159 udelay(1);
1160 }
c44ade9e
JB		 1161 }
1162 return status;
1163}
1164
9a799d71
AK		 1165/**
1166 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1167 * @hw: pointer to hardware structure
1168 *
1169 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1170 **/
1171static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1172{
1173 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 1174 u32 timeout = 2000;
9a799d71
AK		 1175 u32 i;
1176 u32 swsm;
1177
9a799d71
AK		 1178 /* Get SMBI software semaphore between device drivers first */
1179 for (i = 0; i < timeout; i++) {
1180 /*
1181 * If the SMBI bit is 0 when we read it, then the bit will be
1182 * set and we have the semaphore
1183 */
1184 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1185 if (!(swsm & IXGBE_SWSM_SMBI)) {
1186 status = 0;
1187 break;
1188 }
dbf893ee 1189 udelay(50);
9a799d71
AK		 1190 }
1191
51275d37
ET		 1192 if (i == timeout) {
1193 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1194 "not granted.\n");
1195 /*
1196 * this release is particularly important because our attempts
1197 * above to get the semaphore may have succeeded, and if there
1198 * was a timeout, we should unconditionally clear the semaphore
1199 * bits to free the driver to make progress
1200 */
1201 ixgbe_release_eeprom_semaphore(hw);
1202
1203 udelay(50);
1204 /*
1205 * one last try
1206 * If the SMBI bit is 0 when we read it, then the bit will be
1207 * set and we have the semaphore
1208 */
1209 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1210 if (!(swsm & IXGBE_SWSM_SMBI))
1211 status = 0;
1212 }
1213
9a799d71
AK		 1214 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1215 if (status == 0) {
1216 for (i = 0; i < timeout; i++) {
1217 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1218
1219 /* Set the SW EEPROM semaphore bit to request access */
1220 swsm |= IXGBE_SWSM_SWESMBI;
1221 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1222
1223 /*
1224 * If we set the bit successfully then we got the
1225 * semaphore.
1226 */
1227 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1228 if (swsm & IXGBE_SWSM_SWESMBI)
1229 break;
1230
1231 udelay(50);
1232 }
1233
1234 /*
1235 * Release semaphores and return error if SW EEPROM semaphore
1236 * was not granted because we don't have access to the EEPROM
1237 */
1238 if (i >= timeout) {
dbf893ee 1239 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 1240 "not granted.\n");
9a799d71
AK		 1241 ixgbe_release_eeprom_semaphore(hw);
1242 status = IXGBE_ERR_EEPROM;
1243 }
dbf893ee
ET		 1244 } else {
1245 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1246 "not granted.\n");
9a799d71
AK		 1247 }
1248
1249 return status;
1250}
1251
1252/**
1253 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1254 * @hw: pointer to hardware structure
1255 *
1256 * This function clears hardware semaphore bits.
1257 **/
1258static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1259{
1260 u32 swsm;
1261
1262 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1263
1264 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1265 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1266 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1267 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1268}
1269
c44ade9e
JB		 1270/**
1271 * ixgbe_ready_eeprom - Polls for EEPROM ready
1272 * @hw: pointer to hardware structure
1273 **/
1274static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1275{
1276 s32 status = 0;
1277 u16 i;
1278 u8 spi_stat_reg;
1279
1280 /*
1281 * Read "Status Register" repeatedly until the LSB is cleared. The
1282 * EEPROM will signal that the command has been completed by clearing
1283 * bit 0 of the internal status register. If it's not cleared within
1284 * 5 milliseconds, then error out.
1285 */
1286 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1287 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1288 IXGBE_EEPROM_OPCODE_BITS);
1289 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1290 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1291 break;
1292
1293 udelay(5);
1294 ixgbe_standby_eeprom(hw);
6403eab1 1295 }
c44ade9e
JB		 1296
1297 /*
1298 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1299 * devices (and only 0-5mSec on 5V devices)
1300 */
1301 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1302 hw_dbg(hw, "SPI EEPROM Status error\n");
1303 status = IXGBE_ERR_EEPROM;
1304 }
1305
1306 return status;
1307}
1308
1309/**
1310 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1311 * @hw: pointer to hardware structure
1312 **/
1313static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1314{
1315 u32 eec;
1316
1317 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1318
1319 /* Toggle CS to flush commands */
1320 eec |= IXGBE_EEC_CS;
1321 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1322 IXGBE_WRITE_FLUSH(hw);
1323 udelay(1);
1324 eec &= ~IXGBE_EEC_CS;
1325 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1326 IXGBE_WRITE_FLUSH(hw);
1327 udelay(1);
1328}
1329
1330/**
1331 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1332 * @hw: pointer to hardware structure
1333 * @data: data to send to the EEPROM
1334 * @count: number of bits to shift out
1335 **/
1336static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1337 u16 count)
1338{
1339 u32 eec;
1340 u32 mask;
1341 u32 i;
1342
1343 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1344
1345 /*
1346 * Mask is used to shift "count" bits of "data" out to the EEPROM
1347 * one bit at a time. Determine the starting bit based on count
1348 */
1349 mask = 0x01 << (count - 1);
1350
1351 for (i = 0; i < count; i++) {
1352 /*
1353 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1354 * "1", and then raising and then lowering the clock (the SK
1355 * bit controls the clock input to the EEPROM). A "0" is
1356 * shifted out to the EEPROM by setting "DI" to "0" and then
1357 * raising and then lowering the clock.
1358 */
1359 if (data & mask)
1360 eec |= IXGBE_EEC_DI;
1361 else
1362 eec &= ~IXGBE_EEC_DI;
1363
1364 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1365 IXGBE_WRITE_FLUSH(hw);
1366
1367 udelay(1);
1368
1369 ixgbe_raise_eeprom_clk(hw, &eec);
1370 ixgbe_lower_eeprom_clk(hw, &eec);
1371
1372 /*
1373 * Shift mask to signify next bit of data to shift in to the
1374 * EEPROM
1375 */
1376 mask = mask >> 1;
6403eab1 1377 }
c44ade9e
JB		 1378
1379 /* We leave the "DI" bit set to "0" when we leave this routine. */
1380 eec &= ~IXGBE_EEC_DI;
1381 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1382 IXGBE_WRITE_FLUSH(hw);
1383}
1384
1385/**
1386 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1387 * @hw: pointer to hardware structure
1388 **/
1389static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1390{
1391 u32 eec;
1392 u32 i;
1393 u16 data = 0;
1394
1395 /*
1396 * In order to read a register from the EEPROM, we need to shift
1397 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1398 * the clock input to the EEPROM (setting the SK bit), and then reading
1399 * the value of the "DO" bit. During this "shifting in" process the
1400 * "DI" bit should always be clear.
1401 */
1402 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1403
1404 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1405
1406 for (i = 0; i < count; i++) {
1407 data = data << 1;
1408 ixgbe_raise_eeprom_clk(hw, &eec);
1409
1410 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1411
1412 eec &= ~(IXGBE_EEC_DI);
1413 if (eec & IXGBE_EEC_DO)
1414 data |= 1;
1415
1416 ixgbe_lower_eeprom_clk(hw, &eec);
1417 }
1418
1419 return data;
1420}
1421
1422/**
1423 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1424 * @hw: pointer to hardware structure
1425 * @eec: EEC register's current value
1426 **/
1427static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1428{
1429 /*
1430 * Raise the clock input to the EEPROM
1431 * (setting the SK bit), then delay
1432 */
1433 *eec = *eec | IXGBE_EEC_SK;
1434 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1435 IXGBE_WRITE_FLUSH(hw);
1436 udelay(1);
1437}
1438
1439/**
1440 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1441 * @hw: pointer to hardware structure
1442 * @eecd: EECD's current value
1443 **/
1444static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1445{
1446 /*
1447 * Lower the clock input to the EEPROM (clearing the SK bit), then
1448 * delay
1449 */
1450 *eec = *eec & ~IXGBE_EEC_SK;
1451 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1452 IXGBE_WRITE_FLUSH(hw);
1453 udelay(1);
1454}
1455
1456/**
1457 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1458 * @hw: pointer to hardware structure
1459 **/
1460static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1461{
1462 u32 eec;
1463
1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1465
1466 eec |= IXGBE_EEC_CS; /* Pull CS high */
1467 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1468
1469 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1470 IXGBE_WRITE_FLUSH(hw);
1471
1472 udelay(1);
1473
1474 /* Stop requesting EEPROM access */
1475 eec &= ~IXGBE_EEC_REQ;
1476 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1477
90827996 1478 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1479
032b4325
DS		 1480 /*
1481 * Delay before attempt to obtain semaphore again to allow FW
1482 * access. semaphore_delay is in ms we need us for usleep_range
1483 */
1484 usleep_range(hw->eeprom.semaphore_delay * 1000,
1485 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1486}
1487
9a799d71 1488/**
dbf893ee 1489 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1490 * @hw: pointer to hardware structure
1491 **/
a391f1d5 1492u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1493{
1494 u16 i;
1495 u16 j;
1496 u16 checksum = 0;
1497 u16 length = 0;
1498 u16 pointer = 0;
1499 u16 word = 0;
1500
1501 /* Include 0x0-0x3F in the checksum */
1502 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1503 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1504 hw_dbg(hw, "EEPROM read failed\n");
1505 break;
1506 }
1507 checksum += word;
1508 }
1509
1510 /* Include all data from pointers except for the fw pointer */
1511 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1512 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1513
1514 /* Make sure the pointer seems valid */
1515 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1516 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1517
1518 if (length != 0xFFFF && length != 0) {
1519 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1520 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1521 checksum += word;
1522 }
1523 }
1524 }
1525 }
1526
1527 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1528
1529 return checksum;
1530}
1531
1532/**
c44ade9e 1533 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1534 * @hw: pointer to hardware structure
1535 * @checksum_val: calculated checksum
1536 *
1537 * Performs checksum calculation and validates the EEPROM checksum. If the
1538 * caller does not need checksum_val, the value can be NULL.
1539 **/
c44ade9e
JB		 1540s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1541 u16 *checksum_val)
9a799d71
AK		 1542{
1543 s32 status;
1544 u16 checksum;
1545 u16 read_checksum = 0;
1546
1547 /*
1548 * Read the first word from the EEPROM. If this times out or fails, do
1549 * not continue or we could be in for a very long wait while every
1550 * EEPROM read fails
1551 */
c44ade9e 1552 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1553
1554 if (status == 0) {
a391f1d5 1555 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1556
c44ade9e 1557 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1558
1559 /*
1560 * Verify read checksum from EEPROM is the same as
1561 * calculated checksum
1562 */
1563 if (read_checksum != checksum)
1564 status = IXGBE_ERR_EEPROM_CHECKSUM;
1565
1566 /* If the user cares, return the calculated checksum */
1567 if (checksum_val)
1568 *checksum_val = checksum;
1569 } else {
1570 hw_dbg(hw, "EEPROM read failed\n");
1571 }
1572
1573 return status;
1574}
1575
c44ade9e
JB		 1576/**
1577 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1578 * @hw: pointer to hardware structure
1579 **/
1580s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1581{
1582 s32 status;
1583 u16 checksum;
1584
1585 /*
1586 * Read the first word from the EEPROM. If this times out or fails, do
1587 * not continue or we could be in for a very long wait while every
1588 * EEPROM read fails
1589 */
1590 status = hw->eeprom.ops.read(hw, 0, &checksum);
1591
1592 if (status == 0) {
a391f1d5 1593 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1594 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1595 checksum);
c44ade9e
JB		 1596 } else {
1597 hw_dbg(hw, "EEPROM read failed\n");
1598 }
1599
1600 return status;
1601}
1602
9a799d71
AK		 1603/**
1604 * ixgbe_validate_mac_addr - Validate MAC address
1605 * @mac_addr: pointer to MAC address.
1606 *
1607 * Tests a MAC address to ensure it is a valid Individual Address
1608 **/
1609s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1610{
1611 s32 status = 0;
1612
1613 /* Make sure it is not a multicast address */
1614 if (IXGBE_IS_MULTICAST(mac_addr))
1615 status = IXGBE_ERR_INVALID_MAC_ADDR;
1616 /* Not a broadcast address */
1617 else if (IXGBE_IS_BROADCAST(mac_addr))
1618 status = IXGBE_ERR_INVALID_MAC_ADDR;
1619 /* Reject the zero address */
1620 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1621 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1622 status = IXGBE_ERR_INVALID_MAC_ADDR;
1623
1624 return status;
1625}
1626
1627/**
c44ade9e 1628 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1629 * @hw: pointer to hardware structure
9a799d71 1630 * @index: Receive address register to write
c44ade9e
JB		 1631 * @addr: Address to put into receive address register
1632 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1633 * @enable_addr: set flag that address is active
1634 *
1635 * Puts an ethernet address into a receive address register.
1636 **/
c44ade9e
JB		 1637s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1638 u32 enable_addr)
9a799d71
AK		 1639{
1640 u32 rar_low, rar_high;
c44ade9e
JB		 1641 u32 rar_entries = hw->mac.num_rar_entries;
1642
c700f4e6
ET		 1643 /* Make sure we are using a valid rar index range */
1644 if (index >= rar_entries) {
1645 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1646 return IXGBE_ERR_INVALID_ARGUMENT;
1647 }
1648
c44ade9e
JB		 1649 /* setup VMDq pool selection before this RAR gets enabled */
1650 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1651
c700f4e6
ET		 1652 /*
1653 * HW expects these in little endian so we reverse the byte
1654 * order from network order (big endian) to little endian
1655 */
1656 rar_low = ((u32)addr[0] |
1657 ((u32)addr[1] << 8) |
1658 ((u32)addr[2] << 16) |
1659 ((u32)addr[3] << 24));
1660 /*
1661 * Some parts put the VMDq setting in the extra RAH bits,
1662 * so save everything except the lower 16 bits that hold part
1663 * of the address and the address valid bit.
1664 */
1665 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1666 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1667 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1668
c700f4e6
ET		 1669 if (enable_addr != 0)
1670 rar_high |= IXGBE_RAH_AV;
9a799d71 1671
c700f4e6
ET		 1672 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1673 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1674
1675 return 0;
1676}
1677
1678/**
1679 * ixgbe_clear_rar_generic - Remove Rx address register
1680 * @hw: pointer to hardware structure
1681 * @index: Receive address register to write
1682 *
1683 * Clears an ethernet address from a receive address register.
1684 **/
1685s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1686{
1687 u32 rar_high;
1688 u32 rar_entries = hw->mac.num_rar_entries;
1689
1690 /* Make sure we are using a valid rar index range */
c700f4e6 1691 if (index >= rar_entries) {
c44ade9e 1692 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1693 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1694 }
1695
c700f4e6
ET		 1696 /*
1697 * Some parts put the VMDq setting in the extra RAH bits,
1698 * so save everything except the lower 16 bits that hold part
1699 * of the address and the address valid bit.
1700 */
1701 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1702 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1703
1704 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1705 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1706
c44ade9e
JB		 1707 /* clear VMDq pool/queue selection for this RAR */
1708 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1709
1710 return 0;
1711}
1712
c44ade9e
JB		 1713/**
1714 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1715 * @hw: pointer to hardware structure
1716 *
1717 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1718 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1719 * the receiver is in reset when the routine is called.
1720 **/
c44ade9e 1721s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1722{
1723 u32 i;
2c5645cf 1724 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1725
1726 /*
1727 * If the current mac address is valid, assume it is a software override
1728 * to the permanent address.
1729 * Otherwise, use the permanent address from the eeprom.
1730 */
1731 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1732 IXGBE_ERR_INVALID_MAC_ADDR) {
1733 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1734 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1735
ce7194d8 1736 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1737 } else {
1738 /* Setup the receive address. */
1739 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1740 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1741
c44ade9e 1742 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1743
1744 /* clear VMDq pool/queue selection for RAR 0 */
1745 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1746 }
c44ade9e 1747 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1748
1749 hw->addr_ctrl.rar_used_count = 1;
1750
1751 /* Zero out the other receive addresses. */
c44ade9e 1752 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1753 for (i = 1; i < rar_entries; i++) {
1754 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1755 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1756 }
1757
1758 /* Clear the MTA */
9a799d71
AK		 1759 hw->addr_ctrl.mta_in_use = 0;
1760 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1761
1762 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1763 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1764 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1765
c44ade9e
JB		 1766 if (hw->mac.ops.init_uta_tables)
1767 hw->mac.ops.init_uta_tables(hw);
1768
9a799d71
AK		 1769 return 0;
1770}
1771
1772/**
1773 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1774 * @hw: pointer to hardware structure
1775 * @mc_addr: the multicast address
1776 *
1777 * Extracts the 12 bits, from a multicast address, to determine which
1778 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1779 * incoming rx multicast addresses, to determine the bit-vector to check in
1780 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1781 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1782 * to mc_filter_type.
1783 **/
1784static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1785{
1786 u32 vector = 0;
1787
1788 switch (hw->mac.mc_filter_type) {
b4617240 1789 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1790 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1791 break;
b4617240 1792 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1793 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1794 break;
b4617240 1795 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1796 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1797 break;
b4617240 1798 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1799 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1800 break;
b4617240 1801 default: /* Invalid mc_filter_type */
9a799d71
AK		 1802 hw_dbg(hw, "MC filter type param set incorrectly\n");
1803 break;
1804 }
1805
1806 /* vector can only be 12-bits or boundary will be exceeded */
1807 vector &= 0xFFF;
1808 return vector;
1809}
1810
1811/**
1812 * ixgbe_set_mta - Set bit-vector in multicast table
1813 * @hw: pointer to hardware structure
1814 * @hash_value: Multicast address hash value
1815 *
1816 * Sets the bit-vector in the multicast table.
1817 **/
1818static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1819{
1820 u32 vector;
1821 u32 vector_bit;
1822 u32 vector_reg;
9a799d71
AK		 1823
1824 hw->addr_ctrl.mta_in_use++;
1825
1826 vector = ixgbe_mta_vector(hw, mc_addr);
1827 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1828
1829 /*
1830 * The MTA is a register array of 128 32-bit registers. It is treated
1831 * like an array of 4096 bits. We want to set bit
1832 * BitArray[vector_value]. So we figure out what register the bit is
1833 * in, read it, OR in the new bit, then write back the new value. The
1834 * register is determined by the upper 7 bits of the vector value and
1835 * the bit within that register are determined by the lower 5 bits of
1836 * the value.
1837 */
1838 vector_reg = (vector >> 5) & 0x7F;
1839 vector_bit = vector & 0x1F;
80960ab0 1840 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1841}
1842
9a799d71 1843/**
c44ade9e 1844 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1845 * @hw: pointer to hardware structure
2853eb89 1846 * @netdev: pointer to net device structure
9a799d71
AK		 1847 *
1848 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1849 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1850 * registers for the first multicast addresses, and hashes the rest into the
1851 * multicast table.
1852 **/
2853eb89
JP		 1853s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1854 struct net_device *netdev)
9a799d71 1855{
22bedad3 1856 struct netdev_hw_addr *ha;
9a799d71 1857 u32 i;
9a799d71
AK		 1858
1859 /*
1860 * Set the new number of MC addresses that we are being requested to
1861 * use.
1862 */
2853eb89 1863 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1864 hw->addr_ctrl.mta_in_use = 0;
1865
80960ab0 1866 /* Clear mta_shadow */
9a799d71 1867 hw_dbg(hw, " Clearing MTA\n");
80960ab0 1868 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 1869
80960ab0 1870 /* Update mta shadow */
22bedad3 1871 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1872 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1873 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1874 }
1875
1876 /* Enable mta */
80960ab0
ET		 1877 for (i = 0; i < hw->mac.mcft_size; i++)
1878 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1879 hw->mac.mta_shadow[i]);
1880
9a799d71
AK		 1881 if (hw->addr_ctrl.mta_in_use > 0)
1882 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1883 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1884
c44ade9e 1885 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1886 return 0;
1887}
1888
1889/**
c44ade9e 1890 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1891 * @hw: pointer to hardware structure
1892 *
c44ade9e 1893 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1894 **/
c44ade9e 1895s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1896{
c44ade9e 1897 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1898
c44ade9e
JB		 1899 if (a->mta_in_use > 0)
1900 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1901 hw->mac.mc_filter_type);
9a799d71
AK		 1902
1903 return 0;
1904}
1905
1906/**
c44ade9e 1907 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1908 * @hw: pointer to hardware structure
9a799d71 1909 *
c44ade9e 1910 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1911 **/
c44ade9e 1912s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1913{
c44ade9e 1914 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1915
c44ade9e
JB		 1916 if (a->mta_in_use > 0)
1917 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1918
1919 return 0;
1920}
1921
11afc1b1 1922/**
620fa036 1923 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1924 * @hw: pointer to hardware structure
1925 * @packetbuf_num: packet buffer number (0-7)
1926 *
1927 * Enable flow control according to the current settings.
1928 **/
620fa036 1929s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1930{
1931 s32 ret_val = 0;
620fa036 1932 u32 mflcn_reg, fccfg_reg;
11afc1b1 1933 u32 reg;
70b77628 1934 u32 rx_pba_size;
16b61beb 1935 u32 fcrtl, fcrth;
70b77628
PWJ		 1936
1937#ifdef CONFIG_DCB
1938 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1939 goto out;
1940
1941#endif /* CONFIG_DCB */
620fa036
MC		 1942 /* Negotiate the fc mode to use */
1943 ret_val = ixgbe_fc_autoneg(hw);
0b0c2b31 1944 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
620fa036 1945 goto out;
11afc1b1 1946
620fa036 1947 /* Disable any previous flow control settings */
11afc1b1
PW		 1948 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1949 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1950
1951 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1952 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1953
1954 /*
1955 * The possible values of fc.current_mode are:
1956 * 0: Flow control is completely disabled
1957 * 1: Rx flow control is enabled (we can receive pause frames,
1958 * but not send pause frames).
bb3daa4a
PW		 1959 * 2: Tx flow control is enabled (we can send pause frames but
1960 * we do not support receiving pause frames).
11afc1b1 1961 * 3: Both Rx and Tx flow control (symmetric) are enabled.
8c7bea32 1962#ifdef CONFIG_DCB
bb3daa4a 1963 * 4: Priority Flow Control is enabled.
8c7bea32 1964#endif
11afc1b1
PW		 1965 * other: Invalid.
1966 */
1967 switch (hw->fc.current_mode) {
1968 case ixgbe_fc_none:
620fa036
MC		 1969 /*
1970 * Flow control is disabled by software override or autoneg.
1971 * The code below will actually disable it in the HW.
1972 */
11afc1b1
PW		 1973 break;
1974 case ixgbe_fc_rx_pause:
1975 /*
1976 * Rx Flow control is enabled and Tx Flow control is
1977 * disabled by software override. Since there really
1978 * isn't a way to advertise that we are capable of RX
1979 * Pause ONLY, we will advertise that we support both
1980 * symmetric and asymmetric Rx PAUSE. Later, we will
1981 * disable the adapter's ability to send PAUSE frames.
1982 */
1983 mflcn_reg |= IXGBE_MFLCN_RFCE;
1984 break;
1985 case ixgbe_fc_tx_pause:
1986 /*
1987 * Tx Flow control is enabled, and Rx Flow control is
1988 * disabled by software override.
1989 */
1990 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1991 break;
1992 case ixgbe_fc_full:
1993 /* Flow control (both Rx and Tx) is enabled by SW override. */
1994 mflcn_reg |= IXGBE_MFLCN_RFCE;
1995 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1996 break;
bb3daa4a
PW		 1997#ifdef CONFIG_DCB
1998 case ixgbe_fc_pfc:
1999 goto out;
2000 break;
620fa036 2001#endif /* CONFIG_DCB */
11afc1b1
PW		 2002 default:
2003 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2004 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 2005 goto out;
2006 break;
2007 }
2008
620fa036 2009 /* Set 802.3x based flow control settings. */
2132d381 2010 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2011 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2012 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2013
16b61beb
JF		 2014 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
2015 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
620fa036 2016
16b61beb
JF		 2017 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
2018 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
264857b8 2019
16b61beb
JF		 2020 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2021 fcrth |= IXGBE_FCRTH_FCEN;
2022 if (hw->fc.send_xon)
2023 fcrtl |= IXGBE_FCRTL_XONE;
11afc1b1
PW		 2024 }
2025
16b61beb
JF		 2026 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2027 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2028
11afc1b1 2029 /* Configure pause time (2 TCs per register) */
70b77628 2030 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 2031 if ((packetbuf_num & 1) == 0)
2032 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2033 else
2034 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2035 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2036
2037 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2038
2039out:
2040 return ret_val;
2041}
2042
0ecc061d
PWJ		 2043/**
2044 * ixgbe_fc_autoneg - Configure flow control
2045 * @hw: pointer to hardware structure
2046 *
620fa036
MC		 2047 * Compares our advertised flow control capabilities to those advertised by
2048 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 2049 **/
2050s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2051{
0b0c2b31 2052 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
620fa036 2053 ixgbe_link_speed speed;
620fa036 2054 bool link_up;
0ecc061d 2055
0b0c2b31
ET		 2056 if (hw->fc.disable_fc_autoneg)
2057 goto out;
2058
0ecc061d 2059 /*
620fa036
MC		 2060 * AN should have completed when the cable was plugged in.
2061 * Look for reasons to bail out. Bail out if:
2062 * - FC autoneg is disabled, or if
539e5f02 2063 * - link is not up.
620fa036 2064 *
539e5f02 2065 * Since we're being called from an LSC, link is already known to be up.
620fa036 2066 * So use link_up_wait_to_complete=false.
0ecc061d 2067 */
620fa036 2068 hw->mac.ops.check_link(hw, &speed, &link_up, false);
0b0c2b31
ET		 2069 if (!link_up) {
2070 ret_val = IXGBE_ERR_FLOW_CONTROL;
0ecc061d
PWJ		 2071 goto out;
2072 }
2073
0b0c2b31
ET		 2074 switch (hw->phy.media_type) {
2075 /* Autoneg flow control on fiber adapters */
2076 case ixgbe_media_type_fiber:
2077 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2078 ret_val = ixgbe_fc_autoneg_fiber(hw);
2079 break;
000c486d 2080
0b0c2b31
ET		 2081 /* Autoneg flow control on backplane adapters */
2082 case ixgbe_media_type_backplane:
2083 ret_val = ixgbe_fc_autoneg_backplane(hw);
2084 break;
2085
2086 /* Autoneg flow control on copper adapters */
2087 case ixgbe_media_type_copper:
2088 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2089 ret_val = ixgbe_fc_autoneg_copper(hw);
2090 break;
2091
2092 default:
2093 break;
2094 }
2095
2096out:
2097 if (ret_val == 0) {
2098 hw->fc.fc_was_autonegged = true;
2099 } else {
2100 hw->fc.fc_was_autonegged = false;
2101 hw->fc.current_mode = hw->fc.requested_mode;
539e5f02 2102 }
0b0c2b31
ET		 2103 return ret_val;
2104}
2105
2106/**
2107 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2108 * @hw: pointer to hardware structure
2109 *
2110 * Enable flow control according on 1 gig fiber.
2111 **/
2112static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2113{
2114 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2115 s32 ret_val;
539e5f02
PWJ		 2116
2117 /*
2118 * On multispeed fiber at 1g, bail out if
2119 * - link is up but AN did not complete, or if
2120 * - link is up and AN completed but timed out
2121 */
0b0c2b31
ET		 2122
2123 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de
DS		 2124 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2125 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
0b0c2b31
ET		 2126 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2127 goto out;
539e5f02
PWJ		 2128 }
2129
0b0c2b31
ET		 2130 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2131 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2132
2133 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2134 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2135 IXGBE_PCS1GANA_ASM_PAUSE,
2136 IXGBE_PCS1GANA_SYM_PAUSE,
2137 IXGBE_PCS1GANA_ASM_PAUSE);
2138
2139out:
2140 return ret_val;
2141}
2142
2143/**
2144 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2145 * @hw: pointer to hardware structure
2146 *
2147 * Enable flow control according to IEEE clause 37.
2148 **/
2149static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2150{
2151 u32 links2, anlp1_reg, autoc_reg, links;
2152 s32 ret_val;
2153
9bbe3a57 2154 /*
0b0c2b31
ET		 2155 * On backplane, bail out if
2156 * - backplane autoneg was not completed, or if
2157 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2158 */
0b0c2b31
ET		 2159 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2160 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
9bbe3a57
PW		 2161 hw->fc.fc_was_autonegged = false;
2162 hw->fc.current_mode = hw->fc.requested_mode;
0b0c2b31 2163 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57
PW		 2164 goto out;
2165 }
2166
0b0c2b31
ET		 2167 if (hw->mac.type == ixgbe_mac_82599EB) {
2168 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2169 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2170 hw->fc.fc_was_autonegged = false;
2171 hw->fc.current_mode = hw->fc.requested_mode;
2172 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2173 goto out;
2174 }
2175 }
0ecc061d 2176 /*
0b0c2b31 2177 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2178 * local flow control settings accordingly
2179 */
0b0c2b31
ET		 2180 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2181 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2182
0b0c2b31
ET		 2183 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2184 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2185 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2186
2187out:
2188 return ret_val;
2189}
2190
2191/**
2192 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2193 * @hw: pointer to hardware structure
2194 *
2195 * Enable flow control according to IEEE clause 37.
2196 **/
2197static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2198{
2199 u16 technology_ability_reg = 0;
2200 u16 lp_technology_ability_reg = 0;
2201
2202 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2203 MDIO_MMD_AN,
2204 &technology_ability_reg);
2205 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2206 MDIO_MMD_AN,
2207 &lp_technology_ability_reg);
2208
2209 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2210 (u32)lp_technology_ability_reg,
2211 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2212 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2213}
2214
2215/**
2216 * ixgbe_negotiate_fc - Negotiate flow control
2217 * @hw: pointer to hardware structure
2218 * @adv_reg: flow control advertised settings
2219 * @lp_reg: link partner's flow control settings
2220 * @adv_sym: symmetric pause bit in advertisement
2221 * @adv_asm: asymmetric pause bit in advertisement
2222 * @lp_sym: symmetric pause bit in link partner advertisement
2223 * @lp_asm: asymmetric pause bit in link partner advertisement
2224 *
2225 * Find the intersection between advertised settings and link partner's
2226 * advertised settings
2227 **/
2228static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2229 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2230{
2231 if ((!(adv_reg)) || (!(lp_reg)))
2232 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2233
2234 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
0ecc061d 2235 /*
0b0c2b31
ET		 2236 * Now we need to check if the user selected Rx ONLY
2237 * of pause frames. In this case, we had to advertise
2238 * FULL flow control because we could not advertise RX
2239 * ONLY. Hence, we must now check to see if we need to
2240 * turn OFF the TRANSMISSION of PAUSE frames.
0ecc061d 2241 */
0b0c2b31
ET		 2242 if (hw->fc.requested_mode == ixgbe_fc_full) {
2243 hw->fc.current_mode = ixgbe_fc_full;
2244 hw_dbg(hw, "Flow Control = FULL.\n");
539e5f02 2245 } else {
0b0c2b31
ET		 2246 hw->fc.current_mode = ixgbe_fc_rx_pause;
2247 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
0ecc061d 2248 }
0b0c2b31
ET		 2249 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2250 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2251 hw->fc.current_mode = ixgbe_fc_tx_pause;
2252 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2253 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2254 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2255 hw->fc.current_mode = ixgbe_fc_rx_pause;
2256 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2257 } else {
2258 hw->fc.current_mode = ixgbe_fc_none;
2259 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 2260 }
0b0c2b31 2261 return 0;
0ecc061d
PWJ		 2262}
2263
11afc1b1 2264/**
620fa036 2265 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 2266 * @hw: pointer to hardware structure
2267 *
620fa036 2268 * Called at init time to set up flow control.
11afc1b1 2269 **/
7b25cdba 2270static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 2271{
2272 s32 ret_val = 0;
0b0c2b31
ET		 2273 u32 reg = 0, reg_bp = 0;
2274 u16 reg_cu = 0;
11afc1b1 2275
bb3daa4a
PW		 2276#ifdef CONFIG_DCB
2277 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
2278 hw->fc.current_mode = hw->fc.requested_mode;
2279 goto out;
2280 }
2281
0b0c2b31 2282#endif /* CONFIG_DCB */
11afc1b1
PW		 2283 /* Validate the packetbuf configuration */
2284 if (packetbuf_num < 0 || packetbuf_num > 7) {
2285 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
2286 "is 0-7\n", packetbuf_num);
2287 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2288 goto out;
2289 }
2290
2291 /*
2292 * Validate the water mark configuration. Zero water marks are invalid
2293 * because it causes the controller to just blast out fc packets.
2294 */
2295 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 2296 hw_dbg(hw, "Invalid water mark configuration\n");
2297 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2298 goto out;
11afc1b1
PW		 2299 }
2300
2301 /*
2302 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 2303 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 2304 */
2305 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2306 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
2307 "IEEE mode\n");
2308 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2309 goto out;
2310 }
2311
2312 /*
2313 * 10gig parts do not have a word in the EEPROM to determine the
2314 * default flow control setting, so we explicitly set it to full.
2315 */
2316 if (hw->fc.requested_mode == ixgbe_fc_default)
2317 hw->fc.requested_mode = ixgbe_fc_full;
2318
2319 /*
0b0c2b31
ET		 2320 * Set up the 1G and 10G flow control advertisement registers so the
2321 * HW will be able to do fc autoneg once the cable is plugged in. If
2322 * we link at 10G, the 1G advertisement is harmless and vice versa.
11afc1b1 2323 */
0b0c2b31
ET		 2324
2325 switch (hw->phy.media_type) {
2326 case ixgbe_media_type_fiber:
2327 case ixgbe_media_type_backplane:
2328 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2329 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2330 break;
2331
2332 case ixgbe_media_type_copper:
2333 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2334 MDIO_MMD_AN, &reg_cu);
2335 break;
2336
2337 default:
2338 ;
2339 }
11afc1b1 2340
620fa036
MC		 2341 /*
2342 * The possible values of fc.requested_mode are:
2343 * 0: Flow control is completely disabled
2344 * 1: Rx flow control is enabled (we can receive pause frames,
2345 * but not send pause frames).
2346 * 2: Tx flow control is enabled (we can send pause frames but
2347 * we do not support receiving pause frames).
2348 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2349#ifdef CONFIG_DCB
2350 * 4: Priority Flow Control is enabled.
2351#endif
2352 * other: Invalid.
2353 */
2354 switch (hw->fc.requested_mode) {
2355 case ixgbe_fc_none:
2356 /* Flow control completely disabled by software override. */
2357 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2358 if (hw->phy.media_type == ixgbe_media_type_backplane)
2359 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2360 IXGBE_AUTOC_ASM_PAUSE);
2361 else if (hw->phy.media_type == ixgbe_media_type_copper)
2362 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2363 break;
2364 case ixgbe_fc_rx_pause:
2365 /*
2366 * Rx Flow control is enabled and Tx Flow control is
2367 * disabled by software override. Since there really
2368 * isn't a way to advertise that we are capable of RX
2369 * Pause ONLY, we will advertise that we support both
2370 * symmetric and asymmetric Rx PAUSE. Later, we will
2371 * disable the adapter's ability to send PAUSE frames.
2372 */
2373 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2374 if (hw->phy.media_type == ixgbe_media_type_backplane)
2375 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2376 IXGBE_AUTOC_ASM_PAUSE);
2377 else if (hw->phy.media_type == ixgbe_media_type_copper)
2378 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2379 break;
2380 case ixgbe_fc_tx_pause:
2381 /*
2382 * Tx Flow control is enabled, and Rx Flow control is
2383 * disabled by software override.
2384 */
2385 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2386 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
0b0c2b31
ET		 2387 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2388 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2389 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2390 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2391 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2392 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2393 }
620fa036
MC		 2394 break;
2395 case ixgbe_fc_full:
2396 /* Flow control (both Rx and Tx) is enabled by SW override. */
2397 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
0b0c2b31
ET		 2398 if (hw->phy.media_type == ixgbe_media_type_backplane)
2399 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2400 IXGBE_AUTOC_ASM_PAUSE);
2401 else if (hw->phy.media_type == ixgbe_media_type_copper)
2402 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
620fa036
MC		 2403 break;
2404#ifdef CONFIG_DCB
2405 case ixgbe_fc_pfc:
11afc1b1 2406 goto out;
620fa036
MC		 2407 break;
2408#endif /* CONFIG_DCB */
2409 default:
2410 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2411 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 2412 goto out;
2413 break;
2414 }
2415
0b0c2b31
ET		 2416 if (hw->mac.type != ixgbe_mac_X540) {
2417 /*
2418 * Enable auto-negotiation between the MAC & PHY;
2419 * the MAC will advertise clause 37 flow control.
2420 */
2421 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2422 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
620fa036 2423
0b0c2b31
ET		 2424 /* Disable AN timeout */
2425 if (hw->fc.strict_ieee)
2426 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
11afc1b1 2427
0b0c2b31
ET		 2428 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2429 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2430 }
539e5f02
PWJ		 2431
2432 /*
0b0c2b31
ET		 2433 * AUTOC restart handles negotiation of 1G and 10G on backplane
2434 * and copper. There is no need to set the PCS1GCTL register.
2435 *
539e5f02 2436 */
0b0c2b31
ET		 2437 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2438 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2439 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2440 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2441 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
2442 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
2443 MDIO_MMD_AN, reg_cu);
539e5f02 2444 }
539e5f02 2445
0b0c2b31 2446 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
11afc1b1
PW		 2447out:
2448 return ret_val;
2449}
2450
9a799d71
AK		 2451/**
2452 * ixgbe_disable_pcie_master - Disable PCI-express master access
2453 * @hw: pointer to hardware structure
2454 *
2455 * Disables PCI-Express master access and verifies there are no pending
2456 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2457 * bit hasn't caused the master requests to be disabled, else 0
2458 * is returned signifying master requests disabled.
2459 **/
2460s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2461{
a4297dc2 2462 struct ixgbe_adapter *adapter = hw->back;
c44ade9e
JB		 2463 u32 i;
2464 u32 reg_val;
2465 u32 number_of_queues;
a4297dc2
ET		 2466 s32 status = 0;
2467 u16 dev_status = 0;
2468
2469 /* Just jump out if bus mastering is already disabled */
2470 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2471 goto out;
9a799d71 2472
c44ade9e
JB		 2473 /* Disable the receive unit by stopping each queue */
2474 number_of_queues = hw->mac.max_rx_queues;
2475 for (i = 0; i < number_of_queues; i++) {
2476 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2477 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2478 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2479 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2480 }
2481 }
2482
2483 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2484 reg_val |= IXGBE_CTRL_GIO_DIS;
2485 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2486
2487 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2
ET		 2488 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2489 goto check_device_status;
2490 udelay(100);
2491 }
2492
2493 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2494 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2495
2496 /*
2497 * Before proceeding, make sure that the PCIe block does not have
2498 * transactions pending.
2499 */
2500check_device_status:
2501 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2502 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2503 &dev_status);
2504 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
9a799d71 2505 break;
9a799d71
AK		 2506 udelay(100);
2507 }
2508
a4297dc2
ET		 2509 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2510 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2511 else
2512 goto out;
2513
2514 /*
2515 * Two consecutive resets are required via CTRL.RST per datasheet
2516 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2517 * of this need. The first reset prevents new master requests from
2518 * being issued by our device. We then must wait 1usec for any
2519 * remaining completions from the PCIe bus to trickle in, and then reset
2520 * again to clear out any effects they may have had on our device.
2521 */
2522 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2523
2524out:
9a799d71
AK		 2525 return status;
2526}
2527
2528
2529/**
c44ade9e 2530 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2531 * @hw: pointer to hardware structure
c44ade9e 2532 * @mask: Mask to specify which semaphore to acquire
9a799d71 2533 *
da74cd4a 2534 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2535 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2536 **/
2537s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2538{
2539 u32 gssr;
2540 u32 swmask = mask;
2541 u32 fwmask = mask << 5;
2542 s32 timeout = 200;
2543
2544 while (timeout) {
dbf893ee
ET		 2545 /*
2546 * SW EEPROM semaphore bit is used for access to all
2547 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2548 */
9a799d71 2549 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2550 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2551
2552 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2553 if (!(gssr & (fwmask | swmask)))
2554 break;
2555
2556 /*
2557 * Firmware currently using resource (fwmask) or other software
2558 * thread currently using resource (swmask)
2559 */
2560 ixgbe_release_eeprom_semaphore(hw);
032b4325 2561 usleep_range(5000, 10000);
9a799d71
AK		 2562 timeout--;
2563 }
2564
2565 if (!timeout) {
dbf893ee 2566 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2567 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2568 }
2569
2570 gssr |= swmask;
2571 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2572
2573 ixgbe_release_eeprom_semaphore(hw);
2574 return 0;
2575}
2576
2577/**
2578 * ixgbe_release_swfw_sync - Release SWFW semaphore
2579 * @hw: pointer to hardware structure
c44ade9e 2580 * @mask: Mask to specify which semaphore to release
9a799d71 2581 *
da74cd4a 2582 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2583 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2584 **/
2585void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2586{
2587 u32 gssr;
2588 u32 swmask = mask;
2589
2590 ixgbe_get_eeprom_semaphore(hw);
2591
2592 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2593 gssr &= ~swmask;
2594 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2595
2596 ixgbe_release_eeprom_semaphore(hw);
2597}
2598
11afc1b1
PW		 2599/**
2600 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2601 * @hw: pointer to hardware structure
2602 * @regval: register value to write to RXCTRL
2603 *
2604 * Enables the Rx DMA unit
2605 **/
2606s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2607{
2608 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2609
2610 return 0;
2611}
87c12017
PW		 2612
2613/**
2614 * ixgbe_blink_led_start_generic - Blink LED based on index.
2615 * @hw: pointer to hardware structure
2616 * @index: led number to blink
2617 **/
2618s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2619{
2620 ixgbe_link_speed speed = 0;
2621 bool link_up = 0;
2622 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2623 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2624
2625 /*
2626 * Link must be up to auto-blink the LEDs;
2627 * Force it if link is down.
2628 */
2629 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2630
2631 if (!link_up) {
50ac58ba 2632 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2633 autoc_reg |= IXGBE_AUTOC_FLU;
2634 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
945a5151 2635 IXGBE_WRITE_FLUSH(hw);
032b4325 2636 usleep_range(10000, 20000);
87c12017
PW		 2637 }
2638
2639 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2640 led_reg |= IXGBE_LED_BLINK(index);
2641 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2642 IXGBE_WRITE_FLUSH(hw);
2643
2644 return 0;
2645}
2646
2647/**
2648 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2649 * @hw: pointer to hardware structure
2650 * @index: led number to stop blinking
2651 **/
2652s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2653{
2654 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2655 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2656
2657 autoc_reg &= ~IXGBE_AUTOC_FLU;
2658 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2659 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2660
2661 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2662 led_reg &= ~IXGBE_LED_BLINK(index);
2663 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2664 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2665 IXGBE_WRITE_FLUSH(hw);
2666
2667 return 0;
2668}
21ce849b
MC		 2669
2670/**
2671 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2672 * @hw: pointer to hardware structure
2673 * @san_mac_offset: SAN MAC address offset
2674 *
2675 * This function will read the EEPROM location for the SAN MAC address
2676 * pointer, and returns the value at that location. This is used in both
2677 * get and set mac_addr routines.
2678 **/
2679static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2680 u16 *san_mac_offset)
2681{
2682 /*
2683 * First read the EEPROM pointer to see if the MAC addresses are
2684 * available.
2685 */
2686 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2687
2688 return 0;
2689}
2690
2691/**
2692 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2693 * @hw: pointer to hardware structure
2694 * @san_mac_addr: SAN MAC address
2695 *
2696 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2697 * per-port, so set_lan_id() must be called before reading the addresses.
2698 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2699 * upon for non-SFP connections, so we must call it here.
2700 **/
2701s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2702{
2703 u16 san_mac_data, san_mac_offset;
2704 u8 i;
2705
2706 /*
2707 * First read the EEPROM pointer to see if the MAC addresses are
2708 * available. If they're not, no point in calling set_lan_id() here.
2709 */
2710 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2711
2712 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2713 /*
2714 * No addresses available in this EEPROM. It's not an
2715 * error though, so just wipe the local address and return.
2716 */
2717 for (i = 0; i < 6; i++)
2718 san_mac_addr[i] = 0xFF;
2719
2720 goto san_mac_addr_out;
2721 }
2722
2723 /* make sure we know which port we need to program */
2724 hw->mac.ops.set_lan_id(hw);
2725 /* apply the port offset to the address offset */
2726 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2727 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2728 for (i = 0; i < 3; i++) {
2729 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2730 san_mac_addr[i * 2] = (u8)(san_mac_data);
2731 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2732 san_mac_offset++;
2733 }
2734
2735san_mac_addr_out:
2736 return 0;
2737}
2738
2739/**
2740 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2741 * @hw: pointer to hardware structure
2742 *
2743 * Read PCIe configuration space, and get the MSI-X vector count from
2744 * the capabilities table.
2745 **/
2746u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2747{
2748 struct ixgbe_adapter *adapter = hw->back;
2749 u16 msix_count;
2750 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2751 &msix_count);
2752 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2753
2754 /* MSI-X count is zero-based in HW, so increment to give proper value */
2755 msix_count++;
2756
2757 return msix_count;
2758}
2759
2760/**
2761 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2762 * @hw: pointer to hardware struct
2763 * @rar: receive address register index to disassociate
2764 * @vmdq: VMDq pool index to remove from the rar
2765 **/
2766s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2767{
2768 u32 mpsar_lo, mpsar_hi;
2769 u32 rar_entries = hw->mac.num_rar_entries;
2770
c700f4e6
ET		 2771 /* Make sure we are using a valid rar index range */
2772 if (rar >= rar_entries) {
2773 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2774 return IXGBE_ERR_INVALID_ARGUMENT;
2775 }
21ce849b 2776
c700f4e6
ET		 2777 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2778 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2779
c700f4e6
ET		 2780 if (!mpsar_lo && !mpsar_hi)
2781 goto done;
21ce849b 2782
c700f4e6
ET		 2783 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2784 if (mpsar_lo) {
2785 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2786 mpsar_lo = 0;
2787 }
2788 if (mpsar_hi) {
2789 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2790 mpsar_hi = 0;
2791 }
2792 } else if (vmdq < 32) {
2793 mpsar_lo &= ~(1 << vmdq);
2794 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2795 } else {
c700f4e6
ET		 2796 mpsar_hi &= ~(1 << (vmdq - 32));
2797 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2798 }
2799
c700f4e6
ET		 2800 /* was that the last pool using this rar? */
2801 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2802 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2803done:
2804 return 0;
2805}
2806
2807/**
2808 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2809 * @hw: pointer to hardware struct
2810 * @rar: receive address register index to associate with a VMDq index
2811 * @vmdq: VMDq pool index
2812 **/
2813s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2814{
2815 u32 mpsar;
2816 u32 rar_entries = hw->mac.num_rar_entries;
2817
c700f4e6
ET		 2818 /* Make sure we are using a valid rar index range */
2819 if (rar >= rar_entries) {
21ce849b 2820 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2821 return IXGBE_ERR_INVALID_ARGUMENT;
2822 }
2823
2824 if (vmdq < 32) {
2825 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2826 mpsar |= 1 << vmdq;
2827 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2828 } else {
2829 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2830 mpsar |= 1 << (vmdq - 32);
2831 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2832 }
2833 return 0;
2834}
2835
2836/**
2837 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2838 * @hw: pointer to hardware structure
2839 **/
2840s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2841{
2842 int i;
2843
21ce849b
MC		 2844 for (i = 0; i < 128; i++)
2845 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2846
2847 return 0;
2848}
2849
2850/**
2851 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2852 * @hw: pointer to hardware structure
2853 * @vlan: VLAN id to write to VLAN filter
2854 *
2855 * return the VLVF index where this VLAN id should be placed
2856 *
2857 **/
5d5b7c39 2858static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2859{
2860 u32 bits = 0;
2861 u32 first_empty_slot = 0;
2862 s32 regindex;
2863
2864 /* short cut the special case */
2865 if (vlan == 0)
2866 return 0;
2867
2868 /*
2869 * Search for the vlan id in the VLVF entries. Save off the first empty
2870 * slot found along the way
2871 */
2872 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2873 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2874 if (!bits && !(first_empty_slot))
2875 first_empty_slot = regindex;
2876 else if ((bits & 0x0FFF) == vlan)
2877 break;
2878 }
2879
2880 /*
2881 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2882 * in the VLVF. Else use the first empty VLVF register for this
2883 * vlan id.
2884 */
2885 if (regindex >= IXGBE_VLVF_ENTRIES) {
2886 if (first_empty_slot)
2887 regindex = first_empty_slot;
2888 else {
2889 hw_dbg(hw, "No space in VLVF.\n");
2890 regindex = IXGBE_ERR_NO_SPACE;
2891 }
2892 }
2893
2894 return regindex;
2895}
2896
2897/**
2898 * ixgbe_set_vfta_generic - Set VLAN filter table
2899 * @hw: pointer to hardware structure
2900 * @vlan: VLAN id to write to VLAN filter
2901 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2902 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2903 *
2904 * Turn on/off specified VLAN in the VLAN filter table.
2905 **/
2906s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2907 bool vlan_on)
2908{
2909 s32 regindex;
2910 u32 bitindex;
2911 u32 vfta;
2912 u32 bits;
2913 u32 vt;
2914 u32 targetbit;
2915 bool vfta_changed = false;
2916
2917 if (vlan > 4095)
2918 return IXGBE_ERR_PARAM;
2919
2920 /*
2921 * this is a 2 part operation - first the VFTA, then the
2922 * VLVF and VLVFB if VT Mode is set
2923 * We don't write the VFTA until we know the VLVF part succeeded.
2924 */
2925
2926 /* Part 1
2927 * The VFTA is a bitstring made up of 128 32-bit registers
2928 * that enable the particular VLAN id, much like the MTA:
2929 * bits[11-5]: which register
2930 * bits[4-0]: which bit in the register
2931 */
2932 regindex = (vlan >> 5) & 0x7F;
2933 bitindex = vlan & 0x1F;
2934 targetbit = (1 << bitindex);
2935 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2936
2937 if (vlan_on) {
2938 if (!(vfta & targetbit)) {
2939 vfta |= targetbit;
2940 vfta_changed = true;
2941 }
2942 } else {
2943 if ((vfta & targetbit)) {
2944 vfta &= ~targetbit;
2945 vfta_changed = true;
2946 }
2947 }
2948
2949 /* Part 2
2950 * If VT Mode is set
2951 * Either vlan_on
2952 * make sure the vlan is in VLVF
2953 * set the vind bit in the matching VLVFB
2954 * Or !vlan_on
2955 * clear the pool bit and possibly the vind
2956 */
2957 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2958 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2959 s32 vlvf_index;
2960
2961 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2962 if (vlvf_index < 0)
2963 return vlvf_index;
2964
2965 if (vlan_on) {
2966 /* set the pool bit */
2967 if (vind < 32) {
2968 bits = IXGBE_READ_REG(hw,
2969 IXGBE_VLVFB(vlvf_index*2));
2970 bits |= (1 << vind);
2971 IXGBE_WRITE_REG(hw,
2972 IXGBE_VLVFB(vlvf_index*2),
2973 bits);
2974 } else {
2975 bits = IXGBE_READ_REG(hw,
2976 IXGBE_VLVFB((vlvf_index*2)+1));
2977 bits |= (1 << (vind-32));
2978 IXGBE_WRITE_REG(hw,
2979 IXGBE_VLVFB((vlvf_index*2)+1),
2980 bits);
2981 }
2982 } else {
2983 /* clear the pool bit */
2984 if (vind < 32) {
2985 bits = IXGBE_READ_REG(hw,
2986 IXGBE_VLVFB(vlvf_index*2));
2987 bits &= ~(1 << vind);
2988 IXGBE_WRITE_REG(hw,
2989 IXGBE_VLVFB(vlvf_index*2),
2990 bits);
2991 bits |= IXGBE_READ_REG(hw,
2992 IXGBE_VLVFB((vlvf_index*2)+1));
2993 } else {
2994 bits = IXGBE_READ_REG(hw,
2995 IXGBE_VLVFB((vlvf_index*2)+1));
2996 bits &= ~(1 << (vind-32));
2997 IXGBE_WRITE_REG(hw,
2998 IXGBE_VLVFB((vlvf_index*2)+1),
2999 bits);
3000 bits |= IXGBE_READ_REG(hw,
3001 IXGBE_VLVFB(vlvf_index*2));
3002 }
3003 }
3004
3005 /*
3006 * If there are still bits set in the VLVFB registers
3007 * for the VLAN ID indicated we need to see if the
3008 * caller is requesting that we clear the VFTA entry bit.
3009 * If the caller has requested that we clear the VFTA
3010 * entry bit but there are still pools/VFs using this VLAN
3011 * ID entry then ignore the request. We're not worried
3012 * about the case where we're turning the VFTA VLAN ID
3013 * entry bit on, only when requested to turn it off as
3014 * there may be multiple pools and/or VFs using the
3015 * VLAN ID entry. In that case we cannot clear the
3016 * VFTA bit until all pools/VFs using that VLAN ID have also
3017 * been cleared. This will be indicated by "bits" being
3018 * zero.
3019 */
3020 if (bits) {
3021 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3022 (IXGBE_VLVF_VIEN | vlan));
3023 if (!vlan_on) {
3024 /* someone wants to clear the vfta entry
3025 * but some pools/VFs are still using it.
3026 * Ignore it. */
3027 vfta_changed = false;
3028 }
3029 }
3030 else
3031 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3032 }
3033
3034 if (vfta_changed)
3035 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3036
3037 return 0;
3038}
3039
3040/**
3041 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3042 * @hw: pointer to hardware structure
3043 *
3044 * Clears the VLAN filer table, and the VMDq index associated with the filter
3045 **/
3046s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3047{
3048 u32 offset;
3049
3050 for (offset = 0; offset < hw->mac.vft_size; offset++)
3051 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3052
3053 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3054 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3055 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3056 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3057 }
3058
3059 return 0;
3060}
3061
3062/**
3063 * ixgbe_check_mac_link_generic - Determine link and speed status
3064 * @hw: pointer to hardware structure
3065 * @speed: pointer to link speed
3066 * @link_up: true when link is up
3067 * @link_up_wait_to_complete: bool used to wait for link up or not
3068 *
3069 * Reads the links register to determine if link is up and the current speed
3070 **/
3071s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3072 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3073{
48de36c5 3074 u32 links_reg, links_orig;
21ce849b
MC		 3075 u32 i;
3076
48de36c5
ET		 3077 /* clear the old state */
3078 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3079
21ce849b 3080 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3081
3082 if (links_orig != links_reg) {
3083 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3084 links_orig, links_reg);
3085 }
3086
21ce849b
MC		 3087 if (link_up_wait_to_complete) {
3088 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3089 if (links_reg & IXGBE_LINKS_UP) {
3090 *link_up = true;
3091 break;
3092 } else {
3093 *link_up = false;
3094 }
3095 msleep(100);
3096 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3097 }
3098 } else {
3099 if (links_reg & IXGBE_LINKS_UP)
3100 *link_up = true;
3101 else
3102 *link_up = false;
3103 }
3104
3105 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3106 IXGBE_LINKS_SPEED_10G_82599)
3107 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3108 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 3109 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 3110 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 3111 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3112 IXGBE_LINKS_SPEED_100_82599)
21ce849b 3113 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 3114 else
3115 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b
MC		 3116
3117 /* if link is down, zero out the current_mode */
3118 if (*link_up == false) {
3119 hw->fc.current_mode = ixgbe_fc_none;
3120 hw->fc.fc_was_autonegged = false;
3121 }
3122
3123 return 0;
3124}
a391f1d5
DS		 3125
3126/**
3127 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
3128 * the EEPROM
3129 * @hw: pointer to hardware structure
3130 * @wwnn_prefix: the alternative WWNN prefix
3131 * @wwpn_prefix: the alternative WWPN prefix
3132 *
3133 * This function will read the EEPROM from the alternative SAN MAC address
3134 * block to check the support for the alternative WWNN/WWPN prefix support.
3135 **/
3136s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3137 u16 *wwpn_prefix)
3138{
3139 u16 offset, caps;
3140 u16 alt_san_mac_blk_offset;
3141
3142 /* clear output first */
3143 *wwnn_prefix = 0xFFFF;
3144 *wwpn_prefix = 0xFFFF;
3145
3146 /* check if alternative SAN MAC is supported */
3147 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3148 &alt_san_mac_blk_offset);
3149
3150 if ((alt_san_mac_blk_offset == 0) ||
3151 (alt_san_mac_blk_offset == 0xFFFF))
3152 goto wwn_prefix_out;
3153
3154 /* check capability in alternative san mac address block */
3155 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3156 hw->eeprom.ops.read(hw, offset, &caps);
3157 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3158 goto wwn_prefix_out;
3159
3160 /* get the corresponding prefix for WWNN/WWPN */
3161 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3162 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3163
3164 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3165 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3166
3167wwn_prefix_out:
3168 return 0;
3169}
a985b6c3 3170
0b0c2b31
ET		 3171/**
3172 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
3173 * control
3174 * @hw: pointer to hardware structure
3175 *
3176 * There are several phys that do not support autoneg flow control. This
3177 * function check the device id to see if the associated phy supports
3178 * autoneg flow control.
3179 **/
3180static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
3181{
3182
3183 switch (hw->device_id) {
3184 case IXGBE_DEV_ID_X540T:
3185 return 0;
3186 case IXGBE_DEV_ID_82599_T3_LOM:
3187 return 0;
3188 default:
3189 return IXGBE_ERR_FC_NOT_SUPPORTED;
3190 }
3191}
3192
a985b6c3
GR		 3193/**
3194 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3195 * @hw: pointer to hardware structure
3196 * @enable: enable or disable switch for anti-spoofing
3197 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3198 *
3199 **/
3200void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3201{
3202 int j;
3203 int pf_target_reg = pf >> 3;
3204 int pf_target_shift = pf % 8;
3205 u32 pfvfspoof = 0;
3206
3207 if (hw->mac.type == ixgbe_mac_82598EB)
3208 return;
3209
3210 if (enable)
3211 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3212
3213 /*
3214 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3215 * MAC anti-spoof enables in each register array element.
3216 */
3217 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3218 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3219
3220 /* If not enabling anti-spoofing then done */
3221 if (!enable)
3222 return;
3223
3224 /*
3225 * The PF should be allowed to spoof so that it can support
3226 * emulation mode NICs. Reset the bit assigned to the PF
3227 */
3228 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3229 pfvfspoof ^= (1 << pf_target_shift);
3230 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3231}
3232
3233/**
3234 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3235 * @hw: pointer to hardware structure
3236 * @enable: enable or disable switch for VLAN anti-spoofing
3237 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3238 *
3239 **/
3240void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3241{
3242 int vf_target_reg = vf >> 3;
3243 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3244 u32 pfvfspoof;
3245
3246 if (hw->mac.type == ixgbe_mac_82598EB)
3247 return;
3248
3249 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3250 if (enable)
3251 pfvfspoof |= (1 << vf_target_shift);
3252 else
3253 pfvfspoof &= ~(1 << vf_target_shift);
3254 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3255}
b776d104
ET		 3256
3257/**
3258 * ixgbe_get_device_caps_generic - Get additional device capabilities
3259 * @hw: pointer to hardware structure
3260 * @device_caps: the EEPROM word with the extra device capabilities
3261 *
3262 * This function will read the EEPROM location for the device capabilities,
3263 * and return the word through device_caps.
3264 **/
3265s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3266{
3267 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3268
3269 return 0;
3270}
80605c65
JF		 3271
3272/**
3273 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3274 * @hw: pointer to hardware structure
3275 * @num_pb: number of packet buffers to allocate
3276 * @headroom: reserve n KB of headroom
3277 * @strategy: packet buffer allocation strategy
3278 **/
3279void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3280 int num_pb,
3281 u32 headroom,
3282 int strategy)
3283{
3284 u32 pbsize = hw->mac.rx_pb_size;
3285 int i = 0;
3286 u32 rxpktsize, txpktsize, txpbthresh;
3287
3288 /* Reserve headroom */
3289 pbsize -= headroom;
3290
3291 if (!num_pb)
3292 num_pb = 1;
3293
3294 /* Divide remaining packet buffer space amongst the number
3295 * of packet buffers requested using supplied strategy.
3296 */
3297 switch (strategy) {
3298 case (PBA_STRATEGY_WEIGHTED):
3299 /* pba_80_48 strategy weight first half of packet buffer with
3300 * 5/8 of the packet buffer space.
3301 */
3302 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3303 pbsize -= rxpktsize * (num_pb / 2);
3304 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3305 for (; i < (num_pb / 2); i++)
3306 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3307 /* Fall through to configure remaining packet buffers */
3308 case (PBA_STRATEGY_EQUAL):
3309 /* Divide the remaining Rx packet buffer evenly among the TCs */
3310 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3311 for (; i < num_pb; i++)
3312 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3313 break;
3314 default:
3315 break;
3316 }
3317
3318 /*
3319 * Setup Tx packet buffer and threshold equally for all TCs
3320 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3321 * 10 since the largest packet we support is just over 9K.
3322 */
3323 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3324 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3325 for (i = 0; i < num_pb; i++) {
3326 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3327 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3328 }
3329
3330 /* Clear unused TCs, if any, to zero buffer size*/
3331 for (; i < IXGBE_MAX_PB; i++) {
3332 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3333 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3334 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3335 }
3336}
9612de92
ET		 3337
3338/**
3339 * ixgbe_calculate_checksum - Calculate checksum for buffer
3340 * @buffer: pointer to EEPROM
3341 * @length: size of EEPROM to calculate a checksum for
3342 * Calculates the checksum for some buffer on a specified length. The
3343 * checksum calculated is returned.
3344 **/
3345static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3346{
3347 u32 i;
3348 u8 sum = 0;
3349
3350 if (!buffer)
3351 return 0;
3352
3353 for (i = 0; i < length; i++)
3354 sum += buffer[i];
3355
3356 return (u8) (0 - sum);
3357}
3358
3359/**
3360 * ixgbe_host_interface_command - Issue command to manageability block
3361 * @hw: pointer to the HW structure
3362 * @buffer: contains the command to write and where the return status will
3363 * be placed
3364 * @lenght: lenght of buffer, must be multiple of 4 bytes
3365 *
3366 * Communicates with the manageability block. On success return 0
3367 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3368 **/
3369static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u8 *buffer,
3370 u32 length)
3371{
3372 u32 hicr, i;
3373 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3374 u8 buf_len, dword_len;
3375
3376 s32 ret_val = 0;
3377
3378 if (length == 0 || length & 0x3 ||
3379 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3380 hw_dbg(hw, "Buffer length failure.\n");
3381 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3382 goto out;
3383 }
3384
3385 /* Check that the host interface is enabled. */
3386 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3387 if ((hicr & IXGBE_HICR_EN) == 0) {
3388 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3389 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3390 goto out;
3391 }
3392
3393 /* Calculate length in DWORDs */
3394 dword_len = length >> 2;
3395
3396 /*
3397 * The device driver writes the relevant command block
3398 * into the ram area.
3399 */
3400 for (i = 0; i < dword_len; i++)
3401 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3402 i, *((u32 *)buffer + i));
3403
3404 /* Setting this bit tells the ARC that a new command is pending. */
3405 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3406
3407 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3408 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3409 if (!(hicr & IXGBE_HICR_C))
3410 break;
3411 usleep_range(1000, 2000);
3412 }
3413
3414 /* Check command successful completion. */
3415 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3416 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3417 hw_dbg(hw, "Command has failed with no status valid.\n");
3418 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3419 goto out;
3420 }
3421
3422 /* Calculate length in DWORDs */
3423 dword_len = hdr_size >> 2;
3424
3425 /* first pull in the header so we know the buffer length */
3426 for (i = 0; i < dword_len; i++)
3427 *((u32 *)buffer + i) =
3428 IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3429
3430 /* If there is any thing in data position pull it in */
3431 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3432 if (buf_len == 0)
3433 goto out;
3434
3435 if (length < (buf_len + hdr_size)) {
3436 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3437 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3438 goto out;
3439 }
3440
3441 /* Calculate length in DWORDs, add one for odd lengths */
3442 dword_len = (buf_len + 1) >> 2;
3443
3444 /* Pull in the rest of the buffer (i is where we left off)*/
3445 for (; i < buf_len; i++)
3446 *((u32 *)buffer + i) =
3447 IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, i);
3448
3449out:
3450 return ret_val;
3451}
3452
3453/**
3454 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3455 * @hw: pointer to the HW structure
3456 * @maj: driver version major number
3457 * @min: driver version minor number
3458 * @build: driver version build number
3459 * @sub: driver version sub build number
3460 *
3461 * Sends driver version number to firmware through the manageability
3462 * block. On success return 0
3463 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3464 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3465 **/
3466s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3467 u8 build, u8 sub)
3468{
3469 struct ixgbe_hic_drv_info fw_cmd;
3470 int i;
3471 s32 ret_val = 0;
3472
3473 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3474 ret_val = IXGBE_ERR_SWFW_SYNC;
3475 goto out;
3476 }
3477
3478 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3479 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3480 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3481 fw_cmd.port_num = (u8)hw->bus.func;
3482 fw_cmd.ver_maj = maj;
3483 fw_cmd.ver_min = min;
3484 fw_cmd.ver_build = build;
3485 fw_cmd.ver_sub = sub;
3486 fw_cmd.hdr.checksum = 0;
3487 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3488 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3489 fw_cmd.pad = 0;
3490 fw_cmd.pad2 = 0;
3491
3492 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3493 ret_val = ixgbe_host_interface_command(hw, (u8 *)&fw_cmd,
3494 sizeof(fw_cmd));
3495 if (ret_val != 0)
3496 continue;
3497
3498 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3499 FW_CEM_RESP_STATUS_SUCCESS)
3500 ret_val = 0;
3501 else
3502 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3503
3504 break;
3505 }
3506
3507 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3508out:
3509 return ret_val;
3510}
Linux kernel - Deliverables
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