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ixgbe: Add timeout parameter to ixgbe_host_interface_command
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
14438464 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
ccffad25 32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 44 u16 count);
c44ade9e
JB		 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 49
9a799d71 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
ff9d1a5a 58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 59
67a79df2
AD		 60/**
61 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * control
63 * @hw: pointer to hardware structure
64 *
65 * There are several phys that do not support autoneg flow control. This
66 * function check the device id to see if the associated phy supports
67 * autoneg flow control.
68 **/
73d80953 69bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2 70{
73d80953
DS		 71 bool supported = false;
72 ixgbe_link_speed speed;
73 bool link_up;
67a79df2 74
73d80953
DS		 75 switch (hw->phy.media_type) {
76 case ixgbe_media_type_fiber:
77 hw->mac.ops.check_link(hw, &speed, &link_up, false);
78 /* if link is down, assume supported */
79 if (link_up)
80 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
81 true : false;
82 else
83 supported = true;
84 break;
85 case ixgbe_media_type_backplane:
86 supported = true;
87 break;
88 case ixgbe_media_type_copper:
89 /* only some copper devices support flow control autoneg */
90 switch (hw->device_id) {
91 case IXGBE_DEV_ID_82599_T3_LOM:
92 case IXGBE_DEV_ID_X540T:
93 case IXGBE_DEV_ID_X540T1:
94 supported = true;
95 break;
96 default:
97 break;
98 }
67a79df2 99 default:
73d80953 100 break;
67a79df2 101 }
73d80953
DS		 102
103 return supported;
67a79df2
AD		 104}
105
106/**
107 * ixgbe_setup_fc - Set up flow control
108 * @hw: pointer to hardware structure
109 *
110 * Called at init time to set up flow control.
111 **/
041441d0 112static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 113{
114 s32 ret_val = 0;
115 u32 reg = 0, reg_bp = 0;
116 u16 reg_cu = 0;
429d6a3b 117 bool locked = false;
67a79df2 118
67a79df2
AD		 119 /*
120 * Validate the requested mode. Strict IEEE mode does not allow
121 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
122 */
123 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
124 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
e90dd264 125 return IXGBE_ERR_INVALID_LINK_SETTINGS;
67a79df2
AD		 126 }
127
128 /*
129 * 10gig parts do not have a word in the EEPROM to determine the
130 * default flow control setting, so we explicitly set it to full.
131 */
132 if (hw->fc.requested_mode == ixgbe_fc_default)
133 hw->fc.requested_mode = ixgbe_fc_full;
134
135 /*
136 * Set up the 1G and 10G flow control advertisement registers so the
137 * HW will be able to do fc autoneg once the cable is plugged in. If
138 * we link at 10G, the 1G advertisement is harmless and vice versa.
139 */
67a79df2 140 switch (hw->phy.media_type) {
429d6a3b
DS		 141 case ixgbe_media_type_backplane:
142 /* some MAC's need RMW protection on AUTOC */
143 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
f8cf7a00 144 if (ret_val)
e90dd264 145 return ret_val;
429d6a3b
DS		 146
147 /* only backplane uses autoc so fall though */
67a79df2 148 case ixgbe_media_type_fiber:
67a79df2 149 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
429d6a3b 150
67a79df2 151 break;
67a79df2
AD		 152 case ixgbe_media_type_copper:
153 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
154 MDIO_MMD_AN, &reg_cu);
155 break;
67a79df2 156 default:
041441d0 157 break;
67a79df2
AD		 158 }
159
160 /*
161 * The possible values of fc.requested_mode are:
162 * 0: Flow control is completely disabled
163 * 1: Rx flow control is enabled (we can receive pause frames,
164 * but not send pause frames).
165 * 2: Tx flow control is enabled (we can send pause frames but
166 * we do not support receiving pause frames).
167 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 168 * other: Invalid.
169 */
170 switch (hw->fc.requested_mode) {
171 case ixgbe_fc_none:
172 /* Flow control completely disabled by software override. */
173 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
174 if (hw->phy.media_type == ixgbe_media_type_backplane)
175 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
176 IXGBE_AUTOC_ASM_PAUSE);
177 else if (hw->phy.media_type == ixgbe_media_type_copper)
178 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
179 break;
67a79df2
AD		 180 case ixgbe_fc_tx_pause:
181 /*
182 * Tx Flow control is enabled, and Rx Flow control is
183 * disabled by software override.
184 */
041441d0
AD		 185 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
186 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 187 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 188 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
189 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 190 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 191 reg_cu |= IXGBE_TAF_ASM_PAUSE;
192 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 193 }
194 break;
041441d0
AD		 195 case ixgbe_fc_rx_pause:
196 /*
197 * Rx Flow control is enabled and Tx Flow control is
198 * disabled by software override. Since there really
199 * isn't a way to advertise that we are capable of RX
200 * Pause ONLY, we will advertise that we support both
201 * symmetric and asymmetric Rx PAUSE, as such we fall
202 * through to the fc_full statement. Later, we will
203 * disable the adapter's ability to send PAUSE frames.
204 */
67a79df2
AD		 205 case ixgbe_fc_full:
206 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 207 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 208 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 209 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
210 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 211 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 212 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 213 break;
67a79df2
AD		 214 default:
215 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 216 return IXGBE_ERR_CONFIG;
67a79df2
AD		 217 }
218
219 if (hw->mac.type != ixgbe_mac_X540) {
220 /*
221 * Enable auto-negotiation between the MAC & PHY;
222 * the MAC will advertise clause 37 flow control.
223 */
224 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
225 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
226
227 /* Disable AN timeout */
228 if (hw->fc.strict_ieee)
229 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
230
231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
232 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
233 }
234
235 /*
236 * AUTOC restart handles negotiation of 1G and 10G on backplane
237 * and copper. There is no need to set the PCS1GCTL register.
238 *
239 */
240 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 241 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
242 * LESM is on, likewise reset_pipeline requries the lock as
243 * it also writes AUTOC.
244 */
429d6a3b
DS		 245 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
246 if (ret_val)
e90dd264 247 return ret_val;
d7bbcd32 248
67a79df2 249 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
429d6a3b 250 ixgbe_device_supports_autoneg_fc(hw)) {
67a79df2
AD		 251 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
252 MDIO_MMD_AN, reg_cu);
253 }
254
255 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
67a79df2
AD		 256 return ret_val;
257}
258
9a799d71 259/**
c44ade9e 260 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 261 * @hw: pointer to hardware structure
262 *
263 * Starts the hardware by filling the bus info structure and media type, clears
264 * all on chip counters, initializes receive address registers, multicast
265 * table, VLAN filter table, calls routine to set up link and flow control
266 * settings, and leaves transmit and receive units disabled and uninitialized
267 **/
c44ade9e 268s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71 269{
e5776620 270 s32 ret_val;
9a799d71
AK		 271 u32 ctrl_ext;
272
273 /* Set the media type */
274 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
275
276 /* Identify the PHY */
c44ade9e 277 hw->phy.ops.identify(hw);
9a799d71 278
9a799d71 279 /* Clear the VLAN filter table */
c44ade9e 280 hw->mac.ops.clear_vfta(hw);
9a799d71 281
9a799d71 282 /* Clear statistics registers */
c44ade9e 283 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 284
285 /* Set No Snoop Disable */
286 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
287 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
288 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 289 IXGBE_WRITE_FLUSH(hw);
9a799d71 290
620fa036 291 /* Setup flow control */
e5776620
JK		 292 ret_val = ixgbe_setup_fc(hw);
293 if (!ret_val)
e90dd264 294 return 0;
620fa036 295
9a799d71
AK		 296 /* Clear adapter stopped flag */
297 hw->adapter_stopped = false;
298
e5776620 299 return ret_val;
9a799d71
AK		 300}
301
7184b7cf
ET		 302/**
303 * ixgbe_start_hw_gen2 - Init sequence for common device family
304 * @hw: pointer to hw structure
305 *
306 * Performs the init sequence common to the second generation
307 * of 10 GbE devices.
308 * Devices in the second generation:
309 * 82599
310 * X540
311 **/
312s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
313{
314 u32 i;
3d5c5207 315 u32 regval;
7184b7cf
ET		 316
317 /* Clear the rate limiters */
318 for (i = 0; i < hw->mac.max_tx_queues; i++) {
319 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
320 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
321 }
322 IXGBE_WRITE_FLUSH(hw);
323
3d5c5207
ET		 324 /* Disable relaxed ordering */
325 for (i = 0; i < hw->mac.max_tx_queues; i++) {
326 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 327 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 328 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
329 }
330
331 for (i = 0; i < hw->mac.max_rx_queues; i++) {
332 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 333 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
334 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 335 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
336 }
337
7184b7cf
ET		 338 return 0;
339}
340
9a799d71 341/**
c44ade9e 342 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 343 * @hw: pointer to hardware structure
344 *
c44ade9e 345 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 346 * structure and media type, clears all on chip counters, initializes receive
347 * address registers, multicast table, VLAN filter table, calls routine to set
348 * up link and flow control settings, and leaves transmit and receive units
349 * disabled and uninitialized
350 **/
c44ade9e 351s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 352{
794caeb2
PWJ		 353 s32 status;
354
9a799d71 355 /* Reset the hardware */
794caeb2 356 status = hw->mac.ops.reset_hw(hw);
9a799d71 357
794caeb2
PWJ		 358 if (status == 0) {
359 /* Start the HW */
360 status = hw->mac.ops.start_hw(hw);
361 }
9a799d71 362
794caeb2 363 return status;
9a799d71
AK		 364}
365
366/**
c44ade9e 367 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 368 * @hw: pointer to hardware structure
369 *
370 * Clears all hardware statistics counters by reading them from the hardware
371 * Statistics counters are clear on read.
372 **/
c44ade9e 373s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 374{
375 u16 i = 0;
376
377 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
378 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
379 IXGBE_READ_REG(hw, IXGBE_ERRBC);
380 IXGBE_READ_REG(hw, IXGBE_MSPDC);
381 for (i = 0; i < 8; i++)
382 IXGBE_READ_REG(hw, IXGBE_MPC(i));
383
384 IXGBE_READ_REG(hw, IXGBE_MLFC);
385 IXGBE_READ_REG(hw, IXGBE_MRFC);
386 IXGBE_READ_REG(hw, IXGBE_RLEC);
387 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 388 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 389 if (hw->mac.type >= ixgbe_mac_82599EB) {
390 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
391 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
392 } else {
393 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
394 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
395 }
9a799d71
AK		 396
397 for (i = 0; i < 8; i++) {
398 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 399 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 400 if (hw->mac.type >= ixgbe_mac_82599EB) {
401 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
402 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
403 } else {
404 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
405 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
406 }
9a799d71 407 }
667c7565
ET		 408 if (hw->mac.type >= ixgbe_mac_82599EB)
409 for (i = 0; i < 8; i++)
410 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 411 IXGBE_READ_REG(hw, IXGBE_PRC64);
412 IXGBE_READ_REG(hw, IXGBE_PRC127);
413 IXGBE_READ_REG(hw, IXGBE_PRC255);
414 IXGBE_READ_REG(hw, IXGBE_PRC511);
415 IXGBE_READ_REG(hw, IXGBE_PRC1023);
416 IXGBE_READ_REG(hw, IXGBE_PRC1522);
417 IXGBE_READ_REG(hw, IXGBE_GPRC);
418 IXGBE_READ_REG(hw, IXGBE_BPRC);
419 IXGBE_READ_REG(hw, IXGBE_MPRC);
420 IXGBE_READ_REG(hw, IXGBE_GPTC);
421 IXGBE_READ_REG(hw, IXGBE_GORCL);
422 IXGBE_READ_REG(hw, IXGBE_GORCH);
423 IXGBE_READ_REG(hw, IXGBE_GOTCL);
424 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 425 if (hw->mac.type == ixgbe_mac_82598EB)
426 for (i = 0; i < 8; i++)
427 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 428 IXGBE_READ_REG(hw, IXGBE_RUC);
429 IXGBE_READ_REG(hw, IXGBE_RFC);
430 IXGBE_READ_REG(hw, IXGBE_ROC);
431 IXGBE_READ_REG(hw, IXGBE_RJC);
432 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
433 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
434 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
435 IXGBE_READ_REG(hw, IXGBE_TORL);
436 IXGBE_READ_REG(hw, IXGBE_TORH);
437 IXGBE_READ_REG(hw, IXGBE_TPR);
438 IXGBE_READ_REG(hw, IXGBE_TPT);
439 IXGBE_READ_REG(hw, IXGBE_PTC64);
440 IXGBE_READ_REG(hw, IXGBE_PTC127);
441 IXGBE_READ_REG(hw, IXGBE_PTC255);
442 IXGBE_READ_REG(hw, IXGBE_PTC511);
443 IXGBE_READ_REG(hw, IXGBE_PTC1023);
444 IXGBE_READ_REG(hw, IXGBE_PTC1522);
445 IXGBE_READ_REG(hw, IXGBE_MPTC);
446 IXGBE_READ_REG(hw, IXGBE_BPTC);
447 for (i = 0; i < 16; i++) {
448 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 449 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 450 if (hw->mac.type >= ixgbe_mac_82599EB) {
451 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
452 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
453 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
454 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
455 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
456 } else {
457 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
458 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
459 }
9a799d71
AK		 460 }
461
a3aeea0e
ET		 462 if (hw->mac.type == ixgbe_mac_X540) {
463 if (hw->phy.id == 0)
464 hw->phy.ops.identify(hw);
c1085b10
ET		 465 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
466 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
467 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
468 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 469 }
470
9a799d71
AK		 471 return 0;
472}
473
474/**
289700db 475 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 476 * @hw: pointer to hardware structure
289700db
DS		 477 * @pba_num: stores the part number string from the EEPROM
478 * @pba_num_size: part number string buffer length
c44ade9e 479 *
289700db 480 * Reads the part number string from the EEPROM.
c44ade9e 481 **/
289700db 482s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 483 u32 pba_num_size)
c44ade9e
JB		 484{
485 s32 ret_val;
486 u16 data;
289700db
DS		 487 u16 pba_ptr;
488 u16 offset;
489 u16 length;
490
491 if (pba_num == NULL) {
492 hw_dbg(hw, "PBA string buffer was null\n");
493 return IXGBE_ERR_INVALID_ARGUMENT;
494 }
c44ade9e
JB		 495
496 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
497 if (ret_val) {
498 hw_dbg(hw, "NVM Read Error\n");
499 return ret_val;
500 }
c44ade9e 501
289700db 502 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 503 if (ret_val) {
504 hw_dbg(hw, "NVM Read Error\n");
505 return ret_val;
506 }
289700db
DS		 507
508 /*
509 * if data is not ptr guard the PBA must be in legacy format which
510 * means pba_ptr is actually our second data word for the PBA number
511 * and we can decode it into an ascii string
512 */
513 if (data != IXGBE_PBANUM_PTR_GUARD) {
514 hw_dbg(hw, "NVM PBA number is not stored as string\n");
515
516 /* we will need 11 characters to store the PBA */
517 if (pba_num_size < 11) {
518 hw_dbg(hw, "PBA string buffer too small\n");
519 return IXGBE_ERR_NO_SPACE;
520 }
521
522 /* extract hex string from data and pba_ptr */
523 pba_num[0] = (data >> 12) & 0xF;
524 pba_num[1] = (data >> 8) & 0xF;
525 pba_num[2] = (data >> 4) & 0xF;
526 pba_num[3] = data & 0xF;
527 pba_num[4] = (pba_ptr >> 12) & 0xF;
528 pba_num[5] = (pba_ptr >> 8) & 0xF;
529 pba_num[6] = '-';
530 pba_num[7] = 0;
531 pba_num[8] = (pba_ptr >> 4) & 0xF;
532 pba_num[9] = pba_ptr & 0xF;
533
534 /* put a null character on the end of our string */
535 pba_num[10] = '\0';
536
537 /* switch all the data but the '-' to hex char */
538 for (offset = 0; offset < 10; offset++) {
539 if (pba_num[offset] < 0xA)
540 pba_num[offset] += '0';
541 else if (pba_num[offset] < 0x10)
542 pba_num[offset] += 'A' - 0xA;
543 }
544
545 return 0;
546 }
547
548 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
549 if (ret_val) {
550 hw_dbg(hw, "NVM Read Error\n");
551 return ret_val;
552 }
553
554 if (length == 0xFFFF || length == 0) {
555 hw_dbg(hw, "NVM PBA number section invalid length\n");
556 return IXGBE_ERR_PBA_SECTION;
557 }
558
559 /* check if pba_num buffer is big enough */
560 if (pba_num_size < (((u32)length * 2) - 1)) {
561 hw_dbg(hw, "PBA string buffer too small\n");
562 return IXGBE_ERR_NO_SPACE;
563 }
564
565 /* trim pba length from start of string */
566 pba_ptr++;
567 length--;
568
569 for (offset = 0; offset < length; offset++) {
570 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
571 if (ret_val) {
572 hw_dbg(hw, "NVM Read Error\n");
573 return ret_val;
574 }
575 pba_num[offset * 2] = (u8)(data >> 8);
576 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
577 }
578 pba_num[offset * 2] = '\0';
c44ade9e
JB		 579
580 return 0;
581}
582
583/**
584 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 585 * @hw: pointer to hardware structure
586 * @mac_addr: Adapter MAC address
587 *
588 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
589 * A reset of the adapter must be performed prior to calling this function
590 * in order for the MAC address to have been loaded from the EEPROM into RAR0
591 **/
c44ade9e 592s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 593{
594 u32 rar_high;
595 u32 rar_low;
596 u16 i;
597
598 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
599 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
600
601 for (i = 0; i < 4; i++)
602 mac_addr[i] = (u8)(rar_low >> (i*8));
603
604 for (i = 0; i < 2; i++)
605 mac_addr[i+4] = (u8)(rar_high >> (i*8));
606
607 return 0;
608}
609
ef1889d5
JK		 610enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
611{
612 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
613 case IXGBE_PCI_LINK_WIDTH_1:
614 return ixgbe_bus_width_pcie_x1;
615 case IXGBE_PCI_LINK_WIDTH_2:
616 return ixgbe_bus_width_pcie_x2;
617 case IXGBE_PCI_LINK_WIDTH_4:
618 return ixgbe_bus_width_pcie_x4;
619 case IXGBE_PCI_LINK_WIDTH_8:
620 return ixgbe_bus_width_pcie_x8;
621 default:
622 return ixgbe_bus_width_unknown;
623 }
624}
625
626enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
627{
628 switch (link_status & IXGBE_PCI_LINK_SPEED) {
629 case IXGBE_PCI_LINK_SPEED_2500:
630 return ixgbe_bus_speed_2500;
631 case IXGBE_PCI_LINK_SPEED_5000:
632 return ixgbe_bus_speed_5000;
633 case IXGBE_PCI_LINK_SPEED_8000:
634 return ixgbe_bus_speed_8000;
635 default:
636 return ixgbe_bus_speed_unknown;
637 }
638}
639
11afc1b1
PW		 640/**
641 * ixgbe_get_bus_info_generic - Generic set PCI bus info
642 * @hw: pointer to hardware structure
643 *
644 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
645 **/
646s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
647{
11afc1b1
PW		 648 u16 link_status;
649
650 hw->bus.type = ixgbe_bus_type_pci_express;
651
652 /* Get the negotiated link width and speed from PCI config space */
0d7c6e00 653 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
11afc1b1 654
ef1889d5
JK		 655 hw->bus.width = ixgbe_convert_bus_width(link_status);
656 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1 657
0d7c6e00 658 hw->mac.ops.set_lan_id(hw);
11afc1b1
PW		 659
660 return 0;
661}
662
663/**
664 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
665 * @hw: pointer to the HW structure
666 *
667 * Determines the LAN function id by reading memory-mapped registers
668 * and swaps the port value if requested.
669 **/
670void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
671{
672 struct ixgbe_bus_info *bus = &hw->bus;
673 u32 reg;
674
675 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
676 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
677 bus->lan_id = bus->func;
678
679 /* check for a port swap */
680 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
681 if (reg & IXGBE_FACTPS_LFS)
682 bus->func ^= 0x1;
683}
684
9a799d71 685/**
c44ade9e 686 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 687 * @hw: pointer to hardware structure
688 *
689 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
690 * disables transmit and receive units. The adapter_stopped flag is used by
691 * the shared code and drivers to determine if the adapter is in a stopped
692 * state and should not touch the hardware.
693 **/
c44ade9e 694s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 695{
9a799d71
AK		 696 u32 reg_val;
697 u16 i;
698
699 /*
700 * Set the adapter_stopped flag so other driver functions stop touching
701 * the hardware
702 */
703 hw->adapter_stopped = true;
704
705 /* Disable the receive unit */
ff9d1a5a 706 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
9a799d71 707
ff9d1a5a 708 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 709 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
710
ff9d1a5a 711 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 712 IXGBE_READ_REG(hw, IXGBE_EICR);
713
714 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 715 for (i = 0; i < hw->mac.max_tx_queues; i++)
716 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
717
718 /* Disable the receive unit by stopping each queue */
719 for (i = 0; i < hw->mac.max_rx_queues; i++) {
720 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
721 reg_val &= ~IXGBE_RXDCTL_ENABLE;
722 reg_val |= IXGBE_RXDCTL_SWFLSH;
723 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 724 }
725
ff9d1a5a
ET		 726 /* flush all queues disables */
727 IXGBE_WRITE_FLUSH(hw);
728 usleep_range(1000, 2000);
729
c44ade9e
JB		 730 /*
731 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
732 * access and verify no pending requests
733 */
ff9d1a5a 734 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 735}
736
737/**
c44ade9e 738 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 739 * @hw: pointer to hardware structure
740 * @index: led number to turn on
741 **/
c44ade9e 742s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 743{
744 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
745
746 /* To turn on the LED, set mode to ON. */
747 led_reg &= ~IXGBE_LED_MODE_MASK(index);
748 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
749 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 750 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 751
752 return 0;
753}
754
755/**
c44ade9e 756 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 757 * @hw: pointer to hardware structure
758 * @index: led number to turn off
759 **/
c44ade9e 760s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 761{
762 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
763
764 /* To turn off the LED, set mode to OFF. */
765 led_reg &= ~IXGBE_LED_MODE_MASK(index);
766 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
767 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 768 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 769
770 return 0;
771}
772
9a799d71 773/**
c44ade9e 774 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 775 * @hw: pointer to hardware structure
776 *
777 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
778 * ixgbe_hw struct in order to set up EEPROM access.
779 **/
c44ade9e 780s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 781{
782 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
783 u32 eec;
784 u16 eeprom_size;
785
786 if (eeprom->type == ixgbe_eeprom_uninitialized) {
787 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 788 /* Set default semaphore delay to 10ms which is a well
789 * tested value */
790 eeprom->semaphore_delay = 10;
68c7005d
ET		 791 /* Clear EEPROM page size, it will be initialized as needed */
792 eeprom->word_page_size = 0;
9a799d71
AK		 793
794 /*
795 * Check for EEPROM present first.
796 * If not present leave as none
797 */
798 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
799 if (eec & IXGBE_EEC_PRES) {
800 eeprom->type = ixgbe_eeprom_spi;
801
802 /*
803 * SPI EEPROM is assumed here. This code would need to
804 * change if a future EEPROM is not SPI.
805 */
806 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
807 IXGBE_EEC_SIZE_SHIFT);
808 eeprom->word_size = 1 << (eeprom_size +
809 IXGBE_EEPROM_WORD_SIZE_SHIFT);
810 }
811
812 if (eec & IXGBE_EEC_ADDR_SIZE)
813 eeprom->address_bits = 16;
814 else
815 eeprom->address_bits = 8;
6ec1b71f
JK		 816 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
817 eeprom->type, eeprom->word_size, eeprom->address_bits);
9a799d71
AK		 818 }
819
820 return 0;
821}
822
11afc1b1 823/**
68c7005d 824 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 825 * @hw: pointer to hardware structure
68c7005d
ET		 826 * @offset: offset within the EEPROM to write
827 * @words: number of words
828 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 829 *
68c7005d 830 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 831 **/
68c7005d
ET		 832s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
833 u16 words, u16 *data)
11afc1b1 834{
e90dd264 835 s32 status;
68c7005d 836 u16 i, count;
11afc1b1
PW		 837
838 hw->eeprom.ops.init_params(hw);
839
e90dd264
MR		 840 if (words == 0)
841 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 842
e90dd264
MR		 843 if (offset + words > hw->eeprom.word_size)
844 return IXGBE_ERR_EEPROM;
11afc1b1 845
68c7005d
ET		 846 /*
847 * The EEPROM page size cannot be queried from the chip. We do lazy
848 * initialization. It is worth to do that when we write large buffer.
849 */
850 if ((hw->eeprom.word_page_size == 0) &&
851 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
852 ixgbe_detect_eeprom_page_size_generic(hw, offset);
853
854 /*
855 * We cannot hold synchronization semaphores for too long
856 * to avoid other entity starvation. However it is more efficient
857 * to read in bursts than synchronizing access for each word.
858 */
859 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
860 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
861 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
862 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
863 count, &data[i]);
864
865 if (status != 0)
866 break;
867 }
868
68c7005d
ET		 869 return status;
870}
871
872/**
873 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
874 * @hw: pointer to hardware structure
875 * @offset: offset within the EEPROM to be written to
876 * @words: number of word(s)
877 * @data: 16 bit word(s) to be written to the EEPROM
878 *
879 * If ixgbe_eeprom_update_checksum is not called after this function, the
880 * EEPROM will most likely contain an invalid checksum.
881 **/
882static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
883 u16 words, u16 *data)
884{
885 s32 status;
886 u16 word;
887 u16 page_size;
888 u16 i;
889 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
890
11afc1b1
PW		 891 /* Prepare the EEPROM for writing */
892 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 893 if (status)
894 return status;
11afc1b1 895
e90dd264
MR		 896 if (ixgbe_ready_eeprom(hw) != 0) {
897 ixgbe_release_eeprom(hw);
898 return IXGBE_ERR_EEPROM;
11afc1b1
PW		 899 }
900
e90dd264
MR		 901 for (i = 0; i < words; i++) {
902 ixgbe_standby_eeprom(hw);
903
904 /* Send the WRITE ENABLE command (8 bit opcode) */
905 ixgbe_shift_out_eeprom_bits(hw,
906 IXGBE_EEPROM_WREN_OPCODE_SPI,
907 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 908
e90dd264 909 ixgbe_standby_eeprom(hw);
11afc1b1 910
e90dd264
MR		 911 /* Some SPI eeproms use the 8th address bit embedded
912 * in the opcode
913 */
914 if ((hw->eeprom.address_bits == 8) &&
915 ((offset + i) >= 128))
916 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
11afc1b1 917
e90dd264
MR		 918 /* Send the Write command (8-bit opcode + addr) */
919 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
920 IXGBE_EEPROM_OPCODE_BITS);
921 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
922 hw->eeprom.address_bits);
923
924 page_size = hw->eeprom.word_page_size;
925
926 /* Send the data in burst via SPI */
927 do {
928 word = data[i];
929 word = (word >> 8) | (word << 8);
930 ixgbe_shift_out_eeprom_bits(hw, word, 16);
931
932 if (page_size == 0)
933 break;
934
935 /* do not wrap around page */
936 if (((offset + i) & (page_size - 1)) ==
937 (page_size - 1))
938 break;
939 } while (++i < words);
940
941 ixgbe_standby_eeprom(hw);
942 usleep_range(10000, 20000);
68c7005d 943 }
e90dd264
MR		 944 /* Done with writing - release the EEPROM */
945 ixgbe_release_eeprom(hw);
11afc1b1 946
e90dd264 947 return 0;
68c7005d
ET		 948}
949
950/**
951 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
952 * @hw: pointer to hardware structure
953 * @offset: offset within the EEPROM to be written to
954 * @data: 16 bit word to be written to the EEPROM
955 *
956 * If ixgbe_eeprom_update_checksum is not called after this function, the
957 * EEPROM will most likely contain an invalid checksum.
958 **/
959s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
960{
68c7005d 961 hw->eeprom.ops.init_params(hw);
11afc1b1 962
e90dd264
MR		 963 if (offset >= hw->eeprom.word_size)
964 return IXGBE_ERR_EEPROM;
11afc1b1 965
e90dd264 966 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
11afc1b1
PW		 967}
968
9a799d71 969/**
68c7005d 970 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 971 * @hw: pointer to hardware structure
972 * @offset: offset within the EEPROM to be read
68c7005d
ET		 973 * @words: number of word(s)
974 * @data: read 16 bit words(s) from EEPROM
c44ade9e 975 *
68c7005d 976 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 977 **/
68c7005d
ET		 978s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
979 u16 words, u16 *data)
c44ade9e 980{
e90dd264 981 s32 status;
68c7005d 982 u16 i, count;
c44ade9e
JB		 983
984 hw->eeprom.ops.init_params(hw);
985
e90dd264
MR		 986 if (words == 0)
987 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 988
e90dd264
MR		 989 if (offset + words > hw->eeprom.word_size)
990 return IXGBE_ERR_EEPROM;
c44ade9e 991
68c7005d
ET		 992 /*
993 * We cannot hold synchronization semaphores for too long
994 * to avoid other entity starvation. However it is more efficient
995 * to read in bursts than synchronizing access for each word.
996 */
997 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
998 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
999 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1000
1001 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1002 count, &data[i]);
1003
e90dd264
MR		 1004 if (status)
1005 return status;
68c7005d
ET		 1006 }
1007
e90dd264 1008 return 0;
68c7005d
ET		 1009}
1010
1011/**
1012 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1013 * @hw: pointer to hardware structure
1014 * @offset: offset within the EEPROM to be read
1015 * @words: number of word(s)
1016 * @data: read 16 bit word(s) from EEPROM
1017 *
1018 * Reads 16 bit word(s) from EEPROM through bit-bang method
1019 **/
1020static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1021 u16 words, u16 *data)
1022{
1023 s32 status;
1024 u16 word_in;
1025 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1026 u16 i;
1027
c44ade9e
JB		 1028 /* Prepare the EEPROM for reading */
1029 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 1030 if (status)
1031 return status;
c44ade9e 1032
e90dd264
MR		 1033 if (ixgbe_ready_eeprom(hw) != 0) {
1034 ixgbe_release_eeprom(hw);
1035 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1036 }
1037
e90dd264
MR		 1038 for (i = 0; i < words; i++) {
1039 ixgbe_standby_eeprom(hw);
1040 /* Some SPI eeproms use the 8th address bit embedded
1041 * in the opcode
1042 */
1043 if ((hw->eeprom.address_bits == 8) &&
1044 ((offset + i) >= 128))
1045 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
c44ade9e 1046
e90dd264
MR		 1047 /* Send the READ command (opcode + addr) */
1048 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1049 IXGBE_EEPROM_OPCODE_BITS);
1050 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1051 hw->eeprom.address_bits);
1052
1053 /* Read the data. */
1054 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1055 data[i] = (word_in >> 8) | (word_in << 8);
68c7005d 1056 }
c44ade9e 1057
e90dd264
MR		 1058 /* End this read operation */
1059 ixgbe_release_eeprom(hw);
1060
1061 return 0;
68c7005d 1062}
c44ade9e 1063
68c7005d
ET		 1064/**
1065 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1066 * @hw: pointer to hardware structure
1067 * @offset: offset within the EEPROM to be read
1068 * @data: read 16 bit value from EEPROM
1069 *
1070 * Reads 16 bit value from EEPROM through bit-bang method
1071 **/
1072s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1073 u16 *data)
1074{
68c7005d
ET		 1075 hw->eeprom.ops.init_params(hw);
1076
e90dd264
MR		 1077 if (offset >= hw->eeprom.word_size)
1078 return IXGBE_ERR_EEPROM;
68c7005d 1079
e90dd264 1080 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
c44ade9e
JB		 1081}
1082
1083/**
68c7005d 1084 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1085 * @hw: pointer to hardware structure
68c7005d
ET		 1086 * @offset: offset of word in the EEPROM to read
1087 * @words: number of word(s)
1088 * @data: 16 bit word(s) from the EEPROM
9a799d71 1089 *
68c7005d 1090 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1091 **/
68c7005d
ET		 1092s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1093 u16 words, u16 *data)
9a799d71
AK		 1094{
1095 u32 eerd;
e90dd264 1096 s32 status;
68c7005d 1097 u32 i;
9a799d71 1098
c44ade9e
JB		 1099 hw->eeprom.ops.init_params(hw);
1100
e90dd264
MR		 1101 if (words == 0)
1102 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1103
e90dd264
MR		 1104 if (offset >= hw->eeprom.word_size)
1105 return IXGBE_ERR_EEPROM;
c44ade9e 1106
68c7005d 1107 for (i = 0; i < words; i++) {
d0111575 1108 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1109 IXGBE_EEPROM_RW_REG_START;
9a799d71 1110
68c7005d
ET		 1111 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1112 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1113
68c7005d
ET		 1114 if (status == 0) {
1115 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1116 IXGBE_EEPROM_RW_REG_DATA);
1117 } else {
1118 hw_dbg(hw, "Eeprom read timed out\n");
e90dd264 1119 return status;
68c7005d
ET		 1120 }
1121 }
e90dd264
MR		 1122
1123 return 0;
68c7005d 1124}
9a799d71 1125
68c7005d
ET		 1126/**
1127 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1128 * @hw: pointer to hardware structure
1129 * @offset: offset within the EEPROM to be used as a scratch pad
1130 *
1131 * Discover EEPROM page size by writing marching data at given offset.
1132 * This function is called only when we are writing a new large buffer
1133 * at given offset so the data would be overwritten anyway.
1134 **/
1135static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1136 u16 offset)
1137{
1138 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
e90dd264 1139 s32 status;
68c7005d
ET		 1140 u16 i;
1141
1142 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1143 data[i] = i;
1144
1145 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1146 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1147 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1148 hw->eeprom.word_page_size = 0;
e90dd264
MR		 1149 if (status)
1150 return status;
68c7005d
ET		 1151
1152 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
e90dd264
MR		 1153 if (status)
1154 return status;
68c7005d
ET		 1155
1156 /*
1157 * When writing in burst more than the actual page size
1158 * EEPROM address wraps around current page.
1159 */
1160 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1161
c5ffe7e1 1162 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
68c7005d 1163 hw->eeprom.word_page_size);
e90dd264 1164 return 0;
9a799d71
AK		 1165}
1166
eb9c3e3e 1167/**
68c7005d
ET		 1168 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1169 * @hw: pointer to hardware structure
1170 * @offset: offset of word in the EEPROM to read
1171 * @data: word read from the EEPROM
1172 *
1173 * Reads a 16 bit word from the EEPROM using the EERD register.
1174 **/
1175s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1176{
1177 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1178}
1179
1180/**
1181 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1182 * @hw: pointer to hardware structure
1183 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1184 * @words: number of words
1185 * @data: word(s) write to the EEPROM
eb9c3e3e 1186 *
68c7005d 1187 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1188 **/
68c7005d
ET		 1189s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1190 u16 words, u16 *data)
eb9c3e3e
ET		 1191{
1192 u32 eewr;
e90dd264 1193 s32 status;
68c7005d 1194 u16 i;
eb9c3e3e
ET		 1195
1196 hw->eeprom.ops.init_params(hw);
1197
e90dd264
MR		 1198 if (words == 0)
1199 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1200
e90dd264
MR		 1201 if (offset >= hw->eeprom.word_size)
1202 return IXGBE_ERR_EEPROM;
eb9c3e3e 1203
68c7005d
ET		 1204 for (i = 0; i < words; i++) {
1205 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1206 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1207 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1208
68c7005d 1209 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1210 if (status) {
68c7005d 1211 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1212 return status;
68c7005d 1213 }
eb9c3e3e 1214
68c7005d 1215 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1216
68c7005d 1217 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1218 if (status) {
68c7005d 1219 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1220 return status;
68c7005d 1221 }
eb9c3e3e
ET		 1222 }
1223
e90dd264 1224 return 0;
eb9c3e3e
ET		 1225}
1226
68c7005d
ET		 1227/**
1228 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1229 * @hw: pointer to hardware structure
1230 * @offset: offset of word in the EEPROM to write
1231 * @data: word write to the EEPROM
1232 *
1233 * Write a 16 bit word to the EEPROM using the EEWR register.
1234 **/
1235s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1236{
1237 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1238}
1239
9a799d71 1240/**
21ce849b 1241 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1242 * @hw: pointer to hardware structure
21ce849b 1243 * @ee_reg: EEPROM flag for polling
9a799d71 1244 *
21ce849b
MC		 1245 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1246 * read or write is done respectively.
9a799d71 1247 **/
eb9c3e3e 1248static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1249{
1250 u32 i;
1251 u32 reg;
9a799d71 1252
21ce849b
MC		 1253 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1254 if (ee_reg == IXGBE_NVM_POLL_READ)
1255 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1256 else
1257 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1258
1259 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
e90dd264 1260 return 0;
9a799d71
AK		 1261 }
1262 udelay(5);
1263 }
e90dd264 1264 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1265}
1266
c44ade9e
JB		 1267/**
1268 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1269 * @hw: pointer to hardware structure
1270 *
1271 * Prepares EEPROM for access using bit-bang method. This function should
1272 * be called before issuing a command to the EEPROM.
1273 **/
1274static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1275{
dbf893ee 1276 u32 eec;
c44ade9e
JB		 1277 u32 i;
1278
5e655105 1279 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
e90dd264 1280 return IXGBE_ERR_SWFW_SYNC;
c44ade9e 1281
e90dd264 1282 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
c44ade9e 1283
e90dd264
MR		 1284 /* Request EEPROM Access */
1285 eec |= IXGBE_EEC_REQ;
1286 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
c44ade9e 1287
e90dd264
MR		 1288 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1289 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1290 if (eec & IXGBE_EEC_GNT)
1291 break;
1292 udelay(5);
1293 }
c44ade9e 1294
e90dd264
MR		 1295 /* Release if grant not acquired */
1296 if (!(eec & IXGBE_EEC_GNT)) {
1297 eec &= ~IXGBE_EEC_REQ;
1298 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1299 hw_dbg(hw, "Could not acquire EEPROM grant\n");
c44ade9e 1300
e90dd264
MR		 1301 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1302 return IXGBE_ERR_EEPROM;
c44ade9e 1303 }
e90dd264
MR		 1304
1305 /* Setup EEPROM for Read/Write */
1306 /* Clear CS and SK */
1307 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1308 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1309 IXGBE_WRITE_FLUSH(hw);
1310 udelay(1);
1311 return 0;
c44ade9e
JB		 1312}
1313
9a799d71
AK		 1314/**
1315 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1316 * @hw: pointer to hardware structure
1317 *
1318 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1319 **/
1320static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1321{
dbf893ee 1322 u32 timeout = 2000;
9a799d71
AK		 1323 u32 i;
1324 u32 swsm;
1325
9a799d71
AK		 1326 /* Get SMBI software semaphore between device drivers first */
1327 for (i = 0; i < timeout; i++) {
1328 /*
1329 * If the SMBI bit is 0 when we read it, then the bit will be
1330 * set and we have the semaphore
1331 */
1332 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
e90dd264 1333 if (!(swsm & IXGBE_SWSM_SMBI))
9a799d71 1334 break;
d819fc52 1335 usleep_range(50, 100);
9a799d71
AK		 1336 }
1337
51275d37 1338 if (i == timeout) {
6ec1b71f 1339 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
e90dd264 1340 /* this release is particularly important because our attempts
51275d37
ET		 1341 * above to get the semaphore may have succeeded, and if there
1342 * was a timeout, we should unconditionally clear the semaphore
1343 * bits to free the driver to make progress
1344 */
1345 ixgbe_release_eeprom_semaphore(hw);
1346
d819fc52 1347 usleep_range(50, 100);
e90dd264 1348 /* one last try
51275d37
ET		 1349 * If the SMBI bit is 0 when we read it, then the bit will be
1350 * set and we have the semaphore
1351 */
1352 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
e90dd264
MR		 1353 if (swsm & IXGBE_SWSM_SMBI) {
1354 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1355 return IXGBE_ERR_EEPROM;
1356 }
51275d37
ET		 1357 }
1358
9a799d71 1359 /* Now get the semaphore between SW/FW through the SWESMBI bit */
e90dd264
MR		 1360 for (i = 0; i < timeout; i++) {
1361 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
9a799d71 1362
e90dd264
MR		 1363 /* Set the SW EEPROM semaphore bit to request access */
1364 swsm |= IXGBE_SWSM_SWESMBI;
1365 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
9a799d71 1366
e90dd264
MR		 1367 /* If we set the bit successfully then we got the
1368 * semaphore.
1369 */
1370 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1371 if (swsm & IXGBE_SWSM_SWESMBI)
1372 break;
9a799d71 1373
e90dd264
MR		 1374 usleep_range(50, 100);
1375 }
9a799d71 1376
e90dd264
MR		 1377 /* Release semaphores and return error if SW EEPROM semaphore
1378 * was not granted because we don't have access to the EEPROM
1379 */
1380 if (i >= timeout) {
1381 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1382 ixgbe_release_eeprom_semaphore(hw);
1383 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1384 }
1385
e90dd264 1386 return 0;
9a799d71
AK		 1387}
1388
1389/**
1390 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1391 * @hw: pointer to hardware structure
1392 *
1393 * This function clears hardware semaphore bits.
1394 **/
1395static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1396{
1397 u32 swsm;
1398
1399 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1400
1401 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1402 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1403 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1404 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1405}
1406
c44ade9e
JB		 1407/**
1408 * ixgbe_ready_eeprom - Polls for EEPROM ready
1409 * @hw: pointer to hardware structure
1410 **/
1411static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1412{
c44ade9e
JB		 1413 u16 i;
1414 u8 spi_stat_reg;
1415
1416 /*
1417 * Read "Status Register" repeatedly until the LSB is cleared. The
1418 * EEPROM will signal that the command has been completed by clearing
1419 * bit 0 of the internal status register. If it's not cleared within
1420 * 5 milliseconds, then error out.
1421 */
1422 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1423 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
e7cf745b 1424 IXGBE_EEPROM_OPCODE_BITS);
c44ade9e
JB		 1425 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1426 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1427 break;
1428
1429 udelay(5);
1430 ixgbe_standby_eeprom(hw);
6403eab1 1431 }
c44ade9e
JB		 1432
1433 /*
1434 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1435 * devices (and only 0-5mSec on 5V devices)
1436 */
1437 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1438 hw_dbg(hw, "SPI EEPROM Status error\n");
e90dd264 1439 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1440 }
1441
e90dd264 1442 return 0;
c44ade9e
JB		 1443}
1444
1445/**
1446 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1447 * @hw: pointer to hardware structure
1448 **/
1449static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1450{
1451 u32 eec;
1452
1453 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1454
1455 /* Toggle CS to flush commands */
1456 eec |= IXGBE_EEC_CS;
1457 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1458 IXGBE_WRITE_FLUSH(hw);
1459 udelay(1);
1460 eec &= ~IXGBE_EEC_CS;
1461 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1462 IXGBE_WRITE_FLUSH(hw);
1463 udelay(1);
1464}
1465
1466/**
1467 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1468 * @hw: pointer to hardware structure
1469 * @data: data to send to the EEPROM
1470 * @count: number of bits to shift out
1471 **/
1472static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 1473 u16 count)
c44ade9e
JB		 1474{
1475 u32 eec;
1476 u32 mask;
1477 u32 i;
1478
1479 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1480
1481 /*
1482 * Mask is used to shift "count" bits of "data" out to the EEPROM
1483 * one bit at a time. Determine the starting bit based on count
1484 */
1485 mask = 0x01 << (count - 1);
1486
1487 for (i = 0; i < count; i++) {
1488 /*
1489 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1490 * "1", and then raising and then lowering the clock (the SK
1491 * bit controls the clock input to the EEPROM). A "0" is
1492 * shifted out to the EEPROM by setting "DI" to "0" and then
1493 * raising and then lowering the clock.
1494 */
1495 if (data & mask)
1496 eec |= IXGBE_EEC_DI;
1497 else
1498 eec &= ~IXGBE_EEC_DI;
1499
1500 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1501 IXGBE_WRITE_FLUSH(hw);
1502
1503 udelay(1);
1504
1505 ixgbe_raise_eeprom_clk(hw, &eec);
1506 ixgbe_lower_eeprom_clk(hw, &eec);
1507
1508 /*
1509 * Shift mask to signify next bit of data to shift in to the
1510 * EEPROM
1511 */
1512 mask = mask >> 1;
6403eab1 1513 }
c44ade9e
JB		 1514
1515 /* We leave the "DI" bit set to "0" when we leave this routine. */
1516 eec &= ~IXGBE_EEC_DI;
1517 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1518 IXGBE_WRITE_FLUSH(hw);
1519}
1520
1521/**
1522 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1523 * @hw: pointer to hardware structure
1524 **/
1525static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1526{
1527 u32 eec;
1528 u32 i;
1529 u16 data = 0;
1530
1531 /*
1532 * In order to read a register from the EEPROM, we need to shift
1533 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1534 * the clock input to the EEPROM (setting the SK bit), and then reading
1535 * the value of the "DO" bit. During this "shifting in" process the
1536 * "DI" bit should always be clear.
1537 */
1538 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1539
1540 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1541
1542 for (i = 0; i < count; i++) {
1543 data = data << 1;
1544 ixgbe_raise_eeprom_clk(hw, &eec);
1545
1546 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1547
1548 eec &= ~(IXGBE_EEC_DI);
1549 if (eec & IXGBE_EEC_DO)
1550 data |= 1;
1551
1552 ixgbe_lower_eeprom_clk(hw, &eec);
1553 }
1554
1555 return data;
1556}
1557
1558/**
1559 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1560 * @hw: pointer to hardware structure
1561 * @eec: EEC register's current value
1562 **/
1563static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1564{
1565 /*
1566 * Raise the clock input to the EEPROM
1567 * (setting the SK bit), then delay
1568 */
1569 *eec = *eec | IXGBE_EEC_SK;
1570 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1571 IXGBE_WRITE_FLUSH(hw);
1572 udelay(1);
1573}
1574
1575/**
1576 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1577 * @hw: pointer to hardware structure
1578 * @eecd: EECD's current value
1579 **/
1580static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1581{
1582 /*
1583 * Lower the clock input to the EEPROM (clearing the SK bit), then
1584 * delay
1585 */
1586 *eec = *eec & ~IXGBE_EEC_SK;
1587 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1588 IXGBE_WRITE_FLUSH(hw);
1589 udelay(1);
1590}
1591
1592/**
1593 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1594 * @hw: pointer to hardware structure
1595 **/
1596static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1597{
1598 u32 eec;
1599
1600 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1601
1602 eec |= IXGBE_EEC_CS; /* Pull CS high */
1603 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1604
1605 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1606 IXGBE_WRITE_FLUSH(hw);
1607
1608 udelay(1);
1609
1610 /* Stop requesting EEPROM access */
1611 eec &= ~IXGBE_EEC_REQ;
1612 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1613
90827996 1614 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1615
032b4325
DS		 1616 /*
1617 * Delay before attempt to obtain semaphore again to allow FW
1618 * access. semaphore_delay is in ms we need us for usleep_range
1619 */
1620 usleep_range(hw->eeprom.semaphore_delay * 1000,
1621 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1622}
1623
9a799d71 1624/**
dbf893ee 1625 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1626 * @hw: pointer to hardware structure
1627 **/
a391f1d5 1628u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1629{
1630 u16 i;
1631 u16 j;
1632 u16 checksum = 0;
1633 u16 length = 0;
1634 u16 pointer = 0;
1635 u16 word = 0;
1636
1637 /* Include 0x0-0x3F in the checksum */
1638 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1639 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1640 hw_dbg(hw, "EEPROM read failed\n");
1641 break;
1642 }
1643 checksum += word;
1644 }
1645
1646 /* Include all data from pointers except for the fw pointer */
1647 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1648 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1649
1650 /* Make sure the pointer seems valid */
1651 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1652 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1653
1654 if (length != 0xFFFF && length != 0) {
1655 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1656 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1657 checksum += word;
1658 }
1659 }
1660 }
1661 }
1662
1663 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1664
1665 return checksum;
1666}
1667
1668/**
c44ade9e 1669 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1670 * @hw: pointer to hardware structure
1671 * @checksum_val: calculated checksum
1672 *
1673 * Performs checksum calculation and validates the EEPROM checksum. If the
1674 * caller does not need checksum_val, the value can be NULL.
1675 **/
c44ade9e 1676s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 1677 u16 *checksum_val)
9a799d71
AK		 1678{
1679 s32 status;
1680 u16 checksum;
1681 u16 read_checksum = 0;
1682
1683 /*
1684 * Read the first word from the EEPROM. If this times out or fails, do
1685 * not continue or we could be in for a very long wait while every
1686 * EEPROM read fails
1687 */
c44ade9e 1688 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1689
1690 if (status == 0) {
a391f1d5 1691 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1692
c44ade9e 1693 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1694
1695 /*
1696 * Verify read checksum from EEPROM is the same as
1697 * calculated checksum
1698 */
1699 if (read_checksum != checksum)
1700 status = IXGBE_ERR_EEPROM_CHECKSUM;
1701
1702 /* If the user cares, return the calculated checksum */
1703 if (checksum_val)
1704 *checksum_val = checksum;
1705 } else {
1706 hw_dbg(hw, "EEPROM read failed\n");
1707 }
1708
1709 return status;
1710}
1711
c44ade9e
JB		 1712/**
1713 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1714 * @hw: pointer to hardware structure
1715 **/
1716s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1717{
1718 s32 status;
1719 u16 checksum;
1720
1721 /*
1722 * Read the first word from the EEPROM. If this times out or fails, do
1723 * not continue or we could be in for a very long wait while every
1724 * EEPROM read fails
1725 */
1726 status = hw->eeprom.ops.read(hw, 0, &checksum);
1727
1728 if (status == 0) {
a391f1d5 1729 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1730 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1731 checksum);
c44ade9e
JB		 1732 } else {
1733 hw_dbg(hw, "EEPROM read failed\n");
1734 }
1735
1736 return status;
1737}
1738
9a799d71 1739/**
c44ade9e 1740 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1741 * @hw: pointer to hardware structure
9a799d71 1742 * @index: Receive address register to write
c44ade9e
JB		 1743 * @addr: Address to put into receive address register
1744 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1745 * @enable_addr: set flag that address is active
1746 *
1747 * Puts an ethernet address into a receive address register.
1748 **/
c44ade9e 1749s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 1750 u32 enable_addr)
9a799d71
AK		 1751{
1752 u32 rar_low, rar_high;
c44ade9e
JB		 1753 u32 rar_entries = hw->mac.num_rar_entries;
1754
c700f4e6
ET		 1755 /* Make sure we are using a valid rar index range */
1756 if (index >= rar_entries) {
1757 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1758 return IXGBE_ERR_INVALID_ARGUMENT;
1759 }
1760
c44ade9e
JB		 1761 /* setup VMDq pool selection before this RAR gets enabled */
1762 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1763
c700f4e6
ET		 1764 /*
1765 * HW expects these in little endian so we reverse the byte
1766 * order from network order (big endian) to little endian
1767 */
1768 rar_low = ((u32)addr[0] |
1769 ((u32)addr[1] << 8) |
1770 ((u32)addr[2] << 16) |
1771 ((u32)addr[3] << 24));
1772 /*
1773 * Some parts put the VMDq setting in the extra RAH bits,
1774 * so save everything except the lower 16 bits that hold part
1775 * of the address and the address valid bit.
1776 */
1777 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1778 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1779 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1780
c700f4e6
ET		 1781 if (enable_addr != 0)
1782 rar_high |= IXGBE_RAH_AV;
9a799d71 1783
c700f4e6
ET		 1784 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1785 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1786
1787 return 0;
1788}
1789
1790/**
1791 * ixgbe_clear_rar_generic - Remove Rx address register
1792 * @hw: pointer to hardware structure
1793 * @index: Receive address register to write
1794 *
1795 * Clears an ethernet address from a receive address register.
1796 **/
1797s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1798{
1799 u32 rar_high;
1800 u32 rar_entries = hw->mac.num_rar_entries;
1801
1802 /* Make sure we are using a valid rar index range */
c700f4e6 1803 if (index >= rar_entries) {
c44ade9e 1804 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1805 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1806 }
1807
c700f4e6
ET		 1808 /*
1809 * Some parts put the VMDq setting in the extra RAH bits,
1810 * so save everything except the lower 16 bits that hold part
1811 * of the address and the address valid bit.
1812 */
1813 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1814 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1815
1816 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1817 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1818
c44ade9e
JB		 1819 /* clear VMDq pool/queue selection for this RAR */
1820 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1821
1822 return 0;
1823}
1824
c44ade9e
JB		 1825/**
1826 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1827 * @hw: pointer to hardware structure
1828 *
1829 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1830 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1831 * the receiver is in reset when the routine is called.
1832 **/
c44ade9e 1833s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1834{
1835 u32 i;
2c5645cf 1836 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1837
1838 /*
1839 * If the current mac address is valid, assume it is a software override
1840 * to the permanent address.
1841 * Otherwise, use the permanent address from the eeprom.
1842 */
f8ebc683 1843 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1844 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1845 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1846
ce7194d8 1847 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1848 } else {
1849 /* Setup the receive address. */
1850 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1851 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1852
c44ade9e 1853 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1854
1855 /* clear VMDq pool/queue selection for RAR 0 */
1856 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1857 }
c44ade9e 1858 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1859
1860 hw->addr_ctrl.rar_used_count = 1;
1861
1862 /* Zero out the other receive addresses. */
c44ade9e 1863 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1864 for (i = 1; i < rar_entries; i++) {
1865 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1866 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1867 }
1868
1869 /* Clear the MTA */
9a799d71
AK		 1870 hw->addr_ctrl.mta_in_use = 0;
1871 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1872
1873 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1874 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1875 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1876
c44ade9e
JB		 1877 if (hw->mac.ops.init_uta_tables)
1878 hw->mac.ops.init_uta_tables(hw);
1879
9a799d71
AK		 1880 return 0;
1881}
1882
1883/**
1884 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1885 * @hw: pointer to hardware structure
1886 * @mc_addr: the multicast address
1887 *
1888 * Extracts the 12 bits, from a multicast address, to determine which
1889 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1890 * incoming rx multicast addresses, to determine the bit-vector to check in
1891 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1892 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1893 * to mc_filter_type.
1894 **/
1895static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1896{
1897 u32 vector = 0;
1898
1899 switch (hw->mac.mc_filter_type) {
b4617240 1900 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1901 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1902 break;
b4617240 1903 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1904 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1905 break;
b4617240 1906 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1907 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1908 break;
b4617240 1909 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1910 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1911 break;
b4617240 1912 default: /* Invalid mc_filter_type */
9a799d71
AK		 1913 hw_dbg(hw, "MC filter type param set incorrectly\n");
1914 break;
1915 }
1916
1917 /* vector can only be 12-bits or boundary will be exceeded */
1918 vector &= 0xFFF;
1919 return vector;
1920}
1921
1922/**
1923 * ixgbe_set_mta - Set bit-vector in multicast table
1924 * @hw: pointer to hardware structure
1925 * @hash_value: Multicast address hash value
1926 *
1927 * Sets the bit-vector in the multicast table.
1928 **/
1929static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1930{
1931 u32 vector;
1932 u32 vector_bit;
1933 u32 vector_reg;
9a799d71
AK		 1934
1935 hw->addr_ctrl.mta_in_use++;
1936
1937 vector = ixgbe_mta_vector(hw, mc_addr);
1938 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1939
1940 /*
1941 * The MTA is a register array of 128 32-bit registers. It is treated
1942 * like an array of 4096 bits. We want to set bit
1943 * BitArray[vector_value]. So we figure out what register the bit is
1944 * in, read it, OR in the new bit, then write back the new value. The
1945 * register is determined by the upper 7 bits of the vector value and
1946 * the bit within that register are determined by the lower 5 bits of
1947 * the value.
1948 */
1949 vector_reg = (vector >> 5) & 0x7F;
1950 vector_bit = vector & 0x1F;
80960ab0 1951 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1952}
1953
9a799d71 1954/**
c44ade9e 1955 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1956 * @hw: pointer to hardware structure
2853eb89 1957 * @netdev: pointer to net device structure
9a799d71
AK		 1958 *
1959 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1960 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1961 * registers for the first multicast addresses, and hashes the rest into the
1962 * multicast table.
1963 **/
2853eb89
JP		 1964s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1965 struct net_device *netdev)
9a799d71 1966{
22bedad3 1967 struct netdev_hw_addr *ha;
9a799d71 1968 u32 i;
9a799d71
AK		 1969
1970 /*
1971 * Set the new number of MC addresses that we are being requested to
1972 * use.
1973 */
2853eb89 1974 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1975 hw->addr_ctrl.mta_in_use = 0;
1976
80960ab0 1977 /* Clear mta_shadow */
9a799d71 1978 hw_dbg(hw, " Clearing MTA\n");
80960ab0 1979 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 1980
80960ab0 1981 /* Update mta shadow */
22bedad3 1982 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1983 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1984 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1985 }
1986
1987 /* Enable mta */
80960ab0
ET		 1988 for (i = 0; i < hw->mac.mcft_size; i++)
1989 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1990 hw->mac.mta_shadow[i]);
1991
9a799d71
AK		 1992 if (hw->addr_ctrl.mta_in_use > 0)
1993 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
e7cf745b 1994 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1995
c44ade9e 1996 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1997 return 0;
1998}
1999
2000/**
c44ade9e 2001 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2002 * @hw: pointer to hardware structure
2003 *
c44ade9e 2004 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2005 **/
c44ade9e 2006s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2007{
c44ade9e 2008 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2009
c44ade9e
JB		 2010 if (a->mta_in_use > 0)
2011 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
e7cf745b 2012 hw->mac.mc_filter_type);
9a799d71
AK		 2013
2014 return 0;
2015}
2016
2017/**
c44ade9e 2018 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2019 * @hw: pointer to hardware structure
9a799d71 2020 *
c44ade9e 2021 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2022 **/
c44ade9e 2023s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2024{
c44ade9e 2025 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2026
c44ade9e
JB		 2027 if (a->mta_in_use > 0)
2028 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2029
2030 return 0;
2031}
2032
11afc1b1 2033/**
620fa036 2034 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2035 * @hw: pointer to hardware structure
11afc1b1
PW		 2036 *
2037 * Enable flow control according to the current settings.
2038 **/
041441d0 2039s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1 2040{
620fa036 2041 u32 mflcn_reg, fccfg_reg;
11afc1b1 2042 u32 reg;
16b61beb 2043 u32 fcrtl, fcrth;
041441d0 2044 int i;
70b77628 2045
e5776620 2046 /* Validate the water mark configuration. */
e90dd264
MR		 2047 if (!hw->fc.pause_time)
2048 return IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2049
e5776620
JK		 2050 /* Low water mark of zero causes XOFF floods */
2051 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2052 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2053 hw->fc.high_water[i]) {
2054 if (!hw->fc.low_water[i] ||
2055 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2056 hw_dbg(hw, "Invalid water mark configuration\n");
e90dd264 2057 return IXGBE_ERR_INVALID_LINK_SETTINGS;
e5776620
JK		 2058 }
2059 }
2060 }
2061
620fa036 2062 /* Negotiate the fc mode to use */
786e9a5f 2063 ixgbe_fc_autoneg(hw);
11afc1b1 2064
620fa036 2065 /* Disable any previous flow control settings */
11afc1b1 2066 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2067 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2068
2069 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2070 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2071
2072 /*
2073 * The possible values of fc.current_mode are:
2074 * 0: Flow control is completely disabled
2075 * 1: Rx flow control is enabled (we can receive pause frames,
2076 * but not send pause frames).
bb3daa4a
PW		 2077 * 2: Tx flow control is enabled (we can send pause frames but
2078 * we do not support receiving pause frames).
11afc1b1
PW		 2079 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2080 * other: Invalid.
2081 */
2082 switch (hw->fc.current_mode) {
2083 case ixgbe_fc_none:
620fa036
MC		 2084 /*
2085 * Flow control is disabled by software override or autoneg.
2086 * The code below will actually disable it in the HW.
2087 */
11afc1b1
PW		 2088 break;
2089 case ixgbe_fc_rx_pause:
2090 /*
2091 * Rx Flow control is enabled and Tx Flow control is
2092 * disabled by software override. Since there really
2093 * isn't a way to advertise that we are capable of RX
2094 * Pause ONLY, we will advertise that we support both
2095 * symmetric and asymmetric Rx PAUSE. Later, we will
2096 * disable the adapter's ability to send PAUSE frames.
2097 */
2098 mflcn_reg |= IXGBE_MFLCN_RFCE;
2099 break;
2100 case ixgbe_fc_tx_pause:
2101 /*
2102 * Tx Flow control is enabled, and Rx Flow control is
2103 * disabled by software override.
2104 */
2105 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2106 break;
2107 case ixgbe_fc_full:
2108 /* Flow control (both Rx and Tx) is enabled by SW override. */
2109 mflcn_reg |= IXGBE_MFLCN_RFCE;
2110 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2111 break;
2112 default:
2113 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 2114 return IXGBE_ERR_CONFIG;
11afc1b1
PW		 2115 }
2116
620fa036 2117 /* Set 802.3x based flow control settings. */
2132d381 2118 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2119 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2120 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2121
041441d0
AD		 2122 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2123 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2124 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2125 hw->fc.high_water[i]) {
e5776620 2126 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
041441d0
AD		 2127 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2128 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2129 } else {
2130 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2131 /*
2132 * In order to prevent Tx hangs when the internal Tx
2133 * switch is enabled we must set the high water mark
2134 * to the maximum FCRTH value. This allows the Tx
2135 * switch to function even under heavy Rx workloads.
2136 */
2137 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2138 }
11afc1b1 2139
041441d0
AD		 2140 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2141 }
16b61beb 2142
11afc1b1 2143 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2144 reg = hw->fc.pause_time * 0x00010001;
2145 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2146 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2147
2148 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1 2149
e90dd264 2150 return 0;
11afc1b1
PW		 2151}
2152
0ecc061d 2153/**
67a79df2 2154 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2155 * @hw: pointer to hardware structure
67a79df2
AD		 2156 * @adv_reg: flow control advertised settings
2157 * @lp_reg: link partner's flow control settings
2158 * @adv_sym: symmetric pause bit in advertisement
2159 * @adv_asm: asymmetric pause bit in advertisement
2160 * @lp_sym: symmetric pause bit in link partner advertisement
2161 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2162 *
67a79df2
AD		 2163 * Find the intersection between advertised settings and link partner's
2164 * advertised settings
0ecc061d 2165 **/
67a79df2
AD		 2166static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2167 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2168{
67a79df2
AD		 2169 if ((!(adv_reg)) || (!(lp_reg)))
2170 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2171
67a79df2
AD		 2172 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2173 /*
2174 * Now we need to check if the user selected Rx ONLY
2175 * of pause frames. In this case, we had to advertise
2176 * FULL flow control because we could not advertise RX
2177 * ONLY. Hence, we must now check to see if we need to
2178 * turn OFF the TRANSMISSION of PAUSE frames.
2179 */
2180 if (hw->fc.requested_mode == ixgbe_fc_full) {
2181 hw->fc.current_mode = ixgbe_fc_full;
2182 hw_dbg(hw, "Flow Control = FULL.\n");
2183 } else {
2184 hw->fc.current_mode = ixgbe_fc_rx_pause;
2185 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2186 }
2187 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2188 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2189 hw->fc.current_mode = ixgbe_fc_tx_pause;
2190 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2191 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2192 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2193 hw->fc.current_mode = ixgbe_fc_rx_pause;
2194 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2195 } else {
67a79df2
AD		 2196 hw->fc.current_mode = ixgbe_fc_none;
2197 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2198 }
67a79df2 2199 return 0;
0b0c2b31
ET		 2200}
2201
2202/**
2203 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2204 * @hw: pointer to hardware structure
2205 *
2206 * Enable flow control according on 1 gig fiber.
2207 **/
2208static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2209{
2210 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
e90dd264 2211 s32 ret_val;
539e5f02
PWJ		 2212
2213 /*
2214 * On multispeed fiber at 1g, bail out if
2215 * - link is up but AN did not complete, or if
2216 * - link is up and AN completed but timed out
2217 */
0b0c2b31
ET		 2218
2219 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2220 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2221 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
e90dd264 2222 return IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02 2223
0b0c2b31
ET		 2224 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2225 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2226
2227 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2228 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2229 IXGBE_PCS1GANA_ASM_PAUSE,
2230 IXGBE_PCS1GANA_SYM_PAUSE,
2231 IXGBE_PCS1GANA_ASM_PAUSE);
2232
0b0c2b31
ET		 2233 return ret_val;
2234}
2235
2236/**
2237 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2238 * @hw: pointer to hardware structure
2239 *
2240 * Enable flow control according to IEEE clause 37.
2241 **/
2242static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2243{
2244 u32 links2, anlp1_reg, autoc_reg, links;
e90dd264 2245 s32 ret_val;
0b0c2b31 2246
9bbe3a57 2247 /*
0b0c2b31
ET		 2248 * On backplane, bail out if
2249 * - backplane autoneg was not completed, or if
2250 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2251 */
0b0c2b31 2252 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2253 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
e90dd264 2254 return IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57 2255
0b0c2b31
ET		 2256 if (hw->mac.type == ixgbe_mac_82599EB) {
2257 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2258 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
e90dd264 2259 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2260 }
0ecc061d 2261 /*
0b0c2b31 2262 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2263 * local flow control settings accordingly
2264 */
0b0c2b31
ET		 2265 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2266 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2267
0b0c2b31
ET		 2268 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2269 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2270 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2271
0b0c2b31
ET		 2272 return ret_val;
2273}
2274
2275/**
2276 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2277 * @hw: pointer to hardware structure
2278 *
2279 * Enable flow control according to IEEE clause 37.
2280 **/
2281static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2282{
2283 u16 technology_ability_reg = 0;
2284 u16 lp_technology_ability_reg = 0;
2285
2286 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2287 MDIO_MMD_AN,
2288 &technology_ability_reg);
2289 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2290 MDIO_MMD_AN,
2291 &lp_technology_ability_reg);
2292
2293 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2294 (u32)lp_technology_ability_reg,
2295 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2296 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2297}
2298
2299/**
67a79df2 2300 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2301 * @hw: pointer to hardware structure
2302 *
67a79df2
AD		 2303 * Compares our advertised flow control capabilities to those advertised by
2304 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2305 **/
67a79df2 2306void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2307{
67a79df2
AD		 2308 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2309 ixgbe_link_speed speed;
2310 bool link_up;
11afc1b1
PW		 2311
2312 /*
67a79df2
AD		 2313 * AN should have completed when the cable was plugged in.
2314 * Look for reasons to bail out. Bail out if:
2315 * - FC autoneg is disabled, or if
2316 * - link is not up.
2317 *
2318 * Since we're being called from an LSC, link is already known to be up.
2319 * So use link_up_wait_to_complete=false.
11afc1b1 2320 */
67a79df2 2321 if (hw->fc.disable_fc_autoneg)
620fa036 2322 goto out;
11afc1b1 2323
67a79df2
AD		 2324 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2325 if (!link_up)
11afc1b1 2326 goto out;
0b0c2b31
ET		 2327
2328 switch (hw->phy.media_type) {
67a79df2 2329 /* Autoneg flow control on fiber adapters */
0b0c2b31 2330 case ixgbe_media_type_fiber:
67a79df2
AD		 2331 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2332 ret_val = ixgbe_fc_autoneg_fiber(hw);
2333 break;
2334
2335 /* Autoneg flow control on backplane adapters */
0b0c2b31 2336 case ixgbe_media_type_backplane:
67a79df2 2337 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2338 break;
2339
67a79df2 2340 /* Autoneg flow control on copper adapters */
0b0c2b31 2341 case ixgbe_media_type_copper:
73d80953 2342 if (ixgbe_device_supports_autoneg_fc(hw))
67a79df2 2343 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2344 break;
2345
2346 default:
620fa036 2347 break;
0b0c2b31 2348 }
539e5f02 2349
11afc1b1 2350out:
67a79df2
AD		 2351 if (ret_val == 0) {
2352 hw->fc.fc_was_autonegged = true;
2353 } else {
2354 hw->fc.fc_was_autonegged = false;
2355 hw->fc.current_mode = hw->fc.requested_mode;
2356 }
11afc1b1
PW		 2357}
2358
1f86c983
DS		 2359/**
2360 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2361 * @hw: pointer to hardware structure
2362 *
2363 * System-wide timeout range is encoded in PCIe Device Control2 register.
2364 *
2365 * Add 10% to specified maximum and return the number of times to poll for
2366 * completion timeout, in units of 100 microsec. Never return less than
2367 * 800 = 80 millisec.
2368 **/
2369static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2370{
1f86c983
DS		 2371 s16 devctl2;
2372 u32 pollcnt;
2373
0d7c6e00 2374 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
1f86c983
DS		 2375 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2376
2377 switch (devctl2) {
2378 case IXGBE_PCIDEVCTRL2_65_130ms:
2379 pollcnt = 1300; /* 130 millisec */
2380 break;
2381 case IXGBE_PCIDEVCTRL2_260_520ms:
2382 pollcnt = 5200; /* 520 millisec */
2383 break;
2384 case IXGBE_PCIDEVCTRL2_1_2s:
2385 pollcnt = 20000; /* 2 sec */
2386 break;
2387 case IXGBE_PCIDEVCTRL2_4_8s:
2388 pollcnt = 80000; /* 8 sec */
2389 break;
2390 case IXGBE_PCIDEVCTRL2_17_34s:
2391 pollcnt = 34000; /* 34 sec */
2392 break;
2393 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2394 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2395 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2396 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2397 default:
2398 pollcnt = 800; /* 80 millisec minimum */
2399 break;
2400 }
2401
2402 /* add 10% to spec maximum */
2403 return (pollcnt * 11) / 10;
2404}
2405
9a799d71
AK		 2406/**
2407 * ixgbe_disable_pcie_master - Disable PCI-express master access
2408 * @hw: pointer to hardware structure
2409 *
2410 * Disables PCI-Express master access and verifies there are no pending
2411 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2412 * bit hasn't caused the master requests to be disabled, else 0
2413 * is returned signifying master requests disabled.
2414 **/
ff9d1a5a 2415static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2416{
1f86c983 2417 u32 i, poll;
ff9d1a5a
ET		 2418 u16 value;
2419
2420 /* Always set this bit to ensure any future transactions are blocked */
2421 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2422
ff9d1a5a 2423 /* Exit if master requests are blocked */
14438464
MR		 2424 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2425 ixgbe_removed(hw->hw_addr))
e90dd264 2426 return 0;
9a799d71 2427
ff9d1a5a 2428 /* Poll for master request bit to clear */
9a799d71 2429 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2430 udelay(100);
ff9d1a5a 2431 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
e90dd264 2432 return 0;
a4297dc2
ET		 2433 }
2434
ff9d1a5a
ET		 2435 /*
2436 * Two consecutive resets are required via CTRL.RST per datasheet
2437 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2438 * of this need. The first reset prevents new master requests from
2439 * being issued by our device. We then must wait 1usec or more for any
2440 * remaining completions from the PCIe bus to trickle in, and then reset
2441 * again to clear out any effects they may have had on our device.
2442 */
a4297dc2 2443 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2444 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2445
2446 /*
2447 * Before proceeding, make sure that the PCIe block does not have
2448 * transactions pending.
2449 */
1f86c983
DS		 2450 poll = ixgbe_pcie_timeout_poll(hw);
2451 for (i = 0; i < poll; i++) {
9a799d71 2452 udelay(100);
14438464
MR		 2453 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2454 if (ixgbe_removed(hw->hw_addr))
e90dd264 2455 return 0;
ff9d1a5a 2456 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
e90dd264 2457 return 0;
9a799d71
AK		 2458 }
2459
ff9d1a5a 2460 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
e90dd264 2461 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
9a799d71
AK		 2462}
2463
9a799d71 2464/**
c44ade9e 2465 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2466 * @hw: pointer to hardware structure
c44ade9e 2467 * @mask: Mask to specify which semaphore to acquire
9a799d71 2468 *
da74cd4a 2469 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2470 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2471 **/
2472s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2473{
674c18b2 2474 u32 gssr = 0;
9a799d71
AK		 2475 u32 swmask = mask;
2476 u32 fwmask = mask << 5;
674c18b2
ET		 2477 u32 timeout = 200;
2478 u32 i;
9a799d71 2479
674c18b2 2480 for (i = 0; i < timeout; i++) {
dbf893ee 2481 /*
674c18b2
ET		 2482 * SW NVM semaphore bit is used for access to all
2483 * SW_FW_SYNC bits (not just NVM)
dbf893ee 2484 */
9a799d71 2485 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2486 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2487
2488 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
674c18b2
ET		 2489 if (!(gssr & (fwmask | swmask))) {
2490 gssr |= swmask;
2491 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2492 ixgbe_release_eeprom_semaphore(hw);
2493 return 0;
2494 } else {
2495 /* Resource is currently in use by FW or SW */
2496 ixgbe_release_eeprom_semaphore(hw);
2497 usleep_range(5000, 10000);
2498 }
9a799d71
AK		 2499 }
2500
674c18b2
ET		 2501 /* If time expired clear the bits holding the lock and retry */
2502 if (gssr & (fwmask | swmask))
2503 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
9a799d71 2504
674c18b2
ET		 2505 usleep_range(5000, 10000);
2506 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2507}
2508
2509/**
2510 * ixgbe_release_swfw_sync - Release SWFW semaphore
2511 * @hw: pointer to hardware structure
c44ade9e 2512 * @mask: Mask to specify which semaphore to release
9a799d71 2513 *
da74cd4a 2514 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2515 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2516 **/
2517void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2518{
2519 u32 gssr;
2520 u32 swmask = mask;
2521
2522 ixgbe_get_eeprom_semaphore(hw);
2523
2524 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2525 gssr &= ~swmask;
2526 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2527
2528 ixgbe_release_eeprom_semaphore(hw);
2529}
2530
429d6a3b
DS		 2531/**
2532 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2533 * @hw: pointer to hardware structure
2534 * @reg_val: Value we read from AUTOC
2535 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2536 * true in this the generic case.
2537 *
2538 * The default case requires no protection so just to the register read.
2539 **/
2540s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2541{
2542 *locked = false;
2543 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2544 return 0;
2545}
2546
2547/**
2548 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2549 * @hw: pointer to hardware structure
2550 * @reg_val: value to write to AUTOC
2551 * @locked: bool to indicate whether the SW/FW lock was already taken by
2552 * previous read.
2553 **/
2554s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2555{
2556 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2557 return 0;
2558}
2559
d2f5e7f3
AS		 2560/**
2561 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2562 * @hw: pointer to hardware structure
2563 *
2564 * Stops the receive data path and waits for the HW to internally
2565 * empty the Rx security block.
2566 **/
2567s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2568{
2569#define IXGBE_MAX_SECRX_POLL 40
2570 int i;
2571 int secrxreg;
2572
2573 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2574 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2575 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2576 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2577 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2578 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2579 break;
2580 else
2581 /* Use interrupt-safe sleep just in case */
db76ad47 2582 udelay(1000);
d2f5e7f3
AS		 2583 }
2584
2585 /* For informational purposes only */
2586 if (i >= IXGBE_MAX_SECRX_POLL)
6ec1b71f 2587 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
d2f5e7f3
AS		 2588
2589 return 0;
2590
2591}
2592
2593/**
2594 * ixgbe_enable_rx_buff - Enables the receive data path
2595 * @hw: pointer to hardware structure
2596 *
2597 * Enables the receive data path
2598 **/
2599s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2600{
2601 int secrxreg;
2602
2603 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2604 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2605 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2606 IXGBE_WRITE_FLUSH(hw);
2607
2608 return 0;
2609}
2610
11afc1b1
PW		 2611/**
2612 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2613 * @hw: pointer to hardware structure
2614 * @regval: register value to write to RXCTRL
2615 *
2616 * Enables the Rx DMA unit
2617 **/
2618s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2619{
2620 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2621
2622 return 0;
2623}
87c12017
PW		 2624
2625/**
2626 * ixgbe_blink_led_start_generic - Blink LED based on index.
2627 * @hw: pointer to hardware structure
2628 * @index: led number to blink
2629 **/
2630s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2631{
2632 ixgbe_link_speed speed = 0;
3db1cd5c 2633 bool link_up = false;
87c12017
PW		 2634 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2635 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2636 bool locked = false;
e90dd264 2637 s32 ret_val;
87c12017
PW		 2638
2639 /*
2640 * Link must be up to auto-blink the LEDs;
2641 * Force it if link is down.
2642 */
2643 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2644
2645 if (!link_up) {
429d6a3b 2646 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2647 if (ret_val)
e90dd264 2648 return ret_val;
d7bbcd32 2649
50ac58ba 2650 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2651 autoc_reg |= IXGBE_AUTOC_FLU;
429d6a3b
DS		 2652
2653 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2654 if (ret_val)
e90dd264 2655 return ret_val;
429d6a3b 2656
945a5151 2657 IXGBE_WRITE_FLUSH(hw);
d7bbcd32 2658
032b4325 2659 usleep_range(10000, 20000);
87c12017
PW		 2660 }
2661
2662 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2663 led_reg |= IXGBE_LED_BLINK(index);
2664 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2665 IXGBE_WRITE_FLUSH(hw);
2666
e90dd264 2667 return 0;
87c12017
PW		 2668}
2669
2670/**
2671 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2672 * @hw: pointer to hardware structure
2673 * @index: led number to stop blinking
2674 **/
2675s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2676{
429d6a3b 2677 u32 autoc_reg = 0;
87c12017 2678 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2679 bool locked = false;
e90dd264 2680 s32 ret_val;
d7bbcd32 2681
429d6a3b 2682 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2683 if (ret_val)
e90dd264 2684 return ret_val;
87c12017
PW		 2685
2686 autoc_reg &= ~IXGBE_AUTOC_FLU;
2687 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2688
429d6a3b 2689 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2690 if (ret_val)
e90dd264 2691 return ret_val;
d7bbcd32 2692
87c12017
PW		 2693 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2694 led_reg &= ~IXGBE_LED_BLINK(index);
2695 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2696 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2697 IXGBE_WRITE_FLUSH(hw);
2698
e90dd264 2699 return 0;
87c12017 2700}
21ce849b
MC		 2701
2702/**
2703 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2704 * @hw: pointer to hardware structure
2705 * @san_mac_offset: SAN MAC address offset
2706 *
2707 * This function will read the EEPROM location for the SAN MAC address
2708 * pointer, and returns the value at that location. This is used in both
2709 * get and set mac_addr routines.
2710 **/
2711static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
e7cf745b 2712 u16 *san_mac_offset)
21ce849b 2713{
be0c27b4
MR		 2714 s32 ret_val;
2715
21ce849b
MC		 2716 /*
2717 * First read the EEPROM pointer to see if the MAC addresses are
2718 * available.
2719 */
be0c27b4
MR		 2720 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2721 san_mac_offset);
2722 if (ret_val)
2723 hw_err(hw, "eeprom read at offset %d failed\n",
2724 IXGBE_SAN_MAC_ADDR_PTR);
21ce849b 2725
be0c27b4 2726 return ret_val;
21ce849b
MC		 2727}
2728
2729/**
2730 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2731 * @hw: pointer to hardware structure
2732 * @san_mac_addr: SAN MAC address
2733 *
2734 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2735 * per-port, so set_lan_id() must be called before reading the addresses.
2736 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2737 * upon for non-SFP connections, so we must call it here.
2738 **/
2739s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2740{
2741 u16 san_mac_data, san_mac_offset;
2742 u8 i;
be0c27b4 2743 s32 ret_val;
21ce849b
MC		 2744
2745 /*
2746 * First read the EEPROM pointer to see if the MAC addresses are
2747 * available. If they're not, no point in calling set_lan_id() here.
2748 */
be0c27b4
MR		 2749 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2750 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
21ce849b 2751
be0c27b4 2752 goto san_mac_addr_clr;
21ce849b
MC		 2753
2754 /* make sure we know which port we need to program */
2755 hw->mac.ops.set_lan_id(hw);
2756 /* apply the port offset to the address offset */
2757 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
e7cf745b 2758 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
21ce849b 2759 for (i = 0; i < 3; i++) {
be0c27b4
MR		 2760 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2761 &san_mac_data);
2762 if (ret_val) {
2763 hw_err(hw, "eeprom read at offset %d failed\n",
2764 san_mac_offset);
2765 goto san_mac_addr_clr;
2766 }
21ce849b
MC		 2767 san_mac_addr[i * 2] = (u8)(san_mac_data);
2768 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2769 san_mac_offset++;
2770 }
21ce849b 2771 return 0;
be0c27b4
MR		 2772
2773san_mac_addr_clr:
2774 /* No addresses available in this EEPROM. It's not necessarily an
2775 * error though, so just wipe the local address and return.
2776 */
2777 for (i = 0; i < 6; i++)
2778 san_mac_addr[i] = 0xFF;
2779 return ret_val;
21ce849b
MC		 2780}
2781
2782/**
2783 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2784 * @hw: pointer to hardware structure
2785 *
2786 * Read PCIe configuration space, and get the MSI-X vector count from
2787 * the capabilities table.
2788 **/
71161302 2789u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b 2790{
e90dd264 2791 u16 msix_count;
71161302
ET		 2792 u16 max_msix_count;
2793 u16 pcie_offset;
2794
2795 switch (hw->mac.type) {
2796 case ixgbe_mac_82598EB:
2797 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2798 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2799 break;
2800 case ixgbe_mac_82599EB:
2801 case ixgbe_mac_X540:
9a75a1ac
DS		 2802 case ixgbe_mac_X550:
2803 case ixgbe_mac_X550EM_x:
71161302
ET		 2804 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2805 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2806 break;
2807 default:
e90dd264 2808 return 1;
71161302
ET		 2809 }
2810
14438464
MR		 2811 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2812 if (ixgbe_removed(hw->hw_addr))
2813 msix_count = 0;
21ce849b
MC		 2814 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2815
71161302 2816 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2817 msix_count++;
2818
71161302
ET		 2819 if (msix_count > max_msix_count)
2820 msix_count = max_msix_count;
2821
21ce849b
MC		 2822 return msix_count;
2823}
2824
2825/**
2826 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2827 * @hw: pointer to hardware struct
2828 * @rar: receive address register index to disassociate
2829 * @vmdq: VMDq pool index to remove from the rar
2830 **/
2831s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2832{
2833 u32 mpsar_lo, mpsar_hi;
2834 u32 rar_entries = hw->mac.num_rar_entries;
2835
c700f4e6
ET		 2836 /* Make sure we are using a valid rar index range */
2837 if (rar >= rar_entries) {
2838 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2839 return IXGBE_ERR_INVALID_ARGUMENT;
2840 }
21ce849b 2841
c700f4e6
ET		 2842 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2843 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2844
19458bd4 2845 if (ixgbe_removed(hw->hw_addr))
e90dd264 2846 return 0;
19458bd4 2847
c700f4e6 2848 if (!mpsar_lo && !mpsar_hi)
e90dd264 2849 return 0;
21ce849b 2850
c700f4e6
ET		 2851 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2852 if (mpsar_lo) {
2853 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2854 mpsar_lo = 0;
2855 }
2856 if (mpsar_hi) {
2857 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2858 mpsar_hi = 0;
2859 }
2860 } else if (vmdq < 32) {
2861 mpsar_lo &= ~(1 << vmdq);
2862 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2863 } else {
c700f4e6
ET		 2864 mpsar_hi &= ~(1 << (vmdq - 32));
2865 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2866 }
2867
c700f4e6
ET		 2868 /* was that the last pool using this rar? */
2869 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2870 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2871 return 0;
2872}
2873
2874/**
2875 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2876 * @hw: pointer to hardware struct
2877 * @rar: receive address register index to associate with a VMDq index
2878 * @vmdq: VMDq pool index
2879 **/
2880s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2881{
2882 u32 mpsar;
2883 u32 rar_entries = hw->mac.num_rar_entries;
2884
c700f4e6
ET		 2885 /* Make sure we are using a valid rar index range */
2886 if (rar >= rar_entries) {
21ce849b 2887 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2888 return IXGBE_ERR_INVALID_ARGUMENT;
2889 }
2890
2891 if (vmdq < 32) {
2892 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2893 mpsar |= 1 << vmdq;
2894 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2895 } else {
2896 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2897 mpsar |= 1 << (vmdq - 32);
2898 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2899 }
2900 return 0;
2901}
2902
7fa7c9dc
AD		 2903/**
2904 * This function should only be involved in the IOV mode.
2905 * In IOV mode, Default pool is next pool after the number of
2906 * VFs advertized and not 0.
2907 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2908 *
2909 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2910 * @hw: pointer to hardware struct
2911 * @vmdq: VMDq pool index
2912 **/
2913s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2914{
2915 u32 rar = hw->mac.san_mac_rar_index;
2916
2917 if (vmdq < 32) {
2918 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2919 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2920 } else {
2921 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2922 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2923 }
2924
2925 return 0;
2926}
2927
21ce849b
MC		 2928/**
2929 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2930 * @hw: pointer to hardware structure
2931 **/
2932s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2933{
2934 int i;
2935
21ce849b
MC		 2936 for (i = 0; i < 128; i++)
2937 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2938
2939 return 0;
2940}
2941
2942/**
2943 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2944 * @hw: pointer to hardware structure
2945 * @vlan: VLAN id to write to VLAN filter
2946 *
2947 * return the VLVF index where this VLAN id should be placed
2948 *
2949 **/
5d5b7c39 2950static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2951{
2952 u32 bits = 0;
2953 u32 first_empty_slot = 0;
2954 s32 regindex;
2955
2956 /* short cut the special case */
2957 if (vlan == 0)
2958 return 0;
2959
2960 /*
2961 * Search for the vlan id in the VLVF entries. Save off the first empty
2962 * slot found along the way
2963 */
2964 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2965 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2966 if (!bits && !(first_empty_slot))
2967 first_empty_slot = regindex;
2968 else if ((bits & 0x0FFF) == vlan)
2969 break;
2970 }
2971
2972 /*
2973 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2974 * in the VLVF. Else use the first empty VLVF register for this
2975 * vlan id.
2976 */
2977 if (regindex >= IXGBE_VLVF_ENTRIES) {
2978 if (first_empty_slot)
2979 regindex = first_empty_slot;
2980 else {
2981 hw_dbg(hw, "No space in VLVF.\n");
2982 regindex = IXGBE_ERR_NO_SPACE;
2983 }
2984 }
2985
2986 return regindex;
2987}
2988
2989/**
2990 * ixgbe_set_vfta_generic - Set VLAN filter table
2991 * @hw: pointer to hardware structure
2992 * @vlan: VLAN id to write to VLAN filter
2993 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2994 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2995 *
2996 * Turn on/off specified VLAN in the VLAN filter table.
2997 **/
2998s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
e7cf745b 2999 bool vlan_on)
21ce849b
MC		 3000{
3001 s32 regindex;
3002 u32 bitindex;
3003 u32 vfta;
3004 u32 bits;
3005 u32 vt;
3006 u32 targetbit;
3007 bool vfta_changed = false;
3008
3009 if (vlan > 4095)
3010 return IXGBE_ERR_PARAM;
3011
3012 /*
3013 * this is a 2 part operation - first the VFTA, then the
3014 * VLVF and VLVFB if VT Mode is set
3015 * We don't write the VFTA until we know the VLVF part succeeded.
3016 */
3017
3018 /* Part 1
3019 * The VFTA is a bitstring made up of 128 32-bit registers
3020 * that enable the particular VLAN id, much like the MTA:
3021 * bits[11-5]: which register
3022 * bits[4-0]: which bit in the register
3023 */
3024 regindex = (vlan >> 5) & 0x7F;
3025 bitindex = vlan & 0x1F;
3026 targetbit = (1 << bitindex);
3027 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3028
3029 if (vlan_on) {
3030 if (!(vfta & targetbit)) {
3031 vfta |= targetbit;
3032 vfta_changed = true;
3033 }
3034 } else {
3035 if ((vfta & targetbit)) {
3036 vfta &= ~targetbit;
3037 vfta_changed = true;
3038 }
3039 }
3040
3041 /* Part 2
3042 * If VT Mode is set
3043 * Either vlan_on
3044 * make sure the vlan is in VLVF
3045 * set the vind bit in the matching VLVFB
3046 * Or !vlan_on
3047 * clear the pool bit and possibly the vind
3048 */
3049 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3050 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3051 s32 vlvf_index;
3052
3053 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3054 if (vlvf_index < 0)
3055 return vlvf_index;
3056
3057 if (vlan_on) {
3058 /* set the pool bit */
3059 if (vind < 32) {
3060 bits = IXGBE_READ_REG(hw,
3061 IXGBE_VLVFB(vlvf_index*2));
3062 bits |= (1 << vind);
3063 IXGBE_WRITE_REG(hw,
3064 IXGBE_VLVFB(vlvf_index*2),
3065 bits);
3066 } else {
3067 bits = IXGBE_READ_REG(hw,
3068 IXGBE_VLVFB((vlvf_index*2)+1));
3069 bits |= (1 << (vind-32));
3070 IXGBE_WRITE_REG(hw,
3071 IXGBE_VLVFB((vlvf_index*2)+1),
3072 bits);
3073 }
3074 } else {
3075 /* clear the pool bit */
3076 if (vind < 32) {
3077 bits = IXGBE_READ_REG(hw,
3078 IXGBE_VLVFB(vlvf_index*2));
3079 bits &= ~(1 << vind);
3080 IXGBE_WRITE_REG(hw,
3081 IXGBE_VLVFB(vlvf_index*2),
3082 bits);
3083 bits |= IXGBE_READ_REG(hw,
3084 IXGBE_VLVFB((vlvf_index*2)+1));
3085 } else {
3086 bits = IXGBE_READ_REG(hw,
3087 IXGBE_VLVFB((vlvf_index*2)+1));
3088 bits &= ~(1 << (vind-32));
3089 IXGBE_WRITE_REG(hw,
3090 IXGBE_VLVFB((vlvf_index*2)+1),
3091 bits);
3092 bits |= IXGBE_READ_REG(hw,
3093 IXGBE_VLVFB(vlvf_index*2));
3094 }
3095 }
3096
3097 /*
3098 * If there are still bits set in the VLVFB registers
3099 * for the VLAN ID indicated we need to see if the
3100 * caller is requesting that we clear the VFTA entry bit.
3101 * If the caller has requested that we clear the VFTA
3102 * entry bit but there are still pools/VFs using this VLAN
3103 * ID entry then ignore the request. We're not worried
3104 * about the case where we're turning the VFTA VLAN ID
3105 * entry bit on, only when requested to turn it off as
3106 * there may be multiple pools and/or VFs using the
3107 * VLAN ID entry. In that case we cannot clear the
3108 * VFTA bit until all pools/VFs using that VLAN ID have also
3109 * been cleared. This will be indicated by "bits" being
3110 * zero.
3111 */
3112 if (bits) {
3113 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3114 (IXGBE_VLVF_VIEN | vlan));
3115 if (!vlan_on) {
3116 /* someone wants to clear the vfta entry
3117 * but some pools/VFs are still using it.
3118 * Ignore it. */
3119 vfta_changed = false;
3120 }
63b64de3 3121 } else {
21ce849b 3122 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
63b64de3 3123 }
21ce849b
MC		 3124 }
3125
3126 if (vfta_changed)
3127 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3128
3129 return 0;
3130}
3131
3132/**
3133 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3134 * @hw: pointer to hardware structure
3135 *
3136 * Clears the VLAN filer table, and the VMDq index associated with the filter
3137 **/
3138s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3139{
3140 u32 offset;
3141
3142 for (offset = 0; offset < hw->mac.vft_size; offset++)
3143 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3144
3145 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3146 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3147 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3148 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3149 }
3150
3151 return 0;
3152}
3153
3154/**
3155 * ixgbe_check_mac_link_generic - Determine link and speed status
3156 * @hw: pointer to hardware structure
3157 * @speed: pointer to link speed
3158 * @link_up: true when link is up
3159 * @link_up_wait_to_complete: bool used to wait for link up or not
3160 *
3161 * Reads the links register to determine if link is up and the current speed
3162 **/
3163s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3164 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3165{
48de36c5 3166 u32 links_reg, links_orig;
21ce849b
MC		 3167 u32 i;
3168
48de36c5
ET		 3169 /* clear the old state */
3170 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3171
21ce849b 3172 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3173
3174 if (links_orig != links_reg) {
3175 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3176 links_orig, links_reg);
3177 }
3178
21ce849b
MC		 3179 if (link_up_wait_to_complete) {
3180 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3181 if (links_reg & IXGBE_LINKS_UP) {
3182 *link_up = true;
3183 break;
3184 } else {
3185 *link_up = false;
3186 }
3187 msleep(100);
3188 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3189 }
3190 } else {
3191 if (links_reg & IXGBE_LINKS_UP)
3192 *link_up = true;
3193 else
3194 *link_up = false;
3195 }
3196
9a75a1ac
DS		 3197 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3198 case IXGBE_LINKS_SPEED_10G_82599:
3199 if ((hw->mac.type >= ixgbe_mac_X550) &&
3200 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3201 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3202 else
3203 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3204 break;
3205 case IXGBE_LINKS_SPEED_1G_82599:
21ce849b 3206 *speed = IXGBE_LINK_SPEED_1GB_FULL;
9a75a1ac
DS		 3207 break;
3208 case IXGBE_LINKS_SPEED_100_82599:
3209 if ((hw->mac.type >= ixgbe_mac_X550) &&
3210 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3211 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3212 else
3213 *speed = IXGBE_LINK_SPEED_100_FULL;
3214 break;
3215 default:
63d778df 3216 *speed = IXGBE_LINK_SPEED_UNKNOWN;
9a75a1ac 3217 }
21ce849b 3218
21ce849b
MC		 3219 return 0;
3220}
a391f1d5
DS		 3221
3222/**
49ce9c2c 3223 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3224 * the EEPROM
3225 * @hw: pointer to hardware structure
3226 * @wwnn_prefix: the alternative WWNN prefix
3227 * @wwpn_prefix: the alternative WWPN prefix
3228 *
3229 * This function will read the EEPROM from the alternative SAN MAC address
3230 * block to check the support for the alternative WWNN/WWPN prefix support.
3231 **/
3232s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 3233 u16 *wwpn_prefix)
a391f1d5
DS		 3234{
3235 u16 offset, caps;
3236 u16 alt_san_mac_blk_offset;
3237
3238 /* clear output first */
3239 *wwnn_prefix = 0xFFFF;
3240 *wwpn_prefix = 0xFFFF;
3241
3242 /* check if alternative SAN MAC is supported */
be0c27b4
MR		 3243 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3244 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3245 goto wwn_prefix_err;
a391f1d5
DS		 3246
3247 if ((alt_san_mac_blk_offset == 0) ||
3248 (alt_san_mac_blk_offset == 0xFFFF))
e90dd264 3249 return 0;
a391f1d5
DS		 3250
3251 /* check capability in alternative san mac address block */
3252 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
be0c27b4
MR		 3253 if (hw->eeprom.ops.read(hw, offset, &caps))
3254 goto wwn_prefix_err;
a391f1d5 3255 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
e90dd264 3256 return 0;
a391f1d5
DS		 3257
3258 /* get the corresponding prefix for WWNN/WWPN */
3259 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
be0c27b4
MR		 3260 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3261 hw_err(hw, "eeprom read at offset %d failed\n", offset);
a391f1d5
DS		 3262
3263 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
be0c27b4
MR		 3264 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3265 goto wwn_prefix_err;
a391f1d5 3266
a391f1d5 3267 return 0;
be0c27b4
MR		 3268
3269wwn_prefix_err:
3270 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3271 return 0;
a391f1d5 3272}
a985b6c3
GR		 3273
3274/**
3275 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3276 * @hw: pointer to hardware structure
3277 * @enable: enable or disable switch for anti-spoofing
3278 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3279 *
3280 **/
3281void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3282{
3283 int j;
3284 int pf_target_reg = pf >> 3;
3285 int pf_target_shift = pf % 8;
3286 u32 pfvfspoof = 0;
3287
3288 if (hw->mac.type == ixgbe_mac_82598EB)
3289 return;
3290
3291 if (enable)
3292 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3293
3294 /*
3295 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3296 * MAC anti-spoof enables in each register array element.
3297 */
ef89e0a2 3298 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3299 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3300
a985b6c3
GR		 3301 /*
3302 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3303 * emulation mode NICs. Do not set the bits assigned to the PF
3304 */
3305 pfvfspoof &= (1 << pf_target_shift) - 1;
3306 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3307
3308 /*
3309 * Remaining pools belong to the PF so they do not need to have
3310 * anti-spoofing enabled.
a985b6c3 3311 */
ef89e0a2
AD		 3312 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3313 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3314}
3315
3316/**
3317 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3318 * @hw: pointer to hardware structure
3319 * @enable: enable or disable switch for VLAN anti-spoofing
3320 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3321 *
3322 **/
3323void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3324{
3325 int vf_target_reg = vf >> 3;
3326 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3327 u32 pfvfspoof;
3328
3329 if (hw->mac.type == ixgbe_mac_82598EB)
3330 return;
3331
3332 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3333 if (enable)
3334 pfvfspoof |= (1 << vf_target_shift);
3335 else
3336 pfvfspoof &= ~(1 << vf_target_shift);
3337 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3338}
b776d104
ET		 3339
3340/**
3341 * ixgbe_get_device_caps_generic - Get additional device capabilities
3342 * @hw: pointer to hardware structure
3343 * @device_caps: the EEPROM word with the extra device capabilities
3344 *
3345 * This function will read the EEPROM location for the device capabilities,
3346 * and return the word through device_caps.
3347 **/
3348s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3349{
3350 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3351
3352 return 0;
3353}
80605c65
JF		 3354
3355/**
3356 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3357 * @hw: pointer to hardware structure
3358 * @num_pb: number of packet buffers to allocate
3359 * @headroom: reserve n KB of headroom
3360 * @strategy: packet buffer allocation strategy
3361 **/
3362void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3363 int num_pb,
3364 u32 headroom,
3365 int strategy)
3366{
3367 u32 pbsize = hw->mac.rx_pb_size;
3368 int i = 0;
3369 u32 rxpktsize, txpktsize, txpbthresh;
3370
3371 /* Reserve headroom */
3372 pbsize -= headroom;
3373
3374 if (!num_pb)
3375 num_pb = 1;
3376
3377 /* Divide remaining packet buffer space amongst the number
3378 * of packet buffers requested using supplied strategy.
3379 */
3380 switch (strategy) {
3381 case (PBA_STRATEGY_WEIGHTED):
3382 /* pba_80_48 strategy weight first half of packet buffer with
3383 * 5/8 of the packet buffer space.
3384 */
3385 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3386 pbsize -= rxpktsize * (num_pb / 2);
3387 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3388 for (; i < (num_pb / 2); i++)
3389 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3390 /* Fall through to configure remaining packet buffers */
3391 case (PBA_STRATEGY_EQUAL):
3392 /* Divide the remaining Rx packet buffer evenly among the TCs */
3393 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3394 for (; i < num_pb; i++)
3395 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3396 break;
3397 default:
3398 break;
3399 }
3400
3401 /*
3402 * Setup Tx packet buffer and threshold equally for all TCs
3403 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3404 * 10 since the largest packet we support is just over 9K.
3405 */
3406 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3407 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3408 for (i = 0; i < num_pb; i++) {
3409 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3410 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3411 }
3412
3413 /* Clear unused TCs, if any, to zero buffer size*/
3414 for (; i < IXGBE_MAX_PB; i++) {
3415 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3416 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3417 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3418 }
3419}
9612de92
ET		 3420
3421/**
3422 * ixgbe_calculate_checksum - Calculate checksum for buffer
3423 * @buffer: pointer to EEPROM
3424 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3425 *
9612de92
ET		 3426 * Calculates the checksum for some buffer on a specified length. The
3427 * checksum calculated is returned.
3428 **/
3429static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3430{
3431 u32 i;
3432 u8 sum = 0;
3433
3434 if (!buffer)
3435 return 0;
3436
3437 for (i = 0; i < length; i++)
3438 sum += buffer[i];
3439
3440 return (u8) (0 - sum);
3441}
3442
3443/**
3444 * ixgbe_host_interface_command - Issue command to manageability block
3445 * @hw: pointer to the HW structure
3446 * @buffer: contains the command to write and where the return status will
3447 * be placed
c466d7a7 3448 * @length: length of buffer, must be multiple of 4 bytes
b48e4aa3
DS		 3449 * @timeout: time in ms to wait for command completion
3450 * @return_data: read and return data from the buffer (true) or not (false)
3451 * Needed because FW structures are big endian and decoding of
3452 * these fields can be 8 bit or 16 bit based on command. Decoding
3453 * is not easily understood without making a table of commands.
3454 * So we will leave this up to the caller to read back the data
3455 * in these cases.
9612de92
ET		 3456 *
3457 * Communicates with the manageability block. On success return 0
3458 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3459 **/
79488c58 3460static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
b48e4aa3
DS		 3461 u32 length, u32 timeout,
3462 bool return_data)
9612de92 3463{
b48e4aa3 3464 u32 hicr, i, bi, fwsts;
9612de92 3465 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
b48e4aa3 3466 u16 buf_len, dword_len;
9612de92 3467
b48e4aa3
DS		 3468 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3469 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
e90dd264 3470 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3471 }
3472
b48e4aa3
DS		 3473 /* Set bit 9 of FWSTS clearing FW reset indication */
3474 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3475 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3476
9612de92
ET		 3477 /* Check that the host interface is enabled. */
3478 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3479 if ((hicr & IXGBE_HICR_EN) == 0) {
3480 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
e90dd264 3481 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3482 }
3483
b48e4aa3
DS		 3484 /* Calculate length in DWORDs. We must be DWORD aligned */
3485 if ((length % (sizeof(u32))) != 0) {
3486 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3487 return IXGBE_ERR_INVALID_ARGUMENT;
3488 }
3489
9612de92
ET		 3490 dword_len = length >> 2;
3491
3492 /*
3493 * The device driver writes the relevant command block
3494 * into the ram area.
3495 */
3496 for (i = 0; i < dword_len; i++)
3497 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3498 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3499
3500 /* Setting this bit tells the ARC that a new command is pending. */
3501 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3502
b48e4aa3 3503 for (i = 0; i < timeout; i++) {
9612de92
ET		 3504 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3505 if (!(hicr & IXGBE_HICR_C))
3506 break;
3507 usleep_range(1000, 2000);
3508 }
3509
3510 /* Check command successful completion. */
b48e4aa3 3511 if ((timeout != 0 && i == timeout) ||
9612de92
ET		 3512 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3513 hw_dbg(hw, "Command has failed with no status valid.\n");
e90dd264 3514 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3515 }
3516
b48e4aa3
DS		 3517 if (!return_data)
3518 return 0;
3519
9612de92
ET		 3520 /* Calculate length in DWORDs */
3521 dword_len = hdr_size >> 2;
3522
3523 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3524 for (bi = 0; bi < dword_len; bi++) {
3525 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3526 le32_to_cpus(&buffer[bi]);
79488c58 3527 }
9612de92
ET		 3528
3529 /* If there is any thing in data position pull it in */
3530 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3531 if (buf_len == 0)
e90dd264 3532 return 0;
9612de92
ET		 3533
3534 if (length < (buf_len + hdr_size)) {
3535 hw_dbg(hw, "Buffer not large enough for reply message.\n");
e90dd264 3536 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3537 }
3538
331bcf45
ET		 3539 /* Calculate length in DWORDs, add 3 for odd lengths */
3540 dword_len = (buf_len + 3) >> 2;
9612de92 3541
331bcf45
ET		 3542 /* Pull in the rest of the buffer (bi is where we left off)*/
3543 for (; bi <= dword_len; bi++) {
3544 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3545 le32_to_cpus(&buffer[bi]);
3546 }
9612de92 3547
e90dd264 3548 return 0;
9612de92
ET		 3549}
3550
3551/**
3552 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3553 * @hw: pointer to the HW structure
3554 * @maj: driver version major number
3555 * @min: driver version minor number
3556 * @build: driver version build number
3557 * @sub: driver version sub build number
3558 *
3559 * Sends driver version number to firmware through the manageability
3560 * block. On success return 0
3561 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3562 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3563 **/
3564s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3565 u8 build, u8 sub)
3566{
3567 struct ixgbe_hic_drv_info fw_cmd;
3568 int i;
e90dd264 3569 s32 ret_val;
9612de92 3570
e90dd264
MR		 3571 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
3572 return IXGBE_ERR_SWFW_SYNC;
9612de92
ET		 3573
3574 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3575 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3576 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3577 fw_cmd.port_num = (u8)hw->bus.func;
3578 fw_cmd.ver_maj = maj;
3579 fw_cmd.ver_min = min;
3580 fw_cmd.ver_build = build;
3581 fw_cmd.ver_sub = sub;
3582 fw_cmd.hdr.checksum = 0;
3583 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3584 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3585 fw_cmd.pad = 0;
3586 fw_cmd.pad2 = 0;
3587
3588 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3589 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
b48e4aa3
DS		 3590 sizeof(fw_cmd),
3591 IXGBE_HI_COMMAND_TIMEOUT,
3592 true);
9612de92
ET		 3593 if (ret_val != 0)
3594 continue;
3595
3596 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3597 FW_CEM_RESP_STATUS_SUCCESS)
3598 ret_val = 0;
3599 else
3600 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3601
3602 break;
3603 }
3604
3605 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
9612de92
ET		 3606 return ret_val;
3607}
ff9d1a5a
ET		 3608
3609/**
3610 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3611 * @hw: pointer to the hardware structure
3612 *
3613 * The 82599 and x540 MACs can experience issues if TX work is still pending
3614 * when a reset occurs. This function prevents this by flushing the PCIe
3615 * buffers on the system.
3616 **/
3617void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3618{
71bde601
DS		 3619 u32 gcr_ext, hlreg0, i, poll;
3620 u16 value;
ff9d1a5a
ET		 3621
3622 /*
3623 * If double reset is not requested then all transactions should
3624 * already be clear and as such there is no work to do
3625 */
3626 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3627 return;
3628
3629 /*
3630 * Set loopback enable to prevent any transmits from being sent
3631 * should the link come up. This assumes that the RXCTRL.RXEN bit
3632 * has already been cleared.
3633 */
3634 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3635 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3636
71bde601
DS		 3637 /* wait for a last completion before clearing buffers */
3638 IXGBE_WRITE_FLUSH(hw);
3639 usleep_range(3000, 6000);
3640
3641 /* Before proceeding, make sure that the PCIe block does not have
3642 * transactions pending.
3643 */
3644 poll = ixgbe_pcie_timeout_poll(hw);
3645 for (i = 0; i < poll; i++) {
3646 usleep_range(100, 200);
3647 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3648 if (ixgbe_removed(hw->hw_addr))
3649 break;
3650 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3651 break;
3652 }
3653
ff9d1a5a
ET		 3654 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3655 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3656 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3657 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3658
3659 /* Flush all writes and allow 20usec for all transactions to clear */
3660 IXGBE_WRITE_FLUSH(hw);
3661 udelay(20);
3662
3663 /* restore previous register values */
3664 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3665 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3666}
e1ea9158
DS		 3667
3668static const u8 ixgbe_emc_temp_data[4] = {
3669 IXGBE_EMC_INTERNAL_DATA,
3670 IXGBE_EMC_DIODE1_DATA,
3671 IXGBE_EMC_DIODE2_DATA,
3672 IXGBE_EMC_DIODE3_DATA
3673};
3674static const u8 ixgbe_emc_therm_limit[4] = {
3675 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3676 IXGBE_EMC_DIODE1_THERM_LIMIT,
3677 IXGBE_EMC_DIODE2_THERM_LIMIT,
3678 IXGBE_EMC_DIODE3_THERM_LIMIT
3679};
3680
3681/**
3682 * ixgbe_get_ets_data - Extracts the ETS bit data
3683 * @hw: pointer to hardware structure
3684 * @ets_cfg: extected ETS data
3685 * @ets_offset: offset of ETS data
3686 *
3687 * Returns error code.
3688 **/
3689static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3690 u16 *ets_offset)
3691{
e90dd264 3692 s32 status;
e1ea9158
DS		 3693
3694 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3695 if (status)
e90dd264 3696 return status;
e1ea9158 3697
e90dd264
MR		 3698 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3699 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3700
3701 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3702 if (status)
e90dd264 3703 return status;
e1ea9158 3704
e90dd264
MR		 3705 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3706 return IXGBE_NOT_IMPLEMENTED;
e1ea9158 3707
e90dd264 3708 return 0;
e1ea9158
DS		 3709}
3710
3711/**
3712 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3713 * @hw: pointer to hardware structure
3714 *
3715 * Returns the thermal sensor data structure
3716 **/
3717s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3718{
e90dd264 3719 s32 status;
e1ea9158
DS		 3720 u16 ets_offset;
3721 u16 ets_cfg;
3722 u16 ets_sensor;
3723 u8 num_sensors;
3724 u8 i;
3725 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3726
3ca8bc6d 3727 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3728 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3729 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3730
3731 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3732 if (status)
e90dd264 3733 return status;
e1ea9158
DS		 3734
3735 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3736 if (num_sensors > IXGBE_MAX_SENSORS)
3737 num_sensors = IXGBE_MAX_SENSORS;
3738
3739 for (i = 0; i < num_sensors; i++) {
3740 u8 sensor_index;
3741 u8 sensor_location;
3742
3743 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3744 &ets_sensor);
3745 if (status)
e90dd264 3746 return status;
e1ea9158
DS		 3747
3748 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3749 IXGBE_ETS_DATA_INDEX_SHIFT);
3750 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3751 IXGBE_ETS_DATA_LOC_SHIFT);
3752
3753 if (sensor_location != 0) {
3754 status = hw->phy.ops.read_i2c_byte(hw,
3755 ixgbe_emc_temp_data[sensor_index],
3756 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3757 &data->sensor[i].temp);
3758 if (status)
e90dd264 3759 return status;
e1ea9158
DS		 3760 }
3761 }
e90dd264
MR		 3762
3763 return 0;
e1ea9158
DS		 3764}
3765
3766/**
3767 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3768 * @hw: pointer to hardware structure
3769 *
3770 * Inits the thermal sensor thresholds according to the NVM map
3771 * and save off the threshold and location values into mac.thermal_sensor_data
3772 **/
3773s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3774{
e90dd264 3775 s32 status;
e1ea9158
DS		 3776 u16 ets_offset;
3777 u16 ets_cfg;
3778 u16 ets_sensor;
3779 u8 low_thresh_delta;
3780 u8 num_sensors;
3781 u8 therm_limit;
3782 u8 i;
3783 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3784
3785 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3786
3ca8bc6d 3787 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3788 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3789 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3790
3791 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3792 if (status)
e90dd264 3793 return status;
e1ea9158
DS		 3794
3795 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3796 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3797 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3798 if (num_sensors > IXGBE_MAX_SENSORS)
3799 num_sensors = IXGBE_MAX_SENSORS;
3800
3801 for (i = 0; i < num_sensors; i++) {
3802 u8 sensor_index;
3803 u8 sensor_location;
3804
be0c27b4
MR		 3805 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3806 hw_err(hw, "eeprom read at offset %d failed\n",
3807 ets_offset + 1 + i);
3808 continue;
3809 }
e1ea9158
DS		 3810 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3811 IXGBE_ETS_DATA_INDEX_SHIFT);
3812 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3813 IXGBE_ETS_DATA_LOC_SHIFT);
3814 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3815
3816 hw->phy.ops.write_i2c_byte(hw,
3817 ixgbe_emc_therm_limit[sensor_index],
3818 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3819
3820 if (sensor_location == 0)
3821 continue;
3822
3823 data->sensor[i].location = sensor_location;
3824 data->sensor[i].caution_thresh = therm_limit;
3825 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3826 }
e90dd264
MR		 3827
3828 return 0;
e1ea9158
DS		 3829}
3830
Linux kernel - Deliverables
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