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net: fix some compiler warning in net/core/neighbour.c
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 50static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 51static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
52 u16 words, u16 *data);
53static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
56 u16 offset);
ff9d1a5a 57static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 58
67a79df2
AD		 59/**
60 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
61 * control
62 * @hw: pointer to hardware structure
63 *
64 * There are several phys that do not support autoneg flow control. This
65 * function check the device id to see if the associated phy supports
66 * autoneg flow control.
67 **/
db2adc2d 68s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2
AD		 69{
70
71 switch (hw->device_id) {
72 case IXGBE_DEV_ID_X540T:
df376f0d 73 case IXGBE_DEV_ID_X540T1:
67a79df2
AD		 74 case IXGBE_DEV_ID_82599_T3_LOM:
75 return 0;
76 default:
77 return IXGBE_ERR_FC_NOT_SUPPORTED;
78 }
79}
80
81/**
82 * ixgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
84 *
85 * Called at init time to set up flow control.
86 **/
041441d0 87static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 88{
89 s32 ret_val = 0;
90 u32 reg = 0, reg_bp = 0;
91 u16 reg_cu = 0;
d7bbcd32 92 bool got_lock = false;
67a79df2 93
67a79df2
AD		 94 /*
95 * Validate the requested mode. Strict IEEE mode does not allow
96 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
97 */
98 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
99 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
100 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
101 goto out;
102 }
103
104 /*
105 * 10gig parts do not have a word in the EEPROM to determine the
106 * default flow control setting, so we explicitly set it to full.
107 */
108 if (hw->fc.requested_mode == ixgbe_fc_default)
109 hw->fc.requested_mode = ixgbe_fc_full;
110
111 /*
112 * Set up the 1G and 10G flow control advertisement registers so the
113 * HW will be able to do fc autoneg once the cable is plugged in. If
114 * we link at 10G, the 1G advertisement is harmless and vice versa.
115 */
67a79df2
AD		 116 switch (hw->phy.media_type) {
117 case ixgbe_media_type_fiber:
118 case ixgbe_media_type_backplane:
119 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
120 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
121 break;
67a79df2
AD		 122 case ixgbe_media_type_copper:
123 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
124 MDIO_MMD_AN, &reg_cu);
125 break;
67a79df2 126 default:
041441d0 127 break;
67a79df2
AD		 128 }
129
130 /*
131 * The possible values of fc.requested_mode are:
132 * 0: Flow control is completely disabled
133 * 1: Rx flow control is enabled (we can receive pause frames,
134 * but not send pause frames).
135 * 2: Tx flow control is enabled (we can send pause frames but
136 * we do not support receiving pause frames).
137 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 138 * other: Invalid.
139 */
140 switch (hw->fc.requested_mode) {
141 case ixgbe_fc_none:
142 /* Flow control completely disabled by software override. */
143 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
144 if (hw->phy.media_type == ixgbe_media_type_backplane)
145 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
146 IXGBE_AUTOC_ASM_PAUSE);
147 else if (hw->phy.media_type == ixgbe_media_type_copper)
148 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
149 break;
67a79df2
AD		 150 case ixgbe_fc_tx_pause:
151 /*
152 * Tx Flow control is enabled, and Rx Flow control is
153 * disabled by software override.
154 */
041441d0
AD		 155 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
156 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 157 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 158 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
159 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 160 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 161 reg_cu |= IXGBE_TAF_ASM_PAUSE;
162 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 163 }
164 break;
041441d0
AD		 165 case ixgbe_fc_rx_pause:
166 /*
167 * Rx Flow control is enabled and Tx Flow control is
168 * disabled by software override. Since there really
169 * isn't a way to advertise that we are capable of RX
170 * Pause ONLY, we will advertise that we support both
171 * symmetric and asymmetric Rx PAUSE, as such we fall
172 * through to the fc_full statement. Later, we will
173 * disable the adapter's ability to send PAUSE frames.
174 */
67a79df2
AD		 175 case ixgbe_fc_full:
176 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 177 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 178 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 179 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
180 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 181 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 182 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 183 break;
67a79df2
AD		 184 default:
185 hw_dbg(hw, "Flow control param set incorrectly\n");
186 ret_val = IXGBE_ERR_CONFIG;
187 goto out;
188 break;
189 }
190
191 if (hw->mac.type != ixgbe_mac_X540) {
192 /*
193 * Enable auto-negotiation between the MAC & PHY;
194 * the MAC will advertise clause 37 flow control.
195 */
196 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
197 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
198
199 /* Disable AN timeout */
200 if (hw->fc.strict_ieee)
201 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
202
203 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
204 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
205 }
206
207 /*
208 * AUTOC restart handles negotiation of 1G and 10G on backplane
209 * and copper. There is no need to set the PCS1GCTL register.
210 *
211 */
212 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 213 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
214 * LESM is on, likewise reset_pipeline requries the lock as
215 * it also writes AUTOC.
216 */
217 if ((hw->mac.type == ixgbe_mac_82599EB) &&
218 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
219 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
220 IXGBE_GSSR_MAC_CSR_SM);
221 if (ret_val)
222 goto out;
223
224 got_lock = true;
225 }
226
67a79df2 227 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
d7bbcd32
DS		 228
229 if (hw->mac.type == ixgbe_mac_82599EB)
230 ixgbe_reset_pipeline_82599(hw);
231
232 if (got_lock)
233 hw->mac.ops.release_swfw_sync(hw,
234 IXGBE_GSSR_MAC_CSR_SM);
235
67a79df2
AD		 236 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
237 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
238 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
239 MDIO_MMD_AN, reg_cu);
240 }
241
242 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
243out:
244 return ret_val;
245}
246
9a799d71 247/**
c44ade9e 248 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 249 * @hw: pointer to hardware structure
250 *
251 * Starts the hardware by filling the bus info structure and media type, clears
252 * all on chip counters, initializes receive address registers, multicast
253 * table, VLAN filter table, calls routine to set up link and flow control
254 * settings, and leaves transmit and receive units disabled and uninitialized
255 **/
c44ade9e 256s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 257{
258 u32 ctrl_ext;
259
260 /* Set the media type */
261 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
262
263 /* Identify the PHY */
c44ade9e 264 hw->phy.ops.identify(hw);
9a799d71 265
9a799d71 266 /* Clear the VLAN filter table */
c44ade9e 267 hw->mac.ops.clear_vfta(hw);
9a799d71 268
9a799d71 269 /* Clear statistics registers */
c44ade9e 270 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 271
272 /* Set No Snoop Disable */
273 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
274 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
275 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 276 IXGBE_WRITE_FLUSH(hw);
9a799d71 277
620fa036 278 /* Setup flow control */
041441d0 279 ixgbe_setup_fc(hw);
620fa036 280
9a799d71
AK		 281 /* Clear adapter stopped flag */
282 hw->adapter_stopped = false;
283
284 return 0;
285}
286
7184b7cf
ET		 287/**
288 * ixgbe_start_hw_gen2 - Init sequence for common device family
289 * @hw: pointer to hw structure
290 *
291 * Performs the init sequence common to the second generation
292 * of 10 GbE devices.
293 * Devices in the second generation:
294 * 82599
295 * X540
296 **/
297s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
298{
299 u32 i;
3d5c5207 300 u32 regval;
7184b7cf
ET		 301
302 /* Clear the rate limiters */
303 for (i = 0; i < hw->mac.max_tx_queues; i++) {
304 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
305 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
306 }
307 IXGBE_WRITE_FLUSH(hw);
308
3d5c5207
ET		 309 /* Disable relaxed ordering */
310 for (i = 0; i < hw->mac.max_tx_queues; i++) {
311 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 312 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 313 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
314 }
315
316 for (i = 0; i < hw->mac.max_rx_queues; i++) {
317 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 318 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
319 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 320 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
321 }
322
7184b7cf
ET		 323 return 0;
324}
325
9a799d71 326/**
c44ade9e 327 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 328 * @hw: pointer to hardware structure
329 *
c44ade9e 330 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 331 * structure and media type, clears all on chip counters, initializes receive
332 * address registers, multicast table, VLAN filter table, calls routine to set
333 * up link and flow control settings, and leaves transmit and receive units
334 * disabled and uninitialized
335 **/
c44ade9e 336s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 337{
794caeb2
PWJ		 338 s32 status;
339
9a799d71 340 /* Reset the hardware */
794caeb2 341 status = hw->mac.ops.reset_hw(hw);
9a799d71 342
794caeb2
PWJ		 343 if (status == 0) {
344 /* Start the HW */
345 status = hw->mac.ops.start_hw(hw);
346 }
9a799d71 347
794caeb2 348 return status;
9a799d71
AK		 349}
350
351/**
c44ade9e 352 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 353 * @hw: pointer to hardware structure
354 *
355 * Clears all hardware statistics counters by reading them from the hardware
356 * Statistics counters are clear on read.
357 **/
c44ade9e 358s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 359{
360 u16 i = 0;
361
362 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
363 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
364 IXGBE_READ_REG(hw, IXGBE_ERRBC);
365 IXGBE_READ_REG(hw, IXGBE_MSPDC);
366 for (i = 0; i < 8; i++)
367 IXGBE_READ_REG(hw, IXGBE_MPC(i));
368
369 IXGBE_READ_REG(hw, IXGBE_MLFC);
370 IXGBE_READ_REG(hw, IXGBE_MRFC);
371 IXGBE_READ_REG(hw, IXGBE_RLEC);
372 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 373 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 374 if (hw->mac.type >= ixgbe_mac_82599EB) {
375 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
376 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
377 } else {
378 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
379 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
380 }
9a799d71
AK		 381
382 for (i = 0; i < 8; i++) {
383 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 384 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 385 if (hw->mac.type >= ixgbe_mac_82599EB) {
386 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
387 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
388 } else {
389 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
390 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
391 }
9a799d71 392 }
667c7565
ET		 393 if (hw->mac.type >= ixgbe_mac_82599EB)
394 for (i = 0; i < 8; i++)
395 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 396 IXGBE_READ_REG(hw, IXGBE_PRC64);
397 IXGBE_READ_REG(hw, IXGBE_PRC127);
398 IXGBE_READ_REG(hw, IXGBE_PRC255);
399 IXGBE_READ_REG(hw, IXGBE_PRC511);
400 IXGBE_READ_REG(hw, IXGBE_PRC1023);
401 IXGBE_READ_REG(hw, IXGBE_PRC1522);
402 IXGBE_READ_REG(hw, IXGBE_GPRC);
403 IXGBE_READ_REG(hw, IXGBE_BPRC);
404 IXGBE_READ_REG(hw, IXGBE_MPRC);
405 IXGBE_READ_REG(hw, IXGBE_GPTC);
406 IXGBE_READ_REG(hw, IXGBE_GORCL);
407 IXGBE_READ_REG(hw, IXGBE_GORCH);
408 IXGBE_READ_REG(hw, IXGBE_GOTCL);
409 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 410 if (hw->mac.type == ixgbe_mac_82598EB)
411 for (i = 0; i < 8; i++)
412 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 413 IXGBE_READ_REG(hw, IXGBE_RUC);
414 IXGBE_READ_REG(hw, IXGBE_RFC);
415 IXGBE_READ_REG(hw, IXGBE_ROC);
416 IXGBE_READ_REG(hw, IXGBE_RJC);
417 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
418 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
419 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
420 IXGBE_READ_REG(hw, IXGBE_TORL);
421 IXGBE_READ_REG(hw, IXGBE_TORH);
422 IXGBE_READ_REG(hw, IXGBE_TPR);
423 IXGBE_READ_REG(hw, IXGBE_TPT);
424 IXGBE_READ_REG(hw, IXGBE_PTC64);
425 IXGBE_READ_REG(hw, IXGBE_PTC127);
426 IXGBE_READ_REG(hw, IXGBE_PTC255);
427 IXGBE_READ_REG(hw, IXGBE_PTC511);
428 IXGBE_READ_REG(hw, IXGBE_PTC1023);
429 IXGBE_READ_REG(hw, IXGBE_PTC1522);
430 IXGBE_READ_REG(hw, IXGBE_MPTC);
431 IXGBE_READ_REG(hw, IXGBE_BPTC);
432 for (i = 0; i < 16; i++) {
433 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 434 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 435 if (hw->mac.type >= ixgbe_mac_82599EB) {
436 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
437 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
438 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
439 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
440 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
441 } else {
442 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
443 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
444 }
9a799d71
AK		 445 }
446
a3aeea0e
ET		 447 if (hw->mac.type == ixgbe_mac_X540) {
448 if (hw->phy.id == 0)
449 hw->phy.ops.identify(hw);
c1085b10
ET		 450 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
451 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
452 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
453 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 454 }
455
9a799d71
AK		 456 return 0;
457}
458
459/**
289700db 460 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 461 * @hw: pointer to hardware structure
289700db
DS		 462 * @pba_num: stores the part number string from the EEPROM
463 * @pba_num_size: part number string buffer length
c44ade9e 464 *
289700db 465 * Reads the part number string from the EEPROM.
c44ade9e 466 **/
289700db
DS		 467s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
468 u32 pba_num_size)
c44ade9e
JB		 469{
470 s32 ret_val;
471 u16 data;
289700db
DS		 472 u16 pba_ptr;
473 u16 offset;
474 u16 length;
475
476 if (pba_num == NULL) {
477 hw_dbg(hw, "PBA string buffer was null\n");
478 return IXGBE_ERR_INVALID_ARGUMENT;
479 }
c44ade9e
JB		 480
481 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
482 if (ret_val) {
483 hw_dbg(hw, "NVM Read Error\n");
484 return ret_val;
485 }
c44ade9e 486
289700db 487 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 488 if (ret_val) {
489 hw_dbg(hw, "NVM Read Error\n");
490 return ret_val;
491 }
289700db
DS		 492
493 /*
494 * if data is not ptr guard the PBA must be in legacy format which
495 * means pba_ptr is actually our second data word for the PBA number
496 * and we can decode it into an ascii string
497 */
498 if (data != IXGBE_PBANUM_PTR_GUARD) {
499 hw_dbg(hw, "NVM PBA number is not stored as string\n");
500
501 /* we will need 11 characters to store the PBA */
502 if (pba_num_size < 11) {
503 hw_dbg(hw, "PBA string buffer too small\n");
504 return IXGBE_ERR_NO_SPACE;
505 }
506
507 /* extract hex string from data and pba_ptr */
508 pba_num[0] = (data >> 12) & 0xF;
509 pba_num[1] = (data >> 8) & 0xF;
510 pba_num[2] = (data >> 4) & 0xF;
511 pba_num[3] = data & 0xF;
512 pba_num[4] = (pba_ptr >> 12) & 0xF;
513 pba_num[5] = (pba_ptr >> 8) & 0xF;
514 pba_num[6] = '-';
515 pba_num[7] = 0;
516 pba_num[8] = (pba_ptr >> 4) & 0xF;
517 pba_num[9] = pba_ptr & 0xF;
518
519 /* put a null character on the end of our string */
520 pba_num[10] = '\0';
521
522 /* switch all the data but the '-' to hex char */
523 for (offset = 0; offset < 10; offset++) {
524 if (pba_num[offset] < 0xA)
525 pba_num[offset] += '0';
526 else if (pba_num[offset] < 0x10)
527 pba_num[offset] += 'A' - 0xA;
528 }
529
530 return 0;
531 }
532
533 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
534 if (ret_val) {
535 hw_dbg(hw, "NVM Read Error\n");
536 return ret_val;
537 }
538
539 if (length == 0xFFFF || length == 0) {
540 hw_dbg(hw, "NVM PBA number section invalid length\n");
541 return IXGBE_ERR_PBA_SECTION;
542 }
543
544 /* check if pba_num buffer is big enough */
545 if (pba_num_size < (((u32)length * 2) - 1)) {
546 hw_dbg(hw, "PBA string buffer too small\n");
547 return IXGBE_ERR_NO_SPACE;
548 }
549
550 /* trim pba length from start of string */
551 pba_ptr++;
552 length--;
553
554 for (offset = 0; offset < length; offset++) {
555 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
556 if (ret_val) {
557 hw_dbg(hw, "NVM Read Error\n");
558 return ret_val;
559 }
560 pba_num[offset * 2] = (u8)(data >> 8);
561 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
562 }
563 pba_num[offset * 2] = '\0';
c44ade9e
JB		 564
565 return 0;
566}
567
568/**
569 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 570 * @hw: pointer to hardware structure
571 * @mac_addr: Adapter MAC address
572 *
573 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
574 * A reset of the adapter must be performed prior to calling this function
575 * in order for the MAC address to have been loaded from the EEPROM into RAR0
576 **/
c44ade9e 577s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 578{
579 u32 rar_high;
580 u32 rar_low;
581 u16 i;
582
583 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
584 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
585
586 for (i = 0; i < 4; i++)
587 mac_addr[i] = (u8)(rar_low >> (i*8));
588
589 for (i = 0; i < 2; i++)
590 mac_addr[i+4] = (u8)(rar_high >> (i*8));
591
592 return 0;
593}
594
11afc1b1
PW		 595/**
596 * ixgbe_get_bus_info_generic - Generic set PCI bus info
597 * @hw: pointer to hardware structure
598 *
599 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
600 **/
601s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
602{
603 struct ixgbe_adapter *adapter = hw->back;
604 struct ixgbe_mac_info *mac = &hw->mac;
605 u16 link_status;
606
607 hw->bus.type = ixgbe_bus_type_pci_express;
608
609 /* Get the negotiated link width and speed from PCI config space */
610 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
611 &link_status);
612
613 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
614 case IXGBE_PCI_LINK_WIDTH_1:
615 hw->bus.width = ixgbe_bus_width_pcie_x1;
616 break;
617 case IXGBE_PCI_LINK_WIDTH_2:
618 hw->bus.width = ixgbe_bus_width_pcie_x2;
619 break;
620 case IXGBE_PCI_LINK_WIDTH_4:
621 hw->bus.width = ixgbe_bus_width_pcie_x4;
622 break;
623 case IXGBE_PCI_LINK_WIDTH_8:
624 hw->bus.width = ixgbe_bus_width_pcie_x8;
625 break;
626 default:
627 hw->bus.width = ixgbe_bus_width_unknown;
628 break;
629 }
630
631 switch (link_status & IXGBE_PCI_LINK_SPEED) {
632 case IXGBE_PCI_LINK_SPEED_2500:
633 hw->bus.speed = ixgbe_bus_speed_2500;
634 break;
635 case IXGBE_PCI_LINK_SPEED_5000:
636 hw->bus.speed = ixgbe_bus_speed_5000;
637 break;
638 default:
639 hw->bus.speed = ixgbe_bus_speed_unknown;
640 break;
641 }
642
643 mac->ops.set_lan_id(hw);
644
645 return 0;
646}
647
648/**
649 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
650 * @hw: pointer to the HW structure
651 *
652 * Determines the LAN function id by reading memory-mapped registers
653 * and swaps the port value if requested.
654 **/
655void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
656{
657 struct ixgbe_bus_info *bus = &hw->bus;
658 u32 reg;
659
660 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
661 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
662 bus->lan_id = bus->func;
663
664 /* check for a port swap */
665 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
666 if (reg & IXGBE_FACTPS_LFS)
667 bus->func ^= 0x1;
668}
669
9a799d71 670/**
c44ade9e 671 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 672 * @hw: pointer to hardware structure
673 *
674 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
675 * disables transmit and receive units. The adapter_stopped flag is used by
676 * the shared code and drivers to determine if the adapter is in a stopped
677 * state and should not touch the hardware.
678 **/
c44ade9e 679s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 680{
9a799d71
AK		 681 u32 reg_val;
682 u16 i;
683
684 /*
685 * Set the adapter_stopped flag so other driver functions stop touching
686 * the hardware
687 */
688 hw->adapter_stopped = true;
689
690 /* Disable the receive unit */
ff9d1a5a 691 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
9a799d71 692
ff9d1a5a 693 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 694 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
695
ff9d1a5a 696 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 697 IXGBE_READ_REG(hw, IXGBE_EICR);
698
699 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 700 for (i = 0; i < hw->mac.max_tx_queues; i++)
701 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
702
703 /* Disable the receive unit by stopping each queue */
704 for (i = 0; i < hw->mac.max_rx_queues; i++) {
705 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
706 reg_val &= ~IXGBE_RXDCTL_ENABLE;
707 reg_val |= IXGBE_RXDCTL_SWFLSH;
708 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 709 }
710
ff9d1a5a
ET		 711 /* flush all queues disables */
712 IXGBE_WRITE_FLUSH(hw);
713 usleep_range(1000, 2000);
714
c44ade9e
JB		 715 /*
716 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
717 * access and verify no pending requests
718 */
ff9d1a5a 719 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 720}
721
722/**
c44ade9e 723 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 724 * @hw: pointer to hardware structure
725 * @index: led number to turn on
726 **/
c44ade9e 727s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 728{
729 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
730
731 /* To turn on the LED, set mode to ON. */
732 led_reg &= ~IXGBE_LED_MODE_MASK(index);
733 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
734 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 735 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 736
737 return 0;
738}
739
740/**
c44ade9e 741 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 742 * @hw: pointer to hardware structure
743 * @index: led number to turn off
744 **/
c44ade9e 745s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 746{
747 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
748
749 /* To turn off the LED, set mode to OFF. */
750 led_reg &= ~IXGBE_LED_MODE_MASK(index);
751 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
752 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 753 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 754
755 return 0;
756}
757
9a799d71 758/**
c44ade9e 759 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 760 * @hw: pointer to hardware structure
761 *
762 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
763 * ixgbe_hw struct in order to set up EEPROM access.
764 **/
c44ade9e 765s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 766{
767 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
768 u32 eec;
769 u16 eeprom_size;
770
771 if (eeprom->type == ixgbe_eeprom_uninitialized) {
772 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 773 /* Set default semaphore delay to 10ms which is a well
774 * tested value */
775 eeprom->semaphore_delay = 10;
68c7005d
ET		 776 /* Clear EEPROM page size, it will be initialized as needed */
777 eeprom->word_page_size = 0;
9a799d71
AK		 778
779 /*
780 * Check for EEPROM present first.
781 * If not present leave as none
782 */
783 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
784 if (eec & IXGBE_EEC_PRES) {
785 eeprom->type = ixgbe_eeprom_spi;
786
787 /*
788 * SPI EEPROM is assumed here. This code would need to
789 * change if a future EEPROM is not SPI.
790 */
791 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
792 IXGBE_EEC_SIZE_SHIFT);
793 eeprom->word_size = 1 << (eeprom_size +
794 IXGBE_EEPROM_WORD_SIZE_SHIFT);
795 }
796
797 if (eec & IXGBE_EEC_ADDR_SIZE)
798 eeprom->address_bits = 16;
799 else
800 eeprom->address_bits = 8;
801 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
802 "%d\n", eeprom->type, eeprom->word_size,
803 eeprom->address_bits);
804 }
805
806 return 0;
807}
808
11afc1b1 809/**
68c7005d 810 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 811 * @hw: pointer to hardware structure
68c7005d
ET		 812 * @offset: offset within the EEPROM to write
813 * @words: number of words
814 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 815 *
68c7005d 816 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 817 **/
68c7005d
ET		 818s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
819 u16 words, u16 *data)
11afc1b1 820{
68c7005d
ET		 821 s32 status = 0;
822 u16 i, count;
11afc1b1
PW		 823
824 hw->eeprom.ops.init_params(hw);
825
68c7005d
ET		 826 if (words == 0) {
827 status = IXGBE_ERR_INVALID_ARGUMENT;
828 goto out;
829 }
830
831 if (offset + words > hw->eeprom.word_size) {
11afc1b1
PW		 832 status = IXGBE_ERR_EEPROM;
833 goto out;
834 }
835
68c7005d
ET		 836 /*
837 * The EEPROM page size cannot be queried from the chip. We do lazy
838 * initialization. It is worth to do that when we write large buffer.
839 */
840 if ((hw->eeprom.word_page_size == 0) &&
841 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
842 ixgbe_detect_eeprom_page_size_generic(hw, offset);
843
844 /*
845 * We cannot hold synchronization semaphores for too long
846 * to avoid other entity starvation. However it is more efficient
847 * to read in bursts than synchronizing access for each word.
848 */
849 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
850 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
851 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
852 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
853 count, &data[i]);
854
855 if (status != 0)
856 break;
857 }
858
859out:
860 return status;
861}
862
863/**
864 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
865 * @hw: pointer to hardware structure
866 * @offset: offset within the EEPROM to be written to
867 * @words: number of word(s)
868 * @data: 16 bit word(s) to be written to the EEPROM
869 *
870 * If ixgbe_eeprom_update_checksum is not called after this function, the
871 * EEPROM will most likely contain an invalid checksum.
872 **/
873static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
874 u16 words, u16 *data)
875{
876 s32 status;
877 u16 word;
878 u16 page_size;
879 u16 i;
880 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
881
11afc1b1
PW		 882 /* Prepare the EEPROM for writing */
883 status = ixgbe_acquire_eeprom(hw);
884
885 if (status == 0) {
886 if (ixgbe_ready_eeprom(hw) != 0) {
887 ixgbe_release_eeprom(hw);
888 status = IXGBE_ERR_EEPROM;
889 }
890 }
891
892 if (status == 0) {
68c7005d
ET		 893 for (i = 0; i < words; i++) {
894 ixgbe_standby_eeprom(hw);
11afc1b1 895
68c7005d
ET		 896 /* Send the WRITE ENABLE command (8 bit opcode ) */
897 ixgbe_shift_out_eeprom_bits(hw,
898 IXGBE_EEPROM_WREN_OPCODE_SPI,
899 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 900
68c7005d 901 ixgbe_standby_eeprom(hw);
11afc1b1 902
68c7005d
ET		 903 /*
904 * Some SPI eeproms use the 8th address bit embedded
905 * in the opcode
906 */
907 if ((hw->eeprom.address_bits == 8) &&
908 ((offset + i) >= 128))
909 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
910
911 /* Send the Write command (8-bit opcode + addr) */
912 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
913 IXGBE_EEPROM_OPCODE_BITS);
914 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
915 hw->eeprom.address_bits);
916
917 page_size = hw->eeprom.word_page_size;
918
919 /* Send the data in burst via SPI*/
920 do {
921 word = data[i];
922 word = (word >> 8) | (word << 8);
923 ixgbe_shift_out_eeprom_bits(hw, word, 16);
924
925 if (page_size == 0)
926 break;
927
928 /* do not wrap around page */
929 if (((offset + i) & (page_size - 1)) ==
930 (page_size - 1))
931 break;
932 } while (++i < words);
933
934 ixgbe_standby_eeprom(hw);
935 usleep_range(10000, 20000);
936 }
937 /* Done with writing - release the EEPROM */
938 ixgbe_release_eeprom(hw);
939 }
11afc1b1 940
68c7005d
ET		 941 return status;
942}
943
944/**
945 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
946 * @hw: pointer to hardware structure
947 * @offset: offset within the EEPROM to be written to
948 * @data: 16 bit word to be written to the EEPROM
949 *
950 * If ixgbe_eeprom_update_checksum is not called after this function, the
951 * EEPROM will most likely contain an invalid checksum.
952 **/
953s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
954{
955 s32 status;
11afc1b1 956
68c7005d 957 hw->eeprom.ops.init_params(hw);
11afc1b1 958
68c7005d
ET		 959 if (offset >= hw->eeprom.word_size) {
960 status = IXGBE_ERR_EEPROM;
961 goto out;
11afc1b1
PW		 962 }
963
68c7005d
ET		 964 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
965
11afc1b1
PW		 966out:
967 return status;
968}
969
9a799d71 970/**
68c7005d 971 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 972 * @hw: pointer to hardware structure
973 * @offset: offset within the EEPROM to be read
68c7005d
ET		 974 * @words: number of word(s)
975 * @data: read 16 bit words(s) from EEPROM
c44ade9e 976 *
68c7005d 977 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 978 **/
68c7005d
ET		 979s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
980 u16 words, u16 *data)
c44ade9e 981{
68c7005d
ET		 982 s32 status = 0;
983 u16 i, count;
c44ade9e
JB		 984
985 hw->eeprom.ops.init_params(hw);
986
68c7005d
ET		 987 if (words == 0) {
988 status = IXGBE_ERR_INVALID_ARGUMENT;
989 goto out;
990 }
991
992 if (offset + words > hw->eeprom.word_size) {
c44ade9e
JB		 993 status = IXGBE_ERR_EEPROM;
994 goto out;
995 }
996
68c7005d
ET		 997 /*
998 * We cannot hold synchronization semaphores for too long
999 * to avoid other entity starvation. However it is more efficient
1000 * to read in bursts than synchronizing access for each word.
1001 */
1002 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1003 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1004 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1005
1006 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1007 count, &data[i]);
1008
1009 if (status != 0)
1010 break;
1011 }
1012
1013out:
1014 return status;
1015}
1016
1017/**
1018 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1019 * @hw: pointer to hardware structure
1020 * @offset: offset within the EEPROM to be read
1021 * @words: number of word(s)
1022 * @data: read 16 bit word(s) from EEPROM
1023 *
1024 * Reads 16 bit word(s) from EEPROM through bit-bang method
1025 **/
1026static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1027 u16 words, u16 *data)
1028{
1029 s32 status;
1030 u16 word_in;
1031 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1032 u16 i;
1033
c44ade9e
JB		 1034 /* Prepare the EEPROM for reading */
1035 status = ixgbe_acquire_eeprom(hw);
1036
1037 if (status == 0) {
1038 if (ixgbe_ready_eeprom(hw) != 0) {
1039 ixgbe_release_eeprom(hw);
1040 status = IXGBE_ERR_EEPROM;
1041 }
1042 }
1043
1044 if (status == 0) {
68c7005d
ET		 1045 for (i = 0; i < words; i++) {
1046 ixgbe_standby_eeprom(hw);
1047 /*
1048 * Some SPI eeproms use the 8th address bit embedded
1049 * in the opcode
1050 */
1051 if ((hw->eeprom.address_bits == 8) &&
1052 ((offset + i) >= 128))
1053 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1054
1055 /* Send the READ command (opcode + addr) */
1056 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1057 IXGBE_EEPROM_OPCODE_BITS);
1058 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1059 hw->eeprom.address_bits);
1060
1061 /* Read the data. */
1062 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1063 data[i] = (word_in >> 8) | (word_in << 8);
1064 }
c44ade9e 1065
68c7005d
ET		 1066 /* End this read operation */
1067 ixgbe_release_eeprom(hw);
1068 }
c44ade9e 1069
68c7005d
ET		 1070 return status;
1071}
c44ade9e 1072
68c7005d
ET		 1073/**
1074 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1075 * @hw: pointer to hardware structure
1076 * @offset: offset within the EEPROM to be read
1077 * @data: read 16 bit value from EEPROM
1078 *
1079 * Reads 16 bit value from EEPROM through bit-bang method
1080 **/
1081s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1082 u16 *data)
1083{
1084 s32 status;
c44ade9e 1085
68c7005d
ET		 1086 hw->eeprom.ops.init_params(hw);
1087
1088 if (offset >= hw->eeprom.word_size) {
1089 status = IXGBE_ERR_EEPROM;
1090 goto out;
c44ade9e
JB		 1091 }
1092
68c7005d
ET		 1093 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1094
c44ade9e
JB		 1095out:
1096 return status;
1097}
1098
1099/**
68c7005d 1100 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1101 * @hw: pointer to hardware structure
68c7005d
ET		 1102 * @offset: offset of word in the EEPROM to read
1103 * @words: number of word(s)
1104 * @data: 16 bit word(s) from the EEPROM
9a799d71 1105 *
68c7005d 1106 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1107 **/
68c7005d
ET		 1108s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1109 u16 words, u16 *data)
9a799d71
AK		 1110{
1111 u32 eerd;
68c7005d
ET		 1112 s32 status = 0;
1113 u32 i;
9a799d71 1114
c44ade9e
JB		 1115 hw->eeprom.ops.init_params(hw);
1116
68c7005d
ET		 1117 if (words == 0) {
1118 status = IXGBE_ERR_INVALID_ARGUMENT;
1119 goto out;
1120 }
1121
c44ade9e
JB		 1122 if (offset >= hw->eeprom.word_size) {
1123 status = IXGBE_ERR_EEPROM;
1124 goto out;
1125 }
1126
68c7005d
ET		 1127 for (i = 0; i < words; i++) {
1128 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1129 IXGBE_EEPROM_RW_REG_START;
9a799d71 1130
68c7005d
ET		 1131 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1132 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1133
68c7005d
ET		 1134 if (status == 0) {
1135 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1136 IXGBE_EEPROM_RW_REG_DATA);
1137 } else {
1138 hw_dbg(hw, "Eeprom read timed out\n");
1139 goto out;
1140 }
1141 }
1142out:
1143 return status;
1144}
9a799d71 1145
68c7005d
ET		 1146/**
1147 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1148 * @hw: pointer to hardware structure
1149 * @offset: offset within the EEPROM to be used as a scratch pad
1150 *
1151 * Discover EEPROM page size by writing marching data at given offset.
1152 * This function is called only when we are writing a new large buffer
1153 * at given offset so the data would be overwritten anyway.
1154 **/
1155static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1156 u16 offset)
1157{
1158 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1159 s32 status = 0;
1160 u16 i;
1161
1162 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1163 data[i] = i;
1164
1165 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1166 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1167 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1168 hw->eeprom.word_page_size = 0;
1169 if (status != 0)
1170 goto out;
1171
1172 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1173 if (status != 0)
1174 goto out;
1175
1176 /*
1177 * When writing in burst more than the actual page size
1178 * EEPROM address wraps around current page.
1179 */
1180 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1181
1182 hw_dbg(hw, "Detected EEPROM page size = %d words.",
1183 hw->eeprom.word_page_size);
c44ade9e 1184out:
9a799d71
AK		 1185 return status;
1186}
1187
eb9c3e3e 1188/**
68c7005d
ET		 1189 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1190 * @hw: pointer to hardware structure
1191 * @offset: offset of word in the EEPROM to read
1192 * @data: word read from the EEPROM
1193 *
1194 * Reads a 16 bit word from the EEPROM using the EERD register.
1195 **/
1196s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1197{
1198 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1199}
1200
1201/**
1202 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1203 * @hw: pointer to hardware structure
1204 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1205 * @words: number of words
1206 * @data: word(s) write to the EEPROM
eb9c3e3e 1207 *
68c7005d 1208 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1209 **/
68c7005d
ET		 1210s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1211 u16 words, u16 *data)
eb9c3e3e
ET		 1212{
1213 u32 eewr;
68c7005d
ET		 1214 s32 status = 0;
1215 u16 i;
eb9c3e3e
ET		 1216
1217 hw->eeprom.ops.init_params(hw);
1218
68c7005d
ET		 1219 if (words == 0) {
1220 status = IXGBE_ERR_INVALID_ARGUMENT;
1221 goto out;
1222 }
1223
eb9c3e3e
ET		 1224 if (offset >= hw->eeprom.word_size) {
1225 status = IXGBE_ERR_EEPROM;
1226 goto out;
1227 }
1228
68c7005d
ET		 1229 for (i = 0; i < words; i++) {
1230 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1231 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1232 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1233
68c7005d
ET		 1234 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1235 if (status != 0) {
1236 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1237 goto out;
1238 }
eb9c3e3e 1239
68c7005d 1240 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1241
68c7005d
ET		 1242 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1243 if (status != 0) {
1244 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1245 goto out;
1246 }
eb9c3e3e
ET		 1247 }
1248
1249out:
1250 return status;
1251}
1252
68c7005d
ET		 1253/**
1254 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1255 * @hw: pointer to hardware structure
1256 * @offset: offset of word in the EEPROM to write
1257 * @data: word write to the EEPROM
1258 *
1259 * Write a 16 bit word to the EEPROM using the EEWR register.
1260 **/
1261s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1262{
1263 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1264}
1265
9a799d71 1266/**
21ce849b 1267 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1268 * @hw: pointer to hardware structure
21ce849b 1269 * @ee_reg: EEPROM flag for polling
9a799d71 1270 *
21ce849b
MC		 1271 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1272 * read or write is done respectively.
9a799d71 1273 **/
eb9c3e3e 1274static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1275{
1276 u32 i;
1277 u32 reg;
1278 s32 status = IXGBE_ERR_EEPROM;
1279
21ce849b
MC		 1280 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1281 if (ee_reg == IXGBE_NVM_POLL_READ)
1282 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1283 else
1284 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1285
1286 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 1287 status = 0;
1288 break;
1289 }
1290 udelay(5);
1291 }
1292 return status;
1293}
1294
c44ade9e
JB		 1295/**
1296 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1297 * @hw: pointer to hardware structure
1298 *
1299 * Prepares EEPROM for access using bit-bang method. This function should
1300 * be called before issuing a command to the EEPROM.
1301 **/
1302static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1303{
1304 s32 status = 0;
dbf893ee 1305 u32 eec;
c44ade9e
JB		 1306 u32 i;
1307
5e655105 1308 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
c44ade9e
JB		 1309 status = IXGBE_ERR_SWFW_SYNC;
1310
1311 if (status == 0) {
1312 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1313
1314 /* Request EEPROM Access */
1315 eec |= IXGBE_EEC_REQ;
1316 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1317
1318 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1319 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1320 if (eec & IXGBE_EEC_GNT)
1321 break;
1322 udelay(5);
1323 }
1324
1325 /* Release if grant not acquired */
1326 if (!(eec & IXGBE_EEC_GNT)) {
1327 eec &= ~IXGBE_EEC_REQ;
1328 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1329 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1330
5e655105 1331 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
c44ade9e
JB		 1332 status = IXGBE_ERR_EEPROM;
1333 }
c44ade9e 1334
dbf893ee
ET		 1335 /* Setup EEPROM for Read/Write */
1336 if (status == 0) {
1337 /* Clear CS and SK */
1338 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1339 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1340 IXGBE_WRITE_FLUSH(hw);
1341 udelay(1);
1342 }
c44ade9e
JB		 1343 }
1344 return status;
1345}
1346
9a799d71
AK		 1347/**
1348 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1349 * @hw: pointer to hardware structure
1350 *
1351 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1352 **/
1353static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1354{
1355 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 1356 u32 timeout = 2000;
9a799d71
AK		 1357 u32 i;
1358 u32 swsm;
1359
9a799d71
AK		 1360 /* Get SMBI software semaphore between device drivers first */
1361 for (i = 0; i < timeout; i++) {
1362 /*
1363 * If the SMBI bit is 0 when we read it, then the bit will be
1364 * set and we have the semaphore
1365 */
1366 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1367 if (!(swsm & IXGBE_SWSM_SMBI)) {
1368 status = 0;
1369 break;
1370 }
dbf893ee 1371 udelay(50);
9a799d71
AK		 1372 }
1373
51275d37
ET		 1374 if (i == timeout) {
1375 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1376 "not granted.\n");
1377 /*
1378 * this release is particularly important because our attempts
1379 * above to get the semaphore may have succeeded, and if there
1380 * was a timeout, we should unconditionally clear the semaphore
1381 * bits to free the driver to make progress
1382 */
1383 ixgbe_release_eeprom_semaphore(hw);
1384
1385 udelay(50);
1386 /*
1387 * one last try
1388 * If the SMBI bit is 0 when we read it, then the bit will be
1389 * set and we have the semaphore
1390 */
1391 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1392 if (!(swsm & IXGBE_SWSM_SMBI))
1393 status = 0;
1394 }
1395
9a799d71
AK		 1396 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1397 if (status == 0) {
1398 for (i = 0; i < timeout; i++) {
1399 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1400
1401 /* Set the SW EEPROM semaphore bit to request access */
1402 swsm |= IXGBE_SWSM_SWESMBI;
1403 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1404
1405 /*
1406 * If we set the bit successfully then we got the
1407 * semaphore.
1408 */
1409 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1410 if (swsm & IXGBE_SWSM_SWESMBI)
1411 break;
1412
1413 udelay(50);
1414 }
1415
1416 /*
1417 * Release semaphores and return error if SW EEPROM semaphore
1418 * was not granted because we don't have access to the EEPROM
1419 */
1420 if (i >= timeout) {
dbf893ee 1421 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 1422 "not granted.\n");
9a799d71
AK		 1423 ixgbe_release_eeprom_semaphore(hw);
1424 status = IXGBE_ERR_EEPROM;
1425 }
dbf893ee
ET		 1426 } else {
1427 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1428 "not granted.\n");
9a799d71
AK		 1429 }
1430
1431 return status;
1432}
1433
1434/**
1435 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1436 * @hw: pointer to hardware structure
1437 *
1438 * This function clears hardware semaphore bits.
1439 **/
1440static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1441{
1442 u32 swsm;
1443
1444 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1445
1446 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1447 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1448 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1449 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1450}
1451
c44ade9e
JB		 1452/**
1453 * ixgbe_ready_eeprom - Polls for EEPROM ready
1454 * @hw: pointer to hardware structure
1455 **/
1456static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1457{
1458 s32 status = 0;
1459 u16 i;
1460 u8 spi_stat_reg;
1461
1462 /*
1463 * Read "Status Register" repeatedly until the LSB is cleared. The
1464 * EEPROM will signal that the command has been completed by clearing
1465 * bit 0 of the internal status register. If it's not cleared within
1466 * 5 milliseconds, then error out.
1467 */
1468 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1469 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1470 IXGBE_EEPROM_OPCODE_BITS);
1471 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1472 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1473 break;
1474
1475 udelay(5);
1476 ixgbe_standby_eeprom(hw);
6403eab1 1477 }
c44ade9e
JB		 1478
1479 /*
1480 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1481 * devices (and only 0-5mSec on 5V devices)
1482 */
1483 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1484 hw_dbg(hw, "SPI EEPROM Status error\n");
1485 status = IXGBE_ERR_EEPROM;
1486 }
1487
1488 return status;
1489}
1490
1491/**
1492 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1493 * @hw: pointer to hardware structure
1494 **/
1495static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1496{
1497 u32 eec;
1498
1499 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1500
1501 /* Toggle CS to flush commands */
1502 eec |= IXGBE_EEC_CS;
1503 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1504 IXGBE_WRITE_FLUSH(hw);
1505 udelay(1);
1506 eec &= ~IXGBE_EEC_CS;
1507 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1508 IXGBE_WRITE_FLUSH(hw);
1509 udelay(1);
1510}
1511
1512/**
1513 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1514 * @hw: pointer to hardware structure
1515 * @data: data to send to the EEPROM
1516 * @count: number of bits to shift out
1517 **/
1518static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1519 u16 count)
1520{
1521 u32 eec;
1522 u32 mask;
1523 u32 i;
1524
1525 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1526
1527 /*
1528 * Mask is used to shift "count" bits of "data" out to the EEPROM
1529 * one bit at a time. Determine the starting bit based on count
1530 */
1531 mask = 0x01 << (count - 1);
1532
1533 for (i = 0; i < count; i++) {
1534 /*
1535 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1536 * "1", and then raising and then lowering the clock (the SK
1537 * bit controls the clock input to the EEPROM). A "0" is
1538 * shifted out to the EEPROM by setting "DI" to "0" and then
1539 * raising and then lowering the clock.
1540 */
1541 if (data & mask)
1542 eec |= IXGBE_EEC_DI;
1543 else
1544 eec &= ~IXGBE_EEC_DI;
1545
1546 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1547 IXGBE_WRITE_FLUSH(hw);
1548
1549 udelay(1);
1550
1551 ixgbe_raise_eeprom_clk(hw, &eec);
1552 ixgbe_lower_eeprom_clk(hw, &eec);
1553
1554 /*
1555 * Shift mask to signify next bit of data to shift in to the
1556 * EEPROM
1557 */
1558 mask = mask >> 1;
6403eab1 1559 }
c44ade9e
JB		 1560
1561 /* We leave the "DI" bit set to "0" when we leave this routine. */
1562 eec &= ~IXGBE_EEC_DI;
1563 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1564 IXGBE_WRITE_FLUSH(hw);
1565}
1566
1567/**
1568 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1569 * @hw: pointer to hardware structure
1570 **/
1571static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1572{
1573 u32 eec;
1574 u32 i;
1575 u16 data = 0;
1576
1577 /*
1578 * In order to read a register from the EEPROM, we need to shift
1579 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1580 * the clock input to the EEPROM (setting the SK bit), and then reading
1581 * the value of the "DO" bit. During this "shifting in" process the
1582 * "DI" bit should always be clear.
1583 */
1584 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1585
1586 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1587
1588 for (i = 0; i < count; i++) {
1589 data = data << 1;
1590 ixgbe_raise_eeprom_clk(hw, &eec);
1591
1592 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1593
1594 eec &= ~(IXGBE_EEC_DI);
1595 if (eec & IXGBE_EEC_DO)
1596 data |= 1;
1597
1598 ixgbe_lower_eeprom_clk(hw, &eec);
1599 }
1600
1601 return data;
1602}
1603
1604/**
1605 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1606 * @hw: pointer to hardware structure
1607 * @eec: EEC register's current value
1608 **/
1609static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1610{
1611 /*
1612 * Raise the clock input to the EEPROM
1613 * (setting the SK bit), then delay
1614 */
1615 *eec = *eec | IXGBE_EEC_SK;
1616 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1617 IXGBE_WRITE_FLUSH(hw);
1618 udelay(1);
1619}
1620
1621/**
1622 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1623 * @hw: pointer to hardware structure
1624 * @eecd: EECD's current value
1625 **/
1626static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1627{
1628 /*
1629 * Lower the clock input to the EEPROM (clearing the SK bit), then
1630 * delay
1631 */
1632 *eec = *eec & ~IXGBE_EEC_SK;
1633 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1634 IXGBE_WRITE_FLUSH(hw);
1635 udelay(1);
1636}
1637
1638/**
1639 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1640 * @hw: pointer to hardware structure
1641 **/
1642static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1643{
1644 u32 eec;
1645
1646 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1647
1648 eec |= IXGBE_EEC_CS; /* Pull CS high */
1649 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1650
1651 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1652 IXGBE_WRITE_FLUSH(hw);
1653
1654 udelay(1);
1655
1656 /* Stop requesting EEPROM access */
1657 eec &= ~IXGBE_EEC_REQ;
1658 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1659
90827996 1660 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1661
032b4325
DS		 1662 /*
1663 * Delay before attempt to obtain semaphore again to allow FW
1664 * access. semaphore_delay is in ms we need us for usleep_range
1665 */
1666 usleep_range(hw->eeprom.semaphore_delay * 1000,
1667 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1668}
1669
9a799d71 1670/**
dbf893ee 1671 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1672 * @hw: pointer to hardware structure
1673 **/
a391f1d5 1674u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1675{
1676 u16 i;
1677 u16 j;
1678 u16 checksum = 0;
1679 u16 length = 0;
1680 u16 pointer = 0;
1681 u16 word = 0;
1682
1683 /* Include 0x0-0x3F in the checksum */
1684 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1685 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1686 hw_dbg(hw, "EEPROM read failed\n");
1687 break;
1688 }
1689 checksum += word;
1690 }
1691
1692 /* Include all data from pointers except for the fw pointer */
1693 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1694 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1695
1696 /* Make sure the pointer seems valid */
1697 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1698 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1699
1700 if (length != 0xFFFF && length != 0) {
1701 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1702 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1703 checksum += word;
1704 }
1705 }
1706 }
1707 }
1708
1709 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1710
1711 return checksum;
1712}
1713
1714/**
c44ade9e 1715 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1716 * @hw: pointer to hardware structure
1717 * @checksum_val: calculated checksum
1718 *
1719 * Performs checksum calculation and validates the EEPROM checksum. If the
1720 * caller does not need checksum_val, the value can be NULL.
1721 **/
c44ade9e
JB		 1722s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1723 u16 *checksum_val)
9a799d71
AK		 1724{
1725 s32 status;
1726 u16 checksum;
1727 u16 read_checksum = 0;
1728
1729 /*
1730 * Read the first word from the EEPROM. If this times out or fails, do
1731 * not continue or we could be in for a very long wait while every
1732 * EEPROM read fails
1733 */
c44ade9e 1734 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1735
1736 if (status == 0) {
a391f1d5 1737 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1738
c44ade9e 1739 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1740
1741 /*
1742 * Verify read checksum from EEPROM is the same as
1743 * calculated checksum
1744 */
1745 if (read_checksum != checksum)
1746 status = IXGBE_ERR_EEPROM_CHECKSUM;
1747
1748 /* If the user cares, return the calculated checksum */
1749 if (checksum_val)
1750 *checksum_val = checksum;
1751 } else {
1752 hw_dbg(hw, "EEPROM read failed\n");
1753 }
1754
1755 return status;
1756}
1757
c44ade9e
JB		 1758/**
1759 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1760 * @hw: pointer to hardware structure
1761 **/
1762s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1763{
1764 s32 status;
1765 u16 checksum;
1766
1767 /*
1768 * Read the first word from the EEPROM. If this times out or fails, do
1769 * not continue or we could be in for a very long wait while every
1770 * EEPROM read fails
1771 */
1772 status = hw->eeprom.ops.read(hw, 0, &checksum);
1773
1774 if (status == 0) {
a391f1d5 1775 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1776 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1777 checksum);
c44ade9e
JB		 1778 } else {
1779 hw_dbg(hw, "EEPROM read failed\n");
1780 }
1781
1782 return status;
1783}
1784
9a799d71
AK		 1785/**
1786 * ixgbe_validate_mac_addr - Validate MAC address
1787 * @mac_addr: pointer to MAC address.
1788 *
1789 * Tests a MAC address to ensure it is a valid Individual Address
1790 **/
1791s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1792{
1793 s32 status = 0;
1794
1795 /* Make sure it is not a multicast address */
1796 if (IXGBE_IS_MULTICAST(mac_addr))
1797 status = IXGBE_ERR_INVALID_MAC_ADDR;
1798 /* Not a broadcast address */
1799 else if (IXGBE_IS_BROADCAST(mac_addr))
1800 status = IXGBE_ERR_INVALID_MAC_ADDR;
1801 /* Reject the zero address */
51a1f721 1802 else if (is_zero_ether_addr(mac_addr))
9a799d71
AK		 1803 status = IXGBE_ERR_INVALID_MAC_ADDR;
1804
1805 return status;
1806}
1807
1808/**
c44ade9e 1809 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1810 * @hw: pointer to hardware structure
9a799d71 1811 * @index: Receive address register to write
c44ade9e
JB		 1812 * @addr: Address to put into receive address register
1813 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1814 * @enable_addr: set flag that address is active
1815 *
1816 * Puts an ethernet address into a receive address register.
1817 **/
c44ade9e
JB		 1818s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1819 u32 enable_addr)
9a799d71
AK		 1820{
1821 u32 rar_low, rar_high;
c44ade9e
JB		 1822 u32 rar_entries = hw->mac.num_rar_entries;
1823
c700f4e6
ET		 1824 /* Make sure we are using a valid rar index range */
1825 if (index >= rar_entries) {
1826 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1827 return IXGBE_ERR_INVALID_ARGUMENT;
1828 }
1829
c44ade9e
JB		 1830 /* setup VMDq pool selection before this RAR gets enabled */
1831 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1832
c700f4e6
ET		 1833 /*
1834 * HW expects these in little endian so we reverse the byte
1835 * order from network order (big endian) to little endian
1836 */
1837 rar_low = ((u32)addr[0] |
1838 ((u32)addr[1] << 8) |
1839 ((u32)addr[2] << 16) |
1840 ((u32)addr[3] << 24));
1841 /*
1842 * Some parts put the VMDq setting in the extra RAH bits,
1843 * so save everything except the lower 16 bits that hold part
1844 * of the address and the address valid bit.
1845 */
1846 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1847 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1848 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1849
c700f4e6
ET		 1850 if (enable_addr != 0)
1851 rar_high |= IXGBE_RAH_AV;
9a799d71 1852
c700f4e6
ET		 1853 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1854 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1855
1856 return 0;
1857}
1858
1859/**
1860 * ixgbe_clear_rar_generic - Remove Rx address register
1861 * @hw: pointer to hardware structure
1862 * @index: Receive address register to write
1863 *
1864 * Clears an ethernet address from a receive address register.
1865 **/
1866s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1867{
1868 u32 rar_high;
1869 u32 rar_entries = hw->mac.num_rar_entries;
1870
1871 /* Make sure we are using a valid rar index range */
c700f4e6 1872 if (index >= rar_entries) {
c44ade9e 1873 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1874 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1875 }
1876
c700f4e6
ET		 1877 /*
1878 * Some parts put the VMDq setting in the extra RAH bits,
1879 * so save everything except the lower 16 bits that hold part
1880 * of the address and the address valid bit.
1881 */
1882 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1883 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1884
1885 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1886 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1887
c44ade9e
JB		 1888 /* clear VMDq pool/queue selection for this RAR */
1889 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1890
1891 return 0;
1892}
1893
c44ade9e
JB		 1894/**
1895 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1896 * @hw: pointer to hardware structure
1897 *
1898 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1899 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1900 * the receiver is in reset when the routine is called.
1901 **/
c44ade9e 1902s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1903{
1904 u32 i;
2c5645cf 1905 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1906
1907 /*
1908 * If the current mac address is valid, assume it is a software override
1909 * to the permanent address.
1910 * Otherwise, use the permanent address from the eeprom.
1911 */
1912 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1913 IXGBE_ERR_INVALID_MAC_ADDR) {
1914 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1915 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1916
ce7194d8 1917 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1918 } else {
1919 /* Setup the receive address. */
1920 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1921 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1922
c44ade9e 1923 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1924
1925 /* clear VMDq pool/queue selection for RAR 0 */
1926 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1927 }
c44ade9e 1928 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1929
1930 hw->addr_ctrl.rar_used_count = 1;
1931
1932 /* Zero out the other receive addresses. */
c44ade9e 1933 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1934 for (i = 1; i < rar_entries; i++) {
1935 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1936 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1937 }
1938
1939 /* Clear the MTA */
9a799d71
AK		 1940 hw->addr_ctrl.mta_in_use = 0;
1941 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1942
1943 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1944 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1945 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1946
c44ade9e
JB		 1947 if (hw->mac.ops.init_uta_tables)
1948 hw->mac.ops.init_uta_tables(hw);
1949
9a799d71
AK		 1950 return 0;
1951}
1952
1953/**
1954 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1955 * @hw: pointer to hardware structure
1956 * @mc_addr: the multicast address
1957 *
1958 * Extracts the 12 bits, from a multicast address, to determine which
1959 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1960 * incoming rx multicast addresses, to determine the bit-vector to check in
1961 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1962 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1963 * to mc_filter_type.
1964 **/
1965static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1966{
1967 u32 vector = 0;
1968
1969 switch (hw->mac.mc_filter_type) {
b4617240 1970 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1971 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1972 break;
b4617240 1973 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1974 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1975 break;
b4617240 1976 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1977 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1978 break;
b4617240 1979 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1980 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1981 break;
b4617240 1982 default: /* Invalid mc_filter_type */
9a799d71
AK		 1983 hw_dbg(hw, "MC filter type param set incorrectly\n");
1984 break;
1985 }
1986
1987 /* vector can only be 12-bits or boundary will be exceeded */
1988 vector &= 0xFFF;
1989 return vector;
1990}
1991
1992/**
1993 * ixgbe_set_mta - Set bit-vector in multicast table
1994 * @hw: pointer to hardware structure
1995 * @hash_value: Multicast address hash value
1996 *
1997 * Sets the bit-vector in the multicast table.
1998 **/
1999static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2000{
2001 u32 vector;
2002 u32 vector_bit;
2003 u32 vector_reg;
9a799d71
AK		 2004
2005 hw->addr_ctrl.mta_in_use++;
2006
2007 vector = ixgbe_mta_vector(hw, mc_addr);
2008 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2009
2010 /*
2011 * The MTA is a register array of 128 32-bit registers. It is treated
2012 * like an array of 4096 bits. We want to set bit
2013 * BitArray[vector_value]. So we figure out what register the bit is
2014 * in, read it, OR in the new bit, then write back the new value. The
2015 * register is determined by the upper 7 bits of the vector value and
2016 * the bit within that register are determined by the lower 5 bits of
2017 * the value.
2018 */
2019 vector_reg = (vector >> 5) & 0x7F;
2020 vector_bit = vector & 0x1F;
80960ab0 2021 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 2022}
2023
9a799d71 2024/**
c44ade9e 2025 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 2026 * @hw: pointer to hardware structure
2853eb89 2027 * @netdev: pointer to net device structure
9a799d71
AK		 2028 *
2029 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 2030 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 2031 * registers for the first multicast addresses, and hashes the rest into the
2032 * multicast table.
2033 **/
2853eb89
JP		 2034s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2035 struct net_device *netdev)
9a799d71 2036{
22bedad3 2037 struct netdev_hw_addr *ha;
9a799d71 2038 u32 i;
9a799d71
AK		 2039
2040 /*
2041 * Set the new number of MC addresses that we are being requested to
2042 * use.
2043 */
2853eb89 2044 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2045 hw->addr_ctrl.mta_in_use = 0;
2046
80960ab0 2047 /* Clear mta_shadow */
9a799d71 2048 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2049 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2050
80960ab0 2051 /* Update mta shadow */
22bedad3 2052 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2053 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2054 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2055 }
2056
2057 /* Enable mta */
80960ab0
ET		 2058 for (i = 0; i < hw->mac.mcft_size; i++)
2059 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2060 hw->mac.mta_shadow[i]);
2061
9a799d71
AK		 2062 if (hw->addr_ctrl.mta_in_use > 0)
2063 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 2064 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2065
c44ade9e 2066 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2067 return 0;
2068}
2069
2070/**
c44ade9e 2071 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2072 * @hw: pointer to hardware structure
2073 *
c44ade9e 2074 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2075 **/
c44ade9e 2076s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2077{
c44ade9e 2078 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2079
c44ade9e
JB		 2080 if (a->mta_in_use > 0)
2081 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2082 hw->mac.mc_filter_type);
9a799d71
AK		 2083
2084 return 0;
2085}
2086
2087/**
c44ade9e 2088 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2089 * @hw: pointer to hardware structure
9a799d71 2090 *
c44ade9e 2091 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2092 **/
c44ade9e 2093s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2094{
c44ade9e 2095 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2096
c44ade9e
JB		 2097 if (a->mta_in_use > 0)
2098 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2099
2100 return 0;
2101}
2102
11afc1b1 2103/**
620fa036 2104 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2105 * @hw: pointer to hardware structure
11afc1b1
PW		 2106 *
2107 * Enable flow control according to the current settings.
2108 **/
041441d0 2109s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1
PW		 2110{
2111 s32 ret_val = 0;
620fa036 2112 u32 mflcn_reg, fccfg_reg;
11afc1b1 2113 u32 reg;
16b61beb 2114 u32 fcrtl, fcrth;
041441d0 2115 int i;
70b77628 2116
041441d0
AD		 2117 /*
2118 * Validate the water mark configuration for packet buffer 0. Zero
2119 * water marks indicate that the packet buffer was not configured
2120 * and the watermarks for packet buffer 0 should always be configured.
2121 */
2122 if (!hw->fc.low_water ||
2123 !hw->fc.high_water[0] ||
2124 !hw->fc.pause_time) {
2125 hw_dbg(hw, "Invalid water mark configuration\n");
2126 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2127 goto out;
041441d0 2128 }
70b77628 2129
620fa036 2130 /* Negotiate the fc mode to use */
786e9a5f 2131 ixgbe_fc_autoneg(hw);
11afc1b1 2132
620fa036 2133 /* Disable any previous flow control settings */
11afc1b1 2134 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2135 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2136
2137 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2138 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2139
2140 /*
2141 * The possible values of fc.current_mode are:
2142 * 0: Flow control is completely disabled
2143 * 1: Rx flow control is enabled (we can receive pause frames,
2144 * but not send pause frames).
bb3daa4a
PW		 2145 * 2: Tx flow control is enabled (we can send pause frames but
2146 * we do not support receiving pause frames).
11afc1b1
PW		 2147 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2148 * other: Invalid.
2149 */
2150 switch (hw->fc.current_mode) {
2151 case ixgbe_fc_none:
620fa036
MC		 2152 /*
2153 * Flow control is disabled by software override or autoneg.
2154 * The code below will actually disable it in the HW.
2155 */
11afc1b1
PW		 2156 break;
2157 case ixgbe_fc_rx_pause:
2158 /*
2159 * Rx Flow control is enabled and Tx Flow control is
2160 * disabled by software override. Since there really
2161 * isn't a way to advertise that we are capable of RX
2162 * Pause ONLY, we will advertise that we support both
2163 * symmetric and asymmetric Rx PAUSE. Later, we will
2164 * disable the adapter's ability to send PAUSE frames.
2165 */
2166 mflcn_reg |= IXGBE_MFLCN_RFCE;
2167 break;
2168 case ixgbe_fc_tx_pause:
2169 /*
2170 * Tx Flow control is enabled, and Rx Flow control is
2171 * disabled by software override.
2172 */
2173 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2174 break;
2175 case ixgbe_fc_full:
2176 /* Flow control (both Rx and Tx) is enabled by SW override. */
2177 mflcn_reg |= IXGBE_MFLCN_RFCE;
2178 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2179 break;
2180 default:
2181 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 2182 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 2183 goto out;
2184 break;
2185 }
2186
620fa036 2187 /* Set 802.3x based flow control settings. */
2132d381 2188 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2189 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2190 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2191
041441d0 2192 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
264857b8 2193
041441d0
AD		 2194 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2195 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2196 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2197 hw->fc.high_water[i]) {
2198 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2199 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2200 } else {
2201 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2202 /*
2203 * In order to prevent Tx hangs when the internal Tx
2204 * switch is enabled we must set the high water mark
2205 * to the maximum FCRTH value. This allows the Tx
2206 * switch to function even under heavy Rx workloads.
2207 */
2208 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2209 }
11afc1b1 2210
041441d0
AD		 2211 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2212 }
16b61beb 2213
11afc1b1 2214 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2215 reg = hw->fc.pause_time * 0x00010001;
2216 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2217 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2218
2219 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1
PW		 2220
2221out:
2222 return ret_val;
2223}
2224
0ecc061d 2225/**
67a79df2 2226 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2227 * @hw: pointer to hardware structure
67a79df2
AD		 2228 * @adv_reg: flow control advertised settings
2229 * @lp_reg: link partner's flow control settings
2230 * @adv_sym: symmetric pause bit in advertisement
2231 * @adv_asm: asymmetric pause bit in advertisement
2232 * @lp_sym: symmetric pause bit in link partner advertisement
2233 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2234 *
67a79df2
AD		 2235 * Find the intersection between advertised settings and link partner's
2236 * advertised settings
0ecc061d 2237 **/
67a79df2
AD		 2238static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2239 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2240{
67a79df2
AD		 2241 if ((!(adv_reg)) || (!(lp_reg)))
2242 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2243
67a79df2
AD		 2244 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2245 /*
2246 * Now we need to check if the user selected Rx ONLY
2247 * of pause frames. In this case, we had to advertise
2248 * FULL flow control because we could not advertise RX
2249 * ONLY. Hence, we must now check to see if we need to
2250 * turn OFF the TRANSMISSION of PAUSE frames.
2251 */
2252 if (hw->fc.requested_mode == ixgbe_fc_full) {
2253 hw->fc.current_mode = ixgbe_fc_full;
2254 hw_dbg(hw, "Flow Control = FULL.\n");
2255 } else {
2256 hw->fc.current_mode = ixgbe_fc_rx_pause;
2257 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2258 }
2259 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2260 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2261 hw->fc.current_mode = ixgbe_fc_tx_pause;
2262 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2263 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2264 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2265 hw->fc.current_mode = ixgbe_fc_rx_pause;
2266 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2267 } else {
67a79df2
AD		 2268 hw->fc.current_mode = ixgbe_fc_none;
2269 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2270 }
67a79df2 2271 return 0;
0b0c2b31
ET		 2272}
2273
2274/**
2275 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2276 * @hw: pointer to hardware structure
2277 *
2278 * Enable flow control according on 1 gig fiber.
2279 **/
2280static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2281{
2282 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
786e9a5f 2283 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02
PWJ		 2284
2285 /*
2286 * On multispeed fiber at 1g, bail out if
2287 * - link is up but AN did not complete, or if
2288 * - link is up and AN completed but timed out
2289 */
0b0c2b31
ET		 2290
2291 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2292 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2293 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
0b0c2b31 2294 goto out;
539e5f02 2295
0b0c2b31
ET		 2296 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2297 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2298
2299 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2300 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2301 IXGBE_PCS1GANA_ASM_PAUSE,
2302 IXGBE_PCS1GANA_SYM_PAUSE,
2303 IXGBE_PCS1GANA_ASM_PAUSE);
2304
2305out:
2306 return ret_val;
2307}
2308
2309/**
2310 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2311 * @hw: pointer to hardware structure
2312 *
2313 * Enable flow control according to IEEE clause 37.
2314 **/
2315static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2316{
2317 u32 links2, anlp1_reg, autoc_reg, links;
786e9a5f 2318 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2319
9bbe3a57 2320 /*
0b0c2b31
ET		 2321 * On backplane, bail out if
2322 * - backplane autoneg was not completed, or if
2323 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2324 */
0b0c2b31 2325 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2326 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
9bbe3a57 2327 goto out;
9bbe3a57 2328
0b0c2b31
ET		 2329 if (hw->mac.type == ixgbe_mac_82599EB) {
2330 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2331 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
0b0c2b31 2332 goto out;
0b0c2b31 2333 }
0ecc061d 2334 /*
0b0c2b31 2335 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2336 * local flow control settings accordingly
2337 */
0b0c2b31
ET		 2338 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2339 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2340
0b0c2b31
ET		 2341 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2342 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2343 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2344
2345out:
2346 return ret_val;
2347}
2348
2349/**
2350 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2351 * @hw: pointer to hardware structure
2352 *
2353 * Enable flow control according to IEEE clause 37.
2354 **/
2355static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2356{
2357 u16 technology_ability_reg = 0;
2358 u16 lp_technology_ability_reg = 0;
2359
2360 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2361 MDIO_MMD_AN,
2362 &technology_ability_reg);
2363 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2364 MDIO_MMD_AN,
2365 &lp_technology_ability_reg);
2366
2367 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2368 (u32)lp_technology_ability_reg,
2369 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2370 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2371}
2372
2373/**
67a79df2 2374 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2375 * @hw: pointer to hardware structure
2376 *
67a79df2
AD		 2377 * Compares our advertised flow control capabilities to those advertised by
2378 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2379 **/
67a79df2 2380void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2381{
67a79df2
AD		 2382 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2383 ixgbe_link_speed speed;
2384 bool link_up;
11afc1b1
PW		 2385
2386 /*
67a79df2
AD		 2387 * AN should have completed when the cable was plugged in.
2388 * Look for reasons to bail out. Bail out if:
2389 * - FC autoneg is disabled, or if
2390 * - link is not up.
2391 *
2392 * Since we're being called from an LSC, link is already known to be up.
2393 * So use link_up_wait_to_complete=false.
11afc1b1 2394 */
67a79df2 2395 if (hw->fc.disable_fc_autoneg)
620fa036 2396 goto out;
11afc1b1 2397
67a79df2
AD		 2398 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2399 if (!link_up)
11afc1b1 2400 goto out;
0b0c2b31
ET		 2401
2402 switch (hw->phy.media_type) {
67a79df2 2403 /* Autoneg flow control on fiber adapters */
0b0c2b31 2404 case ixgbe_media_type_fiber:
67a79df2
AD		 2405 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2406 ret_val = ixgbe_fc_autoneg_fiber(hw);
2407 break;
2408
2409 /* Autoneg flow control on backplane adapters */
0b0c2b31 2410 case ixgbe_media_type_backplane:
67a79df2 2411 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2412 break;
2413
67a79df2 2414 /* Autoneg flow control on copper adapters */
0b0c2b31 2415 case ixgbe_media_type_copper:
67a79df2
AD		 2416 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
2417 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2418 break;
2419
2420 default:
620fa036 2421 break;
0b0c2b31 2422 }
539e5f02 2423
11afc1b1 2424out:
67a79df2
AD		 2425 if (ret_val == 0) {
2426 hw->fc.fc_was_autonegged = true;
2427 } else {
2428 hw->fc.fc_was_autonegged = false;
2429 hw->fc.current_mode = hw->fc.requested_mode;
2430 }
11afc1b1
PW		 2431}
2432
9a799d71
AK		 2433/**
2434 * ixgbe_disable_pcie_master - Disable PCI-express master access
2435 * @hw: pointer to hardware structure
2436 *
2437 * Disables PCI-Express master access and verifies there are no pending
2438 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2439 * bit hasn't caused the master requests to be disabled, else 0
2440 * is returned signifying master requests disabled.
2441 **/
ff9d1a5a 2442static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2443{
a4297dc2 2444 struct ixgbe_adapter *adapter = hw->back;
a4297dc2 2445 s32 status = 0;
ff9d1a5a
ET		 2446 u32 i;
2447 u16 value;
2448
2449 /* Always set this bit to ensure any future transactions are blocked */
2450 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2451
ff9d1a5a 2452 /* Exit if master requests are blocked */
a4297dc2
ET		 2453 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2454 goto out;
9a799d71 2455
ff9d1a5a 2456 /* Poll for master request bit to clear */
9a799d71 2457 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2458 udelay(100);
ff9d1a5a
ET		 2459 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2460 goto out;
a4297dc2
ET		 2461 }
2462
ff9d1a5a
ET		 2463 /*
2464 * Two consecutive resets are required via CTRL.RST per datasheet
2465 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2466 * of this need. The first reset prevents new master requests from
2467 * being issued by our device. We then must wait 1usec or more for any
2468 * remaining completions from the PCIe bus to trickle in, and then reset
2469 * again to clear out any effects they may have had on our device.
2470 */
a4297dc2 2471 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2472 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2473
2474 /*
2475 * Before proceeding, make sure that the PCIe block does not have
2476 * transactions pending.
2477 */
a4297dc2 2478 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
9a799d71 2479 udelay(100);
ff9d1a5a
ET		 2480 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2481 &value);
2482 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2483 goto out;
9a799d71
AK		 2484 }
2485
ff9d1a5a
ET		 2486 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2487 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
a4297dc2
ET		 2488
2489out:
9a799d71
AK		 2490 return status;
2491}
2492
9a799d71 2493/**
c44ade9e 2494 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2495 * @hw: pointer to hardware structure
c44ade9e 2496 * @mask: Mask to specify which semaphore to acquire
9a799d71 2497 *
da74cd4a 2498 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2499 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2500 **/
2501s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2502{
2503 u32 gssr;
2504 u32 swmask = mask;
2505 u32 fwmask = mask << 5;
2506 s32 timeout = 200;
2507
2508 while (timeout) {
dbf893ee
ET		 2509 /*
2510 * SW EEPROM semaphore bit is used for access to all
2511 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2512 */
9a799d71 2513 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2514 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2515
2516 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2517 if (!(gssr & (fwmask | swmask)))
2518 break;
2519
2520 /*
2521 * Firmware currently using resource (fwmask) or other software
2522 * thread currently using resource (swmask)
2523 */
2524 ixgbe_release_eeprom_semaphore(hw);
032b4325 2525 usleep_range(5000, 10000);
9a799d71
AK		 2526 timeout--;
2527 }
2528
2529 if (!timeout) {
dbf893ee 2530 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2531 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2532 }
2533
2534 gssr |= swmask;
2535 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2536
2537 ixgbe_release_eeprom_semaphore(hw);
2538 return 0;
2539}
2540
2541/**
2542 * ixgbe_release_swfw_sync - Release SWFW semaphore
2543 * @hw: pointer to hardware structure
c44ade9e 2544 * @mask: Mask to specify which semaphore to release
9a799d71 2545 *
da74cd4a 2546 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2547 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2548 **/
2549void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2550{
2551 u32 gssr;
2552 u32 swmask = mask;
2553
2554 ixgbe_get_eeprom_semaphore(hw);
2555
2556 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2557 gssr &= ~swmask;
2558 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2559
2560 ixgbe_release_eeprom_semaphore(hw);
2561}
2562
d2f5e7f3
AS		 2563/**
2564 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2565 * @hw: pointer to hardware structure
2566 *
2567 * Stops the receive data path and waits for the HW to internally
2568 * empty the Rx security block.
2569 **/
2570s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2571{
2572#define IXGBE_MAX_SECRX_POLL 40
2573 int i;
2574 int secrxreg;
2575
2576 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2577 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2578 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2579 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2580 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2581 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2582 break;
2583 else
2584 /* Use interrupt-safe sleep just in case */
db76ad47 2585 udelay(1000);
d2f5e7f3
AS		 2586 }
2587
2588 /* For informational purposes only */
2589 if (i >= IXGBE_MAX_SECRX_POLL)
2590 hw_dbg(hw, "Rx unit being enabled before security "
2591 "path fully disabled. Continuing with init.\n");
2592
2593 return 0;
2594
2595}
2596
2597/**
2598 * ixgbe_enable_rx_buff - Enables the receive data path
2599 * @hw: pointer to hardware structure
2600 *
2601 * Enables the receive data path
2602 **/
2603s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2604{
2605 int secrxreg;
2606
2607 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2608 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2609 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2610 IXGBE_WRITE_FLUSH(hw);
2611
2612 return 0;
2613}
2614
11afc1b1
PW		 2615/**
2616 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2617 * @hw: pointer to hardware structure
2618 * @regval: register value to write to RXCTRL
2619 *
2620 * Enables the Rx DMA unit
2621 **/
2622s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2623{
2624 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2625
2626 return 0;
2627}
87c12017
PW		 2628
2629/**
2630 * ixgbe_blink_led_start_generic - Blink LED based on index.
2631 * @hw: pointer to hardware structure
2632 * @index: led number to blink
2633 **/
2634s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2635{
2636 ixgbe_link_speed speed = 0;
3db1cd5c 2637 bool link_up = false;
87c12017
PW		 2638 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2639 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
d7bbcd32 2640 s32 ret_val = 0;
87c12017
PW		 2641
2642 /*
2643 * Link must be up to auto-blink the LEDs;
2644 * Force it if link is down.
2645 */
2646 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2647
2648 if (!link_up) {
d7bbcd32
DS		 2649 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
2650 * LESM is on.
2651 */
2652 bool got_lock = false;
2653
2654 if ((hw->mac.type == ixgbe_mac_82599EB) &&
2655 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
2656 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
2657 IXGBE_GSSR_MAC_CSR_SM);
2658 if (ret_val)
2659 goto out;
2660
2661 got_lock = true;
2662 }
50ac58ba 2663 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2664 autoc_reg |= IXGBE_AUTOC_FLU;
2665 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
945a5151 2666 IXGBE_WRITE_FLUSH(hw);
d7bbcd32
DS		 2667
2668 if (got_lock)
2669 hw->mac.ops.release_swfw_sync(hw,
2670 IXGBE_GSSR_MAC_CSR_SM);
032b4325 2671 usleep_range(10000, 20000);
87c12017
PW		 2672 }
2673
2674 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2675 led_reg |= IXGBE_LED_BLINK(index);
2676 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2677 IXGBE_WRITE_FLUSH(hw);
2678
d7bbcd32
DS		 2679out:
2680 return ret_val;
87c12017
PW		 2681}
2682
2683/**
2684 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2685 * @hw: pointer to hardware structure
2686 * @index: led number to stop blinking
2687 **/
2688s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2689{
2690 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2691 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
d7bbcd32
DS		 2692 s32 ret_val = 0;
2693 bool got_lock = false;
2694
2695 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
2696 * LESM is on.
2697 */
2698 if ((hw->mac.type == ixgbe_mac_82599EB) &&
2699 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
2700 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
2701 IXGBE_GSSR_MAC_CSR_SM);
2702 if (ret_val)
2703 goto out;
2704
2705 got_lock = true;
2706 }
87c12017
PW		 2707
2708 autoc_reg &= ~IXGBE_AUTOC_FLU;
2709 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2710 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2711
d7bbcd32
DS		 2712 if (hw->mac.type == ixgbe_mac_82599EB)
2713 ixgbe_reset_pipeline_82599(hw);
2714
2715 if (got_lock)
2716 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
2717
87c12017
PW		 2718 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2719 led_reg &= ~IXGBE_LED_BLINK(index);
2720 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2721 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2722 IXGBE_WRITE_FLUSH(hw);
2723
d7bbcd32
DS		 2724out:
2725 return ret_val;
87c12017 2726}
21ce849b
MC		 2727
2728/**
2729 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2730 * @hw: pointer to hardware structure
2731 * @san_mac_offset: SAN MAC address offset
2732 *
2733 * This function will read the EEPROM location for the SAN MAC address
2734 * pointer, and returns the value at that location. This is used in both
2735 * get and set mac_addr routines.
2736 **/
2737static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2738 u16 *san_mac_offset)
2739{
2740 /*
2741 * First read the EEPROM pointer to see if the MAC addresses are
2742 * available.
2743 */
2744 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2745
2746 return 0;
2747}
2748
2749/**
2750 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2751 * @hw: pointer to hardware structure
2752 * @san_mac_addr: SAN MAC address
2753 *
2754 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2755 * per-port, so set_lan_id() must be called before reading the addresses.
2756 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2757 * upon for non-SFP connections, so we must call it here.
2758 **/
2759s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2760{
2761 u16 san_mac_data, san_mac_offset;
2762 u8 i;
2763
2764 /*
2765 * First read the EEPROM pointer to see if the MAC addresses are
2766 * available. If they're not, no point in calling set_lan_id() here.
2767 */
2768 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2769
2770 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2771 /*
2772 * No addresses available in this EEPROM. It's not an
2773 * error though, so just wipe the local address and return.
2774 */
2775 for (i = 0; i < 6; i++)
2776 san_mac_addr[i] = 0xFF;
2777
2778 goto san_mac_addr_out;
2779 }
2780
2781 /* make sure we know which port we need to program */
2782 hw->mac.ops.set_lan_id(hw);
2783 /* apply the port offset to the address offset */
2784 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2785 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2786 for (i = 0; i < 3; i++) {
2787 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2788 san_mac_addr[i * 2] = (u8)(san_mac_data);
2789 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2790 san_mac_offset++;
2791 }
2792
2793san_mac_addr_out:
2794 return 0;
2795}
2796
2797/**
2798 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2799 * @hw: pointer to hardware structure
2800 *
2801 * Read PCIe configuration space, and get the MSI-X vector count from
2802 * the capabilities table.
2803 **/
71161302 2804u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b
MC		 2805{
2806 struct ixgbe_adapter *adapter = hw->back;
71161302
ET		 2807 u16 msix_count = 1;
2808 u16 max_msix_count;
2809 u16 pcie_offset;
2810
2811 switch (hw->mac.type) {
2812 case ixgbe_mac_82598EB:
2813 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2814 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2815 break;
2816 case ixgbe_mac_82599EB:
2817 case ixgbe_mac_X540:
2818 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2819 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2820 break;
2821 default:
2822 return msix_count;
2823 }
2824
2825 pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
21ce849b
MC		 2826 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2827
71161302 2828 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2829 msix_count++;
2830
71161302
ET		 2831 if (msix_count > max_msix_count)
2832 msix_count = max_msix_count;
2833
21ce849b
MC		 2834 return msix_count;
2835}
2836
2837/**
2838 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2839 * @hw: pointer to hardware struct
2840 * @rar: receive address register index to disassociate
2841 * @vmdq: VMDq pool index to remove from the rar
2842 **/
2843s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2844{
2845 u32 mpsar_lo, mpsar_hi;
2846 u32 rar_entries = hw->mac.num_rar_entries;
2847
c700f4e6
ET		 2848 /* Make sure we are using a valid rar index range */
2849 if (rar >= rar_entries) {
2850 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2851 return IXGBE_ERR_INVALID_ARGUMENT;
2852 }
21ce849b 2853
c700f4e6
ET		 2854 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2855 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2856
c700f4e6
ET		 2857 if (!mpsar_lo && !mpsar_hi)
2858 goto done;
21ce849b 2859
c700f4e6
ET		 2860 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2861 if (mpsar_lo) {
2862 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2863 mpsar_lo = 0;
2864 }
2865 if (mpsar_hi) {
2866 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2867 mpsar_hi = 0;
2868 }
2869 } else if (vmdq < 32) {
2870 mpsar_lo &= ~(1 << vmdq);
2871 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2872 } else {
c700f4e6
ET		 2873 mpsar_hi &= ~(1 << (vmdq - 32));
2874 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2875 }
2876
c700f4e6
ET		 2877 /* was that the last pool using this rar? */
2878 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2879 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2880done:
2881 return 0;
2882}
2883
2884/**
2885 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2886 * @hw: pointer to hardware struct
2887 * @rar: receive address register index to associate with a VMDq index
2888 * @vmdq: VMDq pool index
2889 **/
2890s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2891{
2892 u32 mpsar;
2893 u32 rar_entries = hw->mac.num_rar_entries;
2894
c700f4e6
ET		 2895 /* Make sure we are using a valid rar index range */
2896 if (rar >= rar_entries) {
21ce849b 2897 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2898 return IXGBE_ERR_INVALID_ARGUMENT;
2899 }
2900
2901 if (vmdq < 32) {
2902 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2903 mpsar |= 1 << vmdq;
2904 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2905 } else {
2906 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2907 mpsar |= 1 << (vmdq - 32);
2908 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2909 }
2910 return 0;
2911}
2912
7fa7c9dc
AD		 2913/**
2914 * This function should only be involved in the IOV mode.
2915 * In IOV mode, Default pool is next pool after the number of
2916 * VFs advertized and not 0.
2917 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2918 *
2919 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2920 * @hw: pointer to hardware struct
2921 * @vmdq: VMDq pool index
2922 **/
2923s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2924{
2925 u32 rar = hw->mac.san_mac_rar_index;
2926
2927 if (vmdq < 32) {
2928 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2929 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2930 } else {
2931 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2932 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2933 }
2934
2935 return 0;
2936}
2937
21ce849b
MC		 2938/**
2939 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2940 * @hw: pointer to hardware structure
2941 **/
2942s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2943{
2944 int i;
2945
21ce849b
MC		 2946 for (i = 0; i < 128; i++)
2947 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2948
2949 return 0;
2950}
2951
2952/**
2953 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2954 * @hw: pointer to hardware structure
2955 * @vlan: VLAN id to write to VLAN filter
2956 *
2957 * return the VLVF index where this VLAN id should be placed
2958 *
2959 **/
5d5b7c39 2960static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2961{
2962 u32 bits = 0;
2963 u32 first_empty_slot = 0;
2964 s32 regindex;
2965
2966 /* short cut the special case */
2967 if (vlan == 0)
2968 return 0;
2969
2970 /*
2971 * Search for the vlan id in the VLVF entries. Save off the first empty
2972 * slot found along the way
2973 */
2974 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2975 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2976 if (!bits && !(first_empty_slot))
2977 first_empty_slot = regindex;
2978 else if ((bits & 0x0FFF) == vlan)
2979 break;
2980 }
2981
2982 /*
2983 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2984 * in the VLVF. Else use the first empty VLVF register for this
2985 * vlan id.
2986 */
2987 if (regindex >= IXGBE_VLVF_ENTRIES) {
2988 if (first_empty_slot)
2989 regindex = first_empty_slot;
2990 else {
2991 hw_dbg(hw, "No space in VLVF.\n");
2992 regindex = IXGBE_ERR_NO_SPACE;
2993 }
2994 }
2995
2996 return regindex;
2997}
2998
2999/**
3000 * ixgbe_set_vfta_generic - Set VLAN filter table
3001 * @hw: pointer to hardware structure
3002 * @vlan: VLAN id to write to VLAN filter
3003 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3004 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3005 *
3006 * Turn on/off specified VLAN in the VLAN filter table.
3007 **/
3008s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3009 bool vlan_on)
3010{
3011 s32 regindex;
3012 u32 bitindex;
3013 u32 vfta;
3014 u32 bits;
3015 u32 vt;
3016 u32 targetbit;
3017 bool vfta_changed = false;
3018
3019 if (vlan > 4095)
3020 return IXGBE_ERR_PARAM;
3021
3022 /*
3023 * this is a 2 part operation - first the VFTA, then the
3024 * VLVF and VLVFB if VT Mode is set
3025 * We don't write the VFTA until we know the VLVF part succeeded.
3026 */
3027
3028 /* Part 1
3029 * The VFTA is a bitstring made up of 128 32-bit registers
3030 * that enable the particular VLAN id, much like the MTA:
3031 * bits[11-5]: which register
3032 * bits[4-0]: which bit in the register
3033 */
3034 regindex = (vlan >> 5) & 0x7F;
3035 bitindex = vlan & 0x1F;
3036 targetbit = (1 << bitindex);
3037 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3038
3039 if (vlan_on) {
3040 if (!(vfta & targetbit)) {
3041 vfta |= targetbit;
3042 vfta_changed = true;
3043 }
3044 } else {
3045 if ((vfta & targetbit)) {
3046 vfta &= ~targetbit;
3047 vfta_changed = true;
3048 }
3049 }
3050
3051 /* Part 2
3052 * If VT Mode is set
3053 * Either vlan_on
3054 * make sure the vlan is in VLVF
3055 * set the vind bit in the matching VLVFB
3056 * Or !vlan_on
3057 * clear the pool bit and possibly the vind
3058 */
3059 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3060 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3061 s32 vlvf_index;
3062
3063 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3064 if (vlvf_index < 0)
3065 return vlvf_index;
3066
3067 if (vlan_on) {
3068 /* set the pool bit */
3069 if (vind < 32) {
3070 bits = IXGBE_READ_REG(hw,
3071 IXGBE_VLVFB(vlvf_index*2));
3072 bits |= (1 << vind);
3073 IXGBE_WRITE_REG(hw,
3074 IXGBE_VLVFB(vlvf_index*2),
3075 bits);
3076 } else {
3077 bits = IXGBE_READ_REG(hw,
3078 IXGBE_VLVFB((vlvf_index*2)+1));
3079 bits |= (1 << (vind-32));
3080 IXGBE_WRITE_REG(hw,
3081 IXGBE_VLVFB((vlvf_index*2)+1),
3082 bits);
3083 }
3084 } else {
3085 /* clear the pool bit */
3086 if (vind < 32) {
3087 bits = IXGBE_READ_REG(hw,
3088 IXGBE_VLVFB(vlvf_index*2));
3089 bits &= ~(1 << vind);
3090 IXGBE_WRITE_REG(hw,
3091 IXGBE_VLVFB(vlvf_index*2),
3092 bits);
3093 bits |= IXGBE_READ_REG(hw,
3094 IXGBE_VLVFB((vlvf_index*2)+1));
3095 } else {
3096 bits = IXGBE_READ_REG(hw,
3097 IXGBE_VLVFB((vlvf_index*2)+1));
3098 bits &= ~(1 << (vind-32));
3099 IXGBE_WRITE_REG(hw,
3100 IXGBE_VLVFB((vlvf_index*2)+1),
3101 bits);
3102 bits |= IXGBE_READ_REG(hw,
3103 IXGBE_VLVFB(vlvf_index*2));
3104 }
3105 }
3106
3107 /*
3108 * If there are still bits set in the VLVFB registers
3109 * for the VLAN ID indicated we need to see if the
3110 * caller is requesting that we clear the VFTA entry bit.
3111 * If the caller has requested that we clear the VFTA
3112 * entry bit but there are still pools/VFs using this VLAN
3113 * ID entry then ignore the request. We're not worried
3114 * about the case where we're turning the VFTA VLAN ID
3115 * entry bit on, only when requested to turn it off as
3116 * there may be multiple pools and/or VFs using the
3117 * VLAN ID entry. In that case we cannot clear the
3118 * VFTA bit until all pools/VFs using that VLAN ID have also
3119 * been cleared. This will be indicated by "bits" being
3120 * zero.
3121 */
3122 if (bits) {
3123 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3124 (IXGBE_VLVF_VIEN | vlan));
3125 if (!vlan_on) {
3126 /* someone wants to clear the vfta entry
3127 * but some pools/VFs are still using it.
3128 * Ignore it. */
3129 vfta_changed = false;
3130 }
3131 }
3132 else
3133 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3134 }
3135
3136 if (vfta_changed)
3137 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3138
3139 return 0;
3140}
3141
3142/**
3143 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3144 * @hw: pointer to hardware structure
3145 *
3146 * Clears the VLAN filer table, and the VMDq index associated with the filter
3147 **/
3148s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3149{
3150 u32 offset;
3151
3152 for (offset = 0; offset < hw->mac.vft_size; offset++)
3153 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3154
3155 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3156 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3157 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3158 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3159 }
3160
3161 return 0;
3162}
3163
3164/**
3165 * ixgbe_check_mac_link_generic - Determine link and speed status
3166 * @hw: pointer to hardware structure
3167 * @speed: pointer to link speed
3168 * @link_up: true when link is up
3169 * @link_up_wait_to_complete: bool used to wait for link up or not
3170 *
3171 * Reads the links register to determine if link is up and the current speed
3172 **/
3173s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3174 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3175{
48de36c5 3176 u32 links_reg, links_orig;
21ce849b
MC		 3177 u32 i;
3178
48de36c5
ET		 3179 /* clear the old state */
3180 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3181
21ce849b 3182 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3183
3184 if (links_orig != links_reg) {
3185 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3186 links_orig, links_reg);
3187 }
3188
21ce849b
MC		 3189 if (link_up_wait_to_complete) {
3190 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3191 if (links_reg & IXGBE_LINKS_UP) {
3192 *link_up = true;
3193 break;
3194 } else {
3195 *link_up = false;
3196 }
3197 msleep(100);
3198 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3199 }
3200 } else {
3201 if (links_reg & IXGBE_LINKS_UP)
3202 *link_up = true;
3203 else
3204 *link_up = false;
3205 }
3206
3207 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3208 IXGBE_LINKS_SPEED_10G_82599)
3209 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3210 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 3211 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 3212 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 3213 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3214 IXGBE_LINKS_SPEED_100_82599)
21ce849b 3215 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 3216 else
3217 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b 3218
21ce849b
MC		 3219 return 0;
3220}
a391f1d5
DS		 3221
3222/**
49ce9c2c 3223 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3224 * the EEPROM
3225 * @hw: pointer to hardware structure
3226 * @wwnn_prefix: the alternative WWNN prefix
3227 * @wwpn_prefix: the alternative WWPN prefix
3228 *
3229 * This function will read the EEPROM from the alternative SAN MAC address
3230 * block to check the support for the alternative WWNN/WWPN prefix support.
3231 **/
3232s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3233 u16 *wwpn_prefix)
3234{
3235 u16 offset, caps;
3236 u16 alt_san_mac_blk_offset;
3237
3238 /* clear output first */
3239 *wwnn_prefix = 0xFFFF;
3240 *wwpn_prefix = 0xFFFF;
3241
3242 /* check if alternative SAN MAC is supported */
3243 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3244 &alt_san_mac_blk_offset);
3245
3246 if ((alt_san_mac_blk_offset == 0) ||
3247 (alt_san_mac_blk_offset == 0xFFFF))
3248 goto wwn_prefix_out;
3249
3250 /* check capability in alternative san mac address block */
3251 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3252 hw->eeprom.ops.read(hw, offset, &caps);
3253 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3254 goto wwn_prefix_out;
3255
3256 /* get the corresponding prefix for WWNN/WWPN */
3257 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3258 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3259
3260 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3261 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3262
3263wwn_prefix_out:
3264 return 0;
3265}
a985b6c3
GR		 3266
3267/**
3268 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3269 * @hw: pointer to hardware structure
3270 * @enable: enable or disable switch for anti-spoofing
3271 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3272 *
3273 **/
3274void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3275{
3276 int j;
3277 int pf_target_reg = pf >> 3;
3278 int pf_target_shift = pf % 8;
3279 u32 pfvfspoof = 0;
3280
3281 if (hw->mac.type == ixgbe_mac_82598EB)
3282 return;
3283
3284 if (enable)
3285 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3286
3287 /*
3288 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3289 * MAC anti-spoof enables in each register array element.
3290 */
ef89e0a2 3291 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3292 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3293
a985b6c3
GR		 3294 /*
3295 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3296 * emulation mode NICs. Do not set the bits assigned to the PF
3297 */
3298 pfvfspoof &= (1 << pf_target_shift) - 1;
3299 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3300
3301 /*
3302 * Remaining pools belong to the PF so they do not need to have
3303 * anti-spoofing enabled.
a985b6c3 3304 */
ef89e0a2
AD		 3305 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3306 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3307}
3308
3309/**
3310 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3311 * @hw: pointer to hardware structure
3312 * @enable: enable or disable switch for VLAN anti-spoofing
3313 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3314 *
3315 **/
3316void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3317{
3318 int vf_target_reg = vf >> 3;
3319 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3320 u32 pfvfspoof;
3321
3322 if (hw->mac.type == ixgbe_mac_82598EB)
3323 return;
3324
3325 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3326 if (enable)
3327 pfvfspoof |= (1 << vf_target_shift);
3328 else
3329 pfvfspoof &= ~(1 << vf_target_shift);
3330 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3331}
b776d104
ET		 3332
3333/**
3334 * ixgbe_get_device_caps_generic - Get additional device capabilities
3335 * @hw: pointer to hardware structure
3336 * @device_caps: the EEPROM word with the extra device capabilities
3337 *
3338 * This function will read the EEPROM location for the device capabilities,
3339 * and return the word through device_caps.
3340 **/
3341s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3342{
3343 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3344
3345 return 0;
3346}
80605c65
JF		 3347
3348/**
3349 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3350 * @hw: pointer to hardware structure
3351 * @num_pb: number of packet buffers to allocate
3352 * @headroom: reserve n KB of headroom
3353 * @strategy: packet buffer allocation strategy
3354 **/
3355void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3356 int num_pb,
3357 u32 headroom,
3358 int strategy)
3359{
3360 u32 pbsize = hw->mac.rx_pb_size;
3361 int i = 0;
3362 u32 rxpktsize, txpktsize, txpbthresh;
3363
3364 /* Reserve headroom */
3365 pbsize -= headroom;
3366
3367 if (!num_pb)
3368 num_pb = 1;
3369
3370 /* Divide remaining packet buffer space amongst the number
3371 * of packet buffers requested using supplied strategy.
3372 */
3373 switch (strategy) {
3374 case (PBA_STRATEGY_WEIGHTED):
3375 /* pba_80_48 strategy weight first half of packet buffer with
3376 * 5/8 of the packet buffer space.
3377 */
3378 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3379 pbsize -= rxpktsize * (num_pb / 2);
3380 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3381 for (; i < (num_pb / 2); i++)
3382 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3383 /* Fall through to configure remaining packet buffers */
3384 case (PBA_STRATEGY_EQUAL):
3385 /* Divide the remaining Rx packet buffer evenly among the TCs */
3386 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3387 for (; i < num_pb; i++)
3388 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3389 break;
3390 default:
3391 break;
3392 }
3393
3394 /*
3395 * Setup Tx packet buffer and threshold equally for all TCs
3396 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3397 * 10 since the largest packet we support is just over 9K.
3398 */
3399 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3400 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3401 for (i = 0; i < num_pb; i++) {
3402 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3403 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3404 }
3405
3406 /* Clear unused TCs, if any, to zero buffer size*/
3407 for (; i < IXGBE_MAX_PB; i++) {
3408 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3409 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3410 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3411 }
3412}
9612de92
ET		 3413
3414/**
3415 * ixgbe_calculate_checksum - Calculate checksum for buffer
3416 * @buffer: pointer to EEPROM
3417 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3418 *
9612de92
ET		 3419 * Calculates the checksum for some buffer on a specified length. The
3420 * checksum calculated is returned.
3421 **/
3422static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3423{
3424 u32 i;
3425 u8 sum = 0;
3426
3427 if (!buffer)
3428 return 0;
3429
3430 for (i = 0; i < length; i++)
3431 sum += buffer[i];
3432
3433 return (u8) (0 - sum);
3434}
3435
3436/**
3437 * ixgbe_host_interface_command - Issue command to manageability block
3438 * @hw: pointer to the HW structure
3439 * @buffer: contains the command to write and where the return status will
3440 * be placed
c466d7a7 3441 * @length: length of buffer, must be multiple of 4 bytes
9612de92
ET		 3442 *
3443 * Communicates with the manageability block. On success return 0
3444 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3445 **/
79488c58 3446static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
9612de92
ET		 3447 u32 length)
3448{
331bcf45 3449 u32 hicr, i, bi;
9612de92
ET		 3450 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3451 u8 buf_len, dword_len;
3452
3453 s32 ret_val = 0;
3454
3455 if (length == 0 || length & 0x3 ||
3456 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3457 hw_dbg(hw, "Buffer length failure.\n");
3458 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3459 goto out;
3460 }
3461
3462 /* Check that the host interface is enabled. */
3463 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3464 if ((hicr & IXGBE_HICR_EN) == 0) {
3465 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3466 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3467 goto out;
3468 }
3469
3470 /* Calculate length in DWORDs */
3471 dword_len = length >> 2;
3472
3473 /*
3474 * The device driver writes the relevant command block
3475 * into the ram area.
3476 */
3477 for (i = 0; i < dword_len; i++)
3478 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3479 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3480
3481 /* Setting this bit tells the ARC that a new command is pending. */
3482 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3483
3484 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3485 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3486 if (!(hicr & IXGBE_HICR_C))
3487 break;
3488 usleep_range(1000, 2000);
3489 }
3490
3491 /* Check command successful completion. */
3492 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3493 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3494 hw_dbg(hw, "Command has failed with no status valid.\n");
3495 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3496 goto out;
3497 }
3498
3499 /* Calculate length in DWORDs */
3500 dword_len = hdr_size >> 2;
3501
3502 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3503 for (bi = 0; bi < dword_len; bi++) {
3504 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3505 le32_to_cpus(&buffer[bi]);
79488c58 3506 }
9612de92
ET		 3507
3508 /* If there is any thing in data position pull it in */
3509 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3510 if (buf_len == 0)
3511 goto out;
3512
3513 if (length < (buf_len + hdr_size)) {
3514 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3515 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3516 goto out;
3517 }
3518
331bcf45
ET		 3519 /* Calculate length in DWORDs, add 3 for odd lengths */
3520 dword_len = (buf_len + 3) >> 2;
9612de92 3521
331bcf45
ET		 3522 /* Pull in the rest of the buffer (bi is where we left off)*/
3523 for (; bi <= dword_len; bi++) {
3524 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3525 le32_to_cpus(&buffer[bi]);
3526 }
9612de92
ET		 3527
3528out:
3529 return ret_val;
3530}
3531
3532/**
3533 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3534 * @hw: pointer to the HW structure
3535 * @maj: driver version major number
3536 * @min: driver version minor number
3537 * @build: driver version build number
3538 * @sub: driver version sub build number
3539 *
3540 * Sends driver version number to firmware through the manageability
3541 * block. On success return 0
3542 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3543 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3544 **/
3545s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3546 u8 build, u8 sub)
3547{
3548 struct ixgbe_hic_drv_info fw_cmd;
3549 int i;
3550 s32 ret_val = 0;
3551
3552 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3553 ret_val = IXGBE_ERR_SWFW_SYNC;
3554 goto out;
3555 }
3556
3557 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3558 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3559 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3560 fw_cmd.port_num = (u8)hw->bus.func;
3561 fw_cmd.ver_maj = maj;
3562 fw_cmd.ver_min = min;
3563 fw_cmd.ver_build = build;
3564 fw_cmd.ver_sub = sub;
3565 fw_cmd.hdr.checksum = 0;
3566 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3567 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3568 fw_cmd.pad = 0;
3569 fw_cmd.pad2 = 0;
3570
3571 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3572 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
9612de92
ET		 3573 sizeof(fw_cmd));
3574 if (ret_val != 0)
3575 continue;
3576
3577 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3578 FW_CEM_RESP_STATUS_SUCCESS)
3579 ret_val = 0;
3580 else
3581 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3582
3583 break;
3584 }
3585
3586 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3587out:
3588 return ret_val;
3589}
ff9d1a5a
ET		 3590
3591/**
3592 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3593 * @hw: pointer to the hardware structure
3594 *
3595 * The 82599 and x540 MACs can experience issues if TX work is still pending
3596 * when a reset occurs. This function prevents this by flushing the PCIe
3597 * buffers on the system.
3598 **/
3599void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3600{
3601 u32 gcr_ext, hlreg0;
3602
3603 /*
3604 * If double reset is not requested then all transactions should
3605 * already be clear and as such there is no work to do
3606 */
3607 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3608 return;
3609
3610 /*
3611 * Set loopback enable to prevent any transmits from being sent
3612 * should the link come up. This assumes that the RXCTRL.RXEN bit
3613 * has already been cleared.
3614 */
3615 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3616 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3617
3618 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3619 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3620 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3621 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3622
3623 /* Flush all writes and allow 20usec for all transactions to clear */
3624 IXGBE_WRITE_FLUSH(hw);
3625 udelay(20);
3626
3627 /* restore previous register values */
3628 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3629 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3630}
e1ea9158
DS		 3631
3632static const u8 ixgbe_emc_temp_data[4] = {
3633 IXGBE_EMC_INTERNAL_DATA,
3634 IXGBE_EMC_DIODE1_DATA,
3635 IXGBE_EMC_DIODE2_DATA,
3636 IXGBE_EMC_DIODE3_DATA
3637};
3638static const u8 ixgbe_emc_therm_limit[4] = {
3639 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3640 IXGBE_EMC_DIODE1_THERM_LIMIT,
3641 IXGBE_EMC_DIODE2_THERM_LIMIT,
3642 IXGBE_EMC_DIODE3_THERM_LIMIT
3643};
3644
3645/**
3646 * ixgbe_get_ets_data - Extracts the ETS bit data
3647 * @hw: pointer to hardware structure
3648 * @ets_cfg: extected ETS data
3649 * @ets_offset: offset of ETS data
3650 *
3651 * Returns error code.
3652 **/
3653static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3654 u16 *ets_offset)
3655{
3656 s32 status = 0;
3657
3658 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3659 if (status)
3660 goto out;
3661
3662 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
3663 status = IXGBE_NOT_IMPLEMENTED;
3664 goto out;
3665 }
3666
3667 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3668 if (status)
3669 goto out;
3670
3671 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
3672 status = IXGBE_NOT_IMPLEMENTED;
3673 goto out;
3674 }
3675
3676out:
3677 return status;
3678}
3679
3680/**
3681 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3682 * @hw: pointer to hardware structure
3683 *
3684 * Returns the thermal sensor data structure
3685 **/
3686s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3687{
3688 s32 status = 0;
3689 u16 ets_offset;
3690 u16 ets_cfg;
3691 u16 ets_sensor;
3692 u8 num_sensors;
3693 u8 i;
3694 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3695
3ca8bc6d
DS		 3696 /* Only support thermal sensors attached to physical port 0 */
3697 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
e1ea9158
DS		 3698 status = IXGBE_NOT_IMPLEMENTED;
3699 goto out;
3700 }
3701
3702 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3703 if (status)
3704 goto out;
3705
3706 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3707 if (num_sensors > IXGBE_MAX_SENSORS)
3708 num_sensors = IXGBE_MAX_SENSORS;
3709
3710 for (i = 0; i < num_sensors; i++) {
3711 u8 sensor_index;
3712 u8 sensor_location;
3713
3714 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3715 &ets_sensor);
3716 if (status)
3717 goto out;
3718
3719 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3720 IXGBE_ETS_DATA_INDEX_SHIFT);
3721 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3722 IXGBE_ETS_DATA_LOC_SHIFT);
3723
3724 if (sensor_location != 0) {
3725 status = hw->phy.ops.read_i2c_byte(hw,
3726 ixgbe_emc_temp_data[sensor_index],
3727 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3728 &data->sensor[i].temp);
3729 if (status)
3730 goto out;
3731 }
3732 }
3733out:
3734 return status;
3735}
3736
3737/**
3738 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3739 * @hw: pointer to hardware structure
3740 *
3741 * Inits the thermal sensor thresholds according to the NVM map
3742 * and save off the threshold and location values into mac.thermal_sensor_data
3743 **/
3744s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3745{
3746 s32 status = 0;
3747 u16 ets_offset;
3748 u16 ets_cfg;
3749 u16 ets_sensor;
3750 u8 low_thresh_delta;
3751 u8 num_sensors;
3752 u8 therm_limit;
3753 u8 i;
3754 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3755
3756 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3757
3ca8bc6d
DS		 3758 /* Only support thermal sensors attached to physical port 0 */
3759 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
e1ea9158
DS		 3760 status = IXGBE_NOT_IMPLEMENTED;
3761 goto out;
3762 }
3763
3764 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3765 if (status)
3766 goto out;
3767
3768 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3769 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3770 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3771 if (num_sensors > IXGBE_MAX_SENSORS)
3772 num_sensors = IXGBE_MAX_SENSORS;
3773
3774 for (i = 0; i < num_sensors; i++) {
3775 u8 sensor_index;
3776 u8 sensor_location;
3777
3778 hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
3779 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3780 IXGBE_ETS_DATA_INDEX_SHIFT);
3781 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3782 IXGBE_ETS_DATA_LOC_SHIFT);
3783 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3784
3785 hw->phy.ops.write_i2c_byte(hw,
3786 ixgbe_emc_therm_limit[sensor_index],
3787 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3788
3789 if (sensor_location == 0)
3790 continue;
3791
3792 data->sensor[i].location = sensor_location;
3793 data->sensor[i].caution_thresh = therm_limit;
3794 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3795 }
3796out:
3797 return status;
3798}
3799
Linux kernel - Deliverables
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