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ixgbe: Simplify definitions for regidx and bit in set_vfta
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
48b44612 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
ccffad25 32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 44 u16 count);
c44ade9e
JB		 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 49
9a799d71 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
ff9d1a5a 58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 59
9a900eca
DS		 60/* Base table for registers values that change by MAC */
61const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
62 IXGBE_MVALS_INIT(8259X)
63};
64
67a79df2
AD		 65/**
66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
67 * control
68 * @hw: pointer to hardware structure
69 *
70 * There are several phys that do not support autoneg flow control. This
71 * function check the device id to see if the associated phy supports
72 * autoneg flow control.
73 **/
73d80953 74bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2 75{
73d80953
DS		 76 bool supported = false;
77 ixgbe_link_speed speed;
78 bool link_up;
67a79df2 79
73d80953
DS		 80 switch (hw->phy.media_type) {
81 case ixgbe_media_type_fiber:
82 hw->mac.ops.check_link(hw, &speed, &link_up, false);
83 /* if link is down, assume supported */
84 if (link_up)
85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
86 true : false;
87 else
88 supported = true;
89 break;
90 case ixgbe_media_type_backplane:
91 supported = true;
92 break;
93 case ixgbe_media_type_copper:
94 /* only some copper devices support flow control autoneg */
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82599_T3_LOM:
97 case IXGBE_DEV_ID_X540T:
98 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 99 case IXGBE_DEV_ID_X550T:
100 case IXGBE_DEV_ID_X550EM_X_10G_T:
73d80953
DS		 101 supported = true;
102 break;
103 default:
104 break;
105 }
67a79df2 106 default:
73d80953 107 break;
67a79df2 108 }
73d80953
DS		 109
110 return supported;
67a79df2
AD		 111}
112
113/**
114 * ixgbe_setup_fc - Set up flow control
115 * @hw: pointer to hardware structure
116 *
117 * Called at init time to set up flow control.
118 **/
041441d0 119static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 120{
121 s32 ret_val = 0;
122 u32 reg = 0, reg_bp = 0;
123 u16 reg_cu = 0;
429d6a3b 124 bool locked = false;
67a79df2 125
67a79df2
AD		 126 /*
127 * Validate the requested mode. Strict IEEE mode does not allow
128 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
129 */
130 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
131 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
e90dd264 132 return IXGBE_ERR_INVALID_LINK_SETTINGS;
67a79df2
AD		 133 }
134
135 /*
136 * 10gig parts do not have a word in the EEPROM to determine the
137 * default flow control setting, so we explicitly set it to full.
138 */
139 if (hw->fc.requested_mode == ixgbe_fc_default)
140 hw->fc.requested_mode = ixgbe_fc_full;
141
142 /*
143 * Set up the 1G and 10G flow control advertisement registers so the
144 * HW will be able to do fc autoneg once the cable is plugged in. If
145 * we link at 10G, the 1G advertisement is harmless and vice versa.
146 */
67a79df2 147 switch (hw->phy.media_type) {
429d6a3b
DS		 148 case ixgbe_media_type_backplane:
149 /* some MAC's need RMW protection on AUTOC */
150 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
f8cf7a00 151 if (ret_val)
e90dd264 152 return ret_val;
429d6a3b
DS		 153
154 /* only backplane uses autoc so fall though */
67a79df2 155 case ixgbe_media_type_fiber:
67a79df2 156 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
429d6a3b 157
67a79df2 158 break;
67a79df2
AD		 159 case ixgbe_media_type_copper:
160 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
161 MDIO_MMD_AN, &reg_cu);
162 break;
67a79df2 163 default:
041441d0 164 break;
67a79df2
AD		 165 }
166
167 /*
168 * The possible values of fc.requested_mode are:
169 * 0: Flow control is completely disabled
170 * 1: Rx flow control is enabled (we can receive pause frames,
171 * but not send pause frames).
172 * 2: Tx flow control is enabled (we can send pause frames but
173 * we do not support receiving pause frames).
174 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 175 * other: Invalid.
176 */
177 switch (hw->fc.requested_mode) {
178 case ixgbe_fc_none:
179 /* Flow control completely disabled by software override. */
180 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
181 if (hw->phy.media_type == ixgbe_media_type_backplane)
182 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
183 IXGBE_AUTOC_ASM_PAUSE);
184 else if (hw->phy.media_type == ixgbe_media_type_copper)
185 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
186 break;
67a79df2
AD		 187 case ixgbe_fc_tx_pause:
188 /*
189 * Tx Flow control is enabled, and Rx Flow control is
190 * disabled by software override.
191 */
041441d0
AD		 192 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
193 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 194 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 195 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
196 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 197 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 198 reg_cu |= IXGBE_TAF_ASM_PAUSE;
199 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 200 }
201 break;
041441d0
AD		 202 case ixgbe_fc_rx_pause:
203 /*
204 * Rx Flow control is enabled and Tx Flow control is
205 * disabled by software override. Since there really
206 * isn't a way to advertise that we are capable of RX
207 * Pause ONLY, we will advertise that we support both
208 * symmetric and asymmetric Rx PAUSE, as such we fall
209 * through to the fc_full statement. Later, we will
210 * disable the adapter's ability to send PAUSE frames.
211 */
67a79df2
AD		 212 case ixgbe_fc_full:
213 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 214 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 215 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 216 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
217 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 218 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 219 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 220 break;
67a79df2
AD		 221 default:
222 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 223 return IXGBE_ERR_CONFIG;
67a79df2
AD		 224 }
225
226 if (hw->mac.type != ixgbe_mac_X540) {
227 /*
228 * Enable auto-negotiation between the MAC & PHY;
229 * the MAC will advertise clause 37 flow control.
230 */
231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
232 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
233
234 /* Disable AN timeout */
235 if (hw->fc.strict_ieee)
236 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
237
238 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
239 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
240 }
241
242 /*
243 * AUTOC restart handles negotiation of 1G and 10G on backplane
244 * and copper. There is no need to set the PCS1GCTL register.
245 *
246 */
247 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 248 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
249 * LESM is on, likewise reset_pipeline requries the lock as
250 * it also writes AUTOC.
251 */
429d6a3b
DS		 252 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
253 if (ret_val)
e90dd264 254 return ret_val;
d7bbcd32 255
67a79df2 256 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
429d6a3b 257 ixgbe_device_supports_autoneg_fc(hw)) {
67a79df2
AD		 258 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
259 MDIO_MMD_AN, reg_cu);
260 }
261
262 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
67a79df2
AD		 263 return ret_val;
264}
265
9a799d71 266/**
c44ade9e 267 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 268 * @hw: pointer to hardware structure
269 *
270 * Starts the hardware by filling the bus info structure and media type, clears
271 * all on chip counters, initializes receive address registers, multicast
272 * table, VLAN filter table, calls routine to set up link and flow control
273 * settings, and leaves transmit and receive units disabled and uninitialized
274 **/
c44ade9e 275s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71 276{
e5776620 277 s32 ret_val;
9a799d71
AK		 278 u32 ctrl_ext;
279
280 /* Set the media type */
281 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
282
283 /* Identify the PHY */
c44ade9e 284 hw->phy.ops.identify(hw);
9a799d71 285
9a799d71 286 /* Clear the VLAN filter table */
c44ade9e 287 hw->mac.ops.clear_vfta(hw);
9a799d71 288
9a799d71 289 /* Clear statistics registers */
c44ade9e 290 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 291
292 /* Set No Snoop Disable */
293 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
294 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
295 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 296 IXGBE_WRITE_FLUSH(hw);
9a799d71 297
620fa036 298 /* Setup flow control */
e5776620 299 ret_val = ixgbe_setup_fc(hw);
3507a9b8
MR		 300 if (ret_val)
301 return ret_val;
620fa036 302
9a799d71
AK		 303 /* Clear adapter stopped flag */
304 hw->adapter_stopped = false;
305
3507a9b8 306 return 0;
9a799d71
AK		 307}
308
7184b7cf
ET		 309/**
310 * ixgbe_start_hw_gen2 - Init sequence for common device family
311 * @hw: pointer to hw structure
312 *
313 * Performs the init sequence common to the second generation
314 * of 10 GbE devices.
315 * Devices in the second generation:
316 * 82599
317 * X540
318 **/
319s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
320{
321 u32 i;
322
323 /* Clear the rate limiters */
324 for (i = 0; i < hw->mac.max_tx_queues; i++) {
325 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
326 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
327 }
328 IXGBE_WRITE_FLUSH(hw);
329
887012e8 330#ifndef CONFIG_SPARC
3d5c5207
ET		 331 /* Disable relaxed ordering */
332 for (i = 0; i < hw->mac.max_tx_queues; i++) {
887012e8
JK		 333 u32 regval;
334
3d5c5207 335 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 336 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 337 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
338 }
339
340 for (i = 0; i < hw->mac.max_rx_queues; i++) {
887012e8
JK		 341 u32 regval;
342
3d5c5207 343 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 344 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
345 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 346 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
347 }
887012e8 348#endif
7184b7cf
ET		 349 return 0;
350}
351
9a799d71 352/**
c44ade9e 353 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 354 * @hw: pointer to hardware structure
355 *
c44ade9e 356 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 357 * structure and media type, clears all on chip counters, initializes receive
358 * address registers, multicast table, VLAN filter table, calls routine to set
359 * up link and flow control settings, and leaves transmit and receive units
360 * disabled and uninitialized
361 **/
c44ade9e 362s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 363{
794caeb2
PWJ		 364 s32 status;
365
9a799d71 366 /* Reset the hardware */
794caeb2 367 status = hw->mac.ops.reset_hw(hw);
9a799d71 368
794caeb2
PWJ		 369 if (status == 0) {
370 /* Start the HW */
371 status = hw->mac.ops.start_hw(hw);
372 }
9a799d71 373
794caeb2 374 return status;
9a799d71
AK		 375}
376
377/**
c44ade9e 378 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 379 * @hw: pointer to hardware structure
380 *
381 * Clears all hardware statistics counters by reading them from the hardware
382 * Statistics counters are clear on read.
383 **/
c44ade9e 384s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 385{
386 u16 i = 0;
387
388 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
389 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
390 IXGBE_READ_REG(hw, IXGBE_ERRBC);
391 IXGBE_READ_REG(hw, IXGBE_MSPDC);
392 for (i = 0; i < 8; i++)
393 IXGBE_READ_REG(hw, IXGBE_MPC(i));
394
395 IXGBE_READ_REG(hw, IXGBE_MLFC);
396 IXGBE_READ_REG(hw, IXGBE_MRFC);
397 IXGBE_READ_REG(hw, IXGBE_RLEC);
398 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 399 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 400 if (hw->mac.type >= ixgbe_mac_82599EB) {
401 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
402 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
403 } else {
404 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
405 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
406 }
9a799d71
AK		 407
408 for (i = 0; i < 8; i++) {
409 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 410 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 411 if (hw->mac.type >= ixgbe_mac_82599EB) {
412 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
413 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
414 } else {
415 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
416 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
417 }
9a799d71 418 }
667c7565
ET		 419 if (hw->mac.type >= ixgbe_mac_82599EB)
420 for (i = 0; i < 8; i++)
421 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 422 IXGBE_READ_REG(hw, IXGBE_PRC64);
423 IXGBE_READ_REG(hw, IXGBE_PRC127);
424 IXGBE_READ_REG(hw, IXGBE_PRC255);
425 IXGBE_READ_REG(hw, IXGBE_PRC511);
426 IXGBE_READ_REG(hw, IXGBE_PRC1023);
427 IXGBE_READ_REG(hw, IXGBE_PRC1522);
428 IXGBE_READ_REG(hw, IXGBE_GPRC);
429 IXGBE_READ_REG(hw, IXGBE_BPRC);
430 IXGBE_READ_REG(hw, IXGBE_MPRC);
431 IXGBE_READ_REG(hw, IXGBE_GPTC);
432 IXGBE_READ_REG(hw, IXGBE_GORCL);
433 IXGBE_READ_REG(hw, IXGBE_GORCH);
434 IXGBE_READ_REG(hw, IXGBE_GOTCL);
435 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 436 if (hw->mac.type == ixgbe_mac_82598EB)
437 for (i = 0; i < 8; i++)
438 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 439 IXGBE_READ_REG(hw, IXGBE_RUC);
440 IXGBE_READ_REG(hw, IXGBE_RFC);
441 IXGBE_READ_REG(hw, IXGBE_ROC);
442 IXGBE_READ_REG(hw, IXGBE_RJC);
443 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
444 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
445 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
446 IXGBE_READ_REG(hw, IXGBE_TORL);
447 IXGBE_READ_REG(hw, IXGBE_TORH);
448 IXGBE_READ_REG(hw, IXGBE_TPR);
449 IXGBE_READ_REG(hw, IXGBE_TPT);
450 IXGBE_READ_REG(hw, IXGBE_PTC64);
451 IXGBE_READ_REG(hw, IXGBE_PTC127);
452 IXGBE_READ_REG(hw, IXGBE_PTC255);
453 IXGBE_READ_REG(hw, IXGBE_PTC511);
454 IXGBE_READ_REG(hw, IXGBE_PTC1023);
455 IXGBE_READ_REG(hw, IXGBE_PTC1522);
456 IXGBE_READ_REG(hw, IXGBE_MPTC);
457 IXGBE_READ_REG(hw, IXGBE_BPTC);
458 for (i = 0; i < 16; i++) {
459 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 460 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 461 if (hw->mac.type >= ixgbe_mac_82599EB) {
462 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
463 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
464 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
465 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
467 } else {
468 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
469 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
470 }
9a799d71
AK		 471 }
472
e87ce1cd 473 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
a3aeea0e
ET		 474 if (hw->phy.id == 0)
475 hw->phy.ops.identify(hw);
c1085b10
ET		 476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
477 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
479 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 480 }
481
9a799d71
AK		 482 return 0;
483}
484
485/**
289700db 486 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 487 * @hw: pointer to hardware structure
289700db
DS		 488 * @pba_num: stores the part number string from the EEPROM
489 * @pba_num_size: part number string buffer length
c44ade9e 490 *
289700db 491 * Reads the part number string from the EEPROM.
c44ade9e 492 **/
289700db 493s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 494 u32 pba_num_size)
c44ade9e
JB		 495{
496 s32 ret_val;
497 u16 data;
289700db
DS		 498 u16 pba_ptr;
499 u16 offset;
500 u16 length;
501
502 if (pba_num == NULL) {
503 hw_dbg(hw, "PBA string buffer was null\n");
504 return IXGBE_ERR_INVALID_ARGUMENT;
505 }
c44ade9e
JB		 506
507 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
508 if (ret_val) {
509 hw_dbg(hw, "NVM Read Error\n");
510 return ret_val;
511 }
c44ade9e 512
289700db 513 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 514 if (ret_val) {
515 hw_dbg(hw, "NVM Read Error\n");
516 return ret_val;
517 }
289700db
DS		 518
519 /*
520 * if data is not ptr guard the PBA must be in legacy format which
521 * means pba_ptr is actually our second data word for the PBA number
522 * and we can decode it into an ascii string
523 */
524 if (data != IXGBE_PBANUM_PTR_GUARD) {
525 hw_dbg(hw, "NVM PBA number is not stored as string\n");
526
527 /* we will need 11 characters to store the PBA */
528 if (pba_num_size < 11) {
529 hw_dbg(hw, "PBA string buffer too small\n");
530 return IXGBE_ERR_NO_SPACE;
531 }
532
533 /* extract hex string from data and pba_ptr */
534 pba_num[0] = (data >> 12) & 0xF;
535 pba_num[1] = (data >> 8) & 0xF;
536 pba_num[2] = (data >> 4) & 0xF;
537 pba_num[3] = data & 0xF;
538 pba_num[4] = (pba_ptr >> 12) & 0xF;
539 pba_num[5] = (pba_ptr >> 8) & 0xF;
540 pba_num[6] = '-';
541 pba_num[7] = 0;
542 pba_num[8] = (pba_ptr >> 4) & 0xF;
543 pba_num[9] = pba_ptr & 0xF;
544
545 /* put a null character on the end of our string */
546 pba_num[10] = '\0';
547
548 /* switch all the data but the '-' to hex char */
549 for (offset = 0; offset < 10; offset++) {
550 if (pba_num[offset] < 0xA)
551 pba_num[offset] += '0';
552 else if (pba_num[offset] < 0x10)
553 pba_num[offset] += 'A' - 0xA;
554 }
555
556 return 0;
557 }
558
559 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
560 if (ret_val) {
561 hw_dbg(hw, "NVM Read Error\n");
562 return ret_val;
563 }
564
565 if (length == 0xFFFF || length == 0) {
566 hw_dbg(hw, "NVM PBA number section invalid length\n");
567 return IXGBE_ERR_PBA_SECTION;
568 }
569
570 /* check if pba_num buffer is big enough */
571 if (pba_num_size < (((u32)length * 2) - 1)) {
572 hw_dbg(hw, "PBA string buffer too small\n");
573 return IXGBE_ERR_NO_SPACE;
574 }
575
576 /* trim pba length from start of string */
577 pba_ptr++;
578 length--;
579
580 for (offset = 0; offset < length; offset++) {
581 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
582 if (ret_val) {
583 hw_dbg(hw, "NVM Read Error\n");
584 return ret_val;
585 }
586 pba_num[offset * 2] = (u8)(data >> 8);
587 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
588 }
589 pba_num[offset * 2] = '\0';
c44ade9e
JB		 590
591 return 0;
592}
593
594/**
595 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 596 * @hw: pointer to hardware structure
597 * @mac_addr: Adapter MAC address
598 *
599 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
600 * A reset of the adapter must be performed prior to calling this function
601 * in order for the MAC address to have been loaded from the EEPROM into RAR0
602 **/
c44ade9e 603s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 604{
605 u32 rar_high;
606 u32 rar_low;
607 u16 i;
608
609 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
610 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
611
612 for (i = 0; i < 4; i++)
613 mac_addr[i] = (u8)(rar_low >> (i*8));
614
615 for (i = 0; i < 2; i++)
616 mac_addr[i+4] = (u8)(rar_high >> (i*8));
617
618 return 0;
619}
620
ef1889d5
JK		 621enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
622{
623 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
624 case IXGBE_PCI_LINK_WIDTH_1:
625 return ixgbe_bus_width_pcie_x1;
626 case IXGBE_PCI_LINK_WIDTH_2:
627 return ixgbe_bus_width_pcie_x2;
628 case IXGBE_PCI_LINK_WIDTH_4:
629 return ixgbe_bus_width_pcie_x4;
630 case IXGBE_PCI_LINK_WIDTH_8:
631 return ixgbe_bus_width_pcie_x8;
632 default:
633 return ixgbe_bus_width_unknown;
634 }
635}
636
637enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
638{
639 switch (link_status & IXGBE_PCI_LINK_SPEED) {
640 case IXGBE_PCI_LINK_SPEED_2500:
641 return ixgbe_bus_speed_2500;
642 case IXGBE_PCI_LINK_SPEED_5000:
643 return ixgbe_bus_speed_5000;
644 case IXGBE_PCI_LINK_SPEED_8000:
645 return ixgbe_bus_speed_8000;
646 default:
647 return ixgbe_bus_speed_unknown;
648 }
649}
650
11afc1b1
PW		 651/**
652 * ixgbe_get_bus_info_generic - Generic set PCI bus info
653 * @hw: pointer to hardware structure
654 *
655 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
656 **/
657s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
658{
11afc1b1
PW		 659 u16 link_status;
660
661 hw->bus.type = ixgbe_bus_type_pci_express;
662
663 /* Get the negotiated link width and speed from PCI config space */
0d7c6e00 664 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
11afc1b1 665
ef1889d5
JK		 666 hw->bus.width = ixgbe_convert_bus_width(link_status);
667 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1 668
0d7c6e00 669 hw->mac.ops.set_lan_id(hw);
11afc1b1
PW		 670
671 return 0;
672}
673
674/**
675 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
676 * @hw: pointer to the HW structure
677 *
678 * Determines the LAN function id by reading memory-mapped registers
679 * and swaps the port value if requested.
680 **/
681void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
682{
683 struct ixgbe_bus_info *bus = &hw->bus;
684 u32 reg;
685
686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
687 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
688 bus->lan_id = bus->func;
689
690 /* check for a port swap */
9a900eca 691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
11afc1b1
PW		 692 if (reg & IXGBE_FACTPS_LFS)
693 bus->func ^= 0x1;
694}
695
9a799d71 696/**
c44ade9e 697 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 698 * @hw: pointer to hardware structure
699 *
700 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
701 * disables transmit and receive units. The adapter_stopped flag is used by
702 * the shared code and drivers to determine if the adapter is in a stopped
703 * state and should not touch the hardware.
704 **/
c44ade9e 705s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 706{
9a799d71
AK		 707 u32 reg_val;
708 u16 i;
709
710 /*
711 * Set the adapter_stopped flag so other driver functions stop touching
712 * the hardware
713 */
714 hw->adapter_stopped = true;
715
716 /* Disable the receive unit */
1f9ac57c 717 hw->mac.ops.disable_rx(hw);
9a799d71 718
ff9d1a5a 719 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 720 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
721
ff9d1a5a 722 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 723 IXGBE_READ_REG(hw, IXGBE_EICR);
724
725 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 726 for (i = 0; i < hw->mac.max_tx_queues; i++)
727 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
728
729 /* Disable the receive unit by stopping each queue */
730 for (i = 0; i < hw->mac.max_rx_queues; i++) {
731 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
732 reg_val &= ~IXGBE_RXDCTL_ENABLE;
733 reg_val |= IXGBE_RXDCTL_SWFLSH;
734 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 735 }
736
ff9d1a5a
ET		 737 /* flush all queues disables */
738 IXGBE_WRITE_FLUSH(hw);
739 usleep_range(1000, 2000);
740
c44ade9e
JB		 741 /*
742 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
743 * access and verify no pending requests
744 */
ff9d1a5a 745 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 746}
747
748/**
c44ade9e 749 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 750 * @hw: pointer to hardware structure
751 * @index: led number to turn on
752 **/
c44ade9e 753s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 754{
755 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
756
757 /* To turn on the LED, set mode to ON. */
758 led_reg &= ~IXGBE_LED_MODE_MASK(index);
759 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
760 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 761 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 762
763 return 0;
764}
765
766/**
c44ade9e 767 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 768 * @hw: pointer to hardware structure
769 * @index: led number to turn off
770 **/
c44ade9e 771s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 772{
773 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
774
775 /* To turn off the LED, set mode to OFF. */
776 led_reg &= ~IXGBE_LED_MODE_MASK(index);
777 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
778 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 779 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 780
781 return 0;
782}
783
9a799d71 784/**
c44ade9e 785 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 786 * @hw: pointer to hardware structure
787 *
788 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
789 * ixgbe_hw struct in order to set up EEPROM access.
790 **/
c44ade9e 791s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 792{
793 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
794 u32 eec;
795 u16 eeprom_size;
796
797 if (eeprom->type == ixgbe_eeprom_uninitialized) {
798 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 799 /* Set default semaphore delay to 10ms which is a well
800 * tested value */
801 eeprom->semaphore_delay = 10;
68c7005d
ET		 802 /* Clear EEPROM page size, it will be initialized as needed */
803 eeprom->word_page_size = 0;
9a799d71
AK		 804
805 /*
806 * Check for EEPROM present first.
807 * If not present leave as none
808 */
9a900eca 809 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9a799d71
AK		 810 if (eec & IXGBE_EEC_PRES) {
811 eeprom->type = ixgbe_eeprom_spi;
812
813 /*
814 * SPI EEPROM is assumed here. This code would need to
815 * change if a future EEPROM is not SPI.
816 */
817 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
818 IXGBE_EEC_SIZE_SHIFT);
819 eeprom->word_size = 1 << (eeprom_size +
820 IXGBE_EEPROM_WORD_SIZE_SHIFT);
821 }
822
823 if (eec & IXGBE_EEC_ADDR_SIZE)
824 eeprom->address_bits = 16;
825 else
826 eeprom->address_bits = 8;
6ec1b71f
JK		 827 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
828 eeprom->type, eeprom->word_size, eeprom->address_bits);
9a799d71
AK		 829 }
830
831 return 0;
832}
833
11afc1b1 834/**
68c7005d 835 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 836 * @hw: pointer to hardware structure
68c7005d
ET		 837 * @offset: offset within the EEPROM to write
838 * @words: number of words
839 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 840 *
68c7005d 841 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 842 **/
68c7005d
ET		 843s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
844 u16 words, u16 *data)
11afc1b1 845{
e90dd264 846 s32 status;
68c7005d 847 u16 i, count;
11afc1b1
PW		 848
849 hw->eeprom.ops.init_params(hw);
850
e90dd264
MR		 851 if (words == 0)
852 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 853
e90dd264
MR		 854 if (offset + words > hw->eeprom.word_size)
855 return IXGBE_ERR_EEPROM;
11afc1b1 856
68c7005d
ET		 857 /*
858 * The EEPROM page size cannot be queried from the chip. We do lazy
859 * initialization. It is worth to do that when we write large buffer.
860 */
861 if ((hw->eeprom.word_page_size == 0) &&
862 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
863 ixgbe_detect_eeprom_page_size_generic(hw, offset);
864
865 /*
866 * We cannot hold synchronization semaphores for too long
867 * to avoid other entity starvation. However it is more efficient
868 * to read in bursts than synchronizing access for each word.
869 */
870 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
871 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
872 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
873 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
874 count, &data[i]);
875
876 if (status != 0)
877 break;
878 }
879
68c7005d
ET		 880 return status;
881}
882
883/**
884 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
885 * @hw: pointer to hardware structure
886 * @offset: offset within the EEPROM to be written to
887 * @words: number of word(s)
888 * @data: 16 bit word(s) to be written to the EEPROM
889 *
890 * If ixgbe_eeprom_update_checksum is not called after this function, the
891 * EEPROM will most likely contain an invalid checksum.
892 **/
893static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
894 u16 words, u16 *data)
895{
896 s32 status;
897 u16 word;
898 u16 page_size;
899 u16 i;
900 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
901
11afc1b1
PW		 902 /* Prepare the EEPROM for writing */
903 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 904 if (status)
905 return status;
11afc1b1 906
e90dd264
MR		 907 if (ixgbe_ready_eeprom(hw) != 0) {
908 ixgbe_release_eeprom(hw);
909 return IXGBE_ERR_EEPROM;
11afc1b1
PW		 910 }
911
e90dd264
MR		 912 for (i = 0; i < words; i++) {
913 ixgbe_standby_eeprom(hw);
914
915 /* Send the WRITE ENABLE command (8 bit opcode) */
916 ixgbe_shift_out_eeprom_bits(hw,
917 IXGBE_EEPROM_WREN_OPCODE_SPI,
918 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 919
e90dd264 920 ixgbe_standby_eeprom(hw);
11afc1b1 921
e90dd264
MR		 922 /* Some SPI eeproms use the 8th address bit embedded
923 * in the opcode
924 */
925 if ((hw->eeprom.address_bits == 8) &&
926 ((offset + i) >= 128))
927 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
11afc1b1 928
e90dd264
MR		 929 /* Send the Write command (8-bit opcode + addr) */
930 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
931 IXGBE_EEPROM_OPCODE_BITS);
932 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
933 hw->eeprom.address_bits);
934
935 page_size = hw->eeprom.word_page_size;
936
937 /* Send the data in burst via SPI */
938 do {
939 word = data[i];
940 word = (word >> 8) | (word << 8);
941 ixgbe_shift_out_eeprom_bits(hw, word, 16);
942
943 if (page_size == 0)
944 break;
945
946 /* do not wrap around page */
947 if (((offset + i) & (page_size - 1)) ==
948 (page_size - 1))
949 break;
950 } while (++i < words);
951
952 ixgbe_standby_eeprom(hw);
953 usleep_range(10000, 20000);
68c7005d 954 }
e90dd264
MR		 955 /* Done with writing - release the EEPROM */
956 ixgbe_release_eeprom(hw);
11afc1b1 957
e90dd264 958 return 0;
68c7005d
ET		 959}
960
961/**
962 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
963 * @hw: pointer to hardware structure
964 * @offset: offset within the EEPROM to be written to
965 * @data: 16 bit word to be written to the EEPROM
966 *
967 * If ixgbe_eeprom_update_checksum is not called after this function, the
968 * EEPROM will most likely contain an invalid checksum.
969 **/
970s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
971{
68c7005d 972 hw->eeprom.ops.init_params(hw);
11afc1b1 973
e90dd264
MR		 974 if (offset >= hw->eeprom.word_size)
975 return IXGBE_ERR_EEPROM;
11afc1b1 976
e90dd264 977 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
11afc1b1
PW		 978}
979
9a799d71 980/**
68c7005d 981 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 982 * @hw: pointer to hardware structure
983 * @offset: offset within the EEPROM to be read
68c7005d
ET		 984 * @words: number of word(s)
985 * @data: read 16 bit words(s) from EEPROM
c44ade9e 986 *
68c7005d 987 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 988 **/
68c7005d
ET		 989s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
990 u16 words, u16 *data)
c44ade9e 991{
e90dd264 992 s32 status;
68c7005d 993 u16 i, count;
c44ade9e
JB		 994
995 hw->eeprom.ops.init_params(hw);
996
e90dd264
MR		 997 if (words == 0)
998 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 999
e90dd264
MR		 1000 if (offset + words > hw->eeprom.word_size)
1001 return IXGBE_ERR_EEPROM;
c44ade9e 1002
68c7005d
ET		 1003 /*
1004 * We cannot hold synchronization semaphores for too long
1005 * to avoid other entity starvation. However it is more efficient
1006 * to read in bursts than synchronizing access for each word.
1007 */
1008 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1009 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1010 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1011
1012 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1013 count, &data[i]);
1014
e90dd264
MR		 1015 if (status)
1016 return status;
68c7005d
ET		 1017 }
1018
e90dd264 1019 return 0;
68c7005d
ET		 1020}
1021
1022/**
1023 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1024 * @hw: pointer to hardware structure
1025 * @offset: offset within the EEPROM to be read
1026 * @words: number of word(s)
1027 * @data: read 16 bit word(s) from EEPROM
1028 *
1029 * Reads 16 bit word(s) from EEPROM through bit-bang method
1030 **/
1031static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1032 u16 words, u16 *data)
1033{
1034 s32 status;
1035 u16 word_in;
1036 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1037 u16 i;
1038
c44ade9e
JB		 1039 /* Prepare the EEPROM for reading */
1040 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 1041 if (status)
1042 return status;
c44ade9e 1043
e90dd264
MR		 1044 if (ixgbe_ready_eeprom(hw) != 0) {
1045 ixgbe_release_eeprom(hw);
1046 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1047 }
1048
e90dd264
MR		 1049 for (i = 0; i < words; i++) {
1050 ixgbe_standby_eeprom(hw);
1051 /* Some SPI eeproms use the 8th address bit embedded
1052 * in the opcode
1053 */
1054 if ((hw->eeprom.address_bits == 8) &&
1055 ((offset + i) >= 128))
1056 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
c44ade9e 1057
e90dd264
MR		 1058 /* Send the READ command (opcode + addr) */
1059 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1060 IXGBE_EEPROM_OPCODE_BITS);
1061 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1062 hw->eeprom.address_bits);
1063
1064 /* Read the data. */
1065 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1066 data[i] = (word_in >> 8) | (word_in << 8);
68c7005d 1067 }
c44ade9e 1068
e90dd264
MR		 1069 /* End this read operation */
1070 ixgbe_release_eeprom(hw);
1071
1072 return 0;
68c7005d 1073}
c44ade9e 1074
68c7005d
ET		 1075/**
1076 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1077 * @hw: pointer to hardware structure
1078 * @offset: offset within the EEPROM to be read
1079 * @data: read 16 bit value from EEPROM
1080 *
1081 * Reads 16 bit value from EEPROM through bit-bang method
1082 **/
1083s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1084 u16 *data)
1085{
68c7005d
ET		 1086 hw->eeprom.ops.init_params(hw);
1087
e90dd264
MR		 1088 if (offset >= hw->eeprom.word_size)
1089 return IXGBE_ERR_EEPROM;
68c7005d 1090
e90dd264 1091 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
c44ade9e
JB		 1092}
1093
1094/**
68c7005d 1095 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1096 * @hw: pointer to hardware structure
68c7005d
ET		 1097 * @offset: offset of word in the EEPROM to read
1098 * @words: number of word(s)
1099 * @data: 16 bit word(s) from the EEPROM
9a799d71 1100 *
68c7005d 1101 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1102 **/
68c7005d
ET		 1103s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1104 u16 words, u16 *data)
9a799d71
AK		 1105{
1106 u32 eerd;
e90dd264 1107 s32 status;
68c7005d 1108 u32 i;
9a799d71 1109
c44ade9e
JB		 1110 hw->eeprom.ops.init_params(hw);
1111
e90dd264
MR		 1112 if (words == 0)
1113 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1114
e90dd264
MR		 1115 if (offset >= hw->eeprom.word_size)
1116 return IXGBE_ERR_EEPROM;
c44ade9e 1117
68c7005d 1118 for (i = 0; i < words; i++) {
d0111575 1119 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1120 IXGBE_EEPROM_RW_REG_START;
9a799d71 1121
68c7005d
ET		 1122 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1123 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1124
68c7005d
ET		 1125 if (status == 0) {
1126 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1127 IXGBE_EEPROM_RW_REG_DATA);
1128 } else {
1129 hw_dbg(hw, "Eeprom read timed out\n");
e90dd264 1130 return status;
68c7005d
ET		 1131 }
1132 }
e90dd264
MR		 1133
1134 return 0;
68c7005d 1135}
9a799d71 1136
68c7005d
ET		 1137/**
1138 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1139 * @hw: pointer to hardware structure
1140 * @offset: offset within the EEPROM to be used as a scratch pad
1141 *
1142 * Discover EEPROM page size by writing marching data at given offset.
1143 * This function is called only when we are writing a new large buffer
1144 * at given offset so the data would be overwritten anyway.
1145 **/
1146static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1147 u16 offset)
1148{
1149 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
e90dd264 1150 s32 status;
68c7005d
ET		 1151 u16 i;
1152
1153 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1154 data[i] = i;
1155
1156 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1157 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1158 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1159 hw->eeprom.word_page_size = 0;
e90dd264
MR		 1160 if (status)
1161 return status;
68c7005d
ET		 1162
1163 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
e90dd264
MR		 1164 if (status)
1165 return status;
68c7005d
ET		 1166
1167 /*
1168 * When writing in burst more than the actual page size
1169 * EEPROM address wraps around current page.
1170 */
1171 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1172
c5ffe7e1 1173 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
68c7005d 1174 hw->eeprom.word_page_size);
e90dd264 1175 return 0;
9a799d71
AK		 1176}
1177
eb9c3e3e 1178/**
68c7005d
ET		 1179 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1180 * @hw: pointer to hardware structure
1181 * @offset: offset of word in the EEPROM to read
1182 * @data: word read from the EEPROM
1183 *
1184 * Reads a 16 bit word from the EEPROM using the EERD register.
1185 **/
1186s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1187{
1188 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1189}
1190
1191/**
1192 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1193 * @hw: pointer to hardware structure
1194 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1195 * @words: number of words
1196 * @data: word(s) write to the EEPROM
eb9c3e3e 1197 *
68c7005d 1198 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1199 **/
68c7005d
ET		 1200s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1201 u16 words, u16 *data)
eb9c3e3e
ET		 1202{
1203 u32 eewr;
e90dd264 1204 s32 status;
68c7005d 1205 u16 i;
eb9c3e3e
ET		 1206
1207 hw->eeprom.ops.init_params(hw);
1208
e90dd264
MR		 1209 if (words == 0)
1210 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1211
e90dd264
MR		 1212 if (offset >= hw->eeprom.word_size)
1213 return IXGBE_ERR_EEPROM;
eb9c3e3e 1214
68c7005d
ET		 1215 for (i = 0; i < words; i++) {
1216 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1217 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1218 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1219
68c7005d 1220 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1221 if (status) {
68c7005d 1222 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1223 return status;
68c7005d 1224 }
eb9c3e3e 1225
68c7005d 1226 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1227
68c7005d 1228 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1229 if (status) {
68c7005d 1230 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1231 return status;
68c7005d 1232 }
eb9c3e3e
ET		 1233 }
1234
e90dd264 1235 return 0;
eb9c3e3e
ET		 1236}
1237
68c7005d
ET		 1238/**
1239 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1240 * @hw: pointer to hardware structure
1241 * @offset: offset of word in the EEPROM to write
1242 * @data: word write to the EEPROM
1243 *
1244 * Write a 16 bit word to the EEPROM using the EEWR register.
1245 **/
1246s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1247{
1248 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1249}
1250
9a799d71 1251/**
21ce849b 1252 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1253 * @hw: pointer to hardware structure
21ce849b 1254 * @ee_reg: EEPROM flag for polling
9a799d71 1255 *
21ce849b
MC		 1256 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1257 * read or write is done respectively.
9a799d71 1258 **/
eb9c3e3e 1259static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1260{
1261 u32 i;
1262 u32 reg;
9a799d71 1263
21ce849b
MC		 1264 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1265 if (ee_reg == IXGBE_NVM_POLL_READ)
1266 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1267 else
1268 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1269
1270 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
e90dd264 1271 return 0;
9a799d71
AK		 1272 }
1273 udelay(5);
1274 }
e90dd264 1275 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1276}
1277
c44ade9e
JB		 1278/**
1279 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1280 * @hw: pointer to hardware structure
1281 *
1282 * Prepares EEPROM for access using bit-bang method. This function should
1283 * be called before issuing a command to the EEPROM.
1284 **/
1285static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1286{
dbf893ee 1287 u32 eec;
c44ade9e
JB		 1288 u32 i;
1289
5e655105 1290 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
e90dd264 1291 return IXGBE_ERR_SWFW_SYNC;
c44ade9e 1292
9a900eca 1293 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e 1294
e90dd264
MR		 1295 /* Request EEPROM Access */
1296 eec |= IXGBE_EEC_REQ;
9a900eca 1297 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e 1298
e90dd264 1299 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
9a900eca 1300 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
e90dd264
MR		 1301 if (eec & IXGBE_EEC_GNT)
1302 break;
1303 udelay(5);
1304 }
c44ade9e 1305
e90dd264
MR		 1306 /* Release if grant not acquired */
1307 if (!(eec & IXGBE_EEC_GNT)) {
1308 eec &= ~IXGBE_EEC_REQ;
9a900eca 1309 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
e90dd264 1310 hw_dbg(hw, "Could not acquire EEPROM grant\n");
c44ade9e 1311
e90dd264
MR		 1312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1313 return IXGBE_ERR_EEPROM;
c44ade9e 1314 }
e90dd264
MR		 1315
1316 /* Setup EEPROM for Read/Write */
1317 /* Clear CS and SK */
1318 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
9a900eca 1319 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
e90dd264
MR		 1320 IXGBE_WRITE_FLUSH(hw);
1321 udelay(1);
1322 return 0;
c44ade9e
JB		 1323}
1324
9a799d71
AK		 1325/**
1326 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1327 * @hw: pointer to hardware structure
1328 *
1329 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1330 **/
1331static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1332{
dbf893ee 1333 u32 timeout = 2000;
9a799d71
AK		 1334 u32 i;
1335 u32 swsm;
1336
9a799d71
AK		 1337 /* Get SMBI software semaphore between device drivers first */
1338 for (i = 0; i < timeout; i++) {
1339 /*
1340 * If the SMBI bit is 0 when we read it, then the bit will be
1341 * set and we have the semaphore
1342 */
9a900eca 1343 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264 1344 if (!(swsm & IXGBE_SWSM_SMBI))
9a799d71 1345 break;
d819fc52 1346 usleep_range(50, 100);
9a799d71
AK		 1347 }
1348
51275d37 1349 if (i == timeout) {
6ec1b71f 1350 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
e90dd264 1351 /* this release is particularly important because our attempts
51275d37
ET		 1352 * above to get the semaphore may have succeeded, and if there
1353 * was a timeout, we should unconditionally clear the semaphore
1354 * bits to free the driver to make progress
1355 */
1356 ixgbe_release_eeprom_semaphore(hw);
1357
d819fc52 1358 usleep_range(50, 100);
e90dd264 1359 /* one last try
51275d37
ET		 1360 * If the SMBI bit is 0 when we read it, then the bit will be
1361 * set and we have the semaphore
1362 */
9a900eca 1363 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264
MR		 1364 if (swsm & IXGBE_SWSM_SMBI) {
1365 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1366 return IXGBE_ERR_EEPROM;
1367 }
51275d37
ET		 1368 }
1369
9a799d71 1370 /* Now get the semaphore between SW/FW through the SWESMBI bit */
e90dd264 1371 for (i = 0; i < timeout; i++) {
9a900eca 1372 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
9a799d71 1373
e90dd264
MR		 1374 /* Set the SW EEPROM semaphore bit to request access */
1375 swsm |= IXGBE_SWSM_SWESMBI;
9a900eca 1376 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
9a799d71 1377
e90dd264
MR		 1378 /* If we set the bit successfully then we got the
1379 * semaphore.
1380 */
9a900eca 1381 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
e90dd264
MR		 1382 if (swsm & IXGBE_SWSM_SWESMBI)
1383 break;
9a799d71 1384
e90dd264
MR		 1385 usleep_range(50, 100);
1386 }
9a799d71 1387
e90dd264
MR		 1388 /* Release semaphores and return error if SW EEPROM semaphore
1389 * was not granted because we don't have access to the EEPROM
1390 */
1391 if (i >= timeout) {
1392 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1393 ixgbe_release_eeprom_semaphore(hw);
1394 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1395 }
1396
e90dd264 1397 return 0;
9a799d71
AK		 1398}
1399
1400/**
1401 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1402 * @hw: pointer to hardware structure
1403 *
1404 * This function clears hardware semaphore bits.
1405 **/
1406static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1407{
1408 u32 swsm;
1409
9a900eca 1410 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
9a799d71
AK		 1411
1412 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1413 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
9a900eca 1414 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
3957d63d 1415 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1416}
1417
c44ade9e
JB		 1418/**
1419 * ixgbe_ready_eeprom - Polls for EEPROM ready
1420 * @hw: pointer to hardware structure
1421 **/
1422static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1423{
c44ade9e
JB		 1424 u16 i;
1425 u8 spi_stat_reg;
1426
1427 /*
1428 * Read "Status Register" repeatedly until the LSB is cleared. The
1429 * EEPROM will signal that the command has been completed by clearing
1430 * bit 0 of the internal status register. If it's not cleared within
1431 * 5 milliseconds, then error out.
1432 */
1433 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1434 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
e7cf745b 1435 IXGBE_EEPROM_OPCODE_BITS);
c44ade9e
JB		 1436 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1437 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1438 break;
1439
1440 udelay(5);
1441 ixgbe_standby_eeprom(hw);
6403eab1 1442 }
c44ade9e
JB		 1443
1444 /*
1445 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1446 * devices (and only 0-5mSec on 5V devices)
1447 */
1448 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1449 hw_dbg(hw, "SPI EEPROM Status error\n");
e90dd264 1450 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1451 }
1452
e90dd264 1453 return 0;
c44ade9e
JB		 1454}
1455
1456/**
1457 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1458 * @hw: pointer to hardware structure
1459 **/
1460static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1461{
1462 u32 eec;
1463
9a900eca 1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1465
1466 /* Toggle CS to flush commands */
1467 eec |= IXGBE_EEC_CS;
9a900eca 1468 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1469 IXGBE_WRITE_FLUSH(hw);
1470 udelay(1);
1471 eec &= ~IXGBE_EEC_CS;
9a900eca 1472 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1473 IXGBE_WRITE_FLUSH(hw);
1474 udelay(1);
1475}
1476
1477/**
1478 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1479 * @hw: pointer to hardware structure
1480 * @data: data to send to the EEPROM
1481 * @count: number of bits to shift out
1482 **/
1483static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 1484 u16 count)
c44ade9e
JB		 1485{
1486 u32 eec;
1487 u32 mask;
1488 u32 i;
1489
9a900eca 1490 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1491
1492 /*
1493 * Mask is used to shift "count" bits of "data" out to the EEPROM
1494 * one bit at a time. Determine the starting bit based on count
1495 */
1496 mask = 0x01 << (count - 1);
1497
1498 for (i = 0; i < count; i++) {
1499 /*
1500 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1501 * "1", and then raising and then lowering the clock (the SK
1502 * bit controls the clock input to the EEPROM). A "0" is
1503 * shifted out to the EEPROM by setting "DI" to "0" and then
1504 * raising and then lowering the clock.
1505 */
1506 if (data & mask)
1507 eec |= IXGBE_EEC_DI;
1508 else
1509 eec &= ~IXGBE_EEC_DI;
1510
9a900eca 1511 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1512 IXGBE_WRITE_FLUSH(hw);
1513
1514 udelay(1);
1515
1516 ixgbe_raise_eeprom_clk(hw, &eec);
1517 ixgbe_lower_eeprom_clk(hw, &eec);
1518
1519 /*
1520 * Shift mask to signify next bit of data to shift in to the
1521 * EEPROM
1522 */
1523 mask = mask >> 1;
6403eab1 1524 }
c44ade9e
JB		 1525
1526 /* We leave the "DI" bit set to "0" when we leave this routine. */
1527 eec &= ~IXGBE_EEC_DI;
9a900eca 1528 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1529 IXGBE_WRITE_FLUSH(hw);
1530}
1531
1532/**
1533 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1534 * @hw: pointer to hardware structure
1535 **/
1536static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1537{
1538 u32 eec;
1539 u32 i;
1540 u16 data = 0;
1541
1542 /*
1543 * In order to read a register from the EEPROM, we need to shift
1544 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1545 * the clock input to the EEPROM (setting the SK bit), and then reading
1546 * the value of the "DO" bit. During this "shifting in" process the
1547 * "DI" bit should always be clear.
1548 */
9a900eca 1549 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1550
1551 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1552
1553 for (i = 0; i < count; i++) {
1554 data = data << 1;
1555 ixgbe_raise_eeprom_clk(hw, &eec);
1556
9a900eca 1557 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1558
1559 eec &= ~(IXGBE_EEC_DI);
1560 if (eec & IXGBE_EEC_DO)
1561 data |= 1;
1562
1563 ixgbe_lower_eeprom_clk(hw, &eec);
1564 }
1565
1566 return data;
1567}
1568
1569/**
1570 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1571 * @hw: pointer to hardware structure
1572 * @eec: EEC register's current value
1573 **/
1574static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1575{
1576 /*
1577 * Raise the clock input to the EEPROM
1578 * (setting the SK bit), then delay
1579 */
1580 *eec = *eec | IXGBE_EEC_SK;
9a900eca 1581 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
c44ade9e
JB		 1582 IXGBE_WRITE_FLUSH(hw);
1583 udelay(1);
1584}
1585
1586/**
1587 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1588 * @hw: pointer to hardware structure
1589 * @eecd: EECD's current value
1590 **/
1591static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1592{
1593 /*
1594 * Lower the clock input to the EEPROM (clearing the SK bit), then
1595 * delay
1596 */
1597 *eec = *eec & ~IXGBE_EEC_SK;
9a900eca 1598 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
c44ade9e
JB		 1599 IXGBE_WRITE_FLUSH(hw);
1600 udelay(1);
1601}
1602
1603/**
1604 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1605 * @hw: pointer to hardware structure
1606 **/
1607static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1608{
1609 u32 eec;
1610
9a900eca 1611 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
c44ade9e
JB		 1612
1613 eec |= IXGBE_EEC_CS; /* Pull CS high */
1614 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1615
9a900eca 1616 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e
JB		 1617 IXGBE_WRITE_FLUSH(hw);
1618
1619 udelay(1);
1620
1621 /* Stop requesting EEPROM access */
1622 eec &= ~IXGBE_EEC_REQ;
9a900eca 1623 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
c44ade9e 1624
90827996 1625 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1626
032b4325
DS		 1627 /*
1628 * Delay before attempt to obtain semaphore again to allow FW
1629 * access. semaphore_delay is in ms we need us for usleep_range
1630 */
1631 usleep_range(hw->eeprom.semaphore_delay * 1000,
1632 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1633}
1634
9a799d71 1635/**
dbf893ee 1636 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1637 * @hw: pointer to hardware structure
1638 **/
735c35af 1639s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1640{
1641 u16 i;
1642 u16 j;
1643 u16 checksum = 0;
1644 u16 length = 0;
1645 u16 pointer = 0;
1646 u16 word = 0;
1647
1648 /* Include 0x0-0x3F in the checksum */
1649 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
735c35af 1650 if (hw->eeprom.ops.read(hw, i, &word)) {
9a799d71
AK		 1651 hw_dbg(hw, "EEPROM read failed\n");
1652 break;
1653 }
1654 checksum += word;
1655 }
1656
1657 /* Include all data from pointers except for the fw pointer */
1658 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
735c35af
DS		 1659 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1660 hw_dbg(hw, "EEPROM read failed\n");
1661 return IXGBE_ERR_EEPROM;
1662 }
1663
1664 /* If the pointer seems invalid */
1665 if (pointer == 0xFFFF || pointer == 0)
1666 continue;
1667
1668 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1669 hw_dbg(hw, "EEPROM read failed\n");
1670 return IXGBE_ERR_EEPROM;
1671 }
9a799d71 1672
735c35af
DS		 1673 if (length == 0xFFFF || length == 0)
1674 continue;
9a799d71 1675
735c35af
DS		 1676 for (j = pointer + 1; j <= pointer + length; j++) {
1677 if (hw->eeprom.ops.read(hw, j, &word)) {
1678 hw_dbg(hw, "EEPROM read failed\n");
1679 return IXGBE_ERR_EEPROM;
9a799d71 1680 }
735c35af 1681 checksum += word;
9a799d71
AK		 1682 }
1683 }
1684
1685 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1686
735c35af 1687 return (s32)checksum;
9a799d71
AK		 1688}
1689
1690/**
c44ade9e 1691 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1692 * @hw: pointer to hardware structure
1693 * @checksum_val: calculated checksum
1694 *
1695 * Performs checksum calculation and validates the EEPROM checksum. If the
1696 * caller does not need checksum_val, the value can be NULL.
1697 **/
c44ade9e 1698s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 1699 u16 *checksum_val)
9a799d71
AK		 1700{
1701 s32 status;
1702 u16 checksum;
1703 u16 read_checksum = 0;
1704
1705 /*
1706 * Read the first word from the EEPROM. If this times out or fails, do
1707 * not continue or we could be in for a very long wait while every
1708 * EEPROM read fails
1709 */
c44ade9e 1710 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af
DS		 1711 if (status) {
1712 hw_dbg(hw, "EEPROM read failed\n");
1713 return status;
1714 }
9a799d71 1715
735c35af
DS		 1716 status = hw->eeprom.ops.calc_checksum(hw);
1717 if (status < 0)
1718 return status;
9a799d71 1719
735c35af 1720 checksum = (u16)(status & 0xffff);
9a799d71 1721
735c35af
DS		 1722 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1723 if (status) {
9a799d71 1724 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1725 return status;
9a799d71
AK		 1726 }
1727
735c35af
DS		 1728 /* Verify read checksum from EEPROM is the same as
1729 * calculated checksum
1730 */
1731 if (read_checksum != checksum)
1732 status = IXGBE_ERR_EEPROM_CHECKSUM;
1733
1734 /* If the user cares, return the calculated checksum */
1735 if (checksum_val)
1736 *checksum_val = checksum;
1737
9a799d71
AK		 1738 return status;
1739}
1740
c44ade9e
JB		 1741/**
1742 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1743 * @hw: pointer to hardware structure
1744 **/
1745s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1746{
1747 s32 status;
1748 u16 checksum;
1749
1750 /*
1751 * Read the first word from the EEPROM. If this times out or fails, do
1752 * not continue or we could be in for a very long wait while every
1753 * EEPROM read fails
1754 */
1755 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af 1756 if (status) {
c44ade9e 1757 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1758 return status;
c44ade9e
JB		 1759 }
1760
735c35af
DS		 1761 status = hw->eeprom.ops.calc_checksum(hw);
1762 if (status < 0)
1763 return status;
1764
1765 checksum = (u16)(status & 0xffff);
1766
1767 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1768
c44ade9e
JB		 1769 return status;
1770}
1771
9a799d71 1772/**
c44ade9e 1773 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1774 * @hw: pointer to hardware structure
9a799d71 1775 * @index: Receive address register to write
c44ade9e
JB		 1776 * @addr: Address to put into receive address register
1777 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1778 * @enable_addr: set flag that address is active
1779 *
1780 * Puts an ethernet address into a receive address register.
1781 **/
c44ade9e 1782s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 1783 u32 enable_addr)
9a799d71
AK		 1784{
1785 u32 rar_low, rar_high;
c44ade9e
JB		 1786 u32 rar_entries = hw->mac.num_rar_entries;
1787
c700f4e6
ET		 1788 /* Make sure we are using a valid rar index range */
1789 if (index >= rar_entries) {
1790 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1791 return IXGBE_ERR_INVALID_ARGUMENT;
1792 }
1793
c44ade9e
JB		 1794 /* setup VMDq pool selection before this RAR gets enabled */
1795 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1796
c700f4e6
ET		 1797 /*
1798 * HW expects these in little endian so we reverse the byte
1799 * order from network order (big endian) to little endian
1800 */
1801 rar_low = ((u32)addr[0] |
1802 ((u32)addr[1] << 8) |
1803 ((u32)addr[2] << 16) |
1804 ((u32)addr[3] << 24));
1805 /*
1806 * Some parts put the VMDq setting in the extra RAH bits,
1807 * so save everything except the lower 16 bits that hold part
1808 * of the address and the address valid bit.
1809 */
1810 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1811 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1812 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1813
c700f4e6
ET		 1814 if (enable_addr != 0)
1815 rar_high |= IXGBE_RAH_AV;
9a799d71 1816
c700f4e6
ET		 1817 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1818 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1819
1820 return 0;
1821}
1822
1823/**
1824 * ixgbe_clear_rar_generic - Remove Rx address register
1825 * @hw: pointer to hardware structure
1826 * @index: Receive address register to write
1827 *
1828 * Clears an ethernet address from a receive address register.
1829 **/
1830s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1831{
1832 u32 rar_high;
1833 u32 rar_entries = hw->mac.num_rar_entries;
1834
1835 /* Make sure we are using a valid rar index range */
c700f4e6 1836 if (index >= rar_entries) {
c44ade9e 1837 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1838 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1839 }
1840
c700f4e6
ET		 1841 /*
1842 * Some parts put the VMDq setting in the extra RAH bits,
1843 * so save everything except the lower 16 bits that hold part
1844 * of the address and the address valid bit.
1845 */
1846 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1847 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1848
1849 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1850 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1851
c44ade9e
JB		 1852 /* clear VMDq pool/queue selection for this RAR */
1853 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1854
1855 return 0;
1856}
1857
c44ade9e
JB		 1858/**
1859 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1860 * @hw: pointer to hardware structure
1861 *
1862 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1863 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1864 * the receiver is in reset when the routine is called.
1865 **/
c44ade9e 1866s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1867{
1868 u32 i;
2c5645cf 1869 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1870
1871 /*
1872 * If the current mac address is valid, assume it is a software override
1873 * to the permanent address.
1874 * Otherwise, use the permanent address from the eeprom.
1875 */
f8ebc683 1876 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1877 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1878 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1879
ce7194d8 1880 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1881 } else {
1882 /* Setup the receive address. */
1883 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1884 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1885
c44ade9e 1886 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1887
1888 /* clear VMDq pool/queue selection for RAR 0 */
1889 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1890 }
c44ade9e 1891 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1892
1893 hw->addr_ctrl.rar_used_count = 1;
1894
1895 /* Zero out the other receive addresses. */
c44ade9e 1896 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1897 for (i = 1; i < rar_entries; i++) {
1898 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1899 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1900 }
1901
1902 /* Clear the MTA */
9a799d71
AK		 1903 hw->addr_ctrl.mta_in_use = 0;
1904 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1905
1906 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1907 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1908 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1909
c44ade9e
JB		 1910 if (hw->mac.ops.init_uta_tables)
1911 hw->mac.ops.init_uta_tables(hw);
1912
9a799d71
AK		 1913 return 0;
1914}
1915
1916/**
1917 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1918 * @hw: pointer to hardware structure
1919 * @mc_addr: the multicast address
1920 *
1921 * Extracts the 12 bits, from a multicast address, to determine which
1922 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1923 * incoming rx multicast addresses, to determine the bit-vector to check in
1924 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1925 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1926 * to mc_filter_type.
1927 **/
1928static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1929{
1930 u32 vector = 0;
1931
1932 switch (hw->mac.mc_filter_type) {
b4617240 1933 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1934 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1935 break;
b4617240 1936 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1937 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1938 break;
b4617240 1939 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1940 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1941 break;
b4617240 1942 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1943 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1944 break;
b4617240 1945 default: /* Invalid mc_filter_type */
9a799d71
AK		 1946 hw_dbg(hw, "MC filter type param set incorrectly\n");
1947 break;
1948 }
1949
1950 /* vector can only be 12-bits or boundary will be exceeded */
1951 vector &= 0xFFF;
1952 return vector;
1953}
1954
1955/**
1956 * ixgbe_set_mta - Set bit-vector in multicast table
1957 * @hw: pointer to hardware structure
1958 * @hash_value: Multicast address hash value
1959 *
1960 * Sets the bit-vector in the multicast table.
1961 **/
1962static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1963{
1964 u32 vector;
1965 u32 vector_bit;
1966 u32 vector_reg;
9a799d71
AK		 1967
1968 hw->addr_ctrl.mta_in_use++;
1969
1970 vector = ixgbe_mta_vector(hw, mc_addr);
1971 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1972
1973 /*
1974 * The MTA is a register array of 128 32-bit registers. It is treated
1975 * like an array of 4096 bits. We want to set bit
1976 * BitArray[vector_value]. So we figure out what register the bit is
1977 * in, read it, OR in the new bit, then write back the new value. The
1978 * register is determined by the upper 7 bits of the vector value and
1979 * the bit within that register are determined by the lower 5 bits of
1980 * the value.
1981 */
1982 vector_reg = (vector >> 5) & 0x7F;
1983 vector_bit = vector & 0x1F;
80960ab0 1984 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1985}
1986
9a799d71 1987/**
c44ade9e 1988 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1989 * @hw: pointer to hardware structure
2853eb89 1990 * @netdev: pointer to net device structure
9a799d71
AK		 1991 *
1992 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1993 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1994 * registers for the first multicast addresses, and hashes the rest into the
1995 * multicast table.
1996 **/
2853eb89
JP		 1997s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1998 struct net_device *netdev)
9a799d71 1999{
22bedad3 2000 struct netdev_hw_addr *ha;
9a799d71 2001 u32 i;
9a799d71
AK		 2002
2003 /*
2004 * Set the new number of MC addresses that we are being requested to
2005 * use.
2006 */
2853eb89 2007 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2008 hw->addr_ctrl.mta_in_use = 0;
2009
80960ab0 2010 /* Clear mta_shadow */
9a799d71 2011 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2012 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2013
80960ab0 2014 /* Update mta shadow */
22bedad3 2015 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2016 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2017 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2018 }
2019
2020 /* Enable mta */
80960ab0
ET		 2021 for (i = 0; i < hw->mac.mcft_size; i++)
2022 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2023 hw->mac.mta_shadow[i]);
2024
9a799d71
AK		 2025 if (hw->addr_ctrl.mta_in_use > 0)
2026 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
e7cf745b 2027 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2028
c44ade9e 2029 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2030 return 0;
2031}
2032
2033/**
c44ade9e 2034 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2035 * @hw: pointer to hardware structure
2036 *
c44ade9e 2037 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2038 **/
c44ade9e 2039s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2040{
c44ade9e 2041 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2042
c44ade9e
JB		 2043 if (a->mta_in_use > 0)
2044 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
e7cf745b 2045 hw->mac.mc_filter_type);
9a799d71
AK		 2046
2047 return 0;
2048}
2049
2050/**
c44ade9e 2051 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2052 * @hw: pointer to hardware structure
9a799d71 2053 *
c44ade9e 2054 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2055 **/
c44ade9e 2056s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2057{
c44ade9e 2058 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2059
c44ade9e
JB		 2060 if (a->mta_in_use > 0)
2061 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2062
2063 return 0;
2064}
2065
11afc1b1 2066/**
620fa036 2067 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2068 * @hw: pointer to hardware structure
11afc1b1
PW		 2069 *
2070 * Enable flow control according to the current settings.
2071 **/
041441d0 2072s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1 2073{
620fa036 2074 u32 mflcn_reg, fccfg_reg;
11afc1b1 2075 u32 reg;
16b61beb 2076 u32 fcrtl, fcrth;
041441d0 2077 int i;
70b77628 2078
e5776620 2079 /* Validate the water mark configuration. */
e90dd264
MR		 2080 if (!hw->fc.pause_time)
2081 return IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2082
e5776620
JK		 2083 /* Low water mark of zero causes XOFF floods */
2084 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2085 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2086 hw->fc.high_water[i]) {
2087 if (!hw->fc.low_water[i] ||
2088 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2089 hw_dbg(hw, "Invalid water mark configuration\n");
e90dd264 2090 return IXGBE_ERR_INVALID_LINK_SETTINGS;
e5776620
JK		 2091 }
2092 }
2093 }
2094
620fa036 2095 /* Negotiate the fc mode to use */
786e9a5f 2096 ixgbe_fc_autoneg(hw);
11afc1b1 2097
620fa036 2098 /* Disable any previous flow control settings */
11afc1b1 2099 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2100 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2101
2102 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2103 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2104
2105 /*
2106 * The possible values of fc.current_mode are:
2107 * 0: Flow control is completely disabled
2108 * 1: Rx flow control is enabled (we can receive pause frames,
2109 * but not send pause frames).
bb3daa4a
PW		 2110 * 2: Tx flow control is enabled (we can send pause frames but
2111 * we do not support receiving pause frames).
11afc1b1
PW		 2112 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2113 * other: Invalid.
2114 */
2115 switch (hw->fc.current_mode) {
2116 case ixgbe_fc_none:
620fa036
MC		 2117 /*
2118 * Flow control is disabled by software override or autoneg.
2119 * The code below will actually disable it in the HW.
2120 */
11afc1b1
PW		 2121 break;
2122 case ixgbe_fc_rx_pause:
2123 /*
2124 * Rx Flow control is enabled and Tx Flow control is
2125 * disabled by software override. Since there really
2126 * isn't a way to advertise that we are capable of RX
2127 * Pause ONLY, we will advertise that we support both
2128 * symmetric and asymmetric Rx PAUSE. Later, we will
2129 * disable the adapter's ability to send PAUSE frames.
2130 */
2131 mflcn_reg |= IXGBE_MFLCN_RFCE;
2132 break;
2133 case ixgbe_fc_tx_pause:
2134 /*
2135 * Tx Flow control is enabled, and Rx Flow control is
2136 * disabled by software override.
2137 */
2138 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2139 break;
2140 case ixgbe_fc_full:
2141 /* Flow control (both Rx and Tx) is enabled by SW override. */
2142 mflcn_reg |= IXGBE_MFLCN_RFCE;
2143 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2144 break;
2145 default:
2146 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 2147 return IXGBE_ERR_CONFIG;
11afc1b1
PW		 2148 }
2149
620fa036 2150 /* Set 802.3x based flow control settings. */
2132d381 2151 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2152 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2153 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2154
041441d0
AD		 2155 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2156 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2157 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2158 hw->fc.high_water[i]) {
e5776620 2159 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
041441d0
AD		 2160 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2161 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2162 } else {
2163 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2164 /*
2165 * In order to prevent Tx hangs when the internal Tx
2166 * switch is enabled we must set the high water mark
bc1fc64f
MR		 2167 * to the Rx packet buffer size - 24KB. This allows
2168 * the Tx switch to function even under heavy Rx
2169 * workloads.
041441d0 2170 */
bc1fc64f 2171 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
041441d0 2172 }
11afc1b1 2173
041441d0
AD		 2174 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2175 }
16b61beb 2176
11afc1b1 2177 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2178 reg = hw->fc.pause_time * 0x00010001;
2179 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2180 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2181
2182 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1 2183
e90dd264 2184 return 0;
11afc1b1
PW		 2185}
2186
0ecc061d 2187/**
67a79df2 2188 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2189 * @hw: pointer to hardware structure
67a79df2
AD		 2190 * @adv_reg: flow control advertised settings
2191 * @lp_reg: link partner's flow control settings
2192 * @adv_sym: symmetric pause bit in advertisement
2193 * @adv_asm: asymmetric pause bit in advertisement
2194 * @lp_sym: symmetric pause bit in link partner advertisement
2195 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2196 *
67a79df2
AD		 2197 * Find the intersection between advertised settings and link partner's
2198 * advertised settings
0ecc061d 2199 **/
67a79df2
AD		 2200static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2201 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2202{
67a79df2
AD		 2203 if ((!(adv_reg)) || (!(lp_reg)))
2204 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2205
67a79df2
AD		 2206 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2207 /*
2208 * Now we need to check if the user selected Rx ONLY
2209 * of pause frames. In this case, we had to advertise
2210 * FULL flow control because we could not advertise RX
2211 * ONLY. Hence, we must now check to see if we need to
2212 * turn OFF the TRANSMISSION of PAUSE frames.
2213 */
2214 if (hw->fc.requested_mode == ixgbe_fc_full) {
2215 hw->fc.current_mode = ixgbe_fc_full;
2216 hw_dbg(hw, "Flow Control = FULL.\n");
2217 } else {
2218 hw->fc.current_mode = ixgbe_fc_rx_pause;
2219 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2220 }
2221 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2222 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2223 hw->fc.current_mode = ixgbe_fc_tx_pause;
2224 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2225 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2226 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2227 hw->fc.current_mode = ixgbe_fc_rx_pause;
2228 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2229 } else {
67a79df2
AD		 2230 hw->fc.current_mode = ixgbe_fc_none;
2231 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2232 }
67a79df2 2233 return 0;
0b0c2b31
ET		 2234}
2235
2236/**
2237 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2238 * @hw: pointer to hardware structure
2239 *
2240 * Enable flow control according on 1 gig fiber.
2241 **/
2242static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2243{
2244 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
e90dd264 2245 s32 ret_val;
539e5f02
PWJ		 2246
2247 /*
2248 * On multispeed fiber at 1g, bail out if
2249 * - link is up but AN did not complete, or if
2250 * - link is up and AN completed but timed out
2251 */
0b0c2b31
ET		 2252
2253 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2254 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2255 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
e90dd264 2256 return IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02 2257
0b0c2b31
ET		 2258 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2259 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2260
2261 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2262 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2263 IXGBE_PCS1GANA_ASM_PAUSE,
2264 IXGBE_PCS1GANA_SYM_PAUSE,
2265 IXGBE_PCS1GANA_ASM_PAUSE);
2266
0b0c2b31
ET		 2267 return ret_val;
2268}
2269
2270/**
2271 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2272 * @hw: pointer to hardware structure
2273 *
2274 * Enable flow control according to IEEE clause 37.
2275 **/
2276static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2277{
2278 u32 links2, anlp1_reg, autoc_reg, links;
e90dd264 2279 s32 ret_val;
0b0c2b31 2280
9bbe3a57 2281 /*
0b0c2b31
ET		 2282 * On backplane, bail out if
2283 * - backplane autoneg was not completed, or if
2284 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2285 */
0b0c2b31 2286 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2287 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
e90dd264 2288 return IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57 2289
0b0c2b31
ET		 2290 if (hw->mac.type == ixgbe_mac_82599EB) {
2291 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2292 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
e90dd264 2293 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2294 }
0ecc061d 2295 /*
0b0c2b31 2296 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2297 * local flow control settings accordingly
2298 */
0b0c2b31
ET		 2299 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2300 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2301
0b0c2b31
ET		 2302 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2303 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2304 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2305
0b0c2b31
ET		 2306 return ret_val;
2307}
2308
2309/**
2310 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2311 * @hw: pointer to hardware structure
2312 *
2313 * Enable flow control according to IEEE clause 37.
2314 **/
2315static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2316{
2317 u16 technology_ability_reg = 0;
2318 u16 lp_technology_ability_reg = 0;
2319
2320 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2321 MDIO_MMD_AN,
2322 &technology_ability_reg);
2323 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2324 MDIO_MMD_AN,
2325 &lp_technology_ability_reg);
2326
2327 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2328 (u32)lp_technology_ability_reg,
2329 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2330 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2331}
2332
2333/**
67a79df2 2334 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2335 * @hw: pointer to hardware structure
2336 *
67a79df2
AD		 2337 * Compares our advertised flow control capabilities to those advertised by
2338 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2339 **/
67a79df2 2340void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2341{
67a79df2
AD		 2342 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2343 ixgbe_link_speed speed;
2344 bool link_up;
11afc1b1
PW		 2345
2346 /*
67a79df2
AD		 2347 * AN should have completed when the cable was plugged in.
2348 * Look for reasons to bail out. Bail out if:
2349 * - FC autoneg is disabled, or if
2350 * - link is not up.
2351 *
2352 * Since we're being called from an LSC, link is already known to be up.
2353 * So use link_up_wait_to_complete=false.
11afc1b1 2354 */
67a79df2 2355 if (hw->fc.disable_fc_autoneg)
620fa036 2356 goto out;
11afc1b1 2357
67a79df2
AD		 2358 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2359 if (!link_up)
11afc1b1 2360 goto out;
0b0c2b31
ET		 2361
2362 switch (hw->phy.media_type) {
67a79df2 2363 /* Autoneg flow control on fiber adapters */
0b0c2b31 2364 case ixgbe_media_type_fiber:
67a79df2
AD		 2365 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2366 ret_val = ixgbe_fc_autoneg_fiber(hw);
2367 break;
2368
2369 /* Autoneg flow control on backplane adapters */
0b0c2b31 2370 case ixgbe_media_type_backplane:
67a79df2 2371 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2372 break;
2373
67a79df2 2374 /* Autoneg flow control on copper adapters */
0b0c2b31 2375 case ixgbe_media_type_copper:
73d80953 2376 if (ixgbe_device_supports_autoneg_fc(hw))
67a79df2 2377 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2378 break;
2379
2380 default:
620fa036 2381 break;
0b0c2b31 2382 }
539e5f02 2383
11afc1b1 2384out:
67a79df2
AD		 2385 if (ret_val == 0) {
2386 hw->fc.fc_was_autonegged = true;
2387 } else {
2388 hw->fc.fc_was_autonegged = false;
2389 hw->fc.current_mode = hw->fc.requested_mode;
2390 }
11afc1b1
PW		 2391}
2392
1f86c983
DS		 2393/**
2394 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2395 * @hw: pointer to hardware structure
2396 *
2397 * System-wide timeout range is encoded in PCIe Device Control2 register.
2398 *
2399 * Add 10% to specified maximum and return the number of times to poll for
2400 * completion timeout, in units of 100 microsec. Never return less than
2401 * 800 = 80 millisec.
2402 **/
2403static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2404{
1f86c983
DS		 2405 s16 devctl2;
2406 u32 pollcnt;
2407
0d7c6e00 2408 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
1f86c983
DS		 2409 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2410
2411 switch (devctl2) {
2412 case IXGBE_PCIDEVCTRL2_65_130ms:
2413 pollcnt = 1300; /* 130 millisec */
2414 break;
2415 case IXGBE_PCIDEVCTRL2_260_520ms:
2416 pollcnt = 5200; /* 520 millisec */
2417 break;
2418 case IXGBE_PCIDEVCTRL2_1_2s:
2419 pollcnt = 20000; /* 2 sec */
2420 break;
2421 case IXGBE_PCIDEVCTRL2_4_8s:
2422 pollcnt = 80000; /* 8 sec */
2423 break;
2424 case IXGBE_PCIDEVCTRL2_17_34s:
2425 pollcnt = 34000; /* 34 sec */
2426 break;
2427 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2428 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2429 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2430 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2431 default:
2432 pollcnt = 800; /* 80 millisec minimum */
2433 break;
2434 }
2435
2436 /* add 10% to spec maximum */
2437 return (pollcnt * 11) / 10;
2438}
2439
9a799d71
AK		 2440/**
2441 * ixgbe_disable_pcie_master - Disable PCI-express master access
2442 * @hw: pointer to hardware structure
2443 *
2444 * Disables PCI-Express master access and verifies there are no pending
2445 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2446 * bit hasn't caused the master requests to be disabled, else 0
2447 * is returned signifying master requests disabled.
2448 **/
ff9d1a5a 2449static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2450{
1f86c983 2451 u32 i, poll;
ff9d1a5a
ET		 2452 u16 value;
2453
2454 /* Always set this bit to ensure any future transactions are blocked */
2455 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2456
48b44612
MR		 2457 /* Poll for bit to read as set */
2458 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2459 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
2460 break;
2461 usleep_range(100, 120);
2462 }
2463 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) {
2464 hw_dbg(hw, "GIO disable did not set - requesting resets\n");
2465 goto gio_disable_fail;
2466 }
2467
ff9d1a5a 2468 /* Exit if master requests are blocked */
14438464
MR		 2469 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2470 ixgbe_removed(hw->hw_addr))
e90dd264 2471 return 0;
9a799d71 2472
ff9d1a5a 2473 /* Poll for master request bit to clear */
9a799d71 2474 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2475 udelay(100);
ff9d1a5a 2476 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
e90dd264 2477 return 0;
a4297dc2
ET		 2478 }
2479
ff9d1a5a
ET		 2480 /*
2481 * Two consecutive resets are required via CTRL.RST per datasheet
2482 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2483 * of this need. The first reset prevents new master requests from
2484 * being issued by our device. We then must wait 1usec or more for any
2485 * remaining completions from the PCIe bus to trickle in, and then reset
2486 * again to clear out any effects they may have had on our device.
2487 */
a4297dc2 2488 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
48b44612 2489gio_disable_fail:
ff9d1a5a 2490 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2 2491
7fc15103
MR		 2492 if (hw->mac.type >= ixgbe_mac_X550)
2493 return 0;
2494
a4297dc2
ET		 2495 /*
2496 * Before proceeding, make sure that the PCIe block does not have
2497 * transactions pending.
2498 */
1f86c983
DS		 2499 poll = ixgbe_pcie_timeout_poll(hw);
2500 for (i = 0; i < poll; i++) {
9a799d71 2501 udelay(100);
14438464
MR		 2502 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2503 if (ixgbe_removed(hw->hw_addr))
e90dd264 2504 return 0;
ff9d1a5a 2505 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
e90dd264 2506 return 0;
9a799d71
AK		 2507 }
2508
ff9d1a5a 2509 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
e90dd264 2510 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
9a799d71
AK		 2511}
2512
9a799d71 2513/**
c44ade9e 2514 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2515 * @hw: pointer to hardware structure
c44ade9e 2516 * @mask: Mask to specify which semaphore to acquire
9a799d71 2517 *
da74cd4a 2518 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2519 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2520 **/
030eaece 2521s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71 2522{
674c18b2 2523 u32 gssr = 0;
9a799d71
AK		 2524 u32 swmask = mask;
2525 u32 fwmask = mask << 5;
674c18b2
ET		 2526 u32 timeout = 200;
2527 u32 i;
9a799d71 2528
674c18b2 2529 for (i = 0; i < timeout; i++) {
dbf893ee 2530 /*
674c18b2
ET		 2531 * SW NVM semaphore bit is used for access to all
2532 * SW_FW_SYNC bits (not just NVM)
dbf893ee 2533 */
9a799d71 2534 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2535 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2536
2537 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
674c18b2
ET		 2538 if (!(gssr & (fwmask | swmask))) {
2539 gssr |= swmask;
2540 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2541 ixgbe_release_eeprom_semaphore(hw);
2542 return 0;
2543 } else {
2544 /* Resource is currently in use by FW or SW */
2545 ixgbe_release_eeprom_semaphore(hw);
2546 usleep_range(5000, 10000);
2547 }
9a799d71
AK		 2548 }
2549
674c18b2
ET		 2550 /* If time expired clear the bits holding the lock and retry */
2551 if (gssr & (fwmask | swmask))
2552 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
9a799d71 2553
674c18b2
ET		 2554 usleep_range(5000, 10000);
2555 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2556}
2557
2558/**
2559 * ixgbe_release_swfw_sync - Release SWFW semaphore
2560 * @hw: pointer to hardware structure
c44ade9e 2561 * @mask: Mask to specify which semaphore to release
9a799d71 2562 *
da74cd4a 2563 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2564 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2565 **/
030eaece 2566void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71
AK		 2567{
2568 u32 gssr;
2569 u32 swmask = mask;
2570
2571 ixgbe_get_eeprom_semaphore(hw);
2572
2573 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2574 gssr &= ~swmask;
2575 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2576
2577 ixgbe_release_eeprom_semaphore(hw);
2578}
2579
429d6a3b
DS		 2580/**
2581 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2582 * @hw: pointer to hardware structure
2583 * @reg_val: Value we read from AUTOC
2584 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2585 * true in this the generic case.
2586 *
2587 * The default case requires no protection so just to the register read.
2588 **/
2589s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2590{
2591 *locked = false;
2592 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2593 return 0;
2594}
2595
2596/**
2597 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2598 * @hw: pointer to hardware structure
2599 * @reg_val: value to write to AUTOC
2600 * @locked: bool to indicate whether the SW/FW lock was already taken by
2601 * previous read.
2602 **/
2603s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2604{
2605 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2606 return 0;
2607}
2608
d2f5e7f3
AS		 2609/**
2610 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2611 * @hw: pointer to hardware structure
2612 *
2613 * Stops the receive data path and waits for the HW to internally
2614 * empty the Rx security block.
2615 **/
2616s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2617{
2618#define IXGBE_MAX_SECRX_POLL 40
2619 int i;
2620 int secrxreg;
2621
2622 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2623 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2624 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2625 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2626 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2627 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2628 break;
2629 else
2630 /* Use interrupt-safe sleep just in case */
db76ad47 2631 udelay(1000);
d2f5e7f3
AS		 2632 }
2633
2634 /* For informational purposes only */
2635 if (i >= IXGBE_MAX_SECRX_POLL)
6ec1b71f 2636 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
d2f5e7f3
AS		 2637
2638 return 0;
2639
2640}
2641
2642/**
2643 * ixgbe_enable_rx_buff - Enables the receive data path
2644 * @hw: pointer to hardware structure
2645 *
2646 * Enables the receive data path
2647 **/
2648s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2649{
2650 int secrxreg;
2651
2652 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2653 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2654 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2655 IXGBE_WRITE_FLUSH(hw);
2656
2657 return 0;
2658}
2659
11afc1b1
PW		 2660/**
2661 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2662 * @hw: pointer to hardware structure
2663 * @regval: register value to write to RXCTRL
2664 *
2665 * Enables the Rx DMA unit
2666 **/
2667s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2668{
1f9ac57c
DS		 2669 if (regval & IXGBE_RXCTRL_RXEN)
2670 hw->mac.ops.enable_rx(hw);
2671 else
2672 hw->mac.ops.disable_rx(hw);
11afc1b1
PW		 2673
2674 return 0;
2675}
87c12017
PW		 2676
2677/**
2678 * ixgbe_blink_led_start_generic - Blink LED based on index.
2679 * @hw: pointer to hardware structure
2680 * @index: led number to blink
2681 **/
2682s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2683{
2684 ixgbe_link_speed speed = 0;
3db1cd5c 2685 bool link_up = false;
87c12017
PW		 2686 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2687 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2688 bool locked = false;
e90dd264 2689 s32 ret_val;
87c12017
PW		 2690
2691 /*
2692 * Link must be up to auto-blink the LEDs;
2693 * Force it if link is down.
2694 */
2695 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2696
2697 if (!link_up) {
429d6a3b 2698 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2699 if (ret_val)
e90dd264 2700 return ret_val;
d7bbcd32 2701
50ac58ba 2702 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2703 autoc_reg |= IXGBE_AUTOC_FLU;
429d6a3b
DS		 2704
2705 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2706 if (ret_val)
e90dd264 2707 return ret_val;
429d6a3b 2708
945a5151 2709 IXGBE_WRITE_FLUSH(hw);
d7bbcd32 2710
032b4325 2711 usleep_range(10000, 20000);
87c12017
PW		 2712 }
2713
2714 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2715 led_reg |= IXGBE_LED_BLINK(index);
2716 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2717 IXGBE_WRITE_FLUSH(hw);
2718
e90dd264 2719 return 0;
87c12017
PW		 2720}
2721
2722/**
2723 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2724 * @hw: pointer to hardware structure
2725 * @index: led number to stop blinking
2726 **/
2727s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2728{
429d6a3b 2729 u32 autoc_reg = 0;
87c12017 2730 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2731 bool locked = false;
e90dd264 2732 s32 ret_val;
d7bbcd32 2733
429d6a3b 2734 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2735 if (ret_val)
e90dd264 2736 return ret_val;
87c12017
PW		 2737
2738 autoc_reg &= ~IXGBE_AUTOC_FLU;
2739 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2740
429d6a3b 2741 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2742 if (ret_val)
e90dd264 2743 return ret_val;
d7bbcd32 2744
87c12017
PW		 2745 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2746 led_reg &= ~IXGBE_LED_BLINK(index);
2747 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2748 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2749 IXGBE_WRITE_FLUSH(hw);
2750
e90dd264 2751 return 0;
87c12017 2752}
21ce849b
MC		 2753
2754/**
2755 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2756 * @hw: pointer to hardware structure
2757 * @san_mac_offset: SAN MAC address offset
2758 *
2759 * This function will read the EEPROM location for the SAN MAC address
2760 * pointer, and returns the value at that location. This is used in both
2761 * get and set mac_addr routines.
2762 **/
2763static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
e7cf745b 2764 u16 *san_mac_offset)
21ce849b 2765{
be0c27b4
MR		 2766 s32 ret_val;
2767
21ce849b
MC		 2768 /*
2769 * First read the EEPROM pointer to see if the MAC addresses are
2770 * available.
2771 */
be0c27b4
MR		 2772 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2773 san_mac_offset);
2774 if (ret_val)
2775 hw_err(hw, "eeprom read at offset %d failed\n",
2776 IXGBE_SAN_MAC_ADDR_PTR);
21ce849b 2777
be0c27b4 2778 return ret_val;
21ce849b
MC		 2779}
2780
2781/**
2782 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2783 * @hw: pointer to hardware structure
2784 * @san_mac_addr: SAN MAC address
2785 *
2786 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2787 * per-port, so set_lan_id() must be called before reading the addresses.
2788 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2789 * upon for non-SFP connections, so we must call it here.
2790 **/
2791s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2792{
2793 u16 san_mac_data, san_mac_offset;
2794 u8 i;
be0c27b4 2795 s32 ret_val;
21ce849b
MC		 2796
2797 /*
2798 * First read the EEPROM pointer to see if the MAC addresses are
2799 * available. If they're not, no point in calling set_lan_id() here.
2800 */
be0c27b4
MR		 2801 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2802 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
21ce849b 2803
be0c27b4 2804 goto san_mac_addr_clr;
21ce849b
MC		 2805
2806 /* make sure we know which port we need to program */
2807 hw->mac.ops.set_lan_id(hw);
2808 /* apply the port offset to the address offset */
2809 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
e7cf745b 2810 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
21ce849b 2811 for (i = 0; i < 3; i++) {
be0c27b4
MR		 2812 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2813 &san_mac_data);
2814 if (ret_val) {
2815 hw_err(hw, "eeprom read at offset %d failed\n",
2816 san_mac_offset);
2817 goto san_mac_addr_clr;
2818 }
21ce849b
MC		 2819 san_mac_addr[i * 2] = (u8)(san_mac_data);
2820 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2821 san_mac_offset++;
2822 }
21ce849b 2823 return 0;
be0c27b4
MR		 2824
2825san_mac_addr_clr:
2826 /* No addresses available in this EEPROM. It's not necessarily an
2827 * error though, so just wipe the local address and return.
2828 */
2829 for (i = 0; i < 6; i++)
2830 san_mac_addr[i] = 0xFF;
2831 return ret_val;
21ce849b
MC		 2832}
2833
2834/**
2835 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2836 * @hw: pointer to hardware structure
2837 *
2838 * Read PCIe configuration space, and get the MSI-X vector count from
2839 * the capabilities table.
2840 **/
71161302 2841u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b 2842{
e90dd264 2843 u16 msix_count;
71161302
ET		 2844 u16 max_msix_count;
2845 u16 pcie_offset;
2846
2847 switch (hw->mac.type) {
2848 case ixgbe_mac_82598EB:
2849 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2850 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2851 break;
2852 case ixgbe_mac_82599EB:
2853 case ixgbe_mac_X540:
9a75a1ac
DS		 2854 case ixgbe_mac_X550:
2855 case ixgbe_mac_X550EM_x:
71161302
ET		 2856 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2857 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2858 break;
2859 default:
e90dd264 2860 return 1;
71161302
ET		 2861 }
2862
14438464
MR		 2863 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2864 if (ixgbe_removed(hw->hw_addr))
2865 msix_count = 0;
21ce849b
MC		 2866 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2867
71161302 2868 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2869 msix_count++;
2870
71161302
ET		 2871 if (msix_count > max_msix_count)
2872 msix_count = max_msix_count;
2873
21ce849b
MC		 2874 return msix_count;
2875}
2876
2877/**
2878 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2879 * @hw: pointer to hardware struct
2880 * @rar: receive address register index to disassociate
2881 * @vmdq: VMDq pool index to remove from the rar
2882 **/
2883s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2884{
2885 u32 mpsar_lo, mpsar_hi;
2886 u32 rar_entries = hw->mac.num_rar_entries;
2887
c700f4e6
ET		 2888 /* Make sure we are using a valid rar index range */
2889 if (rar >= rar_entries) {
2890 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2891 return IXGBE_ERR_INVALID_ARGUMENT;
2892 }
21ce849b 2893
c700f4e6
ET		 2894 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2895 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2896
19458bd4 2897 if (ixgbe_removed(hw->hw_addr))
e90dd264 2898 return 0;
19458bd4 2899
c700f4e6 2900 if (!mpsar_lo && !mpsar_hi)
e90dd264 2901 return 0;
21ce849b 2902
c700f4e6
ET		 2903 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2904 if (mpsar_lo) {
2905 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2906 mpsar_lo = 0;
2907 }
2908 if (mpsar_hi) {
2909 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2910 mpsar_hi = 0;
2911 }
2912 } else if (vmdq < 32) {
2913 mpsar_lo &= ~(1 << vmdq);
2914 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2915 } else {
c700f4e6
ET		 2916 mpsar_hi &= ~(1 << (vmdq - 32));
2917 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2918 }
2919
c700f4e6
ET		 2920 /* was that the last pool using this rar? */
2921 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2922 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2923 return 0;
2924}
2925
2926/**
2927 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2928 * @hw: pointer to hardware struct
2929 * @rar: receive address register index to associate with a VMDq index
2930 * @vmdq: VMDq pool index
2931 **/
2932s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2933{
2934 u32 mpsar;
2935 u32 rar_entries = hw->mac.num_rar_entries;
2936
c700f4e6
ET		 2937 /* Make sure we are using a valid rar index range */
2938 if (rar >= rar_entries) {
21ce849b 2939 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2940 return IXGBE_ERR_INVALID_ARGUMENT;
2941 }
2942
2943 if (vmdq < 32) {
2944 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2945 mpsar |= 1 << vmdq;
2946 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2947 } else {
2948 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2949 mpsar |= 1 << (vmdq - 32);
2950 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2951 }
2952 return 0;
2953}
2954
7fa7c9dc
AD		 2955/**
2956 * This function should only be involved in the IOV mode.
2957 * In IOV mode, Default pool is next pool after the number of
2958 * VFs advertized and not 0.
2959 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2960 *
2961 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2962 * @hw: pointer to hardware struct
2963 * @vmdq: VMDq pool index
2964 **/
2965s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2966{
2967 u32 rar = hw->mac.san_mac_rar_index;
2968
2969 if (vmdq < 32) {
2970 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2971 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2972 } else {
2973 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2974 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2975 }
2976
2977 return 0;
2978}
2979
21ce849b
MC		 2980/**
2981 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2982 * @hw: pointer to hardware structure
2983 **/
2984s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2985{
2986 int i;
2987
21ce849b
MC		 2988 for (i = 0; i < 128; i++)
2989 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2990
2991 return 0;
2992}
2993
2994/**
2995 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2996 * @hw: pointer to hardware structure
2997 * @vlan: VLAN id to write to VLAN filter
2998 *
2999 * return the VLVF index where this VLAN id should be placed
3000 *
3001 **/
5d5b7c39 3002static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 3003{
3004 u32 bits = 0;
3005 u32 first_empty_slot = 0;
3006 s32 regindex;
3007
3008 /* short cut the special case */
3009 if (vlan == 0)
3010 return 0;
3011
3012 /*
3013 * Search for the vlan id in the VLVF entries. Save off the first empty
3014 * slot found along the way
3015 */
3016 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3017 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3018 if (!bits && !(first_empty_slot))
3019 first_empty_slot = regindex;
3020 else if ((bits & 0x0FFF) == vlan)
3021 break;
3022 }
3023
3024 /*
3025 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3026 * in the VLVF. Else use the first empty VLVF register for this
3027 * vlan id.
3028 */
3029 if (regindex >= IXGBE_VLVF_ENTRIES) {
3030 if (first_empty_slot)
3031 regindex = first_empty_slot;
3032 else {
3033 hw_dbg(hw, "No space in VLVF.\n");
3034 regindex = IXGBE_ERR_NO_SPACE;
3035 }
3036 }
3037
3038 return regindex;
3039}
3040
3041/**
3042 * ixgbe_set_vfta_generic - Set VLAN filter table
3043 * @hw: pointer to hardware structure
3044 * @vlan: VLAN id to write to VLAN filter
3045 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3046 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3047 *
3048 * Turn on/off specified VLAN in the VLAN filter table.
3049 **/
3050s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
e7cf745b 3051 bool vlan_on)
21ce849b 3052{
c18fbd5f 3053 u32 regidx, vfta_delta, vfta;
21ce849b
MC		 3054 u32 bits;
3055 u32 vt;
21ce849b
MC		 3056
3057 if (vlan > 4095)
3058 return IXGBE_ERR_PARAM;
3059
3060 /*
3061 * this is a 2 part operation - first the VFTA, then the
3062 * VLVF and VLVFB if VT Mode is set
3063 * We don't write the VFTA until we know the VLVF part succeeded.
3064 */
3065
3066 /* Part 1
3067 * The VFTA is a bitstring made up of 128 32-bit registers
3068 * that enable the particular VLAN id, much like the MTA:
3069 * bits[11-5]: which register
3070 * bits[4-0]: which bit in the register
3071 */
c18fbd5f
AD		 3072 regidx = vlan / 32;
3073 vfta_delta = 1 << (vlan % 32);
3074 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3075
3076 /* vfta_delta represents the difference between the current value
3077 * of vfta and the value we want in the register. Since the diff
3078 * is an XOR mask we can just update vfta using an XOR.
3079 */
3080 vfta_delta &= vlan_on ? ~vfta : vfta;
3081 vfta ^= vfta_delta;
21ce849b
MC		 3082
3083 /* Part 2
3084 * If VT Mode is set
3085 * Either vlan_on
3086 * make sure the vlan is in VLVF
3087 * set the vind bit in the matching VLVFB
3088 * Or !vlan_on
3089 * clear the pool bit and possibly the vind
3090 */
3091 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3092 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3093 s32 vlvf_index;
3094
3095 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3096 if (vlvf_index < 0)
3097 return vlvf_index;
3098
3099 if (vlan_on) {
3100 /* set the pool bit */
3101 if (vind < 32) {
3102 bits = IXGBE_READ_REG(hw,
3103 IXGBE_VLVFB(vlvf_index*2));
3104 bits |= (1 << vind);
3105 IXGBE_WRITE_REG(hw,
3106 IXGBE_VLVFB(vlvf_index*2),
3107 bits);
3108 } else {
3109 bits = IXGBE_READ_REG(hw,
3110 IXGBE_VLVFB((vlvf_index*2)+1));
3111 bits |= (1 << (vind-32));
3112 IXGBE_WRITE_REG(hw,
3113 IXGBE_VLVFB((vlvf_index*2)+1),
3114 bits);
3115 }
3116 } else {
3117 /* clear the pool bit */
3118 if (vind < 32) {
3119 bits = IXGBE_READ_REG(hw,
3120 IXGBE_VLVFB(vlvf_index*2));
3121 bits &= ~(1 << vind);
3122 IXGBE_WRITE_REG(hw,
3123 IXGBE_VLVFB(vlvf_index*2),
3124 bits);
3125 bits |= IXGBE_READ_REG(hw,
3126 IXGBE_VLVFB((vlvf_index*2)+1));
3127 } else {
3128 bits = IXGBE_READ_REG(hw,
3129 IXGBE_VLVFB((vlvf_index*2)+1));
3130 bits &= ~(1 << (vind-32));
3131 IXGBE_WRITE_REG(hw,
3132 IXGBE_VLVFB((vlvf_index*2)+1),
3133 bits);
3134 bits |= IXGBE_READ_REG(hw,
3135 IXGBE_VLVFB(vlvf_index*2));
3136 }
3137 }
3138
3139 /*
3140 * If there are still bits set in the VLVFB registers
3141 * for the VLAN ID indicated we need to see if the
3142 * caller is requesting that we clear the VFTA entry bit.
3143 * If the caller has requested that we clear the VFTA
3144 * entry bit but there are still pools/VFs using this VLAN
3145 * ID entry then ignore the request. We're not worried
3146 * about the case where we're turning the VFTA VLAN ID
3147 * entry bit on, only when requested to turn it off as
3148 * there may be multiple pools and/or VFs using the
3149 * VLAN ID entry. In that case we cannot clear the
3150 * VFTA bit until all pools/VFs using that VLAN ID have also
3151 * been cleared. This will be indicated by "bits" being
3152 * zero.
3153 */
3154 if (bits) {
3155 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3156 (IXGBE_VLVF_VIEN | vlan));
c18fbd5f
AD		 3157
3158 /* if someone wants to clear the vfta entry but
3159 * some pools/VFs are still using it. Ignore it.
3160 */
3161 if (!vlan_on)
3162 vfta_delta = 0;
63b64de3 3163 } else {
21ce849b 3164 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
63b64de3 3165 }
21ce849b
MC		 3166 }
3167
c18fbd5f
AD		 3168 if (vfta_delta)
3169 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
21ce849b
MC		 3170
3171 return 0;
3172}
3173
3174/**
3175 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3176 * @hw: pointer to hardware structure
3177 *
3178 * Clears the VLAN filer table, and the VMDq index associated with the filter
3179 **/
3180s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3181{
3182 u32 offset;
3183
3184 for (offset = 0; offset < hw->mac.vft_size; offset++)
3185 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3186
3187 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3188 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3189 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3190 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3191 }
3192
3193 return 0;
3194}
3195
3196/**
3197 * ixgbe_check_mac_link_generic - Determine link and speed status
3198 * @hw: pointer to hardware structure
3199 * @speed: pointer to link speed
3200 * @link_up: true when link is up
3201 * @link_up_wait_to_complete: bool used to wait for link up or not
3202 *
3203 * Reads the links register to determine if link is up and the current speed
3204 **/
3205s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3206 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3207{
48de36c5 3208 u32 links_reg, links_orig;
21ce849b
MC		 3209 u32 i;
3210
48de36c5
ET		 3211 /* clear the old state */
3212 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3213
21ce849b 3214 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3215
3216 if (links_orig != links_reg) {
3217 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3218 links_orig, links_reg);
3219 }
3220
21ce849b
MC		 3221 if (link_up_wait_to_complete) {
3222 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3223 if (links_reg & IXGBE_LINKS_UP) {
3224 *link_up = true;
3225 break;
3226 } else {
3227 *link_up = false;
3228 }
3229 msleep(100);
3230 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3231 }
3232 } else {
3233 if (links_reg & IXGBE_LINKS_UP)
3234 *link_up = true;
3235 else
3236 *link_up = false;
3237 }
3238
9a75a1ac
DS		 3239 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3240 case IXGBE_LINKS_SPEED_10G_82599:
3241 if ((hw->mac.type >= ixgbe_mac_X550) &&
3242 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3243 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3244 else
3245 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3246 break;
3247 case IXGBE_LINKS_SPEED_1G_82599:
21ce849b 3248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
9a75a1ac
DS		 3249 break;
3250 case IXGBE_LINKS_SPEED_100_82599:
3251 if ((hw->mac.type >= ixgbe_mac_X550) &&
3252 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3253 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3254 else
3255 *speed = IXGBE_LINK_SPEED_100_FULL;
3256 break;
3257 default:
63d778df 3258 *speed = IXGBE_LINK_SPEED_UNKNOWN;
9a75a1ac 3259 }
21ce849b 3260
21ce849b
MC		 3261 return 0;
3262}
a391f1d5
DS		 3263
3264/**
49ce9c2c 3265 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3266 * the EEPROM
3267 * @hw: pointer to hardware structure
3268 * @wwnn_prefix: the alternative WWNN prefix
3269 * @wwpn_prefix: the alternative WWPN prefix
3270 *
3271 * This function will read the EEPROM from the alternative SAN MAC address
3272 * block to check the support for the alternative WWNN/WWPN prefix support.
3273 **/
3274s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 3275 u16 *wwpn_prefix)
a391f1d5
DS		 3276{
3277 u16 offset, caps;
3278 u16 alt_san_mac_blk_offset;
3279
3280 /* clear output first */
3281 *wwnn_prefix = 0xFFFF;
3282 *wwpn_prefix = 0xFFFF;
3283
3284 /* check if alternative SAN MAC is supported */
be0c27b4
MR		 3285 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3286 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3287 goto wwn_prefix_err;
a391f1d5
DS		 3288
3289 if ((alt_san_mac_blk_offset == 0) ||
3290 (alt_san_mac_blk_offset == 0xFFFF))
e90dd264 3291 return 0;
a391f1d5
DS		 3292
3293 /* check capability in alternative san mac address block */
3294 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
be0c27b4
MR		 3295 if (hw->eeprom.ops.read(hw, offset, &caps))
3296 goto wwn_prefix_err;
a391f1d5 3297 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
e90dd264 3298 return 0;
a391f1d5
DS		 3299
3300 /* get the corresponding prefix for WWNN/WWPN */
3301 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
be0c27b4
MR		 3302 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3303 hw_err(hw, "eeprom read at offset %d failed\n", offset);
a391f1d5
DS		 3304
3305 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
be0c27b4
MR		 3306 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3307 goto wwn_prefix_err;
a391f1d5 3308
a391f1d5 3309 return 0;
be0c27b4
MR		 3310
3311wwn_prefix_err:
3312 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3313 return 0;
a391f1d5 3314}
a985b6c3
GR		 3315
3316/**
3317 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3318 * @hw: pointer to hardware structure
3319 * @enable: enable or disable switch for anti-spoofing
3320 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3321 *
3322 **/
3323void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3324{
3325 int j;
3326 int pf_target_reg = pf >> 3;
3327 int pf_target_shift = pf % 8;
3328 u32 pfvfspoof = 0;
3329
3330 if (hw->mac.type == ixgbe_mac_82598EB)
3331 return;
3332
3333 if (enable)
3334 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3335
3336 /*
3337 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3338 * MAC anti-spoof enables in each register array element.
3339 */
ef89e0a2 3340 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3341 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3342
a985b6c3
GR		 3343 /*
3344 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3345 * emulation mode NICs. Do not set the bits assigned to the PF
3346 */
3347 pfvfspoof &= (1 << pf_target_shift) - 1;
3348 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3349
3350 /*
3351 * Remaining pools belong to the PF so they do not need to have
3352 * anti-spoofing enabled.
a985b6c3 3353 */
ef89e0a2
AD		 3354 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3355 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3356}
3357
3358/**
3359 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3360 * @hw: pointer to hardware structure
3361 * @enable: enable or disable switch for VLAN anti-spoofing
3362 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3363 *
3364 **/
3365void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3366{
3367 int vf_target_reg = vf >> 3;
3368 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3369 u32 pfvfspoof;
3370
3371 if (hw->mac.type == ixgbe_mac_82598EB)
3372 return;
3373
3374 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3375 if (enable)
3376 pfvfspoof |= (1 << vf_target_shift);
3377 else
3378 pfvfspoof &= ~(1 << vf_target_shift);
3379 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3380}
b776d104
ET		 3381
3382/**
3383 * ixgbe_get_device_caps_generic - Get additional device capabilities
3384 * @hw: pointer to hardware structure
3385 * @device_caps: the EEPROM word with the extra device capabilities
3386 *
3387 * This function will read the EEPROM location for the device capabilities,
3388 * and return the word through device_caps.
3389 **/
3390s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3391{
3392 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3393
3394 return 0;
3395}
80605c65
JF		 3396
3397/**
3398 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3399 * @hw: pointer to hardware structure
3400 * @num_pb: number of packet buffers to allocate
3401 * @headroom: reserve n KB of headroom
3402 * @strategy: packet buffer allocation strategy
3403 **/
3404void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3405 int num_pb,
3406 u32 headroom,
3407 int strategy)
3408{
3409 u32 pbsize = hw->mac.rx_pb_size;
3410 int i = 0;
3411 u32 rxpktsize, txpktsize, txpbthresh;
3412
3413 /* Reserve headroom */
3414 pbsize -= headroom;
3415
3416 if (!num_pb)
3417 num_pb = 1;
3418
3419 /* Divide remaining packet buffer space amongst the number
3420 * of packet buffers requested using supplied strategy.
3421 */
3422 switch (strategy) {
3423 case (PBA_STRATEGY_WEIGHTED):
3424 /* pba_80_48 strategy weight first half of packet buffer with
3425 * 5/8 of the packet buffer space.
3426 */
3427 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3428 pbsize -= rxpktsize * (num_pb / 2);
3429 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3430 for (; i < (num_pb / 2); i++)
3431 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3432 /* Fall through to configure remaining packet buffers */
3433 case (PBA_STRATEGY_EQUAL):
3434 /* Divide the remaining Rx packet buffer evenly among the TCs */
3435 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3436 for (; i < num_pb; i++)
3437 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3438 break;
3439 default:
3440 break;
3441 }
3442
3443 /*
3444 * Setup Tx packet buffer and threshold equally for all TCs
3445 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3446 * 10 since the largest packet we support is just over 9K.
3447 */
3448 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3449 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3450 for (i = 0; i < num_pb; i++) {
3451 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3452 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3453 }
3454
3455 /* Clear unused TCs, if any, to zero buffer size*/
3456 for (; i < IXGBE_MAX_PB; i++) {
3457 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3458 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3459 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3460 }
3461}
9612de92
ET		 3462
3463/**
3464 * ixgbe_calculate_checksum - Calculate checksum for buffer
3465 * @buffer: pointer to EEPROM
3466 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3467 *
9612de92
ET		 3468 * Calculates the checksum for some buffer on a specified length. The
3469 * checksum calculated is returned.
3470 **/
3471static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3472{
3473 u32 i;
3474 u8 sum = 0;
3475
3476 if (!buffer)
3477 return 0;
3478
3479 for (i = 0; i < length; i++)
3480 sum += buffer[i];
3481
3482 return (u8) (0 - sum);
3483}
3484
3485/**
3486 * ixgbe_host_interface_command - Issue command to manageability block
3487 * @hw: pointer to the HW structure
3488 * @buffer: contains the command to write and where the return status will
3489 * be placed
c466d7a7 3490 * @length: length of buffer, must be multiple of 4 bytes
b48e4aa3
DS		 3491 * @timeout: time in ms to wait for command completion
3492 * @return_data: read and return data from the buffer (true) or not (false)
3493 * Needed because FW structures are big endian and decoding of
3494 * these fields can be 8 bit or 16 bit based on command. Decoding
3495 * is not easily understood without making a table of commands.
3496 * So we will leave this up to the caller to read back the data
3497 * in these cases.
9612de92
ET		 3498 *
3499 * Communicates with the manageability block. On success return 0
3500 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3501 **/
6a14ee0c
DS		 3502s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3503 u32 length, u32 timeout,
3504 bool return_data)
9612de92 3505{
b48e4aa3 3506 u32 hicr, i, bi, fwsts;
9612de92 3507 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
b48e4aa3 3508 u16 buf_len, dword_len;
9612de92 3509
b48e4aa3
DS		 3510 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3511 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
e90dd264 3512 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3513 }
3514
b48e4aa3
DS		 3515 /* Set bit 9 of FWSTS clearing FW reset indication */
3516 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3517 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3518
9612de92
ET		 3519 /* Check that the host interface is enabled. */
3520 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3521 if ((hicr & IXGBE_HICR_EN) == 0) {
3522 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
e90dd264 3523 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3524 }
3525
b48e4aa3
DS		 3526 /* Calculate length in DWORDs. We must be DWORD aligned */
3527 if ((length % (sizeof(u32))) != 0) {
3528 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3529 return IXGBE_ERR_INVALID_ARGUMENT;
3530 }
3531
9612de92
ET		 3532 dword_len = length >> 2;
3533
3534 /*
3535 * The device driver writes the relevant command block
3536 * into the ram area.
3537 */
3538 for (i = 0; i < dword_len; i++)
3539 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3540 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3541
3542 /* Setting this bit tells the ARC that a new command is pending. */
3543 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3544
b48e4aa3 3545 for (i = 0; i < timeout; i++) {
9612de92
ET		 3546 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3547 if (!(hicr & IXGBE_HICR_C))
3548 break;
3549 usleep_range(1000, 2000);
3550 }
3551
3552 /* Check command successful completion. */
b48e4aa3 3553 if ((timeout != 0 && i == timeout) ||
9612de92
ET		 3554 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3555 hw_dbg(hw, "Command has failed with no status valid.\n");
e90dd264 3556 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3557 }
3558
b48e4aa3
DS		 3559 if (!return_data)
3560 return 0;
3561
9612de92
ET		 3562 /* Calculate length in DWORDs */
3563 dword_len = hdr_size >> 2;
3564
3565 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3566 for (bi = 0; bi < dword_len; bi++) {
3567 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3568 le32_to_cpus(&buffer[bi]);
79488c58 3569 }
9612de92
ET		 3570
3571 /* If there is any thing in data position pull it in */
3572 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3573 if (buf_len == 0)
e90dd264 3574 return 0;
9612de92
ET		 3575
3576 if (length < (buf_len + hdr_size)) {
3577 hw_dbg(hw, "Buffer not large enough for reply message.\n");
e90dd264 3578 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3579 }
3580
331bcf45
ET		 3581 /* Calculate length in DWORDs, add 3 for odd lengths */
3582 dword_len = (buf_len + 3) >> 2;
9612de92 3583
331bcf45
ET		 3584 /* Pull in the rest of the buffer (bi is where we left off)*/
3585 for (; bi <= dword_len; bi++) {
3586 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3587 le32_to_cpus(&buffer[bi]);
3588 }
9612de92 3589
e90dd264 3590 return 0;
9612de92
ET		 3591}
3592
3593/**
3594 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3595 * @hw: pointer to the HW structure
3596 * @maj: driver version major number
3597 * @min: driver version minor number
3598 * @build: driver version build number
3599 * @sub: driver version sub build number
3600 *
3601 * Sends driver version number to firmware through the manageability
3602 * block. On success return 0
3603 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3604 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3605 **/
3606s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3607 u8 build, u8 sub)
3608{
3609 struct ixgbe_hic_drv_info fw_cmd;
3610 int i;
e90dd264 3611 s32 ret_val;
9612de92 3612
e90dd264
MR		 3613 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
3614 return IXGBE_ERR_SWFW_SYNC;
9612de92
ET		 3615
3616 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3617 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3618 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3619 fw_cmd.port_num = (u8)hw->bus.func;
3620 fw_cmd.ver_maj = maj;
3621 fw_cmd.ver_min = min;
3622 fw_cmd.ver_build = build;
3623 fw_cmd.ver_sub = sub;
3624 fw_cmd.hdr.checksum = 0;
3625 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3626 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3627 fw_cmd.pad = 0;
3628 fw_cmd.pad2 = 0;
3629
3630 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3631 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
b48e4aa3
DS		 3632 sizeof(fw_cmd),
3633 IXGBE_HI_COMMAND_TIMEOUT,
3634 true);
9612de92
ET		 3635 if (ret_val != 0)
3636 continue;
3637
3638 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3639 FW_CEM_RESP_STATUS_SUCCESS)
3640 ret_val = 0;
3641 else
3642 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3643
3644 break;
3645 }
3646
3647 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
9612de92
ET		 3648 return ret_val;
3649}
ff9d1a5a
ET		 3650
3651/**
3652 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3653 * @hw: pointer to the hardware structure
3654 *
3655 * The 82599 and x540 MACs can experience issues if TX work is still pending
3656 * when a reset occurs. This function prevents this by flushing the PCIe
3657 * buffers on the system.
3658 **/
3659void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3660{
71bde601
DS		 3661 u32 gcr_ext, hlreg0, i, poll;
3662 u16 value;
ff9d1a5a
ET		 3663
3664 /*
3665 * If double reset is not requested then all transactions should
3666 * already be clear and as such there is no work to do
3667 */
3668 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3669 return;
3670
3671 /*
3672 * Set loopback enable to prevent any transmits from being sent
3673 * should the link come up. This assumes that the RXCTRL.RXEN bit
3674 * has already been cleared.
3675 */
3676 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3677 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3678
71bde601
DS		 3679 /* wait for a last completion before clearing buffers */
3680 IXGBE_WRITE_FLUSH(hw);
3681 usleep_range(3000, 6000);
3682
3683 /* Before proceeding, make sure that the PCIe block does not have
3684 * transactions pending.
3685 */
3686 poll = ixgbe_pcie_timeout_poll(hw);
3687 for (i = 0; i < poll; i++) {
3688 usleep_range(100, 200);
3689 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3690 if (ixgbe_removed(hw->hw_addr))
3691 break;
3692 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3693 break;
3694 }
3695
ff9d1a5a
ET		 3696 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3697 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3698 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3699 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3700
3701 /* Flush all writes and allow 20usec for all transactions to clear */
3702 IXGBE_WRITE_FLUSH(hw);
3703 udelay(20);
3704
3705 /* restore previous register values */
3706 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3707 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3708}
e1ea9158
DS		 3709
3710static const u8 ixgbe_emc_temp_data[4] = {
3711 IXGBE_EMC_INTERNAL_DATA,
3712 IXGBE_EMC_DIODE1_DATA,
3713 IXGBE_EMC_DIODE2_DATA,
3714 IXGBE_EMC_DIODE3_DATA
3715};
3716static const u8 ixgbe_emc_therm_limit[4] = {
3717 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3718 IXGBE_EMC_DIODE1_THERM_LIMIT,
3719 IXGBE_EMC_DIODE2_THERM_LIMIT,
3720 IXGBE_EMC_DIODE3_THERM_LIMIT
3721};
3722
3723/**
3724 * ixgbe_get_ets_data - Extracts the ETS bit data
3725 * @hw: pointer to hardware structure
3726 * @ets_cfg: extected ETS data
3727 * @ets_offset: offset of ETS data
3728 *
3729 * Returns error code.
3730 **/
3731static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3732 u16 *ets_offset)
3733{
e90dd264 3734 s32 status;
e1ea9158
DS		 3735
3736 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3737 if (status)
e90dd264 3738 return status;
e1ea9158 3739
e90dd264
MR		 3740 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3741 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3742
3743 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3744 if (status)
e90dd264 3745 return status;
e1ea9158 3746
e90dd264
MR		 3747 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3748 return IXGBE_NOT_IMPLEMENTED;
e1ea9158 3749
e90dd264 3750 return 0;
e1ea9158
DS		 3751}
3752
3753/**
3754 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3755 * @hw: pointer to hardware structure
3756 *
3757 * Returns the thermal sensor data structure
3758 **/
3759s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3760{
e90dd264 3761 s32 status;
e1ea9158
DS		 3762 u16 ets_offset;
3763 u16 ets_cfg;
3764 u16 ets_sensor;
3765 u8 num_sensors;
3766 u8 i;
3767 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3768
3ca8bc6d 3769 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3770 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3771 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3772
3773 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3774 if (status)
e90dd264 3775 return status;
e1ea9158
DS		 3776
3777 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3778 if (num_sensors > IXGBE_MAX_SENSORS)
3779 num_sensors = IXGBE_MAX_SENSORS;
3780
3781 for (i = 0; i < num_sensors; i++) {
3782 u8 sensor_index;
3783 u8 sensor_location;
3784
3785 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3786 &ets_sensor);
3787 if (status)
e90dd264 3788 return status;
e1ea9158
DS		 3789
3790 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3791 IXGBE_ETS_DATA_INDEX_SHIFT);
3792 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3793 IXGBE_ETS_DATA_LOC_SHIFT);
3794
3795 if (sensor_location != 0) {
3796 status = hw->phy.ops.read_i2c_byte(hw,
3797 ixgbe_emc_temp_data[sensor_index],
3798 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3799 &data->sensor[i].temp);
3800 if (status)
e90dd264 3801 return status;
e1ea9158
DS		 3802 }
3803 }
e90dd264
MR		 3804
3805 return 0;
e1ea9158
DS		 3806}
3807
3808/**
3809 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3810 * @hw: pointer to hardware structure
3811 *
3812 * Inits the thermal sensor thresholds according to the NVM map
3813 * and save off the threshold and location values into mac.thermal_sensor_data
3814 **/
3815s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3816{
e90dd264 3817 s32 status;
e1ea9158
DS		 3818 u16 ets_offset;
3819 u16 ets_cfg;
3820 u16 ets_sensor;
3821 u8 low_thresh_delta;
3822 u8 num_sensors;
3823 u8 therm_limit;
3824 u8 i;
3825 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3826
3827 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3828
3ca8bc6d 3829 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3830 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3831 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3832
3833 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3834 if (status)
e90dd264 3835 return status;
e1ea9158
DS		 3836
3837 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3838 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3839 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3840 if (num_sensors > IXGBE_MAX_SENSORS)
3841 num_sensors = IXGBE_MAX_SENSORS;
3842
3843 for (i = 0; i < num_sensors; i++) {
3844 u8 sensor_index;
3845 u8 sensor_location;
3846
be0c27b4
MR		 3847 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3848 hw_err(hw, "eeprom read at offset %d failed\n",
3849 ets_offset + 1 + i);
3850 continue;
3851 }
e1ea9158
DS		 3852 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3853 IXGBE_ETS_DATA_INDEX_SHIFT);
3854 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3855 IXGBE_ETS_DATA_LOC_SHIFT);
3856 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3857
3858 hw->phy.ops.write_i2c_byte(hw,
3859 ixgbe_emc_therm_limit[sensor_index],
3860 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3861
3862 if (sensor_location == 0)
3863 continue;
3864
3865 data->sensor[i].location = sensor_location;
3866 data->sensor[i].caution_thresh = therm_limit;
3867 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3868 }
e90dd264
MR		 3869
3870 return 0;
e1ea9158
DS		 3871}
3872
1f9ac57c
DS		 3873void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
3874{
3875 u32 rxctrl;
3876
3877 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3878 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3879 if (hw->mac.type != ixgbe_mac_82598EB) {
3880 u32 pfdtxgswc;
3881
3882 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3883 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3884 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3885 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3886 hw->mac.set_lben = true;
3887 } else {
3888 hw->mac.set_lben = false;
3889 }
3890 }
3891 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3892 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3893 }
3894}
3895
3896void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
3897{
3898 u32 rxctrl;
3899
3900 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3901 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
3902
3903 if (hw->mac.type != ixgbe_mac_82598EB) {
3904 if (hw->mac.set_lben) {
3905 u32 pfdtxgswc;
3906
3907 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3908 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
3909 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3910 hw->mac.set_lben = false;
3911 }
3912 }
3913}
bd8069ac
DS		 3914
3915/** ixgbe_mng_present - returns true when management capability is present
3916 * @hw: pointer to hardware structure
3917 **/
3918bool ixgbe_mng_present(struct ixgbe_hw *hw)
3919{
3920 u32 fwsm;
3921
3922 if (hw->mac.type < ixgbe_mac_82599EB)
3923 return false;
3924
3925 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
3926 fwsm &= IXGBE_FWSM_MODE_MASK;
3927 return fwsm == IXGBE_FWSM_FW_MODE_PT;
3928}
6d373a1b
MR		 3929
3930/**
3931 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
3932 * @hw: pointer to hardware structure
3933 * @speed: new link speed
3934 * @autoneg_wait_to_complete: true when waiting for completion is needed
3935 *
3936 * Set the link speed in the MAC and/or PHY register and restarts link.
3937 */
3938s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
3939 ixgbe_link_speed speed,
3940 bool autoneg_wait_to_complete)
3941{
3942 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3943 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3944 s32 status = 0;
3945 u32 speedcnt = 0;
3946 u32 i = 0;
3947 bool autoneg, link_up = false;
3948
3949 /* Mask off requested but non-supported speeds */
3950 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
3951 if (status)
3952 return status;
3953
3954 speed &= link_speed;
3955
3956 /* Try each speed one by one, highest priority first. We do this in
3957 * software because 10Gb fiber doesn't support speed autonegotiation.
3958 */
3959 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
3960 speedcnt++;
3961 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
3962
3963 /* If we already have link at this speed, just jump out */
3964 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
3965 false);
3966 if (status)
3967 return status;
3968
3969 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up)
3970 goto out;
3971
3972 /* Set the module link speed */
3973 switch (hw->phy.media_type) {
3974 case ixgbe_media_type_fiber:
3975 hw->mac.ops.set_rate_select_speed(hw,
3976 IXGBE_LINK_SPEED_10GB_FULL);
3977 break;
3978 case ixgbe_media_type_fiber_qsfp:
3979 /* QSFP module automatically detects MAC link speed */
3980 break;
3981 default:
3982 hw_dbg(hw, "Unexpected media type\n");
3983 break;
3984 }
3985
3986 /* Allow module to change analog characteristics (1G->10G) */
3987 msleep(40);
3988
3989 status = hw->mac.ops.setup_mac_link(hw,
3990 IXGBE_LINK_SPEED_10GB_FULL,
3991 autoneg_wait_to_complete);
3992 if (status)
3993 return status;
3994
3995 /* Flap the Tx laser if it has not already been done */
3996 if (hw->mac.ops.flap_tx_laser)
3997 hw->mac.ops.flap_tx_laser(hw);
3998
3999 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
4000 * Section 73.10.2, we may have to wait up to 500ms if KR is
4001 * attempted. 82599 uses the same timing for 10g SFI.
4002 */
4003 for (i = 0; i < 5; i++) {
4004 /* Wait for the link partner to also set speed */
4005 msleep(100);
4006
4007 /* If we have link, just jump out */
4008 status = hw->mac.ops.check_link(hw, &link_speed,
4009 &link_up, false);
4010 if (status)
4011 return status;
4012
4013 if (link_up)
4014 goto out;
4015 }
4016 }
4017
4018 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4019 speedcnt++;
4020 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4021 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4022
4023 /* If we already have link at this speed, just jump out */
4024 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4025 false);
4026 if (status)
4027 return status;
4028
4029 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up)
4030 goto out;
4031
4032 /* Set the module link speed */
4033 switch (hw->phy.media_type) {
4034 case ixgbe_media_type_fiber:
4035 hw->mac.ops.set_rate_select_speed(hw,
4036 IXGBE_LINK_SPEED_1GB_FULL);
4037 break;
4038 case ixgbe_media_type_fiber_qsfp:
4039 /* QSFP module automatically detects link speed */
4040 break;
4041 default:
4042 hw_dbg(hw, "Unexpected media type\n");
4043 break;
4044 }
4045
4046 /* Allow module to change analog characteristics (10G->1G) */
4047 msleep(40);
4048
4049 status = hw->mac.ops.setup_mac_link(hw,
4050 IXGBE_LINK_SPEED_1GB_FULL,
4051 autoneg_wait_to_complete);
4052 if (status)
4053 return status;
4054
4055 /* Flap the Tx laser if it has not already been done */
4056 if (hw->mac.ops.flap_tx_laser)
4057 hw->mac.ops.flap_tx_laser(hw);
4058
4059 /* Wait for the link partner to also set speed */
4060 msleep(100);
4061
4062 /* If we have link, just jump out */
4063 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4064 false);
4065 if (status)
4066 return status;
4067
4068 if (link_up)
4069 goto out;
4070 }
4071
4072 /* We didn't get link. Configure back to the highest speed we tried,
4073 * (if there was more than one). We call ourselves back with just the
4074 * single highest speed that the user requested.
4075 */
4076 if (speedcnt > 1)
4077 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4078 highest_link_speed,
4079 autoneg_wait_to_complete);
4080
4081out:
4082 /* Set autoneg_advertised value based on input link speed */
4083 hw->phy.autoneg_advertised = 0;
4084
4085 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4086 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4087
4088 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4089 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4090
4091 return status;
4092}
4093
4094/**
4095 * ixgbe_set_soft_rate_select_speed - Set module link speed
4096 * @hw: pointer to hardware structure
4097 * @speed: link speed to set
4098 *
4099 * Set module link speed via the soft rate select.
4100 */
4101void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4102 ixgbe_link_speed speed)
4103{
4104 s32 status;
4105 u8 rs, eeprom_data;
4106
4107 switch (speed) {
4108 case IXGBE_LINK_SPEED_10GB_FULL:
4109 /* one bit mask same as setting on */
4110 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4111 break;
4112 case IXGBE_LINK_SPEED_1GB_FULL:
4113 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4114 break;
4115 default:
4116 hw_dbg(hw, "Invalid fixed module speed\n");
4117 return;
4118 }
4119
4120 /* Set RS0 */
4121 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4122 IXGBE_I2C_EEPROM_DEV_ADDR2,
4123 &eeprom_data);
4124 if (status) {
4125 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
4126 return;
4127 }
4128
4129 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4130
4131 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4132 IXGBE_I2C_EEPROM_DEV_ADDR2,
4133 eeprom_data);
4134 if (status) {
4135 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
4136 return;
4137 }
4138}
Linux kernel - Deliverables
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