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ixgbe: cleanup some log messages
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
a6b7a407 30#include <linux/interrupt.h>
9a799d71
AK		 31#include <linux/types.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
9a799d71
AK		 34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/ethtool.h>
37#include <linux/vmalloc.h>
f800326d 38#include <linux/highmem.h>
9a799d71
AK		 39#include <linux/uaccess.h>
40
41#include "ixgbe.h"
71858acb 42#include "ixgbe_phy.h"
9a799d71
AK		 43
44
45#define IXGBE_ALL_RAR_ENTRIES 16
46
29c3a050
AK		 47enum {NETDEV_STATS, IXGBE_STATS};
48
9a799d71
AK		 49struct ixgbe_stats {
50 char stat_string[ETH_GSTRING_LEN];
29c3a050 51 int type;
9a799d71
AK		 52 int sizeof_stat;
53 int stat_offset;
54};
55
29c3a050
AK		 56#define IXGBE_STAT(m) IXGBE_STATS, \
57 sizeof(((struct ixgbe_adapter *)0)->m), \
58 offsetof(struct ixgbe_adapter, m)
59#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 60 sizeof(((struct rtnl_link_stats64 *)0)->m), \
61 offsetof(struct rtnl_link_stats64, m)
29c3a050 62
1bba2e81 63static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 72 {"lsc_int", IXGBE_STAT(lsc_int)},
73 {"tx_busy", IXGBE_STAT(tx_busy)},
74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
79 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 80 {"broadcast", IXGBE_STAT(stats.bprc)},
81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 82 {"collisions", IXGBE_NETDEV_STAT(collisions)},
83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
98 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 113#ifdef IXGBE_FCOE
114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
7b859ebc
AH		 118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
6d45522c
YZ		 120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
122#endif /* IXGBE_FCOE */
9a799d71
AK		 123};
124
9cc00b51
JF		 125/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
126 * we set the num_rx_queues to evaluate to num_tx_queues. This is
127 * used because we do not have a good way to get the max number of
128 * rx queues with CONFIG_RPS disabled.
129 */
130#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
131
132#define IXGBE_QUEUE_STATS_LEN ( \
133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
454d7c9b 134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 135#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 136#define IXGBE_PB_STATS_LEN ( \
9cc00b51
JF		 137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
141 / sizeof(u64))
2f90b865
AD		 142#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
143 IXGBE_PB_STATS_LEN + \
144 IXGBE_QUEUE_STATS_LEN)
9a799d71 145
da4dd0f7
PWJ		 146static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
147 "Register test (offline)", "Eeprom test (offline)",
148 "Interrupt test (offline)", "Loopback test (offline)",
149 "Link test (on/offline)"
150};
151#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
152
9a799d71 153static int ixgbe_get_settings(struct net_device *netdev,
b4617240 154 struct ethtool_cmd *ecmd)
9a799d71
AK		 155{
156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 157 struct ixgbe_hw *hw = &adapter->hw;
db018963 158 ixgbe_link_speed supported_link;
735441fb 159 u32 link_speed = 0;
fd0326f2 160 bool autoneg = false;
735441fb 161 bool link_up;
9a799d71 162
db018963 163 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
1b1c0a48 164
db018963
JK		 165 /* set the supported link speeds */
166 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
167 ecmd->supported |= SUPPORTED_10000baseT_Full;
168 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
169 ecmd->supported |= SUPPORTED_1000baseT_Full;
170 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
171 ecmd->supported |= SUPPORTED_100baseT_Full;
1b1c0a48 172
db018963
JK		 173 /* set the advertised speeds */
174 if (hw->phy.autoneg_advertised) {
175 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
176 ecmd->advertising |= ADVERTISED_100baseT_Full;
177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
178 ecmd->advertising |= ADVERTISED_10000baseT_Full;
179 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
180 ecmd->advertising |= ADVERTISED_1000baseT_Full;
735441fb 181 } else {
db018963
JK		 182 /* default modes in case phy.autoneg_advertised isn't set */
183 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
184 ecmd->advertising |= ADVERTISED_10000baseT_Full;
185 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
186 ecmd->advertising |= ADVERTISED_1000baseT_Full;
187 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
735441fb 189 }
9a799d71 190
db018963
JK		 191 if (autoneg) {
192 ecmd->supported |= SUPPORTED_Autoneg;
193 ecmd->advertising |= ADVERTISED_Autoneg;
194 ecmd->autoneg = AUTONEG_ENABLE;
195 } else
196 ecmd->autoneg = AUTONEG_DISABLE;
197
198 ecmd->transceiver = XCVR_EXTERNAL;
199
200 /* Determine the remaining settings based on the PHY type. */
3b8626ba
PW		 201 switch (adapter->hw.phy.type) {
202 case ixgbe_phy_tn:
fe15e8e1 203 case ixgbe_phy_aq:
3b8626ba 204 case ixgbe_phy_cu_unknown:
db018963
JK		 205 ecmd->supported |= SUPPORTED_TP;
206 ecmd->advertising |= ADVERTISED_TP;
3b8626ba
PW		 207 ecmd->port = PORT_TP;
208 break;
209 case ixgbe_phy_qt:
db018963
JK		 210 ecmd->supported |= SUPPORTED_FIBRE;
211 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
3b8626ba 221 /* SFP+ devices, further checking needed */
db018963 222 switch (adapter->hw.phy.sfp_type) {
3b8626ba
PW		 223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
db018963
JK		 226 ecmd->supported |= SUPPORTED_FIBRE;
227 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 228 ecmd->port = PORT_DA;
229 break;
230 case ixgbe_sfp_type_sr:
231 case ixgbe_sfp_type_lr:
232 case ixgbe_sfp_type_srlr_core0:
233 case ixgbe_sfp_type_srlr_core1:
345be204
DS		 234 case ixgbe_sfp_type_1g_sx_core0:
235 case ixgbe_sfp_type_1g_sx_core1:
236 case ixgbe_sfp_type_1g_lx_core0:
237 case ixgbe_sfp_type_1g_lx_core1:
db018963
JK		 238 ecmd->supported |= SUPPORTED_FIBRE;
239 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 240 ecmd->port = PORT_FIBRE;
241 break;
242 case ixgbe_sfp_type_not_present:
db018963
JK		 243 ecmd->supported |= SUPPORTED_FIBRE;
244 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 245 ecmd->port = PORT_NONE;
246 break;
cb836a97
DS		 247 case ixgbe_sfp_type_1g_cu_core0:
248 case ixgbe_sfp_type_1g_cu_core1:
db018963
JK		 249 ecmd->supported |= SUPPORTED_TP;
250 ecmd->advertising |= ADVERTISED_TP;
cb836a97 251 ecmd->port = PORT_TP;
db018963 252 break;
3b8626ba
PW		 253 case ixgbe_sfp_type_unknown:
254 default:
db018963
JK		 255 ecmd->supported |= SUPPORTED_FIBRE;
256 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 257 ecmd->port = PORT_OTHER;
258 break;
259 }
260 break;
261 case ixgbe_phy_xaui:
db018963
JK		 262 ecmd->supported |= SUPPORTED_FIBRE;
263 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 264 ecmd->port = PORT_NONE;
265 break;
266 case ixgbe_phy_unknown:
267 case ixgbe_phy_generic:
268 case ixgbe_phy_sfp_unsupported:
269 default:
db018963
JK		 270 ecmd->supported |= SUPPORTED_FIBRE;
271 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 272 ecmd->port = PORT_OTHER;
273 break;
274 }
275
c44ade9e 276 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 277 if (link_up) {
1b1c0a48
AS		 278 switch (link_speed) {
279 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 280 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 281 break;
282 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 283 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 284 break;
285 case IXGBE_LINK_SPEED_100_FULL:
70739497 286 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 287 break;
288 default:
289 break;
290 }
9a799d71
AK		 291 ecmd->duplex = DUPLEX_FULL;
292 } else {
70739497 293 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 294 ecmd->duplex = -1;
295 }
296
9a799d71
AK		 297 return 0;
298}
299
300static int ixgbe_set_settings(struct net_device *netdev,
b4617240 301 struct ethtool_cmd *ecmd)
9a799d71
AK		 302{
303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 304 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 305 u32 advertised, old;
74766013 306 s32 err = 0;
9a799d71 307
74766013 308 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 309 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 310 /*
311 * this function does not support duplex forcing, but can
312 * limit the advertising of the adapter to the specified speed
313 */
0befdb3e
JB		 314 if (ecmd->autoneg == AUTONEG_DISABLE)
315 return -EINVAL;
316
abcc80d2
ET		 317 if (ecmd->advertising & ~ecmd->supported)
318 return -EINVAL;
319
0befdb3e
JB		 320 old = hw->phy.autoneg_advertised;
321 advertised = 0;
322 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
323 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
324
325 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
326 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
327
2b642ca5
ET		 328 if (ecmd->advertising & ADVERTISED_100baseT_Full)
329 advertised |= IXGBE_LINK_SPEED_100_FULL;
330
0befdb3e 331 if (old == advertised)
74766013 332 return err;
0befdb3e 333 /* this sets the link speed and restarts auto-neg */
74766013 334 hw->mac.autotry_restart = true;
fd0326f2 335 err = hw->mac.ops.setup_link(hw, advertised, true);
0befdb3e 336 if (err) {
396e799c 337 e_info(probe, "setup link failed with code %d\n", err);
fd0326f2 338 hw->mac.ops.setup_link(hw, old, true);
0befdb3e 339 }
74766013
MC		 340 } else {
341 /* in this case we currently only support 10Gb/FULL */
25db0338 342 u32 speed = ethtool_cmd_speed(ecmd);
74766013 343 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 344 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 345 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 346 return -EINVAL;
9a799d71
AK		 347 }
348
74766013 349 return err;
9a799d71
AK		 350}
351
352static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 353 struct ethtool_pauseparam *pause)
9a799d71
AK		 354{
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
357
73d80953
DS		 358 if (ixgbe_device_supports_autoneg_fc(hw) &&
359 !hw->fc.disable_fc_autoneg)
71fd570b 360 pause->autoneg = 1;
73d80953
DS		 361 else
362 pause->autoneg = 0;
9a799d71 363
0ecc061d 364 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 365 pause->rx_pause = 1;
0ecc061d 366 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 367 pause->tx_pause = 1;
0ecc061d 368 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 369 pause->rx_pause = 1;
370 pause->tx_pause = 1;
371 }
372}
373
374static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 375 struct ethtool_pauseparam *pause)
9a799d71
AK		 376{
377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
378 struct ixgbe_hw *hw = &adapter->hw;
943561d3 379 struct ixgbe_fc_info fc = hw->fc;
9a799d71 380
943561d3
AD		 381 /* 82598 does no support link flow control with DCB enabled */
382 if ((hw->mac.type == ixgbe_mac_82598EB) &&
383 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
264857b8
PWJ		 384 return -EINVAL;
385
db2adc2d
JK		 386 /* some devices do not support autoneg of link flow control */
387 if ((pause->autoneg == AUTONEG_ENABLE) &&
73d80953 388 !ixgbe_device_supports_autoneg_fc(hw))
db2adc2d
JK		 389 return -EINVAL;
390
943561d3 391 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
71fd570b 392
1c4f0ef8 393 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 394 fc.requested_mode = ixgbe_fc_full;
9a799d71 395 else if (pause->rx_pause && !pause->tx_pause)
620fa036 396 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 397 else if (!pause->rx_pause && pause->tx_pause)
620fa036 398 fc.requested_mode = ixgbe_fc_tx_pause;
9c83b070 399 else
943561d3 400 fc.requested_mode = ixgbe_fc_none;
620fa036
MC		 401
402 /* if the thing changed then we'll update and use new autoneg */
403 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
404 hw->fc = fc;
405 if (netif_running(netdev))
406 ixgbe_reinit_locked(adapter);
407 else
408 ixgbe_reset(adapter);
409 }
9a799d71
AK		 410
411 return 0;
412}
413
9a799d71
AK		 414static u32 ixgbe_get_msglevel(struct net_device *netdev)
415{
416 struct ixgbe_adapter *adapter = netdev_priv(netdev);
417 return adapter->msg_enable;
418}
419
420static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
421{
422 struct ixgbe_adapter *adapter = netdev_priv(netdev);
423 adapter->msg_enable = data;
424}
425
426static int ixgbe_get_regs_len(struct net_device *netdev)
427{
217995ec 428#define IXGBE_REGS_LEN 1129
9a799d71
AK		 429 return IXGBE_REGS_LEN * sizeof(u32);
430}
431
432#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
433
434static void ixgbe_get_regs(struct net_device *netdev,
b4617240 435 struct ethtool_regs *regs, void *p)
9a799d71
AK		 436{
437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
438 struct ixgbe_hw *hw = &adapter->hw;
439 u32 *regs_buff = p;
440 u8 i;
441
442 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
443
c4a56de8
ET		 444 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
445 hw->device_id;
9a799d71
AK		 446
447 /* General Registers */
448 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
449 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
450 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
451 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
452 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
453 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
454 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
455 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
456
457 /* NVM Register */
458 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
459 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
460 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
461 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
462 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
463 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
464 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
465 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
466 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
467 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
468
469 /* Interrupt */
98c00a1c
JB		 470 /* don't read EICR because it can clear interrupt causes, instead
471 * read EICS which is a shadow but doesn't clear EICR */
472 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 473 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
474 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
475 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
476 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
477 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
478 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
479 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
480 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
481 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 482 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 483 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
484
485 /* Flow Control */
486 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
487 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
488 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
489 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
490 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 491 for (i = 0; i < 8; i++) {
492 switch (hw->mac.type) {
493 case ixgbe_mac_82598EB:
494 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
495 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
496 break;
497 case ixgbe_mac_82599EB:
80bb25e3 498 case ixgbe_mac_X540:
bd508178
AD		 499 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
500 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
501 break;
502 default:
503 break;
504 }
505 }
9a799d71
AK		 506 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
507 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
508
509 /* Receive DMA */
510 for (i = 0; i < 64; i++)
511 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
512 for (i = 0; i < 64; i++)
513 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
514 for (i = 0; i < 64; i++)
515 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
516 for (i = 0; i < 64; i++)
517 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
518 for (i = 0; i < 64; i++)
519 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
520 for (i = 0; i < 64; i++)
521 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
522 for (i = 0; i < 16; i++)
523 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
524 for (i = 0; i < 16; i++)
525 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
526 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
527 for (i = 0; i < 8; i++)
528 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
529 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
530 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
531
532 /* Receive */
533 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
534 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
535 for (i = 0; i < 16; i++)
536 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
537 for (i = 0; i < 16; i++)
538 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 539 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 540 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
541 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
542 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
543 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
544 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
545 for (i = 0; i < 8; i++)
546 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
547 for (i = 0; i < 8; i++)
548 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
549 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
550
551 /* Transmit */
552 for (i = 0; i < 32; i++)
553 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
554 for (i = 0; i < 32; i++)
555 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
556 for (i = 0; i < 32; i++)
557 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
558 for (i = 0; i < 32; i++)
559 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
560 for (i = 0; i < 32; i++)
561 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
562 for (i = 0; i < 32; i++)
563 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
564 for (i = 0; i < 32; i++)
565 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
566 for (i = 0; i < 32; i++)
567 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
568 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
569 for (i = 0; i < 16; i++)
570 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
571 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
572 for (i = 0; i < 8; i++)
573 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
574 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
575
576 /* Wake Up */
577 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
578 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
579 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
580 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
581 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
582 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
583 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
584 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 585 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 586
673ac604 587 /* DCB */
9a799d71
AK		 588 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
589 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
590 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
591 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
592 for (i = 0; i < 8; i++)
593 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
594 for (i = 0; i < 8; i++)
595 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
596 for (i = 0; i < 8; i++)
597 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
598 for (i = 0; i < 8; i++)
599 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
600 for (i = 0; i < 8; i++)
601 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
602 for (i = 0; i < 8; i++)
603 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
604
605 /* Statistics */
606 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
607 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
608 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
609 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
610 for (i = 0; i < 8; i++)
611 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
612 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
613 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
614 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
615 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
616 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
617 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
618 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
619 for (i = 0; i < 8; i++)
620 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
621 for (i = 0; i < 8; i++)
622 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
623 for (i = 0; i < 8; i++)
624 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
625 for (i = 0; i < 8; i++)
626 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
627 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
628 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
629 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
630 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
631 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
632 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
633 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
634 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
635 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
636 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
637 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
638 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
639 for (i = 0; i < 8; i++)
640 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
641 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
642 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
643 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
644 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
645 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
646 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
647 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
648 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
649 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
650 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
651 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
652 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
653 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
654 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
655 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
656 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
657 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
658 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
659 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
660 for (i = 0; i < 16; i++)
661 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
662 for (i = 0; i < 16; i++)
663 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
664 for (i = 0; i < 16; i++)
665 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
666 for (i = 0; i < 16; i++)
667 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
668
669 /* MAC */
670 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
671 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
672 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
673 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
674 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
675 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
676 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
677 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
678 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
679 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
680 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
681 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
682 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
683 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
684 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
685 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
686 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
687 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
688 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
689 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
690 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
691 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
692 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
693 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
694 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
695 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
696 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
697 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
698 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
699 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
700 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
701 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
702 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
703
704 /* Diagnostic */
705 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
706 for (i = 0; i < 8; i++)
98c00a1c 707 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 708 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 709 for (i = 0; i < 4; i++)
710 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 711 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
712 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
713 for (i = 0; i < 8; i++)
98c00a1c 714 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 715 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 716 for (i = 0; i < 4; i++)
717 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 718 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
719 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
720 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
721 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
722 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
723 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
724 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
725 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
726 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
727 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
728 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
729 for (i = 0; i < 8; i++)
98c00a1c 730 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 731 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
732 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
733 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
734 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
735 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
736 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
737 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
738 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
739 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
217995ec
ET		 740
741 /* 82599 X540 specific registers */
742 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
9a799d71
AK		 743}
744
745static int ixgbe_get_eeprom_len(struct net_device *netdev)
746{
747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
748 return adapter->hw.eeprom.word_size * 2;
749}
750
751static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 752 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 753{
754 struct ixgbe_adapter *adapter = netdev_priv(netdev);
755 struct ixgbe_hw *hw = &adapter->hw;
756 u16 *eeprom_buff;
757 int first_word, last_word, eeprom_len;
758 int ret_val = 0;
759 u16 i;
760
761 if (eeprom->len == 0)
762 return -EINVAL;
763
764 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
765
766 first_word = eeprom->offset >> 1;
767 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
768 eeprom_len = last_word - first_word + 1;
769
770 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
771 if (!eeprom_buff)
772 return -ENOMEM;
773
68c7005d
ET		 774 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
775 eeprom_buff);
9a799d71
AK		 776
777 /* Device's eeprom is always little-endian, word addressable */
778 for (i = 0; i < eeprom_len; i++)
779 le16_to_cpus(&eeprom_buff[i]);
780
781 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
782 kfree(eeprom_buff);
783
784 return ret_val;
785}
786
2fa5eef4
ET		 787static int ixgbe_set_eeprom(struct net_device *netdev,
788 struct ethtool_eeprom *eeprom, u8 *bytes)
789{
790 struct ixgbe_adapter *adapter = netdev_priv(netdev);
791 struct ixgbe_hw *hw = &adapter->hw;
792 u16 *eeprom_buff;
793 void *ptr;
794 int max_len, first_word, last_word, ret_val = 0;
795 u16 i;
796
797 if (eeprom->len == 0)
798 return -EINVAL;
799
800 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
801 return -EINVAL;
802
803 max_len = hw->eeprom.word_size * 2;
804
805 first_word = eeprom->offset >> 1;
806 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
807 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
808 if (!eeprom_buff)
809 return -ENOMEM;
810
811 ptr = eeprom_buff;
812
813 if (eeprom->offset & 1) {
814 /*
815 * need read/modify/write of first changed EEPROM word
816 * only the second byte of the word is being modified
817 */
818 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
819 if (ret_val)
820 goto err;
821
822 ptr++;
823 }
824 if ((eeprom->offset + eeprom->len) & 1) {
825 /*
826 * need read/modify/write of last changed EEPROM word
827 * only the first byte of the word is being modified
828 */
829 ret_val = hw->eeprom.ops.read(hw, last_word,
830 &eeprom_buff[last_word - first_word]);
831 if (ret_val)
832 goto err;
833 }
834
835 /* Device's eeprom is always little-endian, word addressable */
836 for (i = 0; i < last_word - first_word + 1; i++)
837 le16_to_cpus(&eeprom_buff[i]);
838
839 memcpy(ptr, bytes, eeprom->len);
840
841 for (i = 0; i < last_word - first_word + 1; i++)
842 cpu_to_le16s(&eeprom_buff[i]);
843
844 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
845 last_word - first_word + 1,
846 eeprom_buff);
847
848 /* Update the checksum */
849 if (ret_val == 0)
850 hw->eeprom.ops.update_checksum(hw);
851
852err:
853 kfree(eeprom_buff);
854 return ret_val;
855}
856
9a799d71 857static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 858 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 859{
860 struct ixgbe_adapter *adapter = netdev_priv(netdev);
15e5209f 861 u32 nvm_track_id;
9a799d71 862
612a94d6
RJ		 863 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
864 strlcpy(drvinfo->version, ixgbe_driver_version,
865 sizeof(drvinfo->version));
083fc582 866
15e5209f
ET		 867 nvm_track_id = (adapter->eeprom_verh << 16) |
868 adapter->eeprom_verl;
612a94d6 869 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
15e5209f 870 nvm_track_id);
083fc582 871
612a94d6
RJ		 872 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
873 sizeof(drvinfo->bus_info));
9a799d71 874 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 875 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 876 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
877}
878
879static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 880 struct ethtool_ringparam *ring)
9a799d71
AK		 881{
882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 883 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
884 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 885
886 ring->rx_max_pending = IXGBE_MAX_RXD;
887 ring->tx_max_pending = IXGBE_MAX_TXD;
9a799d71
AK		 888 ring->rx_pending = rx_ring->count;
889 ring->tx_pending = tx_ring->count;
9a799d71
AK		 890}
891
892static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 893 struct ethtool_ringparam *ring)
9a799d71
AK		 894{
895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1f4702aa 896 struct ixgbe_ring *temp_ring;
759884b4 897 int i, err = 0;
c431f97e 898 u32 new_rx_count, new_tx_count;
9a799d71
AK		 899
900 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
901 return -EINVAL;
902
1f4702aa
AD		 903 new_tx_count = clamp_t(u32, ring->tx_pending,
904 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
9a799d71
AK		 905 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
906
1f4702aa
AD		 907 new_rx_count = clamp_t(u32, ring->rx_pending,
908 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
909 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
910
911 if ((new_tx_count == adapter->tx_ring_count) &&
912 (new_rx_count == adapter->rx_ring_count)) {
9a799d71
AK		 913 /* nothing to do */
914 return 0;
915 }
916
d4f80882 917 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 918 usleep_range(1000, 2000);
d4f80882 919
759884b4
AD		 920 if (!netif_running(adapter->netdev)) {
921 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 922 adapter->tx_ring[i]->count = new_tx_count;
759884b4 923 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 924 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 925 adapter->tx_ring_count = new_tx_count;
926 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 927 goto clear_reset;
759884b4
AD		 928 }
929
1f4702aa
AD		 930 /* allocate temporary buffer to store rings in */
931 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
932 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
933
934 if (!temp_ring) {
f9ed8854 935 err = -ENOMEM;
4a0b9ca0 936 goto clear_reset;
f9ed8854
MC		 937 }
938
1f4702aa
AD		 939 ixgbe_down(adapter);
940
941 /*
942 * Setup new Tx resources and free the old Tx resources in that order.
943 * We can then assign the new resources to the rings via a memcpy.
944 * The advantage to this approach is that we are guaranteed to still
945 * have resources even in the case of an allocation failure.
946 */
f9ed8854 947 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 948 for (i = 0; i < adapter->num_tx_queues; i++) {
1f4702aa 949 memcpy(&temp_ring[i], adapter->tx_ring[i],
4a0b9ca0 950 sizeof(struct ixgbe_ring));
1f4702aa
AD		 951
952 temp_ring[i].count = new_tx_count;
953 err = ixgbe_setup_tx_resources(&temp_ring[i]);
9a799d71 954 if (err) {
c431f97e
JB		 955 while (i) {
956 i--;
1f4702aa 957 ixgbe_free_tx_resources(&temp_ring[i]);
c431f97e 958 }
1f4702aa 959 goto err_setup;
9a799d71 960 }
9a799d71 961 }
9a799d71 962
1f4702aa
AD		 963 for (i = 0; i < adapter->num_tx_queues; i++) {
964 ixgbe_free_tx_resources(adapter->tx_ring[i]);
965
966 memcpy(adapter->tx_ring[i], &temp_ring[i],
967 sizeof(struct ixgbe_ring));
968 }
969
970 adapter->tx_ring_count = new_tx_count;
d3fa4721 971 }
9a799d71 972
1f4702aa 973 /* Repeat the process for the Rx rings if needed */
f9ed8854 974 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 975 for (i = 0; i < adapter->num_rx_queues; i++) {
1f4702aa 976 memcpy(&temp_ring[i], adapter->rx_ring[i],
4a0b9ca0 977 sizeof(struct ixgbe_ring));
1f4702aa
AD		 978
979 temp_ring[i].count = new_rx_count;
980 err = ixgbe_setup_rx_resources(&temp_ring[i]);
9a799d71 981 if (err) {
c431f97e
JB		 982 while (i) {
983 i--;
1f4702aa 984 ixgbe_free_rx_resources(&temp_ring[i]);
c431f97e 985 }
9a799d71
AK		 986 goto err_setup;
987 }
1f4702aa 988
9a799d71 989 }
f9ed8854 990
1f4702aa
AD		 991 for (i = 0; i < adapter->num_rx_queues; i++) {
992 ixgbe_free_rx_resources(adapter->rx_ring[i]);
f9ed8854 993
1f4702aa
AD		 994 memcpy(adapter->rx_ring[i], &temp_ring[i],
995 sizeof(struct ixgbe_ring));
f9ed8854
MC		 996 }
997
1f4702aa 998 adapter->rx_ring_count = new_rx_count;
759884b4 999 }
4a0b9ca0 1000
f9ed8854 1001err_setup:
1f4702aa
AD		 1002 ixgbe_up(adapter);
1003 vfree(temp_ring);
4a0b9ca0 1004clear_reset:
d4f80882 1005 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1006 return err;
1007}
1008
b9f2c044 1009static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1010{
b9f2c044 1011 switch (sset) {
da4dd0f7
PWJ		 1012 case ETH_SS_TEST:
1013 return IXGBE_TEST_LEN;
b9f2c044
JG		 1014 case ETH_SS_STATS:
1015 return IXGBE_STATS_LEN;
1016 default:
1017 return -EOPNOTSUPP;
1018 }
9a799d71
AK		 1019}
1020
1021static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 1022 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1023{
1024 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1025 struct rtnl_link_stats64 temp;
1026 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1027 unsigned int start;
1028 struct ixgbe_ring *ring;
1029 int i, j;
29c3a050 1030 char *p = NULL;
9a799d71
AK		 1031
1032 ixgbe_update_stats(adapter);
28172739 1033 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1034 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1035 switch (ixgbe_gstrings_stats[i].type) {
1036 case NETDEV_STATS:
28172739 1037 p = (char *) net_stats +
29c3a050
AK		 1038 ixgbe_gstrings_stats[i].stat_offset;
1039 break;
1040 case IXGBE_STATS:
1041 p = (char *) adapter +
1042 ixgbe_gstrings_stats[i].stat_offset;
1043 break;
f752be9c
JH		 1044 default:
1045 data[i] = 0;
1046 continue;
29c3a050
AK		 1047 }
1048
9a799d71 1049 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1050 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71 1051 }
bd8a1b12 1052 for (j = 0; j < netdev->num_tx_queues; j++) {
de1036b1 1053 ring = adapter->tx_ring[j];
9cc00b51
JF		 1054 if (!ring) {
1055 data[i] = 0;
1056 data[i+1] = 0;
1057 i += 2;
7e15b90f
ET		 1058#ifdef LL_EXTENDED_STATS
1059 data[i] = 0;
1060 data[i+1] = 0;
1061 data[i+2] = 0;
1062 i += 3;
1063#endif
9cc00b51
JF		 1064 continue;
1065 }
1066
de1036b1
ED		 1067 do {
1068 start = u64_stats_fetch_begin_bh(&ring->syncp);
1069 data[i] = ring->stats.packets;
1070 data[i+1] = ring->stats.bytes;
1071 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1072 i += 2;
7e15b90f
ET		 1073#ifdef LL_EXTENDED_STATS
1074 data[i] = ring->stats.yields;
1075 data[i+1] = ring->stats.misses;
1076 data[i+2] = ring->stats.cleaned;
1077 i += 3;
1078#endif
9a799d71 1079 }
9cc00b51 1080 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1081 ring = adapter->rx_ring[j];
9cc00b51
JF		 1082 if (!ring) {
1083 data[i] = 0;
1084 data[i+1] = 0;
1085 i += 2;
7e15b90f
ET		 1086#ifdef LL_EXTENDED_STATS
1087 data[i] = 0;
1088 data[i+1] = 0;
1089 data[i+2] = 0;
1090 i += 3;
1091#endif
9cc00b51
JF		 1092 continue;
1093 }
1094
de1036b1
ED		 1095 do {
1096 start = u64_stats_fetch_begin_bh(&ring->syncp);
1097 data[i] = ring->stats.packets;
1098 data[i+1] = ring->stats.bytes;
1099 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1100 i += 2;
7e15b90f
ET		 1101#ifdef LL_EXTENDED_STATS
1102 data[i] = ring->stats.yields;
1103 data[i+1] = ring->stats.misses;
1104 data[i+2] = ring->stats.cleaned;
1105 i += 3;
1106#endif
9a799d71 1107 }
9cc00b51
JF		 1108
1109 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1110 data[i++] = adapter->stats.pxontxc[j];
1111 data[i++] = adapter->stats.pxofftxc[j];
1112 }
1113 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1114 data[i++] = adapter->stats.pxonrxc[j];
1115 data[i++] = adapter->stats.pxoffrxc[j];
2f90b865 1116 }
9a799d71
AK		 1117}
1118
1119static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1120 u8 *data)
9a799d71 1121{
c44ade9e 1122 char *p = (char *)data;
9a799d71
AK		 1123 int i;
1124
1125 switch (stringset) {
da4dd0f7 1126 case ETH_SS_TEST:
d2c47b62
JH		 1127 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1128 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1129 data += ETH_GSTRING_LEN;
1130 }
da4dd0f7 1131 break;
9a799d71
AK		 1132 case ETH_SS_STATS:
1133 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1134 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1135 ETH_GSTRING_LEN);
1136 p += ETH_GSTRING_LEN;
1137 }
9cc00b51 1138 for (i = 0; i < netdev->num_tx_queues; i++) {
9a799d71
AK		 1139 sprintf(p, "tx_queue_%u_packets", i);
1140 p += ETH_GSTRING_LEN;
1141 sprintf(p, "tx_queue_%u_bytes", i);
1142 p += ETH_GSTRING_LEN;
7e15b90f 1143#ifdef LL_EXTENDED_STATS
9c432ada 1144 sprintf(p, "tx_queue_%u_ll_napi_yield", i);
7e15b90f 1145 p += ETH_GSTRING_LEN;
9c432ada 1146 sprintf(p, "tx_queue_%u_ll_misses", i);
7e15b90f 1147 p += ETH_GSTRING_LEN;
9c432ada 1148 sprintf(p, "tx_queue_%u_ll_cleaned", i);
7e15b90f
ET		 1149 p += ETH_GSTRING_LEN;
1150#endif /* LL_EXTENDED_STATS */
9a799d71 1151 }
9cc00b51 1152 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
9a799d71
AK		 1153 sprintf(p, "rx_queue_%u_packets", i);
1154 p += ETH_GSTRING_LEN;
1155 sprintf(p, "rx_queue_%u_bytes", i);
1156 p += ETH_GSTRING_LEN;
7e15b90f 1157#ifdef LL_EXTENDED_STATS
9c432ada 1158 sprintf(p, "rx_queue_%u_ll_poll_yield", i);
7e15b90f 1159 p += ETH_GSTRING_LEN;
9c432ada 1160 sprintf(p, "rx_queue_%u_ll_misses", i);
7e15b90f 1161 p += ETH_GSTRING_LEN;
9c432ada 1162 sprintf(p, "rx_queue_%u_ll_cleaned", i);
7e15b90f
ET		 1163 p += ETH_GSTRING_LEN;
1164#endif /* LL_EXTENDED_STATS */
9a799d71 1165 }
9cc00b51
JF		 1166 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1167 sprintf(p, "tx_pb_%u_pxon", i);
1168 p += ETH_GSTRING_LEN;
1169 sprintf(p, "tx_pb_%u_pxoff", i);
1170 p += ETH_GSTRING_LEN;
1171 }
1172 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1173 sprintf(p, "rx_pb_%u_pxon", i);
1174 p += ETH_GSTRING_LEN;
1175 sprintf(p, "rx_pb_%u_pxoff", i);
1176 p += ETH_GSTRING_LEN;
2f90b865 1177 }
b4617240 1178 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1179 break;
1180 }
1181}
1182
da4dd0f7
PWJ		 1183static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1184{
1185 struct ixgbe_hw *hw = &adapter->hw;
1186 bool link_up;
1187 u32 link_speed = 0;
1188 *data = 0;
1189
1190 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1191 if (link_up)
1192 return *data;
1193 else
1194 *data = 1;
1195 return *data;
1196}
1197
1198/* ethtool register test data */
1199struct ixgbe_reg_test {
1200 u16 reg;
1201 u8 array_len;
1202 u8 test_type;
1203 u32 mask;
1204 u32 write;
1205};
1206
1207/* In the hardware, registers are laid out either singly, in arrays
1208 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1209 * most tests take place on arrays or single registers (handled
1210 * as a single-element array) and special-case the tables.
1211 * Table tests are always pattern tests.
1212 *
1213 * We also make provision for some required setup steps by specifying
1214 * registers to be written without any read-back testing.
1215 */
1216
1217#define PATTERN_TEST 1
1218#define SET_READ_TEST 2
1219#define WRITE_NO_TEST 3
1220#define TABLE32_TEST 4
1221#define TABLE64_TEST_LO 5
1222#define TABLE64_TEST_HI 6
1223
1224/* default 82599 register test */
66744500 1225static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1226 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1227 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1228 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1229 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1230 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1231 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1232 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1233 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1234 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1235 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1236 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1237 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1238 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1239 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1240 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1241 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1242 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1243 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1244 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1245 { 0, 0, 0, 0 }
1246};
1247
1248/* default 82598 register test */
66744500 1249static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1250 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1251 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1252 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1253 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1254 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1255 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1256 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1257 /* Enable all four RX queues before testing. */
1258 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1259 /* RDH is read-only for 82598, only test RDT. */
1260 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1261 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1262 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1263 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1264 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1265 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1266 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1267 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1268 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1269 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1270 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1271 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1272 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1273 { 0, 0, 0, 0 }
1274};
1275
95a46011
ET		 1276static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1277 u32 mask, u32 write)
1278{
1279 u32 pat, val, before;
1280 static const u32 test_pattern[] = {
1281 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1282
1283 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1284 before = readl(adapter->hw.hw_addr + reg);
1285 writel((test_pattern[pat] & write),
1286 (adapter->hw.hw_addr + reg));
1287 val = readl(adapter->hw.hw_addr + reg);
1288 if (val != (test_pattern[pat] & write & mask)) {
1289 e_err(drv, "pattern test reg %04X failed: got "
1290 "0x%08X expected 0x%08X\n",
1291 reg, val, (test_pattern[pat] & write & mask));
1292 *data = reg;
1293 writel(before, adapter->hw.hw_addr + reg);
1294 return 1;
1295 }
1296 writel(before, adapter->hw.hw_addr + reg);
1297 }
1298 return 0;
da4dd0f7
PWJ		 1299}
1300
95a46011
ET		 1301static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1302 u32 mask, u32 write)
1303{
1304 u32 val, before;
1305 before = readl(adapter->hw.hw_addr + reg);
1306 writel((write & mask), (adapter->hw.hw_addr + reg));
1307 val = readl(adapter->hw.hw_addr + reg);
1308 if ((write & mask) != (val & mask)) {
1309 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1310 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1311 *data = reg;
1312 writel(before, (adapter->hw.hw_addr + reg));
1313 return 1;
1314 }
1315 writel(before, (adapter->hw.hw_addr + reg));
1316 return 0;
da4dd0f7
PWJ		 1317}
1318
95a46011
ET		 1319#define REG_PATTERN_TEST(reg, mask, write) \
1320 do { \
1321 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1322 return 1; \
1323 } while (0) \
1324
1325
1326#define REG_SET_AND_CHECK(reg, mask, write) \
1327 do { \
1328 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1329 return 1; \
1330 } while (0) \
1331
da4dd0f7
PWJ		 1332static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1333{
66744500 1334 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1335 u32 value, before, after;
1336 u32 i, toggle;
1337
bd508178
AD		 1338 switch (adapter->hw.mac.type) {
1339 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1340 toggle = 0x7FFFF3FF;
1341 test = reg_test_82598;
bd508178
AD		 1342 break;
1343 case ixgbe_mac_82599EB:
b93a2226 1344 case ixgbe_mac_X540:
bd508178
AD		 1345 toggle = 0x7FFFF30F;
1346 test = reg_test_82599;
1347 break;
1348 default:
1349 *data = 1;
1350 return 1;
1351 break;
da4dd0f7
PWJ		 1352 }
1353
1354 /*
1355 * Because the status register is such a special case,
1356 * we handle it separately from the rest of the register
1357 * tests. Some bits are read-only, some toggle, and some
1358 * are writeable on newer MACs.
1359 */
1360 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1361 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1363 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1364 if (value != after) {
396e799c
ET		 1365 e_err(drv, "failed STATUS register test got: 0x%08X "
1366 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1367 *data = 1;
1368 return 1;
1369 }
1370 /* restore previous status */
1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1372
1373 /*
1374 * Perform the remainder of the register test, looping through
1375 * the test table until we either fail or reach the null entry.
1376 */
1377 while (test->reg) {
1378 for (i = 0; i < test->array_len; i++) {
1379 switch (test->test_type) {
1380 case PATTERN_TEST:
1381 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1382 test->mask,
1383 test->write);
da4dd0f7
PWJ		 1384 break;
1385 case SET_READ_TEST:
1386 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1387 test->mask,
1388 test->write);
da4dd0f7
PWJ		 1389 break;
1390 case WRITE_NO_TEST:
1391 writel(test->write,
1392 (adapter->hw.hw_addr + test->reg)
1393 + (i * 0x40));
1394 break;
1395 case TABLE32_TEST:
1396 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1397 test->mask,
1398 test->write);
da4dd0f7
PWJ		 1399 break;
1400 case TABLE64_TEST_LO:
1401 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1402 test->mask,
1403 test->write);
da4dd0f7
PWJ		 1404 break;
1405 case TABLE64_TEST_HI:
1406 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1407 test->mask,
1408 test->write);
da4dd0f7
PWJ		 1409 break;
1410 }
1411 }
1412 test++;
1413 }
1414
1415 *data = 0;
1416 return 0;
1417}
1418
1419static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1420{
1421 struct ixgbe_hw *hw = &adapter->hw;
1422 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1423 *data = 1;
1424 else
1425 *data = 0;
1426 return *data;
1427}
1428
1429static irqreturn_t ixgbe_test_intr(int irq, void *data)
1430{
1431 struct net_device *netdev = (struct net_device *) data;
1432 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1433
1434 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1435
1436 return IRQ_HANDLED;
1437}
1438
1439static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1440{
1441 struct net_device *netdev = adapter->netdev;
1442 u32 mask, i = 0, shared_int = true;
1443 u32 irq = adapter->pdev->irq;
1444
1445 *data = 0;
1446
1447 /* Hook up test interrupt handler just for this test */
1448 if (adapter->msix_entries) {
1449 /* NOTE: we don't test MSI-X interrupts here, yet */
1450 return 0;
1451 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1452 shared_int = false;
a0607fd3 1453 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1454 netdev)) {
1455 *data = 1;
1456 return -1;
1457 }
a0607fd3 1458 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1459 netdev->name, netdev)) {
1460 shared_int = false;
a0607fd3 1461 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1462 netdev->name, netdev)) {
1463 *data = 1;
1464 return -1;
1465 }
396e799c
ET		 1466 e_info(hw, "testing %s interrupt\n", shared_int ?
1467 "shared" : "unshared");
da4dd0f7
PWJ		 1468
1469 /* Disable all the interrupts */
1470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1471 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1472 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1473
1474 /* Test each interrupt */
1475 for (; i < 10; i++) {
1476 /* Interrupt to test */
1477 mask = 1 << i;
1478
1479 if (!shared_int) {
1480 /*
1481 * Disable the interrupts to be reported in
1482 * the cause register and then force the same
1483 * interrupt and see if one gets posted. If
1484 * an interrupt was posted to the bus, the
1485 * test failed.
1486 */
1487 adapter->test_icr = 0;
1488 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1489 ~mask & 0x00007FFF);
1490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1491 ~mask & 0x00007FFF);
945a5151 1492 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1493 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1494
1495 if (adapter->test_icr & mask) {
1496 *data = 3;
1497 break;
1498 }
1499 }
1500
1501 /*
1502 * Enable the interrupt to be reported in the cause
1503 * register and then force the same interrupt and see
1504 * if one gets posted. If an interrupt was not posted
1505 * to the bus, the test failed.
1506 */
1507 adapter->test_icr = 0;
1508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1510 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1511 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1512
1513 if (!(adapter->test_icr &mask)) {
1514 *data = 4;
1515 break;
1516 }
1517
1518 if (!shared_int) {
1519 /*
1520 * Disable the other interrupts to be reported in
1521 * the cause register and then force the other
1522 * interrupts and see if any get posted. If
1523 * an interrupt was posted to the bus, the
1524 * test failed.
1525 */
1526 adapter->test_icr = 0;
1527 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1528 ~mask & 0x00007FFF);
1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1530 ~mask & 0x00007FFF);
945a5151 1531 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1532 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1533
1534 if (adapter->test_icr) {
1535 *data = 5;
1536 break;
1537 }
1538 }
1539 }
1540
1541 /* Disable all the interrupts */
1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1543 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1544 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1545
1546 /* Unhook test interrupt handler */
1547 free_irq(irq, netdev);
1548
1549 return *data;
1550}
1551
1552static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1553{
1554 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1555 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1556 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1557 u32 reg_ctl;
da4dd0f7
PWJ		 1558
1559 /* shut down the DMA engines now so they can be reinitialized later */
1560
1561 /* first Rx */
1562 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1563 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1564 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1565 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1566
1567 /* now Tx */
84418e3b 1568 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1569 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1570 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1571
bd508178
AD		 1572 switch (hw->mac.type) {
1573 case ixgbe_mac_82599EB:
b93a2226 1574 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1575 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1576 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1577 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1578 break;
1579 default:
1580 break;
da4dd0f7
PWJ		 1581 }
1582
1583 ixgbe_reset(adapter);
1584
b6ec895e
AD		 1585 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1586 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1587}
1588
1589static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1590{
1591 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1592 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1593 u32 rctl, reg_data;
84418e3b
AD		 1594 int ret_val;
1595 int err;
da4dd0f7
PWJ		 1596
1597 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1598 tx_ring->count = IXGBE_DEFAULT_TXD;
1599 tx_ring->queue_index = 0;
b6ec895e 1600 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1601 tx_ring->netdev = adapter->netdev;
84418e3b 1602 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
da4dd0f7 1603
b6ec895e 1604 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1605 if (err)
1606 return 1;
da4dd0f7 1607
bd508178
AD		 1608 switch (adapter->hw.mac.type) {
1609 case ixgbe_mac_82599EB:
b93a2226 1610 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1611 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1612 reg_data |= IXGBE_DMATXCTL_TE;
1613 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1614 break;
1615 default:
1616 break;
da4dd0f7 1617 }
f4ec443b 1618
84418e3b 1619 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1620
1621 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1622 rx_ring->count = IXGBE_DEFAULT_RXD;
1623 rx_ring->queue_index = 0;
b6ec895e 1624 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1625 rx_ring->netdev = adapter->netdev;
84418e3b 1626 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
84418e3b 1627
b6ec895e 1628 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1629 if (err) {
da4dd0f7
PWJ		 1630 ret_val = 4;
1631 goto err_nomem;
1632 }
1633
da4dd0f7
PWJ		 1634 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1636
84418e3b 1637 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1638
1639 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1641
da4dd0f7
PWJ		 1642 return 0;
1643
1644err_nomem:
1645 ixgbe_free_desc_rings(adapter);
1646 return ret_val;
1647}
1648
1649static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1650{
1651 struct ixgbe_hw *hw = &adapter->hw;
1652 u32 reg_data;
1653
e7fd9253 1654
84418e3b 1655 /* Setup MAC loopback */
26b4742b 1656 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
da4dd0f7 1657 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1658 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1659
35c7f8a1 1660 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1661 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1662 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1663
26b4742b
ET		 1664 /* X540 needs to set the MACC.FLU bit to force link up */
1665 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1666 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1667 reg_data |= IXGBE_MACC_FLU;
1668 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1669 } else {
1670 if (hw->mac.orig_autoc) {
1671 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1672 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1673 } else {
1674 return 10;
1675 }
1676 }
35c7f8a1 1677 IXGBE_WRITE_FLUSH(hw);
032b4325 1678 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1679
1680 /* Disable Atlas Tx lanes; re-enabled in reset path */
1681 if (hw->mac.type == ixgbe_mac_82598EB) {
1682 u8 atlas;
1683
1684 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1685 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1686 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1687
1688 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1689 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1690 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1691
1692 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1693 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1694 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1695
1696 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1697 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1698 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1699 }
1700
1701 return 0;
1702}
1703
1704static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1705{
1706 u32 reg_data;
1707
1708 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1709 reg_data &= ~IXGBE_HLREG0_LPBK;
1710 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1711}
1712
1713static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
3832b26e 1714 unsigned int frame_size)
da4dd0f7
PWJ		 1715{
1716 memset(skb->data, 0xFF, frame_size);
3832b26e
AD		 1717 frame_size >>= 1;
1718 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1719 memset(&skb->data[frame_size + 10], 0xBE, 1);
1720 memset(&skb->data[frame_size + 12], 0xAF, 1);
da4dd0f7
PWJ		 1721}
1722
3832b26e
AD		 1723static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1724 unsigned int frame_size)
da4dd0f7 1725{
3832b26e
AD		 1726 unsigned char *data;
1727 bool match = true;
1728
1729 frame_size >>= 1;
1730
f800326d 1731 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
3832b26e
AD		 1732
1733 if (data[3] != 0xFF ||
1734 data[frame_size + 10] != 0xBE ||
1735 data[frame_size + 12] != 0xAF)
1736 match = false;
1737
f800326d
AD		 1738 kunmap(rx_buffer->page);
1739
3832b26e 1740 return match;
da4dd0f7
PWJ		 1741}
1742
fc77dc3c 1743static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
3832b26e
AD		 1744 struct ixgbe_ring *tx_ring,
1745 unsigned int size)
84418e3b
AD		 1746{
1747 union ixgbe_adv_rx_desc *rx_desc;
3832b26e
AD		 1748 struct ixgbe_rx_buffer *rx_buffer;
1749 struct ixgbe_tx_buffer *tx_buffer;
84418e3b
AD		 1750 u16 rx_ntc, tx_ntc, count = 0;
1751
1752 /* initialize next to clean and descriptor values */
1753 rx_ntc = rx_ring->next_to_clean;
1754 tx_ntc = tx_ring->next_to_clean;
e4f74028 1755 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b 1756
3832b26e 1757 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
84418e3b 1758 /* check Rx buffer */
3832b26e 1759 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
84418e3b 1760
f800326d
AD		 1761 /* sync Rx buffer for CPU read */
1762 dma_sync_single_for_cpu(rx_ring->dev,
1763 rx_buffer->dma,
1764 ixgbe_rx_bufsz(rx_ring),
1765 DMA_FROM_DEVICE);
84418e3b
AD		 1766
1767 /* verify contents of skb */
3832b26e 1768 if (ixgbe_check_lbtest_frame(rx_buffer, size))
84418e3b
AD		 1769 count++;
1770
f800326d
AD		 1771 /* sync Rx buffer for device write */
1772 dma_sync_single_for_device(rx_ring->dev,
1773 rx_buffer->dma,
1774 ixgbe_rx_bufsz(rx_ring),
1775 DMA_FROM_DEVICE);
1776
84418e3b 1777 /* unmap buffer on Tx side */
3832b26e
AD		 1778 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1779 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
84418e3b
AD		 1780
1781 /* increment Rx/Tx next to clean counters */
1782 rx_ntc++;
1783 if (rx_ntc == rx_ring->count)
1784 rx_ntc = 0;
1785 tx_ntc++;
1786 if (tx_ntc == tx_ring->count)
1787 tx_ntc = 0;
1788
1789 /* fetch next descriptor */
e4f74028 1790 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b
AD		 1791 }
1792
dad8a3b3
JF		 1793 netdev_tx_reset_queue(txring_txq(tx_ring));
1794
84418e3b 1795 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1796 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1797 rx_ring->next_to_clean = rx_ntc;
1798 tx_ring->next_to_clean = tx_ntc;
1799
1800 return count;
1801}
1802
da4dd0f7
PWJ		 1803static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1804{
1805 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1806 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1807 int i, j, lc, good_cnt, ret_val = 0;
1808 unsigned int size = 1024;
1809 netdev_tx_t tx_ret_val;
1810 struct sk_buff *skb;
1811
1812 /* allocate test skb */
1813 skb = alloc_skb(size, GFP_KERNEL);
1814 if (!skb)
1815 return 11;
da4dd0f7 1816
84418e3b
AD		 1817 /* place data into test skb */
1818 ixgbe_create_lbtest_frame(skb, size);
1819 skb_put(skb, size);
da4dd0f7
PWJ		 1820
1821 /*
1822 * Calculate the loop count based on the largest descriptor ring
1823 * The idea is to wrap the largest ring a number of times using 64
1824 * send/receive pairs during each loop
1825 */
1826
1827 if (rx_ring->count <= tx_ring->count)
1828 lc = ((tx_ring->count / 64) * 2) + 1;
1829 else
1830 lc = ((rx_ring->count / 64) * 2) + 1;
1831
da4dd0f7 1832 for (j = 0; j <= lc; j++) {
84418e3b 1833 /* reset count of good packets */
da4dd0f7 1834 good_cnt = 0;
84418e3b
AD		 1835
1836 /* place 64 packets on the transmit queue*/
1837 for (i = 0; i < 64; i++) {
1838 skb_get(skb);
1839 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1840 adapter,
1841 tx_ring);
1842 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1843 good_cnt++;
84418e3b
AD		 1844 }
1845
da4dd0f7 1846 if (good_cnt != 64) {
84418e3b 1847 ret_val = 12;
da4dd0f7
PWJ		 1848 break;
1849 }
84418e3b
AD		 1850
1851 /* allow 200 milliseconds for packets to go from Tx to Rx */
1852 msleep(200);
1853
fc77dc3c 1854 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1855 if (good_cnt != 64) {
1856 ret_val = 13;
da4dd0f7
PWJ		 1857 break;
1858 }
1859 }
1860
84418e3b
AD		 1861 /* free the original skb */
1862 kfree_skb(skb);
1863
da4dd0f7
PWJ		 1864 return ret_val;
1865}
1866
1867static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1868{
1869 *data = ixgbe_setup_desc_rings(adapter);
1870 if (*data)
1871 goto out;
1872 *data = ixgbe_setup_loopback_test(adapter);
1873 if (*data)
1874 goto err_loopback;
1875 *data = ixgbe_run_loopback_test(adapter);
1876 ixgbe_loopback_cleanup(adapter);
1877
1878err_loopback:
1879 ixgbe_free_desc_rings(adapter);
1880out:
1881 return *data;
1882}
1883
1884static void ixgbe_diag_test(struct net_device *netdev,
1885 struct ethtool_test *eth_test, u64 *data)
1886{
1887 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1888 bool if_running = netif_running(netdev);
1889
1890 set_bit(__IXGBE_TESTING, &adapter->state);
1891 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
4ec375b1
ET		 1892 struct ixgbe_hw *hw = &adapter->hw;
1893
e7d481a6
GR		 1894 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1895 int i;
1896 for (i = 0; i < adapter->num_vfs; i++) {
1897 if (adapter->vfinfo[i].clear_to_send) {
1898 netdev_warn(netdev, "%s",
1899 "offline diagnostic is not "
1900 "supported when VFs are "
1901 "present\n");
1902 data[0] = 1;
1903 data[1] = 1;
1904 data[2] = 1;
1905 data[3] = 1;
1906 eth_test->flags |= ETH_TEST_FL_FAILED;
1907 clear_bit(__IXGBE_TESTING,
1908 &adapter->state);
1909 goto skip_ol_tests;
1910 }
1911 }
1912 }
1913
dfcc4615
JK		 1914 /* Offline tests */
1915 e_info(hw, "offline testing starting\n");
1916
dfcc4615
JK		 1917 /* Link test performed before hardware reset so autoneg doesn't
1918 * interfere with test result
1919 */
1920 if (ixgbe_link_test(adapter, &data[4]))
1921 eth_test->flags |= ETH_TEST_FL_FAILED;
1922
4ec375b1
ET		 1923 if (if_running)
1924 /* indicate we're in test mode */
1925 dev_close(netdev);
1926 else
1927 ixgbe_reset(adapter);
1928
396e799c 1929 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1930 if (ixgbe_reg_test(adapter, &data[0]))
1931 eth_test->flags |= ETH_TEST_FL_FAILED;
1932
1933 ixgbe_reset(adapter);
396e799c 1934 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1935 if (ixgbe_eeprom_test(adapter, &data[1]))
1936 eth_test->flags |= ETH_TEST_FL_FAILED;
1937
1938 ixgbe_reset(adapter);
396e799c 1939 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1940 if (ixgbe_intr_test(adapter, &data[2]))
1941 eth_test->flags |= ETH_TEST_FL_FAILED;
1942
bdbec4b8
GR		 1943 /* If SRIOV or VMDq is enabled then skip MAC
1944 * loopback diagnostic. */
1945 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1946 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1947 e_info(hw, "Skip MAC loopback diagnostic in VT "
1948 "mode\n");
bdbec4b8
GR		 1949 data[3] = 0;
1950 goto skip_loopback;
1951 }
1952
da4dd0f7 1953 ixgbe_reset(adapter);
396e799c 1954 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1955 if (ixgbe_loopback_test(adapter, &data[3]))
1956 eth_test->flags |= ETH_TEST_FL_FAILED;
1957
bdbec4b8 1958skip_loopback:
da4dd0f7
PWJ		 1959 ixgbe_reset(adapter);
1960
dfcc4615 1961 /* clear testing bit and return adapter to previous state */
da4dd0f7
PWJ		 1962 clear_bit(__IXGBE_TESTING, &adapter->state);
1963 if (if_running)
1964 dev_open(netdev);
4ec375b1
ET		 1965 else if (hw->mac.ops.disable_tx_laser)
1966 hw->mac.ops.disable_tx_laser(hw);
da4dd0f7 1967 } else {
396e799c 1968 e_info(hw, "online testing starting\n");
dfcc4615 1969
da4dd0f7
PWJ		 1970 /* Online tests */
1971 if (ixgbe_link_test(adapter, &data[4]))
1972 eth_test->flags |= ETH_TEST_FL_FAILED;
1973
dfcc4615 1974 /* Offline tests aren't run; pass by default */
da4dd0f7
PWJ		 1975 data[0] = 0;
1976 data[1] = 0;
1977 data[2] = 0;
1978 data[3] = 0;
1979
1980 clear_bit(__IXGBE_TESTING, &adapter->state);
1981 }
dfcc4615 1982
e7d481a6 1983skip_ol_tests:
da4dd0f7
PWJ		 1984 msleep_interruptible(4 * 1000);
1985}
9a799d71 1986
d6c519e1
AD		 1987static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1988 struct ethtool_wolinfo *wol)
1989{
1990 struct ixgbe_hw *hw = &adapter->hw;
8e2813f5 1991 int retval = 0;
c23f5b6b 1992
8e2813f5
JK		 1993 /* WOL not supported for all devices */
1994 if (!ixgbe_wol_supported(adapter, hw->device_id,
1995 hw->subsystem_device_id)) {
1996 retval = 1;
d6c519e1 1997 wol->supported = 0;
d6c519e1
AD		 1998 }
1999
2000 return retval;
2001}
2002
9a799d71 2003static void ixgbe_get_wol(struct net_device *netdev,
b4617240 2004 struct ethtool_wolinfo *wol)
9a799d71 2005{
e63d9762
PW		 2006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2007
2008 wol->supported = WAKE_UCAST | WAKE_MCAST |
2009 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 2010 wol->wolopts = 0;
2011
d6c519e1
AD		 2012 if (ixgbe_wol_exclusion(adapter, wol) ||
2013 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 2014 return;
2015
2016 if (adapter->wol & IXGBE_WUFC_EX)
2017 wol->wolopts |= WAKE_UCAST;
2018 if (adapter->wol & IXGBE_WUFC_MC)
2019 wol->wolopts |= WAKE_MCAST;
2020 if (adapter->wol & IXGBE_WUFC_BC)
2021 wol->wolopts |= WAKE_BCAST;
2022 if (adapter->wol & IXGBE_WUFC_MAG)
2023 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 2024}
2025
e63d9762
PW		 2026static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2027{
2028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2029
2030 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2031 return -EOPNOTSUPP;
2032
d6c519e1
AD		 2033 if (ixgbe_wol_exclusion(adapter, wol))
2034 return wol->wolopts ? -EOPNOTSUPP : 0;
2035
e63d9762
PW		 2036 adapter->wol = 0;
2037
2038 if (wol->wolopts & WAKE_UCAST)
2039 adapter->wol |= IXGBE_WUFC_EX;
2040 if (wol->wolopts & WAKE_MCAST)
2041 adapter->wol |= IXGBE_WUFC_MC;
2042 if (wol->wolopts & WAKE_BCAST)
2043 adapter->wol |= IXGBE_WUFC_BC;
2044 if (wol->wolopts & WAKE_MAGIC)
2045 adapter->wol |= IXGBE_WUFC_MAG;
2046
2047 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2048
2049 return 0;
2050}
2051
9a799d71
AK		 2052static int ixgbe_nway_reset(struct net_device *netdev)
2053{
2054 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2055
d4f80882
AV		 2056 if (netif_running(netdev))
2057 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2058
2059 return 0;
2060}
2061
66e6961c
ET		 2062static int ixgbe_set_phys_id(struct net_device *netdev,
2063 enum ethtool_phys_id_state state)
9a799d71
AK		 2064{
2065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2066 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2067
66e6961c
ET		 2068 switch (state) {
2069 case ETHTOOL_ID_ACTIVE:
2070 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2071 return 2;
9a799d71 2072
66e6961c 2073 case ETHTOOL_ID_ON:
c44ade9e 2074 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2075 break;
2076
2077 case ETHTOOL_ID_OFF:
c44ade9e 2078 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2079 break;
9a799d71 2080
66e6961c
ET		 2081 case ETHTOOL_ID_INACTIVE:
2082 /* Restore LED settings */
2083 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2084 break;
2085 }
9a799d71
AK		 2086
2087 return 0;
2088}
2089
2090static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2091 struct ethtool_coalesce *ec)
9a799d71
AK		 2092{
2093 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2094
30efa5a3 2095 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2096 if (adapter->rx_itr_setting <= 1)
2097 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2098 else
2099 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
f7554a2b 2100
cfb3f91a 2101 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2102 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2103 return 0;
2104
f7554a2b 2105 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2106 if (adapter->tx_itr_setting <= 1)
2107 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2108 else
2109 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
f7554a2b 2110
9a799d71
AK		 2111 return 0;
2112}
2113
80fba3f4
AD		 2114/*
2115 * this function must be called before setting the new value of
2116 * rx_itr_setting
2117 */
567d2de2 2118static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
80fba3f4
AD		 2119{
2120 struct net_device *netdev = adapter->netdev;
2121
567d2de2
AD		 2122 /* nothing to do if LRO or RSC are not enabled */
2123 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2124 !(netdev->features & NETIF_F_LRO))
80fba3f4
AD		 2125 return false;
2126
567d2de2
AD		 2127 /* check the feature flag value and enable RSC if necessary */
2128 if (adapter->rx_itr_setting == 1 ||
2129 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2130 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
80fba3f4 2131 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
567d2de2
AD		 2132 e_info(probe, "rx-usecs value high enough "
2133 "to re-enable RSC\n");
80fba3f4
AD		 2134 return true;
2135 }
567d2de2
AD		 2136 /* if interrupt rate is too high then disable RSC */
2137 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2138 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2139 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2140 return true;
80fba3f4
AD		 2141 }
2142 return false;
2143}
2144
9a799d71 2145static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2146 struct ethtool_coalesce *ec)
9a799d71
AK		 2147{
2148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2149 struct ixgbe_q_vector *q_vector;
30efa5a3 2150 int i;
67da097e 2151 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
ef021194 2152 bool need_reset = false;
9a799d71 2153
67da097e
ET		 2154 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2155 /* reject Tx specific changes in case of mixed RxTx vectors */
2156 if (ec->tx_coalesce_usecs)
2157 return -EINVAL;
2158 tx_itr_prev = adapter->rx_itr_setting;
2159 } else {
2160 tx_itr_prev = adapter->tx_itr_setting;
2161 }
f7554a2b 2162
d5bf4f67
ET		 2163 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2164 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2165 return -EINVAL;
30efa5a3 2166
d5bf4f67
ET		 2167 if (ec->rx_coalesce_usecs > 1)
2168 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2169 else
2170 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
f7554a2b 2171
d5bf4f67
ET		 2172 if (adapter->rx_itr_setting == 1)
2173 rx_itr_param = IXGBE_20K_ITR;
2174 else
2175 rx_itr_param = adapter->rx_itr_setting;
f7554a2b 2176
d5bf4f67
ET		 2177 if (ec->tx_coalesce_usecs > 1)
2178 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2179 else
2180 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
f7554a2b 2181
d5bf4f67
ET		 2182 if (adapter->tx_itr_setting == 1)
2183 tx_itr_param = IXGBE_10K_ITR;
2184 else
2185 tx_itr_param = adapter->tx_itr_setting;
f7554a2b 2186
67da097e
ET		 2187 /* mixed Rx/Tx */
2188 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2189 adapter->tx_itr_setting = adapter->rx_itr_setting;
2190
2191#if IS_ENABLED(CONFIG_BQL)
2192 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2193 if ((adapter->tx_itr_setting > 1) &&
2194 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2195 if ((tx_itr_prev == 1) ||
2196 (tx_itr_prev > IXGBE_100K_ITR))
2197 need_reset = true;
2198 } else {
2199 if ((tx_itr_prev > 1) &&
2200 (tx_itr_prev < IXGBE_100K_ITR))
2201 need_reset = true;
2202 }
2203#endif
567d2de2 2204 /* check the old value and enable RSC if necessary */
67da097e 2205 need_reset |= ixgbe_update_rsc(adapter);
567d2de2 2206
49c7ffbe 2207 for (i = 0; i < adapter->num_q_vectors; i++) {
d5bf4f67 2208 q_vector = adapter->q_vector[i];
d5bf4f67
ET		 2209 if (q_vector->tx.count && !q_vector->rx.count)
2210 /* tx only */
2211 q_vector->itr = tx_itr_param;
2212 else
2213 /* rx only or mixed */
2214 q_vector->itr = rx_itr_param;
fe49f04a 2215 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2216 }
2217
ef021194
JB		 2218 /*
2219 * do reset here at the end to make sure EITR==0 case is handled
2220 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2221 * also locks in RSC enable/disable which requires reset
2222 */
c988ee82
ET		 2223 if (need_reset)
2224 ixgbe_do_reset(netdev);
ef021194 2225
9a799d71
AK		 2226 return 0;
2227}
2228
3e05334f
AD		 2229static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2230 struct ethtool_rxnfc *cmd)
2231{
2232 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2233 struct ethtool_rx_flow_spec *fsp =
2234 (struct ethtool_rx_flow_spec *)&cmd->fs;
b67bfe0d 2235 struct hlist_node *node2;
3e05334f
AD		 2236 struct ixgbe_fdir_filter *rule = NULL;
2237
2238 /* report total rule count */
2239 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2240
b67bfe0d 2241 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2242 &adapter->fdir_filter_list, fdir_node) {
2243 if (fsp->location <= rule->sw_idx)
2244 break;
2245 }
2246
2247 if (!rule || fsp->location != rule->sw_idx)
2248 return -EINVAL;
2249
2250 /* fill out the flow spec entry */
2251
2252 /* set flow type field */
2253 switch (rule->filter.formatted.flow_type) {
2254 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2255 fsp->flow_type = TCP_V4_FLOW;
2256 break;
2257 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2258 fsp->flow_type = UDP_V4_FLOW;
2259 break;
2260 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2261 fsp->flow_type = SCTP_V4_FLOW;
2262 break;
2263 case IXGBE_ATR_FLOW_TYPE_IPV4:
2264 fsp->flow_type = IP_USER_FLOW;
2265 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2266 fsp->h_u.usr_ip4_spec.proto = 0;
2267 fsp->m_u.usr_ip4_spec.proto = 0;
2268 break;
2269 default:
2270 return -EINVAL;
2271 }
2272
2273 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2274 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2275 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2276 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2277 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2278 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2279 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2280 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2281 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2282 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2283 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2284 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2285 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2286 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2287 fsp->flow_type |= FLOW_EXT;
2288
2289 /* record action */
2290 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2291 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2292 else
2293 fsp->ring_cookie = rule->action;
2294
2295 return 0;
2296}
2297
2298static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2299 struct ethtool_rxnfc *cmd,
2300 u32 *rule_locs)
2301{
b67bfe0d 2302 struct hlist_node *node2;
3e05334f
AD		 2303 struct ixgbe_fdir_filter *rule;
2304 int cnt = 0;
2305
2306 /* report total rule count */
2307 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2308
b67bfe0d 2309 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2310 &adapter->fdir_filter_list, fdir_node) {
2311 if (cnt == cmd->rule_cnt)
2312 return -EMSGSIZE;
2313 rule_locs[cnt] = rule->sw_idx;
2314 cnt++;
2315 }
2316
473e64ee
BH		 2317 cmd->rule_cnt = cnt;
2318
3e05334f
AD		 2319 return 0;
2320}
2321
ef6afc0c
AD		 2322static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2323 struct ethtool_rxnfc *cmd)
2324{
2325 cmd->data = 0;
2326
ef6afc0c
AD		 2327 /* Report default options for RSS on ixgbe */
2328 switch (cmd->flow_type) {
2329 case TCP_V4_FLOW:
2330 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2331 case UDP_V4_FLOW:
2332 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2333 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2334 case SCTP_V4_FLOW:
2335 case AH_ESP_V4_FLOW:
2336 case AH_V4_FLOW:
2337 case ESP_V4_FLOW:
2338 case IPV4_FLOW:
2339 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2340 break;
2341 case TCP_V6_FLOW:
2342 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2343 case UDP_V6_FLOW:
2344 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2345 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2346 case SCTP_V6_FLOW:
2347 case AH_ESP_V6_FLOW:
2348 case AH_V6_FLOW:
2349 case ESP_V6_FLOW:
2350 case IPV6_FLOW:
2351 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2352 break;
2353 default:
2354 return -EINVAL;
2355 }
2356
2357 return 0;
2358}
2359
91cd94bf 2360static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2361 u32 *rule_locs)
91cd94bf
AD		 2362{
2363 struct ixgbe_adapter *adapter = netdev_priv(dev);
2364 int ret = -EOPNOTSUPP;
2365
2366 switch (cmd->cmd) {
2367 case ETHTOOL_GRXRINGS:
2368 cmd->data = adapter->num_rx_queues;
2369 ret = 0;
2370 break;
3e05334f
AD		 2371 case ETHTOOL_GRXCLSRLCNT:
2372 cmd->rule_cnt = adapter->fdir_filter_count;
2373 ret = 0;
2374 break;
2375 case ETHTOOL_GRXCLSRULE:
2376 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2377 break;
2378 case ETHTOOL_GRXCLSRLALL:
815c7db5 2379 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2380 break;
ef6afc0c
AD		 2381 case ETHTOOL_GRXFH:
2382 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2383 break;
91cd94bf
AD		 2384 default:
2385 break;
2386 }
2387
2388 return ret;
2389}
2390
e4911d57
AD		 2391static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2392 struct ixgbe_fdir_filter *input,
2393 u16 sw_idx)
2394{
2395 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d
SL		 2396 struct hlist_node *node2;
2397 struct ixgbe_fdir_filter *rule, *parent;
e4911d57
AD		 2398 int err = -EINVAL;
2399
2400 parent = NULL;
2401 rule = NULL;
2402
b67bfe0d 2403 hlist_for_each_entry_safe(rule, node2,
e4911d57
AD		 2404 &adapter->fdir_filter_list, fdir_node) {
2405 /* hash found, or no matching entry */
2406 if (rule->sw_idx >= sw_idx)
2407 break;
b67bfe0d 2408 parent = rule;
e4911d57
AD		 2409 }
2410
2411 /* if there is an old rule occupying our place remove it */
2412 if (rule && (rule->sw_idx == sw_idx)) {
2413 if (!input || (rule->filter.formatted.bkt_hash !=
2414 input->filter.formatted.bkt_hash)) {
2415 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2416 &rule->filter,
2417 sw_idx);
2418 }
2419
2420 hlist_del(&rule->fdir_node);
2421 kfree(rule);
2422 adapter->fdir_filter_count--;
2423 }
2424
2425 /*
2426 * If no input this was a delete, err should be 0 if a rule was
2427 * successfully found and removed from the list else -EINVAL
2428 */
2429 if (!input)
2430 return err;
2431
2432 /* initialize node and set software index */
2433 INIT_HLIST_NODE(&input->fdir_node);
2434
2435 /* add filter to the list */
2436 if (parent)
b67bfe0d 2437 hlist_add_after(&parent->fdir_node, &input->fdir_node);
e4911d57
AD		 2438 else
2439 hlist_add_head(&input->fdir_node,
2440 &adapter->fdir_filter_list);
2441
2442 /* update counts */
2443 adapter->fdir_filter_count++;
2444
2445 return 0;
2446}
2447
2448static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2449 u8 *flow_type)
2450{
2451 switch (fsp->flow_type & ~FLOW_EXT) {
2452 case TCP_V4_FLOW:
2453 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2454 break;
2455 case UDP_V4_FLOW:
2456 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2457 break;
2458 case SCTP_V4_FLOW:
2459 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2460 break;
2461 case IP_USER_FLOW:
2462 switch (fsp->h_u.usr_ip4_spec.proto) {
2463 case IPPROTO_TCP:
2464 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2465 break;
2466 case IPPROTO_UDP:
2467 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2468 break;
2469 case IPPROTO_SCTP:
2470 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2471 break;
2472 case 0:
2473 if (!fsp->m_u.usr_ip4_spec.proto) {
2474 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2475 break;
2476 }
2477 default:
2478 return 0;
2479 }
2480 break;
2481 default:
2482 return 0;
2483 }
2484
2485 return 1;
2486}
2487
2488static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2489 struct ethtool_rxnfc *cmd)
2490{
2491 struct ethtool_rx_flow_spec *fsp =
2492 (struct ethtool_rx_flow_spec *)&cmd->fs;
2493 struct ixgbe_hw *hw = &adapter->hw;
2494 struct ixgbe_fdir_filter *input;
2495 union ixgbe_atr_input mask;
2496 int err;
2497
2498 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2499 return -EOPNOTSUPP;
2500
2501 /*
2502 * Don't allow programming if the action is a queue greater than
2503 * the number of online Rx queues.
2504 */
2505 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2506 (fsp->ring_cookie >= adapter->num_rx_queues))
2507 return -EINVAL;
2508
2509 /* Don't allow indexes to exist outside of available space */
2510 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2511 e_err(drv, "Location out of range\n");
2512 return -EINVAL;
2513 }
2514
2515 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2516 if (!input)
2517 return -ENOMEM;
2518
2519 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2520
2521 /* set SW index */
2522 input->sw_idx = fsp->location;
2523
2524 /* record flow type */
2525 if (!ixgbe_flowspec_to_flow_type(fsp,
2526 &input->filter.formatted.flow_type)) {
2527 e_err(drv, "Unrecognized flow type\n");
2528 goto err_out;
2529 }
2530
2531 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2532 IXGBE_ATR_L4TYPE_MASK;
2533
2534 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2535 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2536
2537 /* Copy input into formatted structures */
2538 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2539 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2540 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2541 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2542 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2543 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2544 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2545 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2546
2547 if (fsp->flow_type & FLOW_EXT) {
2548 input->filter.formatted.vm_pool =
2549 (unsigned char)ntohl(fsp->h_ext.data[1]);
2550 mask.formatted.vm_pool =
2551 (unsigned char)ntohl(fsp->m_ext.data[1]);
2552 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2553 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2554 input->filter.formatted.flex_bytes =
2555 fsp->h_ext.vlan_etype;
2556 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2557 }
2558
2559 /* determine if we need to drop or route the packet */
2560 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2561 input->action = IXGBE_FDIR_DROP_QUEUE;
2562 else
2563 input->action = fsp->ring_cookie;
2564
2565 spin_lock(&adapter->fdir_perfect_lock);
2566
2567 if (hlist_empty(&adapter->fdir_filter_list)) {
2568 /* save mask and program input mask into HW */
2569 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2570 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2571 if (err) {
2572 e_err(drv, "Error writing mask\n");
2573 goto err_out_w_lock;
2574 }
2575 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2576 e_err(drv, "Only one mask supported per port\n");
2577 goto err_out_w_lock;
2578 }
2579
2580 /* apply mask and compute/store hash */
2581 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2582
2583 /* program filters to filter memory */
2584 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2585 &input->filter, input->sw_idx,
1f4d5183
AD		 2586 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2587 IXGBE_FDIR_DROP_QUEUE :
e4911d57
AD		 2588 adapter->rx_ring[input->action]->reg_idx);
2589 if (err)
2590 goto err_out_w_lock;
2591
2592 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2593
2594 spin_unlock(&adapter->fdir_perfect_lock);
2595
2596 return err;
2597err_out_w_lock:
2598 spin_unlock(&adapter->fdir_perfect_lock);
2599err_out:
2600 kfree(input);
2601 return -EINVAL;
2602}
2603
2604static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2605 struct ethtool_rxnfc *cmd)
2606{
2607 struct ethtool_rx_flow_spec *fsp =
2608 (struct ethtool_rx_flow_spec *)&cmd->fs;
2609 int err;
2610
2611 spin_lock(&adapter->fdir_perfect_lock);
2612 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2613 spin_unlock(&adapter->fdir_perfect_lock);
2614
2615 return err;
2616}
2617
ef6afc0c
AD		 2618#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2619 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2620static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2621 struct ethtool_rxnfc *nfc)
2622{
2623 u32 flags2 = adapter->flags2;
2624
2625 /*
2626 * RSS does not support anything other than hashing
2627 * to queues on src and dst IPs and ports
2628 */
2629 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2630 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2631 return -EINVAL;
2632
2633 switch (nfc->flow_type) {
2634 case TCP_V4_FLOW:
2635 case TCP_V6_FLOW:
2636 if (!(nfc->data & RXH_IP_SRC) ||
2637 !(nfc->data & RXH_IP_DST) ||
2638 !(nfc->data & RXH_L4_B_0_1) ||
2639 !(nfc->data & RXH_L4_B_2_3))
2640 return -EINVAL;
2641 break;
2642 case UDP_V4_FLOW:
2643 if (!(nfc->data & RXH_IP_SRC) ||
2644 !(nfc->data & RXH_IP_DST))
2645 return -EINVAL;
2646 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2647 case 0:
2648 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2649 break;
2650 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2651 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656 break;
2657 case UDP_V6_FLOW:
2658 if (!(nfc->data & RXH_IP_SRC) ||
2659 !(nfc->data & RXH_IP_DST))
2660 return -EINVAL;
2661 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2662 case 0:
2663 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2664 break;
2665 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2666 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2667 break;
2668 default:
2669 return -EINVAL;
2670 }
2671 break;
2672 case AH_ESP_V4_FLOW:
2673 case AH_V4_FLOW:
2674 case ESP_V4_FLOW:
2675 case SCTP_V4_FLOW:
2676 case AH_ESP_V6_FLOW:
2677 case AH_V6_FLOW:
2678 case ESP_V6_FLOW:
2679 case SCTP_V6_FLOW:
2680 if (!(nfc->data & RXH_IP_SRC) ||
2681 !(nfc->data & RXH_IP_DST) ||
2682 (nfc->data & RXH_L4_B_0_1) ||
2683 (nfc->data & RXH_L4_B_2_3))
2684 return -EINVAL;
2685 break;
2686 default:
2687 return -EINVAL;
2688 }
2689
2690 /* if we changed something we need to update flags */
2691 if (flags2 != adapter->flags2) {
2692 struct ixgbe_hw *hw = &adapter->hw;
2693 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2694
2695 if ((flags2 & UDP_RSS_FLAGS) &&
2696 !(adapter->flags2 & UDP_RSS_FLAGS))
2697 e_warn(drv, "enabling UDP RSS: fragmented packets"
2698 " may arrive out of order to the stack above\n");
2699
2700 adapter->flags2 = flags2;
2701
2702 /* Perform hash on these packet types */
2703 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2704 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2705 | IXGBE_MRQC_RSS_FIELD_IPV6
2706 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2707
2708 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2709 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2710
2711 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2712 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2713
2714 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2715 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2716
2717 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2718 }
2719
2720 return 0;
2721}
2722
e4911d57
AD		 2723static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2724{
2725 struct ixgbe_adapter *adapter = netdev_priv(dev);
2726 int ret = -EOPNOTSUPP;
2727
2728 switch (cmd->cmd) {
2729 case ETHTOOL_SRXCLSRLINS:
2730 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2731 break;
2732 case ETHTOOL_SRXCLSRLDEL:
2733 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2734 break;
ef6afc0c
AD		 2735 case ETHTOOL_SRXFH:
2736 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2737 break;
e4911d57
AD		 2738 default:
2739 break;
2740 }
2741
2742 return ret;
2743}
2744
e3aac889
JK		 2745static int ixgbe_get_ts_info(struct net_device *dev,
2746 struct ethtool_ts_info *info)
2747{
2748 struct ixgbe_adapter *adapter = netdev_priv(dev);
2749
2750 switch (adapter->hw.mac.type) {
e3aac889
JK		 2751 case ixgbe_mac_X540:
2752 case ixgbe_mac_82599EB:
2753 info->so_timestamping =
50f8d35d
JK		 2754 SOF_TIMESTAMPING_TX_SOFTWARE |
2755 SOF_TIMESTAMPING_RX_SOFTWARE |
2756 SOF_TIMESTAMPING_SOFTWARE |
e3aac889
JK		 2757 SOF_TIMESTAMPING_TX_HARDWARE |
2758 SOF_TIMESTAMPING_RX_HARDWARE |
2759 SOF_TIMESTAMPING_RAW_HARDWARE;
2760
2761 if (adapter->ptp_clock)
2762 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2763 else
2764 info->phc_index = -1;
2765
2766 info->tx_types =
2767 (1 << HWTSTAMP_TX_OFF) |
2768 (1 << HWTSTAMP_TX_ON);
2769
2770 info->rx_filters =
2771 (1 << HWTSTAMP_FILTER_NONE) |
2772 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2773 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
aeb82648
JK		 2774 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2775 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2776 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2777 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2778 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2779 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2780 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2781 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1cc92eb8 2782 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
e3aac889 2783 break;
e3aac889
JK		 2784 default:
2785 return ethtool_op_get_ts_info(dev, info);
2786 break;
2787 }
2788 return 0;
2789}
2790
5348c9db
AD		 2791static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2792{
2793 unsigned int max_combined;
2794 u8 tcs = netdev_get_num_tc(adapter->netdev);
2795
2796 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2797 /* We only support one q_vector without MSI-X */
2798 max_combined = 1;
2799 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2800 /* SR-IOV currently only allows one queue on the PF */
2801 max_combined = 1;
2802 } else if (tcs > 1) {
2803 /* For DCB report channels per traffic class */
2804 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2805 /* 8 TC w/ 4 queues per TC */
2806 max_combined = 4;
2807 } else if (tcs > 4) {
2808 /* 8 TC w/ 8 queues per TC */
2809 max_combined = 8;
2810 } else {
2811 /* 4 TC w/ 16 queues per TC */
2812 max_combined = 16;
2813 }
2814 } else if (adapter->atr_sample_rate) {
2815 /* support up to 64 queues with ATR */
2816 max_combined = IXGBE_MAX_FDIR_INDICES;
2817 } else {
2818 /* support up to 16 queues with RSS */
2819 max_combined = IXGBE_MAX_RSS_INDICES;
2820 }
2821
2822 return max_combined;
2823}
2824
2825static void ixgbe_get_channels(struct net_device *dev,
2826 struct ethtool_channels *ch)
2827{
2828 struct ixgbe_adapter *adapter = netdev_priv(dev);
2829
2830 /* report maximum channels */
2831 ch->max_combined = ixgbe_max_channels(adapter);
2832
2833 /* report info for other vector */
2834 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2835 ch->max_other = NON_Q_VECTORS;
2836 ch->other_count = NON_Q_VECTORS;
2837 }
2838
2839 /* record RSS queues */
2840 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2841
2842 /* nothing else to report if RSS is disabled */
2843 if (ch->combined_count == 1)
2844 return;
2845
2846 /* we do not support ATR queueing if SR-IOV is enabled */
2847 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2848 return;
2849
2850 /* same thing goes for being DCB enabled */
2851 if (netdev_get_num_tc(dev) > 1)
2852 return;
2853
2854 /* if ATR is disabled we can exit */
2855 if (!adapter->atr_sample_rate)
2856 return;
2857
2858 /* report flow director queues as maximum channels */
2859 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2860}
2861
4c696ca9
AD		 2862static int ixgbe_set_channels(struct net_device *dev,
2863 struct ethtool_channels *ch)
2864{
2865 struct ixgbe_adapter *adapter = netdev_priv(dev);
2866 unsigned int count = ch->combined_count;
2867
2868 /* verify they are not requesting separate vectors */
2869 if (!count || ch->rx_count || ch->tx_count)
2870 return -EINVAL;
2871
2872 /* verify other_count has not changed */
2873 if (ch->other_count != NON_Q_VECTORS)
2874 return -EINVAL;
2875
2876 /* verify the number of channels does not exceed hardware limits */
2877 if (count > ixgbe_max_channels(adapter))
2878 return -EINVAL;
2879
2880 /* update feature limits from largest to smallest supported values */
2881 adapter->ring_feature[RING_F_FDIR].limit = count;
2882
2883 /* cap RSS limit at 16 */
2884 if (count > IXGBE_MAX_RSS_INDICES)
2885 count = IXGBE_MAX_RSS_INDICES;
2886 adapter->ring_feature[RING_F_RSS].limit = count;
2887
2888#ifdef IXGBE_FCOE
2889 /* cap FCoE limit at 8 */
2890 if (count > IXGBE_FCRETA_SIZE)
2891 count = IXGBE_FCRETA_SIZE;
2892 adapter->ring_feature[RING_F_FCOE].limit = count;
2893
2894#endif
2895 /* use setup TC to update any traffic class queue mapping */
2896 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2897}
2898
71858acb
AG		 2899static int ixgbe_get_module_info(struct net_device *dev,
2900 struct ethtool_modinfo *modinfo)
2901{
2902 struct ixgbe_adapter *adapter = netdev_priv(dev);
2903 struct ixgbe_hw *hw = &adapter->hw;
2904 u32 status;
2905 u8 sff8472_rev, addr_mode;
71858acb
AG		 2906 bool page_swap = false;
2907
71858acb
AG		 2908 /* Check whether we support SFF-8472 or not */
2909 status = hw->phy.ops.read_i2c_eeprom(hw,
2910 IXGBE_SFF_SFF_8472_COMP,
2911 &sff8472_rev);
a4b6fc6b
ET		 2912 if (status != 0)
2913 return -EIO;
71858acb
AG		 2914
2915 /* addressing mode is not supported */
2916 status = hw->phy.ops.read_i2c_eeprom(hw,
2917 IXGBE_SFF_SFF_8472_SWAP,
2918 &addr_mode);
a4b6fc6b
ET		 2919 if (status != 0)
2920 return -EIO;
71858acb
AG		 2921
2922 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
2923 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2924 page_swap = true;
2925 }
2926
2927 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
2928 /* We have a SFP, but it does not support SFF-8472 */
2929 modinfo->type = ETH_MODULE_SFF_8079;
2930 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2931 } else {
2932 /* We have a SFP which supports a revision of SFF-8472. */
2933 modinfo->type = ETH_MODULE_SFF_8472;
2934 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2935 }
2936
a4b6fc6b 2937 return 0;
71858acb
AG		 2938}
2939
2940static int ixgbe_get_module_eeprom(struct net_device *dev,
2941 struct ethtool_eeprom *ee,
2942 u8 *data)
2943{
2944 struct ixgbe_adapter *adapter = netdev_priv(dev);
2945 struct ixgbe_hw *hw = &adapter->hw;
2946 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2947 u8 databyte = 0xFF;
2948 int i = 0;
2949 int ret_val = 0;
2950
a4b6fc6b
ET		 2951 if (ee->len == 0)
2952 return -EINVAL;
71858acb 2953
a4b6fc6b
ET		 2954 for (i = ee->offset; i < ee->len; i++) {
2955 /* I2C reads can take long time */
2956 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2957 return -EBUSY;
71858acb 2958
a4b6fc6b
ET		 2959 if (i < ETH_MODULE_SFF_8079_LEN)
2960 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
2961 else
2962 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
2963
2964 if (status != 0)
71858acb 2965 ret_val = -EIO;
71858acb 2966
a4b6fc6b 2967 data[i - ee->offset] = databyte;
71858acb
AG		 2968 }
2969
71858acb
AG		 2970 return ret_val;
2971}
2972
b9804972 2973static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2974 .get_settings = ixgbe_get_settings,
2975 .set_settings = ixgbe_set_settings,
2976 .get_drvinfo = ixgbe_get_drvinfo,
2977 .get_regs_len = ixgbe_get_regs_len,
2978 .get_regs = ixgbe_get_regs,
2979 .get_wol = ixgbe_get_wol,
e63d9762 2980 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2981 .nway_reset = ixgbe_nway_reset,
2982 .get_link = ethtool_op_get_link,
2983 .get_eeprom_len = ixgbe_get_eeprom_len,
2984 .get_eeprom = ixgbe_get_eeprom,
2fa5eef4 2985 .set_eeprom = ixgbe_set_eeprom,
9a799d71
AK		 2986 .get_ringparam = ixgbe_get_ringparam,
2987 .set_ringparam = ixgbe_set_ringparam,
2988 .get_pauseparam = ixgbe_get_pauseparam,
2989 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 2990 .get_msglevel = ixgbe_get_msglevel,
2991 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 2992 .self_test = ixgbe_diag_test,
9a799d71 2993 .get_strings = ixgbe_get_strings,
66e6961c 2994 .set_phys_id = ixgbe_set_phys_id,
b4617240 2995 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2996 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2997 .get_coalesce = ixgbe_get_coalesce,
2998 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 2999 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 3000 .set_rxnfc = ixgbe_set_rxnfc,
5348c9db 3001 .get_channels = ixgbe_get_channels,
4c696ca9 3002 .set_channels = ixgbe_set_channels,
e3aac889 3003 .get_ts_info = ixgbe_get_ts_info,
71858acb
AG		 3004 .get_module_info = ixgbe_get_module_info,
3005 .get_module_eeprom = ixgbe_get_module_eeprom,
9a799d71
AK		 3006};
3007
3008void ixgbe_set_ethtool_ops(struct net_device *netdev)
3009{
3010 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
3011}
Linux kernel - Deliverables
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