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ixgbe: fix checkpatch style of blank line after declaration
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0edd2bdf 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for ixgbe */
30
a6b7a407 31#include <linux/interrupt.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/module.h>
5a0e3ad6 34#include <linux/slab.h>
9a799d71
AK		 35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/ethtool.h>
38#include <linux/vmalloc.h>
f800326d 39#include <linux/highmem.h>
9a799d71
AK		 40#include <linux/uaccess.h>
41
42#include "ixgbe.h"
71858acb 43#include "ixgbe_phy.h"
9a799d71
AK		 44
45
46#define IXGBE_ALL_RAR_ENTRIES 16
47
29c3a050
AK		 48enum {NETDEV_STATS, IXGBE_STATS};
49
9a799d71
AK		 50struct ixgbe_stats {
51 char stat_string[ETH_GSTRING_LEN];
29c3a050 52 int type;
9a799d71
AK		 53 int sizeof_stat;
54 int stat_offset;
55};
56
29c3a050
AK		 57#define IXGBE_STAT(m) IXGBE_STATS, \
58 sizeof(((struct ixgbe_adapter *)0)->m), \
59 offsetof(struct ixgbe_adapter, m)
60#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \
62 offsetof(struct rtnl_link_stats64, m)
29c3a050 63
1bba2e81 64static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 73 {"lsc_int", IXGBE_STAT(lsc_int)},
74 {"tx_busy", IXGBE_STAT(tx_busy)},
75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
80 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 81 {"broadcast", IXGBE_STAT(stats.bprc)},
82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 83 {"collisions", IXGBE_NETDEV_STAT(collisions)},
84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
99 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 114#ifdef IXGBE_FCOE
115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
7b859ebc
AH		 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
6d45522c
YZ		 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
123#endif /* IXGBE_FCOE */
9a799d71
AK		 124};
125
9cc00b51
JF		 126/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
127 * we set the num_rx_queues to evaluate to num_tx_queues. This is
128 * used because we do not have a good way to get the max number of
129 * rx queues with CONFIG_RPS disabled.
130 */
131#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
132
133#define IXGBE_QUEUE_STATS_LEN ( \
134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
454d7c9b 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 136#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 137#define IXGBE_PB_STATS_LEN ( \
9cc00b51
JF		 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
142 / sizeof(u64))
2f90b865 143#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
e7cf745b
JK		 144 IXGBE_PB_STATS_LEN + \
145 IXGBE_QUEUE_STATS_LEN)
9a799d71 146
da4dd0f7
PWJ		 147static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
148 "Register test (offline)", "Eeprom test (offline)",
149 "Interrupt test (offline)", "Loopback test (offline)",
150 "Link test (on/offline)"
151};
152#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
153
9a799d71 154static int ixgbe_get_settings(struct net_device *netdev,
e7cf745b 155 struct ethtool_cmd *ecmd)
9a799d71
AK		 156{
157 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 158 struct ixgbe_hw *hw = &adapter->hw;
db018963 159 ixgbe_link_speed supported_link;
735441fb 160 u32 link_speed = 0;
fd0326f2 161 bool autoneg = false;
735441fb 162 bool link_up;
9a799d71 163
0f8fdab1
ET		 164 /* SFP type is needed for get_link_capabilities */
165 if (hw->phy.media_type & (ixgbe_media_type_fiber |
166 ixgbe_media_type_fiber_qsfp)) {
167 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
168 hw->phy.ops.identify_sfp(hw);
169 }
170
db018963 171 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
1b1c0a48 172
db018963
JK		 173 /* set the supported link speeds */
174 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
175 ecmd->supported |= SUPPORTED_10000baseT_Full;
176 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
177 ecmd->supported |= SUPPORTED_1000baseT_Full;
178 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
179 ecmd->supported |= SUPPORTED_100baseT_Full;
1b1c0a48 180
db018963
JK		 181 /* set the advertised speeds */
182 if (hw->phy.autoneg_advertised) {
183 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
184 ecmd->advertising |= ADVERTISED_100baseT_Full;
185 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
186 ecmd->advertising |= ADVERTISED_10000baseT_Full;
187 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
188 ecmd->advertising |= ADVERTISED_1000baseT_Full;
735441fb 189 } else {
db018963
JK		 190 /* default modes in case phy.autoneg_advertised isn't set */
191 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
192 ecmd->advertising |= ADVERTISED_10000baseT_Full;
193 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
194 ecmd->advertising |= ADVERTISED_1000baseT_Full;
195 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
196 ecmd->advertising |= ADVERTISED_100baseT_Full;
ed33ff66
ET		 197
198 if (hw->phy.multispeed_fiber && !autoneg) {
199 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
200 ecmd->advertising = ADVERTISED_10000baseT_Full;
201 }
735441fb 202 }
9a799d71 203
db018963
JK		 204 if (autoneg) {
205 ecmd->supported |= SUPPORTED_Autoneg;
206 ecmd->advertising |= ADVERTISED_Autoneg;
207 ecmd->autoneg = AUTONEG_ENABLE;
208 } else
209 ecmd->autoneg = AUTONEG_DISABLE;
210
211 ecmd->transceiver = XCVR_EXTERNAL;
212
213 /* Determine the remaining settings based on the PHY type. */
3b8626ba
PW		 214 switch (adapter->hw.phy.type) {
215 case ixgbe_phy_tn:
fe15e8e1 216 case ixgbe_phy_aq:
3b8626ba 217 case ixgbe_phy_cu_unknown:
db018963
JK		 218 ecmd->supported |= SUPPORTED_TP;
219 ecmd->advertising |= ADVERTISED_TP;
3b8626ba
PW		 220 ecmd->port = PORT_TP;
221 break;
222 case ixgbe_phy_qt:
db018963
JK		 223 ecmd->supported |= SUPPORTED_FIBRE;
224 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 225 ecmd->port = PORT_FIBRE;
226 break;
227 case ixgbe_phy_nl:
ea0a04df
DS		 228 case ixgbe_phy_sfp_passive_tyco:
229 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 230 case ixgbe_phy_sfp_ftl:
231 case ixgbe_phy_sfp_avago:
232 case ixgbe_phy_sfp_intel:
233 case ixgbe_phy_sfp_unknown:
3b8626ba 234 /* SFP+ devices, further checking needed */
db018963 235 switch (adapter->hw.phy.sfp_type) {
3b8626ba
PW		 236 case ixgbe_sfp_type_da_cu:
237 case ixgbe_sfp_type_da_cu_core0:
238 case ixgbe_sfp_type_da_cu_core1:
db018963
JK		 239 ecmd->supported |= SUPPORTED_FIBRE;
240 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 241 ecmd->port = PORT_DA;
242 break;
243 case ixgbe_sfp_type_sr:
244 case ixgbe_sfp_type_lr:
245 case ixgbe_sfp_type_srlr_core0:
246 case ixgbe_sfp_type_srlr_core1:
345be204
DS		 247 case ixgbe_sfp_type_1g_sx_core0:
248 case ixgbe_sfp_type_1g_sx_core1:
249 case ixgbe_sfp_type_1g_lx_core0:
250 case ixgbe_sfp_type_1g_lx_core1:
db018963
JK		 251 ecmd->supported |= SUPPORTED_FIBRE;
252 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 253 ecmd->port = PORT_FIBRE;
254 break;
255 case ixgbe_sfp_type_not_present:
db018963
JK		 256 ecmd->supported |= SUPPORTED_FIBRE;
257 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 258 ecmd->port = PORT_NONE;
259 break;
cb836a97
DS		 260 case ixgbe_sfp_type_1g_cu_core0:
261 case ixgbe_sfp_type_1g_cu_core1:
db018963
JK		 262 ecmd->supported |= SUPPORTED_TP;
263 ecmd->advertising |= ADVERTISED_TP;
cb836a97 264 ecmd->port = PORT_TP;
db018963 265 break;
3b8626ba
PW		 266 case ixgbe_sfp_type_unknown:
267 default:
db018963
JK		 268 ecmd->supported |= SUPPORTED_FIBRE;
269 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 270 ecmd->port = PORT_OTHER;
271 break;
272 }
273 break;
274 case ixgbe_phy_xaui:
db018963
JK		 275 ecmd->supported |= SUPPORTED_FIBRE;
276 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 277 ecmd->port = PORT_NONE;
278 break;
279 case ixgbe_phy_unknown:
280 case ixgbe_phy_generic:
281 case ixgbe_phy_sfp_unsupported:
282 default:
db018963
JK		 283 ecmd->supported |= SUPPORTED_FIBRE;
284 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 285 ecmd->port = PORT_OTHER;
286 break;
287 }
288
c44ade9e 289 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 290 if (link_up) {
1b1c0a48
AS		 291 switch (link_speed) {
292 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 293 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 294 break;
295 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 296 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 297 break;
298 case IXGBE_LINK_SPEED_100_FULL:
70739497 299 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 300 break;
301 default:
302 break;
303 }
9a799d71
AK		 304 ecmd->duplex = DUPLEX_FULL;
305 } else {
70739497 306 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 307 ecmd->duplex = -1;
308 }
309
9a799d71
AK		 310 return 0;
311}
312
313static int ixgbe_set_settings(struct net_device *netdev,
e7cf745b 314 struct ethtool_cmd *ecmd)
9a799d71
AK		 315{
316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 317 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 318 u32 advertised, old;
74766013 319 s32 err = 0;
9a799d71 320
74766013 321 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 322 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 323 /*
324 * this function does not support duplex forcing, but can
325 * limit the advertising of the adapter to the specified speed
326 */
abcc80d2
ET		 327 if (ecmd->advertising & ~ecmd->supported)
328 return -EINVAL;
329
ed33ff66
ET		 330 /* only allow one speed at a time if no autoneg */
331 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
332 if (ecmd->advertising ==
333 (ADVERTISED_10000baseT_Full |
334 ADVERTISED_1000baseT_Full))
335 return -EINVAL;
336 }
337
0befdb3e
JB		 338 old = hw->phy.autoneg_advertised;
339 advertised = 0;
340 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
341 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
342
343 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
344 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
345
2b642ca5
ET		 346 if (ecmd->advertising & ADVERTISED_100baseT_Full)
347 advertised |= IXGBE_LINK_SPEED_100_FULL;
348
0befdb3e 349 if (old == advertised)
74766013 350 return err;
0befdb3e 351 /* this sets the link speed and restarts auto-neg */
74766013 352 hw->mac.autotry_restart = true;
fd0326f2 353 err = hw->mac.ops.setup_link(hw, advertised, true);
0befdb3e 354 if (err) {
396e799c 355 e_info(probe, "setup link failed with code %d\n", err);
fd0326f2 356 hw->mac.ops.setup_link(hw, old, true);
0befdb3e 357 }
74766013
MC		 358 } else {
359 /* in this case we currently only support 10Gb/FULL */
25db0338 360 u32 speed = ethtool_cmd_speed(ecmd);
74766013 361 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 362 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 363 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 364 return -EINVAL;
9a799d71
AK		 365 }
366
74766013 367 return err;
9a799d71
AK		 368}
369
370static void ixgbe_get_pauseparam(struct net_device *netdev,
e7cf745b 371 struct ethtool_pauseparam *pause)
9a799d71
AK		 372{
373 struct ixgbe_adapter *adapter = netdev_priv(netdev);
374 struct ixgbe_hw *hw = &adapter->hw;
375
73d80953
DS		 376 if (ixgbe_device_supports_autoneg_fc(hw) &&
377 !hw->fc.disable_fc_autoneg)
71fd570b 378 pause->autoneg = 1;
73d80953
DS		 379 else
380 pause->autoneg = 0;
9a799d71 381
0ecc061d 382 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 383 pause->rx_pause = 1;
0ecc061d 384 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 385 pause->tx_pause = 1;
0ecc061d 386 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 387 pause->rx_pause = 1;
388 pause->tx_pause = 1;
389 }
390}
391
392static int ixgbe_set_pauseparam(struct net_device *netdev,
e7cf745b 393 struct ethtool_pauseparam *pause)
9a799d71
AK		 394{
395 struct ixgbe_adapter *adapter = netdev_priv(netdev);
396 struct ixgbe_hw *hw = &adapter->hw;
943561d3 397 struct ixgbe_fc_info fc = hw->fc;
9a799d71 398
943561d3
AD		 399 /* 82598 does no support link flow control with DCB enabled */
400 if ((hw->mac.type == ixgbe_mac_82598EB) &&
401 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
264857b8
PWJ		 402 return -EINVAL;
403
db2adc2d
JK		 404 /* some devices do not support autoneg of link flow control */
405 if ((pause->autoneg == AUTONEG_ENABLE) &&
73d80953 406 !ixgbe_device_supports_autoneg_fc(hw))
db2adc2d
JK		 407 return -EINVAL;
408
943561d3 409 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
71fd570b 410
1c4f0ef8 411 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 412 fc.requested_mode = ixgbe_fc_full;
9a799d71 413 else if (pause->rx_pause && !pause->tx_pause)
620fa036 414 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 415 else if (!pause->rx_pause && pause->tx_pause)
620fa036 416 fc.requested_mode = ixgbe_fc_tx_pause;
9c83b070 417 else
943561d3 418 fc.requested_mode = ixgbe_fc_none;
620fa036
MC		 419
420 /* if the thing changed then we'll update and use new autoneg */
421 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
422 hw->fc = fc;
423 if (netif_running(netdev))
424 ixgbe_reinit_locked(adapter);
425 else
426 ixgbe_reset(adapter);
427 }
9a799d71
AK		 428
429 return 0;
430}
431
9a799d71
AK		 432static u32 ixgbe_get_msglevel(struct net_device *netdev)
433{
434 struct ixgbe_adapter *adapter = netdev_priv(netdev);
435 return adapter->msg_enable;
436}
437
438static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
439{
440 struct ixgbe_adapter *adapter = netdev_priv(netdev);
441 adapter->msg_enable = data;
442}
443
444static int ixgbe_get_regs_len(struct net_device *netdev)
445{
51e409f1 446#define IXGBE_REGS_LEN 1139
9a799d71
AK		 447 return IXGBE_REGS_LEN * sizeof(u32);
448}
449
450#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
451
452static void ixgbe_get_regs(struct net_device *netdev,
e7cf745b 453 struct ethtool_regs *regs, void *p)
9a799d71
AK		 454{
455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
456 struct ixgbe_hw *hw = &adapter->hw;
457 u32 *regs_buff = p;
458 u8 i;
459
460 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
461
c4a56de8
ET		 462 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
463 hw->device_id;
9a799d71
AK		 464
465 /* General Registers */
466 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
467 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
468 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
469 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
470 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
471 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
472 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
473 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
474
475 /* NVM Register */
476 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
477 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
478 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
479 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
480 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
481 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
482 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
483 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
484 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
485 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
486
487 /* Interrupt */
98c00a1c
JB		 488 /* don't read EICR because it can clear interrupt causes, instead
489 * read EICS which is a shadow but doesn't clear EICR */
490 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 491 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
492 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
493 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
494 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
495 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
496 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
497 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
498 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
499 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 500 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 501 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
502
503 /* Flow Control */
504 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
505 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
506 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
507 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
508 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 509 for (i = 0; i < 8; i++) {
510 switch (hw->mac.type) {
511 case ixgbe_mac_82598EB:
512 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
513 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
514 break;
515 case ixgbe_mac_82599EB:
80bb25e3 516 case ixgbe_mac_X540:
bd508178
AD		 517 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
518 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
519 break;
520 default:
521 break;
522 }
523 }
9a799d71
AK		 524 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
525 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
526
527 /* Receive DMA */
528 for (i = 0; i < 64; i++)
529 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
530 for (i = 0; i < 64; i++)
531 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
532 for (i = 0; i < 64; i++)
533 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
534 for (i = 0; i < 64; i++)
535 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
536 for (i = 0; i < 64; i++)
537 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
538 for (i = 0; i < 64; i++)
539 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
540 for (i = 0; i < 16; i++)
541 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
542 for (i = 0; i < 16; i++)
543 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
544 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
545 for (i = 0; i < 8; i++)
546 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
547 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
548 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
549
550 /* Receive */
551 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
552 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
553 for (i = 0; i < 16; i++)
554 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
555 for (i = 0; i < 16; i++)
556 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 557 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 558 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
559 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
560 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
561 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
562 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
563 for (i = 0; i < 8; i++)
564 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
565 for (i = 0; i < 8; i++)
566 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
567 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
568
569 /* Transmit */
570 for (i = 0; i < 32; i++)
571 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
572 for (i = 0; i < 32; i++)
573 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
574 for (i = 0; i < 32; i++)
575 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
576 for (i = 0; i < 32; i++)
577 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
578 for (i = 0; i < 32; i++)
579 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
580 for (i = 0; i < 32; i++)
581 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
582 for (i = 0; i < 32; i++)
583 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
584 for (i = 0; i < 32; i++)
585 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
586 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
587 for (i = 0; i < 16; i++)
588 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
589 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
590 for (i = 0; i < 8; i++)
591 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
592 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
593
594 /* Wake Up */
595 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
596 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
597 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
598 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
599 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
600 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
601 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
602 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 603 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 604
673ac604 605 /* DCB */
51e409f1
LP		 606 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
607 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
608
609 switch (hw->mac.type) {
610 case ixgbe_mac_82598EB:
611 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
612 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
613 for (i = 0; i < 8; i++)
614 regs_buff[833 + i] =
615 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
616 for (i = 0; i < 8; i++)
617 regs_buff[841 + i] =
618 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
619 for (i = 0; i < 8; i++)
620 regs_buff[849 + i] =
621 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
622 for (i = 0; i < 8; i++)
623 regs_buff[857 + i] =
624 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
625 break;
626 case ixgbe_mac_82599EB:
627 case ixgbe_mac_X540:
628 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
629 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
630 for (i = 0; i < 8; i++)
631 regs_buff[833 + i] =
632 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
633 for (i = 0; i < 8; i++)
634 regs_buff[841 + i] =
635 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
636 for (i = 0; i < 8; i++)
637 regs_buff[849 + i] =
638 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
639 for (i = 0; i < 8; i++)
640 regs_buff[857 + i] =
641 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
642 break;
643 default:
644 break;
645 }
646
9a799d71 647 for (i = 0; i < 8; i++)
51e409f1
LP		 648 regs_buff[865 + i] =
649 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
9a799d71 650 for (i = 0; i < 8; i++)
51e409f1
LP		 651 regs_buff[873 + i] =
652 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
9a799d71
AK		 653
654 /* Statistics */
655 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
656 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
657 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
658 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
659 for (i = 0; i < 8; i++)
660 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
661 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
662 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
663 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
664 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
665 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
666 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
667 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
668 for (i = 0; i < 8; i++)
669 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
670 for (i = 0; i < 8; i++)
671 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
672 for (i = 0; i < 8; i++)
673 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
674 for (i = 0; i < 8; i++)
675 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
676 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
677 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
678 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
679 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
680 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
681 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
682 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
683 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
684 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
685 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
686 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
687 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
688 for (i = 0; i < 8; i++)
689 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
690 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
691 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
692 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
693 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
694 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
695 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
696 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
697 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
698 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
699 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
700 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
701 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
702 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
703 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
704 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
705 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
706 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
707 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
708 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
709 for (i = 0; i < 16; i++)
710 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
711 for (i = 0; i < 16; i++)
712 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
713 for (i = 0; i < 16; i++)
714 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
715 for (i = 0; i < 16; i++)
716 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
717
718 /* MAC */
719 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
720 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
721 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
722 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
723 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
724 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
725 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
726 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
727 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
728 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
729 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
730 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
731 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
732 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
733 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
734 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
735 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
736 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
737 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
738 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
739 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
740 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
741 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
742 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
743 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
744 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
745 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
746 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
747 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
748 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
749 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
750 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
751 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
752
753 /* Diagnostic */
754 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
755 for (i = 0; i < 8; i++)
98c00a1c 756 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 757 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 758 for (i = 0; i < 4; i++)
759 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 760 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
761 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
762 for (i = 0; i < 8; i++)
98c00a1c 763 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 764 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 765 for (i = 0; i < 4; i++)
766 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 767 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
768 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
769 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
770 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
771 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
772 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
773 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
774 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
775 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
776 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
777 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
778 for (i = 0; i < 8; i++)
98c00a1c 779 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 780 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
781 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
782 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
783 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
784 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
785 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
786 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
787 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
788 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
217995ec
ET		 789
790 /* 82599 X540 specific registers */
791 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
51e409f1
LP		 792
793 /* 82599 X540 specific DCB registers */
794 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
795 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
796 for (i = 0; i < 4; i++)
797 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
798 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
799 /* same as RTTQCNRM */
800 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
801 /* same as RTTQCNRR */
802
803 /* X540 specific DCB registers */
804 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
805 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
9a799d71
AK		 806}
807
808static int ixgbe_get_eeprom_len(struct net_device *netdev)
809{
810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
811 return adapter->hw.eeprom.word_size * 2;
812}
813
814static int ixgbe_get_eeprom(struct net_device *netdev,
e7cf745b 815 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 816{
817 struct ixgbe_adapter *adapter = netdev_priv(netdev);
818 struct ixgbe_hw *hw = &adapter->hw;
819 u16 *eeprom_buff;
820 int first_word, last_word, eeprom_len;
821 int ret_val = 0;
822 u16 i;
823
824 if (eeprom->len == 0)
825 return -EINVAL;
826
827 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
828
829 first_word = eeprom->offset >> 1;
830 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
831 eeprom_len = last_word - first_word + 1;
832
833 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
834 if (!eeprom_buff)
835 return -ENOMEM;
836
68c7005d
ET		 837 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
838 eeprom_buff);
9a799d71
AK		 839
840 /* Device's eeprom is always little-endian, word addressable */
841 for (i = 0; i < eeprom_len; i++)
842 le16_to_cpus(&eeprom_buff[i]);
843
844 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
845 kfree(eeprom_buff);
846
847 return ret_val;
848}
849
2fa5eef4
ET		 850static int ixgbe_set_eeprom(struct net_device *netdev,
851 struct ethtool_eeprom *eeprom, u8 *bytes)
852{
853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
854 struct ixgbe_hw *hw = &adapter->hw;
855 u16 *eeprom_buff;
856 void *ptr;
857 int max_len, first_word, last_word, ret_val = 0;
858 u16 i;
859
860 if (eeprom->len == 0)
861 return -EINVAL;
862
863 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
864 return -EINVAL;
865
866 max_len = hw->eeprom.word_size * 2;
867
868 first_word = eeprom->offset >> 1;
869 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
870 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
871 if (!eeprom_buff)
872 return -ENOMEM;
873
874 ptr = eeprom_buff;
875
876 if (eeprom->offset & 1) {
877 /*
878 * need read/modify/write of first changed EEPROM word
879 * only the second byte of the word is being modified
880 */
881 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
882 if (ret_val)
883 goto err;
884
885 ptr++;
886 }
887 if ((eeprom->offset + eeprom->len) & 1) {
888 /*
889 * need read/modify/write of last changed EEPROM word
890 * only the first byte of the word is being modified
891 */
892 ret_val = hw->eeprom.ops.read(hw, last_word,
893 &eeprom_buff[last_word - first_word]);
894 if (ret_val)
895 goto err;
896 }
897
898 /* Device's eeprom is always little-endian, word addressable */
899 for (i = 0; i < last_word - first_word + 1; i++)
900 le16_to_cpus(&eeprom_buff[i]);
901
902 memcpy(ptr, bytes, eeprom->len);
903
904 for (i = 0; i < last_word - first_word + 1; i++)
905 cpu_to_le16s(&eeprom_buff[i]);
906
907 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
908 last_word - first_word + 1,
909 eeprom_buff);
910
911 /* Update the checksum */
912 if (ret_val == 0)
913 hw->eeprom.ops.update_checksum(hw);
914
915err:
916 kfree(eeprom_buff);
917 return ret_val;
918}
919
9a799d71 920static void ixgbe_get_drvinfo(struct net_device *netdev,
e7cf745b 921 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 922{
923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
15e5209f 924 u32 nvm_track_id;
9a799d71 925
612a94d6
RJ		 926 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
927 strlcpy(drvinfo->version, ixgbe_driver_version,
928 sizeof(drvinfo->version));
083fc582 929
15e5209f
ET		 930 nvm_track_id = (adapter->eeprom_verh << 16) |
931 adapter->eeprom_verl;
612a94d6 932 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
15e5209f 933 nvm_track_id);
083fc582 934
612a94d6
RJ		 935 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
936 sizeof(drvinfo->bus_info));
9a799d71 937 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 938 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 939 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
940}
941
942static void ixgbe_get_ringparam(struct net_device *netdev,
e7cf745b 943 struct ethtool_ringparam *ring)
9a799d71
AK		 944{
945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 946 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
947 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 948
949 ring->rx_max_pending = IXGBE_MAX_RXD;
950 ring->tx_max_pending = IXGBE_MAX_TXD;
9a799d71
AK		 951 ring->rx_pending = rx_ring->count;
952 ring->tx_pending = tx_ring->count;
9a799d71
AK		 953}
954
955static int ixgbe_set_ringparam(struct net_device *netdev,
e7cf745b 956 struct ethtool_ringparam *ring)
9a799d71
AK		 957{
958 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1f4702aa 959 struct ixgbe_ring *temp_ring;
759884b4 960 int i, err = 0;
c431f97e 961 u32 new_rx_count, new_tx_count;
9a799d71
AK		 962
963 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
964 return -EINVAL;
965
1f4702aa
AD		 966 new_tx_count = clamp_t(u32, ring->tx_pending,
967 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
9a799d71
AK		 968 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
969
1f4702aa
AD		 970 new_rx_count = clamp_t(u32, ring->rx_pending,
971 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
972 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
973
974 if ((new_tx_count == adapter->tx_ring_count) &&
975 (new_rx_count == adapter->rx_ring_count)) {
9a799d71
AK		 976 /* nothing to do */
977 return 0;
978 }
979
d4f80882 980 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 981 usleep_range(1000, 2000);
d4f80882 982
759884b4
AD		 983 if (!netif_running(adapter->netdev)) {
984 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 985 adapter->tx_ring[i]->count = new_tx_count;
759884b4 986 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 987 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 988 adapter->tx_ring_count = new_tx_count;
989 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 990 goto clear_reset;
759884b4
AD		 991 }
992
1f4702aa
AD		 993 /* allocate temporary buffer to store rings in */
994 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
995 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
996
997 if (!temp_ring) {
f9ed8854 998 err = -ENOMEM;
4a0b9ca0 999 goto clear_reset;
f9ed8854
MC		 1000 }
1001
1f4702aa
AD		 1002 ixgbe_down(adapter);
1003
1004 /*
1005 * Setup new Tx resources and free the old Tx resources in that order.
1006 * We can then assign the new resources to the rings via a memcpy.
1007 * The advantage to this approach is that we are guaranteed to still
1008 * have resources even in the case of an allocation failure.
1009 */
f9ed8854 1010 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 1011 for (i = 0; i < adapter->num_tx_queues; i++) {
1f4702aa 1012 memcpy(&temp_ring[i], adapter->tx_ring[i],
4a0b9ca0 1013 sizeof(struct ixgbe_ring));
1f4702aa
AD		 1014
1015 temp_ring[i].count = new_tx_count;
1016 err = ixgbe_setup_tx_resources(&temp_ring[i]);
9a799d71 1017 if (err) {
c431f97e
JB		 1018 while (i) {
1019 i--;
1f4702aa 1020 ixgbe_free_tx_resources(&temp_ring[i]);
c431f97e 1021 }
1f4702aa 1022 goto err_setup;
9a799d71 1023 }
9a799d71 1024 }
9a799d71 1025
1f4702aa
AD		 1026 for (i = 0; i < adapter->num_tx_queues; i++) {
1027 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1028
1029 memcpy(adapter->tx_ring[i], &temp_ring[i],
1030 sizeof(struct ixgbe_ring));
1031 }
1032
1033 adapter->tx_ring_count = new_tx_count;
d3fa4721 1034 }
9a799d71 1035
1f4702aa 1036 /* Repeat the process for the Rx rings if needed */
f9ed8854 1037 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 1038 for (i = 0; i < adapter->num_rx_queues; i++) {
1f4702aa 1039 memcpy(&temp_ring[i], adapter->rx_ring[i],
4a0b9ca0 1040 sizeof(struct ixgbe_ring));
1f4702aa
AD		 1041
1042 temp_ring[i].count = new_rx_count;
1043 err = ixgbe_setup_rx_resources(&temp_ring[i]);
9a799d71 1044 if (err) {
c431f97e
JB		 1045 while (i) {
1046 i--;
1f4702aa 1047 ixgbe_free_rx_resources(&temp_ring[i]);
c431f97e 1048 }
9a799d71
AK		 1049 goto err_setup;
1050 }
1f4702aa 1051
9a799d71 1052 }
f9ed8854 1053
1f4702aa
AD		 1054 for (i = 0; i < adapter->num_rx_queues; i++) {
1055 ixgbe_free_rx_resources(adapter->rx_ring[i]);
f9ed8854 1056
1f4702aa
AD		 1057 memcpy(adapter->rx_ring[i], &temp_ring[i],
1058 sizeof(struct ixgbe_ring));
f9ed8854
MC		 1059 }
1060
1f4702aa 1061 adapter->rx_ring_count = new_rx_count;
759884b4 1062 }
4a0b9ca0 1063
f9ed8854 1064err_setup:
1f4702aa
AD		 1065 ixgbe_up(adapter);
1066 vfree(temp_ring);
4a0b9ca0 1067clear_reset:
d4f80882 1068 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1069 return err;
1070}
1071
b9f2c044 1072static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1073{
b9f2c044 1074 switch (sset) {
da4dd0f7
PWJ		 1075 case ETH_SS_TEST:
1076 return IXGBE_TEST_LEN;
b9f2c044
JG		 1077 case ETH_SS_STATS:
1078 return IXGBE_STATS_LEN;
1079 default:
1080 return -EOPNOTSUPP;
1081 }
9a799d71
AK		 1082}
1083
1084static void ixgbe_get_ethtool_stats(struct net_device *netdev,
e7cf745b 1085 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1086{
1087 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1088 struct rtnl_link_stats64 temp;
1089 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1090 unsigned int start;
1091 struct ixgbe_ring *ring;
1092 int i, j;
29c3a050 1093 char *p = NULL;
9a799d71
AK		 1094
1095 ixgbe_update_stats(adapter);
28172739 1096 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1097 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1098 switch (ixgbe_gstrings_stats[i].type) {
1099 case NETDEV_STATS:
28172739 1100 p = (char *) net_stats +
29c3a050
AK		 1101 ixgbe_gstrings_stats[i].stat_offset;
1102 break;
1103 case IXGBE_STATS:
1104 p = (char *) adapter +
1105 ixgbe_gstrings_stats[i].stat_offset;
1106 break;
f752be9c
JH		 1107 default:
1108 data[i] = 0;
1109 continue;
29c3a050
AK		 1110 }
1111
9a799d71 1112 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
e7cf745b 1113 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71 1114 }
bd8a1b12 1115 for (j = 0; j < netdev->num_tx_queues; j++) {
de1036b1 1116 ring = adapter->tx_ring[j];
9cc00b51
JF		 1117 if (!ring) {
1118 data[i] = 0;
1119 data[i+1] = 0;
1120 i += 2;
b4640030 1121#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1122 data[i] = 0;
1123 data[i+1] = 0;
1124 data[i+2] = 0;
1125 i += 3;
1126#endif
9cc00b51
JF		 1127 continue;
1128 }
1129
de1036b1 1130 do {
57a7744e 1131 start = u64_stats_fetch_begin_irq(&ring->syncp);
de1036b1
ED		 1132 data[i] = ring->stats.packets;
1133 data[i+1] = ring->stats.bytes;
57a7744e 1134 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
de1036b1 1135 i += 2;
b4640030 1136#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1137 data[i] = ring->stats.yields;
1138 data[i+1] = ring->stats.misses;
1139 data[i+2] = ring->stats.cleaned;
1140 i += 3;
1141#endif
9a799d71 1142 }
9cc00b51 1143 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1144 ring = adapter->rx_ring[j];
9cc00b51
JF		 1145 if (!ring) {
1146 data[i] = 0;
1147 data[i+1] = 0;
1148 i += 2;
b4640030 1149#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1150 data[i] = 0;
1151 data[i+1] = 0;
1152 data[i+2] = 0;
1153 i += 3;
1154#endif
9cc00b51
JF		 1155 continue;
1156 }
1157
de1036b1 1158 do {
57a7744e 1159 start = u64_stats_fetch_begin_irq(&ring->syncp);
de1036b1
ED		 1160 data[i] = ring->stats.packets;
1161 data[i+1] = ring->stats.bytes;
57a7744e 1162 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
de1036b1 1163 i += 2;
b4640030 1164#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1165 data[i] = ring->stats.yields;
1166 data[i+1] = ring->stats.misses;
1167 data[i+2] = ring->stats.cleaned;
1168 i += 3;
1169#endif
9a799d71 1170 }
9cc00b51
JF		 1171
1172 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1173 data[i++] = adapter->stats.pxontxc[j];
1174 data[i++] = adapter->stats.pxofftxc[j];
1175 }
1176 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1177 data[i++] = adapter->stats.pxonrxc[j];
1178 data[i++] = adapter->stats.pxoffrxc[j];
2f90b865 1179 }
9a799d71
AK		 1180}
1181
1182static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
e7cf745b 1183 u8 *data)
9a799d71 1184{
c44ade9e 1185 char *p = (char *)data;
9a799d71
AK		 1186 int i;
1187
1188 switch (stringset) {
da4dd0f7 1189 case ETH_SS_TEST:
d2c47b62
JH		 1190 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1191 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1192 data += ETH_GSTRING_LEN;
1193 }
da4dd0f7 1194 break;
9a799d71
AK		 1195 case ETH_SS_STATS:
1196 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1197 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1198 ETH_GSTRING_LEN);
1199 p += ETH_GSTRING_LEN;
1200 }
9cc00b51 1201 for (i = 0; i < netdev->num_tx_queues; i++) {
9a799d71
AK		 1202 sprintf(p, "tx_queue_%u_packets", i);
1203 p += ETH_GSTRING_LEN;
1204 sprintf(p, "tx_queue_%u_bytes", i);
1205 p += ETH_GSTRING_LEN;
b4640030
JK		 1206#ifdef BP_EXTENDED_STATS
1207 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
7e15b90f 1208 p += ETH_GSTRING_LEN;
b4640030 1209 sprintf(p, "tx_queue_%u_bp_misses", i);
7e15b90f 1210 p += ETH_GSTRING_LEN;
b4640030 1211 sprintf(p, "tx_queue_%u_bp_cleaned", i);
7e15b90f 1212 p += ETH_GSTRING_LEN;
b4640030 1213#endif /* BP_EXTENDED_STATS */
9a799d71 1214 }
9cc00b51 1215 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
9a799d71
AK		 1216 sprintf(p, "rx_queue_%u_packets", i);
1217 p += ETH_GSTRING_LEN;
1218 sprintf(p, "rx_queue_%u_bytes", i);
1219 p += ETH_GSTRING_LEN;
b4640030
JK		 1220#ifdef BP_EXTENDED_STATS
1221 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
7e15b90f 1222 p += ETH_GSTRING_LEN;
b4640030 1223 sprintf(p, "rx_queue_%u_bp_misses", i);
7e15b90f 1224 p += ETH_GSTRING_LEN;
b4640030 1225 sprintf(p, "rx_queue_%u_bp_cleaned", i);
7e15b90f 1226 p += ETH_GSTRING_LEN;
b4640030 1227#endif /* BP_EXTENDED_STATS */
9a799d71 1228 }
9cc00b51
JF		 1229 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1230 sprintf(p, "tx_pb_%u_pxon", i);
1231 p += ETH_GSTRING_LEN;
1232 sprintf(p, "tx_pb_%u_pxoff", i);
1233 p += ETH_GSTRING_LEN;
1234 }
1235 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1236 sprintf(p, "rx_pb_%u_pxon", i);
1237 p += ETH_GSTRING_LEN;
1238 sprintf(p, "rx_pb_%u_pxoff", i);
1239 p += ETH_GSTRING_LEN;
2f90b865 1240 }
b4617240 1241 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1242 break;
1243 }
1244}
1245
da4dd0f7
PWJ		 1246static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1247{
1248 struct ixgbe_hw *hw = &adapter->hw;
1249 bool link_up;
1250 u32 link_speed = 0;
0edd2bdf
MR		 1251
1252 if (ixgbe_removed(hw->hw_addr)) {
1253 *data = 1;
1254 return 1;
1255 }
da4dd0f7
PWJ		 1256 *data = 0;
1257
1258 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1259 if (link_up)
1260 return *data;
1261 else
1262 *data = 1;
1263 return *data;
1264}
1265
1266/* ethtool register test data */
1267struct ixgbe_reg_test {
1268 u16 reg;
1269 u8 array_len;
1270 u8 test_type;
1271 u32 mask;
1272 u32 write;
1273};
1274
1275/* In the hardware, registers are laid out either singly, in arrays
1276 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1277 * most tests take place on arrays or single registers (handled
1278 * as a single-element array) and special-case the tables.
1279 * Table tests are always pattern tests.
1280 *
1281 * We also make provision for some required setup steps by specifying
1282 * registers to be written without any read-back testing.
1283 */
1284
1285#define PATTERN_TEST 1
1286#define SET_READ_TEST 2
1287#define WRITE_NO_TEST 3
1288#define TABLE32_TEST 4
1289#define TABLE64_TEST_LO 5
1290#define TABLE64_TEST_HI 6
1291
1292/* default 82599 register test */
66744500 1293static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1294 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1295 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1296 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1297 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1298 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1299 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1300 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1301 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1302 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1303 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1304 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1305 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1306 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1307 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1308 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1309 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1310 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1311 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1312 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1313 { 0, 0, 0, 0 }
1314};
1315
1316/* default 82598 register test */
66744500 1317static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1318 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1319 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1320 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1321 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1322 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1323 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1324 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1325 /* Enable all four RX queues before testing. */
1326 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1327 /* RDH is read-only for 82598, only test RDT. */
1328 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1329 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1330 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1331 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1332 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1333 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1334 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1335 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1336 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1337 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1338 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1339 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1340 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1341 { 0, 0, 0, 0 }
1342};
1343
95a46011
ET		 1344static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1345 u32 mask, u32 write)
1346{
1347 u32 pat, val, before;
1348 static const u32 test_pattern[] = {
1349 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1350
b0483c8f
MR		 1351 if (ixgbe_removed(adapter->hw.hw_addr)) {
1352 *data = 1;
1353 return 1;
1354 }
95a46011 1355 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
49bde319
MR		 1356 before = ixgbe_read_reg(&adapter->hw, reg);
1357 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1358 val = ixgbe_read_reg(&adapter->hw, reg);
95a46011
ET		 1359 if (val != (test_pattern[pat] & write & mask)) {
1360 e_err(drv, "pattern test reg %04X failed: got "
1361 "0x%08X expected 0x%08X\n",
1362 reg, val, (test_pattern[pat] & write & mask));
1363 *data = reg;
49bde319
MR		 1364 ixgbe_write_reg(&adapter->hw, reg, before);
1365 return true;
95a46011 1366 }
49bde319 1367 ixgbe_write_reg(&adapter->hw, reg, before);
95a46011 1368 }
49bde319 1369 return false;
da4dd0f7
PWJ		 1370}
1371
95a46011
ET		 1372static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1373 u32 mask, u32 write)
1374{
1375 u32 val, before;
49bde319 1376
b0483c8f
MR		 1377 if (ixgbe_removed(adapter->hw.hw_addr)) {
1378 *data = 1;
1379 return 1;
1380 }
49bde319
MR		 1381 before = ixgbe_read_reg(&adapter->hw, reg);
1382 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1383 val = ixgbe_read_reg(&adapter->hw, reg);
95a46011
ET		 1384 if ((write & mask) != (val & mask)) {
1385 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1386 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1387 *data = reg;
49bde319
MR		 1388 ixgbe_write_reg(&adapter->hw, reg, before);
1389 return true;
95a46011 1390 }
49bde319
MR		 1391 ixgbe_write_reg(&adapter->hw, reg, before);
1392 return false;
da4dd0f7
PWJ		 1393}
1394
1395static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1396{
66744500 1397 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1398 u32 value, before, after;
1399 u32 i, toggle;
1400
b0483c8f
MR		 1401 if (ixgbe_removed(adapter->hw.hw_addr)) {
1402 e_err(drv, "Adapter removed - register test blocked\n");
1403 *data = 1;
1404 return 1;
1405 }
bd508178
AD		 1406 switch (adapter->hw.mac.type) {
1407 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1408 toggle = 0x7FFFF3FF;
1409 test = reg_test_82598;
bd508178
AD		 1410 break;
1411 case ixgbe_mac_82599EB:
b93a2226 1412 case ixgbe_mac_X540:
bd508178
AD		 1413 toggle = 0x7FFFF30F;
1414 test = reg_test_82599;
1415 break;
1416 default:
1417 *data = 1;
1418 return 1;
1419 break;
da4dd0f7
PWJ		 1420 }
1421
1422 /*
1423 * Because the status register is such a special case,
1424 * we handle it separately from the rest of the register
1425 * tests. Some bits are read-only, some toggle, and some
1426 * are writeable on newer MACs.
1427 */
49bde319
MR		 1428 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1429 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1430 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1431 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
da4dd0f7 1432 if (value != after) {
396e799c
ET		 1433 e_err(drv, "failed STATUS register test got: 0x%08X "
1434 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1435 *data = 1;
1436 return 1;
1437 }
1438 /* restore previous status */
49bde319 1439 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
da4dd0f7
PWJ		 1440
1441 /*
1442 * Perform the remainder of the register test, looping through
1443 * the test table until we either fail or reach the null entry.
1444 */
1445 while (test->reg) {
1446 for (i = 0; i < test->array_len; i++) {
49bde319
MR		 1447 bool b = false;
1448
da4dd0f7
PWJ		 1449 switch (test->test_type) {
1450 case PATTERN_TEST:
49bde319
MR		 1451 b = reg_pattern_test(adapter, data,
1452 test->reg + (i * 0x40),
1453 test->mask,
1454 test->write);
da4dd0f7
PWJ		 1455 break;
1456 case SET_READ_TEST:
49bde319
MR		 1457 b = reg_set_and_check(adapter, data,
1458 test->reg + (i * 0x40),
1459 test->mask,
1460 test->write);
da4dd0f7
PWJ		 1461 break;
1462 case WRITE_NO_TEST:
49bde319
MR		 1463 ixgbe_write_reg(&adapter->hw,
1464 test->reg + (i * 0x40),
1465 test->write);
da4dd0f7
PWJ		 1466 break;
1467 case TABLE32_TEST:
49bde319
MR		 1468 b = reg_pattern_test(adapter, data,
1469 test->reg + (i * 4),
1470 test->mask,
1471 test->write);
da4dd0f7
PWJ		 1472 break;
1473 case TABLE64_TEST_LO:
49bde319
MR		 1474 b = reg_pattern_test(adapter, data,
1475 test->reg + (i * 8),
1476 test->mask,
1477 test->write);
da4dd0f7
PWJ		 1478 break;
1479 case TABLE64_TEST_HI:
49bde319
MR		 1480 b = reg_pattern_test(adapter, data,
1481 (test->reg + 4) + (i * 8),
1482 test->mask,
1483 test->write);
da4dd0f7
PWJ		 1484 break;
1485 }
49bde319
MR		 1486 if (b)
1487 return 1;
da4dd0f7
PWJ		 1488 }
1489 test++;
1490 }
1491
1492 *data = 0;
1493 return 0;
1494}
1495
1496static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1497{
1498 struct ixgbe_hw *hw = &adapter->hw;
1499 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1500 *data = 1;
1501 else
1502 *data = 0;
1503 return *data;
1504}
1505
1506static irqreturn_t ixgbe_test_intr(int irq, void *data)
1507{
1508 struct net_device *netdev = (struct net_device *) data;
1509 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1510
1511 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1512
1513 return IRQ_HANDLED;
1514}
1515
1516static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1517{
1518 struct net_device *netdev = adapter->netdev;
1519 u32 mask, i = 0, shared_int = true;
1520 u32 irq = adapter->pdev->irq;
1521
1522 *data = 0;
1523
1524 /* Hook up test interrupt handler just for this test */
1525 if (adapter->msix_entries) {
1526 /* NOTE: we don't test MSI-X interrupts here, yet */
1527 return 0;
1528 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1529 shared_int = false;
a0607fd3 1530 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1531 netdev)) {
1532 *data = 1;
1533 return -1;
1534 }
a0607fd3 1535 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
e7cf745b 1536 netdev->name, netdev)) {
da4dd0f7 1537 shared_int = false;
a0607fd3 1538 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
e7cf745b 1539 netdev->name, netdev)) {
da4dd0f7
PWJ		 1540 *data = 1;
1541 return -1;
1542 }
396e799c
ET		 1543 e_info(hw, "testing %s interrupt\n", shared_int ?
1544 "shared" : "unshared");
da4dd0f7
PWJ		 1545
1546 /* Disable all the interrupts */
1547 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1548 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1549 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1550
1551 /* Test each interrupt */
1552 for (; i < 10; i++) {
1553 /* Interrupt to test */
1554 mask = 1 << i;
1555
1556 if (!shared_int) {
1557 /*
1558 * Disable the interrupts to be reported in
1559 * the cause register and then force the same
1560 * interrupt and see if one gets posted. If
1561 * an interrupt was posted to the bus, the
1562 * test failed.
1563 */
1564 adapter->test_icr = 0;
1565 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
e7cf745b 1566 ~mask & 0x00007FFF);
da4dd0f7 1567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
e7cf745b 1568 ~mask & 0x00007FFF);
945a5151 1569 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1570 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1571
1572 if (adapter->test_icr & mask) {
1573 *data = 3;
1574 break;
1575 }
1576 }
1577
1578 /*
1579 * Enable the interrupt to be reported in the cause
1580 * register and then force the same interrupt and see
1581 * if one gets posted. If an interrupt was not posted
1582 * to the bus, the test failed.
1583 */
1584 adapter->test_icr = 0;
1585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1587 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1588 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1589
1590 if (!(adapter->test_icr &mask)) {
1591 *data = 4;
1592 break;
1593 }
1594
1595 if (!shared_int) {
1596 /*
1597 * Disable the other interrupts to be reported in
1598 * the cause register and then force the other
1599 * interrupts and see if any get posted. If
1600 * an interrupt was posted to the bus, the
1601 * test failed.
1602 */
1603 adapter->test_icr = 0;
1604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
e7cf745b 1605 ~mask & 0x00007FFF);
da4dd0f7 1606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
e7cf745b 1607 ~mask & 0x00007FFF);
945a5151 1608 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1609 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1610
1611 if (adapter->test_icr) {
1612 *data = 5;
1613 break;
1614 }
1615 }
1616 }
1617
1618 /* Disable all the interrupts */
1619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1620 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1621 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1622
1623 /* Unhook test interrupt handler */
1624 free_irq(irq, netdev);
1625
1626 return *data;
1627}
1628
1629static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1630{
1631 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1632 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1633 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1634 u32 reg_ctl;
da4dd0f7
PWJ		 1635
1636 /* shut down the DMA engines now so they can be reinitialized later */
1637
1638 /* first Rx */
1639 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1640 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1641 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1642 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1643
1644 /* now Tx */
84418e3b 1645 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1646 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1647 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1648
bd508178
AD		 1649 switch (hw->mac.type) {
1650 case ixgbe_mac_82599EB:
b93a2226 1651 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1652 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1653 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1654 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1655 break;
1656 default:
1657 break;
da4dd0f7
PWJ		 1658 }
1659
1660 ixgbe_reset(adapter);
1661
b6ec895e
AD		 1662 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1663 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1664}
1665
1666static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1667{
1668 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1669 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1670 u32 rctl, reg_data;
84418e3b
AD		 1671 int ret_val;
1672 int err;
da4dd0f7
PWJ		 1673
1674 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1675 tx_ring->count = IXGBE_DEFAULT_TXD;
1676 tx_ring->queue_index = 0;
b6ec895e 1677 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1678 tx_ring->netdev = adapter->netdev;
84418e3b 1679 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
da4dd0f7 1680
b6ec895e 1681 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1682 if (err)
1683 return 1;
da4dd0f7 1684
bd508178
AD		 1685 switch (adapter->hw.mac.type) {
1686 case ixgbe_mac_82599EB:
b93a2226 1687 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1688 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1689 reg_data |= IXGBE_DMATXCTL_TE;
1690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1691 break;
1692 default:
1693 break;
da4dd0f7 1694 }
f4ec443b 1695
84418e3b 1696 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1697
1698 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1699 rx_ring->count = IXGBE_DEFAULT_RXD;
1700 rx_ring->queue_index = 0;
b6ec895e 1701 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1702 rx_ring->netdev = adapter->netdev;
84418e3b 1703 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
84418e3b 1704
b6ec895e 1705 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1706 if (err) {
da4dd0f7
PWJ		 1707 ret_val = 4;
1708 goto err_nomem;
1709 }
1710
da4dd0f7
PWJ		 1711 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1712 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1713
84418e3b 1714 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1715
1716 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1717 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1718
da4dd0f7
PWJ		 1719 return 0;
1720
1721err_nomem:
1722 ixgbe_free_desc_rings(adapter);
1723 return ret_val;
1724}
1725
1726static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1727{
1728 struct ixgbe_hw *hw = &adapter->hw;
1729 u32 reg_data;
1730
e7fd9253 1731
84418e3b 1732 /* Setup MAC loopback */
26b4742b 1733 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
da4dd0f7 1734 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1735 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1736
35c7f8a1 1737 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1738 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1739 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1740
26b4742b
ET		 1741 /* X540 needs to set the MACC.FLU bit to force link up */
1742 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1743 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1744 reg_data |= IXGBE_MACC_FLU;
1745 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1746 } else {
1747 if (hw->mac.orig_autoc) {
1748 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1749 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1750 } else {
1751 return 10;
1752 }
1753 }
35c7f8a1 1754 IXGBE_WRITE_FLUSH(hw);
032b4325 1755 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1756
1757 /* Disable Atlas Tx lanes; re-enabled in reset path */
1758 if (hw->mac.type == ixgbe_mac_82598EB) {
1759 u8 atlas;
1760
1761 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1762 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1763 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1764
1765 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1766 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1767 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1768
1769 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1770 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1771 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1772
1773 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1774 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1775 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1776 }
1777
1778 return 0;
1779}
1780
1781static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1782{
1783 u32 reg_data;
1784
1785 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1786 reg_data &= ~IXGBE_HLREG0_LPBK;
1787 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1788}
1789
1790static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
3832b26e 1791 unsigned int frame_size)
da4dd0f7
PWJ		 1792{
1793 memset(skb->data, 0xFF, frame_size);
3832b26e
AD		 1794 frame_size >>= 1;
1795 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1796 memset(&skb->data[frame_size + 10], 0xBE, 1);
1797 memset(&skb->data[frame_size + 12], 0xAF, 1);
da4dd0f7
PWJ		 1798}
1799
3832b26e
AD		 1800static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1801 unsigned int frame_size)
da4dd0f7 1802{
3832b26e
AD		 1803 unsigned char *data;
1804 bool match = true;
1805
1806 frame_size >>= 1;
1807
f800326d 1808 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
3832b26e
AD		 1809
1810 if (data[3] != 0xFF ||
1811 data[frame_size + 10] != 0xBE ||
1812 data[frame_size + 12] != 0xAF)
1813 match = false;
1814
f800326d
AD		 1815 kunmap(rx_buffer->page);
1816
3832b26e 1817 return match;
da4dd0f7
PWJ		 1818}
1819
fc77dc3c 1820static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
3832b26e
AD		 1821 struct ixgbe_ring *tx_ring,
1822 unsigned int size)
84418e3b
AD		 1823{
1824 union ixgbe_adv_rx_desc *rx_desc;
3832b26e
AD		 1825 struct ixgbe_rx_buffer *rx_buffer;
1826 struct ixgbe_tx_buffer *tx_buffer;
84418e3b
AD		 1827 u16 rx_ntc, tx_ntc, count = 0;
1828
1829 /* initialize next to clean and descriptor values */
1830 rx_ntc = rx_ring->next_to_clean;
1831 tx_ntc = tx_ring->next_to_clean;
e4f74028 1832 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b 1833
3832b26e 1834 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
84418e3b 1835 /* check Rx buffer */
3832b26e 1836 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
84418e3b 1837
f800326d
AD		 1838 /* sync Rx buffer for CPU read */
1839 dma_sync_single_for_cpu(rx_ring->dev,
1840 rx_buffer->dma,
1841 ixgbe_rx_bufsz(rx_ring),
1842 DMA_FROM_DEVICE);
84418e3b
AD		 1843
1844 /* verify contents of skb */
3832b26e 1845 if (ixgbe_check_lbtest_frame(rx_buffer, size))
84418e3b
AD		 1846 count++;
1847
f800326d
AD		 1848 /* sync Rx buffer for device write */
1849 dma_sync_single_for_device(rx_ring->dev,
1850 rx_buffer->dma,
1851 ixgbe_rx_bufsz(rx_ring),
1852 DMA_FROM_DEVICE);
1853
84418e3b 1854 /* unmap buffer on Tx side */
3832b26e
AD		 1855 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1856 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
84418e3b
AD		 1857
1858 /* increment Rx/Tx next to clean counters */
1859 rx_ntc++;
1860 if (rx_ntc == rx_ring->count)
1861 rx_ntc = 0;
1862 tx_ntc++;
1863 if (tx_ntc == tx_ring->count)
1864 tx_ntc = 0;
1865
1866 /* fetch next descriptor */
e4f74028 1867 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b
AD		 1868 }
1869
dad8a3b3
JF		 1870 netdev_tx_reset_queue(txring_txq(tx_ring));
1871
84418e3b 1872 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1873 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1874 rx_ring->next_to_clean = rx_ntc;
1875 tx_ring->next_to_clean = tx_ntc;
1876
1877 return count;
1878}
1879
da4dd0f7
PWJ		 1880static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1881{
1882 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1883 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1884 int i, j, lc, good_cnt, ret_val = 0;
1885 unsigned int size = 1024;
1886 netdev_tx_t tx_ret_val;
1887 struct sk_buff *skb;
91ffdc84
ET		 1888 u32 flags_orig = adapter->flags;
1889
1890 /* DCB can modify the frames on Tx */
1891 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
84418e3b
AD		 1892
1893 /* allocate test skb */
1894 skb = alloc_skb(size, GFP_KERNEL);
1895 if (!skb)
1896 return 11;
da4dd0f7 1897
84418e3b
AD		 1898 /* place data into test skb */
1899 ixgbe_create_lbtest_frame(skb, size);
1900 skb_put(skb, size);
da4dd0f7
PWJ		 1901
1902 /*
1903 * Calculate the loop count based on the largest descriptor ring
1904 * The idea is to wrap the largest ring a number of times using 64
1905 * send/receive pairs during each loop
1906 */
1907
1908 if (rx_ring->count <= tx_ring->count)
1909 lc = ((tx_ring->count / 64) * 2) + 1;
1910 else
1911 lc = ((rx_ring->count / 64) * 2) + 1;
1912
da4dd0f7 1913 for (j = 0; j <= lc; j++) {
84418e3b 1914 /* reset count of good packets */
da4dd0f7 1915 good_cnt = 0;
84418e3b
AD		 1916
1917 /* place 64 packets on the transmit queue*/
1918 for (i = 0; i < 64; i++) {
1919 skb_get(skb);
1920 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1921 adapter,
1922 tx_ring);
1923 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1924 good_cnt++;
84418e3b
AD		 1925 }
1926
da4dd0f7 1927 if (good_cnt != 64) {
84418e3b 1928 ret_val = 12;
da4dd0f7
PWJ		 1929 break;
1930 }
84418e3b
AD		 1931
1932 /* allow 200 milliseconds for packets to go from Tx to Rx */
1933 msleep(200);
1934
fc77dc3c 1935 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1936 if (good_cnt != 64) {
1937 ret_val = 13;
da4dd0f7
PWJ		 1938 break;
1939 }
1940 }
1941
84418e3b
AD		 1942 /* free the original skb */
1943 kfree_skb(skb);
91ffdc84 1944 adapter->flags = flags_orig;
84418e3b 1945
da4dd0f7
PWJ		 1946 return ret_val;
1947}
1948
1949static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1950{
1951 *data = ixgbe_setup_desc_rings(adapter);
1952 if (*data)
1953 goto out;
1954 *data = ixgbe_setup_loopback_test(adapter);
1955 if (*data)
1956 goto err_loopback;
1957 *data = ixgbe_run_loopback_test(adapter);
1958 ixgbe_loopback_cleanup(adapter);
1959
1960err_loopback:
1961 ixgbe_free_desc_rings(adapter);
1962out:
1963 return *data;
1964}
1965
1966static void ixgbe_diag_test(struct net_device *netdev,
e7cf745b 1967 struct ethtool_test *eth_test, u64 *data)
da4dd0f7
PWJ		 1968{
1969 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1970 bool if_running = netif_running(netdev);
1971
b0483c8f
MR		 1972 if (ixgbe_removed(adapter->hw.hw_addr)) {
1973 e_err(hw, "Adapter removed - test blocked\n");
1974 data[0] = 1;
1975 data[1] = 1;
1976 data[2] = 1;
1977 data[3] = 1;
0edd2bdf 1978 data[4] = 1;
b0483c8f
MR		 1979 eth_test->flags |= ETH_TEST_FL_FAILED;
1980 return;
1981 }
da4dd0f7
PWJ		 1982 set_bit(__IXGBE_TESTING, &adapter->state);
1983 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
4ec375b1
ET		 1984 struct ixgbe_hw *hw = &adapter->hw;
1985
e7d481a6
GR		 1986 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1987 int i;
1988 for (i = 0; i < adapter->num_vfs; i++) {
1989 if (adapter->vfinfo[i].clear_to_send) {
1990 netdev_warn(netdev, "%s",
1991 "offline diagnostic is not "
1992 "supported when VFs are "
1993 "present\n");
1994 data[0] = 1;
1995 data[1] = 1;
1996 data[2] = 1;
1997 data[3] = 1;
0edd2bdf 1998 data[4] = 1;
e7d481a6
GR		 1999 eth_test->flags |= ETH_TEST_FL_FAILED;
2000 clear_bit(__IXGBE_TESTING,
2001 &adapter->state);
2002 goto skip_ol_tests;
2003 }
2004 }
2005 }
2006
dfcc4615
JK		 2007 /* Offline tests */
2008 e_info(hw, "offline testing starting\n");
2009
dfcc4615
JK		 2010 /* Link test performed before hardware reset so autoneg doesn't
2011 * interfere with test result
2012 */
2013 if (ixgbe_link_test(adapter, &data[4]))
2014 eth_test->flags |= ETH_TEST_FL_FAILED;
2015
4ec375b1
ET		 2016 if (if_running)
2017 /* indicate we're in test mode */
2018 dev_close(netdev);
2019 else
2020 ixgbe_reset(adapter);
2021
396e799c 2022 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 2023 if (ixgbe_reg_test(adapter, &data[0]))
2024 eth_test->flags |= ETH_TEST_FL_FAILED;
2025
2026 ixgbe_reset(adapter);
396e799c 2027 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 2028 if (ixgbe_eeprom_test(adapter, &data[1]))
2029 eth_test->flags |= ETH_TEST_FL_FAILED;
2030
2031 ixgbe_reset(adapter);
396e799c 2032 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 2033 if (ixgbe_intr_test(adapter, &data[2]))
2034 eth_test->flags |= ETH_TEST_FL_FAILED;
2035
bdbec4b8
GR		 2036 /* If SRIOV or VMDq is enabled then skip MAC
2037 * loopback diagnostic. */
2038 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2039 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 2040 e_info(hw, "Skip MAC loopback diagnostic in VT "
2041 "mode\n");
bdbec4b8
GR		 2042 data[3] = 0;
2043 goto skip_loopback;
2044 }
2045
da4dd0f7 2046 ixgbe_reset(adapter);
396e799c 2047 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 2048 if (ixgbe_loopback_test(adapter, &data[3]))
2049 eth_test->flags |= ETH_TEST_FL_FAILED;
2050
bdbec4b8 2051skip_loopback:
da4dd0f7
PWJ		 2052 ixgbe_reset(adapter);
2053
dfcc4615 2054 /* clear testing bit and return adapter to previous state */
da4dd0f7
PWJ		 2055 clear_bit(__IXGBE_TESTING, &adapter->state);
2056 if (if_running)
2057 dev_open(netdev);
4ec375b1
ET		 2058 else if (hw->mac.ops.disable_tx_laser)
2059 hw->mac.ops.disable_tx_laser(hw);
da4dd0f7 2060 } else {
396e799c 2061 e_info(hw, "online testing starting\n");
dfcc4615 2062
da4dd0f7
PWJ		 2063 /* Online tests */
2064 if (ixgbe_link_test(adapter, &data[4]))
2065 eth_test->flags |= ETH_TEST_FL_FAILED;
2066
dfcc4615 2067 /* Offline tests aren't run; pass by default */
da4dd0f7
PWJ		 2068 data[0] = 0;
2069 data[1] = 0;
2070 data[2] = 0;
2071 data[3] = 0;
2072
2073 clear_bit(__IXGBE_TESTING, &adapter->state);
2074 }
dfcc4615 2075
e7d481a6 2076skip_ol_tests:
da4dd0f7
PWJ		 2077 msleep_interruptible(4 * 1000);
2078}
9a799d71 2079
d6c519e1 2080static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
e7cf745b 2081 struct ethtool_wolinfo *wol)
d6c519e1
AD		 2082{
2083 struct ixgbe_hw *hw = &adapter->hw;
8e2813f5 2084 int retval = 0;
c23f5b6b 2085
8e2813f5
JK		 2086 /* WOL not supported for all devices */
2087 if (!ixgbe_wol_supported(adapter, hw->device_id,
2088 hw->subsystem_device_id)) {
2089 retval = 1;
d6c519e1 2090 wol->supported = 0;
d6c519e1
AD		 2091 }
2092
2093 return retval;
2094}
2095
9a799d71 2096static void ixgbe_get_wol(struct net_device *netdev,
e7cf745b 2097 struct ethtool_wolinfo *wol)
9a799d71 2098{
e63d9762
PW		 2099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2100
2101 wol->supported = WAKE_UCAST | WAKE_MCAST |
e7cf745b 2102 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 2103 wol->wolopts = 0;
2104
d6c519e1
AD		 2105 if (ixgbe_wol_exclusion(adapter, wol) ||
2106 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 2107 return;
2108
2109 if (adapter->wol & IXGBE_WUFC_EX)
2110 wol->wolopts |= WAKE_UCAST;
2111 if (adapter->wol & IXGBE_WUFC_MC)
2112 wol->wolopts |= WAKE_MCAST;
2113 if (adapter->wol & IXGBE_WUFC_BC)
2114 wol->wolopts |= WAKE_BCAST;
2115 if (adapter->wol & IXGBE_WUFC_MAG)
2116 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 2117}
2118
e63d9762
PW		 2119static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2120{
2121 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2122
2123 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2124 return -EOPNOTSUPP;
2125
d6c519e1
AD		 2126 if (ixgbe_wol_exclusion(adapter, wol))
2127 return wol->wolopts ? -EOPNOTSUPP : 0;
2128
e63d9762
PW		 2129 adapter->wol = 0;
2130
2131 if (wol->wolopts & WAKE_UCAST)
2132 adapter->wol |= IXGBE_WUFC_EX;
2133 if (wol->wolopts & WAKE_MCAST)
2134 adapter->wol |= IXGBE_WUFC_MC;
2135 if (wol->wolopts & WAKE_BCAST)
2136 adapter->wol |= IXGBE_WUFC_BC;
2137 if (wol->wolopts & WAKE_MAGIC)
2138 adapter->wol |= IXGBE_WUFC_MAG;
2139
2140 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2141
2142 return 0;
2143}
2144
9a799d71
AK		 2145static int ixgbe_nway_reset(struct net_device *netdev)
2146{
2147 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2148
d4f80882
AV		 2149 if (netif_running(netdev))
2150 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2151
2152 return 0;
2153}
2154
66e6961c
ET		 2155static int ixgbe_set_phys_id(struct net_device *netdev,
2156 enum ethtool_phys_id_state state)
9a799d71
AK		 2157{
2158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2159 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2160
66e6961c
ET		 2161 switch (state) {
2162 case ETHTOOL_ID_ACTIVE:
2163 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2164 return 2;
9a799d71 2165
66e6961c 2166 case ETHTOOL_ID_ON:
c44ade9e 2167 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2168 break;
2169
2170 case ETHTOOL_ID_OFF:
c44ade9e 2171 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2172 break;
9a799d71 2173
66e6961c
ET		 2174 case ETHTOOL_ID_INACTIVE:
2175 /* Restore LED settings */
2176 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2177 break;
2178 }
9a799d71
AK		 2179
2180 return 0;
2181}
2182
2183static int ixgbe_get_coalesce(struct net_device *netdev,
e7cf745b 2184 struct ethtool_coalesce *ec)
9a799d71
AK		 2185{
2186 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2187
30efa5a3 2188 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2189 if (adapter->rx_itr_setting <= 1)
2190 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2191 else
2192 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
f7554a2b 2193
cfb3f91a 2194 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2195 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2196 return 0;
2197
f7554a2b 2198 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2199 if (adapter->tx_itr_setting <= 1)
2200 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2201 else
2202 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
f7554a2b 2203
9a799d71
AK		 2204 return 0;
2205}
2206
80fba3f4
AD		 2207/*
2208 * this function must be called before setting the new value of
2209 * rx_itr_setting
2210 */
567d2de2 2211static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
80fba3f4
AD		 2212{
2213 struct net_device *netdev = adapter->netdev;
2214
567d2de2
AD		 2215 /* nothing to do if LRO or RSC are not enabled */
2216 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2217 !(netdev->features & NETIF_F_LRO))
80fba3f4
AD		 2218 return false;
2219
567d2de2
AD		 2220 /* check the feature flag value and enable RSC if necessary */
2221 if (adapter->rx_itr_setting == 1 ||
2222 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2223 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
80fba3f4 2224 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
567d2de2
AD		 2225 e_info(probe, "rx-usecs value high enough "
2226 "to re-enable RSC\n");
80fba3f4
AD		 2227 return true;
2228 }
567d2de2
AD		 2229 /* if interrupt rate is too high then disable RSC */
2230 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2231 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2232 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2233 return true;
80fba3f4
AD		 2234 }
2235 return false;
2236}
2237
9a799d71 2238static int ixgbe_set_coalesce(struct net_device *netdev,
e7cf745b 2239 struct ethtool_coalesce *ec)
9a799d71
AK		 2240{
2241 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2242 struct ixgbe_q_vector *q_vector;
30efa5a3 2243 int i;
67da097e 2244 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
ef021194 2245 bool need_reset = false;
9a799d71 2246
67da097e
ET		 2247 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2248 /* reject Tx specific changes in case of mixed RxTx vectors */
2249 if (ec->tx_coalesce_usecs)
2250 return -EINVAL;
2251 tx_itr_prev = adapter->rx_itr_setting;
2252 } else {
2253 tx_itr_prev = adapter->tx_itr_setting;
2254 }
f7554a2b 2255
d5bf4f67
ET		 2256 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2257 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2258 return -EINVAL;
30efa5a3 2259
d5bf4f67
ET		 2260 if (ec->rx_coalesce_usecs > 1)
2261 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2262 else
2263 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
f7554a2b 2264
d5bf4f67
ET		 2265 if (adapter->rx_itr_setting == 1)
2266 rx_itr_param = IXGBE_20K_ITR;
2267 else
2268 rx_itr_param = adapter->rx_itr_setting;
f7554a2b 2269
d5bf4f67
ET		 2270 if (ec->tx_coalesce_usecs > 1)
2271 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2272 else
2273 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
f7554a2b 2274
d5bf4f67
ET		 2275 if (adapter->tx_itr_setting == 1)
2276 tx_itr_param = IXGBE_10K_ITR;
2277 else
2278 tx_itr_param = adapter->tx_itr_setting;
f7554a2b 2279
67da097e
ET		 2280 /* mixed Rx/Tx */
2281 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2282 adapter->tx_itr_setting = adapter->rx_itr_setting;
2283
2284#if IS_ENABLED(CONFIG_BQL)
2285 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2e010381 2286 if ((adapter->tx_itr_setting != 1) &&
67da097e
ET		 2287 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2288 if ((tx_itr_prev == 1) ||
2e010381 2289 (tx_itr_prev >= IXGBE_100K_ITR))
67da097e
ET		 2290 need_reset = true;
2291 } else {
2e010381 2292 if ((tx_itr_prev != 1) &&
67da097e
ET		 2293 (tx_itr_prev < IXGBE_100K_ITR))
2294 need_reset = true;
2295 }
2296#endif
567d2de2 2297 /* check the old value and enable RSC if necessary */
67da097e 2298 need_reset |= ixgbe_update_rsc(adapter);
567d2de2 2299
49c7ffbe 2300 for (i = 0; i < adapter->num_q_vectors; i++) {
d5bf4f67 2301 q_vector = adapter->q_vector[i];
d5bf4f67
ET		 2302 if (q_vector->tx.count && !q_vector->rx.count)
2303 /* tx only */
2304 q_vector->itr = tx_itr_param;
2305 else
2306 /* rx only or mixed */
2307 q_vector->itr = rx_itr_param;
fe49f04a 2308 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2309 }
2310
ef021194
JB		 2311 /*
2312 * do reset here at the end to make sure EITR==0 case is handled
2313 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2314 * also locks in RSC enable/disable which requires reset
2315 */
c988ee82
ET		 2316 if (need_reset)
2317 ixgbe_do_reset(netdev);
ef021194 2318
9a799d71
AK		 2319 return 0;
2320}
2321
3e05334f
AD		 2322static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2323 struct ethtool_rxnfc *cmd)
2324{
2325 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2326 struct ethtool_rx_flow_spec *fsp =
2327 (struct ethtool_rx_flow_spec *)&cmd->fs;
b67bfe0d 2328 struct hlist_node *node2;
3e05334f
AD		 2329 struct ixgbe_fdir_filter *rule = NULL;
2330
2331 /* report total rule count */
2332 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2333
b67bfe0d 2334 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2335 &adapter->fdir_filter_list, fdir_node) {
2336 if (fsp->location <= rule->sw_idx)
2337 break;
2338 }
2339
2340 if (!rule || fsp->location != rule->sw_idx)
2341 return -EINVAL;
2342
2343 /* fill out the flow spec entry */
2344
2345 /* set flow type field */
2346 switch (rule->filter.formatted.flow_type) {
2347 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2348 fsp->flow_type = TCP_V4_FLOW;
2349 break;
2350 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2351 fsp->flow_type = UDP_V4_FLOW;
2352 break;
2353 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2354 fsp->flow_type = SCTP_V4_FLOW;
2355 break;
2356 case IXGBE_ATR_FLOW_TYPE_IPV4:
2357 fsp->flow_type = IP_USER_FLOW;
2358 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2359 fsp->h_u.usr_ip4_spec.proto = 0;
2360 fsp->m_u.usr_ip4_spec.proto = 0;
2361 break;
2362 default:
2363 return -EINVAL;
2364 }
2365
2366 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2367 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2368 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2369 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2370 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2371 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2372 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2373 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2374 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2375 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2376 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2377 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2378 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2379 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2380 fsp->flow_type |= FLOW_EXT;
2381
2382 /* record action */
2383 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2384 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2385 else
2386 fsp->ring_cookie = rule->action;
2387
2388 return 0;
2389}
2390
2391static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2392 struct ethtool_rxnfc *cmd,
2393 u32 *rule_locs)
2394{
b67bfe0d 2395 struct hlist_node *node2;
3e05334f
AD		 2396 struct ixgbe_fdir_filter *rule;
2397 int cnt = 0;
2398
2399 /* report total rule count */
2400 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2401
b67bfe0d 2402 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2403 &adapter->fdir_filter_list, fdir_node) {
2404 if (cnt == cmd->rule_cnt)
2405 return -EMSGSIZE;
2406 rule_locs[cnt] = rule->sw_idx;
2407 cnt++;
2408 }
2409
473e64ee
BH		 2410 cmd->rule_cnt = cnt;
2411
3e05334f
AD		 2412 return 0;
2413}
2414
ef6afc0c
AD		 2415static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2416 struct ethtool_rxnfc *cmd)
2417{
2418 cmd->data = 0;
2419
ef6afc0c
AD		 2420 /* Report default options for RSS on ixgbe */
2421 switch (cmd->flow_type) {
2422 case TCP_V4_FLOW:
2423 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2424 case UDP_V4_FLOW:
2425 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2426 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2427 case SCTP_V4_FLOW:
2428 case AH_ESP_V4_FLOW:
2429 case AH_V4_FLOW:
2430 case ESP_V4_FLOW:
2431 case IPV4_FLOW:
2432 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2433 break;
2434 case TCP_V6_FLOW:
2435 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2436 case UDP_V6_FLOW:
2437 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2438 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2439 case SCTP_V6_FLOW:
2440 case AH_ESP_V6_FLOW:
2441 case AH_V6_FLOW:
2442 case ESP_V6_FLOW:
2443 case IPV6_FLOW:
2444 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2445 break;
2446 default:
2447 return -EINVAL;
2448 }
2449
2450 return 0;
2451}
2452
91cd94bf 2453static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2454 u32 *rule_locs)
91cd94bf
AD		 2455{
2456 struct ixgbe_adapter *adapter = netdev_priv(dev);
2457 int ret = -EOPNOTSUPP;
2458
2459 switch (cmd->cmd) {
2460 case ETHTOOL_GRXRINGS:
2461 cmd->data = adapter->num_rx_queues;
2462 ret = 0;
2463 break;
3e05334f
AD		 2464 case ETHTOOL_GRXCLSRLCNT:
2465 cmd->rule_cnt = adapter->fdir_filter_count;
2466 ret = 0;
2467 break;
2468 case ETHTOOL_GRXCLSRULE:
2469 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2470 break;
2471 case ETHTOOL_GRXCLSRLALL:
815c7db5 2472 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2473 break;
ef6afc0c
AD		 2474 case ETHTOOL_GRXFH:
2475 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2476 break;
91cd94bf
AD		 2477 default:
2478 break;
2479 }
2480
2481 return ret;
2482}
2483
e4911d57
AD		 2484static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2485 struct ixgbe_fdir_filter *input,
2486 u16 sw_idx)
2487{
2488 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d
SL		 2489 struct hlist_node *node2;
2490 struct ixgbe_fdir_filter *rule, *parent;
e4911d57
AD		 2491 int err = -EINVAL;
2492
2493 parent = NULL;
2494 rule = NULL;
2495
b67bfe0d 2496 hlist_for_each_entry_safe(rule, node2,
e4911d57
AD		 2497 &adapter->fdir_filter_list, fdir_node) {
2498 /* hash found, or no matching entry */
2499 if (rule->sw_idx >= sw_idx)
2500 break;
b67bfe0d 2501 parent = rule;
e4911d57
AD		 2502 }
2503
2504 /* if there is an old rule occupying our place remove it */
2505 if (rule && (rule->sw_idx == sw_idx)) {
2506 if (!input || (rule->filter.formatted.bkt_hash !=
2507 input->filter.formatted.bkt_hash)) {
2508 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2509 &rule->filter,
2510 sw_idx);
2511 }
2512
2513 hlist_del(&rule->fdir_node);
2514 kfree(rule);
2515 adapter->fdir_filter_count--;
2516 }
2517
2518 /*
2519 * If no input this was a delete, err should be 0 if a rule was
2520 * successfully found and removed from the list else -EINVAL
2521 */
2522 if (!input)
2523 return err;
2524
2525 /* initialize node and set software index */
2526 INIT_HLIST_NODE(&input->fdir_node);
2527
2528 /* add filter to the list */
2529 if (parent)
b67bfe0d 2530 hlist_add_after(&parent->fdir_node, &input->fdir_node);
e4911d57
AD		 2531 else
2532 hlist_add_head(&input->fdir_node,
2533 &adapter->fdir_filter_list);
2534
2535 /* update counts */
2536 adapter->fdir_filter_count++;
2537
2538 return 0;
2539}
2540
2541static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2542 u8 *flow_type)
2543{
2544 switch (fsp->flow_type & ~FLOW_EXT) {
2545 case TCP_V4_FLOW:
2546 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2547 break;
2548 case UDP_V4_FLOW:
2549 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2550 break;
2551 case SCTP_V4_FLOW:
2552 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2553 break;
2554 case IP_USER_FLOW:
2555 switch (fsp->h_u.usr_ip4_spec.proto) {
2556 case IPPROTO_TCP:
2557 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2558 break;
2559 case IPPROTO_UDP:
2560 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2561 break;
2562 case IPPROTO_SCTP:
2563 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2564 break;
2565 case 0:
2566 if (!fsp->m_u.usr_ip4_spec.proto) {
2567 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2568 break;
2569 }
2570 default:
2571 return 0;
2572 }
2573 break;
2574 default:
2575 return 0;
2576 }
2577
2578 return 1;
2579}
2580
2581static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2582 struct ethtool_rxnfc *cmd)
2583{
2584 struct ethtool_rx_flow_spec *fsp =
2585 (struct ethtool_rx_flow_spec *)&cmd->fs;
2586 struct ixgbe_hw *hw = &adapter->hw;
2587 struct ixgbe_fdir_filter *input;
2588 union ixgbe_atr_input mask;
2589 int err;
2590
2591 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2592 return -EOPNOTSUPP;
2593
2594 /*
2595 * Don't allow programming if the action is a queue greater than
2596 * the number of online Rx queues.
2597 */
2598 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2599 (fsp->ring_cookie >= adapter->num_rx_queues))
2600 return -EINVAL;
2601
2602 /* Don't allow indexes to exist outside of available space */
2603 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2604 e_err(drv, "Location out of range\n");
2605 return -EINVAL;
2606 }
2607
2608 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2609 if (!input)
2610 return -ENOMEM;
2611
2612 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2613
2614 /* set SW index */
2615 input->sw_idx = fsp->location;
2616
2617 /* record flow type */
2618 if (!ixgbe_flowspec_to_flow_type(fsp,
2619 &input->filter.formatted.flow_type)) {
2620 e_err(drv, "Unrecognized flow type\n");
2621 goto err_out;
2622 }
2623
2624 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2625 IXGBE_ATR_L4TYPE_MASK;
2626
2627 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2628 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2629
2630 /* Copy input into formatted structures */
2631 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2632 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2633 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2634 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2635 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2636 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2637 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2638 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2639
2640 if (fsp->flow_type & FLOW_EXT) {
2641 input->filter.formatted.vm_pool =
2642 (unsigned char)ntohl(fsp->h_ext.data[1]);
2643 mask.formatted.vm_pool =
2644 (unsigned char)ntohl(fsp->m_ext.data[1]);
2645 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2646 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2647 input->filter.formatted.flex_bytes =
2648 fsp->h_ext.vlan_etype;
2649 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2650 }
2651
2652 /* determine if we need to drop or route the packet */
2653 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2654 input->action = IXGBE_FDIR_DROP_QUEUE;
2655 else
2656 input->action = fsp->ring_cookie;
2657
2658 spin_lock(&adapter->fdir_perfect_lock);
2659
2660 if (hlist_empty(&adapter->fdir_filter_list)) {
2661 /* save mask and program input mask into HW */
2662 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2663 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2664 if (err) {
2665 e_err(drv, "Error writing mask\n");
2666 goto err_out_w_lock;
2667 }
2668 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2669 e_err(drv, "Only one mask supported per port\n");
2670 goto err_out_w_lock;
2671 }
2672
2673 /* apply mask and compute/store hash */
2674 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2675
2676 /* program filters to filter memory */
2677 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2678 &input->filter, input->sw_idx,
1f4d5183
AD		 2679 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2680 IXGBE_FDIR_DROP_QUEUE :
e4911d57
AD		 2681 adapter->rx_ring[input->action]->reg_idx);
2682 if (err)
2683 goto err_out_w_lock;
2684
2685 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2686
2687 spin_unlock(&adapter->fdir_perfect_lock);
2688
2689 return err;
2690err_out_w_lock:
2691 spin_unlock(&adapter->fdir_perfect_lock);
2692err_out:
2693 kfree(input);
2694 return -EINVAL;
2695}
2696
2697static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2698 struct ethtool_rxnfc *cmd)
2699{
2700 struct ethtool_rx_flow_spec *fsp =
2701 (struct ethtool_rx_flow_spec *)&cmd->fs;
2702 int err;
2703
2704 spin_lock(&adapter->fdir_perfect_lock);
2705 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2706 spin_unlock(&adapter->fdir_perfect_lock);
2707
2708 return err;
2709}
2710
ef6afc0c
AD		 2711#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2712 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2713static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2714 struct ethtool_rxnfc *nfc)
2715{
2716 u32 flags2 = adapter->flags2;
2717
2718 /*
2719 * RSS does not support anything other than hashing
2720 * to queues on src and dst IPs and ports
2721 */
2722 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2723 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2724 return -EINVAL;
2725
2726 switch (nfc->flow_type) {
2727 case TCP_V4_FLOW:
2728 case TCP_V6_FLOW:
2729 if (!(nfc->data & RXH_IP_SRC) ||
2730 !(nfc->data & RXH_IP_DST) ||
2731 !(nfc->data & RXH_L4_B_0_1) ||
2732 !(nfc->data & RXH_L4_B_2_3))
2733 return -EINVAL;
2734 break;
2735 case UDP_V4_FLOW:
2736 if (!(nfc->data & RXH_IP_SRC) ||
2737 !(nfc->data & RXH_IP_DST))
2738 return -EINVAL;
2739 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2740 case 0:
2741 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2742 break;
2743 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2744 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2745 break;
2746 default:
2747 return -EINVAL;
2748 }
2749 break;
2750 case UDP_V6_FLOW:
2751 if (!(nfc->data & RXH_IP_SRC) ||
2752 !(nfc->data & RXH_IP_DST))
2753 return -EINVAL;
2754 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2755 case 0:
2756 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2757 break;
2758 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2759 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2760 break;
2761 default:
2762 return -EINVAL;
2763 }
2764 break;
2765 case AH_ESP_V4_FLOW:
2766 case AH_V4_FLOW:
2767 case ESP_V4_FLOW:
2768 case SCTP_V4_FLOW:
2769 case AH_ESP_V6_FLOW:
2770 case AH_V6_FLOW:
2771 case ESP_V6_FLOW:
2772 case SCTP_V6_FLOW:
2773 if (!(nfc->data & RXH_IP_SRC) ||
2774 !(nfc->data & RXH_IP_DST) ||
2775 (nfc->data & RXH_L4_B_0_1) ||
2776 (nfc->data & RXH_L4_B_2_3))
2777 return -EINVAL;
2778 break;
2779 default:
2780 return -EINVAL;
2781 }
2782
2783 /* if we changed something we need to update flags */
2784 if (flags2 != adapter->flags2) {
2785 struct ixgbe_hw *hw = &adapter->hw;
2786 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2787
2788 if ((flags2 & UDP_RSS_FLAGS) &&
2789 !(adapter->flags2 & UDP_RSS_FLAGS))
2790 e_warn(drv, "enabling UDP RSS: fragmented packets"
2791 " may arrive out of order to the stack above\n");
2792
2793 adapter->flags2 = flags2;
2794
2795 /* Perform hash on these packet types */
2796 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2797 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2798 | IXGBE_MRQC_RSS_FIELD_IPV6
2799 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2800
2801 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2802 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2803
2804 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2805 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2806
2807 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2808 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2809
2810 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2811 }
2812
2813 return 0;
2814}
2815
e4911d57
AD		 2816static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2817{
2818 struct ixgbe_adapter *adapter = netdev_priv(dev);
2819 int ret = -EOPNOTSUPP;
2820
2821 switch (cmd->cmd) {
2822 case ETHTOOL_SRXCLSRLINS:
2823 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2824 break;
2825 case ETHTOOL_SRXCLSRLDEL:
2826 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2827 break;
ef6afc0c
AD		 2828 case ETHTOOL_SRXFH:
2829 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2830 break;
e4911d57
AD		 2831 default:
2832 break;
2833 }
2834
2835 return ret;
2836}
2837
e3aac889
JK		 2838static int ixgbe_get_ts_info(struct net_device *dev,
2839 struct ethtool_ts_info *info)
2840{
2841 struct ixgbe_adapter *adapter = netdev_priv(dev);
2842
2843 switch (adapter->hw.mac.type) {
e3aac889
JK		 2844 case ixgbe_mac_X540:
2845 case ixgbe_mac_82599EB:
2846 info->so_timestamping =
50f8d35d
JK		 2847 SOF_TIMESTAMPING_TX_SOFTWARE |
2848 SOF_TIMESTAMPING_RX_SOFTWARE |
2849 SOF_TIMESTAMPING_SOFTWARE |
e3aac889
JK		 2850 SOF_TIMESTAMPING_TX_HARDWARE |
2851 SOF_TIMESTAMPING_RX_HARDWARE |
2852 SOF_TIMESTAMPING_RAW_HARDWARE;
2853
2854 if (adapter->ptp_clock)
2855 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2856 else
2857 info->phc_index = -1;
2858
2859 info->tx_types =
2860 (1 << HWTSTAMP_TX_OFF) |
2861 (1 << HWTSTAMP_TX_ON);
2862
2863 info->rx_filters =
2864 (1 << HWTSTAMP_FILTER_NONE) |
2865 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2866 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
aeb82648
JK		 2867 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2868 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2869 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2870 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2871 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2872 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2873 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2874 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1cc92eb8 2875 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
e3aac889 2876 break;
e3aac889
JK		 2877 default:
2878 return ethtool_op_get_ts_info(dev, info);
2879 break;
2880 }
2881 return 0;
2882}
2883
5348c9db
AD		 2884static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2885{
2886 unsigned int max_combined;
2887 u8 tcs = netdev_get_num_tc(adapter->netdev);
2888
2889 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2890 /* We only support one q_vector without MSI-X */
2891 max_combined = 1;
2892 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2893 /* SR-IOV currently only allows one queue on the PF */
2894 max_combined = 1;
2895 } else if (tcs > 1) {
2896 /* For DCB report channels per traffic class */
2897 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2898 /* 8 TC w/ 4 queues per TC */
2899 max_combined = 4;
2900 } else if (tcs > 4) {
2901 /* 8 TC w/ 8 queues per TC */
2902 max_combined = 8;
2903 } else {
2904 /* 4 TC w/ 16 queues per TC */
2905 max_combined = 16;
2906 }
2907 } else if (adapter->atr_sample_rate) {
2908 /* support up to 64 queues with ATR */
2909 max_combined = IXGBE_MAX_FDIR_INDICES;
2910 } else {
2911 /* support up to 16 queues with RSS */
2912 max_combined = IXGBE_MAX_RSS_INDICES;
2913 }
2914
2915 return max_combined;
2916}
2917
2918static void ixgbe_get_channels(struct net_device *dev,
2919 struct ethtool_channels *ch)
2920{
2921 struct ixgbe_adapter *adapter = netdev_priv(dev);
2922
2923 /* report maximum channels */
2924 ch->max_combined = ixgbe_max_channels(adapter);
2925
2926 /* report info for other vector */
2927 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2928 ch->max_other = NON_Q_VECTORS;
2929 ch->other_count = NON_Q_VECTORS;
2930 }
2931
2932 /* record RSS queues */
2933 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2934
2935 /* nothing else to report if RSS is disabled */
2936 if (ch->combined_count == 1)
2937 return;
2938
2939 /* we do not support ATR queueing if SR-IOV is enabled */
2940 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2941 return;
2942
2943 /* same thing goes for being DCB enabled */
2944 if (netdev_get_num_tc(dev) > 1)
2945 return;
2946
2947 /* if ATR is disabled we can exit */
2948 if (!adapter->atr_sample_rate)
2949 return;
2950
2951 /* report flow director queues as maximum channels */
2952 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2953}
2954
4c696ca9
AD		 2955static int ixgbe_set_channels(struct net_device *dev,
2956 struct ethtool_channels *ch)
2957{
2958 struct ixgbe_adapter *adapter = netdev_priv(dev);
2959 unsigned int count = ch->combined_count;
2960
2961 /* verify they are not requesting separate vectors */
2962 if (!count || ch->rx_count || ch->tx_count)
2963 return -EINVAL;
2964
2965 /* verify other_count has not changed */
2966 if (ch->other_count != NON_Q_VECTORS)
2967 return -EINVAL;
2968
2969 /* verify the number of channels does not exceed hardware limits */
2970 if (count > ixgbe_max_channels(adapter))
2971 return -EINVAL;
2972
2973 /* update feature limits from largest to smallest supported values */
2974 adapter->ring_feature[RING_F_FDIR].limit = count;
2975
2976 /* cap RSS limit at 16 */
2977 if (count > IXGBE_MAX_RSS_INDICES)
2978 count = IXGBE_MAX_RSS_INDICES;
2979 adapter->ring_feature[RING_F_RSS].limit = count;
2980
2981#ifdef IXGBE_FCOE
2982 /* cap FCoE limit at 8 */
2983 if (count > IXGBE_FCRETA_SIZE)
2984 count = IXGBE_FCRETA_SIZE;
2985 adapter->ring_feature[RING_F_FCOE].limit = count;
2986
2987#endif
2988 /* use setup TC to update any traffic class queue mapping */
2989 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2990}
2991
71858acb
AG		 2992static int ixgbe_get_module_info(struct net_device *dev,
2993 struct ethtool_modinfo *modinfo)
2994{
2995 struct ixgbe_adapter *adapter = netdev_priv(dev);
2996 struct ixgbe_hw *hw = &adapter->hw;
2997 u32 status;
2998 u8 sff8472_rev, addr_mode;
71858acb
AG		 2999 bool page_swap = false;
3000
71858acb
AG		 3001 /* Check whether we support SFF-8472 or not */
3002 status = hw->phy.ops.read_i2c_eeprom(hw,
3003 IXGBE_SFF_SFF_8472_COMP,
3004 &sff8472_rev);
a4b6fc6b
ET		 3005 if (status != 0)
3006 return -EIO;
71858acb
AG		 3007
3008 /* addressing mode is not supported */
3009 status = hw->phy.ops.read_i2c_eeprom(hw,
3010 IXGBE_SFF_SFF_8472_SWAP,
3011 &addr_mode);
a4b6fc6b
ET		 3012 if (status != 0)
3013 return -EIO;
71858acb
AG		 3014
3015 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3016 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3017 page_swap = true;
3018 }
3019
3020 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3021 /* We have a SFP, but it does not support SFF-8472 */
3022 modinfo->type = ETH_MODULE_SFF_8079;
3023 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3024 } else {
3025 /* We have a SFP which supports a revision of SFF-8472. */
3026 modinfo->type = ETH_MODULE_SFF_8472;
3027 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3028 }
3029
a4b6fc6b 3030 return 0;
71858acb
AG		 3031}
3032
3033static int ixgbe_get_module_eeprom(struct net_device *dev,
3034 struct ethtool_eeprom *ee,
3035 u8 *data)
3036{
3037 struct ixgbe_adapter *adapter = netdev_priv(dev);
3038 struct ixgbe_hw *hw = &adapter->hw;
3039 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3040 u8 databyte = 0xFF;
3041 int i = 0;
71858acb 3042
a4b6fc6b
ET		 3043 if (ee->len == 0)
3044 return -EINVAL;
71858acb 3045
31c7d2b0 3046 for (i = ee->offset; i < ee->offset + ee->len; i++) {
a4b6fc6b
ET		 3047 /* I2C reads can take long time */
3048 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3049 return -EBUSY;
71858acb 3050
a4b6fc6b 3051 if (i < ETH_MODULE_SFF_8079_LEN)
31c7d2b0 3052 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
a4b6fc6b
ET		 3053 else
3054 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3055
3056 if (status != 0)
31c7d2b0 3057 return -EIO;
71858acb 3058
a4b6fc6b 3059 data[i - ee->offset] = databyte;
71858acb
AG		 3060 }
3061
31c7d2b0 3062 return 0;
71858acb
AG		 3063}
3064
b9804972 3065static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 3066 .get_settings = ixgbe_get_settings,
3067 .set_settings = ixgbe_set_settings,
3068 .get_drvinfo = ixgbe_get_drvinfo,
3069 .get_regs_len = ixgbe_get_regs_len,
3070 .get_regs = ixgbe_get_regs,
3071 .get_wol = ixgbe_get_wol,
e63d9762 3072 .set_wol = ixgbe_set_wol,
9a799d71
AK		 3073 .nway_reset = ixgbe_nway_reset,
3074 .get_link = ethtool_op_get_link,
3075 .get_eeprom_len = ixgbe_get_eeprom_len,
3076 .get_eeprom = ixgbe_get_eeprom,
2fa5eef4 3077 .set_eeprom = ixgbe_set_eeprom,
9a799d71
AK		 3078 .get_ringparam = ixgbe_get_ringparam,
3079 .set_ringparam = ixgbe_set_ringparam,
3080 .get_pauseparam = ixgbe_get_pauseparam,
3081 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 3082 .get_msglevel = ixgbe_get_msglevel,
3083 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 3084 .self_test = ixgbe_diag_test,
9a799d71 3085 .get_strings = ixgbe_get_strings,
66e6961c 3086 .set_phys_id = ixgbe_set_phys_id,
b4617240 3087 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 3088 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3089 .get_coalesce = ixgbe_get_coalesce,
3090 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 3091 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 3092 .set_rxnfc = ixgbe_set_rxnfc,
5348c9db 3093 .get_channels = ixgbe_get_channels,
4c696ca9 3094 .set_channels = ixgbe_set_channels,
e3aac889 3095 .get_ts_info = ixgbe_get_ts_info,
71858acb
AG		 3096 .get_module_info = ixgbe_get_module_info,
3097 .get_module_eeprom = ixgbe_get_module_eeprom,
9a799d71
AK		 3098};
3099
3100void ixgbe_set_ethtool_ops(struct net_device *netdev)
3101{
7ad24ea4 3102 netdev->ethtool_ops = &ixgbe_ethtool_ops;
9a799d71 3103}
Linux kernel - Deliverables
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