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ixgbevf: minor cleanups for ixgbevf_set_itr()
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0edd2bdf 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for ixgbe */
30
a6b7a407 31#include <linux/interrupt.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/module.h>
5a0e3ad6 34#include <linux/slab.h>
9a799d71
AK		 35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/ethtool.h>
38#include <linux/vmalloc.h>
f800326d 39#include <linux/highmem.h>
9a799d71
AK		 40#include <linux/uaccess.h>
41
42#include "ixgbe.h"
71858acb 43#include "ixgbe_phy.h"
9a799d71
AK		 44
45
46#define IXGBE_ALL_RAR_ENTRIES 16
47
29c3a050
AK		 48enum {NETDEV_STATS, IXGBE_STATS};
49
9a799d71
AK		 50struct ixgbe_stats {
51 char stat_string[ETH_GSTRING_LEN];
29c3a050 52 int type;
9a799d71
AK		 53 int sizeof_stat;
54 int stat_offset;
55};
56
29c3a050
AK		 57#define IXGBE_STAT(m) IXGBE_STATS, \
58 sizeof(((struct ixgbe_adapter *)0)->m), \
59 offsetof(struct ixgbe_adapter, m)
60#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \
62 offsetof(struct rtnl_link_stats64, m)
29c3a050 63
1bba2e81 64static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 73 {"lsc_int", IXGBE_STAT(lsc_int)},
74 {"tx_busy", IXGBE_STAT(tx_busy)},
75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
80 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 81 {"broadcast", IXGBE_STAT(stats.bprc)},
82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 83 {"collisions", IXGBE_NETDEV_STAT(collisions)},
84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
99 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 114#ifdef IXGBE_FCOE
115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
7b859ebc
AH		 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
6d45522c
YZ		 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
123#endif /* IXGBE_FCOE */
9a799d71
AK		 124};
125
9cc00b51
JF		 126/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
127 * we set the num_rx_queues to evaluate to num_tx_queues. This is
128 * used because we do not have a good way to get the max number of
129 * rx queues with CONFIG_RPS disabled.
130 */
131#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
132
133#define IXGBE_QUEUE_STATS_LEN ( \
134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
454d7c9b 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 136#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 137#define IXGBE_PB_STATS_LEN ( \
9cc00b51
JF		 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
142 / sizeof(u64))
2f90b865 143#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
e7cf745b
JK		 144 IXGBE_PB_STATS_LEN + \
145 IXGBE_QUEUE_STATS_LEN)
9a799d71 146
da4dd0f7
PWJ		 147static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
148 "Register test (offline)", "Eeprom test (offline)",
149 "Interrupt test (offline)", "Loopback test (offline)",
150 "Link test (on/offline)"
151};
152#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
153
9a799d71 154static int ixgbe_get_settings(struct net_device *netdev,
e7cf745b 155 struct ethtool_cmd *ecmd)
9a799d71
AK		 156{
157 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 158 struct ixgbe_hw *hw = &adapter->hw;
db018963 159 ixgbe_link_speed supported_link;
735441fb 160 u32 link_speed = 0;
fd0326f2 161 bool autoneg = false;
735441fb 162 bool link_up;
9a799d71 163
db018963 164 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
1b1c0a48 165
db018963
JK		 166 /* set the supported link speeds */
167 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
168 ecmd->supported |= SUPPORTED_10000baseT_Full;
169 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
170 ecmd->supported |= SUPPORTED_1000baseT_Full;
171 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
172 ecmd->supported |= SUPPORTED_100baseT_Full;
1b1c0a48 173
db018963
JK		 174 /* set the advertised speeds */
175 if (hw->phy.autoneg_advertised) {
176 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
177 ecmd->advertising |= ADVERTISED_100baseT_Full;
178 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
179 ecmd->advertising |= ADVERTISED_10000baseT_Full;
180 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
181 ecmd->advertising |= ADVERTISED_1000baseT_Full;
735441fb 182 } else {
db018963
JK		 183 /* default modes in case phy.autoneg_advertised isn't set */
184 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
185 ecmd->advertising |= ADVERTISED_10000baseT_Full;
186 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
187 ecmd->advertising |= ADVERTISED_1000baseT_Full;
188 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
189 ecmd->advertising |= ADVERTISED_100baseT_Full;
ed33ff66
ET		 190
191 if (hw->phy.multispeed_fiber && !autoneg) {
192 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
193 ecmd->advertising = ADVERTISED_10000baseT_Full;
194 }
735441fb 195 }
9a799d71 196
db018963
JK		 197 if (autoneg) {
198 ecmd->supported |= SUPPORTED_Autoneg;
199 ecmd->advertising |= ADVERTISED_Autoneg;
200 ecmd->autoneg = AUTONEG_ENABLE;
201 } else
202 ecmd->autoneg = AUTONEG_DISABLE;
203
204 ecmd->transceiver = XCVR_EXTERNAL;
205
206 /* Determine the remaining settings based on the PHY type. */
3b8626ba
PW		 207 switch (adapter->hw.phy.type) {
208 case ixgbe_phy_tn:
fe15e8e1 209 case ixgbe_phy_aq:
c2c78d5c 210 case ixgbe_phy_x550em_ext_t:
3b8626ba 211 case ixgbe_phy_cu_unknown:
db018963
JK		 212 ecmd->supported |= SUPPORTED_TP;
213 ecmd->advertising |= ADVERTISED_TP;
3b8626ba
PW		 214 ecmd->port = PORT_TP;
215 break;
216 case ixgbe_phy_qt:
db018963
JK		 217 ecmd->supported |= SUPPORTED_FIBRE;
218 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 219 ecmd->port = PORT_FIBRE;
220 break;
221 case ixgbe_phy_nl:
ea0a04df
DS		 222 case ixgbe_phy_sfp_passive_tyco:
223 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 224 case ixgbe_phy_sfp_ftl:
225 case ixgbe_phy_sfp_avago:
226 case ixgbe_phy_sfp_intel:
227 case ixgbe_phy_sfp_unknown:
3b8626ba 228 /* SFP+ devices, further checking needed */
db018963 229 switch (adapter->hw.phy.sfp_type) {
3b8626ba
PW		 230 case ixgbe_sfp_type_da_cu:
231 case ixgbe_sfp_type_da_cu_core0:
232 case ixgbe_sfp_type_da_cu_core1:
db018963
JK		 233 ecmd->supported |= SUPPORTED_FIBRE;
234 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 235 ecmd->port = PORT_DA;
236 break;
237 case ixgbe_sfp_type_sr:
238 case ixgbe_sfp_type_lr:
239 case ixgbe_sfp_type_srlr_core0:
240 case ixgbe_sfp_type_srlr_core1:
345be204
DS		 241 case ixgbe_sfp_type_1g_sx_core0:
242 case ixgbe_sfp_type_1g_sx_core1:
243 case ixgbe_sfp_type_1g_lx_core0:
244 case ixgbe_sfp_type_1g_lx_core1:
db018963
JK		 245 ecmd->supported |= SUPPORTED_FIBRE;
246 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 247 ecmd->port = PORT_FIBRE;
248 break;
249 case ixgbe_sfp_type_not_present:
db018963
JK		 250 ecmd->supported |= SUPPORTED_FIBRE;
251 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 252 ecmd->port = PORT_NONE;
253 break;
cb836a97
DS		 254 case ixgbe_sfp_type_1g_cu_core0:
255 case ixgbe_sfp_type_1g_cu_core1:
db018963
JK		 256 ecmd->supported |= SUPPORTED_TP;
257 ecmd->advertising |= ADVERTISED_TP;
cb836a97 258 ecmd->port = PORT_TP;
db018963 259 break;
3b8626ba
PW		 260 case ixgbe_sfp_type_unknown:
261 default:
db018963
JK		 262 ecmd->supported |= SUPPORTED_FIBRE;
263 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 264 ecmd->port = PORT_OTHER;
265 break;
266 }
267 break;
268 case ixgbe_phy_xaui:
db018963
JK		 269 ecmd->supported |= SUPPORTED_FIBRE;
270 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 271 ecmd->port = PORT_NONE;
272 break;
273 case ixgbe_phy_unknown:
274 case ixgbe_phy_generic:
275 case ixgbe_phy_sfp_unsupported:
276 default:
db018963
JK		 277 ecmd->supported |= SUPPORTED_FIBRE;
278 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 279 ecmd->port = PORT_OTHER;
280 break;
281 }
282
c44ade9e 283 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 284 if (link_up) {
1b1c0a48
AS		 285 switch (link_speed) {
286 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 287 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48 288 break;
454adb00
MR		 289 case IXGBE_LINK_SPEED_2_5GB_FULL:
290 ethtool_cmd_speed_set(ecmd, SPEED_2500);
291 break;
1b1c0a48 292 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 293 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 294 break;
295 case IXGBE_LINK_SPEED_100_FULL:
70739497 296 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 297 break;
298 default:
299 break;
300 }
9a799d71
AK		 301 ecmd->duplex = DUPLEX_FULL;
302 } else {
537fae01
JP		 303 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
304 ecmd->duplex = DUPLEX_UNKNOWN;
9a799d71
AK		 305 }
306
9a799d71
AK		 307 return 0;
308}
309
310static int ixgbe_set_settings(struct net_device *netdev,
e7cf745b 311 struct ethtool_cmd *ecmd)
9a799d71
AK		 312{
313 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 314 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 315 u32 advertised, old;
74766013 316 s32 err = 0;
9a799d71 317
74766013 318 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 319 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 320 /*
321 * this function does not support duplex forcing, but can
322 * limit the advertising of the adapter to the specified speed
323 */
abcc80d2
ET		 324 if (ecmd->advertising & ~ecmd->supported)
325 return -EINVAL;
326
ed33ff66
ET		 327 /* only allow one speed at a time if no autoneg */
328 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
329 if (ecmd->advertising ==
330 (ADVERTISED_10000baseT_Full |
331 ADVERTISED_1000baseT_Full))
332 return -EINVAL;
333 }
334
0befdb3e
JB		 335 old = hw->phy.autoneg_advertised;
336 advertised = 0;
337 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
338 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
339
340 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
341 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
342
2b642ca5
ET		 343 if (ecmd->advertising & ADVERTISED_100baseT_Full)
344 advertised |= IXGBE_LINK_SPEED_100_FULL;
345
0befdb3e 346 if (old == advertised)
74766013 347 return err;
0befdb3e 348 /* this sets the link speed and restarts auto-neg */
e3215f0a
ET		 349 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
350 usleep_range(1000, 2000);
351
74766013 352 hw->mac.autotry_restart = true;
fd0326f2 353 err = hw->mac.ops.setup_link(hw, advertised, true);
0befdb3e 354 if (err) {
396e799c 355 e_info(probe, "setup link failed with code %d\n", err);
fd0326f2 356 hw->mac.ops.setup_link(hw, old, true);
0befdb3e 357 }
e3215f0a 358 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
74766013
MC		 359 } else {
360 /* in this case we currently only support 10Gb/FULL */
25db0338 361 u32 speed = ethtool_cmd_speed(ecmd);
74766013 362 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 363 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 364 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 365 return -EINVAL;
9a799d71
AK		 366 }
367
74766013 368 return err;
9a799d71
AK		 369}
370
371static void ixgbe_get_pauseparam(struct net_device *netdev,
e7cf745b 372 struct ethtool_pauseparam *pause)
9a799d71
AK		 373{
374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
375 struct ixgbe_hw *hw = &adapter->hw;
376
73d80953
DS		 377 if (ixgbe_device_supports_autoneg_fc(hw) &&
378 !hw->fc.disable_fc_autoneg)
71fd570b 379 pause->autoneg = 1;
73d80953
DS		 380 else
381 pause->autoneg = 0;
9a799d71 382
0ecc061d 383 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 384 pause->rx_pause = 1;
0ecc061d 385 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 386 pause->tx_pause = 1;
0ecc061d 387 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 388 pause->rx_pause = 1;
389 pause->tx_pause = 1;
390 }
391}
392
393static int ixgbe_set_pauseparam(struct net_device *netdev,
e7cf745b 394 struct ethtool_pauseparam *pause)
9a799d71
AK		 395{
396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
397 struct ixgbe_hw *hw = &adapter->hw;
943561d3 398 struct ixgbe_fc_info fc = hw->fc;
9a799d71 399
943561d3
AD		 400 /* 82598 does no support link flow control with DCB enabled */
401 if ((hw->mac.type == ixgbe_mac_82598EB) &&
402 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
264857b8
PWJ		 403 return -EINVAL;
404
db2adc2d
JK		 405 /* some devices do not support autoneg of link flow control */
406 if ((pause->autoneg == AUTONEG_ENABLE) &&
73d80953 407 !ixgbe_device_supports_autoneg_fc(hw))
db2adc2d
JK		 408 return -EINVAL;
409
943561d3 410 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
71fd570b 411
1c4f0ef8 412 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 413 fc.requested_mode = ixgbe_fc_full;
9a799d71 414 else if (pause->rx_pause && !pause->tx_pause)
620fa036 415 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 416 else if (!pause->rx_pause && pause->tx_pause)
620fa036 417 fc.requested_mode = ixgbe_fc_tx_pause;
9c83b070 418 else
943561d3 419 fc.requested_mode = ixgbe_fc_none;
620fa036
MC		 420
421 /* if the thing changed then we'll update and use new autoneg */
422 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
423 hw->fc = fc;
424 if (netif_running(netdev))
425 ixgbe_reinit_locked(adapter);
426 else
427 ixgbe_reset(adapter);
428 }
9a799d71
AK		 429
430 return 0;
431}
432
9a799d71
AK		 433static u32 ixgbe_get_msglevel(struct net_device *netdev)
434{
435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
436 return adapter->msg_enable;
437}
438
439static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
440{
441 struct ixgbe_adapter *adapter = netdev_priv(netdev);
442 adapter->msg_enable = data;
443}
444
445static int ixgbe_get_regs_len(struct net_device *netdev)
446{
51e409f1 447#define IXGBE_REGS_LEN 1139
9a799d71
AK		 448 return IXGBE_REGS_LEN * sizeof(u32);
449}
450
451#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
452
453static void ixgbe_get_regs(struct net_device *netdev,
e7cf745b 454 struct ethtool_regs *regs, void *p)
9a799d71
AK		 455{
456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
457 struct ixgbe_hw *hw = &adapter->hw;
458 u32 *regs_buff = p;
459 u8 i;
460
461 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
462
c4a56de8
ET		 463 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
464 hw->device_id;
9a799d71
AK		 465
466 /* General Registers */
467 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
468 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
469 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
470 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
471 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
472 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
473 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
474 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
475
476 /* NVM Register */
9a900eca 477 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9a799d71 478 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
9a900eca 479 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
9a799d71
AK		 480 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
481 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
482 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
483 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
484 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
485 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
9a900eca 486 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
9a799d71
AK		 487
488 /* Interrupt */
98c00a1c
JB		 489 /* don't read EICR because it can clear interrupt causes, instead
490 * read EICS which is a shadow but doesn't clear EICR */
491 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 492 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
493 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
494 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
495 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
496 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
497 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
498 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
499 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
500 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 501 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 502 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
503
504 /* Flow Control */
505 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
506 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
507 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
508 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
509 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 510 for (i = 0; i < 8; i++) {
511 switch (hw->mac.type) {
512 case ixgbe_mac_82598EB:
513 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
514 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
515 break;
516 case ixgbe_mac_82599EB:
80bb25e3 517 case ixgbe_mac_X540:
9a75a1ac
DS		 518 case ixgbe_mac_X550:
519 case ixgbe_mac_X550EM_x:
bd508178
AD		 520 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
521 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
522 break;
523 default:
524 break;
525 }
526 }
9a799d71
AK		 527 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
528 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
529
530 /* Receive DMA */
531 for (i = 0; i < 64; i++)
532 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
533 for (i = 0; i < 64; i++)
534 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
535 for (i = 0; i < 64; i++)
536 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
537 for (i = 0; i < 64; i++)
538 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
539 for (i = 0; i < 64; i++)
540 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
541 for (i = 0; i < 64; i++)
542 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
543 for (i = 0; i < 16; i++)
544 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
545 for (i = 0; i < 16; i++)
546 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
547 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
548 for (i = 0; i < 8; i++)
549 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
550 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
551 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
552
553 /* Receive */
554 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
555 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
556 for (i = 0; i < 16; i++)
557 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
558 for (i = 0; i < 16; i++)
559 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 560 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 561 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
562 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
563 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
564 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
565 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
566 for (i = 0; i < 8; i++)
567 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
568 for (i = 0; i < 8; i++)
569 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
570 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
571
572 /* Transmit */
573 for (i = 0; i < 32; i++)
574 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
575 for (i = 0; i < 32; i++)
576 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
577 for (i = 0; i < 32; i++)
578 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
579 for (i = 0; i < 32; i++)
580 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
581 for (i = 0; i < 32; i++)
582 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
583 for (i = 0; i < 32; i++)
584 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
585 for (i = 0; i < 32; i++)
586 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
587 for (i = 0; i < 32; i++)
588 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
589 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
590 for (i = 0; i < 16; i++)
591 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
592 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
593 for (i = 0; i < 8; i++)
594 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
595 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
596
597 /* Wake Up */
598 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
599 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
600 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
601 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
602 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
603 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
604 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
605 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 606 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 607
673ac604 608 /* DCB */
51e409f1
LP		 609 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
610 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
611
612 switch (hw->mac.type) {
613 case ixgbe_mac_82598EB:
614 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
615 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
616 for (i = 0; i < 8; i++)
617 regs_buff[833 + i] =
618 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
619 for (i = 0; i < 8; i++)
620 regs_buff[841 + i] =
621 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
622 for (i = 0; i < 8; i++)
623 regs_buff[849 + i] =
624 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
625 for (i = 0; i < 8; i++)
626 regs_buff[857 + i] =
627 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
628 break;
629 case ixgbe_mac_82599EB:
630 case ixgbe_mac_X540:
9a75a1ac
DS		 631 case ixgbe_mac_X550:
632 case ixgbe_mac_X550EM_x:
51e409f1
LP		 633 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
634 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
635 for (i = 0; i < 8; i++)
636 regs_buff[833 + i] =
637 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
638 for (i = 0; i < 8; i++)
639 regs_buff[841 + i] =
640 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
641 for (i = 0; i < 8; i++)
642 regs_buff[849 + i] =
643 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
644 for (i = 0; i < 8; i++)
645 regs_buff[857 + i] =
646 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
647 break;
648 default:
649 break;
650 }
651
9a799d71 652 for (i = 0; i < 8; i++)
51e409f1
LP		 653 regs_buff[865 + i] =
654 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
9a799d71 655 for (i = 0; i < 8; i++)
51e409f1
LP		 656 regs_buff[873 + i] =
657 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
9a799d71
AK		 658
659 /* Statistics */
660 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
661 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
662 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
663 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
664 for (i = 0; i < 8; i++)
665 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
666 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
667 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
668 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
669 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
670 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
671 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
672 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
673 for (i = 0; i < 8; i++)
674 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
675 for (i = 0; i < 8; i++)
676 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
677 for (i = 0; i < 8; i++)
678 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
679 for (i = 0; i < 8; i++)
680 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
681 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
682 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
683 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
684 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
685 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
686 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
687 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
688 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
689 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
690 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
691 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
692 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
693 for (i = 0; i < 8; i++)
694 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
695 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
696 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
697 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
698 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
699 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
700 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
701 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
702 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
703 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
704 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
705 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
706 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
707 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
708 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
709 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
710 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
711 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
712 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
713 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
714 for (i = 0; i < 16; i++)
715 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
716 for (i = 0; i < 16; i++)
717 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
718 for (i = 0; i < 16; i++)
719 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
720 for (i = 0; i < 16; i++)
721 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
722
723 /* MAC */
724 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
725 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
726 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
727 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
728 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
729 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
730 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
731 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
732 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
733 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
734 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
735 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
736 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
737 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
738 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
739 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
740 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
741 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
742 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
743 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
744 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
745 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
746 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
747 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
748 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
749 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
750 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
751 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
752 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
753 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
754 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
755 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
756 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
757
758 /* Diagnostic */
759 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
760 for (i = 0; i < 8; i++)
98c00a1c 761 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 762 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 763 for (i = 0; i < 4; i++)
764 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 765 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
766 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
767 for (i = 0; i < 8; i++)
98c00a1c 768 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 769 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 770 for (i = 0; i < 4; i++)
771 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 772 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
773 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
774 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
775 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
776 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
777 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
778 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
779 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
780 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
781 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
782 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
783 for (i = 0; i < 8; i++)
98c00a1c 784 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 785 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
786 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
787 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
788 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
789 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
790 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
791 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
792 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
793 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
217995ec
ET		 794
795 /* 82599 X540 specific registers */
796 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
51e409f1
LP		 797
798 /* 82599 X540 specific DCB registers */
799 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
800 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
801 for (i = 0; i < 4; i++)
802 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
803 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
804 /* same as RTTQCNRM */
805 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
806 /* same as RTTQCNRR */
807
808 /* X540 specific DCB registers */
809 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
810 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
9a799d71
AK		 811}
812
813static int ixgbe_get_eeprom_len(struct net_device *netdev)
814{
815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
816 return adapter->hw.eeprom.word_size * 2;
817}
818
819static int ixgbe_get_eeprom(struct net_device *netdev,
e7cf745b 820 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 821{
822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
823 struct ixgbe_hw *hw = &adapter->hw;
824 u16 *eeprom_buff;
825 int first_word, last_word, eeprom_len;
826 int ret_val = 0;
827 u16 i;
828
829 if (eeprom->len == 0)
830 return -EINVAL;
831
832 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
833
834 first_word = eeprom->offset >> 1;
835 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
836 eeprom_len = last_word - first_word + 1;
837
838 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
839 if (!eeprom_buff)
840 return -ENOMEM;
841
68c7005d
ET		 842 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
843 eeprom_buff);
9a799d71
AK		 844
845 /* Device's eeprom is always little-endian, word addressable */
846 for (i = 0; i < eeprom_len; i++)
847 le16_to_cpus(&eeprom_buff[i]);
848
849 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
850 kfree(eeprom_buff);
851
852 return ret_val;
853}
854
2fa5eef4
ET		 855static int ixgbe_set_eeprom(struct net_device *netdev,
856 struct ethtool_eeprom *eeprom, u8 *bytes)
857{
858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
859 struct ixgbe_hw *hw = &adapter->hw;
860 u16 *eeprom_buff;
861 void *ptr;
862 int max_len, first_word, last_word, ret_val = 0;
863 u16 i;
864
865 if (eeprom->len == 0)
866 return -EINVAL;
867
868 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
869 return -EINVAL;
870
871 max_len = hw->eeprom.word_size * 2;
872
873 first_word = eeprom->offset >> 1;
874 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
875 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
876 if (!eeprom_buff)
877 return -ENOMEM;
878
879 ptr = eeprom_buff;
880
881 if (eeprom->offset & 1) {
882 /*
883 * need read/modify/write of first changed EEPROM word
884 * only the second byte of the word is being modified
885 */
886 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
887 if (ret_val)
888 goto err;
889
890 ptr++;
891 }
892 if ((eeprom->offset + eeprom->len) & 1) {
893 /*
894 * need read/modify/write of last changed EEPROM word
895 * only the first byte of the word is being modified
896 */
897 ret_val = hw->eeprom.ops.read(hw, last_word,
898 &eeprom_buff[last_word - first_word]);
899 if (ret_val)
900 goto err;
901 }
902
903 /* Device's eeprom is always little-endian, word addressable */
904 for (i = 0; i < last_word - first_word + 1; i++)
905 le16_to_cpus(&eeprom_buff[i]);
906
907 memcpy(ptr, bytes, eeprom->len);
908
909 for (i = 0; i < last_word - first_word + 1; i++)
910 cpu_to_le16s(&eeprom_buff[i]);
911
912 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
913 last_word - first_word + 1,
914 eeprom_buff);
915
916 /* Update the checksum */
917 if (ret_val == 0)
918 hw->eeprom.ops.update_checksum(hw);
919
920err:
921 kfree(eeprom_buff);
922 return ret_val;
923}
924
9a799d71 925static void ixgbe_get_drvinfo(struct net_device *netdev,
e7cf745b 926 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 927{
928 struct ixgbe_adapter *adapter = netdev_priv(netdev);
15e5209f 929 u32 nvm_track_id;
9a799d71 930
612a94d6
RJ		 931 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
932 strlcpy(drvinfo->version, ixgbe_driver_version,
933 sizeof(drvinfo->version));
083fc582 934
15e5209f
ET		 935 nvm_track_id = (adapter->eeprom_verh << 16) |
936 adapter->eeprom_verl;
612a94d6 937 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
15e5209f 938 nvm_track_id);
083fc582 939
612a94d6
RJ		 940 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
941 sizeof(drvinfo->bus_info));
9a799d71
AK		 942}
943
944static void ixgbe_get_ringparam(struct net_device *netdev,
e7cf745b 945 struct ethtool_ringparam *ring)
9a799d71
AK		 946{
947 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 948 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
949 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 950
951 ring->rx_max_pending = IXGBE_MAX_RXD;
952 ring->tx_max_pending = IXGBE_MAX_TXD;
9a799d71
AK		 953 ring->rx_pending = rx_ring->count;
954 ring->tx_pending = tx_ring->count;
9a799d71
AK		 955}
956
957static int ixgbe_set_ringparam(struct net_device *netdev,
e7cf745b 958 struct ethtool_ringparam *ring)
9a799d71
AK		 959{
960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1f4702aa 961 struct ixgbe_ring *temp_ring;
759884b4 962 int i, err = 0;
c431f97e 963 u32 new_rx_count, new_tx_count;
9a799d71
AK		 964
965 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
966 return -EINVAL;
967
1f4702aa
AD		 968 new_tx_count = clamp_t(u32, ring->tx_pending,
969 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
9a799d71
AK		 970 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
971
1f4702aa
AD		 972 new_rx_count = clamp_t(u32, ring->rx_pending,
973 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
974 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
975
976 if ((new_tx_count == adapter->tx_ring_count) &&
977 (new_rx_count == adapter->rx_ring_count)) {
9a799d71
AK		 978 /* nothing to do */
979 return 0;
980 }
981
d4f80882 982 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 983 usleep_range(1000, 2000);
d4f80882 984
759884b4
AD		 985 if (!netif_running(adapter->netdev)) {
986 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 987 adapter->tx_ring[i]->count = new_tx_count;
759884b4 988 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 989 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 990 adapter->tx_ring_count = new_tx_count;
991 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 992 goto clear_reset;
759884b4
AD		 993 }
994
1f4702aa
AD		 995 /* allocate temporary buffer to store rings in */
996 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
997 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
998
999 if (!temp_ring) {
f9ed8854 1000 err = -ENOMEM;
4a0b9ca0 1001 goto clear_reset;
f9ed8854
MC		 1002 }
1003
1f4702aa
AD		 1004 ixgbe_down(adapter);
1005
1006 /*
1007 * Setup new Tx resources and free the old Tx resources in that order.
1008 * We can then assign the new resources to the rings via a memcpy.
1009 * The advantage to this approach is that we are guaranteed to still
1010 * have resources even in the case of an allocation failure.
1011 */
f9ed8854 1012 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 1013 for (i = 0; i < adapter->num_tx_queues; i++) {
1f4702aa 1014 memcpy(&temp_ring[i], adapter->tx_ring[i],
4a0b9ca0 1015 sizeof(struct ixgbe_ring));
1f4702aa
AD		 1016
1017 temp_ring[i].count = new_tx_count;
1018 err = ixgbe_setup_tx_resources(&temp_ring[i]);
9a799d71 1019 if (err) {
c431f97e
JB		 1020 while (i) {
1021 i--;
1f4702aa 1022 ixgbe_free_tx_resources(&temp_ring[i]);
c431f97e 1023 }
1f4702aa 1024 goto err_setup;
9a799d71 1025 }
9a799d71 1026 }
9a799d71 1027
1f4702aa
AD		 1028 for (i = 0; i < adapter->num_tx_queues; i++) {
1029 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1030
1031 memcpy(adapter->tx_ring[i], &temp_ring[i],
1032 sizeof(struct ixgbe_ring));
1033 }
1034
1035 adapter->tx_ring_count = new_tx_count;
d3fa4721 1036 }
9a799d71 1037
1f4702aa 1038 /* Repeat the process for the Rx rings if needed */
f9ed8854 1039 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 1040 for (i = 0; i < adapter->num_rx_queues; i++) {
1f4702aa 1041 memcpy(&temp_ring[i], adapter->rx_ring[i],
4a0b9ca0 1042 sizeof(struct ixgbe_ring));
1f4702aa
AD		 1043
1044 temp_ring[i].count = new_rx_count;
1045 err = ixgbe_setup_rx_resources(&temp_ring[i]);
9a799d71 1046 if (err) {
c431f97e
JB		 1047 while (i) {
1048 i--;
1f4702aa 1049 ixgbe_free_rx_resources(&temp_ring[i]);
c431f97e 1050 }
9a799d71
AK		 1051 goto err_setup;
1052 }
1f4702aa 1053
9a799d71 1054 }
f9ed8854 1055
1f4702aa
AD		 1056 for (i = 0; i < adapter->num_rx_queues; i++) {
1057 ixgbe_free_rx_resources(adapter->rx_ring[i]);
f9ed8854 1058
1f4702aa
AD		 1059 memcpy(adapter->rx_ring[i], &temp_ring[i],
1060 sizeof(struct ixgbe_ring));
f9ed8854
MC		 1061 }
1062
1f4702aa 1063 adapter->rx_ring_count = new_rx_count;
759884b4 1064 }
4a0b9ca0 1065
f9ed8854 1066err_setup:
1f4702aa
AD		 1067 ixgbe_up(adapter);
1068 vfree(temp_ring);
4a0b9ca0 1069clear_reset:
d4f80882 1070 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1071 return err;
1072}
1073
b9f2c044 1074static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1075{
b9f2c044 1076 switch (sset) {
da4dd0f7
PWJ		 1077 case ETH_SS_TEST:
1078 return IXGBE_TEST_LEN;
b9f2c044
JG		 1079 case ETH_SS_STATS:
1080 return IXGBE_STATS_LEN;
1081 default:
1082 return -EOPNOTSUPP;
1083 }
9a799d71
AK		 1084}
1085
1086static void ixgbe_get_ethtool_stats(struct net_device *netdev,
e7cf745b 1087 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1088{
1089 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1090 struct rtnl_link_stats64 temp;
1091 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1092 unsigned int start;
1093 struct ixgbe_ring *ring;
1094 int i, j;
29c3a050 1095 char *p = NULL;
9a799d71
AK		 1096
1097 ixgbe_update_stats(adapter);
28172739 1098 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1099 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1100 switch (ixgbe_gstrings_stats[i].type) {
1101 case NETDEV_STATS:
28172739 1102 p = (char *) net_stats +
29c3a050
AK		 1103 ixgbe_gstrings_stats[i].stat_offset;
1104 break;
1105 case IXGBE_STATS:
1106 p = (char *) adapter +
1107 ixgbe_gstrings_stats[i].stat_offset;
1108 break;
f752be9c
JH		 1109 default:
1110 data[i] = 0;
1111 continue;
29c3a050
AK		 1112 }
1113
9a799d71 1114 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
e7cf745b 1115 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71 1116 }
bd8a1b12 1117 for (j = 0; j < netdev->num_tx_queues; j++) {
de1036b1 1118 ring = adapter->tx_ring[j];
9cc00b51
JF		 1119 if (!ring) {
1120 data[i] = 0;
1121 data[i+1] = 0;
1122 i += 2;
b4640030 1123#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1124 data[i] = 0;
1125 data[i+1] = 0;
1126 data[i+2] = 0;
1127 i += 3;
1128#endif
9cc00b51
JF		 1129 continue;
1130 }
1131
de1036b1 1132 do {
57a7744e 1133 start = u64_stats_fetch_begin_irq(&ring->syncp);
de1036b1
ED		 1134 data[i] = ring->stats.packets;
1135 data[i+1] = ring->stats.bytes;
57a7744e 1136 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
de1036b1 1137 i += 2;
b4640030 1138#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1139 data[i] = ring->stats.yields;
1140 data[i+1] = ring->stats.misses;
1141 data[i+2] = ring->stats.cleaned;
1142 i += 3;
1143#endif
9a799d71 1144 }
9cc00b51 1145 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1146 ring = adapter->rx_ring[j];
9cc00b51
JF		 1147 if (!ring) {
1148 data[i] = 0;
1149 data[i+1] = 0;
1150 i += 2;
b4640030 1151#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1152 data[i] = 0;
1153 data[i+1] = 0;
1154 data[i+2] = 0;
1155 i += 3;
1156#endif
9cc00b51
JF		 1157 continue;
1158 }
1159
de1036b1 1160 do {
57a7744e 1161 start = u64_stats_fetch_begin_irq(&ring->syncp);
de1036b1
ED		 1162 data[i] = ring->stats.packets;
1163 data[i+1] = ring->stats.bytes;
57a7744e 1164 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
de1036b1 1165 i += 2;
b4640030 1166#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1167 data[i] = ring->stats.yields;
1168 data[i+1] = ring->stats.misses;
1169 data[i+2] = ring->stats.cleaned;
1170 i += 3;
1171#endif
9a799d71 1172 }
9cc00b51
JF		 1173
1174 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1175 data[i++] = adapter->stats.pxontxc[j];
1176 data[i++] = adapter->stats.pxofftxc[j];
1177 }
1178 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1179 data[i++] = adapter->stats.pxonrxc[j];
1180 data[i++] = adapter->stats.pxoffrxc[j];
2f90b865 1181 }
9a799d71
AK		 1182}
1183
1184static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
e7cf745b 1185 u8 *data)
9a799d71 1186{
c44ade9e 1187 char *p = (char *)data;
9a799d71
AK		 1188 int i;
1189
1190 switch (stringset) {
da4dd0f7 1191 case ETH_SS_TEST:
d2c47b62
JH		 1192 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1193 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1194 data += ETH_GSTRING_LEN;
1195 }
da4dd0f7 1196 break;
9a799d71
AK		 1197 case ETH_SS_STATS:
1198 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1199 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1200 ETH_GSTRING_LEN);
1201 p += ETH_GSTRING_LEN;
1202 }
9cc00b51 1203 for (i = 0; i < netdev->num_tx_queues; i++) {
9a799d71
AK		 1204 sprintf(p, "tx_queue_%u_packets", i);
1205 p += ETH_GSTRING_LEN;
1206 sprintf(p, "tx_queue_%u_bytes", i);
1207 p += ETH_GSTRING_LEN;
b4640030
JK		 1208#ifdef BP_EXTENDED_STATS
1209 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
7e15b90f 1210 p += ETH_GSTRING_LEN;
b4640030 1211 sprintf(p, "tx_queue_%u_bp_misses", i);
7e15b90f 1212 p += ETH_GSTRING_LEN;
b4640030 1213 sprintf(p, "tx_queue_%u_bp_cleaned", i);
7e15b90f 1214 p += ETH_GSTRING_LEN;
b4640030 1215#endif /* BP_EXTENDED_STATS */
9a799d71 1216 }
9cc00b51 1217 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
9a799d71
AK		 1218 sprintf(p, "rx_queue_%u_packets", i);
1219 p += ETH_GSTRING_LEN;
1220 sprintf(p, "rx_queue_%u_bytes", i);
1221 p += ETH_GSTRING_LEN;
b4640030
JK		 1222#ifdef BP_EXTENDED_STATS
1223 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
7e15b90f 1224 p += ETH_GSTRING_LEN;
b4640030 1225 sprintf(p, "rx_queue_%u_bp_misses", i);
7e15b90f 1226 p += ETH_GSTRING_LEN;
b4640030 1227 sprintf(p, "rx_queue_%u_bp_cleaned", i);
7e15b90f 1228 p += ETH_GSTRING_LEN;
b4640030 1229#endif /* BP_EXTENDED_STATS */
9a799d71 1230 }
9cc00b51
JF		 1231 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1232 sprintf(p, "tx_pb_%u_pxon", i);
1233 p += ETH_GSTRING_LEN;
1234 sprintf(p, "tx_pb_%u_pxoff", i);
1235 p += ETH_GSTRING_LEN;
1236 }
1237 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1238 sprintf(p, "rx_pb_%u_pxon", i);
1239 p += ETH_GSTRING_LEN;
1240 sprintf(p, "rx_pb_%u_pxoff", i);
1241 p += ETH_GSTRING_LEN;
2f90b865 1242 }
b4617240 1243 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1244 break;
1245 }
1246}
1247
da4dd0f7
PWJ		 1248static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1249{
1250 struct ixgbe_hw *hw = &adapter->hw;
1251 bool link_up;
1252 u32 link_speed = 0;
0edd2bdf
MR		 1253
1254 if (ixgbe_removed(hw->hw_addr)) {
1255 *data = 1;
1256 return 1;
1257 }
da4dd0f7
PWJ		 1258 *data = 0;
1259
1260 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1261 if (link_up)
1262 return *data;
1263 else
1264 *data = 1;
1265 return *data;
1266}
1267
1268/* ethtool register test data */
1269struct ixgbe_reg_test {
1270 u16 reg;
1271 u8 array_len;
1272 u8 test_type;
1273 u32 mask;
1274 u32 write;
1275};
1276
1277/* In the hardware, registers are laid out either singly, in arrays
1278 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1279 * most tests take place on arrays or single registers (handled
1280 * as a single-element array) and special-case the tables.
1281 * Table tests are always pattern tests.
1282 *
1283 * We also make provision for some required setup steps by specifying
1284 * registers to be written without any read-back testing.
1285 */
1286
1287#define PATTERN_TEST 1
1288#define SET_READ_TEST 2
1289#define WRITE_NO_TEST 3
1290#define TABLE32_TEST 4
1291#define TABLE64_TEST_LO 5
1292#define TABLE64_TEST_HI 6
1293
1294/* default 82599 register test */
66744500 1295static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1296 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1297 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1298 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1299 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1300 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1301 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1302 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1303 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1304 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1305 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1306 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1307 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1308 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1309 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1310 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1311 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1312 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1313 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1314 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
ca8dfe25 1315 { .reg = 0 }
da4dd0f7
PWJ		 1316};
1317
1318/* default 82598 register test */
66744500 1319static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1320 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1321 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1322 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1323 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1324 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1325 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1326 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1327 /* Enable all four RX queues before testing. */
1328 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1329 /* RDH is read-only for 82598, only test RDT. */
1330 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1331 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1332 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1333 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1334 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1335 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1336 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1337 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1338 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1339 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1340 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1341 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1342 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
ca8dfe25 1343 { .reg = 0 }
da4dd0f7
PWJ		 1344};
1345
95a46011
ET		 1346static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1347 u32 mask, u32 write)
1348{
1349 u32 pat, val, before;
1350 static const u32 test_pattern[] = {
1351 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1352
b0483c8f
MR		 1353 if (ixgbe_removed(adapter->hw.hw_addr)) {
1354 *data = 1;
4e833c59 1355 return true;
b0483c8f 1356 }
95a46011 1357 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
49bde319
MR		 1358 before = ixgbe_read_reg(&adapter->hw, reg);
1359 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1360 val = ixgbe_read_reg(&adapter->hw, reg);
95a46011 1361 if (val != (test_pattern[pat] & write & mask)) {
6ec1b71f 1362 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
95a46011
ET		 1363 reg, val, (test_pattern[pat] & write & mask));
1364 *data = reg;
49bde319
MR		 1365 ixgbe_write_reg(&adapter->hw, reg, before);
1366 return true;
95a46011 1367 }
49bde319 1368 ixgbe_write_reg(&adapter->hw, reg, before);
95a46011 1369 }
49bde319 1370 return false;
da4dd0f7
PWJ		 1371}
1372
95a46011
ET		 1373static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1374 u32 mask, u32 write)
1375{
1376 u32 val, before;
49bde319 1377
b0483c8f
MR		 1378 if (ixgbe_removed(adapter->hw.hw_addr)) {
1379 *data = 1;
4e833c59 1380 return true;
b0483c8f 1381 }
49bde319
MR		 1382 before = ixgbe_read_reg(&adapter->hw, reg);
1383 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1384 val = ixgbe_read_reg(&adapter->hw, reg);
95a46011 1385 if ((write & mask) != (val & mask)) {
6ec1b71f
JK		 1386 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1387 reg, (val & mask), (write & mask));
95a46011 1388 *data = reg;
49bde319
MR		 1389 ixgbe_write_reg(&adapter->hw, reg, before);
1390 return true;
95a46011 1391 }
49bde319
MR		 1392 ixgbe_write_reg(&adapter->hw, reg, before);
1393 return false;
da4dd0f7
PWJ		 1394}
1395
1396static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1397{
66744500 1398 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1399 u32 value, before, after;
1400 u32 i, toggle;
1401
b0483c8f
MR		 1402 if (ixgbe_removed(adapter->hw.hw_addr)) {
1403 e_err(drv, "Adapter removed - register test blocked\n");
1404 *data = 1;
1405 return 1;
1406 }
bd508178
AD		 1407 switch (adapter->hw.mac.type) {
1408 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1409 toggle = 0x7FFFF3FF;
1410 test = reg_test_82598;
bd508178
AD		 1411 break;
1412 case ixgbe_mac_82599EB:
b93a2226 1413 case ixgbe_mac_X540:
9a75a1ac
DS		 1414 case ixgbe_mac_X550:
1415 case ixgbe_mac_X550EM_x:
bd508178
AD		 1416 toggle = 0x7FFFF30F;
1417 test = reg_test_82599;
1418 break;
1419 default:
1420 *data = 1;
1421 return 1;
da4dd0f7
PWJ		 1422 }
1423
1424 /*
1425 * Because the status register is such a special case,
1426 * we handle it separately from the rest of the register
1427 * tests. Some bits are read-only, some toggle, and some
1428 * are writeable on newer MACs.
1429 */
49bde319
MR		 1430 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1431 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1432 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1433 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
da4dd0f7 1434 if (value != after) {
6ec1b71f
JK		 1435 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1436 after, value);
da4dd0f7
PWJ		 1437 *data = 1;
1438 return 1;
1439 }
1440 /* restore previous status */
49bde319 1441 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
da4dd0f7
PWJ		 1442
1443 /*
1444 * Perform the remainder of the register test, looping through
1445 * the test table until we either fail or reach the null entry.
1446 */
1447 while (test->reg) {
1448 for (i = 0; i < test->array_len; i++) {
49bde319
MR		 1449 bool b = false;
1450
da4dd0f7
PWJ		 1451 switch (test->test_type) {
1452 case PATTERN_TEST:
49bde319
MR		 1453 b = reg_pattern_test(adapter, data,
1454 test->reg + (i * 0x40),
1455 test->mask,
1456 test->write);
da4dd0f7
PWJ		 1457 break;
1458 case SET_READ_TEST:
49bde319
MR		 1459 b = reg_set_and_check(adapter, data,
1460 test->reg + (i * 0x40),
1461 test->mask,
1462 test->write);
da4dd0f7
PWJ		 1463 break;
1464 case WRITE_NO_TEST:
49bde319
MR		 1465 ixgbe_write_reg(&adapter->hw,
1466 test->reg + (i * 0x40),
1467 test->write);
da4dd0f7
PWJ		 1468 break;
1469 case TABLE32_TEST:
49bde319
MR		 1470 b = reg_pattern_test(adapter, data,
1471 test->reg + (i * 4),
1472 test->mask,
1473 test->write);
da4dd0f7
PWJ		 1474 break;
1475 case TABLE64_TEST_LO:
49bde319
MR		 1476 b = reg_pattern_test(adapter, data,
1477 test->reg + (i * 8),
1478 test->mask,
1479 test->write);
da4dd0f7
PWJ		 1480 break;
1481 case TABLE64_TEST_HI:
49bde319
MR		 1482 b = reg_pattern_test(adapter, data,
1483 (test->reg + 4) + (i * 8),
1484 test->mask,
1485 test->write);
da4dd0f7
PWJ		 1486 break;
1487 }
49bde319
MR		 1488 if (b)
1489 return 1;
da4dd0f7
PWJ		 1490 }
1491 test++;
1492 }
1493
1494 *data = 0;
1495 return 0;
1496}
1497
1498static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1499{
1500 struct ixgbe_hw *hw = &adapter->hw;
1501 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1502 *data = 1;
1503 else
1504 *data = 0;
1505 return *data;
1506}
1507
1508static irqreturn_t ixgbe_test_intr(int irq, void *data)
1509{
1510 struct net_device *netdev = (struct net_device *) data;
1511 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1512
1513 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1514
1515 return IRQ_HANDLED;
1516}
1517
1518static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1519{
1520 struct net_device *netdev = adapter->netdev;
1521 u32 mask, i = 0, shared_int = true;
1522 u32 irq = adapter->pdev->irq;
1523
1524 *data = 0;
1525
1526 /* Hook up test interrupt handler just for this test */
1527 if (adapter->msix_entries) {
1528 /* NOTE: we don't test MSI-X interrupts here, yet */
1529 return 0;
1530 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1531 shared_int = false;
a0607fd3 1532 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1533 netdev)) {
1534 *data = 1;
1535 return -1;
1536 }
a0607fd3 1537 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
e7cf745b 1538 netdev->name, netdev)) {
da4dd0f7 1539 shared_int = false;
a0607fd3 1540 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
e7cf745b 1541 netdev->name, netdev)) {
da4dd0f7
PWJ		 1542 *data = 1;
1543 return -1;
1544 }
396e799c
ET		 1545 e_info(hw, "testing %s interrupt\n", shared_int ?
1546 "shared" : "unshared");
da4dd0f7
PWJ		 1547
1548 /* Disable all the interrupts */
1549 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1550 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1551 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1552
1553 /* Test each interrupt */
1554 for (; i < 10; i++) {
1555 /* Interrupt to test */
1556 mask = 1 << i;
1557
1558 if (!shared_int) {
1559 /*
1560 * Disable the interrupts to be reported in
1561 * the cause register and then force the same
1562 * interrupt and see if one gets posted. If
1563 * an interrupt was posted to the bus, the
1564 * test failed.
1565 */
1566 adapter->test_icr = 0;
1567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
e7cf745b 1568 ~mask & 0x00007FFF);
da4dd0f7 1569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
e7cf745b 1570 ~mask & 0x00007FFF);
945a5151 1571 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1572 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1573
1574 if (adapter->test_icr & mask) {
1575 *data = 3;
1576 break;
1577 }
1578 }
1579
1580 /*
1581 * Enable the interrupt to be reported in the cause
1582 * register and then force the same interrupt and see
1583 * if one gets posted. If an interrupt was not posted
1584 * to the bus, the test failed.
1585 */
1586 adapter->test_icr = 0;
1587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1589 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1590 usleep_range(10000, 20000);
da4dd0f7 1591
8105ecdf 1592 if (!(adapter->test_icr & mask)) {
da4dd0f7
PWJ		 1593 *data = 4;
1594 break;
1595 }
1596
1597 if (!shared_int) {
1598 /*
1599 * Disable the other interrupts to be reported in
1600 * the cause register and then force the other
1601 * interrupts and see if any get posted. If
1602 * an interrupt was posted to the bus, the
1603 * test failed.
1604 */
1605 adapter->test_icr = 0;
1606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
e7cf745b 1607 ~mask & 0x00007FFF);
da4dd0f7 1608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
e7cf745b 1609 ~mask & 0x00007FFF);
945a5151 1610 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1611 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1612
1613 if (adapter->test_icr) {
1614 *data = 5;
1615 break;
1616 }
1617 }
1618 }
1619
1620 /* Disable all the interrupts */
1621 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1622 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1623 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1624
1625 /* Unhook test interrupt handler */
1626 free_irq(irq, netdev);
1627
1628 return *data;
1629}
1630
1631static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1632{
1633 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1634 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1635 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1636 u32 reg_ctl;
da4dd0f7
PWJ		 1637
1638 /* shut down the DMA engines now so they can be reinitialized later */
1639
1640 /* first Rx */
1f9ac57c 1641 hw->mac.ops.disable_rx(hw);
2d39d576 1642 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1643
1644 /* now Tx */
84418e3b 1645 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1646 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1647 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1648
bd508178
AD		 1649 switch (hw->mac.type) {
1650 case ixgbe_mac_82599EB:
b93a2226 1651 case ixgbe_mac_X540:
9a75a1ac
DS		 1652 case ixgbe_mac_X550:
1653 case ixgbe_mac_X550EM_x:
da4dd0f7
PWJ		 1654 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1655 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1656 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1657 break;
1658 default:
1659 break;
da4dd0f7
PWJ		 1660 }
1661
1662 ixgbe_reset(adapter);
1663
b6ec895e
AD		 1664 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1665 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1666}
1667
1668static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1669{
1670 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1671 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1f9ac57c 1672 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1673 u32 rctl, reg_data;
84418e3b
AD		 1674 int ret_val;
1675 int err;
da4dd0f7
PWJ		 1676
1677 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1678 tx_ring->count = IXGBE_DEFAULT_TXD;
1679 tx_ring->queue_index = 0;
b6ec895e 1680 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1681 tx_ring->netdev = adapter->netdev;
84418e3b 1682 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
da4dd0f7 1683
b6ec895e 1684 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1685 if (err)
1686 return 1;
da4dd0f7 1687
bd508178
AD		 1688 switch (adapter->hw.mac.type) {
1689 case ixgbe_mac_82599EB:
b93a2226 1690 case ixgbe_mac_X540:
9a75a1ac
DS		 1691 case ixgbe_mac_X550:
1692 case ixgbe_mac_X550EM_x:
da4dd0f7
PWJ		 1693 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1694 reg_data |= IXGBE_DMATXCTL_TE;
1695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1696 break;
1697 default:
1698 break;
da4dd0f7 1699 }
f4ec443b 1700
84418e3b 1701 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1702
1703 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1704 rx_ring->count = IXGBE_DEFAULT_RXD;
1705 rx_ring->queue_index = 0;
b6ec895e 1706 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1707 rx_ring->netdev = adapter->netdev;
84418e3b 1708 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
84418e3b 1709
b6ec895e 1710 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1711 if (err) {
da4dd0f7
PWJ		 1712 ret_val = 4;
1713 goto err_nomem;
1714 }
1715
1f9ac57c 1716 hw->mac.ops.disable_rx(hw);
da4dd0f7 1717
84418e3b 1718 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7 1719
1f9ac57c
DS		 1720 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1721 rctl |= IXGBE_RXCTRL_DMBYPS;
da4dd0f7
PWJ		 1722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1723
1f9ac57c
DS		 1724 hw->mac.ops.enable_rx(hw);
1725
da4dd0f7
PWJ		 1726 return 0;
1727
1728err_nomem:
1729 ixgbe_free_desc_rings(adapter);
1730 return ret_val;
1731}
1732
1733static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1734{
1735 struct ixgbe_hw *hw = &adapter->hw;
1736 u32 reg_data;
1737
e7fd9253 1738
84418e3b 1739 /* Setup MAC loopback */
26b4742b 1740 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
da4dd0f7 1741 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1742 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1743
35c7f8a1 1744 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1745 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1746 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1747
9a75a1ac
DS		 1748 /* X540 and X550 needs to set the MACC.FLU bit to force link up */
1749 switch (adapter->hw.mac.type) {
1750 case ixgbe_mac_X540:
1751 case ixgbe_mac_X550:
1752 case ixgbe_mac_X550EM_x:
26b4742b
ET		 1753 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1754 reg_data |= IXGBE_MACC_FLU;
1755 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
9a75a1ac
DS		 1756 break;
1757 default:
26b4742b
ET		 1758 if (hw->mac.orig_autoc) {
1759 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1760 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1761 } else {
1762 return 10;
1763 }
1764 }
35c7f8a1 1765 IXGBE_WRITE_FLUSH(hw);
032b4325 1766 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1767
1768 /* Disable Atlas Tx lanes; re-enabled in reset path */
1769 if (hw->mac.type == ixgbe_mac_82598EB) {
1770 u8 atlas;
1771
1772 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1773 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1774 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1775
1776 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1777 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1778 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1779
1780 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1781 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1782 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1783
1784 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1785 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1786 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1787 }
1788
1789 return 0;
1790}
1791
1792static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1793{
1794 u32 reg_data;
1795
1796 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1797 reg_data &= ~IXGBE_HLREG0_LPBK;
1798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1799}
1800
1801static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
3832b26e 1802 unsigned int frame_size)
da4dd0f7
PWJ		 1803{
1804 memset(skb->data, 0xFF, frame_size);
3832b26e
AD		 1805 frame_size >>= 1;
1806 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1807 memset(&skb->data[frame_size + 10], 0xBE, 1);
1808 memset(&skb->data[frame_size + 12], 0xAF, 1);
da4dd0f7
PWJ		 1809}
1810
3832b26e
AD		 1811static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1812 unsigned int frame_size)
da4dd0f7 1813{
3832b26e
AD		 1814 unsigned char *data;
1815 bool match = true;
1816
1817 frame_size >>= 1;
1818
f800326d 1819 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
3832b26e
AD		 1820
1821 if (data[3] != 0xFF ||
1822 data[frame_size + 10] != 0xBE ||
1823 data[frame_size + 12] != 0xAF)
1824 match = false;
1825
f800326d
AD		 1826 kunmap(rx_buffer->page);
1827
3832b26e 1828 return match;
da4dd0f7
PWJ		 1829}
1830
fc77dc3c 1831static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
3832b26e
AD		 1832 struct ixgbe_ring *tx_ring,
1833 unsigned int size)
84418e3b
AD		 1834{
1835 union ixgbe_adv_rx_desc *rx_desc;
3832b26e
AD		 1836 struct ixgbe_rx_buffer *rx_buffer;
1837 struct ixgbe_tx_buffer *tx_buffer;
84418e3b
AD		 1838 u16 rx_ntc, tx_ntc, count = 0;
1839
1840 /* initialize next to clean and descriptor values */
1841 rx_ntc = rx_ring->next_to_clean;
1842 tx_ntc = tx_ring->next_to_clean;
e4f74028 1843 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b 1844
3832b26e 1845 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
84418e3b 1846 /* check Rx buffer */
3832b26e 1847 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
84418e3b 1848
f800326d
AD		 1849 /* sync Rx buffer for CPU read */
1850 dma_sync_single_for_cpu(rx_ring->dev,
1851 rx_buffer->dma,
1852 ixgbe_rx_bufsz(rx_ring),
1853 DMA_FROM_DEVICE);
84418e3b
AD		 1854
1855 /* verify contents of skb */
3832b26e 1856 if (ixgbe_check_lbtest_frame(rx_buffer, size))
84418e3b
AD		 1857 count++;
1858
f800326d
AD		 1859 /* sync Rx buffer for device write */
1860 dma_sync_single_for_device(rx_ring->dev,
1861 rx_buffer->dma,
1862 ixgbe_rx_bufsz(rx_ring),
1863 DMA_FROM_DEVICE);
1864
84418e3b 1865 /* unmap buffer on Tx side */
3832b26e
AD		 1866 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1867 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
84418e3b
AD		 1868
1869 /* increment Rx/Tx next to clean counters */
1870 rx_ntc++;
1871 if (rx_ntc == rx_ring->count)
1872 rx_ntc = 0;
1873 tx_ntc++;
1874 if (tx_ntc == tx_ring->count)
1875 tx_ntc = 0;
1876
1877 /* fetch next descriptor */
e4f74028 1878 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b
AD		 1879 }
1880
dad8a3b3
JF		 1881 netdev_tx_reset_queue(txring_txq(tx_ring));
1882
84418e3b 1883 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1884 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1885 rx_ring->next_to_clean = rx_ntc;
1886 tx_ring->next_to_clean = tx_ntc;
1887
1888 return count;
1889}
1890
da4dd0f7
PWJ		 1891static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1892{
1893 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1894 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1895 int i, j, lc, good_cnt, ret_val = 0;
1896 unsigned int size = 1024;
1897 netdev_tx_t tx_ret_val;
1898 struct sk_buff *skb;
91ffdc84
ET		 1899 u32 flags_orig = adapter->flags;
1900
1901 /* DCB can modify the frames on Tx */
1902 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
84418e3b
AD		 1903
1904 /* allocate test skb */
1905 skb = alloc_skb(size, GFP_KERNEL);
1906 if (!skb)
1907 return 11;
da4dd0f7 1908
84418e3b
AD		 1909 /* place data into test skb */
1910 ixgbe_create_lbtest_frame(skb, size);
1911 skb_put(skb, size);
da4dd0f7
PWJ		 1912
1913 /*
1914 * Calculate the loop count based on the largest descriptor ring
1915 * The idea is to wrap the largest ring a number of times using 64
1916 * send/receive pairs during each loop
1917 */
1918
1919 if (rx_ring->count <= tx_ring->count)
1920 lc = ((tx_ring->count / 64) * 2) + 1;
1921 else
1922 lc = ((rx_ring->count / 64) * 2) + 1;
1923
da4dd0f7 1924 for (j = 0; j <= lc; j++) {
84418e3b 1925 /* reset count of good packets */
da4dd0f7 1926 good_cnt = 0;
84418e3b
AD		 1927
1928 /* place 64 packets on the transmit queue*/
1929 for (i = 0; i < 64; i++) {
1930 skb_get(skb);
1931 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1932 adapter,
1933 tx_ring);
1934 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1935 good_cnt++;
84418e3b
AD		 1936 }
1937
da4dd0f7 1938 if (good_cnt != 64) {
84418e3b 1939 ret_val = 12;
da4dd0f7
PWJ		 1940 break;
1941 }
84418e3b
AD		 1942
1943 /* allow 200 milliseconds for packets to go from Tx to Rx */
1944 msleep(200);
1945
fc77dc3c 1946 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1947 if (good_cnt != 64) {
1948 ret_val = 13;
da4dd0f7
PWJ		 1949 break;
1950 }
1951 }
1952
84418e3b
AD		 1953 /* free the original skb */
1954 kfree_skb(skb);
91ffdc84 1955 adapter->flags = flags_orig;
84418e3b 1956
da4dd0f7
PWJ		 1957 return ret_val;
1958}
1959
1960static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1961{
1962 *data = ixgbe_setup_desc_rings(adapter);
1963 if (*data)
1964 goto out;
1965 *data = ixgbe_setup_loopback_test(adapter);
1966 if (*data)
1967 goto err_loopback;
1968 *data = ixgbe_run_loopback_test(adapter);
1969 ixgbe_loopback_cleanup(adapter);
1970
1971err_loopback:
1972 ixgbe_free_desc_rings(adapter);
1973out:
1974 return *data;
1975}
1976
1977static void ixgbe_diag_test(struct net_device *netdev,
e7cf745b 1978 struct ethtool_test *eth_test, u64 *data)
da4dd0f7
PWJ		 1979{
1980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1981 bool if_running = netif_running(netdev);
1982
b0483c8f
MR		 1983 if (ixgbe_removed(adapter->hw.hw_addr)) {
1984 e_err(hw, "Adapter removed - test blocked\n");
1985 data[0] = 1;
1986 data[1] = 1;
1987 data[2] = 1;
1988 data[3] = 1;
0edd2bdf 1989 data[4] = 1;
b0483c8f
MR		 1990 eth_test->flags |= ETH_TEST_FL_FAILED;
1991 return;
1992 }
da4dd0f7
PWJ		 1993 set_bit(__IXGBE_TESTING, &adapter->state);
1994 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
4ec375b1
ET		 1995 struct ixgbe_hw *hw = &adapter->hw;
1996
e7d481a6
GR		 1997 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1998 int i;
1999 for (i = 0; i < adapter->num_vfs; i++) {
2000 if (adapter->vfinfo[i].clear_to_send) {
6ec1b71f 2001 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
e7d481a6
GR		 2002 data[0] = 1;
2003 data[1] = 1;
2004 data[2] = 1;
2005 data[3] = 1;
0edd2bdf 2006 data[4] = 1;
e7d481a6
GR		 2007 eth_test->flags |= ETH_TEST_FL_FAILED;
2008 clear_bit(__IXGBE_TESTING,
2009 &adapter->state);
2010 goto skip_ol_tests;
2011 }
2012 }
2013 }
2014
dfcc4615
JK		 2015 /* Offline tests */
2016 e_info(hw, "offline testing starting\n");
2017
dfcc4615
JK		 2018 /* Link test performed before hardware reset so autoneg doesn't
2019 * interfere with test result
2020 */
2021 if (ixgbe_link_test(adapter, &data[4]))
2022 eth_test->flags |= ETH_TEST_FL_FAILED;
2023
4ec375b1
ET		 2024 if (if_running)
2025 /* indicate we're in test mode */
2026 dev_close(netdev);
2027 else
2028 ixgbe_reset(adapter);
2029
396e799c 2030 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 2031 if (ixgbe_reg_test(adapter, &data[0]))
2032 eth_test->flags |= ETH_TEST_FL_FAILED;
2033
2034 ixgbe_reset(adapter);
396e799c 2035 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 2036 if (ixgbe_eeprom_test(adapter, &data[1]))
2037 eth_test->flags |= ETH_TEST_FL_FAILED;
2038
2039 ixgbe_reset(adapter);
396e799c 2040 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 2041 if (ixgbe_intr_test(adapter, &data[2]))
2042 eth_test->flags |= ETH_TEST_FL_FAILED;
2043
bdbec4b8
GR		 2044 /* If SRIOV or VMDq is enabled then skip MAC
2045 * loopback diagnostic. */
2046 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2047 IXGBE_FLAG_VMDQ_ENABLED)) {
6ec1b71f 2048 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
bdbec4b8
GR		 2049 data[3] = 0;
2050 goto skip_loopback;
2051 }
2052
da4dd0f7 2053 ixgbe_reset(adapter);
396e799c 2054 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 2055 if (ixgbe_loopback_test(adapter, &data[3]))
2056 eth_test->flags |= ETH_TEST_FL_FAILED;
2057
bdbec4b8 2058skip_loopback:
da4dd0f7
PWJ		 2059 ixgbe_reset(adapter);
2060
dfcc4615 2061 /* clear testing bit and return adapter to previous state */
da4dd0f7
PWJ		 2062 clear_bit(__IXGBE_TESTING, &adapter->state);
2063 if (if_running)
2064 dev_open(netdev);
4ec375b1
ET		 2065 else if (hw->mac.ops.disable_tx_laser)
2066 hw->mac.ops.disable_tx_laser(hw);
da4dd0f7 2067 } else {
396e799c 2068 e_info(hw, "online testing starting\n");
dfcc4615 2069
da4dd0f7
PWJ		 2070 /* Online tests */
2071 if (ixgbe_link_test(adapter, &data[4]))
2072 eth_test->flags |= ETH_TEST_FL_FAILED;
2073
dfcc4615 2074 /* Offline tests aren't run; pass by default */
da4dd0f7
PWJ		 2075 data[0] = 0;
2076 data[1] = 0;
2077 data[2] = 0;
2078 data[3] = 0;
2079
2080 clear_bit(__IXGBE_TESTING, &adapter->state);
2081 }
dfcc4615 2082
e7d481a6 2083skip_ol_tests:
da4dd0f7
PWJ		 2084 msleep_interruptible(4 * 1000);
2085}
9a799d71 2086
d6c519e1 2087static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
e7cf745b 2088 struct ethtool_wolinfo *wol)
d6c519e1
AD		 2089{
2090 struct ixgbe_hw *hw = &adapter->hw;
8e2813f5 2091 int retval = 0;
c23f5b6b 2092
8e2813f5
JK		 2093 /* WOL not supported for all devices */
2094 if (!ixgbe_wol_supported(adapter, hw->device_id,
2095 hw->subsystem_device_id)) {
2096 retval = 1;
d6c519e1 2097 wol->supported = 0;
d6c519e1
AD		 2098 }
2099
2100 return retval;
2101}
2102
9a799d71 2103static void ixgbe_get_wol(struct net_device *netdev,
e7cf745b 2104 struct ethtool_wolinfo *wol)
9a799d71 2105{
e63d9762
PW		 2106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2107
2108 wol->supported = WAKE_UCAST | WAKE_MCAST |
e7cf745b 2109 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 2110 wol->wolopts = 0;
2111
d6c519e1
AD		 2112 if (ixgbe_wol_exclusion(adapter, wol) ||
2113 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 2114 return;
2115
2116 if (adapter->wol & IXGBE_WUFC_EX)
2117 wol->wolopts |= WAKE_UCAST;
2118 if (adapter->wol & IXGBE_WUFC_MC)
2119 wol->wolopts |= WAKE_MCAST;
2120 if (adapter->wol & IXGBE_WUFC_BC)
2121 wol->wolopts |= WAKE_BCAST;
2122 if (adapter->wol & IXGBE_WUFC_MAG)
2123 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 2124}
2125
e63d9762
PW		 2126static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2127{
2128 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2129
2130 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2131 return -EOPNOTSUPP;
2132
d6c519e1
AD		 2133 if (ixgbe_wol_exclusion(adapter, wol))
2134 return wol->wolopts ? -EOPNOTSUPP : 0;
2135
e63d9762
PW		 2136 adapter->wol = 0;
2137
2138 if (wol->wolopts & WAKE_UCAST)
2139 adapter->wol |= IXGBE_WUFC_EX;
2140 if (wol->wolopts & WAKE_MCAST)
2141 adapter->wol |= IXGBE_WUFC_MC;
2142 if (wol->wolopts & WAKE_BCAST)
2143 adapter->wol |= IXGBE_WUFC_BC;
2144 if (wol->wolopts & WAKE_MAGIC)
2145 adapter->wol |= IXGBE_WUFC_MAG;
2146
2147 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2148
2149 return 0;
2150}
2151
9a799d71
AK		 2152static int ixgbe_nway_reset(struct net_device *netdev)
2153{
2154 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2155
d4f80882
AV		 2156 if (netif_running(netdev))
2157 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2158
2159 return 0;
2160}
2161
66e6961c
ET		 2162static int ixgbe_set_phys_id(struct net_device *netdev,
2163 enum ethtool_phys_id_state state)
9a799d71
AK		 2164{
2165 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2166 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2167
66e6961c
ET		 2168 switch (state) {
2169 case ETHTOOL_ID_ACTIVE:
2170 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2171 return 2;
9a799d71 2172
66e6961c 2173 case ETHTOOL_ID_ON:
c44ade9e 2174 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2175 break;
2176
2177 case ETHTOOL_ID_OFF:
c44ade9e 2178 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2179 break;
9a799d71 2180
66e6961c
ET		 2181 case ETHTOOL_ID_INACTIVE:
2182 /* Restore LED settings */
2183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2184 break;
2185 }
9a799d71
AK		 2186
2187 return 0;
2188}
2189
2190static int ixgbe_get_coalesce(struct net_device *netdev,
e7cf745b 2191 struct ethtool_coalesce *ec)
9a799d71
AK		 2192{
2193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2194
30efa5a3 2195 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2196 if (adapter->rx_itr_setting <= 1)
2197 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2198 else
2199 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
f7554a2b 2200
cfb3f91a 2201 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2202 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2203 return 0;
2204
f7554a2b 2205 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2206 if (adapter->tx_itr_setting <= 1)
2207 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2208 else
2209 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
f7554a2b 2210
9a799d71
AK		 2211 return 0;
2212}
2213
80fba3f4
AD		 2214/*
2215 * this function must be called before setting the new value of
2216 * rx_itr_setting
2217 */
567d2de2 2218static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
80fba3f4
AD		 2219{
2220 struct net_device *netdev = adapter->netdev;
2221
567d2de2
AD		 2222 /* nothing to do if LRO or RSC are not enabled */
2223 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2224 !(netdev->features & NETIF_F_LRO))
80fba3f4
AD		 2225 return false;
2226
567d2de2
AD		 2227 /* check the feature flag value and enable RSC if necessary */
2228 if (adapter->rx_itr_setting == 1 ||
2229 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2230 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
80fba3f4 2231 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6ec1b71f 2232 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
80fba3f4
AD		 2233 return true;
2234 }
567d2de2
AD		 2235 /* if interrupt rate is too high then disable RSC */
2236 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2237 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2238 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2239 return true;
80fba3f4
AD		 2240 }
2241 return false;
2242}
2243
9a799d71 2244static int ixgbe_set_coalesce(struct net_device *netdev,
e7cf745b 2245 struct ethtool_coalesce *ec)
9a799d71
AK		 2246{
2247 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2248 struct ixgbe_q_vector *q_vector;
30efa5a3 2249 int i;
67da097e 2250 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
ef021194 2251 bool need_reset = false;
9a799d71 2252
67da097e
ET		 2253 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2254 /* reject Tx specific changes in case of mixed RxTx vectors */
2255 if (ec->tx_coalesce_usecs)
2256 return -EINVAL;
2257 tx_itr_prev = adapter->rx_itr_setting;
2258 } else {
2259 tx_itr_prev = adapter->tx_itr_setting;
2260 }
f7554a2b 2261
d5bf4f67
ET		 2262 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2263 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2264 return -EINVAL;
30efa5a3 2265
d5bf4f67
ET		 2266 if (ec->rx_coalesce_usecs > 1)
2267 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2268 else
2269 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
f7554a2b 2270
d5bf4f67
ET		 2271 if (adapter->rx_itr_setting == 1)
2272 rx_itr_param = IXGBE_20K_ITR;
2273 else
2274 rx_itr_param = adapter->rx_itr_setting;
f7554a2b 2275
d5bf4f67
ET		 2276 if (ec->tx_coalesce_usecs > 1)
2277 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2278 else
2279 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
f7554a2b 2280
d5bf4f67 2281 if (adapter->tx_itr_setting == 1)
8ac34f10 2282 tx_itr_param = IXGBE_12K_ITR;
d5bf4f67
ET		 2283 else
2284 tx_itr_param = adapter->tx_itr_setting;
f7554a2b 2285
67da097e
ET		 2286 /* mixed Rx/Tx */
2287 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2288 adapter->tx_itr_setting = adapter->rx_itr_setting;
2289
67da097e 2290 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2e010381 2291 if ((adapter->tx_itr_setting != 1) &&
67da097e
ET		 2292 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2293 if ((tx_itr_prev == 1) ||
2e010381 2294 (tx_itr_prev >= IXGBE_100K_ITR))
67da097e
ET		 2295 need_reset = true;
2296 } else {
2e010381 2297 if ((tx_itr_prev != 1) &&
67da097e
ET		 2298 (tx_itr_prev < IXGBE_100K_ITR))
2299 need_reset = true;
2300 }
ffefa9f6 2301
567d2de2 2302 /* check the old value and enable RSC if necessary */
67da097e 2303 need_reset |= ixgbe_update_rsc(adapter);
567d2de2 2304
49c7ffbe 2305 for (i = 0; i < adapter->num_q_vectors; i++) {
d5bf4f67 2306 q_vector = adapter->q_vector[i];
d5bf4f67
ET		 2307 if (q_vector->tx.count && !q_vector->rx.count)
2308 /* tx only */
2309 q_vector->itr = tx_itr_param;
2310 else
2311 /* rx only or mixed */
2312 q_vector->itr = rx_itr_param;
fe49f04a 2313 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2314 }
2315
ef021194
JB		 2316 /*
2317 * do reset here at the end to make sure EITR==0 case is handled
2318 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2319 * also locks in RSC enable/disable which requires reset
2320 */
c988ee82
ET		 2321 if (need_reset)
2322 ixgbe_do_reset(netdev);
ef021194 2323
9a799d71
AK		 2324 return 0;
2325}
2326
3e05334f
AD		 2327static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2328 struct ethtool_rxnfc *cmd)
2329{
2330 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2331 struct ethtool_rx_flow_spec *fsp =
2332 (struct ethtool_rx_flow_spec *)&cmd->fs;
b67bfe0d 2333 struct hlist_node *node2;
3e05334f
AD		 2334 struct ixgbe_fdir_filter *rule = NULL;
2335
2336 /* report total rule count */
2337 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2338
b67bfe0d 2339 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2340 &adapter->fdir_filter_list, fdir_node) {
2341 if (fsp->location <= rule->sw_idx)
2342 break;
2343 }
2344
2345 if (!rule || fsp->location != rule->sw_idx)
2346 return -EINVAL;
2347
2348 /* fill out the flow spec entry */
2349
2350 /* set flow type field */
2351 switch (rule->filter.formatted.flow_type) {
2352 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2353 fsp->flow_type = TCP_V4_FLOW;
2354 break;
2355 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2356 fsp->flow_type = UDP_V4_FLOW;
2357 break;
2358 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2359 fsp->flow_type = SCTP_V4_FLOW;
2360 break;
2361 case IXGBE_ATR_FLOW_TYPE_IPV4:
2362 fsp->flow_type = IP_USER_FLOW;
2363 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2364 fsp->h_u.usr_ip4_spec.proto = 0;
2365 fsp->m_u.usr_ip4_spec.proto = 0;
2366 break;
2367 default:
2368 return -EINVAL;
2369 }
2370
2371 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2372 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2373 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2374 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2375 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2376 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2377 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2378 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2379 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2380 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2381 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2382 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2383 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2384 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2385 fsp->flow_type |= FLOW_EXT;
2386
2387 /* record action */
2388 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2389 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2390 else
2391 fsp->ring_cookie = rule->action;
2392
2393 return 0;
2394}
2395
2396static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2397 struct ethtool_rxnfc *cmd,
2398 u32 *rule_locs)
2399{
b67bfe0d 2400 struct hlist_node *node2;
3e05334f
AD		 2401 struct ixgbe_fdir_filter *rule;
2402 int cnt = 0;
2403
2404 /* report total rule count */
2405 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2406
b67bfe0d 2407 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2408 &adapter->fdir_filter_list, fdir_node) {
2409 if (cnt == cmd->rule_cnt)
2410 return -EMSGSIZE;
2411 rule_locs[cnt] = rule->sw_idx;
2412 cnt++;
2413 }
2414
473e64ee
BH		 2415 cmd->rule_cnt = cnt;
2416
3e05334f
AD		 2417 return 0;
2418}
2419
ef6afc0c
AD		 2420static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2421 struct ethtool_rxnfc *cmd)
2422{
2423 cmd->data = 0;
2424
ef6afc0c
AD		 2425 /* Report default options for RSS on ixgbe */
2426 switch (cmd->flow_type) {
2427 case TCP_V4_FLOW:
2428 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2429 /* fallthrough */
ef6afc0c
AD		 2430 case UDP_V4_FLOW:
2431 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2432 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2433 /* fallthrough */
ef6afc0c
AD		 2434 case SCTP_V4_FLOW:
2435 case AH_ESP_V4_FLOW:
2436 case AH_V4_FLOW:
2437 case ESP_V4_FLOW:
2438 case IPV4_FLOW:
2439 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2440 break;
2441 case TCP_V6_FLOW:
2442 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2443 /* fallthrough */
ef6afc0c
AD		 2444 case UDP_V6_FLOW:
2445 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2446 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2447 /* fallthrough */
ef6afc0c
AD		 2448 case SCTP_V6_FLOW:
2449 case AH_ESP_V6_FLOW:
2450 case AH_V6_FLOW:
2451 case ESP_V6_FLOW:
2452 case IPV6_FLOW:
2453 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2454 break;
2455 default:
2456 return -EINVAL;
2457 }
2458
2459 return 0;
2460}
2461
91cd94bf 2462static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2463 u32 *rule_locs)
91cd94bf
AD		 2464{
2465 struct ixgbe_adapter *adapter = netdev_priv(dev);
2466 int ret = -EOPNOTSUPP;
2467
2468 switch (cmd->cmd) {
2469 case ETHTOOL_GRXRINGS:
2470 cmd->data = adapter->num_rx_queues;
2471 ret = 0;
2472 break;
3e05334f
AD		 2473 case ETHTOOL_GRXCLSRLCNT:
2474 cmd->rule_cnt = adapter->fdir_filter_count;
2475 ret = 0;
2476 break;
2477 case ETHTOOL_GRXCLSRULE:
2478 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2479 break;
2480 case ETHTOOL_GRXCLSRLALL:
815c7db5 2481 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2482 break;
ef6afc0c
AD		 2483 case ETHTOOL_GRXFH:
2484 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2485 break;
91cd94bf
AD		 2486 default:
2487 break;
2488 }
2489
2490 return ret;
2491}
2492
e4911d57
AD		 2493static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2494 struct ixgbe_fdir_filter *input,
2495 u16 sw_idx)
2496{
2497 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d
SL		 2498 struct hlist_node *node2;
2499 struct ixgbe_fdir_filter *rule, *parent;
e4911d57
AD		 2500 int err = -EINVAL;
2501
2502 parent = NULL;
2503 rule = NULL;
2504
b67bfe0d 2505 hlist_for_each_entry_safe(rule, node2,
e4911d57
AD		 2506 &adapter->fdir_filter_list, fdir_node) {
2507 /* hash found, or no matching entry */
2508 if (rule->sw_idx >= sw_idx)
2509 break;
b67bfe0d 2510 parent = rule;
e4911d57
AD		 2511 }
2512
2513 /* if there is an old rule occupying our place remove it */
2514 if (rule && (rule->sw_idx == sw_idx)) {
2515 if (!input || (rule->filter.formatted.bkt_hash !=
2516 input->filter.formatted.bkt_hash)) {
2517 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2518 &rule->filter,
2519 sw_idx);
2520 }
2521
2522 hlist_del(&rule->fdir_node);
2523 kfree(rule);
2524 adapter->fdir_filter_count--;
2525 }
2526
2527 /*
2528 * If no input this was a delete, err should be 0 if a rule was
2529 * successfully found and removed from the list else -EINVAL
2530 */
2531 if (!input)
2532 return err;
2533
2534 /* initialize node and set software index */
2535 INIT_HLIST_NODE(&input->fdir_node);
2536
2537 /* add filter to the list */
2538 if (parent)
1d023284 2539 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
e4911d57
AD		 2540 else
2541 hlist_add_head(&input->fdir_node,
2542 &adapter->fdir_filter_list);
2543
2544 /* update counts */
2545 adapter->fdir_filter_count++;
2546
2547 return 0;
2548}
2549
2550static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2551 u8 *flow_type)
2552{
2553 switch (fsp->flow_type & ~FLOW_EXT) {
2554 case TCP_V4_FLOW:
2555 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2556 break;
2557 case UDP_V4_FLOW:
2558 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2559 break;
2560 case SCTP_V4_FLOW:
2561 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2562 break;
2563 case IP_USER_FLOW:
2564 switch (fsp->h_u.usr_ip4_spec.proto) {
2565 case IPPROTO_TCP:
2566 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2567 break;
2568 case IPPROTO_UDP:
2569 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2570 break;
2571 case IPPROTO_SCTP:
2572 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2573 break;
2574 case 0:
2575 if (!fsp->m_u.usr_ip4_spec.proto) {
2576 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2577 break;
2578 }
2579 default:
2580 return 0;
2581 }
2582 break;
2583 default:
2584 return 0;
2585 }
2586
2587 return 1;
2588}
2589
2590static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2591 struct ethtool_rxnfc *cmd)
2592{
2593 struct ethtool_rx_flow_spec *fsp =
2594 (struct ethtool_rx_flow_spec *)&cmd->fs;
2595 struct ixgbe_hw *hw = &adapter->hw;
2596 struct ixgbe_fdir_filter *input;
2597 union ixgbe_atr_input mask;
7aac8425 2598 u8 queue;
e4911d57
AD		 2599 int err;
2600
2601 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2602 return -EOPNOTSUPP;
2603
7aac8425
JF		 2604 /* ring_cookie is a masked into a set of queues and ixgbe pools or
2605 * we use the drop index.
e4911d57 2606 */
7aac8425
JF		 2607 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2608 queue = IXGBE_FDIR_DROP_QUEUE;
2609 } else {
2610 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2611 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2612
2613 if (!vf && (ring >= adapter->num_rx_queues))
2614 return -EINVAL;
2615 else if (vf &&
2616 ((vf > adapter->num_vfs) ||
2617 ring >= adapter->num_rx_queues_per_pool))
2618 return -EINVAL;
2619
2620 /* Map the ring onto the absolute queue index */
2621 if (!vf)
2622 queue = adapter->rx_ring[ring]->reg_idx;
2623 else
2624 queue = ((vf - 1) *
2625 adapter->num_rx_queues_per_pool) + ring;
2626 }
e4911d57
AD		 2627
2628 /* Don't allow indexes to exist outside of available space */
2629 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2630 e_err(drv, "Location out of range\n");
2631 return -EINVAL;
2632 }
2633
2634 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2635 if (!input)
2636 return -ENOMEM;
2637
2638 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2639
2640 /* set SW index */
2641 input->sw_idx = fsp->location;
2642
2643 /* record flow type */
2644 if (!ixgbe_flowspec_to_flow_type(fsp,
2645 &input->filter.formatted.flow_type)) {
2646 e_err(drv, "Unrecognized flow type\n");
2647 goto err_out;
2648 }
2649
2650 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2651 IXGBE_ATR_L4TYPE_MASK;
2652
2653 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2654 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2655
2656 /* Copy input into formatted structures */
2657 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2658 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2659 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2660 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2661 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2662 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2663 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2664 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2665
2666 if (fsp->flow_type & FLOW_EXT) {
2667 input->filter.formatted.vm_pool =
2668 (unsigned char)ntohl(fsp->h_ext.data[1]);
2669 mask.formatted.vm_pool =
2670 (unsigned char)ntohl(fsp->m_ext.data[1]);
2671 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2672 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2673 input->filter.formatted.flex_bytes =
2674 fsp->h_ext.vlan_etype;
2675 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2676 }
2677
2678 /* determine if we need to drop or route the packet */
2679 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2680 input->action = IXGBE_FDIR_DROP_QUEUE;
2681 else
2682 input->action = fsp->ring_cookie;
2683
2684 spin_lock(&adapter->fdir_perfect_lock);
2685
2686 if (hlist_empty(&adapter->fdir_filter_list)) {
2687 /* save mask and program input mask into HW */
2688 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2689 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2690 if (err) {
2691 e_err(drv, "Error writing mask\n");
2692 goto err_out_w_lock;
2693 }
2694 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2695 e_err(drv, "Only one mask supported per port\n");
2696 goto err_out_w_lock;
2697 }
2698
2699 /* apply mask and compute/store hash */
2700 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2701
2702 /* program filters to filter memory */
2703 err = ixgbe_fdir_write_perfect_filter_82599(hw,
7aac8425 2704 &input->filter, input->sw_idx, queue);
e4911d57
AD		 2705 if (err)
2706 goto err_out_w_lock;
2707
2708 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2709
2710 spin_unlock(&adapter->fdir_perfect_lock);
2711
2712 return err;
2713err_out_w_lock:
2714 spin_unlock(&adapter->fdir_perfect_lock);
2715err_out:
2716 kfree(input);
2717 return -EINVAL;
2718}
2719
2720static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2721 struct ethtool_rxnfc *cmd)
2722{
2723 struct ethtool_rx_flow_spec *fsp =
2724 (struct ethtool_rx_flow_spec *)&cmd->fs;
2725 int err;
2726
2727 spin_lock(&adapter->fdir_perfect_lock);
2728 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2729 spin_unlock(&adapter->fdir_perfect_lock);
2730
2731 return err;
2732}
2733
ef6afc0c
AD		 2734#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2735 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2736static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2737 struct ethtool_rxnfc *nfc)
2738{
2739 u32 flags2 = adapter->flags2;
2740
2741 /*
2742 * RSS does not support anything other than hashing
2743 * to queues on src and dst IPs and ports
2744 */
2745 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2746 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2747 return -EINVAL;
2748
2749 switch (nfc->flow_type) {
2750 case TCP_V4_FLOW:
2751 case TCP_V6_FLOW:
2752 if (!(nfc->data & RXH_IP_SRC) ||
2753 !(nfc->data & RXH_IP_DST) ||
2754 !(nfc->data & RXH_L4_B_0_1) ||
2755 !(nfc->data & RXH_L4_B_2_3))
2756 return -EINVAL;
2757 break;
2758 case UDP_V4_FLOW:
2759 if (!(nfc->data & RXH_IP_SRC) ||
2760 !(nfc->data & RXH_IP_DST))
2761 return -EINVAL;
2762 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2763 case 0:
2764 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2765 break;
2766 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2767 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2768 break;
2769 default:
2770 return -EINVAL;
2771 }
2772 break;
2773 case UDP_V6_FLOW:
2774 if (!(nfc->data & RXH_IP_SRC) ||
2775 !(nfc->data & RXH_IP_DST))
2776 return -EINVAL;
2777 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2778 case 0:
2779 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2780 break;
2781 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2782 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2783 break;
2784 default:
2785 return -EINVAL;
2786 }
2787 break;
2788 case AH_ESP_V4_FLOW:
2789 case AH_V4_FLOW:
2790 case ESP_V4_FLOW:
2791 case SCTP_V4_FLOW:
2792 case AH_ESP_V6_FLOW:
2793 case AH_V6_FLOW:
2794 case ESP_V6_FLOW:
2795 case SCTP_V6_FLOW:
2796 if (!(nfc->data & RXH_IP_SRC) ||
2797 !(nfc->data & RXH_IP_DST) ||
2798 (nfc->data & RXH_L4_B_0_1) ||
2799 (nfc->data & RXH_L4_B_2_3))
2800 return -EINVAL;
2801 break;
2802 default:
2803 return -EINVAL;
2804 }
2805
2806 /* if we changed something we need to update flags */
2807 if (flags2 != adapter->flags2) {
2808 struct ixgbe_hw *hw = &adapter->hw;
9a75a1ac
DS		 2809 u32 mrqc;
2810 unsigned int pf_pool = adapter->num_vfs;
2811
2812 if ((hw->mac.type >= ixgbe_mac_X550) &&
2813 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2814 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2815 else
2816 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
ef6afc0c
AD		 2817
2818 if ((flags2 & UDP_RSS_FLAGS) &&
2819 !(adapter->flags2 & UDP_RSS_FLAGS))
6ec1b71f 2820 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
ef6afc0c
AD		 2821
2822 adapter->flags2 = flags2;
2823
2824 /* Perform hash on these packet types */
2825 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2826 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2827 | IXGBE_MRQC_RSS_FIELD_IPV6
2828 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2829
2830 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2831 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2832
2833 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2834 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2835
2836 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2837 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2838
9a75a1ac
DS		 2839 if ((hw->mac.type >= ixgbe_mac_X550) &&
2840 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2841 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
2842 else
2843 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
ef6afc0c
AD		 2844 }
2845
2846 return 0;
2847}
2848
e4911d57
AD		 2849static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2850{
2851 struct ixgbe_adapter *adapter = netdev_priv(dev);
2852 int ret = -EOPNOTSUPP;
2853
2854 switch (cmd->cmd) {
2855 case ETHTOOL_SRXCLSRLINS:
2856 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2857 break;
2858 case ETHTOOL_SRXCLSRLDEL:
2859 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2860 break;
ef6afc0c
AD		 2861 case ETHTOOL_SRXFH:
2862 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2863 break;
e4911d57
AD		 2864 default:
2865 break;
2866 }
2867
2868 return ret;
2869}
2870
1c7cf078
TB		 2871static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
2872{
2873 if (adapter->hw.mac.type < ixgbe_mac_X550)
2874 return 16;
2875 else
2876 return 64;
2877}
2878
7f276efb
VZ		 2879static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
2880{
2881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2882
2883 return sizeof(adapter->rss_key);
2884}
2885
2886static u32 ixgbe_rss_indir_size(struct net_device *netdev)
2887{
2888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2889
2890 return ixgbe_rss_indir_tbl_entries(adapter);
2891}
2892
2893static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
2894{
2895 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
2896
2897 for (i = 0; i < reta_size; i++)
2898 indir[i] = adapter->rss_indir_tbl[i];
2899}
2900
2901static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2902 u8 *hfunc)
2903{
2904 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2905
2906 if (hfunc)
2907 *hfunc = ETH_RSS_HASH_TOP;
2908
2909 if (indir)
2910 ixgbe_get_reta(adapter, indir);
2911
2912 if (key)
2913 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
2914
2915 return 0;
2916}
2917
1c7cf078
TB		 2918static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
2919 const u8 *key, const u8 hfunc)
2920{
2921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2922 int i;
2923 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
2924
2925 if (hfunc)
2926 return -EINVAL;
2927
2928 /* Fill out the redirection table */
2929 if (indir) {
2930 int max_queues = min_t(int, adapter->num_rx_queues,
2931 ixgbe_rss_indir_tbl_max(adapter));
2932
2933 /*Allow at least 2 queues w/ SR-IOV.*/
2934 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2935 (max_queues < 2))
2936 max_queues = 2;
2937
2938 /* Verify user input. */
2939 for (i = 0; i < reta_entries; i++)
2940 if (indir[i] >= max_queues)
2941 return -EINVAL;
2942
2943 for (i = 0; i < reta_entries; i++)
2944 adapter->rss_indir_tbl[i] = indir[i];
2945 }
2946
2947 /* Fill out the rss hash key */
2948 if (key)
2949 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
2950
2951 ixgbe_store_reta(adapter);
2952
2953 return 0;
2954}
2955
e3aac889
JK		 2956static int ixgbe_get_ts_info(struct net_device *dev,
2957 struct ethtool_ts_info *info)
2958{
2959 struct ixgbe_adapter *adapter = netdev_priv(dev);
2960
2961 switch (adapter->hw.mac.type) {
9a75a1ac
DS		 2962 case ixgbe_mac_X550:
2963 case ixgbe_mac_X550EM_x:
e3aac889
JK		 2964 case ixgbe_mac_X540:
2965 case ixgbe_mac_82599EB:
2966 info->so_timestamping =
50f8d35d
JK		 2967 SOF_TIMESTAMPING_TX_SOFTWARE |
2968 SOF_TIMESTAMPING_RX_SOFTWARE |
2969 SOF_TIMESTAMPING_SOFTWARE |
e3aac889
JK		 2970 SOF_TIMESTAMPING_TX_HARDWARE |
2971 SOF_TIMESTAMPING_RX_HARDWARE |
2972 SOF_TIMESTAMPING_RAW_HARDWARE;
2973
2974 if (adapter->ptp_clock)
2975 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2976 else
2977 info->phc_index = -1;
2978
2979 info->tx_types =
2980 (1 << HWTSTAMP_TX_OFF) |
2981 (1 << HWTSTAMP_TX_ON);
2982
2983 info->rx_filters =
2984 (1 << HWTSTAMP_FILTER_NONE) |
2985 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2986 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1cc92eb8 2987 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
e3aac889 2988 break;
e3aac889
JK		 2989 default:
2990 return ethtool_op_get_ts_info(dev, info);
e3aac889
JK		 2991 }
2992 return 0;
2993}
2994
5348c9db
AD		 2995static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2996{
2997 unsigned int max_combined;
2998 u8 tcs = netdev_get_num_tc(adapter->netdev);
2999
3000 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3001 /* We only support one q_vector without MSI-X */
3002 max_combined = 1;
3003 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3004 /* SR-IOV currently only allows one queue on the PF */
3005 max_combined = 1;
3006 } else if (tcs > 1) {
3007 /* For DCB report channels per traffic class */
3008 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3009 /* 8 TC w/ 4 queues per TC */
3010 max_combined = 4;
3011 } else if (tcs > 4) {
3012 /* 8 TC w/ 8 queues per TC */
3013 max_combined = 8;
3014 } else {
3015 /* 4 TC w/ 16 queues per TC */
3016 max_combined = 16;
3017 }
3018 } else if (adapter->atr_sample_rate) {
3019 /* support up to 64 queues with ATR */
3020 max_combined = IXGBE_MAX_FDIR_INDICES;
3021 } else {
3022 /* support up to 16 queues with RSS */
0f9b232b 3023 max_combined = ixgbe_max_rss_indices(adapter);
5348c9db
AD		 3024 }
3025
3026 return max_combined;
3027}
3028
3029static void ixgbe_get_channels(struct net_device *dev,
3030 struct ethtool_channels *ch)
3031{
3032 struct ixgbe_adapter *adapter = netdev_priv(dev);
3033
3034 /* report maximum channels */
3035 ch->max_combined = ixgbe_max_channels(adapter);
3036
3037 /* report info for other vector */
3038 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3039 ch->max_other = NON_Q_VECTORS;
3040 ch->other_count = NON_Q_VECTORS;
3041 }
3042
3043 /* record RSS queues */
3044 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3045
3046 /* nothing else to report if RSS is disabled */
3047 if (ch->combined_count == 1)
3048 return;
3049
3050 /* we do not support ATR queueing if SR-IOV is enabled */
3051 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3052 return;
3053
3054 /* same thing goes for being DCB enabled */
3055 if (netdev_get_num_tc(dev) > 1)
3056 return;
3057
3058 /* if ATR is disabled we can exit */
3059 if (!adapter->atr_sample_rate)
3060 return;
3061
3062 /* report flow director queues as maximum channels */
3063 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3064}
3065
4c696ca9
AD		 3066static int ixgbe_set_channels(struct net_device *dev,
3067 struct ethtool_channels *ch)
3068{
3069 struct ixgbe_adapter *adapter = netdev_priv(dev);
3070 unsigned int count = ch->combined_count;
0f9b232b 3071 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
4c696ca9
AD		 3072
3073 /* verify they are not requesting separate vectors */
3074 if (!count || ch->rx_count || ch->tx_count)
3075 return -EINVAL;
3076
3077 /* verify other_count has not changed */
3078 if (ch->other_count != NON_Q_VECTORS)
3079 return -EINVAL;
3080
3081 /* verify the number of channels does not exceed hardware limits */
3082 if (count > ixgbe_max_channels(adapter))
3083 return -EINVAL;
3084
3085 /* update feature limits from largest to smallest supported values */
3086 adapter->ring_feature[RING_F_FDIR].limit = count;
3087
0f9b232b
DS		 3088 /* cap RSS limit */
3089 if (count > max_rss_indices)
3090 count = max_rss_indices;
4c696ca9
AD		 3091 adapter->ring_feature[RING_F_RSS].limit = count;
3092
3093#ifdef IXGBE_FCOE
3094 /* cap FCoE limit at 8 */
3095 if (count > IXGBE_FCRETA_SIZE)
3096 count = IXGBE_FCRETA_SIZE;
3097 adapter->ring_feature[RING_F_FCOE].limit = count;
3098
3099#endif
3100 /* use setup TC to update any traffic class queue mapping */
3101 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
3102}
3103
71858acb
AG		 3104static int ixgbe_get_module_info(struct net_device *dev,
3105 struct ethtool_modinfo *modinfo)
3106{
3107 struct ixgbe_adapter *adapter = netdev_priv(dev);
3108 struct ixgbe_hw *hw = &adapter->hw;
a1e869de 3109 s32 status;
71858acb 3110 u8 sff8472_rev, addr_mode;
71858acb
AG		 3111 bool page_swap = false;
3112
71858acb
AG		 3113 /* Check whether we support SFF-8472 or not */
3114 status = hw->phy.ops.read_i2c_eeprom(hw,
3115 IXGBE_SFF_SFF_8472_COMP,
3116 &sff8472_rev);
a1e869de 3117 if (status)
a4b6fc6b 3118 return -EIO;
71858acb
AG		 3119
3120 /* addressing mode is not supported */
3121 status = hw->phy.ops.read_i2c_eeprom(hw,
3122 IXGBE_SFF_SFF_8472_SWAP,
3123 &addr_mode);
a1e869de 3124 if (status)
a4b6fc6b 3125 return -EIO;
71858acb
AG		 3126
3127 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3128 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3129 page_swap = true;
3130 }
3131
3132 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3133 /* We have a SFP, but it does not support SFF-8472 */
3134 modinfo->type = ETH_MODULE_SFF_8079;
3135 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3136 } else {
3137 /* We have a SFP which supports a revision of SFF-8472. */
3138 modinfo->type = ETH_MODULE_SFF_8472;
3139 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3140 }
3141
a4b6fc6b 3142 return 0;
71858acb
AG		 3143}
3144
3145static int ixgbe_get_module_eeprom(struct net_device *dev,
3146 struct ethtool_eeprom *ee,
3147 u8 *data)
3148{
3149 struct ixgbe_adapter *adapter = netdev_priv(dev);
3150 struct ixgbe_hw *hw = &adapter->hw;
a1e869de 3151 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
71858acb
AG		 3152 u8 databyte = 0xFF;
3153 int i = 0;
71858acb 3154
a4b6fc6b
ET		 3155 if (ee->len == 0)
3156 return -EINVAL;
71858acb 3157
31c7d2b0 3158 for (i = ee->offset; i < ee->offset + ee->len; i++) {
a4b6fc6b
ET		 3159 /* I2C reads can take long time */
3160 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3161 return -EBUSY;
71858acb 3162
a4b6fc6b 3163 if (i < ETH_MODULE_SFF_8079_LEN)
31c7d2b0 3164 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
a4b6fc6b
ET		 3165 else
3166 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3167
a1e869de 3168 if (status)
31c7d2b0 3169 return -EIO;
71858acb 3170
a4b6fc6b 3171 data[i - ee->offset] = databyte;
71858acb
AG		 3172 }
3173
31c7d2b0 3174 return 0;
71858acb
AG		 3175}
3176
b9804972 3177static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 3178 .get_settings = ixgbe_get_settings,
3179 .set_settings = ixgbe_set_settings,
3180 .get_drvinfo = ixgbe_get_drvinfo,
3181 .get_regs_len = ixgbe_get_regs_len,
3182 .get_regs = ixgbe_get_regs,
3183 .get_wol = ixgbe_get_wol,
e63d9762 3184 .set_wol = ixgbe_set_wol,
9a799d71
AK		 3185 .nway_reset = ixgbe_nway_reset,
3186 .get_link = ethtool_op_get_link,
3187 .get_eeprom_len = ixgbe_get_eeprom_len,
3188 .get_eeprom = ixgbe_get_eeprom,
2fa5eef4 3189 .set_eeprom = ixgbe_set_eeprom,
9a799d71
AK		 3190 .get_ringparam = ixgbe_get_ringparam,
3191 .set_ringparam = ixgbe_set_ringparam,
3192 .get_pauseparam = ixgbe_get_pauseparam,
3193 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 3194 .get_msglevel = ixgbe_get_msglevel,
3195 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 3196 .self_test = ixgbe_diag_test,
9a799d71 3197 .get_strings = ixgbe_get_strings,
66e6961c 3198 .set_phys_id = ixgbe_set_phys_id,
b4617240 3199 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 3200 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3201 .get_coalesce = ixgbe_get_coalesce,
3202 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 3203 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 3204 .set_rxnfc = ixgbe_set_rxnfc,
7f276efb
VZ		 3205 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3206 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3207 .get_rxfh = ixgbe_get_rxfh,
1c7cf078 3208 .set_rxfh = ixgbe_set_rxfh,
5348c9db 3209 .get_channels = ixgbe_get_channels,
4c696ca9 3210 .set_channels = ixgbe_set_channels,
e3aac889 3211 .get_ts_info = ixgbe_get_ts_info,
71858acb
AG		 3212 .get_module_info = ixgbe_get_module_info,
3213 .get_module_eeprom = ixgbe_get_module_eeprom,
9a799d71
AK		 3214};
3215
3216void ixgbe_set_ethtool_ops(struct net_device *netdev)
3217{
7ad24ea4 3218 netdev->ethtool_ops = &ixgbe_ethtool_ops;
9a799d71 3219}
Linux kernel - Deliverables
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