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ixgbe: avoid HW lockup when adapter is reset with Tx work pending
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
a6b7a407 30#include <linux/interrupt.h>
9a799d71
AK		 31#include <linux/types.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
9a799d71
AK		 34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/ethtool.h>
37#include <linux/vmalloc.h>
38#include <linux/uaccess.h>
39
40#include "ixgbe.h"
41
42
43#define IXGBE_ALL_RAR_ENTRIES 16
44
29c3a050
AK		 45enum {NETDEV_STATS, IXGBE_STATS};
46
9a799d71
AK		 47struct ixgbe_stats {
48 char stat_string[ETH_GSTRING_LEN];
29c3a050 49 int type;
9a799d71
AK		 50 int sizeof_stat;
51 int stat_offset;
52};
53
29c3a050
AK		 54#define IXGBE_STAT(m) IXGBE_STATS, \
55 sizeof(((struct ixgbe_adapter *)0)->m), \
56 offsetof(struct ixgbe_adapter, m)
57#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 58 sizeof(((struct rtnl_link_stats64 *)0)->m), \
59 offsetof(struct rtnl_link_stats64, m)
29c3a050 60
9a799d71 61static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 62 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
63 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
64 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
65 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 66 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
67 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
68 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
69 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 70 {"lsc_int", IXGBE_STAT(lsc_int)},
71 {"tx_busy", IXGBE_STAT(tx_busy)},
72 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 73 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
74 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
75 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
76 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
77 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 78 {"broadcast", IXGBE_STAT(stats.bprc)},
79 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 80 {"collisions", IXGBE_NETDEV_STAT(collisions)},
81 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
82 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
83 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 84 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
85 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 86 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
87 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 88 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 89 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
90 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
91 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
92 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
93 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
94 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 95 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
96 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
97 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
98 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 99 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
100 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
101 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
102 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 103 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 104 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
105 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 106 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 107 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
108 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
109 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
110 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 111#ifdef IXGBE_FCOE
112 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
113 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
114 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
115 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
116 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
117 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
118#endif /* IXGBE_FCOE */
9a799d71
AK		 119};
120
121#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 122 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
123 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
124 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 125#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 126#define IXGBE_PB_STATS_LEN ( \
9d2f4720 127 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 128 IXGBE_FLAG_DCB_ENABLED) ? \
129 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
130 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
131 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
132 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
133 / sizeof(u64) : 0)
134#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
135 IXGBE_PB_STATS_LEN + \
136 IXGBE_QUEUE_STATS_LEN)
9a799d71 137
da4dd0f7
PWJ		 138static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
139 "Register test (offline)", "Eeprom test (offline)",
140 "Interrupt test (offline)", "Loopback test (offline)",
141 "Link test (on/offline)"
142};
143#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
144
9a799d71 145static int ixgbe_get_settings(struct net_device *netdev,
b4617240 146 struct ethtool_cmd *ecmd)
9a799d71
AK		 147{
148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 149 struct ixgbe_hw *hw = &adapter->hw;
150 u32 link_speed = 0;
151 bool link_up;
9a799d71 152
735441fb
AV		 153 ecmd->supported = SUPPORTED_10000baseT_Full;
154 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 155 ecmd->transceiver = XCVR_EXTERNAL;
74766013 156 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 157 (hw->phy.multispeed_fiber)) {
735441fb 158 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 159 SUPPORTED_Autoneg);
735441fb 160
1b1c0a48
AS		 161 switch (hw->mac.type) {
162 case ixgbe_mac_X540:
163 ecmd->supported |= SUPPORTED_100baseT_Full;
164 break;
165 default:
166 break;
167 }
168
74766013 169 ecmd->advertising = ADVERTISED_Autoneg;
2b642ca5
ET		 170 if (hw->phy.autoneg_advertised) {
171 if (hw->phy.autoneg_advertised &
172 IXGBE_LINK_SPEED_100_FULL)
173 ecmd->advertising |= ADVERTISED_100baseT_Full;
174 if (hw->phy.autoneg_advertised &
175 IXGBE_LINK_SPEED_10GB_FULL)
176 ecmd->advertising |= ADVERTISED_10000baseT_Full;
177 if (hw->phy.autoneg_advertised &
178 IXGBE_LINK_SPEED_1GB_FULL)
179 ecmd->advertising |= ADVERTISED_1000baseT_Full;
180 } else {
181 /*
182 * Default advertised modes in case
183 * phy.autoneg_advertised isn't set.
184 */
7c5b8323
DS		 185 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
186 ADVERTISED_1000baseT_Full);
2b642ca5
ET		 187 if (hw->mac.type == ixgbe_mac_X540)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
1b1c0a48
AS		 189 }
190
74766013
MC		 191 if (hw->phy.media_type == ixgbe_media_type_copper) {
192 ecmd->supported |= SUPPORTED_TP;
193 ecmd->advertising |= ADVERTISED_TP;
194 ecmd->port = PORT_TP;
195 } else {
196 ecmd->supported |= SUPPORTED_FIBRE;
197 ecmd->advertising |= ADVERTISED_FIBRE;
198 ecmd->port = PORT_FIBRE;
199 }
1e336d0f
DS		 200 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
201 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 202 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 203 ecmd->supported = (SUPPORTED_1000baseT_Full |
204 SUPPORTED_FIBRE);
205 ecmd->advertising = (ADVERTISED_1000baseT_Full |
206 ADVERTISED_FIBRE);
207 ecmd->port = PORT_FIBRE;
208 ecmd->autoneg = AUTONEG_DISABLE;
50d6c681
AD		 209 } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) ||
210 (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
211 ecmd->supported |= (SUPPORTED_1000baseT_Full |
212 SUPPORTED_Autoneg |
213 SUPPORTED_FIBRE);
214 ecmd->advertising = (ADVERTISED_10000baseT_Full |
215 ADVERTISED_1000baseT_Full |
216 ADVERTISED_Autoneg |
217 ADVERTISED_FIBRE);
218 ecmd->port = PORT_FIBRE;
46a72b35
MC		 219 } else {
220 ecmd->supported |= (SUPPORTED_1000baseT_Full |
221 SUPPORTED_FIBRE);
222 ecmd->advertising = (ADVERTISED_10000baseT_Full |
223 ADVERTISED_1000baseT_Full |
224 ADVERTISED_FIBRE);
225 ecmd->port = PORT_FIBRE;
1e336d0f 226 }
735441fb
AV		 227 } else {
228 ecmd->supported |= SUPPORTED_FIBRE;
229 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 230 ADVERTISED_FIBRE);
735441fb 231 ecmd->port = PORT_FIBRE;
c44ade9e 232 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 233 }
9a799d71 234
3b8626ba
PW		 235 /* Get PHY type */
236 switch (adapter->hw.phy.type) {
237 case ixgbe_phy_tn:
fe15e8e1 238 case ixgbe_phy_aq:
3b8626ba
PW		 239 case ixgbe_phy_cu_unknown:
240 /* Copper 10G-BASET */
241 ecmd->port = PORT_TP;
242 break;
243 case ixgbe_phy_qt:
244 ecmd->port = PORT_FIBRE;
245 break;
246 case ixgbe_phy_nl:
ea0a04df
DS		 247 case ixgbe_phy_sfp_passive_tyco:
248 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 249 case ixgbe_phy_sfp_ftl:
250 case ixgbe_phy_sfp_avago:
251 case ixgbe_phy_sfp_intel:
252 case ixgbe_phy_sfp_unknown:
253 switch (adapter->hw.phy.sfp_type) {
254 /* SFP+ devices, further checking needed */
255 case ixgbe_sfp_type_da_cu:
256 case ixgbe_sfp_type_da_cu_core0:
257 case ixgbe_sfp_type_da_cu_core1:
258 ecmd->port = PORT_DA;
259 break;
260 case ixgbe_sfp_type_sr:
261 case ixgbe_sfp_type_lr:
262 case ixgbe_sfp_type_srlr_core0:
263 case ixgbe_sfp_type_srlr_core1:
264 ecmd->port = PORT_FIBRE;
265 break;
266 case ixgbe_sfp_type_not_present:
267 ecmd->port = PORT_NONE;
268 break;
cb836a97
DS		 269 case ixgbe_sfp_type_1g_cu_core0:
270 case ixgbe_sfp_type_1g_cu_core1:
271 ecmd->port = PORT_TP;
272 ecmd->supported = SUPPORTED_TP;
273 ecmd->advertising = (ADVERTISED_1000baseT_Full |
274 ADVERTISED_TP);
275 break;
3b8626ba
PW		 276 case ixgbe_sfp_type_unknown:
277 default:
278 ecmd->port = PORT_OTHER;
279 break;
280 }
281 break;
282 case ixgbe_phy_xaui:
283 ecmd->port = PORT_NONE;
284 break;
285 case ixgbe_phy_unknown:
286 case ixgbe_phy_generic:
287 case ixgbe_phy_sfp_unsupported:
288 default:
289 ecmd->port = PORT_OTHER;
290 break;
291 }
292
c44ade9e 293 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 294 if (link_up) {
1b1c0a48
AS		 295 switch (link_speed) {
296 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 297 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 298 break;
299 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 300 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 301 break;
302 case IXGBE_LINK_SPEED_100_FULL:
70739497 303 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 304 break;
305 default:
306 break;
307 }
9a799d71
AK		 308 ecmd->duplex = DUPLEX_FULL;
309 } else {
70739497 310 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 311 ecmd->duplex = -1;
312 }
313
9a799d71
AK		 314 return 0;
315}
316
317static int ixgbe_set_settings(struct net_device *netdev,
b4617240 318 struct ethtool_cmd *ecmd)
9a799d71
AK		 319{
320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 321 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 322 u32 advertised, old;
74766013 323 s32 err = 0;
9a799d71 324
74766013 325 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 326 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 327 /*
328 * this function does not support duplex forcing, but can
329 * limit the advertising of the adapter to the specified speed
330 */
0befdb3e
JB		 331 if (ecmd->autoneg == AUTONEG_DISABLE)
332 return -EINVAL;
333
abcc80d2
ET		 334 if (ecmd->advertising & ~ecmd->supported)
335 return -EINVAL;
336
0befdb3e
JB		 337 old = hw->phy.autoneg_advertised;
338 advertised = 0;
339 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
340 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
341
342 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
343 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
344
2b642ca5
ET		 345 if (ecmd->advertising & ADVERTISED_100baseT_Full)
346 advertised |= IXGBE_LINK_SPEED_100_FULL;
347
0befdb3e 348 if (old == advertised)
74766013 349 return err;
0befdb3e 350 /* this sets the link speed and restarts auto-neg */
74766013 351 hw->mac.autotry_restart = true;
8620a103 352 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 353 if (err) {
396e799c 354 e_info(probe, "setup link failed with code %d\n", err);
8620a103 355 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 356 }
74766013
MC		 357 } else {
358 /* in this case we currently only support 10Gb/FULL */
25db0338 359 u32 speed = ethtool_cmd_speed(ecmd);
74766013 360 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 361 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 362 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 363 return -EINVAL;
9a799d71
AK		 364 }
365
74766013 366 return err;
9a799d71
AK		 367}
368
369static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 370 struct ethtool_pauseparam *pause)
9a799d71
AK		 371{
372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
373 struct ixgbe_hw *hw = &adapter->hw;
374
71fd570b
DS		 375 /*
376 * Flow Control Autoneg isn't on if
377 * - we didn't ask for it OR
378 * - it failed, we know this by tx & rx being off
379 */
380 if (hw->fc.disable_fc_autoneg ||
381 (hw->fc.current_mode == ixgbe_fc_none))
382 pause->autoneg = 0;
383 else
384 pause->autoneg = 1;
9a799d71 385
0ecc061d 386 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 387 pause->rx_pause = 1;
0ecc061d 388 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 389 pause->tx_pause = 1;
0ecc061d 390 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 391 pause->rx_pause = 1;
392 pause->tx_pause = 1;
673ac604
AD		 393#ifdef CONFIG_DCB
394 } else if (hw->fc.current_mode == ixgbe_fc_pfc) {
395 pause->rx_pause = 0;
396 pause->tx_pause = 0;
397#endif
9a799d71
AK		 398 }
399}
400
401static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 402 struct ethtool_pauseparam *pause)
9a799d71
AK		 403{
404 struct ixgbe_adapter *adapter = netdev_priv(netdev);
405 struct ixgbe_hw *hw = &adapter->hw;
620fa036 406 struct ixgbe_fc_info fc;
9a799d71 407
264857b8
PWJ		 408#ifdef CONFIG_DCB
409 if (adapter->dcb_cfg.pfc_mode_enable ||
410 ((hw->mac.type == ixgbe_mac_82598EB) &&
411 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
412 return -EINVAL;
413
414#endif
620fa036
MC		 415 fc = hw->fc;
416
71fd570b 417 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 418 fc.disable_fc_autoneg = true;
71fd570b 419 else
620fa036 420 fc.disable_fc_autoneg = false;
71fd570b 421
1c4f0ef8 422 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 423 fc.requested_mode = ixgbe_fc_full;
9a799d71 424 else if (pause->rx_pause && !pause->tx_pause)
620fa036 425 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 426 else if (!pause->rx_pause && pause->tx_pause)
620fa036 427 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 428 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 429 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 430 else
431 return -EINVAL;
9a799d71 432
264857b8 433#ifdef CONFIG_DCB
620fa036 434 adapter->last_lfc_mode = fc.requested_mode;
264857b8 435#endif
620fa036
MC		 436
437 /* if the thing changed then we'll update and use new autoneg */
438 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
439 hw->fc = fc;
440 if (netif_running(netdev))
441 ixgbe_reinit_locked(adapter);
442 else
443 ixgbe_reset(adapter);
444 }
9a799d71
AK		 445
446 return 0;
447}
448
9a799d71
AK		 449static u32 ixgbe_get_msglevel(struct net_device *netdev)
450{
451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
452 return adapter->msg_enable;
453}
454
455static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
456{
457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
458 adapter->msg_enable = data;
459}
460
461static int ixgbe_get_regs_len(struct net_device *netdev)
462{
463#define IXGBE_REGS_LEN 1128
464 return IXGBE_REGS_LEN * sizeof(u32);
465}
466
467#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
468
469static void ixgbe_get_regs(struct net_device *netdev,
b4617240 470 struct ethtool_regs *regs, void *p)
9a799d71
AK		 471{
472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
473 struct ixgbe_hw *hw = &adapter->hw;
474 u32 *regs_buff = p;
475 u8 i;
476
477 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
478
479 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
480
481 /* General Registers */
482 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
483 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
484 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
485 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
486 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
487 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
488 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
489 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
490
491 /* NVM Register */
492 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
493 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
494 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
495 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
496 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
497 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
498 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
499 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
500 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
501 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
502
503 /* Interrupt */
98c00a1c
JB		 504 /* don't read EICR because it can clear interrupt causes, instead
505 * read EICS which is a shadow but doesn't clear EICR */
506 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 507 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
508 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
509 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
510 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
511 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
512 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
513 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
514 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
515 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 516 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 517 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
518
519 /* Flow Control */
520 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
521 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
522 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
523 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
524 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 525 for (i = 0; i < 8; i++) {
526 switch (hw->mac.type) {
527 case ixgbe_mac_82598EB:
528 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
529 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
530 break;
531 case ixgbe_mac_82599EB:
80bb25e3 532 case ixgbe_mac_X540:
bd508178
AD		 533 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
534 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
535 break;
536 default:
537 break;
538 }
539 }
9a799d71
AK		 540 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
541 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
542
543 /* Receive DMA */
544 for (i = 0; i < 64; i++)
545 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
546 for (i = 0; i < 64; i++)
547 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
548 for (i = 0; i < 64; i++)
549 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
550 for (i = 0; i < 64; i++)
551 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
552 for (i = 0; i < 64; i++)
553 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
554 for (i = 0; i < 64; i++)
555 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
556 for (i = 0; i < 16; i++)
557 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
558 for (i = 0; i < 16; i++)
559 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
560 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
561 for (i = 0; i < 8; i++)
562 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
563 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
564 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
565
566 /* Receive */
567 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
568 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
569 for (i = 0; i < 16; i++)
570 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
571 for (i = 0; i < 16; i++)
572 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 573 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 574 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
575 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
576 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
577 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
578 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
579 for (i = 0; i < 8; i++)
580 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
581 for (i = 0; i < 8; i++)
582 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
583 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
584
585 /* Transmit */
586 for (i = 0; i < 32; i++)
587 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
588 for (i = 0; i < 32; i++)
589 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
590 for (i = 0; i < 32; i++)
591 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
592 for (i = 0; i < 32; i++)
593 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
594 for (i = 0; i < 32; i++)
595 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
596 for (i = 0; i < 32; i++)
597 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
598 for (i = 0; i < 32; i++)
599 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
600 for (i = 0; i < 32; i++)
601 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
602 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
603 for (i = 0; i < 16; i++)
604 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
605 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
606 for (i = 0; i < 8; i++)
607 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
608 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
609
610 /* Wake Up */
611 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
612 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
613 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
614 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
615 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
616 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
617 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
618 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 619 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 620
673ac604 621 /* DCB */
9a799d71
AK		 622 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
623 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
624 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
625 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
626 for (i = 0; i < 8; i++)
627 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
628 for (i = 0; i < 8; i++)
629 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
632 for (i = 0; i < 8; i++)
633 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
634 for (i = 0; i < 8; i++)
635 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
636 for (i = 0; i < 8; i++)
637 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
638
639 /* Statistics */
640 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
641 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
642 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
643 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
644 for (i = 0; i < 8; i++)
645 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
646 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
647 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
648 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
649 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
650 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
651 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
652 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
653 for (i = 0; i < 8; i++)
654 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
655 for (i = 0; i < 8; i++)
656 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
657 for (i = 0; i < 8; i++)
658 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
659 for (i = 0; i < 8; i++)
660 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
661 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
662 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
663 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
664 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
665 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
666 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
667 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
668 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
669 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
670 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
671 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
672 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
673 for (i = 0; i < 8; i++)
674 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
675 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
676 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
677 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
678 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
679 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
680 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
681 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
682 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
683 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
684 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
685 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
686 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
687 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
688 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
689 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
690 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
691 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
692 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
693 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
694 for (i = 0; i < 16; i++)
695 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
696 for (i = 0; i < 16; i++)
697 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
698 for (i = 0; i < 16; i++)
699 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
700 for (i = 0; i < 16; i++)
701 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
702
703 /* MAC */
704 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
705 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
706 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
707 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
708 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
709 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
710 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
711 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
712 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
713 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
714 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
715 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
716 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
717 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
718 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
719 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
720 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
721 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
722 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
723 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
724 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
725 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
726 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
727 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
728 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
729 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
730 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
731 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
732 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
733 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
734 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
735 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
736 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
737
738 /* Diagnostic */
739 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
740 for (i = 0; i < 8; i++)
98c00a1c 741 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 742 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 743 for (i = 0; i < 4; i++)
744 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 745 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
746 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
747 for (i = 0; i < 8; i++)
98c00a1c 748 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 749 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 750 for (i = 0; i < 4; i++)
751 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 752 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
753 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
754 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
755 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
756 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
757 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
758 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
759 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
760 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
761 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
762 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
763 for (i = 0; i < 8; i++)
98c00a1c 764 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 765 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
766 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
767 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
768 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
769 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
770 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
771 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
772 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
773 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
774}
775
776static int ixgbe_get_eeprom_len(struct net_device *netdev)
777{
778 struct ixgbe_adapter *adapter = netdev_priv(netdev);
779 return adapter->hw.eeprom.word_size * 2;
780}
781
782static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 783 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 784{
785 struct ixgbe_adapter *adapter = netdev_priv(netdev);
786 struct ixgbe_hw *hw = &adapter->hw;
787 u16 *eeprom_buff;
788 int first_word, last_word, eeprom_len;
789 int ret_val = 0;
790 u16 i;
791
792 if (eeprom->len == 0)
793 return -EINVAL;
794
795 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
796
797 first_word = eeprom->offset >> 1;
798 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
799 eeprom_len = last_word - first_word + 1;
800
801 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
802 if (!eeprom_buff)
803 return -ENOMEM;
804
68c7005d
ET		 805 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
806 eeprom_buff);
9a799d71
AK		 807
808 /* Device's eeprom is always little-endian, word addressable */
809 for (i = 0; i < eeprom_len; i++)
810 le16_to_cpus(&eeprom_buff[i]);
811
812 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
813 kfree(eeprom_buff);
814
815 return ret_val;
816}
817
818static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 819 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 820{
821 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 822 char firmware_version[32];
9a799d71 823
9fe93afd
DS		 824 strncpy(drvinfo->driver, ixgbe_driver_name,
825 sizeof(drvinfo->driver) - 1);
083fc582 826 strncpy(drvinfo->version, ixgbe_driver_version,
9fe93afd 827 sizeof(drvinfo->version) - 1);
083fc582
DS		 828
829 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
830 (adapter->eeprom_version & 0xF000) >> 12,
831 (adapter->eeprom_version & 0x0FF0) >> 4,
832 adapter->eeprom_version & 0x000F);
833
834 strncpy(drvinfo->fw_version, firmware_version,
835 sizeof(drvinfo->fw_version));
836 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
837 sizeof(drvinfo->bus_info));
9a799d71 838 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 839 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 840 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
841}
842
843static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 844 struct ethtool_ringparam *ring)
9a799d71
AK		 845{
846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 847 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
848 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 849
850 ring->rx_max_pending = IXGBE_MAX_RXD;
851 ring->tx_max_pending = IXGBE_MAX_TXD;
852 ring->rx_mini_max_pending = 0;
853 ring->rx_jumbo_max_pending = 0;
854 ring->rx_pending = rx_ring->count;
855 ring->tx_pending = tx_ring->count;
856 ring->rx_mini_pending = 0;
857 ring->rx_jumbo_pending = 0;
858}
859
860static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 861 struct ethtool_ringparam *ring)
9a799d71
AK		 862{
863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 864 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 865 int i, err = 0;
c431f97e 866 u32 new_rx_count, new_tx_count;
f9ed8854 867 bool need_update = false;
9a799d71
AK		 868
869 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
870 return -EINVAL;
871
872 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
873 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
874 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
875
876 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
877 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
878 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
879
4a0b9ca0
PW		 880 if ((new_tx_count == adapter->tx_ring[0]->count) &&
881 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 882 /* nothing to do */
883 return 0;
884 }
885
d4f80882 886 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 887 usleep_range(1000, 2000);
d4f80882 888
759884b4
AD		 889 if (!netif_running(adapter->netdev)) {
890 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 891 adapter->tx_ring[i]->count = new_tx_count;
759884b4 892 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 893 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 894 adapter->tx_ring_count = new_tx_count;
895 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 896 goto clear_reset;
759884b4
AD		 897 }
898
4a0b9ca0 899 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 900 if (!temp_tx_ring) {
901 err = -ENOMEM;
4a0b9ca0 902 goto clear_reset;
f9ed8854
MC		 903 }
904
905 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 906 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 907 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
908 sizeof(struct ixgbe_ring));
f9ed8854 909 temp_tx_ring[i].count = new_tx_count;
b6ec895e 910 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
9a799d71 911 if (err) {
c431f97e
JB		 912 while (i) {
913 i--;
b6ec895e 914 ixgbe_free_tx_resources(&temp_tx_ring[i]);
c431f97e 915 }
4a0b9ca0 916 goto clear_reset;
9a799d71 917 }
9a799d71 918 }
f9ed8854 919 need_update = true;
9a799d71
AK		 920 }
921
4a0b9ca0
PW		 922 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
923 if (!temp_rx_ring) {
f9ed8854
MC		 924 err = -ENOMEM;
925 goto err_setup;
d3fa4721 926 }
9a799d71 927
f9ed8854 928 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 929 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 930 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
931 sizeof(struct ixgbe_ring));
f9ed8854 932 temp_rx_ring[i].count = new_rx_count;
b6ec895e 933 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
9a799d71 934 if (err) {
c431f97e
JB		 935 while (i) {
936 i--;
b6ec895e 937 ixgbe_free_rx_resources(&temp_rx_ring[i]);
c431f97e 938 }
9a799d71
AK		 939 goto err_setup;
940 }
9a799d71 941 }
f9ed8854
MC		 942 need_update = true;
943 }
944
945 /* if rings need to be updated, here's the place to do it in one shot */
946 if (need_update) {
759884b4 947 ixgbe_down(adapter);
f9ed8854
MC		 948
949 /* tx */
950 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0 951 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 952 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4a0b9ca0
PW		 953 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
954 sizeof(struct ixgbe_ring));
955 }
f9ed8854
MC		 956 adapter->tx_ring_count = new_tx_count;
957 }
958
959 /* rx */
960 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0 961 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 962 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4a0b9ca0
PW		 963 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
964 sizeof(struct ixgbe_ring));
965 }
f9ed8854
MC		 966 adapter->rx_ring_count = new_rx_count;
967 }
f9ed8854 968 ixgbe_up(adapter);
759884b4 969 }
4a0b9ca0
PW		 970
971 vfree(temp_rx_ring);
f9ed8854 972err_setup:
4a0b9ca0
PW		 973 vfree(temp_tx_ring);
974clear_reset:
d4f80882 975 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 976 return err;
977}
978
b9f2c044 979static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 980{
b9f2c044 981 switch (sset) {
da4dd0f7
PWJ		 982 case ETH_SS_TEST:
983 return IXGBE_TEST_LEN;
b9f2c044
JG		 984 case ETH_SS_STATS:
985 return IXGBE_STATS_LEN;
986 default:
987 return -EOPNOTSUPP;
988 }
9a799d71
AK		 989}
990
991static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 992 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 993{
994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 995 struct rtnl_link_stats64 temp;
996 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 997 unsigned int start;
998 struct ixgbe_ring *ring;
999 int i, j;
29c3a050 1000 char *p = NULL;
9a799d71
AK		 1001
1002 ixgbe_update_stats(adapter);
28172739 1003 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1004 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1005 switch (ixgbe_gstrings_stats[i].type) {
1006 case NETDEV_STATS:
28172739 1007 p = (char *) net_stats +
29c3a050
AK		 1008 ixgbe_gstrings_stats[i].stat_offset;
1009 break;
1010 case IXGBE_STATS:
1011 p = (char *) adapter +
1012 ixgbe_gstrings_stats[i].stat_offset;
1013 break;
1014 }
1015
9a799d71 1016 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1017 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1018 }
1019 for (j = 0; j < adapter->num_tx_queues; j++) {
de1036b1
ED		 1020 ring = adapter->tx_ring[j];
1021 do {
1022 start = u64_stats_fetch_begin_bh(&ring->syncp);
1023 data[i] = ring->stats.packets;
1024 data[i+1] = ring->stats.bytes;
1025 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1026 i += 2;
9a799d71
AK		 1027 }
1028 for (j = 0; j < adapter->num_rx_queues; j++) {
de1036b1
ED		 1029 ring = adapter->rx_ring[j];
1030 do {
1031 start = u64_stats_fetch_begin_bh(&ring->syncp);
1032 data[i] = ring->stats.packets;
1033 data[i+1] = ring->stats.bytes;
1034 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1035 i += 2;
9a799d71 1036 }
2f90b865
AD		 1037 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1038 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1039 data[i++] = adapter->stats.pxontxc[j];
1040 data[i++] = adapter->stats.pxofftxc[j];
1041 }
1042 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1043 data[i++] = adapter->stats.pxonrxc[j];
1044 data[i++] = adapter->stats.pxoffrxc[j];
1045 }
1046 }
9a799d71
AK		 1047}
1048
1049static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1050 u8 *data)
9a799d71
AK		 1051{
1052 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1053 char *p = (char *)data;
9a799d71
AK		 1054 int i;
1055
1056 switch (stringset) {
da4dd0f7
PWJ		 1057 case ETH_SS_TEST:
1058 memcpy(data, *ixgbe_gstrings_test,
1059 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1060 break;
9a799d71
AK		 1061 case ETH_SS_STATS:
1062 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1063 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1064 ETH_GSTRING_LEN);
1065 p += ETH_GSTRING_LEN;
1066 }
1067 for (i = 0; i < adapter->num_tx_queues; i++) {
1068 sprintf(p, "tx_queue_%u_packets", i);
1069 p += ETH_GSTRING_LEN;
1070 sprintf(p, "tx_queue_%u_bytes", i);
1071 p += ETH_GSTRING_LEN;
1072 }
1073 for (i = 0; i < adapter->num_rx_queues; i++) {
1074 sprintf(p, "rx_queue_%u_packets", i);
1075 p += ETH_GSTRING_LEN;
1076 sprintf(p, "rx_queue_%u_bytes", i);
1077 p += ETH_GSTRING_LEN;
1078 }
2f90b865
AD		 1079 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1080 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1081 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1082 p += ETH_GSTRING_LEN;
1083 sprintf(p, "tx_pb_%u_pxoff", i);
1084 p += ETH_GSTRING_LEN;
2f90b865
AD		 1085 }
1086 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1087 sprintf(p, "rx_pb_%u_pxon", i);
1088 p += ETH_GSTRING_LEN;
1089 sprintf(p, "rx_pb_%u_pxoff", i);
1090 p += ETH_GSTRING_LEN;
2f90b865
AD		 1091 }
1092 }
b4617240 1093 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1094 break;
1095 }
1096}
1097
da4dd0f7
PWJ		 1098static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1099{
1100 struct ixgbe_hw *hw = &adapter->hw;
1101 bool link_up;
1102 u32 link_speed = 0;
1103 *data = 0;
1104
1105 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1106 if (link_up)
1107 return *data;
1108 else
1109 *data = 1;
1110 return *data;
1111}
1112
1113/* ethtool register test data */
1114struct ixgbe_reg_test {
1115 u16 reg;
1116 u8 array_len;
1117 u8 test_type;
1118 u32 mask;
1119 u32 write;
1120};
1121
1122/* In the hardware, registers are laid out either singly, in arrays
1123 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1124 * most tests take place on arrays or single registers (handled
1125 * as a single-element array) and special-case the tables.
1126 * Table tests are always pattern tests.
1127 *
1128 * We also make provision for some required setup steps by specifying
1129 * registers to be written without any read-back testing.
1130 */
1131
1132#define PATTERN_TEST 1
1133#define SET_READ_TEST 2
1134#define WRITE_NO_TEST 3
1135#define TABLE32_TEST 4
1136#define TABLE64_TEST_LO 5
1137#define TABLE64_TEST_HI 6
1138
1139/* default 82599 register test */
66744500 1140static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1141 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1142 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1143 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1144 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1145 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1146 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1147 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1148 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1149 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1150 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1151 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1152 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1153 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1154 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1155 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1156 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1157 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1158 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1159 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1160 { 0, 0, 0, 0 }
1161};
1162
1163/* default 82598 register test */
66744500 1164static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1165 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1166 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1167 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1168 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1169 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1170 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1171 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1172 /* Enable all four RX queues before testing. */
1173 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1174 /* RDH is read-only for 82598, only test RDT. */
1175 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1176 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1177 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1178 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1179 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1180 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1181 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1182 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1183 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1184 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1185 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1186 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1187 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1188 { 0, 0, 0, 0 }
1189};
1190
95a46011
ET		 1191static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1192 u32 mask, u32 write)
1193{
1194 u32 pat, val, before;
1195 static const u32 test_pattern[] = {
1196 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1197
1198 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1199 before = readl(adapter->hw.hw_addr + reg);
1200 writel((test_pattern[pat] & write),
1201 (adapter->hw.hw_addr + reg));
1202 val = readl(adapter->hw.hw_addr + reg);
1203 if (val != (test_pattern[pat] & write & mask)) {
1204 e_err(drv, "pattern test reg %04X failed: got "
1205 "0x%08X expected 0x%08X\n",
1206 reg, val, (test_pattern[pat] & write & mask));
1207 *data = reg;
1208 writel(before, adapter->hw.hw_addr + reg);
1209 return 1;
1210 }
1211 writel(before, adapter->hw.hw_addr + reg);
1212 }
1213 return 0;
da4dd0f7
PWJ		 1214}
1215
95a46011
ET		 1216static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1217 u32 mask, u32 write)
1218{
1219 u32 val, before;
1220 before = readl(adapter->hw.hw_addr + reg);
1221 writel((write & mask), (adapter->hw.hw_addr + reg));
1222 val = readl(adapter->hw.hw_addr + reg);
1223 if ((write & mask) != (val & mask)) {
1224 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1225 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1226 *data = reg;
1227 writel(before, (adapter->hw.hw_addr + reg));
1228 return 1;
1229 }
1230 writel(before, (adapter->hw.hw_addr + reg));
1231 return 0;
da4dd0f7
PWJ		 1232}
1233
95a46011
ET		 1234#define REG_PATTERN_TEST(reg, mask, write) \
1235 do { \
1236 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1237 return 1; \
1238 } while (0) \
1239
1240
1241#define REG_SET_AND_CHECK(reg, mask, write) \
1242 do { \
1243 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1244 return 1; \
1245 } while (0) \
1246
da4dd0f7
PWJ		 1247static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1248{
66744500 1249 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1250 u32 value, before, after;
1251 u32 i, toggle;
1252
bd508178
AD		 1253 switch (adapter->hw.mac.type) {
1254 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1255 toggle = 0x7FFFF3FF;
1256 test = reg_test_82598;
bd508178
AD		 1257 break;
1258 case ixgbe_mac_82599EB:
b93a2226 1259 case ixgbe_mac_X540:
bd508178
AD		 1260 toggle = 0x7FFFF30F;
1261 test = reg_test_82599;
1262 break;
1263 default:
1264 *data = 1;
1265 return 1;
1266 break;
da4dd0f7
PWJ		 1267 }
1268
1269 /*
1270 * Because the status register is such a special case,
1271 * we handle it separately from the rest of the register
1272 * tests. Some bits are read-only, some toggle, and some
1273 * are writeable on newer MACs.
1274 */
1275 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1276 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1278 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1279 if (value != after) {
396e799c
ET		 1280 e_err(drv, "failed STATUS register test got: 0x%08X "
1281 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1282 *data = 1;
1283 return 1;
1284 }
1285 /* restore previous status */
1286 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1287
1288 /*
1289 * Perform the remainder of the register test, looping through
1290 * the test table until we either fail or reach the null entry.
1291 */
1292 while (test->reg) {
1293 for (i = 0; i < test->array_len; i++) {
1294 switch (test->test_type) {
1295 case PATTERN_TEST:
1296 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1297 test->mask,
1298 test->write);
da4dd0f7
PWJ		 1299 break;
1300 case SET_READ_TEST:
1301 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1302 test->mask,
1303 test->write);
da4dd0f7
PWJ		 1304 break;
1305 case WRITE_NO_TEST:
1306 writel(test->write,
1307 (adapter->hw.hw_addr + test->reg)
1308 + (i * 0x40));
1309 break;
1310 case TABLE32_TEST:
1311 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1312 test->mask,
1313 test->write);
da4dd0f7
PWJ		 1314 break;
1315 case TABLE64_TEST_LO:
1316 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1317 test->mask,
1318 test->write);
da4dd0f7
PWJ		 1319 break;
1320 case TABLE64_TEST_HI:
1321 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1322 test->mask,
1323 test->write);
da4dd0f7
PWJ		 1324 break;
1325 }
1326 }
1327 test++;
1328 }
1329
1330 *data = 0;
1331 return 0;
1332}
1333
1334static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1335{
1336 struct ixgbe_hw *hw = &adapter->hw;
1337 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1338 *data = 1;
1339 else
1340 *data = 0;
1341 return *data;
1342}
1343
1344static irqreturn_t ixgbe_test_intr(int irq, void *data)
1345{
1346 struct net_device *netdev = (struct net_device *) data;
1347 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1348
1349 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1350
1351 return IRQ_HANDLED;
1352}
1353
1354static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1355{
1356 struct net_device *netdev = adapter->netdev;
1357 u32 mask, i = 0, shared_int = true;
1358 u32 irq = adapter->pdev->irq;
1359
1360 *data = 0;
1361
1362 /* Hook up test interrupt handler just for this test */
1363 if (adapter->msix_entries) {
1364 /* NOTE: we don't test MSI-X interrupts here, yet */
1365 return 0;
1366 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1367 shared_int = false;
a0607fd3 1368 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1369 netdev)) {
1370 *data = 1;
1371 return -1;
1372 }
a0607fd3 1373 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1374 netdev->name, netdev)) {
1375 shared_int = false;
a0607fd3 1376 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1377 netdev->name, netdev)) {
1378 *data = 1;
1379 return -1;
1380 }
396e799c
ET		 1381 e_info(hw, "testing %s interrupt\n", shared_int ?
1382 "shared" : "unshared");
da4dd0f7
PWJ		 1383
1384 /* Disable all the interrupts */
1385 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1386 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1387 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1388
1389 /* Test each interrupt */
1390 for (; i < 10; i++) {
1391 /* Interrupt to test */
1392 mask = 1 << i;
1393
1394 if (!shared_int) {
1395 /*
1396 * Disable the interrupts to be reported in
1397 * the cause register and then force the same
1398 * interrupt and see if one gets posted. If
1399 * an interrupt was posted to the bus, the
1400 * test failed.
1401 */
1402 adapter->test_icr = 0;
1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1404 ~mask & 0x00007FFF);
1405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1406 ~mask & 0x00007FFF);
945a5151 1407 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1408 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1409
1410 if (adapter->test_icr & mask) {
1411 *data = 3;
1412 break;
1413 }
1414 }
1415
1416 /*
1417 * Enable the interrupt to be reported in the cause
1418 * register and then force the same interrupt and see
1419 * if one gets posted. If an interrupt was not posted
1420 * to the bus, the test failed.
1421 */
1422 adapter->test_icr = 0;
1423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1425 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1426 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1427
1428 if (!(adapter->test_icr &mask)) {
1429 *data = 4;
1430 break;
1431 }
1432
1433 if (!shared_int) {
1434 /*
1435 * Disable the other interrupts to be reported in
1436 * the cause register and then force the other
1437 * interrupts and see if any get posted. If
1438 * an interrupt was posted to the bus, the
1439 * test failed.
1440 */
1441 adapter->test_icr = 0;
1442 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1443 ~mask & 0x00007FFF);
1444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1445 ~mask & 0x00007FFF);
945a5151 1446 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1447 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1448
1449 if (adapter->test_icr) {
1450 *data = 5;
1451 break;
1452 }
1453 }
1454 }
1455
1456 /* Disable all the interrupts */
1457 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1458 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1459 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1460
1461 /* Unhook test interrupt handler */
1462 free_irq(irq, netdev);
1463
1464 return *data;
1465}
1466
1467static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1468{
1469 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1470 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1471 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1472 u32 reg_ctl;
da4dd0f7
PWJ		 1473
1474 /* shut down the DMA engines now so they can be reinitialized later */
1475
1476 /* first Rx */
1477 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1478 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1479 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1480 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1481
1482 /* now Tx */
84418e3b 1483 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1484 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1485 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1486
bd508178
AD		 1487 switch (hw->mac.type) {
1488 case ixgbe_mac_82599EB:
b93a2226 1489 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1490 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1491 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1492 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1493 break;
1494 default:
1495 break;
da4dd0f7
PWJ		 1496 }
1497
1498 ixgbe_reset(adapter);
1499
b6ec895e
AD		 1500 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1501 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1502}
1503
1504static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1505{
1506 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1507 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1508 u32 rctl, reg_data;
84418e3b
AD		 1509 int ret_val;
1510 int err;
da4dd0f7
PWJ		 1511
1512 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1513 tx_ring->count = IXGBE_DEFAULT_TXD;
1514 tx_ring->queue_index = 0;
b6ec895e 1515 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1516 tx_ring->netdev = adapter->netdev;
84418e3b
AD		 1517 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1518 tx_ring->numa_node = adapter->node;
da4dd0f7 1519
b6ec895e 1520 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1521 if (err)
1522 return 1;
da4dd0f7 1523
bd508178
AD		 1524 switch (adapter->hw.mac.type) {
1525 case ixgbe_mac_82599EB:
b93a2226 1526 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1527 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1528 reg_data |= IXGBE_DMATXCTL_TE;
1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1530 break;
1531 default:
1532 break;
da4dd0f7 1533 }
f4ec443b 1534
84418e3b 1535 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1536
1537 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1538 rx_ring->count = IXGBE_DEFAULT_RXD;
1539 rx_ring->queue_index = 0;
b6ec895e 1540 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1541 rx_ring->netdev = adapter->netdev;
84418e3b 1542 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
919e78a6 1543 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2K;
84418e3b
AD		 1544 rx_ring->numa_node = adapter->node;
1545
b6ec895e 1546 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1547 if (err) {
da4dd0f7
PWJ		 1548 ret_val = 4;
1549 goto err_nomem;
1550 }
1551
da4dd0f7
PWJ		 1552 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1554
84418e3b 1555 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1556
1557 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1559
da4dd0f7
PWJ		 1560 return 0;
1561
1562err_nomem:
1563 ixgbe_free_desc_rings(adapter);
1564 return ret_val;
1565}
1566
1567static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1568{
1569 struct ixgbe_hw *hw = &adapter->hw;
1570 u32 reg_data;
1571
e7fd9253
DS		 1572 /* X540 needs to set the MACC.FLU bit to force link up */
1573 if (adapter->hw.mac.type == ixgbe_mac_X540) {
35c7f8a1 1574 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
e7fd9253 1575 reg_data |= IXGBE_MACC_FLU;
35c7f8a1 1576 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
e7fd9253
DS		 1577 }
1578
da4dd0f7 1579 /* right now we only support MAC loopback in the driver */
35c7f8a1 1580 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
84418e3b 1581 /* Setup MAC loopback */
da4dd0f7 1582 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1583 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1584
35c7f8a1 1585 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1586 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1587 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1588
35c7f8a1 1589 reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);
da4dd0f7
PWJ		 1590 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1591 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
35c7f8a1
AD		 1592 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1593 IXGBE_WRITE_FLUSH(hw);
032b4325 1594 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1595
1596 /* Disable Atlas Tx lanes; re-enabled in reset path */
1597 if (hw->mac.type == ixgbe_mac_82598EB) {
1598 u8 atlas;
1599
1600 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1601 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1602 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1603
1604 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1605 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1606 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1607
1608 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1609 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1610 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1611
1612 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1613 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1614 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1615 }
1616
1617 return 0;
1618}
1619
1620static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1621{
1622 u32 reg_data;
1623
1624 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1625 reg_data &= ~IXGBE_HLREG0_LPBK;
1626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1627}
1628
1629static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1630 unsigned int frame_size)
1631{
1632 memset(skb->data, 0xFF, frame_size);
1633 frame_size &= ~1;
1634 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1635 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1636 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1637}
1638
1639static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1640 unsigned int frame_size)
1641{
1642 frame_size &= ~1;
1643 if (*(skb->data + 3) == 0xFF) {
1644 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1645 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1646 return 0;
1647 }
1648 }
1649 return 13;
1650}
1651
fc77dc3c 1652static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
84418e3b
AD		 1653 struct ixgbe_ring *tx_ring,
1654 unsigned int size)
1655{
1656 union ixgbe_adv_rx_desc *rx_desc;
1657 struct ixgbe_rx_buffer *rx_buffer_info;
1658 struct ixgbe_tx_buffer *tx_buffer_info;
1659 const int bufsz = rx_ring->rx_buf_len;
1660 u32 staterr;
1661 u16 rx_ntc, tx_ntc, count = 0;
1662
1663 /* initialize next to clean and descriptor values */
1664 rx_ntc = rx_ring->next_to_clean;
1665 tx_ntc = tx_ring->next_to_clean;
1666 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1667 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1668
1669 while (staterr & IXGBE_RXD_STAT_DD) {
1670 /* check Rx buffer */
1671 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1672
1673 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
b6ec895e 1674 dma_unmap_single(rx_ring->dev,
84418e3b
AD		 1675 rx_buffer_info->dma,
1676 bufsz,
1677 DMA_FROM_DEVICE);
1678 rx_buffer_info->dma = 0;
1679
1680 /* verify contents of skb */
1681 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1682 count++;
1683
1684 /* unmap buffer on Tx side */
1685 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
b6ec895e 1686 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
84418e3b
AD		 1687
1688 /* increment Rx/Tx next to clean counters */
1689 rx_ntc++;
1690 if (rx_ntc == rx_ring->count)
1691 rx_ntc = 0;
1692 tx_ntc++;
1693 if (tx_ntc == tx_ring->count)
1694 tx_ntc = 0;
1695
1696 /* fetch next descriptor */
1697 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1698 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1699 }
1700
1701 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1702 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1703 rx_ring->next_to_clean = rx_ntc;
1704 tx_ring->next_to_clean = tx_ntc;
1705
1706 return count;
1707}
1708
da4dd0f7
PWJ		 1709static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1710{
1711 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1712 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1713 int i, j, lc, good_cnt, ret_val = 0;
1714 unsigned int size = 1024;
1715 netdev_tx_t tx_ret_val;
1716 struct sk_buff *skb;
1717
1718 /* allocate test skb */
1719 skb = alloc_skb(size, GFP_KERNEL);
1720 if (!skb)
1721 return 11;
da4dd0f7 1722
84418e3b
AD		 1723 /* place data into test skb */
1724 ixgbe_create_lbtest_frame(skb, size);
1725 skb_put(skb, size);
da4dd0f7
PWJ		 1726
1727 /*
1728 * Calculate the loop count based on the largest descriptor ring
1729 * The idea is to wrap the largest ring a number of times using 64
1730 * send/receive pairs during each loop
1731 */
1732
1733 if (rx_ring->count <= tx_ring->count)
1734 lc = ((tx_ring->count / 64) * 2) + 1;
1735 else
1736 lc = ((rx_ring->count / 64) * 2) + 1;
1737
da4dd0f7 1738 for (j = 0; j <= lc; j++) {
84418e3b 1739 /* reset count of good packets */
da4dd0f7 1740 good_cnt = 0;
84418e3b
AD		 1741
1742 /* place 64 packets on the transmit queue*/
1743 for (i = 0; i < 64; i++) {
1744 skb_get(skb);
1745 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1746 adapter,
1747 tx_ring);
1748 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1749 good_cnt++;
84418e3b
AD		 1750 }
1751
da4dd0f7 1752 if (good_cnt != 64) {
84418e3b 1753 ret_val = 12;
da4dd0f7
PWJ		 1754 break;
1755 }
84418e3b
AD		 1756
1757 /* allow 200 milliseconds for packets to go from Tx to Rx */
1758 msleep(200);
1759
fc77dc3c 1760 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1761 if (good_cnt != 64) {
1762 ret_val = 13;
da4dd0f7
PWJ		 1763 break;
1764 }
1765 }
1766
84418e3b
AD		 1767 /* free the original skb */
1768 kfree_skb(skb);
1769
da4dd0f7
PWJ		 1770 return ret_val;
1771}
1772
1773static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1774{
1775 *data = ixgbe_setup_desc_rings(adapter);
1776 if (*data)
1777 goto out;
1778 *data = ixgbe_setup_loopback_test(adapter);
1779 if (*data)
1780 goto err_loopback;
1781 *data = ixgbe_run_loopback_test(adapter);
1782 ixgbe_loopback_cleanup(adapter);
1783
1784err_loopback:
1785 ixgbe_free_desc_rings(adapter);
1786out:
1787 return *data;
1788}
1789
1790static void ixgbe_diag_test(struct net_device *netdev,
1791 struct ethtool_test *eth_test, u64 *data)
1792{
1793 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1794 bool if_running = netif_running(netdev);
1795
1796 set_bit(__IXGBE_TESTING, &adapter->state);
1797 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1798 /* Offline tests */
1799
396e799c 1800 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1801
1802 /* Link test performed before hardware reset so autoneg doesn't
1803 * interfere with test result */
1804 if (ixgbe_link_test(adapter, &data[4]))
1805 eth_test->flags |= ETH_TEST_FL_FAILED;
1806
e7d481a6
GR		 1807 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1808 int i;
1809 for (i = 0; i < adapter->num_vfs; i++) {
1810 if (adapter->vfinfo[i].clear_to_send) {
1811 netdev_warn(netdev, "%s",
1812 "offline diagnostic is not "
1813 "supported when VFs are "
1814 "present\n");
1815 data[0] = 1;
1816 data[1] = 1;
1817 data[2] = 1;
1818 data[3] = 1;
1819 eth_test->flags |= ETH_TEST_FL_FAILED;
1820 clear_bit(__IXGBE_TESTING,
1821 &adapter->state);
1822 goto skip_ol_tests;
1823 }
1824 }
1825 }
1826
da4dd0f7
PWJ		 1827 if (if_running)
1828 /* indicate we're in test mode */
1829 dev_close(netdev);
1830 else
1831 ixgbe_reset(adapter);
1832
396e799c 1833 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1834 if (ixgbe_reg_test(adapter, &data[0]))
1835 eth_test->flags |= ETH_TEST_FL_FAILED;
1836
1837 ixgbe_reset(adapter);
396e799c 1838 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1839 if (ixgbe_eeprom_test(adapter, &data[1]))
1840 eth_test->flags |= ETH_TEST_FL_FAILED;
1841
1842 ixgbe_reset(adapter);
396e799c 1843 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1844 if (ixgbe_intr_test(adapter, &data[2]))
1845 eth_test->flags |= ETH_TEST_FL_FAILED;
1846
bdbec4b8
GR		 1847 /* If SRIOV or VMDq is enabled then skip MAC
1848 * loopback diagnostic. */
1849 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1850 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1851 e_info(hw, "Skip MAC loopback diagnostic in VT "
1852 "mode\n");
bdbec4b8
GR		 1853 data[3] = 0;
1854 goto skip_loopback;
1855 }
1856
da4dd0f7 1857 ixgbe_reset(adapter);
396e799c 1858 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1859 if (ixgbe_loopback_test(adapter, &data[3]))
1860 eth_test->flags |= ETH_TEST_FL_FAILED;
1861
bdbec4b8 1862skip_loopback:
da4dd0f7
PWJ		 1863 ixgbe_reset(adapter);
1864
1865 clear_bit(__IXGBE_TESTING, &adapter->state);
1866 if (if_running)
1867 dev_open(netdev);
1868 } else {
396e799c 1869 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1870 /* Online tests */
1871 if (ixgbe_link_test(adapter, &data[4]))
1872 eth_test->flags |= ETH_TEST_FL_FAILED;
1873
1874 /* Online tests aren't run; pass by default */
1875 data[0] = 0;
1876 data[1] = 0;
1877 data[2] = 0;
1878 data[3] = 0;
1879
1880 clear_bit(__IXGBE_TESTING, &adapter->state);
1881 }
e7d481a6 1882skip_ol_tests:
da4dd0f7
PWJ		 1883 msleep_interruptible(4 * 1000);
1884}
9a799d71 1885
d6c519e1
AD		 1886static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1887 struct ethtool_wolinfo *wol)
1888{
1889 struct ixgbe_hw *hw = &adapter->hw;
1890 int retval = 1;
1891
0b077fea 1892 /* WOL not supported except for the following */
d6c519e1 1893 switch(hw->device_id) {
0b077fea
DS		 1894 case IXGBE_DEV_ID_82599_SFP:
1895 /* Only this subdevice supports WOL */
1896 if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) {
1897 wol->supported = 0;
1898 break;
1899 }
1900 retval = 0;
1901 break;
50d6c681
AD		 1902 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1903 /* All except this subdevice support WOL */
1904 if (hw->subsystem_device_id ==
1905 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
1906 wol->supported = 0;
1907 break;
1908 }
0b077fea
DS		 1909 retval = 0;
1910 break;
d6c519e1
AD		 1911 case IXGBE_DEV_ID_82599_KX4:
1912 retval = 0;
1913 break;
1914 default:
1915 wol->supported = 0;
d6c519e1
AD		 1916 }
1917
1918 return retval;
1919}
1920
9a799d71 1921static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1922 struct ethtool_wolinfo *wol)
9a799d71 1923{
e63d9762
PW		 1924 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1925
1926 wol->supported = WAKE_UCAST | WAKE_MCAST |
1927 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1928 wol->wolopts = 0;
1929
d6c519e1
AD		 1930 if (ixgbe_wol_exclusion(adapter, wol) ||
1931 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1932 return;
1933
1934 if (adapter->wol & IXGBE_WUFC_EX)
1935 wol->wolopts |= WAKE_UCAST;
1936 if (adapter->wol & IXGBE_WUFC_MC)
1937 wol->wolopts |= WAKE_MCAST;
1938 if (adapter->wol & IXGBE_WUFC_BC)
1939 wol->wolopts |= WAKE_BCAST;
1940 if (adapter->wol & IXGBE_WUFC_MAG)
1941 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1942}
1943
e63d9762
PW		 1944static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1945{
1946 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1947
1948 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1949 return -EOPNOTSUPP;
1950
d6c519e1
AD		 1951 if (ixgbe_wol_exclusion(adapter, wol))
1952 return wol->wolopts ? -EOPNOTSUPP : 0;
1953
e63d9762
PW		 1954 adapter->wol = 0;
1955
1956 if (wol->wolopts & WAKE_UCAST)
1957 adapter->wol |= IXGBE_WUFC_EX;
1958 if (wol->wolopts & WAKE_MCAST)
1959 adapter->wol |= IXGBE_WUFC_MC;
1960 if (wol->wolopts & WAKE_BCAST)
1961 adapter->wol |= IXGBE_WUFC_BC;
1962 if (wol->wolopts & WAKE_MAGIC)
1963 adapter->wol |= IXGBE_WUFC_MAG;
1964
1965 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1966
1967 return 0;
1968}
1969
9a799d71
AK		 1970static int ixgbe_nway_reset(struct net_device *netdev)
1971{
1972 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1973
d4f80882
AV		 1974 if (netif_running(netdev))
1975 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1976
1977 return 0;
1978}
1979
66e6961c
ET		 1980static int ixgbe_set_phys_id(struct net_device *netdev,
1981 enum ethtool_phys_id_state state)
9a799d71
AK		 1982{
1983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1984 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 1985
66e6961c
ET		 1986 switch (state) {
1987 case ETHTOOL_ID_ACTIVE:
1988 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1989 return 2;
9a799d71 1990
66e6961c 1991 case ETHTOOL_ID_ON:
c44ade9e 1992 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 1993 break;
1994
1995 case ETHTOOL_ID_OFF:
c44ade9e 1996 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 1997 break;
9a799d71 1998
66e6961c
ET		 1999 case ETHTOOL_ID_INACTIVE:
2000 /* Restore LED settings */
2001 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2002 break;
2003 }
9a799d71
AK		 2004
2005 return 0;
2006}
2007
2008static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2009 struct ethtool_coalesce *ec)
9a799d71
AK		 2010{
2011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2012
bd198058 2013 ec->tx_max_coalesced_frames_irq = adapter->tx_work_limit;
30efa5a3
JB		 2014
2015 /* only valid if in constant ITR mode */
f7554a2b 2016 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 2017 case 0:
2018 /* throttling disabled */
2019 ec->rx_coalesce_usecs = 0;
2020 break;
2021 case 1:
2022 /* dynamic ITR mode */
2023 ec->rx_coalesce_usecs = 1;
2024 break;
2025 default:
2026 /* fixed interrupt rate mode */
f7554a2b 2027 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 2028 break;
2029 }
f7554a2b 2030
cfb3f91a 2031 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2032 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2033 return 0;
2034
f7554a2b
NS		 2035 /* only valid if in constant ITR mode */
2036 switch (adapter->tx_itr_setting) {
2037 case 0:
2038 /* throttling disabled */
2039 ec->tx_coalesce_usecs = 0;
2040 break;
2041 case 1:
2042 /* dynamic ITR mode */
2043 ec->tx_coalesce_usecs = 1;
2044 break;
2045 default:
2046 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2047 break;
2048 }
2049
9a799d71
AK		 2050 return 0;
2051}
2052
80fba3f4
AD		 2053/*
2054 * this function must be called before setting the new value of
2055 * rx_itr_setting
2056 */
2057static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2058 struct ethtool_coalesce *ec)
2059{
2060 struct net_device *netdev = adapter->netdev;
2061
2062 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2063 return false;
2064
2065 /* if interrupt rate is too high then disable RSC */
2066 if (ec->rx_coalesce_usecs != 1 &&
2067 ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
2068 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2069 e_info(probe, "rx-usecs set too low, "
2070 "disabling RSC\n");
2071 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2072 return true;
2073 }
2074 } else {
2075 /* check the feature flag value and enable RSC if necessary */
2076 if ((netdev->features & NETIF_F_LRO) &&
2077 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2078 e_info(probe, "rx-usecs set to %d, "
2079 "re-enabling RSC\n",
2080 ec->rx_coalesce_usecs);
2081 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2082 return true;
2083 }
2084 }
2085 return false;
2086}
2087
9a799d71 2088static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2089 struct ethtool_coalesce *ec)
9a799d71
AK		 2090{
2091 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2092 struct ixgbe_q_vector *q_vector;
30efa5a3 2093 int i;
ef021194 2094 bool need_reset = false;
9a799d71 2095
cfb3f91a 2096 /* don't accept tx specific changes if we've got mixed RxTx vectors */
08c8833b 2097 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count
cfb3f91a 2098 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2099 return -EINVAL;
2100
9a799d71 2101 if (ec->tx_max_coalesced_frames_irq)
bd198058 2102 adapter->tx_work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2103
2104 if (ec->rx_coalesce_usecs > 1) {
509ee935 2105 /* check the limits */
80fba3f4 2106 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
509ee935
JB		 2107 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2108 return -EINVAL;
2109
80fba3f4
AD		 2110 /* check the old value and enable RSC if necessary */
2111 need_reset = ixgbe_update_rsc(adapter, ec);
2112
30efa5a3 2113 /* store the value in ints/second */
f7554a2b 2114 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2115
2116 /* static value of interrupt rate */
f7554a2b 2117 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2118 /* clear the lower bit as its used for dynamic state */
f7554a2b 2119 adapter->rx_itr_setting &= ~1;
30efa5a3 2120 } else if (ec->rx_coalesce_usecs == 1) {
80fba3f4
AD		 2121 /* check the old value and enable RSC if necessary */
2122 need_reset = ixgbe_update_rsc(adapter, ec);
2123
30efa5a3 2124 /* 1 means dynamic mode */
f7554a2b
NS		 2125 adapter->rx_eitr_param = 20000;
2126 adapter->rx_itr_setting = 1;
30efa5a3 2127 } else {
80fba3f4
AD		 2128 /* check the old value and enable RSC if necessary */
2129 need_reset = ixgbe_update_rsc(adapter, ec);
509ee935
JB		 2130 /*
2131 * any other value means disable eitr, which is best
2132 * served by setting the interrupt rate very high
2133 */
f8d1dcaf 2134 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b
NS		 2135 adapter->rx_itr_setting = 0;
2136 }
2137
2138 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2139 /*
2140 * don't have to worry about max_int as above because
2141 * tx vectors don't do hardware RSC (an rx function)
2142 */
f7554a2b
NS		 2143 /* check the limits */
2144 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2145 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2146 return -EINVAL;
2147
2148 /* store the value in ints/second */
2149 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2150
2151 /* static value of interrupt rate */
2152 adapter->tx_itr_setting = adapter->tx_eitr_param;
2153
2154 /* clear the lower bit as its used for dynamic state */
2155 adapter->tx_itr_setting &= ~1;
2156 } else if (ec->tx_coalesce_usecs == 1) {
2157 /* 1 means dynamic mode */
2158 adapter->tx_eitr_param = 10000;
2159 adapter->tx_itr_setting = 1;
2160 } else {
2161 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2162 adapter->tx_itr_setting = 0;
30efa5a3 2163 }
9a799d71 2164
237057ad
DS		 2165 /* MSI/MSIx Interrupt Mode */
2166 if (adapter->flags &
2167 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2168 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2169 for (i = 0; i < num_vectors; i++) {
2170 q_vector = adapter->q_vector[i];
08c8833b 2171 if (q_vector->tx.count && !q_vector->rx.count)
f7554a2b
NS		 2172 /* tx only */
2173 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2174 else
2175 /* rx only or mixed */
f7554a2b 2176 q_vector->eitr = adapter->rx_eitr_param;
bd198058 2177 q_vector->tx.work_limit = adapter->tx_work_limit;
237057ad
DS		 2178 ixgbe_write_eitr(q_vector);
2179 }
2180 /* Legacy Interrupt Mode */
2181 } else {
2182 q_vector = adapter->q_vector[0];
f7554a2b 2183 q_vector->eitr = adapter->rx_eitr_param;
bd198058 2184 q_vector->tx.work_limit = adapter->tx_work_limit;
fe49f04a 2185 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2186 }
2187
ef021194
JB		 2188 /*
2189 * do reset here at the end to make sure EITR==0 case is handled
2190 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2191 * also locks in RSC enable/disable which requires reset
2192 */
c988ee82
ET		 2193 if (need_reset)
2194 ixgbe_do_reset(netdev);
ef021194 2195
9a799d71
AK		 2196 return 0;
2197}
2198
3e05334f
AD		 2199static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2200 struct ethtool_rxnfc *cmd)
2201{
2202 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2203 struct ethtool_rx_flow_spec *fsp =
2204 (struct ethtool_rx_flow_spec *)&cmd->fs;
2205 struct hlist_node *node, *node2;
2206 struct ixgbe_fdir_filter *rule = NULL;
2207
2208 /* report total rule count */
2209 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2210
2211 hlist_for_each_entry_safe(rule, node, node2,
2212 &adapter->fdir_filter_list, fdir_node) {
2213 if (fsp->location <= rule->sw_idx)
2214 break;
2215 }
2216
2217 if (!rule || fsp->location != rule->sw_idx)
2218 return -EINVAL;
2219
2220 /* fill out the flow spec entry */
2221
2222 /* set flow type field */
2223 switch (rule->filter.formatted.flow_type) {
2224 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2225 fsp->flow_type = TCP_V4_FLOW;
2226 break;
2227 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2228 fsp->flow_type = UDP_V4_FLOW;
2229 break;
2230 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2231 fsp->flow_type = SCTP_V4_FLOW;
2232 break;
2233 case IXGBE_ATR_FLOW_TYPE_IPV4:
2234 fsp->flow_type = IP_USER_FLOW;
2235 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2236 fsp->h_u.usr_ip4_spec.proto = 0;
2237 fsp->m_u.usr_ip4_spec.proto = 0;
2238 break;
2239 default:
2240 return -EINVAL;
2241 }
2242
2243 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2244 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2245 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2246 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2247 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2248 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2249 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2250 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2251 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2252 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2253 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2254 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2255 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2256 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2257 fsp->flow_type |= FLOW_EXT;
2258
2259 /* record action */
2260 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2261 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2262 else
2263 fsp->ring_cookie = rule->action;
2264
2265 return 0;
2266}
2267
2268static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2269 struct ethtool_rxnfc *cmd,
2270 u32 *rule_locs)
2271{
2272 struct hlist_node *node, *node2;
2273 struct ixgbe_fdir_filter *rule;
2274 int cnt = 0;
2275
2276 /* report total rule count */
2277 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2278
2279 hlist_for_each_entry_safe(rule, node, node2,
2280 &adapter->fdir_filter_list, fdir_node) {
2281 if (cnt == cmd->rule_cnt)
2282 return -EMSGSIZE;
2283 rule_locs[cnt] = rule->sw_idx;
2284 cnt++;
2285 }
2286
473e64ee
BH		 2287 cmd->rule_cnt = cnt;
2288
3e05334f
AD		 2289 return 0;
2290}
2291
91cd94bf 2292static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2293 u32 *rule_locs)
91cd94bf
AD		 2294{
2295 struct ixgbe_adapter *adapter = netdev_priv(dev);
2296 int ret = -EOPNOTSUPP;
2297
2298 switch (cmd->cmd) {
2299 case ETHTOOL_GRXRINGS:
2300 cmd->data = adapter->num_rx_queues;
2301 ret = 0;
2302 break;
3e05334f
AD		 2303 case ETHTOOL_GRXCLSRLCNT:
2304 cmd->rule_cnt = adapter->fdir_filter_count;
2305 ret = 0;
2306 break;
2307 case ETHTOOL_GRXCLSRULE:
2308 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2309 break;
2310 case ETHTOOL_GRXCLSRLALL:
815c7db5 2311 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2312 break;
91cd94bf
AD		 2313 default:
2314 break;
2315 }
2316
2317 return ret;
2318}
2319
e4911d57
AD		 2320static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2321 struct ixgbe_fdir_filter *input,
2322 u16 sw_idx)
2323{
2324 struct ixgbe_hw *hw = &adapter->hw;
2325 struct hlist_node *node, *node2, *parent;
2326 struct ixgbe_fdir_filter *rule;
2327 int err = -EINVAL;
2328
2329 parent = NULL;
2330 rule = NULL;
2331
2332 hlist_for_each_entry_safe(rule, node, node2,
2333 &adapter->fdir_filter_list, fdir_node) {
2334 /* hash found, or no matching entry */
2335 if (rule->sw_idx >= sw_idx)
2336 break;
2337 parent = node;
2338 }
2339
2340 /* if there is an old rule occupying our place remove it */
2341 if (rule && (rule->sw_idx == sw_idx)) {
2342 if (!input || (rule->filter.formatted.bkt_hash !=
2343 input->filter.formatted.bkt_hash)) {
2344 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2345 &rule->filter,
2346 sw_idx);
2347 }
2348
2349 hlist_del(&rule->fdir_node);
2350 kfree(rule);
2351 adapter->fdir_filter_count--;
2352 }
2353
2354 /*
2355 * If no input this was a delete, err should be 0 if a rule was
2356 * successfully found and removed from the list else -EINVAL
2357 */
2358 if (!input)
2359 return err;
2360
2361 /* initialize node and set software index */
2362 INIT_HLIST_NODE(&input->fdir_node);
2363
2364 /* add filter to the list */
2365 if (parent)
2366 hlist_add_after(parent, &input->fdir_node);
2367 else
2368 hlist_add_head(&input->fdir_node,
2369 &adapter->fdir_filter_list);
2370
2371 /* update counts */
2372 adapter->fdir_filter_count++;
2373
2374 return 0;
2375}
2376
2377static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2378 u8 *flow_type)
2379{
2380 switch (fsp->flow_type & ~FLOW_EXT) {
2381 case TCP_V4_FLOW:
2382 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2383 break;
2384 case UDP_V4_FLOW:
2385 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2386 break;
2387 case SCTP_V4_FLOW:
2388 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2389 break;
2390 case IP_USER_FLOW:
2391 switch (fsp->h_u.usr_ip4_spec.proto) {
2392 case IPPROTO_TCP:
2393 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2394 break;
2395 case IPPROTO_UDP:
2396 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2397 break;
2398 case IPPROTO_SCTP:
2399 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2400 break;
2401 case 0:
2402 if (!fsp->m_u.usr_ip4_spec.proto) {
2403 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2404 break;
2405 }
2406 default:
2407 return 0;
2408 }
2409 break;
2410 default:
2411 return 0;
2412 }
2413
2414 return 1;
2415}
2416
2417static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2418 struct ethtool_rxnfc *cmd)
2419{
2420 struct ethtool_rx_flow_spec *fsp =
2421 (struct ethtool_rx_flow_spec *)&cmd->fs;
2422 struct ixgbe_hw *hw = &adapter->hw;
2423 struct ixgbe_fdir_filter *input;
2424 union ixgbe_atr_input mask;
2425 int err;
2426
2427 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2428 return -EOPNOTSUPP;
2429
2430 /*
2431 * Don't allow programming if the action is a queue greater than
2432 * the number of online Rx queues.
2433 */
2434 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2435 (fsp->ring_cookie >= adapter->num_rx_queues))
2436 return -EINVAL;
2437
2438 /* Don't allow indexes to exist outside of available space */
2439 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2440 e_err(drv, "Location out of range\n");
2441 return -EINVAL;
2442 }
2443
2444 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2445 if (!input)
2446 return -ENOMEM;
2447
2448 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2449
2450 /* set SW index */
2451 input->sw_idx = fsp->location;
2452
2453 /* record flow type */
2454 if (!ixgbe_flowspec_to_flow_type(fsp,
2455 &input->filter.formatted.flow_type)) {
2456 e_err(drv, "Unrecognized flow type\n");
2457 goto err_out;
2458 }
2459
2460 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2461 IXGBE_ATR_L4TYPE_MASK;
2462
2463 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2464 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2465
2466 /* Copy input into formatted structures */
2467 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2468 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2469 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2470 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2471 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2472 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2473 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2474 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2475
2476 if (fsp->flow_type & FLOW_EXT) {
2477 input->filter.formatted.vm_pool =
2478 (unsigned char)ntohl(fsp->h_ext.data[1]);
2479 mask.formatted.vm_pool =
2480 (unsigned char)ntohl(fsp->m_ext.data[1]);
2481 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2482 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2483 input->filter.formatted.flex_bytes =
2484 fsp->h_ext.vlan_etype;
2485 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2486 }
2487
2488 /* determine if we need to drop or route the packet */
2489 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2490 input->action = IXGBE_FDIR_DROP_QUEUE;
2491 else
2492 input->action = fsp->ring_cookie;
2493
2494 spin_lock(&adapter->fdir_perfect_lock);
2495
2496 if (hlist_empty(&adapter->fdir_filter_list)) {
2497 /* save mask and program input mask into HW */
2498 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2499 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2500 if (err) {
2501 e_err(drv, "Error writing mask\n");
2502 goto err_out_w_lock;
2503 }
2504 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2505 e_err(drv, "Only one mask supported per port\n");
2506 goto err_out_w_lock;
2507 }
2508
2509 /* apply mask and compute/store hash */
2510 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2511
2512 /* program filters to filter memory */
2513 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2514 &input->filter, input->sw_idx,
1f4d5183
AD		 2515 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2516 IXGBE_FDIR_DROP_QUEUE :
e4911d57
AD		 2517 adapter->rx_ring[input->action]->reg_idx);
2518 if (err)
2519 goto err_out_w_lock;
2520
2521 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2522
2523 spin_unlock(&adapter->fdir_perfect_lock);
2524
2525 return err;
2526err_out_w_lock:
2527 spin_unlock(&adapter->fdir_perfect_lock);
2528err_out:
2529 kfree(input);
2530 return -EINVAL;
2531}
2532
2533static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2534 struct ethtool_rxnfc *cmd)
2535{
2536 struct ethtool_rx_flow_spec *fsp =
2537 (struct ethtool_rx_flow_spec *)&cmd->fs;
2538 int err;
2539
2540 spin_lock(&adapter->fdir_perfect_lock);
2541 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2542 spin_unlock(&adapter->fdir_perfect_lock);
2543
2544 return err;
2545}
2546
2547static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2548{
2549 struct ixgbe_adapter *adapter = netdev_priv(dev);
2550 int ret = -EOPNOTSUPP;
2551
2552 switch (cmd->cmd) {
2553 case ETHTOOL_SRXCLSRLINS:
2554 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2555 break;
2556 case ETHTOOL_SRXCLSRLDEL:
2557 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2558 break;
2559 default:
2560 break;
2561 }
2562
2563 return ret;
2564}
2565
b9804972 2566static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2567 .get_settings = ixgbe_get_settings,
2568 .set_settings = ixgbe_set_settings,
2569 .get_drvinfo = ixgbe_get_drvinfo,
2570 .get_regs_len = ixgbe_get_regs_len,
2571 .get_regs = ixgbe_get_regs,
2572 .get_wol = ixgbe_get_wol,
e63d9762 2573 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2574 .nway_reset = ixgbe_nway_reset,
2575 .get_link = ethtool_op_get_link,
2576 .get_eeprom_len = ixgbe_get_eeprom_len,
2577 .get_eeprom = ixgbe_get_eeprom,
2578 .get_ringparam = ixgbe_get_ringparam,
2579 .set_ringparam = ixgbe_set_ringparam,
2580 .get_pauseparam = ixgbe_get_pauseparam,
2581 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 2582 .get_msglevel = ixgbe_get_msglevel,
2583 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 2584 .self_test = ixgbe_diag_test,
9a799d71 2585 .get_strings = ixgbe_get_strings,
66e6961c 2586 .set_phys_id = ixgbe_set_phys_id,
b4617240 2587 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2588 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2589 .get_coalesce = ixgbe_get_coalesce,
2590 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 2591 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 2592 .set_rxnfc = ixgbe_set_rxnfc,
9a799d71
AK		 2593};
2594
2595void ixgbe_set_ethtool_ops(struct net_device *netdev)
2596{
2597 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2598}
Linux kernel - Deliverables
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