projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9a799d71 AK |
1 | /******************************************************************************* |
| 2 | ||
| 3 | Intel 10 Gigabit PCI Express Linux driver | |
| 37689010 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
| 9a799d71 AK |
5 | |
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms and conditions of the GNU General Public License, | |
| 8 | version 2, as published by the Free Software Foundation. | |
| 9 | ||
| 10 | This program is distributed in the hope it will be useful, but WITHOUT | |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 13 | more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License along with | |
| 16 | this program; if not, write to the Free Software Foundation, Inc., | |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 | ||
| 19 | The full GNU General Public License is included in this distribution in | |
| 20 | the file called "COPYING". | |
| 21 | ||
| 22 | Contact Information: | |
| b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
| 9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 26 | ||
| 27 | *******************************************************************************/ | |
| 28 | ||
| 29 | #ifndef _IXGBE_TYPE_H_ | |
| 30 | #define _IXGBE_TYPE_H_ | |
| 31 | ||
| 32 | #include <linux/types.h> | |
| 6b73e10d | 33 | #include <linux/mdio.h> |
| 32e7bfc4 | 34 | #include <linux/netdevice.h> |
| 9a799d71 | 35 | |
| 9a799d71 | 36 | /* Device IDs */ |
| 1e336d0f | 37 | #define IXGBE_DEV_ID_82598 0x10B6 |
| 2f21bdd3 | 38 | #define IXGBE_DEV_ID_82598_BX 0x1508 |
| 9a799d71 AK |
39 | #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 |
| 40 | #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 | |
| c4900be0 | 41 | #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB |
| 0befdb3e | 42 | #define IXGBE_DEV_ID_82598AT 0x10C8 |
| 3845bec0 | 43 | #define IXGBE_DEV_ID_82598AT2 0x150B |
| 9a799d71 | 44 | #define IXGBE_DEV_ID_82598EB_CX4 0x10DD |
| 8d792cd9 | 45 | #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC |
| c4900be0 DS |
46 | #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 |
| 47 | #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 | |
| b95f5fcb | 48 | #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 |
| 11afc1b1 | 49 | #define IXGBE_DEV_ID_82599_KX4 0x10F7 |
| dbfec662 | 50 | #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 |
| 74757d49 | 51 | #define IXGBE_DEV_ID_82599_KR 0x1517 |
| 119fc60a | 52 | #define IXGBE_DEV_ID_82599_T3_LOM 0x151C |
| 8911184f | 53 | #define IXGBE_DEV_ID_82599_CX4 0x10F9 |
| 11afc1b1 | 54 | #define IXGBE_DEV_ID_82599_SFP 0x10FB |
| dbffcb21 DS |
55 | #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a |
| 56 | #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 | |
| 0b077fea | 57 | #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 |
| 87557440 | 58 | #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 |
| b6dfd939 | 59 | #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 |
| 0e22d043 | 60 | #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 |
| 5700ff26 | 61 | #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B |
| 00103a6c ET |
62 | #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159 |
| 63 | #define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D | |
| 64 | #define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008 | |
| 65 | #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976 | |
| 66 | #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE | |
| f8a06c2c | 67 | #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 |
| 38ad1c8e | 68 | #define IXGBE_DEV_ID_82599_SFP_EM 0x1507 |
| 4c40ef02 | 69 | #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D |
| 7d145282 | 70 | #define IXGBE_DEV_ID_82599EN_SFP 0x1557 |
| 5daebbb0 | 71 | #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 |
| 1fcf03e6 | 72 | #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC |
| 312eb931 | 73 | #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 |
| 50d6c681 | 74 | #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C |
| 4f6290cf | 75 | #define IXGBE_DEV_ID_82599_LS 0x154F |
| b93a2226 | 76 | #define IXGBE_DEV_ID_X540T 0x1528 |
| 9e791e4a | 77 | #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A |
| 8f58332b | 78 | #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 |
| df376f0d | 79 | #define IXGBE_DEV_ID_X540T1 0x1560 |
| 9a799d71 | 80 | |
| 6a14ee0c | 81 | #define IXGBE_DEV_ID_X550T 0x1563 |
| a711ad89 | 82 | #define IXGBE_DEV_ID_X550T1 0x15D1 |
| 6a14ee0c DS |
83 | #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA |
| 84 | #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB | |
| 85 | #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC | |
| 86 | #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD | |
| 87 | #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE | |
| f572b2c4 MR |
88 | #define IXGBE_DEV_ID_X550EM_A_KR 0x15C2 |
| 89 | #define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3 | |
| 207969b9 | 90 | #define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4 |
| 200157c2 MR |
91 | #define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6 |
| 92 | #define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7 | |
| 92ed8430 | 93 | #define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8 |
| c898fe28 | 94 | #define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE |
| 207969b9 MR |
95 | |
| 96 | /* VF Device IDs */ | |
| 61ff59d8 PB |
97 | #define IXGBE_DEV_ID_82599_VF 0x10ED |
| 98 | #define IXGBE_DEV_ID_X540_VF 0x1515 | |
| 9a75a1ac DS |
99 | #define IXGBE_DEV_ID_X550_VF 0x1565 |
| 100 | #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 | |
| 207969b9 | 101 | #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 |
| c6bda30a | 102 | |
| 9a900eca DS |
103 | #define IXGBE_CAT(r, m) IXGBE_##r##_##m |
| 104 | ||
| 105 | #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)]) | |
| 106 | ||
| 9a799d71 AK |
107 | /* General Registers */ |
| 108 | #define IXGBE_CTRL 0x00000 | |
| 109 | #define IXGBE_STATUS 0x00008 | |
| 110 | #define IXGBE_CTRL_EXT 0x00018 | |
| 111 | #define IXGBE_ESDP 0x00020 | |
| 112 | #define IXGBE_EODSDP 0x00028 | |
| 9a900eca DS |
113 | |
| 114 | #define IXGBE_I2CCTL_8259X 0x00028 | |
| 115 | #define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_8259X | |
| 116 | #define IXGBE_I2CCTL_X550 0x15F5C | |
| 117 | #define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550 | |
| 118 | #define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550 | |
| 119 | #define IXGBE_I2CCTL(_hw) IXGBE_BY_MAC((_hw), I2CCTL) | |
| 120 | ||
| 9a799d71 AK |
121 | #define IXGBE_LEDCTL 0x00200 |
| 122 | #define IXGBE_FRTIMER 0x00048 | |
| 123 | #define IXGBE_TCPTIMER 0x0004C | |
| 11afc1b1 PW |
124 | #define IXGBE_CORESPARE 0x00600 |
| 125 | #define IXGBE_EXVET 0x05078 | |
| 9a799d71 AK |
126 | |
| 127 | /* NVM Registers */ | |
| 9a900eca DS |
128 | #define IXGBE_EEC_8259X 0x10010 |
| 129 | #define IXGBE_EEC_X540 IXGBE_EEC_8259X | |
| 130 | #define IXGBE_EEC_X550 IXGBE_EEC_8259X | |
| 131 | #define IXGBE_EEC_X550EM_x IXGBE_EEC_8259X | |
| 132 | #define IXGBE_EEC_X550EM_a 0x15FF8 | |
| 133 | #define IXGBE_EEC(_hw) IXGBE_BY_MAC((_hw), EEC) | |
| 9a799d71 | 134 | #define IXGBE_EERD 0x10014 |
| 21ce849b | 135 | #define IXGBE_EEWR 0x10018 |
| 9a900eca DS |
136 | #define IXGBE_FLA_8259X 0x1001C |
| 137 | #define IXGBE_FLA_X540 IXGBE_FLA_8259X | |
| 138 | #define IXGBE_FLA_X550 IXGBE_FLA_8259X | |
| 139 | #define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X | |
| 207969b9 | 140 | #define IXGBE_FLA_X550EM_a 0x15F68 |
| 9a900eca | 141 | #define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA) |
| 9a799d71 AK |
142 | #define IXGBE_EEMNGCTL 0x10110 |
| 143 | #define IXGBE_EEMNGDATA 0x10114 | |
| 144 | #define IXGBE_FLMNGCTL 0x10118 | |
| 145 | #define IXGBE_FLMNGDATA 0x1011C | |
| 146 | #define IXGBE_FLMNGCNT 0x10120 | |
| 147 | #define IXGBE_FLOP 0x1013C | |
| 9a900eca DS |
148 | #define IXGBE_GRC_8259X 0x10200 |
| 149 | #define IXGBE_GRC_X540 IXGBE_GRC_8259X | |
| 150 | #define IXGBE_GRC_X550 IXGBE_GRC_8259X | |
| 151 | #define IXGBE_GRC_X550EM_x IXGBE_GRC_8259X | |
| 152 | #define IXGBE_GRC_X550EM_a 0x15F64 | |
| 153 | #define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC) | |
| 154 | ||
| 11afc1b1 PW |
155 | /* General Receive Control */ |
| 156 | #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ | |
| 888be1a1 | 157 | #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ |
| 11afc1b1 PW |
158 | |
| 159 | #define IXGBE_VPDDIAG0 0x10204 | |
| 160 | #define IXGBE_VPDDIAG1 0x10208 | |
| 161 | ||
| 162 | /* I2CCTL Bit Masks */ | |
| 9a900eca DS |
163 | #define IXGBE_I2C_CLK_IN_8259X 0x00000001 |
| 164 | #define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN_8259X | |
| 165 | #define IXGBE_I2C_CLK_IN_X550 0x00004000 | |
| 166 | #define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550 | |
| 167 | #define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550 | |
| 168 | #define IXGBE_I2C_CLK_IN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN) | |
| 169 | ||
| 170 | #define IXGBE_I2C_CLK_OUT_8259X 0x00000002 | |
| 171 | #define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT_8259X | |
| 172 | #define IXGBE_I2C_CLK_OUT_X550 0x00000200 | |
| 173 | #define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550 | |
| 174 | #define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550 | |
| 175 | #define IXGBE_I2C_CLK_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT) | |
| 176 | ||
| 177 | #define IXGBE_I2C_DATA_IN_8259X 0x00000004 | |
| 178 | #define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN_8259X | |
| 179 | #define IXGBE_I2C_DATA_IN_X550 0x00001000 | |
| 180 | #define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550 | |
| 181 | #define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550 | |
| 182 | #define IXGBE_I2C_DATA_IN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN) | |
| 183 | ||
| 184 | #define IXGBE_I2C_DATA_OUT_8259X 0x00000008 | |
| 185 | #define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT_8259X | |
| 186 | #define IXGBE_I2C_DATA_OUT_X550 0x00000400 | |
| 187 | #define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550 | |
| 188 | #define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550 | |
| 189 | #define IXGBE_I2C_DATA_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT) | |
| 190 | ||
| 191 | #define IXGBE_I2C_DATA_OE_N_EN_8259X 0 | |
| 192 | #define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN_8259X | |
| 193 | #define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800 | |
| 194 | #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550 | |
| 195 | #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550 | |
| 196 | #define IXGBE_I2C_DATA_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) | |
| 197 | ||
| 198 | #define IXGBE_I2C_BB_EN_8259X 0 | |
| 199 | #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN_8259X | |
| 200 | #define IXGBE_I2C_BB_EN_X550 0x00000100 | |
| 201 | #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 | |
| 202 | #define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550 | |
| 203 | #define IXGBE_I2C_BB_EN(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) | |
| 204 | ||
| 205 | #define IXGBE_I2C_CLK_OE_N_EN_8259X 0 | |
| 206 | #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN_8259X | |
| 207 | #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 | |
| 208 | #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 | |
| 209 | #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550 | |
| 210 | #define IXGBE_I2C_CLK_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) | |
| 211 | ||
| 8f56e4b9 | 212 | #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 |
| 11afc1b1 | 213 | |
| e1ea9158 DS |
214 | #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8 |
| 215 | #define IXGBE_EMC_INTERNAL_DATA 0x00 | |
| 216 | #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20 | |
| 217 | #define IXGBE_EMC_DIODE1_DATA 0x01 | |
| 218 | #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19 | |
| 219 | #define IXGBE_EMC_DIODE2_DATA 0x23 | |
| 220 | #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A | |
| 221 | ||
| 222 | #define IXGBE_MAX_SENSORS 3 | |
| 223 | ||
| 224 | struct ixgbe_thermal_diode_data { | |
| 225 | u8 location; | |
| 226 | u8 temp; | |
| 227 | u8 caution_thresh; | |
| 228 | u8 max_op_thresh; | |
| 229 | }; | |
| 230 | ||
| 231 | struct ixgbe_thermal_sensor_data { | |
| 232 | struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS]; | |
| 233 | }; | |
| 234 | ||
| 9a799d71 AK |
235 | /* Interrupt Registers */ |
| 236 | #define IXGBE_EICR 0x00800 | |
| 237 | #define IXGBE_EICS 0x00808 | |
| 238 | #define IXGBE_EIMS 0x00880 | |
| 239 | #define IXGBE_EIMC 0x00888 | |
| 240 | #define IXGBE_EIAC 0x00810 | |
| 241 | #define IXGBE_EIAM 0x00890 | |
| 11afc1b1 PW |
242 | #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) |
| 243 | #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) | |
| 244 | #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) | |
| 245 | #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) | |
| 509ee935 JB |
246 | /* |
| 247 | * 82598 EITR is 16 bits but set the limits based on the max | |
| 248 | * supported by all ixgbe hardware. 82599 EITR is only 12 bits, | |
| 249 | * with the lower 3 always zero. | |
| 250 | */ | |
| 251 | #define IXGBE_MAX_INT_RATE 488281 | |
| 252 | #define IXGBE_MIN_INT_RATE 956 | |
| 253 | #define IXGBE_MAX_EITR 0x00000FF8 | |
| 254 | #define IXGBE_MIN_EITR 8 | |
| 11afc1b1 | 255 | #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ |
| e7cf745b | 256 | (0x012300 + (((_i) - 24) * 4))) |
| 509ee935 | 257 | #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 |
| 11afc1b1 PW |
258 | #define IXGBE_EITR_LLI_MOD 0x00008000 |
| 259 | #define IXGBE_EITR_CNT_WDIS 0x80000000 | |
| c44ade9e | 260 | #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ |
| 11afc1b1 PW |
261 | #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ |
| 262 | #define IXGBE_EITRSEL 0x00894 | |
| 9a799d71 AK |
263 | #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ |
| 264 | #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ | |
| c44ade9e | 265 | #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) |
| 9a799d71 AK |
266 | #define IXGBE_GPIE 0x00898 |
| 267 | ||
| 268 | /* Flow Control Registers */ | |
| 11afc1b1 PW |
269 | #define IXGBE_FCADBUL 0x03210 |
| 270 | #define IXGBE_FCADBUH 0x03214 | |
| 271 | #define IXGBE_FCAMACL 0x04328 | |
| 272 | #define IXGBE_FCAMACH 0x0432C | |
| 273 | #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 274 | #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 9a799d71 AK |
275 | #define IXGBE_PFCTOP 0x03008 |
| 276 | #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ | |
| 277 | #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ | |
| 278 | #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ | |
| 279 | #define IXGBE_FCRTV 0x032A0 | |
| 11afc1b1 | 280 | #define IXGBE_FCCFG 0x03D00 |
| 9a799d71 AK |
281 | #define IXGBE_TFCS 0x0CE00 |
| 282 | ||
| 283 | /* Receive DMA Registers */ | |
| 11afc1b1 | 284 | #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ |
| 795be954 | 285 | (0x0D000 + (((_i) - 64) * 0x40))) |
| 11afc1b1 | 286 | #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ |
| 795be954 | 287 | (0x0D004 + (((_i) - 64) * 0x40))) |
| 11afc1b1 | 288 | #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ |
| 795be954 | 289 | (0x0D008 + (((_i) - 64) * 0x40))) |
| 11afc1b1 | 290 | #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ |
| 795be954 | 291 | (0x0D010 + (((_i) - 64) * 0x40))) |
| 11afc1b1 | 292 | #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ |
| 795be954 | 293 | (0x0D018 + (((_i) - 64) * 0x40))) |
| 11afc1b1 | 294 | #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ |
| 795be954 | 295 | (0x0D028 + (((_i) - 64) * 0x40))) |
| 83dfde40 | 296 | #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ |
| 795be954 | 297 | (0x0D02C + (((_i) - 64) * 0x40))) |
| 83dfde40 | 298 | #define IXGBE_RSCDBU 0x03028 |
| 11afc1b1 PW |
299 | #define IXGBE_RDDCC 0x02F20 |
| 300 | #define IXGBE_RXMEMWRAP 0x03190 | |
| 301 | #define IXGBE_STARCTRL 0x03024 | |
| c44ade9e JB |
302 | /* |
| 303 | * Split and Replication Receive Control Registers | |
| 304 | * 00-15 : 0x02100 + n*4 | |
| 305 | * 16-64 : 0x01014 + n*0x40 | |
| 306 | * 64-127: 0x0D014 + (n-64)*0x40 | |
| 307 | */ | |
| 308 | #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ | |
| e7cf745b | 309 | (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ |
| 795be954 | 310 | (0x0D014 + (((_i) - 64) * 0x40)))) |
| c44ade9e JB |
311 | /* |
| 312 | * Rx DCA Control Register: | |
| 313 | * 00-15 : 0x02200 + n*4 | |
| 314 | * 16-64 : 0x0100C + n*0x40 | |
| 315 | * 64-127: 0x0D00C + (n-64)*0x40 | |
| 316 | */ | |
| 317 | #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ | |
| e7cf745b | 318 | (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ |
| 795be954 | 319 | (0x0D00C + (((_i) - 64) * 0x40)))) |
| c44ade9e | 320 | #define IXGBE_RDRXCTL 0x02F00 |
| 9a799d71 | 321 | #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) |
| e7cf745b | 322 | /* 8 of these 0x03C00 - 0x03C1C */ |
| 9a799d71 AK |
323 | #define IXGBE_RXCTRL 0x03000 |
| 324 | #define IXGBE_DROPEN 0x03D04 | |
| 325 | #define IXGBE_RXPBSIZE_SHIFT 10 | |
| 326 | ||
| 327 | /* Receive Registers */ | |
| 328 | #define IXGBE_RXCSUM 0x05000 | |
| 329 | #define IXGBE_RFCTL 0x05008 | |
| c44ade9e JB |
330 | #define IXGBE_DRECCCTL 0x02F08 |
| 331 | #define IXGBE_DRECCCTL_DISABLE 0 | |
| 332 | /* Multicast Table Array - 128 entries */ | |
| 9a799d71 | 333 | #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) |
| 11afc1b1 | 334 | #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ |
| e7cf745b | 335 | (0x0A200 + ((_i) * 8))) |
| 11afc1b1 | 336 | #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ |
| e7cf745b | 337 | (0x0A204 + ((_i) * 8))) |
| 11afc1b1 PW |
338 | #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) |
| 339 | #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) | |
| c44ade9e | 340 | /* Packet split receive type */ |
| 11afc1b1 | 341 | #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ |
| e7cf745b | 342 | (0x0EA00 + ((_i) * 4))) |
| c44ade9e | 343 | /* array of 4096 1-bit vlan filters */ |
| 9a799d71 | 344 | #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) |
| c44ade9e | 345 | /*array of 4096 4-bit vlan vmdq indices */ |
| 9a799d71 | 346 | #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) |
| 9a799d71 AK |
347 | #define IXGBE_FCTRL 0x05080 |
| 348 | #define IXGBE_VLNCTRL 0x05088 | |
| 349 | #define IXGBE_MCSTCTRL 0x05090 | |
| 350 | #define IXGBE_MRQC 0x05818 | |
| 11afc1b1 PW |
351 | #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ |
| 352 | #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ | |
| 353 | #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ | |
| 354 | #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ | |
| 355 | #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ | |
| 356 | #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ | |
| 357 | #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ | |
| 358 | #define IXGBE_RQTC 0x0EC70 | |
| 359 | #define IXGBE_MTQC 0x08120 | |
| 360 | #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ | |
| 361 | #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ | |
| 7f01648a | 362 | #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ |
| 6d4c96ad DS |
363 | #define IXGBE_PFFLPL 0x050B0 |
| 364 | #define IXGBE_PFFLPH 0x050B4 | |
| 83dfde40 ET |
365 | #define IXGBE_VT_CTL 0x051B0 |
| 366 | #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ | |
| 367 | #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */ | |
| 368 | #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ | |
| 369 | #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ | |
| 370 | #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) | |
| 371 | #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) | |
| 372 | #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) | |
| 373 | #define IXGBE_QDE 0x2F04 | |
| 374 | #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ | |
| 375 | #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ | |
| 376 | #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) | |
| 377 | #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) | |
| 378 | #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) | |
| 379 | #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) | |
| 207969b9 MR |
380 | #define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */ |
| 381 | #define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */ | |
| 83dfde40 ET |
382 | #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ |
| 383 | #define IXGBE_RXFECCERR0 0x051B8 | |
| 11afc1b1 | 384 | #define IXGBE_LLITHRESH 0x0EC90 |
| 9a799d71 AK |
385 | #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 386 | #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 387 | #define IXGBE_IMIRVP 0x05AC0 | |
| c44ade9e | 388 | #define IXGBE_VMD_CTL 0x0581C |
| 9a799d71 | 389 | #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ |
| 0f9b232b | 390 | #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */ |
| 9a799d71 AK |
391 | #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ |
| 392 | ||
| 9a75a1ac DS |
393 | /* Registers for setting up RSS on X550 with SRIOV |
| 394 | * _p - pool number (0..63) | |
| 395 | * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) | |
| 396 | */ | |
| 397 | #define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) | |
| 398 | #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) | |
| 399 | #define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) | |
| 400 | ||
| bfde493e PWJ |
401 | /* Flow Director registers */ |
| 402 | #define IXGBE_FDIRCTRL 0x0EE00 | |
| 403 | #define IXGBE_FDIRHKEY 0x0EE68 | |
| 404 | #define IXGBE_FDIRSKEY 0x0EE6C | |
| 405 | #define IXGBE_FDIRDIP4M 0x0EE3C | |
| 406 | #define IXGBE_FDIRSIP4M 0x0EE40 | |
| 407 | #define IXGBE_FDIRTCPM 0x0EE44 | |
| 408 | #define IXGBE_FDIRUDPM 0x0EE48 | |
| 5532408b | 409 | #define IXGBE_FDIRSCTPM 0x0EE78 |
| bfde493e PWJ |
410 | #define IXGBE_FDIRIP6M 0x0EE74 |
| 411 | #define IXGBE_FDIRM 0x0EE70 | |
| 412 | ||
| 413 | /* Flow Director Stats registers */ | |
| 414 | #define IXGBE_FDIRFREE 0x0EE38 | |
| 415 | #define IXGBE_FDIRLEN 0x0EE4C | |
| 416 | #define IXGBE_FDIRUSTAT 0x0EE50 | |
| 417 | #define IXGBE_FDIRFSTAT 0x0EE54 | |
| 418 | #define IXGBE_FDIRMATCH 0x0EE58 | |
| 419 | #define IXGBE_FDIRMISS 0x0EE5C | |
| 420 | ||
| 421 | /* Flow Director Programming registers */ | |
| 422 | #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ | |
| 423 | #define IXGBE_FDIRIPSA 0x0EE18 | |
| 424 | #define IXGBE_FDIRIPDA 0x0EE1C | |
| 425 | #define IXGBE_FDIRPORT 0x0EE20 | |
| 426 | #define IXGBE_FDIRVLAN 0x0EE24 | |
| 427 | #define IXGBE_FDIRHASH 0x0EE28 | |
| 428 | #define IXGBE_FDIRCMD 0x0EE2C | |
| 429 | ||
| 9a799d71 | 430 | /* Transmit DMA registers */ |
| c44ade9e | 431 | #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ |
| 9a799d71 AK |
432 | #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) |
| 433 | #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) | |
| 434 | #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) | |
| 435 | #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) | |
| 436 | #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) | |
| 437 | #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) | |
| 438 | #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) | |
| 439 | #define IXGBE_DTXCTL 0x07E00 | |
| c44ade9e | 440 | |
| a985b6c3 GR |
441 | #define IXGBE_DMATXCTL 0x04A80 |
| 442 | #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ | |
| 7f870475 | 443 | #define IXGBE_PFDTXGSWC 0x08220 |
| 11afc1b1 PW |
444 | #define IXGBE_DTXMXSZRQ 0x08100 |
| 445 | #define IXGBE_DTXTCPFLGL 0x04A88 | |
| 446 | #define IXGBE_DTXTCPFLGH 0x04A8C | |
| 447 | #define IXGBE_LBDRPEN 0x0CA00 | |
| 448 | #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ | |
| 449 | ||
| 450 | #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ | |
| 451 | #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ | |
| 452 | #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ | |
| 207969b9 MR |
453 | #define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */ |
| 454 | #define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */ | |
| 11afc1b1 | 455 | #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ |
| 7f870475 GR |
456 | |
| 457 | #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ | |
| a985b6c3 GR |
458 | |
| 459 | /* Anti-spoofing defines */ | |
| 460 | #define IXGBE_SPOOF_MACAS_MASK 0xFF | |
| 461 | #define IXGBE_SPOOF_VLANAS_MASK 0xFF00 | |
| 462 | #define IXGBE_SPOOF_VLANAS_SHIFT 8 | |
| 5b7f000f DS |
463 | #define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000 |
| 464 | #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16 | |
| a985b6c3 GR |
465 | #define IXGBE_PFVFSPOOF_REG_COUNT 8 |
| 466 | ||
| c44ade9e | 467 | #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ |
| 11afc1b1 PW |
468 | /* Tx DCA Control register : 128 of these (0-127) */ |
| 469 | #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) | |
| 9a799d71 | 470 | #define IXGBE_TIPG 0x0CB00 |
| c44ade9e | 471 | #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ |
| 9a799d71 AK |
472 | #define IXGBE_MNGTXMAP 0x0CD10 |
| 473 | #define IXGBE_TIPG_FIBER_DEFAULT 3 | |
| 474 | #define IXGBE_TXPBSIZE_SHIFT 10 | |
| 475 | ||
| 476 | /* Wake up registers */ | |
| 477 | #define IXGBE_WUC 0x05800 | |
| 478 | #define IXGBE_WUFC 0x05808 | |
| 479 | #define IXGBE_WUS 0x05810 | |
| 480 | #define IXGBE_IPAV 0x05838 | |
| 481 | #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ | |
| 482 | #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ | |
| c44ade9e | 483 | |
| 9a799d71 AK |
484 | #define IXGBE_WUPL 0x05900 |
| 485 | #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ | |
| 3f207800 | 486 | #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ |
| 795be954 AD |
487 | #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ |
| 488 | #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host | |
| 489 | * Filter Table */ | |
| 11afc1b1 | 490 | |
| a21d0822 ET |
491 | /* masks for accessing VXLAN and GENEVE UDP ports */ |
| 492 | #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */ | |
| 493 | #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */ | |
| 494 | #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */ | |
| 495 | ||
| 496 | #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16 | |
| 497 | ||
| 11afc1b1 PW |
498 | #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 |
| 499 | #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 | |
| 500 | ||
| 501 | /* Each Flexible Filter is at most 128 (0x80) bytes in length */ | |
| 502 | #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 | |
| 503 | #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ | |
| 504 | #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ | |
| 505 | ||
| 506 | /* Definitions for power management and wakeup registers */ | |
| 507 | /* Wake Up Control */ | |
| 508 | #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ | |
| 509 | #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ | |
| 888be1a1 | 510 | #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ |
| 11afc1b1 PW |
511 | |
| 512 | /* Wake Up Filter Control */ | |
| 513 | #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | |
| 514 | #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | |
| 515 | #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | |
| 516 | #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | |
| 517 | #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | |
| 518 | #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | |
| 519 | #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ | |
| 520 | #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ | |
| 521 | #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ | |
| 522 | ||
| 523 | #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ | |
| 524 | #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ | |
| 525 | #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ | |
| 526 | #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ | |
| 527 | #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ | |
| 528 | #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ | |
| 529 | #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ | |
| 530 | #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ | |
| 531 | #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */ | |
| 83dfde40 | 532 | #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */ |
| 11afc1b1 PW |
533 | #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ |
| 534 | ||
| 535 | /* Wake Up Status */ | |
| 536 | #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC | |
| 537 | #define IXGBE_WUS_MAG IXGBE_WUFC_MAG | |
| 538 | #define IXGBE_WUS_EX IXGBE_WUFC_EX | |
| 539 | #define IXGBE_WUS_MC IXGBE_WUFC_MC | |
| 540 | #define IXGBE_WUS_BC IXGBE_WUFC_BC | |
| 541 | #define IXGBE_WUS_ARP IXGBE_WUFC_ARP | |
| 542 | #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 | |
| 543 | #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 | |
| 544 | #define IXGBE_WUS_MNG IXGBE_WUFC_MNG | |
| 545 | #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 | |
| 546 | #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 | |
| 547 | #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 | |
| 548 | #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 | |
| 549 | #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 | |
| 550 | #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 | |
| 551 | #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS | |
| 552 | ||
| 553 | /* Wake Up Packet Length */ | |
| 554 | #define IXGBE_WUPL_LENGTH_MASK 0xFFFF | |
| 555 | ||
| 556 | /* DCB registers */ | |
| 9da712d2 | 557 | #define MAX_TRAFFIC_CLASS 8 |
| 4de2a022 | 558 | #define X540_TRAFFIC_CLASS 4 |
| 8829009d | 559 | #define DEF_TRAFFIC_CLASS 1 |
| 9a799d71 AK |
560 | #define IXGBE_RMCS 0x03D00 |
| 561 | #define IXGBE_DPMCS 0x07F40 | |
| 562 | #define IXGBE_PDPMCS 0x0CD00 | |
| 563 | #define IXGBE_RUPPBMR 0x050A0 | |
| 564 | #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 565 | #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 566 | #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ | |
| 567 | #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ | |
| 568 | #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 569 | #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 570 | ||
| 11afc1b1 PW |
571 | /* Security Control Registers */ |
| 572 | #define IXGBE_SECTXCTRL 0x08800 | |
| 573 | #define IXGBE_SECTXSTAT 0x08804 | |
| 574 | #define IXGBE_SECTXBUFFAF 0x08808 | |
| 575 | #define IXGBE_SECTXMINIFG 0x08810 | |
| 11afc1b1 PW |
576 | #define IXGBE_SECRXCTRL 0x08D00 |
| 577 | #define IXGBE_SECRXSTAT 0x08D04 | |
| 578 | ||
| 579 | /* Security Bit Fields and Masks */ | |
| 580 | #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 | |
| 581 | #define IXGBE_SECTXCTRL_TX_DIS 0x00000002 | |
| 582 | #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 | |
| 583 | ||
| 584 | #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 | |
| 585 | #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 | |
| 586 | ||
| 587 | #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 | |
| 588 | #define IXGBE_SECRXCTRL_RX_DIS 0x00000002 | |
| 589 | ||
| 590 | #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 | |
| 591 | #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 | |
| 592 | ||
| 593 | /* LinkSec (MacSec) Registers */ | |
| 594 | #define IXGBE_LSECTXCAP 0x08A00 | |
| 595 | #define IXGBE_LSECRXCAP 0x08F00 | |
| 596 | #define IXGBE_LSECTXCTRL 0x08A04 | |
| 597 | #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ | |
| 598 | #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ | |
| 599 | #define IXGBE_LSECTXSA 0x08A10 | |
| 600 | #define IXGBE_LSECTXPN0 0x08A14 | |
| 601 | #define IXGBE_LSECTXPN1 0x08A18 | |
| 602 | #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ | |
| 603 | #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ | |
| 604 | #define IXGBE_LSECRXCTRL 0x08F04 | |
| 605 | #define IXGBE_LSECRXSCL 0x08F08 | |
| 606 | #define IXGBE_LSECRXSCH 0x08F0C | |
| 607 | #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ | |
| 608 | #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ | |
| 609 | #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) | |
| 610 | #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ | |
| 611 | #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ | |
| 612 | #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ | |
| 613 | #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ | |
| 614 | #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ | |
| 615 | #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ | |
| 616 | #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ | |
| 617 | #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ | |
| 618 | #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ | |
| 619 | #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ | |
| 620 | #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ | |
| 621 | #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ | |
| 622 | #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ | |
| 623 | #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ | |
| 624 | #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ | |
| 625 | #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ | |
| 626 | #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ | |
| 627 | #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ | |
| 628 | #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ | |
| 629 | ||
| 630 | /* LinkSec (MacSec) Bit Fields and Masks */ | |
| 631 | #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 | |
| 632 | #define IXGBE_LSECTXCAP_SUM_SHIFT 16 | |
| 633 | #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 | |
| 634 | #define IXGBE_LSECRXCAP_SUM_SHIFT 16 | |
| 635 | ||
| 636 | #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 | |
| 637 | #define IXGBE_LSECTXCTRL_DISABLE 0x0 | |
| 638 | #define IXGBE_LSECTXCTRL_AUTH 0x1 | |
| 639 | #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 | |
| 640 | #define IXGBE_LSECTXCTRL_AISCI 0x00000020 | |
| 641 | #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 | |
| 642 | #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 | |
| 643 | ||
| 644 | #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C | |
| 645 | #define IXGBE_LSECRXCTRL_EN_SHIFT 2 | |
| 646 | #define IXGBE_LSECRXCTRL_DISABLE 0x0 | |
| 647 | #define IXGBE_LSECRXCTRL_CHECK 0x1 | |
| 648 | #define IXGBE_LSECRXCTRL_STRICT 0x2 | |
| 649 | #define IXGBE_LSECRXCTRL_DROP 0x3 | |
| 650 | #define IXGBE_LSECRXCTRL_PLSH 0x00000040 | |
| 651 | #define IXGBE_LSECRXCTRL_RP 0x00000080 | |
| 652 | #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 | |
| 653 | ||
| 654 | /* IpSec Registers */ | |
| 655 | #define IXGBE_IPSTXIDX 0x08900 | |
| 656 | #define IXGBE_IPSTXSALT 0x08904 | |
| 657 | #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ | |
| 658 | #define IXGBE_IPSRXIDX 0x08E00 | |
| 659 | #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ | |
| 660 | #define IXGBE_IPSRXSPI 0x08E14 | |
| 661 | #define IXGBE_IPSRXIPIDX 0x08E18 | |
| 662 | #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ | |
| 663 | #define IXGBE_IPSRXSALT 0x08E2C | |
| 664 | #define IXGBE_IPSRXMOD 0x08E30 | |
| 665 | ||
| 666 | #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 | |
| 667 | ||
| 668 | /* DCB registers */ | |
| 669 | #define IXGBE_RTRPCS 0x02430 | |
| 670 | #define IXGBE_RTTDCS 0x04900 | |
| 7f870475 | 671 | #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ |
| 11afc1b1 PW |
672 | #define IXGBE_RTTPCS 0x0CD00 |
| 673 | #define IXGBE_RTRUP2TC 0x03020 | |
| 674 | #define IXGBE_RTTUP2TC 0x0C800 | |
| 675 | #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 83dfde40 | 676 | #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ |
| 11afc1b1 PW |
677 | #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ |
| 678 | #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 679 | #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 680 | #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 681 | #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 682 | #define IXGBE_RTTDQSEL 0x04904 | |
| 683 | #define IXGBE_RTTDT1C 0x04908 | |
| 684 | #define IXGBE_RTTDT1S 0x0490C | |
| 51e409f1 LP |
685 | #define IXGBE_RTTQCNCR 0x08B00 |
| 686 | #define IXGBE_RTTQCNTG 0x04A90 | |
| 687 | #define IXGBE_RTTBCNRD 0x0498C | |
| 688 | #define IXGBE_RTTQCNRR 0x0498C | |
| 11afc1b1 PW |
689 | #define IXGBE_RTTDTECC 0x04990 |
| 690 | #define IXGBE_RTTDTECC_NO_BCN 0x00000100 | |
| 691 | #define IXGBE_RTTBCNRC 0x04984 | |
| ff4ab206 LL |
692 | #define IXGBE_RTTBCNRC_RS_ENA 0x80000000 |
| 693 | #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF | |
| 694 | #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 | |
| 695 | #define IXGBE_RTTBCNRC_RF_INT_MASK \ | |
| 696 | (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) | |
| 7555e83d | 697 | #define IXGBE_RTTBCNRM 0x04980 |
| 51e409f1 | 698 | #define IXGBE_RTTQCNRM 0x04980 |
| c44ade9e | 699 | |
| ea412015 VD |
700 | /* FCoE Direct DMA Context */ |
| 701 | #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) | |
| 83dfde40 | 702 | /* FCoE DMA Context Registers */ |
| bff66176 YZ |
703 | #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ |
| 704 | #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ | |
| 705 | #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ | |
| 706 | #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ | |
| 707 | #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */ | |
| 708 | #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4)) | |
| b4f47a48 JK |
709 | #define IXGBE_FCBUFF_VALID BIT(0) /* DMA Context Valid */ |
| 710 | #define IXGBE_FCBUFF_BUFFSIZE (3u << 3) /* User Buffer Size */ | |
| 711 | #define IXGBE_FCBUFF_WRCONTX BIT(7) /* 0: Initiator, 1: Target */ | |
| bff66176 YZ |
712 | #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ |
| 713 | #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ | |
| 714 | #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 | |
| 715 | #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 | |
| 716 | #define IXGBE_FCBUFF_OFFSET_SHIFT 16 | |
| b4f47a48 JK |
717 | #define IXGBE_FCDMARW_WE BIT(14) /* Write enable */ |
| 718 | #define IXGBE_FCDMARW_RE BIT(15) /* Read enable */ | |
| bff66176 YZ |
719 | #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ |
| 720 | #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ | |
| 721 | #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 | |
| 722 | ||
| 723 | /* FCoE SOF/EOF */ | |
| 724 | #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ | |
| 725 | #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ | |
| 726 | #define IXGBE_REOFF 0x05158 /* Rx FC EOF */ | |
| 727 | #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ | |
| ea412015 VD |
728 | /* FCoE Direct Filter Context */ |
| 729 | #define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) | |
| 730 | #define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) | |
| bff66176 YZ |
731 | /* FCoE Filter Context Registers */ |
| 732 | #define IXGBE_FCFLT 0x05108 /* FC FLT Context */ | |
| 733 | #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ | |
| 734 | #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ | |
| b4f47a48 JK |
735 | #define IXGBE_FCFLT_VALID BIT(0) /* Filter Context Valid */ |
| 736 | #define IXGBE_FCFLT_FIRST BIT(1) /* Filter First */ | |
| bff66176 YZ |
737 | #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ |
| 738 | #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ | |
| b4f47a48 JK |
739 | #define IXGBE_FCFLTRW_RVALDT BIT(13) /* Fast Re-Validation */ |
| 740 | #define IXGBE_FCFLTRW_WE BIT(14) /* Write Enable */ | |
| 741 | #define IXGBE_FCFLTRW_RE BIT(15) /* Read Enable */ | |
| bff66176 YZ |
742 | /* FCoE Receive Control */ |
| 743 | #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ | |
| b4f47a48 JK |
744 | #define IXGBE_FCRXCTRL_FCOELLI BIT(0) /* Low latency interrupt */ |
| 745 | #define IXGBE_FCRXCTRL_SAVBAD BIT(1) /* Save Bad Frames */ | |
| 746 | #define IXGBE_FCRXCTRL_FRSTRDH BIT(2) /* EN 1st Read Header */ | |
| 747 | #define IXGBE_FCRXCTRL_LASTSEQH BIT(3) /* EN Last Header in Seq */ | |
| 748 | #define IXGBE_FCRXCTRL_ALLH BIT(4) /* EN All Headers */ | |
| 749 | #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5) /* EN 1st Seq. Header */ | |
| 750 | #define IXGBE_FCRXCTRL_ICRC BIT(6) /* Ignore Bad FC CRC */ | |
| 751 | #define IXGBE_FCRXCTRL_FCCRCBO BIT(7) /* FC CRC Byte Ordering */ | |
| bff66176 YZ |
752 | #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ |
| 753 | #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 | |
| 754 | /* FCoE Redirection */ | |
| 755 | #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ | |
| 756 | #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ | |
| 757 | #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ | |
| 758 | #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ | |
| 759 | #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ | |
| 760 | #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ | |
| ea412015 VD |
761 | #define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */ |
| 762 | /* Higher 7 bits for the queue index */ | |
| 763 | #define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000 | |
| 764 | #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16 | |
| bff66176 | 765 | |
| 9a799d71 AK |
766 | /* Stats registers */ |
| 767 | #define IXGBE_CRCERRS 0x04000 | |
| 768 | #define IXGBE_ILLERRC 0x04004 | |
| 769 | #define IXGBE_ERRBC 0x04008 | |
| 770 | #define IXGBE_MSPDC 0x04010 | |
| 771 | #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ | |
| 772 | #define IXGBE_MLFC 0x04034 | |
| 773 | #define IXGBE_MRFC 0x04038 | |
| 774 | #define IXGBE_RLEC 0x04040 | |
| 775 | #define IXGBE_LXONTXC 0x03F60 | |
| 776 | #define IXGBE_LXONRXC 0x0CF60 | |
| 777 | #define IXGBE_LXOFFTXC 0x03F68 | |
| 778 | #define IXGBE_LXOFFRXC 0x0CF68 | |
| 11afc1b1 PW |
779 | #define IXGBE_LXONRXCNT 0x041A4 |
| 780 | #define IXGBE_LXOFFRXCNT 0x041A8 | |
| 781 | #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ | |
| 782 | #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ | |
| 783 | #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ | |
| 9a799d71 AK |
784 | #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ |
| 785 | #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ | |
| 786 | #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ | |
| 787 | #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ | |
| 788 | #define IXGBE_PRC64 0x0405C | |
| 789 | #define IXGBE_PRC127 0x04060 | |
| 790 | #define IXGBE_PRC255 0x04064 | |
| 791 | #define IXGBE_PRC511 0x04068 | |
| 792 | #define IXGBE_PRC1023 0x0406C | |
| 793 | #define IXGBE_PRC1522 0x04070 | |
| 794 | #define IXGBE_GPRC 0x04074 | |
| 795 | #define IXGBE_BPRC 0x04078 | |
| 796 | #define IXGBE_MPRC 0x0407C | |
| 797 | #define IXGBE_GPTC 0x04080 | |
| 798 | #define IXGBE_GORCL 0x04088 | |
| 799 | #define IXGBE_GORCH 0x0408C | |
| 800 | #define IXGBE_GOTCL 0x04090 | |
| 801 | #define IXGBE_GOTCH 0x04094 | |
| 802 | #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ | |
| 803 | #define IXGBE_RUC 0x040A4 | |
| 804 | #define IXGBE_RFC 0x040A8 | |
| 805 | #define IXGBE_ROC 0x040AC | |
| 806 | #define IXGBE_RJC 0x040B0 | |
| 807 | #define IXGBE_MNGPRC 0x040B4 | |
| 808 | #define IXGBE_MNGPDC 0x040B8 | |
| 809 | #define IXGBE_MNGPTC 0x0CF90 | |
| 810 | #define IXGBE_TORL 0x040C0 | |
| 811 | #define IXGBE_TORH 0x040C4 | |
| 812 | #define IXGBE_TPR 0x040D0 | |
| 813 | #define IXGBE_TPT 0x040D4 | |
| 814 | #define IXGBE_PTC64 0x040D8 | |
| 815 | #define IXGBE_PTC127 0x040DC | |
| 816 | #define IXGBE_PTC255 0x040E0 | |
| 817 | #define IXGBE_PTC511 0x040E4 | |
| 818 | #define IXGBE_PTC1023 0x040E8 | |
| 819 | #define IXGBE_PTC1522 0x040EC | |
| 820 | #define IXGBE_MPTC 0x040F0 | |
| 821 | #define IXGBE_BPTC 0x040F4 | |
| 822 | #define IXGBE_XEC 0x04120 | |
| 11afc1b1 | 823 | #define IXGBE_SSVPC 0x08780 |
| 9a799d71 | 824 | |
| 11afc1b1 PW |
825 | #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) |
| 826 | #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ | |
| e7cf745b | 827 | (0x08600 + ((_i) * 4))) |
| 11afc1b1 | 828 | #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) |
| 9a799d71 AK |
829 | |
| 830 | #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ | |
| 831 | #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ | |
| 832 | #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ | |
| 833 | #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ | |
| 667c7565 ET |
834 | #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ |
| 835 | #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ | |
| 11afc1b1 PW |
836 | #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ |
| 837 | #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ | |
| 838 | #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ | |
| bff66176 YZ |
839 | #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */ |
| 840 | #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ | |
| 841 | #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ | |
| 842 | #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ | |
| 843 | #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ | |
| 844 | #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ | |
| 845 | #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ | |
| 58f6bcf9 ET |
846 | #define IXGBE_O2BGPTC 0x041C4 |
| 847 | #define IXGBE_O2BSPC 0x087B0 | |
| 848 | #define IXGBE_B2OSPC 0x041C0 | |
| 849 | #define IXGBE_B2OGPRC 0x02F90 | |
| a3aeea0e ET |
850 | #define IXGBE_PCRC8ECL 0x0E810 |
| 851 | #define IXGBE_PCRC8ECH 0x0E811 | |
| 852 | #define IXGBE_PCRC8ECH_MASK 0x1F | |
| 853 | #define IXGBE_LDPCECL 0x0E820 | |
| 854 | #define IXGBE_LDPCECH 0x0E821 | |
| 9a799d71 | 855 | |
| 6a14ee0c DS |
856 | /* MII clause 22/28 definitions */ |
| 857 | #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 | |
| 858 | ||
| 859 | #define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register */ | |
| 860 | #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */ | |
| 861 | ||
| 862 | #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */ | |
| 863 | ||
| 864 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */ | |
| 6ac74394 | 865 | #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */ |
| 6a14ee0c DS |
866 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */ |
| 867 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */ | |
| 868 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */ | |
| 869 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */ | |
| 870 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */ | |
| 871 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */ | |
| 872 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */ | |
| 873 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */ | |
| 6ac74394 DS |
874 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */ |
| 875 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */ | |
| 876 | ||
| 877 | #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ | |
| 878 | #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ | |
| 879 | #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ | |
| 880 | #define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ | |
| 881 | #define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ | |
| 882 | #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ | |
| 883 | #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ | |
| 884 | #define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 | |
| 885 | #define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800 | |
| 886 | #define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ | |
| 887 | #define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ | |
| 888 | #define IXGBE_MII_RESTART 0x200 | |
| 889 | #define IXGBE_MII_AUTONEG_COMPLETE 0x20 | |
| 890 | #define IXGBE_MII_AUTONEG_LINK_UP 0x04 | |
| 891 | #define IXGBE_MII_AUTONEG_REG 0x0 | |
| 6a14ee0c | 892 | |
| 9a799d71 AK |
893 | /* Management */ |
| 894 | #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 895 | #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 896 | #define IXGBE_MANC 0x05820 | |
| 897 | #define IXGBE_MFVAL 0x05824 | |
| 898 | #define IXGBE_MANC2H 0x05860 | |
| 899 | #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 900 | #define IXGBE_MIPAF 0x058B0 | |
| 901 | #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ | |
| 902 | #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ | |
| 903 | #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ | |
| 11afc1b1 PW |
904 | #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ |
| 905 | #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ | |
| 906 | #define IXGBE_LSWFW 0x15014 | |
| 9a799d71 | 907 | |
| 0b2679d6 DS |
908 | /* Management Bit Fields and Masks */ |
| 909 | #define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ | |
| 910 | ||
| 911 | /* Firmware Semaphore Register */ | |
| 912 | #define IXGBE_FWSM_MODE_MASK 0xE | |
| 913 | #define IXGBE_FWSM_FW_MODE_PT 0x4 | |
| 914 | ||
| 9a799d71 AK |
915 | /* ARC Subsystem registers */ |
| 916 | #define IXGBE_HICR 0x15F00 | |
| 917 | #define IXGBE_FWSTS 0x15F0C | |
| 918 | #define IXGBE_HSMC0R 0x15F04 | |
| 919 | #define IXGBE_HSMC1R 0x15F08 | |
| 920 | #define IXGBE_SWSR 0x15F10 | |
| 921 | #define IXGBE_HFDR 0x15FE8 | |
| 922 | #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ | |
| 923 | ||
| 9612de92 ET |
924 | #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ |
| 925 | /* Driver sets this bit when done to put command in RAM */ | |
| 926 | #define IXGBE_HICR_C 0x02 | |
| 927 | #define IXGBE_HICR_SV 0x04 /* Status Validity */ | |
| 928 | #define IXGBE_HICR_FW_RESET_ENABLE 0x40 | |
| 929 | #define IXGBE_HICR_FW_RESET 0x80 | |
| 930 | ||
| 9a799d71 AK |
931 | /* PCI-E registers */ |
| 932 | #define IXGBE_GCR 0x11000 | |
| 933 | #define IXGBE_GTV 0x11004 | |
| 934 | #define IXGBE_FUNCTAG 0x11008 | |
| 935 | #define IXGBE_GLT 0x1100C | |
| 936 | #define IXGBE_GSCL_1 0x11010 | |
| 937 | #define IXGBE_GSCL_2 0x11014 | |
| 938 | #define IXGBE_GSCL_3 0x11018 | |
| 939 | #define IXGBE_GSCL_4 0x1101C | |
| 940 | #define IXGBE_GSCN_0 0x11020 | |
| 941 | #define IXGBE_GSCN_1 0x11024 | |
| 942 | #define IXGBE_GSCN_2 0x11028 | |
| 943 | #define IXGBE_GSCN_3 0x1102C | |
| 9a900eca DS |
944 | #define IXGBE_FACTPS_8259X 0x10150 |
| 945 | #define IXGBE_FACTPS_X540 IXGBE_FACTPS_8259X | |
| 946 | #define IXGBE_FACTPS_X550 IXGBE_FACTPS_8259X | |
| 947 | #define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS_8259X | |
| 948 | #define IXGBE_FACTPS_X550EM_a 0x15FEC | |
| 949 | #define IXGBE_FACTPS(_hw) IXGBE_BY_MAC((_hw), FACTPS) | |
| 950 | ||
| 9a799d71 | 951 | #define IXGBE_PCIEANACTL 0x11040 |
| 9a900eca DS |
952 | #define IXGBE_SWSM_8259X 0x10140 |
| 953 | #define IXGBE_SWSM_X540 IXGBE_SWSM_8259X | |
| 954 | #define IXGBE_SWSM_X550 IXGBE_SWSM_8259X | |
| 955 | #define IXGBE_SWSM_X550EM_x IXGBE_SWSM_8259X | |
| 956 | #define IXGBE_SWSM_X550EM_a 0x15F70 | |
| 957 | #define IXGBE_SWSM(_hw) IXGBE_BY_MAC((_hw), SWSM) | |
| 958 | #define IXGBE_FWSM_8259X 0x10148 | |
| 959 | #define IXGBE_FWSM_X540 IXGBE_FWSM_8259X | |
| 960 | #define IXGBE_FWSM_X550 IXGBE_FWSM_8259X | |
| 961 | #define IXGBE_FWSM_X550EM_x IXGBE_FWSM_8259X | |
| 962 | #define IXGBE_FWSM_X550EM_a 0x15F74 | |
| 963 | #define IXGBE_FWSM(_hw) IXGBE_BY_MAC((_hw), FWSM) | |
| 9a799d71 AK |
964 | #define IXGBE_GSSR 0x10160 |
| 965 | #define IXGBE_MREVID 0x11064 | |
| 966 | #define IXGBE_DCA_ID 0x11070 | |
| 967 | #define IXGBE_DCA_CTRL 0x11074 | |
| 9a900eca DS |
968 | #define IXGBE_SWFW_SYNC_8259X IXGBE_GSSR |
| 969 | #define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC_8259X | |
| 970 | #define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC_8259X | |
| 971 | #define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC_8259X | |
| 972 | #define IXGBE_SWFW_SYNC_X550EM_a 0x15F78 | |
| 973 | #define IXGBE_SWFW_SYNC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC) | |
| 9a799d71 | 974 | |
| 11afc1b1 PW |
975 | /* PCIe registers 82599-specific */ |
| 976 | #define IXGBE_GCR_EXT 0x11050 | |
| 977 | #define IXGBE_GSCL_5_82599 0x11030 | |
| 978 | #define IXGBE_GSCL_6_82599 0x11034 | |
| 979 | #define IXGBE_GSCL_7_82599 0x11038 | |
| 980 | #define IXGBE_GSCL_8_82599 0x1103C | |
| 981 | #define IXGBE_PHYADR_82599 0x11040 | |
| 982 | #define IXGBE_PHYDAT_82599 0x11044 | |
| 983 | #define IXGBE_PHYCTL_82599 0x11048 | |
| 984 | #define IXGBE_PBACLR_82599 0x11068 | |
| 9a900eca DS |
985 | |
| 986 | #define IXGBE_CIAA_8259X 0x11088 | |
| 987 | #define IXGBE_CIAA_X540 IXGBE_CIAA_8259X | |
| 988 | #define IXGBE_CIAA_X550 0x11508 | |
| 989 | #define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550 | |
| 990 | #define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550 | |
| 991 | #define IXGBE_CIAA(_hw) IXGBE_BY_MAC((_hw), CIAA) | |
| 992 | ||
| 993 | #define IXGBE_CIAD_8259X 0x1108C | |
| 994 | #define IXGBE_CIAD_X540 IXGBE_CIAD_8259X | |
| 995 | #define IXGBE_CIAD_X550 0x11510 | |
| 996 | #define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550 | |
| 997 | #define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550 | |
| 998 | #define IXGBE_CIAD(_hw) IXGBE_BY_MAC((_hw), CIAD) | |
| 999 | ||
| 83dfde40 ET |
1000 | #define IXGBE_PICAUSE 0x110B0 |
| 1001 | #define IXGBE_PIENA 0x110B8 | |
| 11afc1b1 | 1002 | #define IXGBE_CDQ_MBR_82599 0x110B4 |
| 83dfde40 | 1003 | #define IXGBE_PCIESPARE 0x110BC |
| 11afc1b1 PW |
1004 | #define IXGBE_MISC_REG_82599 0x110F0 |
| 1005 | #define IXGBE_ECC_CTRL_0_82599 0x11100 | |
| 1006 | #define IXGBE_ECC_CTRL_1_82599 0x11104 | |
| 1007 | #define IXGBE_ECC_STATUS_82599 0x110E0 | |
| 1008 | #define IXGBE_BAR_CTRL_82599 0x110F4 | |
| 1009 | ||
| 202ff1ec MC |
1010 | /* PCI Express Control */ |
| 1011 | #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 | |
| 1012 | #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 | |
| 1013 | #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 | |
| 1014 | #define IXGBE_GCR_CAP_VER2 0x00040000 | |
| 1015 | ||
| 7f870475 | 1016 | #define IXGBE_GCR_EXT_MSIX_EN 0x80000000 |
| ff9d1a5a | 1017 | #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 |
| 7f870475 GR |
1018 | #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 |
| 1019 | #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 | |
| 1020 | #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 | |
| 1021 | #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ | |
| e7cf745b | 1022 | IXGBE_GCR_EXT_VT_MODE_64) |
| 7f870475 | 1023 | |
| 11afc1b1 PW |
1024 | /* Time Sync Registers */ |
| 1025 | #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ | |
| 1026 | #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ | |
| 1027 | #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ | |
| 1028 | #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ | |
| 1029 | #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ | |
| 1030 | #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ | |
| 1031 | #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ | |
| 1032 | #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ | |
| 1033 | #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ | |
| 1034 | #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ | |
| 1035 | #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ | |
| a9763f3c | 1036 | #define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */ |
| 11afc1b1 | 1037 | #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ |
| 83dfde40 ET |
1038 | #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ |
| 1039 | #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ | |
| 1040 | #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ | |
| 1041 | #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ | |
| 1042 | #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ | |
| 1043 | #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ | |
| 1044 | #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ | |
| 681ae1ad JK |
1045 | #define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ |
| 1046 | #define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ | |
| 83dfde40 ET |
1047 | #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ |
| 1048 | #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ | |
| 1049 | #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ | |
| 1050 | #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ | |
| 1051 | #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ | |
| 1052 | #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ | |
| a9763f3c | 1053 | #define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */ |
| 11afc1b1 | 1054 | |
| 9a799d71 | 1055 | /* Diagnostic Registers */ |
| c44ade9e JB |
1056 | #define IXGBE_RDSTATCTL 0x02C20 |
| 1057 | #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ | |
| 1058 | #define IXGBE_RDHMPN 0x02F08 | |
| 98c00a1c | 1059 | #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) |
| c44ade9e | 1060 | #define IXGBE_RDPROBE 0x02F20 |
| 11afc1b1 PW |
1061 | #define IXGBE_RDMAM 0x02F30 |
| 1062 | #define IXGBE_RDMAD 0x02F34 | |
| c44ade9e JB |
1063 | #define IXGBE_TDSTATCTL 0x07C20 |
| 1064 | #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ | |
| 1065 | #define IXGBE_TDHMPN 0x07F08 | |
| 11afc1b1 PW |
1066 | #define IXGBE_TDHMPN2 0x082FC |
| 1067 | #define IXGBE_TXDESCIC 0x082CC | |
| 98c00a1c | 1068 | #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) |
| 11afc1b1 | 1069 | #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) |
| c44ade9e JB |
1070 | #define IXGBE_TDPROBE 0x07F20 |
| 1071 | #define IXGBE_TXBUFCTRL 0x0C600 | |
| 45a88dfc | 1072 | #define IXGBE_TXBUFDATA(_i) (0x0C610 + ((_i) * 4)) /* 4 of these (0-3) */ |
| 9a799d71 | 1073 | #define IXGBE_RXBUFCTRL 0x03600 |
| 45a88dfc | 1074 | #define IXGBE_RXBUFDATA(_i) (0x03610 + ((_i) * 4)) /* 4 of these (0-3) */ |
| 9a799d71 AK |
1075 | #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ |
| 1076 | #define IXGBE_RFVAL 0x050A4 | |
| 1077 | #define IXGBE_MDFTC1 0x042B8 | |
| 1078 | #define IXGBE_MDFTC2 0x042C0 | |
| 1079 | #define IXGBE_MDFTFIFO1 0x042C4 | |
| 1080 | #define IXGBE_MDFTFIFO2 0x042C8 | |
| 1081 | #define IXGBE_MDFTS 0x042CC | |
| 1082 | #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ | |
| 1083 | #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ | |
| 1084 | #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ | |
| 1085 | #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ | |
| 1086 | #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ | |
| 1087 | #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ | |
| 1088 | #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ | |
| 1089 | #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ | |
| 1090 | #define IXGBE_PCIEECCCTL 0x1106C | |
| 83dfde40 ET |
1091 | #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ |
| 1092 | #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ | |
| 1093 | #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ | |
| 1094 | #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ | |
| 1095 | #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ | |
| 1096 | #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ | |
| 1097 | #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ | |
| 1098 | #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ | |
| 11afc1b1 PW |
1099 | #define IXGBE_PCIEECCCTL0 0x11100 |
| 1100 | #define IXGBE_PCIEECCCTL1 0x11104 | |
| 83dfde40 ET |
1101 | #define IXGBE_RXDBUECC 0x03F70 |
| 1102 | #define IXGBE_TXDBUECC 0x0CF70 | |
| 1103 | #define IXGBE_RXDBUEST 0x03F74 | |
| 1104 | #define IXGBE_TXDBUEST 0x0CF74 | |
| 9a799d71 AK |
1105 | #define IXGBE_PBTXECC 0x0C300 |
| 1106 | #define IXGBE_PBRXECC 0x03300 | |
| 1107 | #define IXGBE_GHECCR 0x110B0 | |
| 1108 | ||
| 1109 | /* MAC Registers */ | |
| 1110 | #define IXGBE_PCS1GCFIG 0x04200 | |
| 1111 | #define IXGBE_PCS1GLCTL 0x04208 | |
| 1112 | #define IXGBE_PCS1GLSTA 0x0420C | |
| 1113 | #define IXGBE_PCS1GDBG0 0x04210 | |
| 1114 | #define IXGBE_PCS1GDBG1 0x04214 | |
| 1115 | #define IXGBE_PCS1GANA 0x04218 | |
| 1116 | #define IXGBE_PCS1GANLP 0x0421C | |
| 1117 | #define IXGBE_PCS1GANNP 0x04220 | |
| 1118 | #define IXGBE_PCS1GANLPNP 0x04224 | |
| 1119 | #define IXGBE_HLREG0 0x04240 | |
| 1120 | #define IXGBE_HLREG1 0x04244 | |
| 1121 | #define IXGBE_PAP 0x04248 | |
| 1122 | #define IXGBE_MACA 0x0424C | |
| 1123 | #define IXGBE_APAE 0x04250 | |
| 1124 | #define IXGBE_ARD 0x04254 | |
| 1125 | #define IXGBE_AIS 0x04258 | |
| 1126 | #define IXGBE_MSCA 0x0425C | |
| 1127 | #define IXGBE_MSRWD 0x04260 | |
| 1128 | #define IXGBE_MLADD 0x04264 | |
| 1129 | #define IXGBE_MHADD 0x04268 | |
| 11afc1b1 | 1130 | #define IXGBE_MAXFRS 0x04268 |
| 9a799d71 AK |
1131 | #define IXGBE_TREG 0x0426C |
| 1132 | #define IXGBE_PCSS1 0x04288 | |
| 1133 | #define IXGBE_PCSS2 0x0428C | |
| 1134 | #define IXGBE_XPCSS 0x04290 | |
| 11afc1b1 | 1135 | #define IXGBE_MFLCN 0x04294 |
| 9a799d71 | 1136 | #define IXGBE_SERDESC 0x04298 |
| 2f2219be | 1137 | #define IXGBE_MAC_SGMII_BUSY 0x04298 |
| 9a799d71 AK |
1138 | #define IXGBE_MACS 0x0429C |
| 1139 | #define IXGBE_AUTOC 0x042A0 | |
| 1140 | #define IXGBE_LINKS 0x042A4 | |
| 11afc1b1 | 1141 | #define IXGBE_LINKS2 0x04324 |
| 9a799d71 AK |
1142 | #define IXGBE_AUTOC2 0x042A8 |
| 1143 | #define IXGBE_AUTOC3 0x042AC | |
| 1144 | #define IXGBE_ANLP1 0x042B0 | |
| 1145 | #define IXGBE_ANLP2 0x042B4 | |
| 83dfde40 | 1146 | #define IXGBE_MACC 0x04330 |
| 9a799d71 | 1147 | #define IXGBE_ATLASCTL 0x04800 |
| 11afc1b1 PW |
1148 | #define IXGBE_MMNGC 0x042D0 |
| 1149 | #define IXGBE_ANLPNP1 0x042D4 | |
| 1150 | #define IXGBE_ANLPNP2 0x042D8 | |
| 1151 | #define IXGBE_KRPCSFC 0x042E0 | |
| 1152 | #define IXGBE_KRPCSS 0x042E4 | |
| 1153 | #define IXGBE_FECS1 0x042E8 | |
| 1154 | #define IXGBE_FECS2 0x042EC | |
| 1155 | #define IXGBE_SMADARCTL 0x14F10 | |
| 1156 | #define IXGBE_MPVC 0x04318 | |
| 1157 | #define IXGBE_SGMIIC 0x04314 | |
| 1158 | ||
| 83dfde40 ET |
1159 | /* Statistics Registers */ |
| 1160 | #define IXGBE_RXNFGPC 0x041B0 | |
| 1161 | #define IXGBE_RXNFGBCL 0x041B4 | |
| 1162 | #define IXGBE_RXNFGBCH 0x041B8 | |
| 1163 | #define IXGBE_RXDGPC 0x02F50 | |
| 1164 | #define IXGBE_RXDGBCL 0x02F54 | |
| 1165 | #define IXGBE_RXDGBCH 0x02F58 | |
| 1166 | #define IXGBE_RXDDGPC 0x02F5C | |
| 1167 | #define IXGBE_RXDDGBCL 0x02F60 | |
| 1168 | #define IXGBE_RXDDGBCH 0x02F64 | |
| 1169 | #define IXGBE_RXLPBKGPC 0x02F68 | |
| 1170 | #define IXGBE_RXLPBKGBCL 0x02F6C | |
| 1171 | #define IXGBE_RXLPBKGBCH 0x02F70 | |
| 1172 | #define IXGBE_RXDLPBKGPC 0x02F74 | |
| 1173 | #define IXGBE_RXDLPBKGBCL 0x02F78 | |
| 1174 | #define IXGBE_RXDLPBKGBCH 0x02F7C | |
| 1175 | #define IXGBE_TXDGPC 0x087A0 | |
| 1176 | #define IXGBE_TXDGBCL 0x087A4 | |
| 1177 | #define IXGBE_TXDGBCH 0x087A8 | |
| 1178 | ||
| 1179 | #define IXGBE_RXDSTATCTRL 0x02F40 | |
| 1180 | ||
| 1181 | /* Copper Pond 2 link timeout */ | |
| 734e979f MC |
1182 | #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 |
| 1183 | ||
| 11afc1b1 PW |
1184 | /* Omer CORECTL */ |
| 1185 | #define IXGBE_CORECTL 0x014F00 | |
| 1186 | /* BARCTRL */ | |
| 83dfde40 ET |
1187 | #define IXGBE_BARCTRL 0x110F4 |
| 1188 | #define IXGBE_BARCTRL_FLSIZE 0x0700 | |
| 1189 | #define IXGBE_BARCTRL_FLSIZE_SHIFT 8 | |
| 1190 | #define IXGBE_BARCTRL_CSRSIZE 0x2000 | |
| 1191 | ||
| 1192 | /* RSCCTL Bit Masks */ | |
| 1193 | #define IXGBE_RSCCTL_RSCEN 0x01 | |
| 1194 | #define IXGBE_RSCCTL_MAXDESC_1 0x00 | |
| 1195 | #define IXGBE_RSCCTL_MAXDESC_4 0x04 | |
| 1196 | #define IXGBE_RSCCTL_MAXDESC_8 0x08 | |
| 1197 | #define IXGBE_RSCCTL_MAXDESC_16 0x0C | |
| 1198 | ||
| 1199 | /* RSCDBU Bit Masks */ | |
| 1200 | #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F | |
| 1201 | #define IXGBE_RSCDBU_RSCACKDIS 0x00000080 | |
| 9a799d71 | 1202 | |
| cc41ac7c JB |
1203 | /* RDRXCTL Bit Masks */ |
| 1204 | #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ | |
| 11afc1b1 | 1205 | #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ |
| f961ddae | 1206 | #define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad small packet */ |
| cc41ac7c JB |
1207 | #define IXGBE_RDRXCTL_MVMEN 0x00000020 |
| 1208 | #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ | |
| 11afc1b1 | 1209 | #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ |
| 83dfde40 ET |
1210 | #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ |
| 1211 | #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */ | |
| 7367096a AD |
1212 | #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */ |
| 1213 | #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */ | |
| 207969b9 MR |
1214 | #define IXGBE_RDRXCTL_MBINTEN 0x10000000 |
| 1215 | #define IXGBE_RDRXCTL_MDP_EN 0x20000000 | |
| 11afc1b1 PW |
1216 | |
| 1217 | /* RQTC Bit Masks and Shifts */ | |
| 1218 | #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) | |
| 1219 | #define IXGBE_RQTC_TC0_MASK (0x7 << 0) | |
| 1220 | #define IXGBE_RQTC_TC1_MASK (0x7 << 4) | |
| 1221 | #define IXGBE_RQTC_TC2_MASK (0x7 << 8) | |
| 1222 | #define IXGBE_RQTC_TC3_MASK (0x7 << 12) | |
| 1223 | #define IXGBE_RQTC_TC4_MASK (0x7 << 16) | |
| 1224 | #define IXGBE_RQTC_TC5_MASK (0x7 << 20) | |
| 1225 | #define IXGBE_RQTC_TC6_MASK (0x7 << 24) | |
| 1226 | #define IXGBE_RQTC_TC7_MASK (0x7 << 28) | |
| 1227 | ||
| 1228 | /* PSRTYPE.RQPL Bit masks and shift */ | |
| 1229 | #define IXGBE_PSRTYPE_RQPL_MASK 0x7 | |
| 1230 | #define IXGBE_PSRTYPE_RQPL_SHIFT 29 | |
| 9a799d71 AK |
1231 | |
| 1232 | /* CTRL Bit Masks */ | |
| 1233 | #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ | |
| 1234 | #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ | |
| 1235 | #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ | |
| 8132b54e | 1236 | #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) |
| 9a799d71 AK |
1237 | |
| 1238 | /* FACTPS */ | |
| 0b2679d6 | 1239 | #define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ |
| 9a799d71 AK |
1240 | #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ |
| 1241 | ||
| 1242 | /* MHADD Bit Masks */ | |
| 1243 | #define IXGBE_MHADD_MFS_MASK 0xFFFF0000 | |
| 1244 | #define IXGBE_MHADD_MFS_SHIFT 16 | |
| 1245 | ||
| 1246 | /* Extended Device Control */ | |
| 11afc1b1 | 1247 | #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ |
| 9a799d71 AK |
1248 | #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ |
| 1249 | #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | |
| 1250 | #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ | |
| 1251 | ||
| 1252 | /* Direct Cache Access (DCA) definitions */ | |
| 1253 | #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ | |
| 1254 | #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ | |
| 1255 | ||
| 1256 | #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ | |
| 1257 | #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ | |
| 1258 | ||
| 1259 | #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ | |
| 11afc1b1 PW |
1260 | #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ |
| 1261 | #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ | |
| b4f47a48 JK |
1262 | #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */ |
| 1263 | #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */ | |
| 1264 | #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */ | |
| 1265 | #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */ | |
| 1266 | #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ | |
| 1267 | #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ | |
| 9a799d71 AK |
1268 | |
| 1269 | #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ | |
| 11afc1b1 PW |
1270 | #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ |
| 1271 | #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ | |
| b4f47a48 JK |
1272 | #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ |
| 1273 | #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ | |
| 1274 | #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ | |
| 1275 | #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ | |
| 9a799d71 AK |
1276 | #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ |
| 1277 | ||
| 1278 | /* MSCA Bit Masks */ | |
| 1279 | #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */ | |
| 1280 | #define IXGBE_MSCA_NP_ADDR_SHIFT 0 | |
| 1281 | #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */ | |
| 1282 | #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */ | |
| 1283 | #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ | |
| 1284 | #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ | |
| 1285 | #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ | |
| 1286 | #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ | |
| 1287 | #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ | |
| 1288 | #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */ | |
| 83dfde40 ET |
1289 | #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */ |
| 1290 | #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/ | |
| 9a799d71 AK |
1291 | #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ |
| 1292 | #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ | |
| 1293 | #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */ | |
| 1294 | #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */ | |
| 1295 | #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ | |
| 1296 | #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */ | |
| 1297 | ||
| 1298 | /* MSRWD bit masks */ | |
| c44ade9e JB |
1299 | #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF |
| 1300 | #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 | |
| 1301 | #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 | |
| 1302 | #define IXGBE_MSRWD_READ_DATA_SHIFT 16 | |
| 9a799d71 AK |
1303 | |
| 1304 | /* Atlas registers */ | |
| 1305 | #define IXGBE_ATLAS_PDN_LPBK 0x24 | |
| 1306 | #define IXGBE_ATLAS_PDN_10G 0xB | |
| 1307 | #define IXGBE_ATLAS_PDN_1G 0xC | |
| 1308 | #define IXGBE_ATLAS_PDN_AN 0xD | |
| 1309 | ||
| 1310 | /* Atlas bit masks */ | |
| 1311 | #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 | |
| 1312 | #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 | |
| 1313 | #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 | |
| 1314 | #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 | |
| 1315 | #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 | |
| 1316 | ||
| 11afc1b1 PW |
1317 | /* Omer bit masks */ |
| 1318 | #define IXGBE_CORECTL_WRITE_CMD 0x00010000 | |
| c44ade9e | 1319 | |
| 6b73e10d | 1320 | /* MDIO definitions */ |
| 9a799d71 | 1321 | |
| 2d40cd17 | 1322 | #define IXGBE_MDIO_ZERO_DEV_TYPE 0x0 |
| 6a14ee0c DS |
1323 | #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 |
| 1324 | #define IXGBE_MDIO_PCS_DEV_TYPE 0x3 | |
| 1325 | #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 | |
| 1326 | #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 | |
| 1327 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ | |
| 1328 | #define IXGBE_TWINAX_DEV 1 | |
| 1329 | ||
| c44ade9e JB |
1330 | #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ |
| 1331 | ||
| 9a799d71 AK |
1332 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */ |
| 1333 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ | |
| 1334 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ | |
| 1335 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */ | |
| 1336 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 | |
| 1337 | #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 | |
| 1338 | ||
| 6a14ee0c DS |
1339 | #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ |
| 1340 | #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ | |
| 1341 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ | |
| 6ac74394 | 1342 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ |
| c3dc4c09 DS |
1343 | #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ |
| 1344 | #define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ | |
| 6a14ee0c DS |
1345 | #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ |
| 1346 | #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ | |
| 1347 | #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ | |
| 1348 | ||
| 961fac88 | 1349 | #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ |
| 6ac74394 DS |
1350 | #define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */ |
| 1351 | #define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT */ | |
| 6a14ee0c DS |
1352 | #define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ |
| 1353 | #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */ | |
| 1354 | #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */ | |
| 1355 | #define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */ | |
| c3dc4c09 DS |
1356 | #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */ |
| 1357 | #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */ | |
| 1358 | #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */ | |
| 1359 | #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */ | |
| 1360 | #define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */ | |
| 83a9fb20 | 1361 | #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */ |
| c3dc4c09 | 1362 | #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */ |
| 83a9fb20 MR |
1363 | #define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* global fault msg */ |
| 1364 | #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */ | |
| c3dc4c09 DS |
1365 | #define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */ |
| 1366 | /* autoneg vendor alarm int enable */ | |
| 1367 | #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 | |
| 1368 | #define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */ | |
| 1369 | #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */ | |
| 1370 | #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */ | |
| 1371 | #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */ | |
| 83a9fb20 | 1372 | #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /*int dev fault enable */ |
| 6a14ee0c DS |
1373 | |
| 1374 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ | |
| 1375 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ | |
| 1376 | #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Stat Reg */ | |
| c3dc4c09 DS |
1377 | #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ |
| 1378 | #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ | |
| 6a14ee0c DS |
1379 | #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Tx Dis Reg */ |
| 1380 | #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Tx Dis */ | |
| c44ade9e | 1381 | |
| 9dda1736 ET |
1382 | /* MII clause 22/28 definitions */ |
| 1383 | #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ | |
| 1384 | #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ | |
| 1385 | #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ | |
| 1386 | #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ | |
| 1387 | #define IXGBE_MII_AUTONEG_REG 0x0 | |
| 1388 | ||
| 9a799d71 AK |
1389 | #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 |
| 1390 | #define IXGBE_MAX_PHY_ADDR 32 | |
| 1391 | ||
| 11afc1b1 | 1392 | /* PHY IDs*/ |
| 0befdb3e JB |
1393 | #define TN1010_PHY_ID 0x00A19410 |
| 1394 | #define TNX_FW_REV 0xB | |
| 2b264909 | 1395 | #define X540_PHY_ID 0x01540200 |
| deda562a | 1396 | #define X550_PHY_ID 0x01540220 |
| c2c78d5c | 1397 | #define X557_PHY_ID 0x01540240 |
| 9a799d71 | 1398 | #define QT2022_PHY_ID 0x0043A400 |
| c4900be0 | 1399 | #define ATH_PHY_ID 0x03429050 |
| fe15e8e1 | 1400 | #define AQ_FW_REV 0x20 |
| 9a799d71 | 1401 | |
| c44ade9e JB |
1402 | /* PHY Types */ |
| 1403 | #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 | |
| 1404 | ||
| c4900be0 DS |
1405 | /* Special PHY Init Routine */ |
| 1406 | #define IXGBE_PHY_INIT_OFFSET_NL 0x002B | |
| 1407 | #define IXGBE_PHY_INIT_END_NL 0xFFFF | |
| 1408 | #define IXGBE_CONTROL_MASK_NL 0xF000 | |
| 1409 | #define IXGBE_DATA_MASK_NL 0x0FFF | |
| 1410 | #define IXGBE_CONTROL_SHIFT_NL 12 | |
| 1411 | #define IXGBE_DELAY_NL 0 | |
| 1412 | #define IXGBE_DATA_NL 1 | |
| 1413 | #define IXGBE_CONTROL_NL 0x000F | |
| 1414 | #define IXGBE_CONTROL_EOL_NL 0x0FFF | |
| 1415 | #define IXGBE_CONTROL_SOL_NL 0x0000 | |
| 1416 | ||
| 9a799d71 | 1417 | /* General purpose Interrupt Enable */ |
| 9a900eca DS |
1418 | #define IXGBE_SDP0_GPIEN_8259X 0x00000001 /* SDP0 */ |
| 1419 | #define IXGBE_SDP1_GPIEN_8259X 0x00000002 /* SDP1 */ | |
| 1420 | #define IXGBE_SDP2_GPIEN_8259X 0x00000004 /* SDP2 */ | |
| 1421 | #define IXGBE_SDP0_GPIEN_X540 0x00000002 /* SDP0 on X540 and X550 */ | |
| 1422 | #define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */ | |
| 1423 | #define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */ | |
| 1424 | #define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540 | |
| 1425 | #define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540 | |
| 1426 | #define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540 | |
| 1427 | #define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540 | |
| 1428 | #define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540 | |
| 1429 | #define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540 | |
| 1430 | #define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540 | |
| 1431 | #define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540 | |
| 1432 | #define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540 | |
| 1433 | #define IXGBE_SDP0_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN) | |
| 1434 | #define IXGBE_SDP1_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN) | |
| 1435 | #define IXGBE_SDP2_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN) | |
| 1436 | ||
| c44ade9e JB |
1437 | #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ |
| 1438 | #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ | |
| 1439 | #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ | |
| 1440 | #define IXGBE_GPIE_EIAME 0x40000000 | |
| 1441 | #define IXGBE_GPIE_PBA_SUPPORT 0x80000000 | |
| 83dfde40 | 1442 | #define IXGBE_GPIE_RSC_DELAY_SHIFT 11 |
| 11afc1b1 PW |
1443 | #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ |
| 1444 | #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ | |
| 1445 | #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ | |
| 1446 | #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ | |
| 9a799d71 | 1447 | |
| 80605c65 JF |
1448 | /* Packet Buffer Initialization */ |
| 1449 | #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ | |
| 1450 | #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ | |
| 1451 | #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ | |
| 1452 | #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ | |
| 1453 | #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ | |
| 1454 | #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ | |
| 1455 | #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer*/ | |
| 1456 | #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/ | |
| 1457 | ||
| 1458 | #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ | |
| 1459 | #define IXGBE_MAX_PB 8 | |
| 1460 | ||
| 1461 | /* Packet buffer allocation strategies */ | |
| 1462 | enum { | |
| 1463 | PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ | |
| 1464 | #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL | |
| 1465 | PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ | |
| 1466 | #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED | |
| 1467 | }; | |
| 1468 | ||
| 9a799d71 AK |
1469 | /* Transmit Flow Control status */ |
| 1470 | #define IXGBE_TFCS_TXOFF 0x00000001 | |
| 1471 | #define IXGBE_TFCS_TXOFF0 0x00000100 | |
| 1472 | #define IXGBE_TFCS_TXOFF1 0x00000200 | |
| 1473 | #define IXGBE_TFCS_TXOFF2 0x00000400 | |
| 1474 | #define IXGBE_TFCS_TXOFF3 0x00000800 | |
| 1475 | #define IXGBE_TFCS_TXOFF4 0x00001000 | |
| 1476 | #define IXGBE_TFCS_TXOFF5 0x00002000 | |
| 1477 | #define IXGBE_TFCS_TXOFF6 0x00004000 | |
| 1478 | #define IXGBE_TFCS_TXOFF7 0x00008000 | |
| 1479 | ||
| 1480 | /* TCP Timer */ | |
| 1481 | #define IXGBE_TCPTIMER_KS 0x00000100 | |
| 1482 | #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 | |
| 1483 | #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 | |
| 1484 | #define IXGBE_TCPTIMER_LOOP 0x00000800 | |
| 1485 | #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF | |
| 1486 | ||
| 1487 | /* HLREG0 Bit Masks */ | |
| 1488 | #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ | |
| 1489 | #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ | |
| 1490 | #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ | |
| 1491 | #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ | |
| 1492 | #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ | |
| 1493 | #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ | |
| 1494 | #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ | |
| 1495 | #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ | |
| 1496 | #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ | |
| 1497 | #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ | |
| 1498 | #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ | |
| 1499 | #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ | |
| 1500 | #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ | |
| 1501 | #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ | |
| 1502 | #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ | |
| 1503 | ||
| 1504 | /* VMD_CTL bitmasks */ | |
| 1505 | #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 | |
| 1506 | #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 | |
| 1507 | ||
| 11afc1b1 PW |
1508 | /* VT_CTL bitmasks */ |
| 1509 | #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ | |
| 1510 | #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ | |
| 1511 | #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ | |
| 6e4e87d6 DS |
1512 | #define IXGBE_VT_CTL_POOL_SHIFT 7 |
| 1513 | #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) | |
| 11afc1b1 PW |
1514 | |
| 1515 | /* VMOLR bitmasks */ | |
| 1516 | #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ | |
| 1517 | #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ | |
| 1518 | #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ | |
| 1519 | #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ | |
| 1520 | #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ | |
| 1521 | ||
| 1522 | /* VFRE bitmask */ | |
| 1523 | #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF | |
| 1524 | ||
| 7f870475 GR |
1525 | #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ |
| 1526 | ||
| 9a799d71 AK |
1527 | /* RDHMPN and TDHMPN bitmasks */ |
| 1528 | #define IXGBE_RDHMPN_RDICADDR 0x007FF800 | |
| 1529 | #define IXGBE_RDHMPN_RDICRDREQ 0x00800000 | |
| 1530 | #define IXGBE_RDHMPN_RDICADDR_SHIFT 11 | |
| 1531 | #define IXGBE_TDHMPN_TDICADDR 0x003FF800 | |
| 1532 | #define IXGBE_TDHMPN_TDICRDREQ 0x00800000 | |
| 1533 | #define IXGBE_TDHMPN_TDICADDR_SHIFT 11 | |
| 1534 | ||
| 11afc1b1 PW |
1535 | #define IXGBE_RDMAM_MEM_SEL_SHIFT 13 |
| 1536 | #define IXGBE_RDMAM_DWORD_SHIFT 9 | |
| 1537 | #define IXGBE_RDMAM_DESC_COMP_FIFO 1 | |
| 1538 | #define IXGBE_RDMAM_DFC_CMD_FIFO 2 | |
| 1539 | #define IXGBE_RDMAM_TCN_STATUS_RAM 4 | |
| 1540 | #define IXGBE_RDMAM_WB_COLL_FIFO 5 | |
| 1541 | #define IXGBE_RDMAM_QSC_CNT_RAM 6 | |
| 1542 | #define IXGBE_RDMAM_QSC_QUEUE_CNT 8 | |
| 1543 | #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA | |
| 1544 | #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 | |
| 1545 | #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 | |
| 1546 | #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 | |
| 1547 | #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 | |
| 1548 | #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 | |
| 1549 | #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 | |
| 1550 | #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 | |
| 1551 | #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 | |
| 1552 | #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 | |
| 1553 | #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 | |
| 1554 | #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 | |
| 1555 | #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 | |
| 1556 | #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 | |
| 1557 | #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 | |
| 1558 | ||
| 1559 | #define IXGBE_TXDESCIC_READY 0x80000000 | |
| 1560 | ||
| 9a799d71 AK |
1561 | /* Receive Checksum Control */ |
| 1562 | #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | |
| 1563 | #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ | |
| 1564 | ||
| 1565 | /* FCRTL Bit Masks */ | |
| 11afc1b1 PW |
1566 | #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ |
| 1567 | #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ | |
| 9a799d71 AK |
1568 | |
| 1569 | /* PAP bit masks*/ | |
| 1570 | #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ | |
| 1571 | ||
| 1572 | /* RMCS Bit Masks */ | |
| c44ade9e | 1573 | #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */ |
| 9a799d71 AK |
1574 | /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ |
| 1575 | #define IXGBE_RMCS_RAC 0x00000004 | |
| 1576 | #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ | |
| 11afc1b1 PW |
1577 | #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ |
| 1578 | #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ | |
| 9a799d71 AK |
1579 | #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ |
| 1580 | ||
| 11afc1b1 PW |
1581 | /* FCCFG Bit Masks */ |
| 1582 | #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ | |
| 1583 | #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ | |
| c44ade9e | 1584 | |
| 9a799d71 AK |
1585 | /* Interrupt register bitmasks */ |
| 1586 | ||
| 1587 | /* Extended Interrupt Cause Read */ | |
| 1588 | #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ | |
| 11afc1b1 PW |
1589 | #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ |
| 1590 | #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ | |
| 1591 | #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ | |
| 1592 | #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ | |
| 9a799d71 | 1593 | #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ |
| 11afc1b1 | 1594 | #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ |
| c44ade9e | 1595 | #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ |
| 4f51bf70 | 1596 | #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ |
| 681ae1ad | 1597 | #define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ |
| 9a900eca DS |
1598 | #define IXGBE_EICR_GPI_SDP0_8259X 0x01000000 /* Gen Purpose INT on SDP0 */ |
| 1599 | #define IXGBE_EICR_GPI_SDP1_8259X 0x02000000 /* Gen Purpose INT on SDP1 */ | |
| 1600 | #define IXGBE_EICR_GPI_SDP2_8259X 0x04000000 /* Gen Purpose INT on SDP2 */ | |
| 1601 | #define IXGBE_EICR_GPI_SDP0_X540 0x02000000 | |
| 1602 | #define IXGBE_EICR_GPI_SDP1_X540 0x04000000 | |
| 1603 | #define IXGBE_EICR_GPI_SDP2_X540 0x08000000 | |
| 1604 | #define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540 | |
| 1605 | #define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540 | |
| 1606 | #define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540 | |
| 1607 | #define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540 | |
| 1608 | #define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540 | |
| 1609 | #define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540 | |
| 1610 | #define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540 | |
| 1611 | #define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540 | |
| 1612 | #define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540 | |
| 1613 | #define IXGBE_EICR_GPI_SDP0(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0) | |
| 1614 | #define IXGBE_EICR_GPI_SDP1(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1) | |
| 1615 | #define IXGBE_EICR_GPI_SDP2(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2) | |
| 1616 | ||
| 11afc1b1 | 1617 | #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ |
| 9a799d71 AK |
1618 | #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ |
| 1619 | #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ | |
| 1620 | #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ | |
| 1621 | #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ | |
| 1622 | ||
| 1623 | /* Extended Interrupt Cause Set */ | |
| 1624 | #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ | |
| 11afc1b1 PW |
1625 | #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ |
| 1626 | #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ | |
| 1627 | #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ | |
| 1628 | #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ | |
| c44ade9e JB |
1629 | #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ |
| 1630 | #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ | |
| 681ae1ad | 1631 | #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ |
| 9a900eca DS |
1632 | #define IXGBE_EICS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw) |
| 1633 | #define IXGBE_EICS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw) | |
| 1634 | #define IXGBE_EICS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw) | |
| 11afc1b1 | 1635 | #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ |
| c44ade9e JB |
1636 | #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
| 1637 | #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ | |
| 9a799d71 AK |
1638 | #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
| 1639 | #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ | |
| 1640 | ||
| 1641 | /* Extended Interrupt Mask Set */ | |
| 1642 | #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ | |
| 11afc1b1 PW |
1643 | #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ |
| 1644 | #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ | |
| 1645 | #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ | |
| 1646 | #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ | |
| 9a799d71 AK |
1647 | #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ |
| 1648 | #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ | |
| 4f51bf70 | 1649 | #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermel Sensor Event */ |
| 681ae1ad | 1650 | #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ |
| 9a900eca DS |
1651 | #define IXGBE_EIMS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw) |
| 1652 | #define IXGBE_EIMS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw) | |
| 1653 | #define IXGBE_EIMS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw) | |
| 11afc1b1 | 1654 | #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ |
| c44ade9e | 1655 | #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
| 9a799d71 AK |
1656 | #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ |
| 1657 | #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ | |
| 1658 | #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ | |
| 1659 | ||
| 1660 | /* Extended Interrupt Mask Clear */ | |
| 1661 | #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ | |
| 11afc1b1 PW |
1662 | #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ |
| 1663 | #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ | |
| 1664 | #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ | |
| 1665 | #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ | |
| 9a799d71 AK |
1666 | #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ |
| 1667 | #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ | |
| 681ae1ad | 1668 | #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ |
| 9a900eca DS |
1669 | #define IXGBE_EIMC_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw) |
| 1670 | #define IXGBE_EIMC_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw) | |
| 1671 | #define IXGBE_EIMC_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw) | |
| 11afc1b1 | 1672 | #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ |
| c44ade9e JB |
1673 | #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ |
| 1674 | #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ | |
| 9a799d71 AK |
1675 | #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ |
| 1676 | #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ | |
| 1677 | ||
| c44ade9e | 1678 | #define IXGBE_EIMS_ENABLE_MASK ( \ |
| e7cf745b JK |
1679 | IXGBE_EIMS_RTX_QUEUE | \ |
| 1680 | IXGBE_EIMS_LSC | \ | |
| 1681 | IXGBE_EIMS_TCP_TIMER | \ | |
| 1682 | IXGBE_EIMS_OTHER) | |
| 9a799d71 | 1683 | |
| c44ade9e | 1684 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ |
| 9a799d71 AK |
1685 | #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ |
| 1686 | #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ | |
| 1687 | #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ | |
| 1688 | #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ | |
| 1689 | #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ | |
| 1690 | #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ | |
| 1691 | #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ | |
| 1692 | #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ | |
| 1693 | #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ | |
| 1694 | #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ | |
| 11afc1b1 PW |
1695 | #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ |
| 1696 | #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ | |
| 1697 | #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ | |
| 1698 | #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ | |
| 1699 | #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ | |
| 1700 | #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ | |
| 1701 | #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ | |
| 1702 | #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */ | |
| 1703 | #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ | |
| 1704 | #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ | |
| 1705 | #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ | |
| 1706 | #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ | |
| 1707 | #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ | |
| 1708 | ||
| 1709 | #define IXGBE_MAX_FTQF_FILTERS 128 | |
| 1710 | #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 | |
| 1711 | #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 | |
| 1712 | #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 | |
| 1713 | #define IXGBE_FTQF_PROTOCOL_SCTP 2 | |
| 1714 | #define IXGBE_FTQF_PRIORITY_MASK 0x00000007 | |
| 1715 | #define IXGBE_FTQF_PRIORITY_SHIFT 2 | |
| 1716 | #define IXGBE_FTQF_POOL_MASK 0x0000003F | |
| 1717 | #define IXGBE_FTQF_POOL_SHIFT 8 | |
| 1718 | #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F | |
| 1719 | #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 | |
| 83dfde40 ET |
1720 | #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E |
| 1721 | #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D | |
| 1722 | #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B | |
| 1723 | #define IXGBE_FTQF_DEST_PORT_MASK 0x17 | |
| 1724 | #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F | |
| 11afc1b1 PW |
1725 | #define IXGBE_FTQF_POOL_MASK_EN 0x40000000 |
| 1726 | #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 | |
| 9a799d71 AK |
1727 | |
| 1728 | /* Interrupt clear mask */ | |
| 1729 | #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF | |
| 1730 | ||
| 1731 | /* Interrupt Vector Allocation Registers */ | |
| 1732 | #define IXGBE_IVAR_REG_NUM 25 | |
| e80e887a | 1733 | #define IXGBE_IVAR_REG_NUM_82599 64 |
| 9a799d71 AK |
1734 | #define IXGBE_IVAR_TXRX_ENTRY 96 |
| 1735 | #define IXGBE_IVAR_RX_ENTRY 64 | |
| 1736 | #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) | |
| 1737 | #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) | |
| 1738 | #define IXGBE_IVAR_TX_ENTRY 32 | |
| 1739 | ||
| 1740 | #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ | |
| 1741 | #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ | |
| 1742 | ||
| 1743 | #define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) | |
| 1744 | ||
| 1745 | #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ | |
| 1746 | ||
| 11afc1b1 PW |
1747 | /* ETYPE Queue Filter/Select Bit Masks */ |
| 1748 | #define IXGBE_MAX_ETQF_FILTERS 8 | |
| bff66176 | 1749 | #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ |
| 11afc1b1 | 1750 | #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ |
| 5b7f000f | 1751 | #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ |
| 11afc1b1 PW |
1752 | #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ |
| 1753 | #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ | |
| b4f47a48 | 1754 | #define IXGBE_ETQF_POOL_ENABLE BIT(26) /* bit 26 */ |
| 81faddef | 1755 | #define IXGBE_ETQF_POOL_SHIFT 20 |
| 11afc1b1 PW |
1756 | |
| 1757 | #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ | |
| 1758 | #define IXGBE_ETQS_RX_QUEUE_SHIFT 16 | |
| 1759 | #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ | |
| 1760 | #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ | |
| 1761 | ||
| 1762 | /* | |
| 1763 | * ETQF filter list: one static filter per filter consumer. This is | |
| 1764 | * to avoid filter collisions later. Add new filters | |
| 1765 | * here!! | |
| 1766 | * | |
| 1767 | * Current filters: | |
| 1768 | * EAPOL 802.1x (0x888e): Filter 0 | |
| 83dfde40 | 1769 | * FCoE (0x8906): Filter 2 |
| 11afc1b1 | 1770 | * 1588 (0x88f7): Filter 3 |
| 83dfde40 | 1771 | * FIP (0x8914): Filter 4 |
| f079fa00 ET |
1772 | * LLDP (0x88CC): Filter 5 |
| 1773 | * LACP (0x8809): Filter 6 | |
| 1774 | * FC (0x8808): Filter 7 | |
| 11afc1b1 PW |
1775 | */ |
| 1776 | #define IXGBE_ETQF_FILTER_EAPOL 0 | |
| bff66176 | 1777 | #define IXGBE_ETQF_FILTER_FCOE 2 |
| 11afc1b1 | 1778 | #define IXGBE_ETQF_FILTER_1588 3 |
| af06393b | 1779 | #define IXGBE_ETQF_FILTER_FIP 4 |
| 5b7f000f DS |
1780 | #define IXGBE_ETQF_FILTER_LLDP 5 |
| 1781 | #define IXGBE_ETQF_FILTER_LACP 6 | |
| f079fa00 | 1782 | #define IXGBE_ETQF_FILTER_FC 7 |
| 5b7f000f | 1783 | |
| 9a799d71 AK |
1784 | /* VLAN Control Bit Masks */ |
| 1785 | #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ | |
| 1786 | #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ | |
| 1787 | #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ | |
| 1788 | #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ | |
| 1789 | #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ | |
| 1790 | ||
| 11afc1b1 PW |
1791 | /* VLAN pool filtering masks */ |
| 1792 | #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ | |
| 1793 | #define IXGBE_VLVF_ENTRIES 64 | |
| 7f870475 | 1794 | #define IXGBE_VLVF_VLANID_MASK 0x00000FFF |
| c44ade9e | 1795 | |
| 7f01648a GR |
1796 | /* Per VF Port VLAN insertion rules */ |
| 1797 | #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ | |
| 1798 | #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ | |
| 1799 | ||
| 9a799d71 AK |
1800 | #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ |
| 1801 | ||
| 1802 | /* STATUS Bit Masks */ | |
| 11afc1b1 PW |
1803 | #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ |
| 1804 | #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ | |
| 1805 | #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ | |
| 9a799d71 AK |
1806 | |
| 1807 | #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ | |
| 1808 | #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ | |
| 1809 | ||
| 1810 | /* ESDP Bit Masks */ | |
| 50ac58ba PWJ |
1811 | #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ |
| 1812 | #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ | |
| 1813 | #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ | |
| 1814 | #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ | |
| 11afc1b1 PW |
1815 | #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ |
| 1816 | #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ | |
| 1817 | #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ | |
| 681ae1ad | 1818 | #define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ |
| 8f58332b | 1819 | #define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ |
| 9a799d71 | 1820 | #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ |
| 11afc1b1 | 1821 | #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ |
| 681ae1ad | 1822 | #define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 Native Function */ |
| 8f58332b | 1823 | #define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ |
| 9a799d71 AK |
1824 | |
| 1825 | /* LEDCTL Bit Masks */ | |
| 1826 | #define IXGBE_LED_IVRT_BASE 0x00000040 | |
| 1827 | #define IXGBE_LED_BLINK_BASE 0x00000080 | |
| 1828 | #define IXGBE_LED_MODE_MASK_BASE 0x0000000F | |
| 1829 | #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) | |
| 795be954 | 1830 | #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i)) |
| 9a799d71 AK |
1831 | #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) |
| 1832 | #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) | |
| 1833 | #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) | |
| a0ad55a3 DS |
1834 | #define IXGBE_X557_LED_MANUAL_SET_MASK BIT(8) |
| 1835 | #define IXGBE_X557_MAX_LED_INDEX 3 | |
| 1836 | #define IXGBE_X557_LED_PROVISIONING 0xC430 | |
| 9a799d71 AK |
1837 | |
| 1838 | /* LED modes */ | |
| 1839 | #define IXGBE_LED_LINK_UP 0x0 | |
| 1840 | #define IXGBE_LED_LINK_10G 0x1 | |
| 1841 | #define IXGBE_LED_MAC 0x2 | |
| 1842 | #define IXGBE_LED_FILTER 0x3 | |
| 1843 | #define IXGBE_LED_LINK_ACTIVE 0x4 | |
| 1844 | #define IXGBE_LED_LINK_1G 0x5 | |
| 1845 | #define IXGBE_LED_ON 0xE | |
| 1846 | #define IXGBE_LED_OFF 0xF | |
| 1847 | ||
| 1848 | /* AUTOC Bit Masks */ | |
| 3201d313 | 1849 | #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 |
| 9a799d71 AK |
1850 | #define IXGBE_AUTOC_KX4_SUPP 0x80000000 |
| 1851 | #define IXGBE_AUTOC_KX_SUPP 0x40000000 | |
| 1852 | #define IXGBE_AUTOC_PAUSE 0x30000000 | |
| 539e5f02 PWJ |
1853 | #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 |
| 1854 | #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 | |
| 9a799d71 AK |
1855 | #define IXGBE_AUTOC_RF 0x08000000 |
| 1856 | #define IXGBE_AUTOC_PD_TMR 0x06000000 | |
| 1857 | #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 | |
| 1858 | #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 | |
| 1859 | #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 | |
| 11afc1b1 PW |
1860 | #define IXGBE_AUTOC_FECA 0x00040000 |
| 1861 | #define IXGBE_AUTOC_FECR 0x00020000 | |
| 1862 | #define IXGBE_AUTOC_KR_SUPP 0x00010000 | |
| 9a799d71 AK |
1863 | #define IXGBE_AUTOC_AN_RESTART 0x00001000 |
| 1864 | #define IXGBE_AUTOC_FLU 0x00000001 | |
| 1865 | #define IXGBE_AUTOC_LMS_SHIFT 13 | |
| 11afc1b1 PW |
1866 | #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) |
| 1867 | #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1868 | #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1869 | #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1870 | #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) | |
| c44ade9e JB |
1871 | #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) |
| 1872 | #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1873 | #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1874 | #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1875 | #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1876 | #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) | |
| 1877 | #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) | |
| 1878 | ||
| 11afc1b1 PW |
1879 | #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 |
| 1880 | #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 | |
| 1881 | #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 | |
| 1882 | #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 | |
| b4f47a48 JK |
1883 | #define IXGBE_AUTOC_10G_XAUI (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) |
| 1884 | #define IXGBE_AUTOC_10G_KX4 (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) | |
| 1885 | #define IXGBE_AUTOC_10G_CX4 (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) | |
| 1886 | #define IXGBE_AUTOC_1G_BX (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) | |
| 1887 | #define IXGBE_AUTOC_1G_KX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) | |
| 1888 | #define IXGBE_AUTOC_1G_SFI (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) | |
| 1889 | #define IXGBE_AUTOC_1G_KX_BX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) | |
| 11afc1b1 PW |
1890 | |
| 1891 | #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 | |
| 1892 | #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 | |
| 1893 | #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 | |
| b4f47a48 JK |
1894 | #define IXGBE_AUTOC2_10G_KR (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) |
| 1895 | #define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) | |
| 1896 | #define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) | |
| f4f1040a | 1897 | #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 |
| 46d5cedd | 1898 | #define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 |
| 9a799d71 | 1899 | |
| 83dfde40 ET |
1900 | #define IXGBE_MACC_FLU 0x00000001 |
| 1901 | #define IXGBE_MACC_FSV_10G 0x00030000 | |
| 1902 | #define IXGBE_MACC_FS 0x00040000 | |
| 1903 | #define IXGBE_MAC_RX2TX_LPBK 0x00000002 | |
| 1904 | ||
| dbedd44e | 1905 | /* Veto Bit definition */ |
| c97506ab DS |
1906 | #define IXGBE_MMNGC_MNG_VETO 0x00000001 |
| 1907 | ||
| 9a799d71 AK |
1908 | /* LINKS Bit Masks */ |
| 1909 | #define IXGBE_LINKS_KX_AN_COMP 0x80000000 | |
| 1910 | #define IXGBE_LINKS_UP 0x40000000 | |
| 1911 | #define IXGBE_LINKS_SPEED 0x20000000 | |
| 1912 | #define IXGBE_LINKS_MODE 0x18000000 | |
| 1913 | #define IXGBE_LINKS_RX_MODE 0x06000000 | |
| 1914 | #define IXGBE_LINKS_TX_MODE 0x01800000 | |
| 1915 | #define IXGBE_LINKS_XGXS_EN 0x00400000 | |
| 11afc1b1 | 1916 | #define IXGBE_LINKS_SGMII_EN 0x02000000 |
| 9a799d71 AK |
1917 | #define IXGBE_LINKS_PCS_1G_EN 0x00200000 |
| 1918 | #define IXGBE_LINKS_1G_AN_EN 0x00100000 | |
| 1919 | #define IXGBE_LINKS_KX_AN_IDLE 0x00080000 | |
| 1920 | #define IXGBE_LINKS_1G_SYNC 0x00040000 | |
| 1921 | #define IXGBE_LINKS_10G_ALIGN 0x00020000 | |
| 1922 | #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 | |
| 1923 | #define IXGBE_LINKS_TL_FAULT 0x00001000 | |
| 1924 | #define IXGBE_LINKS_SIGNAL 0x00000F00 | |
| 1925 | ||
| 9a75a1ac | 1926 | #define IXGBE_LINKS_SPEED_NON_STD 0x08000000 |
| 11afc1b1 PW |
1927 | #define IXGBE_LINKS_SPEED_82599 0x30000000 |
| 1928 | #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 | |
| 1929 | #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 | |
| 1930 | #define IXGBE_LINKS_SPEED_100_82599 0x10000000 | |
| cf8280ee | 1931 | #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ |
| 9a799d71 AK |
1932 | #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
| 1933 | ||
| 539e5f02 PWJ |
1934 | #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 |
| 1935 | ||
| 0ecc061d PWJ |
1936 | /* PCS1GLSTA Bit Masks */ |
| 1937 | #define IXGBE_PCS1GLSTA_LINK_OK 1 | |
| 1938 | #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 | |
| 1939 | #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 | |
| 1940 | #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 | |
| 1941 | #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 | |
| 1942 | #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 | |
| 1943 | #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 | |
| 1944 | ||
| 1945 | #define IXGBE_PCS1GANA_SYM_PAUSE 0x80 | |
| 1946 | #define IXGBE_PCS1GANA_ASM_PAUSE 0x100 | |
| 1947 | ||
| 1948 | /* PCS1GLCTL Bit Masks */ | |
| 1949 | #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ | |
| 1950 | #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 | |
| 1951 | #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 | |
| 1952 | #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 | |
| 1953 | #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 | |
| 1954 | #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 | |
| 1955 | ||
| 539e5f02 PWJ |
1956 | /* ANLP1 Bit Masks */ |
| 1957 | #define IXGBE_ANLP1_PAUSE 0x0C00 | |
| 1958 | #define IXGBE_ANLP1_SYM_PAUSE 0x0400 | |
| 1959 | #define IXGBE_ANLP1_ASM_PAUSE 0x0800 | |
| a7f5a5fc DS |
1960 | #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 |
| 1961 | ||
| 9a799d71 AK |
1962 | /* SW Semaphore Register bitmasks */ |
| 1963 | #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | |
| 1964 | #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | |
| 1965 | #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ | |
| 21ce849b | 1966 | #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ |
| 9a799d71 | 1967 | |
| 21ce849b | 1968 | /* SW_FW_SYNC/GSSR definitions */ |
| 6a14ee0c DS |
1969 | #define IXGBE_GSSR_EEP_SM 0x0001 |
| 1970 | #define IXGBE_GSSR_PHY0_SM 0x0002 | |
| 1971 | #define IXGBE_GSSR_PHY1_SM 0x0004 | |
| 1972 | #define IXGBE_GSSR_MAC_CSR_SM 0x0008 | |
| 1973 | #define IXGBE_GSSR_FLASH_SM 0x0010 | |
| 207969b9 | 1974 | #define IXGBE_GSSR_NVM_UPDATE_SM 0x0200 |
| 6a14ee0c | 1975 | #define IXGBE_GSSR_SW_MNG_SM 0x0400 |
| 207969b9 | 1976 | #define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */ |
| 6a14ee0c DS |
1977 | #define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys & I2Cs */ |
| 1978 | #define IXGBE_GSSR_I2C_MASK 0x1800 | |
| 449e21a9 | 1979 | #define IXGBE_GSSR_NVM_PHY_MASK 0xF |
| 83dfde40 ET |
1980 | |
| 1981 | /* FW Status register bitmask */ | |
| 1982 | #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ | |
| 9a799d71 AK |
1983 | |
| 1984 | /* EEC Register */ | |
| 1985 | #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ | |
| 1986 | #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ | |
| 1987 | #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ | |
| 1988 | #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ | |
| 1989 | #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ | |
| 1990 | #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ | |
| 1991 | #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ | |
| 1992 | #define IXGBE_EEC_FWE_SHIFT 4 | |
| 1993 | #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ | |
| 1994 | #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ | |
| 1995 | #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ | |
| 1996 | #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ | |
| 21ce849b | 1997 | #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ |
| fe15e8e1 | 1998 | #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ |
| 21ce849b | 1999 | #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ |
| 9a799d71 AK |
2000 | /* EEPROM Addressing bits based on type (0-small, 1-large) */ |
| 2001 | #define IXGBE_EEC_ADDR_SIZE 0x00000400 | |
| 2002 | #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ | |
| 83dfde40 | 2003 | #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ |
| 9a799d71 AK |
2004 | |
| 2005 | #define IXGBE_EEC_SIZE_SHIFT 11 | |
| 2006 | #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 | |
| 2007 | #define IXGBE_EEPROM_OPCODE_BITS 8 | |
| 2008 | ||
| 289700db DS |
2009 | /* Part Number String Length */ |
| 2010 | #define IXGBE_PBANUM_LENGTH 11 | |
| 2011 | ||
| 9a799d71 | 2012 | /* Checksum and EEPROM pointers */ |
| 6a14ee0c DS |
2013 | #define IXGBE_PBANUM_PTR_GUARD 0xFAFA |
| 2014 | #define IXGBE_EEPROM_CHECKSUM 0x3F | |
| 2015 | #define IXGBE_EEPROM_SUM 0xBABA | |
| c898fe28 MR |
2016 | #define IXGBE_EEPROM_CTRL_4 0x45 |
| 2017 | #define IXGBE_EE_CTRL_4_INST_ID 0x10 | |
| 2018 | #define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4 | |
| 6a14ee0c DS |
2019 | #define IXGBE_PCIE_ANALOG_PTR 0x03 |
| 2020 | #define IXGBE_ATLAS0_CONFIG_PTR 0x04 | |
| 2021 | #define IXGBE_PHY_PTR 0x04 | |
| 2022 | #define IXGBE_ATLAS1_CONFIG_PTR 0x05 | |
| 2023 | #define IXGBE_OPTION_ROM_PTR 0x05 | |
| 2024 | #define IXGBE_PCIE_GENERAL_PTR 0x06 | |
| 2025 | #define IXGBE_PCIE_CONFIG0_PTR 0x07 | |
| 2026 | #define IXGBE_PCIE_CONFIG1_PTR 0x08 | |
| 2027 | #define IXGBE_CORE0_PTR 0x09 | |
| 2028 | #define IXGBE_CORE1_PTR 0x0A | |
| 2029 | #define IXGBE_MAC0_PTR 0x0B | |
| 2030 | #define IXGBE_MAC1_PTR 0x0C | |
| 2031 | #define IXGBE_CSR0_CONFIG_PTR 0x0D | |
| 2032 | #define IXGBE_CSR1_CONFIG_PTR 0x0E | |
| 2033 | #define IXGBE_PCIE_ANALOG_PTR_X550 0x02 | |
| 2034 | #define IXGBE_SHADOW_RAM_SIZE_X550 0x4000 | |
| 2035 | #define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24 | |
| 2036 | #define IXGBE_PCIE_CONFIG_SIZE 0x08 | |
| 2037 | #define IXGBE_EEPROM_LAST_WORD 0x41 | |
| 2038 | #define IXGBE_FW_PTR 0x0F | |
| 2039 | #define IXGBE_PBANUM0_PTR 0x15 | |
| 2040 | #define IXGBE_PBANUM1_PTR 0x16 | |
| 2041 | #define IXGBE_FREE_SPACE_PTR 0X3E | |
| e1ea9158 DS |
2042 | |
| 2043 | /* External Thermal Sensor Config */ | |
| 2044 | #define IXGBE_ETS_CFG 0x26 | |
| 2045 | #define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0 | |
| 2046 | #define IXGBE_ETS_LTHRES_DELTA_SHIFT 6 | |
| 2047 | #define IXGBE_ETS_TYPE_MASK 0x0038 | |
| 2048 | #define IXGBE_ETS_TYPE_SHIFT 3 | |
| 2049 | #define IXGBE_ETS_TYPE_EMC 0x000 | |
| 2050 | #define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000 | |
| 2051 | #define IXGBE_ETS_NUM_SENSORS_MASK 0x0007 | |
| 2052 | #define IXGBE_ETS_DATA_LOC_MASK 0x3C00 | |
| 2053 | #define IXGBE_ETS_DATA_LOC_SHIFT 10 | |
| 2054 | #define IXGBE_ETS_DATA_INDEX_MASK 0x0300 | |
| 2055 | #define IXGBE_ETS_DATA_INDEX_SHIFT 8 | |
| 2056 | #define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF | |
| 2057 | ||
| 0365e6e4 | 2058 | #define IXGBE_SAN_MAC_ADDR_PTR 0x28 |
| 83dfde40 ET |
2059 | #define IXGBE_DEVICE_CAPS 0x2C |
| 2060 | #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 | |
| 11afc1b1 | 2061 | #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 |
| 71161302 | 2062 | #define IXGBE_MAX_MSIX_VECTORS_82599 0x40 |
| eb7f139c | 2063 | #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 |
| 71161302 | 2064 | #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 |
| eb7f139c PWJ |
2065 | |
| 2066 | /* MSI-X capability fields masks */ | |
| 2067 | #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF | |
| 9a799d71 | 2068 | |
| c44ade9e JB |
2069 | /* Legacy EEPROM word offsets */ |
| 2070 | #define IXGBE_ISCSI_BOOT_CAPS 0x0033 | |
| 2071 | #define IXGBE_ISCSI_SETUP_PORT_0 0x0030 | |
| 2072 | #define IXGBE_ISCSI_SETUP_PORT_1 0x0034 | |
| 2073 | ||
| 9a799d71 AK |
2074 | /* EEPROM Commands - SPI */ |
| 2075 | #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ | |
| 2076 | #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 | |
| 2077 | #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ | |
| 2078 | #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ | |
| 2079 | #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ | |
| 2080 | #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ | |
| c44ade9e | 2081 | /* EEPROM reset Write Enable latch */ |
| 9a799d71 AK |
2082 | #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 |
| 2083 | #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ | |
| 2084 | #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ | |
| 2085 | #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ | |
| 2086 | #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ | |
| 2087 | #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ | |
| 2088 | ||
| 2089 | /* EEPROM Read Register */ | |
| 21ce849b MC |
2090 | #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ |
| 2091 | #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ | |
| 2092 | #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ | |
| 2093 | #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | |
| 2094 | #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ | |
| 2095 | #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */ | |
| 9a799d71 | 2096 | |
| 6ac74394 DS |
2097 | #define NVM_INIT_CTRL_3 0x38 |
| 2098 | #define NVM_INIT_CTRL_3_LPLU 0x8 | |
| 2099 | #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40 | |
| 2100 | #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100 | |
| 2101 | ||
| 68c7005d ET |
2102 | #define IXGBE_EEPROM_PAGE_SIZE_MAX 128 |
| 2103 | #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */ | |
| 2104 | #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */ | |
| 2105 | ||
| f68bfdb1 JK |
2106 | #define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ |
| 2107 | #define IXGBE_EEPROM_CCD_BIT 2 /* EEPROM Core Clock Disable bit */ | |
| 2108 | ||
| 9a799d71 AK |
2109 | #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS |
| 2110 | #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ | |
| 2111 | #endif | |
| 2112 | ||
| 21ce849b MC |
2113 | #ifndef IXGBE_EERD_EEWR_ATTEMPTS |
| 2114 | /* Number of 5 microseconds we wait for EERD read and | |
| 2115 | * EERW write to complete */ | |
| 2116 | #define IXGBE_EERD_EEWR_ATTEMPTS 100000 | |
| 2117 | #endif | |
| 2118 | ||
| 2119 | #ifndef IXGBE_FLUDONE_ATTEMPTS | |
| 2120 | /* # attempts we wait for flush update to complete */ | |
| 2121 | #define IXGBE_FLUDONE_ATTEMPTS 20000 | |
| 9a799d71 AK |
2122 | #endif |
| 2123 | ||
| c9130180 ET |
2124 | #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ |
| 2125 | #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ | |
| 2126 | #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ | |
| 2127 | #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ | |
| 2128 | ||
| 0365e6e4 PW |
2129 | #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 |
| 2130 | #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 | |
| 04193058 | 2131 | #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 |
| eacd73f7 | 2132 | #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 |
| 4319a797 | 2133 | #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR BIT(7) |
| 0fa6d832 ET |
2134 | #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 |
| 2135 | #define IXGBE_FW_LESM_STATE_1 0x1 | |
| 2136 | #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ | |
| 794caeb2 | 2137 | #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 |
| 83dfde40 ET |
2138 | #define IXGBE_FW_PATCH_VERSION_4 0x7 |
| 2139 | #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ | |
| 2140 | #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ | |
| 2141 | #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ | |
| 2142 | #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ | |
| 2143 | #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ | |
| 383ff34b YZ |
2144 | #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ |
| 2145 | #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */ | |
| 2146 | #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */ | |
| 2147 | #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */ | |
| 2148 | #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */ | |
| 2149 | #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */ | |
| 2150 | #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */ | |
| 2151 | #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */ | |
| 2152 | ||
| c23f5b6b ET |
2153 | #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ |
| 2154 | #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ | |
| 2155 | #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ | |
| 2156 | ||
| 9a799d71 | 2157 | /* PCI Bus Info */ |
| a4297dc2 ET |
2158 | #define IXGBE_PCI_DEVICE_STATUS 0xAA |
| 2159 | #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 | |
| 9a799d71 | 2160 | #define IXGBE_PCI_LINK_STATUS 0xB2 |
| 202ff1ec | 2161 | #define IXGBE_PCI_DEVICE_CONTROL2 0xC8 |
| 9a799d71 AK |
2162 | #define IXGBE_PCI_LINK_WIDTH 0x3F0 |
| 2163 | #define IXGBE_PCI_LINK_WIDTH_1 0x10 | |
| 2164 | #define IXGBE_PCI_LINK_WIDTH_2 0x20 | |
| 2165 | #define IXGBE_PCI_LINK_WIDTH_4 0x40 | |
| 2166 | #define IXGBE_PCI_LINK_WIDTH_8 0x80 | |
| 2167 | #define IXGBE_PCI_LINK_SPEED 0xF | |
| 2168 | #define IXGBE_PCI_LINK_SPEED_2500 0x1 | |
| 2169 | #define IXGBE_PCI_LINK_SPEED_5000 0x2 | |
| e8710a5f | 2170 | #define IXGBE_PCI_LINK_SPEED_8000 0x3 |
| 11afc1b1 PW |
2171 | #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E |
| 2172 | #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 | |
| 202ff1ec | 2173 | #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 |
| 9a799d71 | 2174 | |
| 1f86c983 DS |
2175 | #define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf |
| 2176 | #define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 | |
| 2177 | #define IXGBE_PCIDEVCTRL2_50_100us 0x1 | |
| 2178 | #define IXGBE_PCIDEVCTRL2_1_2ms 0x2 | |
| 2179 | #define IXGBE_PCIDEVCTRL2_16_32ms 0x5 | |
| 2180 | #define IXGBE_PCIDEVCTRL2_65_130ms 0x6 | |
| 2181 | #define IXGBE_PCIDEVCTRL2_260_520ms 0x9 | |
| 2182 | #define IXGBE_PCIDEVCTRL2_1_2s 0xa | |
| 2183 | #define IXGBE_PCIDEVCTRL2_4_8s 0xd | |
| 2184 | #define IXGBE_PCIDEVCTRL2_17_34s 0xe | |
| 2185 | ||
| 9a799d71 | 2186 | /* Number of 100 microseconds we wait for PCI Express master disable */ |
| 1f86c983 | 2187 | #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 |
| 9a799d71 | 2188 | |
| 9a799d71 AK |
2189 | /* RAH */ |
| 2190 | #define IXGBE_RAH_VIND_MASK 0x003C0000 | |
| 2191 | #define IXGBE_RAH_VIND_SHIFT 18 | |
| 2192 | #define IXGBE_RAH_AV 0x80000000 | |
| c44ade9e | 2193 | #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF |
| 9a799d71 | 2194 | |
| 9a799d71 AK |
2195 | /* Header split receive */ |
| 2196 | #define IXGBE_RFCTL_ISCSI_DIS 0x00000001 | |
| 2197 | #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E | |
| 2198 | #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 | |
| 6dcc28b9 | 2199 | #define IXGBE_RFCTL_RSC_DIS 0x00000020 |
| 9a799d71 AK |
2200 | #define IXGBE_RFCTL_NFSW_DIS 0x00000040 |
| 2201 | #define IXGBE_RFCTL_NFSR_DIS 0x00000080 | |
| 2202 | #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 | |
| 2203 | #define IXGBE_RFCTL_NFS_VER_SHIFT 8 | |
| 2204 | #define IXGBE_RFCTL_NFS_VER_2 0 | |
| 2205 | #define IXGBE_RFCTL_NFS_VER_3 1 | |
| 2206 | #define IXGBE_RFCTL_NFS_VER_4 2 | |
| 2207 | #define IXGBE_RFCTL_IPV6_DIS 0x00000400 | |
| 2208 | #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 | |
| 2209 | #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 | |
| 2210 | #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 | |
| 2211 | #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | |
| 2212 | ||
| 2213 | /* Transmit Config masks */ | |
| 2214 | #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ | |
| 2215 | #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ | |
| 83dfde40 | 2216 | #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ |
| 9a799d71 AK |
2217 | /* Enable short packet padding to 64 bytes */ |
| 2218 | #define IXGBE_TX_PAD_ENABLE 0x00000400 | |
| 2219 | #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ | |
| 2220 | /* This allows for 16K packets + 4k for vlan */ | |
| 2221 | #define IXGBE_MAX_FRAME_SZ 0x40040000 | |
| 2222 | ||
| 2223 | #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ | |
| c44ade9e | 2224 | #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ |
| 9a799d71 AK |
2225 | |
| 2226 | /* Receive Config masks */ | |
| 2227 | #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ | |
| 2228 | #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ | |
| 2229 | #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ | |
| ff9d1a5a | 2230 | #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ |
| e9f98072 GR |
2231 | #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ |
| 2232 | #define IXGBE_RXDCTL_RLPML_EN 0x00008000 | |
| 83dfde40 | 2233 | #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ |
| 9a799d71 | 2234 | |
| 681ae1ad JK |
2235 | #define IXGBE_TSAUXC_EN_CLK 0x00000004 |
| 2236 | #define IXGBE_TSAUXC_SYNCLK 0x00000008 | |
| 2237 | #define IXGBE_TSAUXC_SDP0_INT 0x00000040 | |
| a9763f3c | 2238 | #define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000 |
| 681ae1ad | 2239 | |
| 3a6a4eda JK |
2240 | #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ |
| 2241 | #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ | |
| 2242 | ||
| 2243 | #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ | |
| 2244 | #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ | |
| 2245 | #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 | |
| 2246 | #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 | |
| 2247 | #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 | |
| a9763f3c | 2248 | #define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08 |
| 3a6a4eda JK |
2249 | #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A |
| 2250 | #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ | |
| a9763f3c MR |
2251 | #define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */ |
| 2252 | ||
| 2253 | #define IXGBE_TSIM_TXTS 0x00000002 | |
| 3a6a4eda JK |
2254 | |
| 2255 | #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF | |
| 2256 | #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 | |
| 2257 | #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 | |
| 2258 | #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 | |
| 2259 | #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 | |
| 2260 | #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 | |
| 2261 | ||
| 2262 | #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 | |
| 2263 | #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 | |
| 2264 | #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 | |
| 2265 | #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 | |
| 2266 | #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 | |
| 2267 | #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 | |
| 2268 | #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 | |
| 2269 | #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 | |
| 2270 | #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 | |
| 2271 | #define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00 | |
| 2272 | #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 | |
| 2273 | ||
| 9a799d71 AK |
2274 | #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ |
| 2275 | #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ | |
| 2276 | #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ | |
| 2277 | #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ | |
| 2278 | #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ | |
| 2279 | #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ | |
| c44ade9e | 2280 | /* Receive Priority Flow Control Enable */ |
| 9a799d71 AK |
2281 | #define IXGBE_FCTRL_RPFCE 0x00004000 |
| 2282 | #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ | |
| 11afc1b1 PW |
2283 | #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ |
| 2284 | #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ | |
| 2285 | #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ | |
| 2286 | #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ | |
| 041441d0 | 2287 | #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Receive FC Mask */ |
| 9a799d71 | 2288 | |
| 45a5f720 JF |
2289 | #define IXGBE_MFLCN_RPFCE_SHIFT 4 |
| 2290 | ||
| 9a799d71 AK |
2291 | /* Multiple Receive Queue Control */ |
| 2292 | #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ | |
| 11afc1b1 PW |
2293 | #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ |
| 2294 | #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ | |
| 2295 | #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ | |
| 2296 | #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ | |
| 2297 | #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ | |
| 2298 | #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ | |
| 2299 | #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ | |
| 2300 | #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ | |
| 2301 | #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ | |
| 2302 | #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ | |
| 9a799d71 AK |
2303 | #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 |
| 2304 | #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 | |
| 2305 | #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 | |
| 2306 | #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 | |
| 2307 | #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 | |
| 2308 | #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 | |
| 2309 | #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 | |
| 2310 | #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 | |
| 2311 | #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 | |
| 2312 | #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 | |
| 0f9b232b | 2313 | #define IXGBE_MRQC_MULTIPLE_RSS 0x00002000 |
| 11afc1b1 PW |
2314 | #define IXGBE_MRQC_L3L4TXSWEN 0x00008000 |
| 2315 | ||
| cb6d0f5e JK |
2316 | #define IXGBE_FWSM_TS_ENABLED 0x1 |
| 2317 | ||
| 11afc1b1 | 2318 | /* Queue Drop Enable */ |
| 87397379 | 2319 | #define IXGBE_QDE_ENABLE 0x00000001 |
| 9a75a1ac | 2320 | #define IXGBE_QDE_HIDE_VLAN 0x00000002 |
| 87397379 AD |
2321 | #define IXGBE_QDE_IDX_MASK 0x00007F00 |
| 2322 | #define IXGBE_QDE_IDX_SHIFT 8 | |
| 2323 | #define IXGBE_QDE_WRITE 0x00010000 | |
| 9a799d71 AK |
2324 | |
| 2325 | #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
| 2326 | #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
| 2327 | #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
| 2328 | #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
| 2329 | #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | |
| 2330 | #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ | |
| 2331 | #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | |
| 2332 | #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | |
| 2333 | #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | |
| 2334 | ||
| 11afc1b1 PW |
2335 | #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 |
| 2336 | #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 | |
| 2337 | #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 | |
| 2338 | #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 | |
| 2339 | #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 | |
| 2340 | /* Multiple Transmit Queue Command Register */ | |
| 2341 | #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ | |
| 2342 | #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ | |
| 2343 | #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ | |
| d988eadb DS |
2344 | #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ |
| 2345 | #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ | |
| 11afc1b1 | 2346 | #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ |
| 8b1c0b24 | 2347 | #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */ |
| 11afc1b1 | 2348 | |
| 9a799d71 AK |
2349 | /* Receive Descriptor bit definitions */ |
| 2350 | #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ | |
| 2351 | #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ | |
| 11afc1b1 | 2352 | #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ |
| 9a799d71 | 2353 | #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
| 11afc1b1 PW |
2354 | #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ |
| 2355 | #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 | |
| c44ade9e | 2356 | #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
| 9a799d71 AK |
2357 | #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ |
| 2358 | #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | |
| 2359 | #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | |
| 2360 | #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ | |
| 3f207800 | 2361 | #define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */ |
| 9a799d71 AK |
2362 | #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ |
| 2363 | #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ | |
| 2364 | #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ | |
| 11afc1b1 | 2365 | #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ |
| a9763f3c | 2366 | #define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */ |
| 11afc1b1 PW |
2367 | #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ |
| 2368 | #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ | |
| 2369 | #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ | |
| 9a799d71 AK |
2370 | #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ |
| 2371 | #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ | |
| 2372 | #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ | |
| 2373 | #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ | |
| 2374 | #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ | |
| 2375 | #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ | |
| 2376 | #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ | |
| 2377 | #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ | |
| 11afc1b1 PW |
2378 | #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ |
| 2379 | #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ | |
| 3f207800 | 2380 | #define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */ |
| bff66176 YZ |
2381 | #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */ |
| 2382 | #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ | |
| bfde493e PWJ |
2383 | #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ |
| 2384 | #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ | |
| 2385 | #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ | |
| c44ade9e | 2386 | #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ |
| 9a799d71 AK |
2387 | #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ |
| 2388 | #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ | |
| 2389 | #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ | |
| 2390 | #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ | |
| 2391 | #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ | |
| 2392 | #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ | |
| 2393 | #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ | |
| 2394 | #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | |
| 2395 | #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | |
| 2396 | #define IXGBE_RXD_PRI_SHIFT 13 | |
| 2397 | #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ | |
| 2398 | #define IXGBE_RXD_CFI_SHIFT 12 | |
| 2399 | ||
| 11afc1b1 PW |
2400 | #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ |
| 2401 | #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ | |
| 2402 | #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ | |
| 2403 | #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ | |
| 2404 | #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ | |
| bff66176 YZ |
2405 | #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ |
| 2406 | #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ | |
| 2407 | #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ | |
| 2408 | #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ | |
| 2409 | #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ | |
| 2410 | #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ | |
| 3a6a4eda | 2411 | #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE 1588 Time Stamp */ |
| 11afc1b1 PW |
2412 | |
| 2413 | /* PSRTYPE bit definitions */ | |
| 2414 | #define IXGBE_PSRTYPE_TCPHDR 0x00000010 | |
| 2415 | #define IXGBE_PSRTYPE_UDPHDR 0x00000020 | |
| 2416 | #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 | |
| 2417 | #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 | |
| dfa12f05 | 2418 | #define IXGBE_PSRTYPE_L2HDR 0x00001000 |
| c44ade9e | 2419 | |
| 9a799d71 | 2420 | /* SRRCTL bit definitions */ |
| c44ade9e | 2421 | #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ |
| 11afc1b1 PW |
2422 | #define IXGBE_SRRCTL_RDMTS_SHIFT 22 |
| 2423 | #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 | |
| 2424 | #define IXGBE_SRRCTL_DROP_EN 0x10000000 | |
| c44ade9e JB |
2425 | #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F |
| 2426 | #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 | |
| 2427 | #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 | |
| 9a799d71 AK |
2428 | #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 |
| 2429 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 | |
| 2430 | #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 | |
| 2431 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 | |
| c44ade9e | 2432 | #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 |
| 9a799d71 AK |
2433 | |
| 2434 | #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 | |
| 2435 | #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF | |
| 2436 | ||
| 2437 | #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F | |
| 2438 | #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 | |
| 11afc1b1 | 2439 | #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 |
| 9a799d71 | 2440 | #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 |
| 83dfde40 ET |
2441 | #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 |
| 2442 | #define IXGBE_RXDADV_RSCCNT_SHIFT 17 | |
| 9a799d71 AK |
2443 | #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 |
| 2444 | #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 | |
| 2445 | #define IXGBE_RXDADV_SPH 0x8000 | |
| 2446 | ||
| 2447 | /* RSS Hash results */ | |
| 2448 | #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 | |
| 2449 | #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 | |
| 2450 | #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 | |
| 2451 | #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 | |
| 2452 | #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 | |
| 2453 | #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 | |
| 2454 | #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 | |
| 2455 | #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 | |
| 2456 | #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 | |
| 2457 | #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 | |
| 2458 | ||
| 2459 | /* RSS Packet Types as indicated in the receive descriptor. */ | |
| 2460 | #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 | |
| 2461 | #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ | |
| 2462 | #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ | |
| 2463 | #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ | |
| 2464 | #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ | |
| 2465 | #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ | |
| 2466 | #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ | |
| 2467 | #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ | |
| 2468 | #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ | |
| 3f207800 DS |
2469 | #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ |
| 2470 | #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ | |
| 11afc1b1 PW |
2471 | #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ |
| 2472 | #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ | |
| 2473 | #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ | |
| 2474 | #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ | |
| 2475 | #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ | |
| 2476 | #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ | |
| 2477 | ||
| 2478 | /* Security Processing bit Indication */ | |
| 2479 | #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 | |
| 2480 | #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 | |
| 2481 | #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 | |
| 2482 | #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 | |
| 2483 | #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 | |
| 2484 | ||
| 9a799d71 | 2485 | /* Masks to determine if packets should be dropped due to frame errors */ |
| c44ade9e | 2486 | #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ |
| e7cf745b JK |
2487 | IXGBE_RXD_ERR_CE | \ |
| 2488 | IXGBE_RXD_ERR_LE | \ | |
| 2489 | IXGBE_RXD_ERR_PE | \ | |
| 2490 | IXGBE_RXD_ERR_OSE | \ | |
| 2491 | IXGBE_RXD_ERR_USE) | |
| c44ade9e JB |
2492 | |
| 2493 | #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ | |
| e7cf745b JK |
2494 | IXGBE_RXDADV_ERR_CE | \ |
| 2495 | IXGBE_RXDADV_ERR_LE | \ | |
| 2496 | IXGBE_RXDADV_ERR_PE | \ | |
| 2497 | IXGBE_RXDADV_ERR_OSE | \ | |
| 2498 | IXGBE_RXDADV_ERR_USE) | |
| 9a799d71 AK |
2499 | |
| 2500 | /* Multicast bit mask */ | |
| 2501 | #define IXGBE_MCSTCTRL_MFE 0x4 | |
| 2502 | ||
| 2503 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ | |
| 2504 | #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
| 2505 | #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
| 2506 | #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 | |
| 2507 | ||
| 2508 | /* Vlan-specific macros */ | |
| 2509 | #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ | |
| 2510 | #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ | |
| 2511 | #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ | |
| 2512 | #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT | |
| 2513 | ||
| 7f870475 GR |
2514 | /* SR-IOV specific macros */ |
| 2515 | #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) | |
| 795be954 AD |
2516 | #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) |
| 2517 | #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600)) | |
| 2518 | #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) | |
| dbf231af | 2519 | /* Translated register #defines */ |
| 07923c17 ET |
2520 | #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) |
| 2521 | #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) | |
| dbf231af AD |
2522 | #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) |
| 2523 | #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) | |
| 2524 | ||
| 2525 | #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ | |
| 2526 | (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index))) | |
| 2527 | #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ | |
| 2528 | (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index))) | |
| 7f870475 | 2529 | |
| 07923c17 ET |
2530 | #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \ |
| 2531 | (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index))) | |
| 2532 | #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \ | |
| 2533 | (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index))) | |
| 2534 | ||
| bfde493e | 2535 | enum ixgbe_fdir_pballoc_type { |
| c04f6ca8 AD |
2536 | IXGBE_FDIR_PBALLOC_NONE = 0, |
| 2537 | IXGBE_FDIR_PBALLOC_64K = 1, | |
| 2538 | IXGBE_FDIR_PBALLOC_128K = 2, | |
| 2539 | IXGBE_FDIR_PBALLOC_256K = 3, | |
| bfde493e PWJ |
2540 | }; |
| 2541 | #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16 | |
| 2542 | ||
| 2543 | /* Flow Director register values */ | |
| 2544 | #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 | |
| 2545 | #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 | |
| 2546 | #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 | |
| 2547 | #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 | |
| 2548 | #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 | |
| 2549 | #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 | |
| 2550 | #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 | |
| 2551 | #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 | |
| 2552 | #define IXGBE_FDIRCTRL_FLEX_SHIFT 16 | |
| 207969b9 MR |
2553 | #define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000 |
| 2554 | #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21 | |
| 2555 | #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */ | |
| 2556 | #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */ | |
| bfde493e PWJ |
2557 | #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 |
| 2558 | #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 | |
| 2559 | #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 | |
| 2560 | #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 | |
| 2561 | ||
| 2562 | #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 | |
| 2563 | #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 | |
| 2564 | #define IXGBE_FDIRIP6M_DIPM_SHIFT 16 | |
| 2565 | #define IXGBE_FDIRM_VLANID 0x00000001 | |
| 2566 | #define IXGBE_FDIRM_VLANP 0x00000002 | |
| 2567 | #define IXGBE_FDIRM_POOL 0x00000004 | |
| 45b9f509 AD |
2568 | #define IXGBE_FDIRM_L4P 0x00000008 |
| 2569 | #define IXGBE_FDIRM_FLEX 0x00000010 | |
| 2570 | #define IXGBE_FDIRM_DIPv6 0x00000020 | |
| bfde493e PWJ |
2571 | |
| 2572 | #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF | |
| 2573 | #define IXGBE_FDIRFREE_FREE_SHIFT 0 | |
| 2574 | #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 | |
| 2575 | #define IXGBE_FDIRFREE_COLL_SHIFT 16 | |
| 2576 | #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F | |
| 2577 | #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 | |
| 2578 | #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 | |
| 2579 | #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 | |
| 2580 | #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF | |
| 2581 | #define IXGBE_FDIRUSTAT_ADD_SHIFT 0 | |
| 2582 | #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 | |
| 2583 | #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 | |
| 2584 | #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF | |
| 2585 | #define IXGBE_FDIRFSTAT_FADD_SHIFT 0 | |
| 2586 | #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 | |
| 2587 | #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 | |
| 2588 | #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 | |
| 2589 | #define IXGBE_FDIRVLAN_FLEX_SHIFT 16 | |
| 2590 | #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 | |
| 2591 | #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 | |
| 2592 | ||
| 2593 | #define IXGBE_FDIRCMD_CMD_MASK 0x00000003 | |
| 2594 | #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 | |
| 2595 | #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 | |
| 2596 | #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 | |
| c04f6ca8 | 2597 | #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 |
| bfde493e PWJ |
2598 | #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 |
| 2599 | #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 | |
| 2600 | #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 | |
| 2601 | #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 | |
| 2602 | #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 | |
| 2603 | #define IXGBE_FDIRCMD_IPV6 0x00000080 | |
| 2604 | #define IXGBE_FDIRCMD_CLEARHT 0x00000100 | |
| 2605 | #define IXGBE_FDIRCMD_DROP 0x00000200 | |
| 2606 | #define IXGBE_FDIRCMD_INT 0x00000400 | |
| 2607 | #define IXGBE_FDIRCMD_LAST 0x00000800 | |
| 2608 | #define IXGBE_FDIRCMD_COLLISION 0x00001000 | |
| 2609 | #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 | |
| 905e4a41 | 2610 | #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 |
| bfde493e | 2611 | #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 |
| 67359c3c | 2612 | #define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT 23 |
| bfde493e PWJ |
2613 | #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 |
| 2614 | #define IXGBE_FDIR_INIT_DONE_POLL 10 | |
| 2615 | #define IXGBE_FDIRCMD_CMD_POLL 10 | |
| 67359c3c | 2616 | #define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000 |
| bfde493e | 2617 | |
| c04f6ca8 AD |
2618 | #define IXGBE_FDIR_DROP_QUEUE 127 |
| 2619 | ||
| 9612de92 | 2620 | /* Manageablility Host Interface defines */ |
| b48e4aa3 DS |
2621 | #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ |
| 2622 | #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ | |
| 2623 | #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ | |
| 2624 | #define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */ | |
| 2625 | #define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ | |
| 2626 | #define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */ | |
| 9612de92 ET |
2627 | |
| 2628 | /* CEM Support */ | |
| 6a14ee0c DS |
2629 | #define FW_CEM_HDR_LEN 0x4 |
| 2630 | #define FW_CEM_CMD_DRIVER_INFO 0xDD | |
| 2631 | #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 | |
| 2632 | #define FW_CEM_CMD_RESERVED 0x0 | |
| 2633 | #define FW_CEM_UNUSED_VER 0x0 | |
| 2634 | #define FW_CEM_MAX_RETRIES 3 | |
| 2635 | #define FW_CEM_RESP_STATUS_SUCCESS 0x1 | |
| 2636 | #define FW_READ_SHADOW_RAM_CMD 0x31 | |
| 2637 | #define FW_READ_SHADOW_RAM_LEN 0x6 | |
| 2638 | #define FW_WRITE_SHADOW_RAM_CMD 0x33 | |
| 2639 | #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ | |
| 2640 | #define FW_SHADOW_RAM_DUMP_CMD 0x36 | |
| 2641 | #define FW_SHADOW_RAM_DUMP_LEN 0 | |
| 2642 | #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ | |
| 2643 | #define FW_NVM_DATA_OFFSET 3 | |
| 2644 | #define FW_MAX_READ_BUFFER_SIZE 1024 | |
| 2645 | #define FW_DISABLE_RXEN_CMD 0xDE | |
| 2646 | #define FW_DISABLE_RXEN_LEN 0x1 | |
| 49425dfc MR |
2647 | #define FW_PHY_MGMT_REQ_CMD 0x20 |
| 2648 | #define FW_PHY_TOKEN_REQ_CMD 0x0A | |
| 2649 | #define FW_PHY_TOKEN_REQ_LEN 2 | |
| 2650 | #define FW_PHY_TOKEN_REQ 0 | |
| 2651 | #define FW_PHY_TOKEN_REL 1 | |
| 2652 | #define FW_PHY_TOKEN_OK 1 | |
| 2653 | #define FW_PHY_TOKEN_RETRY 0x80 | |
| 2654 | #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ | |
| 2655 | #define FW_PHY_TOKEN_WAIT 5 /* seconds */ | |
| 2656 | #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) | |
| 2657 | #define FW_INT_PHY_REQ_CMD 0xB | |
| 2658 | #define FW_INT_PHY_REQ_LEN 10 | |
| 2659 | #define FW_INT_PHY_REQ_READ 0 | |
| 2660 | #define FW_INT_PHY_REQ_WRITE 1 | |
| 9612de92 ET |
2661 | |
| 2662 | /* Host Interface Command Structures */ | |
| 2663 | struct ixgbe_hic_hdr { | |
| 2664 | u8 cmd; | |
| 2665 | u8 buf_len; | |
| 2666 | union { | |
| 2667 | u8 cmd_resv; | |
| 2668 | u8 ret_status; | |
| 2669 | } cmd_or_resp; | |
| 2670 | u8 checksum; | |
| 2671 | }; | |
| 2672 | ||
| 6a14ee0c DS |
2673 | struct ixgbe_hic_hdr2_req { |
| 2674 | u8 cmd; | |
| 2675 | u8 buf_lenh; | |
| 2676 | u8 buf_lenl; | |
| 2677 | u8 checksum; | |
| 2678 | }; | |
| 2679 | ||
| 2680 | struct ixgbe_hic_hdr2_rsp { | |
| 2681 | u8 cmd; | |
| 2682 | u8 buf_lenl; | |
| 2683 | u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ | |
| 2684 | u8 checksum; | |
| 2685 | }; | |
| 2686 | ||
| 2687 | union ixgbe_hic_hdr2 { | |
| 2688 | struct ixgbe_hic_hdr2_req req; | |
| 2689 | struct ixgbe_hic_hdr2_rsp rsp; | |
| 2690 | }; | |
| 2691 | ||
| 9612de92 ET |
2692 | struct ixgbe_hic_drv_info { |
| 2693 | struct ixgbe_hic_hdr hdr; | |
| 2694 | u8 port_num; | |
| 2695 | u8 ver_sub; | |
| 2696 | u8 ver_build; | |
| 2697 | u8 ver_min; | |
| 2698 | u8 ver_maj; | |
| 2699 | u8 pad; /* end spacing to ensure length is mult. of dword */ | |
| 2700 | u16 pad2; /* end spacing to ensure length is mult. of dword2 */ | |
| 2701 | }; | |
| 2702 | ||
| 6a14ee0c DS |
2703 | /* These need to be dword aligned */ |
| 2704 | struct ixgbe_hic_read_shadow_ram { | |
| 2705 | union ixgbe_hic_hdr2 hdr; | |
| 2706 | u32 address; | |
| 2707 | u16 length; | |
| 2708 | u16 pad2; | |
| 2709 | u16 data; | |
| 2710 | u16 pad3; | |
| 2711 | }; | |
| 2712 | ||
| 2713 | struct ixgbe_hic_write_shadow_ram { | |
| 2714 | union ixgbe_hic_hdr2 hdr; | |
| ef5398bb DS |
2715 | __be32 address; |
| 2716 | __be16 length; | |
| 6a14ee0c DS |
2717 | u16 pad2; |
| 2718 | u16 data; | |
| 2719 | u16 pad3; | |
| 2720 | }; | |
| 2721 | ||
| 2722 | struct ixgbe_hic_disable_rxen { | |
| 2723 | struct ixgbe_hic_hdr hdr; | |
| 2724 | u8 port_number; | |
| 2725 | u8 pad2; | |
| 2726 | u16 pad3; | |
| 2727 | }; | |
| 2728 | ||
| 49425dfc MR |
2729 | struct ixgbe_hic_phy_token_req { |
| 2730 | struct ixgbe_hic_hdr hdr; | |
| 2731 | u8 port_number; | |
| 2732 | u8 command_type; | |
| 2733 | u16 pad; | |
| 2734 | }; | |
| 2735 | ||
| 2736 | struct ixgbe_hic_internal_phy_req { | |
| 2737 | struct ixgbe_hic_hdr hdr; | |
| 2738 | u8 port_number; | |
| 2739 | u8 command_type; | |
| 2740 | __be16 address; | |
| 2741 | u16 rsv1; | |
| 2742 | __be32 write_data; | |
| 2743 | u16 pad; | |
| 2744 | } __packed; | |
| 2745 | ||
| 2746 | struct ixgbe_hic_internal_phy_resp { | |
| 2747 | struct ixgbe_hic_hdr hdr; | |
| 2748 | __be32 read_data; | |
| 2749 | }; | |
| 2750 | ||
| 9a799d71 AK |
2751 | /* Transmit Descriptor - Advanced */ |
| 2752 | union ixgbe_adv_tx_desc { | |
| 2753 | struct { | |
| c44ade9e | 2754 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
| 8327d000 AV |
2755 | __le32 cmd_type_len; |
| 2756 | __le32 olinfo_status; | |
| 9a799d71 AK |
2757 | } read; |
| 2758 | struct { | |
| 8327d000 AV |
2759 | __le64 rsvd; /* Reserved */ |
| 2760 | __le32 nxtseq_seed; | |
| 2761 | __le32 status; | |
| 9a799d71 AK |
2762 | } wb; |
| 2763 | }; | |
| 2764 | ||
| 9a799d71 AK |
2765 | /* Receive Descriptor - Advanced */ |
| 2766 | union ixgbe_adv_rx_desc { | |
| 2767 | struct { | |
| 8327d000 AV |
2768 | __le64 pkt_addr; /* Packet buffer address */ |
| 2769 | __le64 hdr_addr; /* Header buffer address */ | |
| 9a799d71 AK |
2770 | } read; |
| 2771 | struct { | |
| 2772 | struct { | |
| 7c6e0a43 JB |
2773 | union { |
| 2774 | __le32 data; | |
| 2775 | struct { | |
| c44ade9e JB |
2776 | __le16 pkt_info; /* RSS, Pkt type */ |
| 2777 | __le16 hdr_info; /* Splithdr, hdrlen */ | |
| 7c6e0a43 | 2778 | } hs_rss; |
| 9a799d71 AK |
2779 | } lo_dword; |
| 2780 | union { | |
| 8327d000 | 2781 | __le32 rss; /* RSS Hash */ |
| 9a799d71 | 2782 | struct { |
| 8327d000 | 2783 | __le16 ip_id; /* IP id */ |
| 9da09bb1 | 2784 | __le16 csum; /* Packet Checksum */ |
| 9a799d71 AK |
2785 | } csum_ip; |
| 2786 | } hi_dword; | |
| 2787 | } lower; | |
| 2788 | struct { | |
| 8327d000 AV |
2789 | __le32 status_error; /* ext status/error */ |
| 2790 | __le16 length; /* Packet length */ | |
| 2791 | __le16 vlan; /* VLAN tag */ | |
| 9a799d71 AK |
2792 | } upper; |
| 2793 | } wb; /* writeback */ | |
| 2794 | }; | |
| 2795 | ||
| 2796 | /* Context descriptors */ | |
| 2797 | struct ixgbe_adv_tx_context_desc { | |
| 8327d000 AV |
2798 | __le32 vlan_macip_lens; |
| 2799 | __le32 seqnum_seed; | |
| 2800 | __le32 type_tucmd_mlhl; | |
| 2801 | __le32 mss_l4len_idx; | |
| 9a799d71 AK |
2802 | }; |
| 2803 | ||
| 2804 | /* Adv Transmit Descriptor Config Masks */ | |
| c44ade9e | 2805 | #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ |
| 11afc1b1 | 2806 | #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ |
| 3a6a4eda | 2807 | #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE 1588 Time Stamp */ |
| 11afc1b1 PW |
2808 | #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ |
| 2809 | #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ | |
| 9a799d71 AK |
2810 | #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ |
| 2811 | #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ | |
| 2812 | #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ | |
| 2813 | #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ | |
| 2814 | #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ | |
| 9a799d71 | 2815 | #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ |
| c44ade9e | 2816 | #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ |
| 9a799d71 AK |
2817 | #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ |
| 2818 | #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ | |
| 2819 | #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ | |
| 2820 | #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ | |
| c44ade9e | 2821 | #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ |
| 9a799d71 AK |
2822 | #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ |
| 2823 | #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ | |
| c44ade9e | 2824 | #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ |
| 9a799d71 AK |
2825 | #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ |
| 2826 | #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ | |
| e7cf745b | 2827 | IXGBE_ADVTXD_POPTS_SHIFT) |
| 9a799d71 | 2828 | #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ |
| e7cf745b | 2829 | IXGBE_ADVTXD_POPTS_SHIFT) |
| c44ade9e JB |
2830 | #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ |
| 2831 | #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ | |
| 2832 | #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ | |
| 2833 | #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */ | |
| 2834 | #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ | |
| 2835 | #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | |
| 2836 | #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ | |
| 2837 | #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ | |
| 2838 | #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ | |
| 2839 | #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ | |
| 2840 | #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ | |
| 2841 | #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ | |
| 2842 | #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ | |
| 8b75451b | 2843 | #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */ |
| c44ade9e | 2844 | #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ |
| 11afc1b1 PW |
2845 | #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ |
| 2846 | #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ | |
| 2847 | #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ | |
| bff66176 | 2848 | #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ |
| b4f47a48 JK |
2849 | #define IXGBE_ADVTXD_FCOEF_SOF (BIT(2) << 10) /* FC SOF index */ |
| 2850 | #define IXGBE_ADVTXD_FCOEF_PARINC (BIT(3) << 10) /* Rel_Off in F_CTL */ | |
| 2851 | #define IXGBE_ADVTXD_FCOEF_ORIE (BIT(4) << 10) /* Orientation: End */ | |
| 2852 | #define IXGBE_ADVTXD_FCOEF_ORIS (BIT(5) << 10) /* Orientation: Start */ | |
| 2853 | #define IXGBE_ADVTXD_FCOEF_EOF_N (0u << 10) /* 00: EOFn */ | |
| 2854 | #define IXGBE_ADVTXD_FCOEF_EOF_T (1u << 10) /* 01: EOFt */ | |
| 2855 | #define IXGBE_ADVTXD_FCOEF_EOF_NI (2u << 10) /* 10: EOFni */ | |
| 2856 | #define IXGBE_ADVTXD_FCOEF_EOF_A (3u << 10) /* 11: EOFa */ | |
| 2857 | #define IXGBE_ADVTXD_FCOEF_EOF_MASK (3u << 10) /* FC EOF index */ | |
| c44ade9e JB |
2858 | #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ |
| 2859 | #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ | |
| 2860 | ||
| 2861 | /* Autonegotiation advertised speeds */ | |
| 2862 | typedef u32 ixgbe_autoneg_advertised; | |
| 9a799d71 | 2863 | /* Link speed */ |
| c44ade9e | 2864 | typedef u32 ixgbe_link_speed; |
| 9a75a1ac DS |
2865 | #define IXGBE_LINK_SPEED_UNKNOWN 0 |
| 2866 | #define IXGBE_LINK_SPEED_100_FULL 0x0008 | |
| 2867 | #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 | |
| 2868 | #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 | |
| 2869 | #define IXGBE_LINK_SPEED_5GB_FULL 0x0800 | |
| 2870 | #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 | |
| c44ade9e | 2871 | #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ |
| e7cf745b | 2872 | IXGBE_LINK_SPEED_10GB_FULL) |
| 11afc1b1 | 2873 | #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ |
| e7cf745b JK |
2874 | IXGBE_LINK_SPEED_1GB_FULL | \ |
| 2875 | IXGBE_LINK_SPEED_10GB_FULL) | |
| 11afc1b1 | 2876 | |
| 9da712d2 JF |
2877 | /* Flow Control Data Sheet defined values |
| 2878 | * Calculation and defines taken from 802.1bb Annex O | |
| 2879 | */ | |
| 2880 | ||
| 2881 | /* BitTimes (BT) conversion */ | |
| 4f8a91ad | 2882 | #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) |
| 9da712d2 JF |
2883 | #define IXGBE_B2BT(BT) (BT * 8) |
| 2884 | ||
| 2885 | /* Calculate Delay to respond to PFC */ | |
| 2886 | #define IXGBE_PFC_D 672 | |
| 2887 | ||
| 2888 | /* Calculate Cable Delay */ | |
| 2889 | #define IXGBE_CABLE_DC 5556 /* Delay Copper */ | |
| 2890 | #define IXGBE_CABLE_DO 5000 /* Delay Optical */ | |
| 2891 | ||
| 2892 | /* Calculate Interface Delay X540 */ | |
| 2893 | #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ | |
| 2894 | #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ | |
| 2895 | #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ | |
| 2896 | ||
| 2897 | #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) | |
| 2898 | ||
| 2899 | /* Calculate Interface Delay 82598, 82599 */ | |
| 2900 | #define IXGBE_PHY_D 12800 | |
| 2901 | #define IXGBE_MAC_D 4096 | |
| 2902 | #define IXGBE_XAUI_D (2 * 1024) | |
| 2903 | ||
| 2904 | #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) | |
| 2905 | ||
| 2906 | /* Calculate Delay incurred from higher layer */ | |
| 2907 | #define IXGBE_HD 6144 | |
| 2908 | ||
| 2909 | /* Calculate PCI Bus delay for low thresholds */ | |
| 2910 | #define IXGBE_PCI_DELAY 10000 | |
| 2911 | ||
| 2912 | /* Calculate X540 delay value in bit times */ | |
| 4f8a91ad JF |
2913 | #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ |
| 2914 | ((36 * \ | |
| 2915 | (IXGBE_B2BT(_max_frame_link) + \ | |
| 2916 | IXGBE_PFC_D + \ | |
| 2917 | (2 * IXGBE_CABLE_DC) + \ | |
| 2918 | (2 * IXGBE_ID_X540) + \ | |
| 2919 | IXGBE_HD) / 25 + 1) + \ | |
| 2920 | 2 * IXGBE_B2BT(_max_frame_tc)) | |
| 9da712d2 JF |
2921 | |
| 2922 | /* Calculate 82599, 82598 delay value in bit times */ | |
| 4f8a91ad JF |
2923 | #define IXGBE_DV(_max_frame_link, _max_frame_tc) \ |
| 2924 | ((36 * \ | |
| 2925 | (IXGBE_B2BT(_max_frame_link) + \ | |
| 2926 | IXGBE_PFC_D + \ | |
| 2927 | (2 * IXGBE_CABLE_DC) + \ | |
| 2928 | (2 * IXGBE_ID) + \ | |
| 2929 | IXGBE_HD) / 25 + 1) + \ | |
| 2930 | 2 * IXGBE_B2BT(_max_frame_tc)) | |
| 16b61beb | 2931 | |
| 9da712d2 | 2932 | /* Calculate low threshold delay values */ |
| 4f8a91ad JF |
2933 | #define IXGBE_LOW_DV_X540(_max_frame_tc) \ |
| 2934 | (2 * IXGBE_B2BT(_max_frame_tc) + \ | |
| 2935 | (36 * IXGBE_PCI_DELAY / 25) + 1) | |
| 2936 | #define IXGBE_LOW_DV(_max_frame_tc) \ | |
| 2937 | (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) | |
| 16b61beb | 2938 | |
| bfde493e | 2939 | /* Software ATR hash keys */ |
| 905e4a41 AD |
2940 | #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 |
| 2941 | #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 | |
| bfde493e | 2942 | |
| 905e4a41 | 2943 | /* Software ATR input stream values and masks */ |
| 67359c3c MR |
2944 | #define IXGBE_ATR_HASH_MASK 0x7fff |
| 2945 | #define IXGBE_ATR_L4TYPE_MASK 0x3 | |
| 2946 | #define IXGBE_ATR_L4TYPE_UDP 0x1 | |
| 2947 | #define IXGBE_ATR_L4TYPE_TCP 0x2 | |
| 2948 | #define IXGBE_ATR_L4TYPE_SCTP 0x3 | |
| 2949 | #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 | |
| 2950 | #define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 | |
| 905e4a41 AD |
2951 | enum ixgbe_atr_flow_type { |
| 2952 | IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, | |
| 2953 | IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, | |
| 2954 | IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, | |
| 2955 | IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, | |
| 2956 | IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, | |
| 2957 | IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, | |
| 2958 | IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, | |
| 2959 | IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, | |
| 2960 | }; | |
| bfde493e PWJ |
2961 | |
| 2962 | /* Flow Director ATR input struct. */ | |
| 905e4a41 AD |
2963 | union ixgbe_atr_input { |
| 2964 | /* | |
| 2965 | * Byte layout in order, all values with MSB first: | |
| bfde493e | 2966 | * |
| 905e4a41 AD |
2967 | * vm_pool - 1 byte |
| 2968 | * flow_type - 1 byte | |
| bfde493e PWJ |
2969 | * vlan_id - 2 bytes |
| 2970 | * src_ip - 16 bytes | |
| 2971 | * dst_ip - 16 bytes | |
| 2972 | * src_port - 2 bytes | |
| 2973 | * dst_port - 2 bytes | |
| 2974 | * flex_bytes - 2 bytes | |
| c04f6ca8 | 2975 | * bkt_hash - 2 bytes |
| bfde493e | 2976 | */ |
| 905e4a41 AD |
2977 | struct { |
| 2978 | u8 vm_pool; | |
| 2979 | u8 flow_type; | |
| 2980 | __be16 vlan_id; | |
| 2981 | __be32 dst_ip[4]; | |
| 2982 | __be32 src_ip[4]; | |
| 2983 | __be16 src_port; | |
| 2984 | __be16 dst_port; | |
| 2985 | __be16 flex_bytes; | |
| c04f6ca8 | 2986 | __be16 bkt_hash; |
| 905e4a41 AD |
2987 | } formatted; |
| 2988 | __be32 dword_stream[11]; | |
| bfde493e PWJ |
2989 | }; |
| 2990 | ||
| 69830529 AD |
2991 | /* Flow Director compressed ATR hash input struct */ |
| 2992 | union ixgbe_atr_hash_dword { | |
| 2993 | struct { | |
| 2994 | u8 vm_pool; | |
| 2995 | u8 flow_type; | |
| 2996 | __be16 vlan_id; | |
| 2997 | } formatted; | |
| 2998 | __be32 ip; | |
| 2999 | struct { | |
| 3000 | __be16 src; | |
| 3001 | __be16 dst; | |
| 3002 | } port; | |
| 3003 | __be16 flex_bytes; | |
| 3004 | __be32 dword; | |
| 3005 | }; | |
| 3006 | ||
| 9a900eca DS |
3007 | #define IXGBE_MVALS_INIT(m) \ |
| 3008 | IXGBE_CAT(EEC, m), \ | |
| 3009 | IXGBE_CAT(FLA, m), \ | |
| 3010 | IXGBE_CAT(GRC, m), \ | |
| 9a900eca DS |
3011 | IXGBE_CAT(FACTPS, m), \ |
| 3012 | IXGBE_CAT(SWSM, m), \ | |
| 3013 | IXGBE_CAT(SWFW_SYNC, m), \ | |
| 3014 | IXGBE_CAT(FWSM, m), \ | |
| 3015 | IXGBE_CAT(SDP0_GPIEN, m), \ | |
| 3016 | IXGBE_CAT(SDP1_GPIEN, m), \ | |
| 3017 | IXGBE_CAT(SDP2_GPIEN, m), \ | |
| 3018 | IXGBE_CAT(EICR_GPI_SDP0, m), \ | |
| 3019 | IXGBE_CAT(EICR_GPI_SDP1, m), \ | |
| 3020 | IXGBE_CAT(EICR_GPI_SDP2, m), \ | |
| 3021 | IXGBE_CAT(CIAA, m), \ | |
| 3022 | IXGBE_CAT(CIAD, m), \ | |
| 3023 | IXGBE_CAT(I2C_CLK_IN, m), \ | |
| 3024 | IXGBE_CAT(I2C_CLK_OUT, m), \ | |
| 3025 | IXGBE_CAT(I2C_DATA_IN, m), \ | |
| 3026 | IXGBE_CAT(I2C_DATA_OUT, m), \ | |
| 3027 | IXGBE_CAT(I2C_DATA_OE_N_EN, m), \ | |
| 3028 | IXGBE_CAT(I2C_BB_EN, m), \ | |
| 3029 | IXGBE_CAT(I2C_CLK_OE_N_EN, m), \ | |
| 3030 | IXGBE_CAT(I2CCTL, m) | |
| 3031 | ||
| 3032 | enum ixgbe_mvals { | |
| 3033 | IXGBE_MVALS_INIT(IDX), | |
| 3034 | IXGBE_MVALS_IDX_LIMIT | |
| 3035 | }; | |
| 3036 | ||
| 9a799d71 AK |
3037 | enum ixgbe_eeprom_type { |
| 3038 | ixgbe_eeprom_uninitialized = 0, | |
| 3039 | ixgbe_eeprom_spi, | |
| fe15e8e1 | 3040 | ixgbe_flash, |
| 9a799d71 AK |
3041 | ixgbe_eeprom_none /* No NVM support */ |
| 3042 | }; | |
| 3043 | ||
| 3044 | enum ixgbe_mac_type { | |
| 3045 | ixgbe_mac_unknown = 0, | |
| 3046 | ixgbe_mac_82598EB, | |
| 11afc1b1 | 3047 | ixgbe_mac_82599EB, |
| fe15e8e1 | 3048 | ixgbe_mac_X540, |
| 9a75a1ac DS |
3049 | ixgbe_mac_X550, |
| 3050 | ixgbe_mac_X550EM_x, | |
| 207969b9 | 3051 | ixgbe_mac_x550em_a, |
| 9a799d71 AK |
3052 | ixgbe_num_macs |
| 3053 | }; | |
| 3054 | ||
| 3055 | enum ixgbe_phy_type { | |
| 3056 | ixgbe_phy_unknown = 0, | |
| 21cc5b4f | 3057 | ixgbe_phy_none, |
| 0befdb3e | 3058 | ixgbe_phy_tn, |
| fe15e8e1 | 3059 | ixgbe_phy_aq, |
| 6a14ee0c DS |
3060 | ixgbe_phy_x550em_kr, |
| 3061 | ixgbe_phy_x550em_kx4, | |
| 3062 | ixgbe_phy_x550em_ext_t, | |
| 11afc1b1 | 3063 | ixgbe_phy_cu_unknown, |
| 9a799d71 | 3064 | ixgbe_phy_qt, |
| c44ade9e | 3065 | ixgbe_phy_xaui, |
| c4900be0 | 3066 | ixgbe_phy_nl, |
| ea0a04df DS |
3067 | ixgbe_phy_sfp_passive_tyco, |
| 3068 | ixgbe_phy_sfp_passive_unknown, | |
| 3069 | ixgbe_phy_sfp_active_unknown, | |
| c44ade9e JB |
3070 | ixgbe_phy_sfp_avago, |
| 3071 | ixgbe_phy_sfp_ftl, | |
| ea0a04df | 3072 | ixgbe_phy_sfp_ftl_active, |
| c44ade9e | 3073 | ixgbe_phy_sfp_unknown, |
| 11afc1b1 | 3074 | ixgbe_phy_sfp_intel, |
| 8f58332b DS |
3075 | ixgbe_phy_qsfp_passive_unknown, |
| 3076 | ixgbe_phy_qsfp_active_unknown, | |
| 3077 | ixgbe_phy_qsfp_intel, | |
| 3078 | ixgbe_phy_qsfp_unknown, | |
| fa466e91 | 3079 | ixgbe_phy_sfp_unsupported, |
| 200157c2 | 3080 | ixgbe_phy_sgmii, |
| c44ade9e JB |
3081 | ixgbe_phy_generic |
| 3082 | }; | |
| 3083 | ||
| 3084 | /* | |
| 3085 | * SFP+ module type IDs: | |
| 3086 | * | |
| 11afc1b1 | 3087 | * ID Module Type |
| c44ade9e | 3088 | * ============= |
| 11afc1b1 PW |
3089 | * 0 SFP_DA_CU |
| 3090 | * 1 SFP_SR | |
| 3091 | * 2 SFP_LR | |
| 3092 | * 3 SFP_DA_CU_CORE0 - 82599-specific | |
| 3093 | * 4 SFP_DA_CU_CORE1 - 82599-specific | |
| 3094 | * 5 SFP_SR/LR_CORE0 - 82599-specific | |
| 3095 | * 6 SFP_SR/LR_CORE1 - 82599-specific | |
| c44ade9e JB |
3096 | */ |
| 3097 | enum ixgbe_sfp_type { | |
| 3098 | ixgbe_sfp_type_da_cu = 0, | |
| 3099 | ixgbe_sfp_type_sr = 1, | |
| 3100 | ixgbe_sfp_type_lr = 2, | |
| 11afc1b1 PW |
3101 | ixgbe_sfp_type_da_cu_core0 = 3, |
| 3102 | ixgbe_sfp_type_da_cu_core1 = 4, | |
| 3103 | ixgbe_sfp_type_srlr_core0 = 5, | |
| 3104 | ixgbe_sfp_type_srlr_core1 = 6, | |
| ea0a04df DS |
3105 | ixgbe_sfp_type_da_act_lmt_core0 = 7, |
| 3106 | ixgbe_sfp_type_da_act_lmt_core1 = 8, | |
| cb836a97 DS |
3107 | ixgbe_sfp_type_1g_cu_core0 = 9, |
| 3108 | ixgbe_sfp_type_1g_cu_core1 = 10, | |
| a49fda3e JK |
3109 | ixgbe_sfp_type_1g_sx_core0 = 11, |
| 3110 | ixgbe_sfp_type_1g_sx_core1 = 12, | |
| 345be204 DS |
3111 | ixgbe_sfp_type_1g_lx_core0 = 13, |
| 3112 | ixgbe_sfp_type_1g_lx_core1 = 14, | |
| c4900be0 | 3113 | ixgbe_sfp_type_not_present = 0xFFFE, |
| c44ade9e | 3114 | ixgbe_sfp_type_unknown = 0xFFFF |
| 9a799d71 AK |
3115 | }; |
| 3116 | ||
| 3117 | enum ixgbe_media_type { | |
| 3118 | ixgbe_media_type_unknown = 0, | |
| 3119 | ixgbe_media_type_fiber, | |
| 8f58332b | 3120 | ixgbe_media_type_fiber_qsfp, |
| 4f6290cf | 3121 | ixgbe_media_type_fiber_lco, |
| 9a799d71 | 3122 | ixgbe_media_type_copper, |
| c44ade9e | 3123 | ixgbe_media_type_backplane, |
| 6b1be199 | 3124 | ixgbe_media_type_cx4, |
| c44ade9e | 3125 | ixgbe_media_type_virtual |
| 9a799d71 AK |
3126 | }; |
| 3127 | ||
| 3128 | /* Flow Control Settings */ | |
| 0ecc061d | 3129 | enum ixgbe_fc_mode { |
| 9a799d71 AK |
3130 | ixgbe_fc_none = 0, |
| 3131 | ixgbe_fc_rx_pause, | |
| 3132 | ixgbe_fc_tx_pause, | |
| 3133 | ixgbe_fc_full, | |
| 3134 | ixgbe_fc_default | |
| 3135 | }; | |
| 3136 | ||
| cd7e1f0b DS |
3137 | /* Smart Speed Settings */ |
| 3138 | #define IXGBE_SMARTSPEED_MAX_RETRIES 3 | |
| 3139 | enum ixgbe_smart_speed { | |
| 3140 | ixgbe_smart_speed_auto = 0, | |
| 3141 | ixgbe_smart_speed_on, | |
| 3142 | ixgbe_smart_speed_off | |
| 3143 | }; | |
| 3144 | ||
| 11afc1b1 PW |
3145 | /* PCI bus types */ |
| 3146 | enum ixgbe_bus_type { | |
| 3147 | ixgbe_bus_type_unknown = 0, | |
| 11afc1b1 | 3148 | ixgbe_bus_type_pci_express, |
| f9328bc6 | 3149 | ixgbe_bus_type_internal, |
| 11afc1b1 PW |
3150 | ixgbe_bus_type_reserved |
| 3151 | }; | |
| 3152 | ||
| 3153 | /* PCI bus speeds */ | |
| 3154 | enum ixgbe_bus_speed { | |
| 3155 | ixgbe_bus_speed_unknown = 0, | |
| 26d6899b ET |
3156 | ixgbe_bus_speed_33 = 33, |
| 3157 | ixgbe_bus_speed_66 = 66, | |
| 3158 | ixgbe_bus_speed_100 = 100, | |
| 3159 | ixgbe_bus_speed_120 = 120, | |
| 3160 | ixgbe_bus_speed_133 = 133, | |
| 3161 | ixgbe_bus_speed_2500 = 2500, | |
| 3162 | ixgbe_bus_speed_5000 = 5000, | |
| e8710a5f | 3163 | ixgbe_bus_speed_8000 = 8000, |
| 11afc1b1 PW |
3164 | ixgbe_bus_speed_reserved |
| 3165 | }; | |
| 3166 | ||
| 3167 | /* PCI bus widths */ | |
| 3168 | enum ixgbe_bus_width { | |
| 3169 | ixgbe_bus_width_unknown = 0, | |
| 26d6899b ET |
3170 | ixgbe_bus_width_pcie_x1 = 1, |
| 3171 | ixgbe_bus_width_pcie_x2 = 2, | |
| 11afc1b1 PW |
3172 | ixgbe_bus_width_pcie_x4 = 4, |
| 3173 | ixgbe_bus_width_pcie_x8 = 8, | |
| 26d6899b ET |
3174 | ixgbe_bus_width_32 = 32, |
| 3175 | ixgbe_bus_width_64 = 64, | |
| 11afc1b1 PW |
3176 | ixgbe_bus_width_reserved |
| 3177 | }; | |
| 3178 | ||
| 9a799d71 AK |
3179 | struct ixgbe_addr_filter_info { |
| 3180 | u32 num_mc_addrs; | |
| 3181 | u32 rar_used_count; | |
| 9a799d71 | 3182 | u32 mta_in_use; |
| 2c5645cf | 3183 | u32 overflow_promisc; |
| e433ea1f | 3184 | bool uc_set_promisc; |
| 2c5645cf | 3185 | bool user_set_promisc; |
| 9a799d71 AK |
3186 | }; |
| 3187 | ||
| 11afc1b1 PW |
3188 | /* Bus parameters */ |
| 3189 | struct ixgbe_bus_info { | |
| 3190 | enum ixgbe_bus_speed speed; | |
| 3191 | enum ixgbe_bus_width width; | |
| 3192 | enum ixgbe_bus_type type; | |
| 3193 | ||
| 3775b814 MR |
3194 | u8 func; |
| 3195 | u8 lan_id; | |
| c898fe28 | 3196 | u8 instance_id; |
| 11afc1b1 PW |
3197 | }; |
| 3198 | ||
| 9a799d71 AK |
3199 | /* Flow control parameters */ |
| 3200 | struct ixgbe_fc_info { | |
| 9da712d2 | 3201 | u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */ |
| e5776620 | 3202 | u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */ |
| 9a799d71 AK |
3203 | u16 pause_time; /* Flow Control Pause timer */ |
| 3204 | bool send_xon; /* Flow control send XON */ | |
| 3205 | bool strict_ieee; /* Strict IEEE mode */ | |
| 620fa036 MC |
3206 | bool disable_fc_autoneg; /* Do not autonegotiate FC */ |
| 3207 | bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ | |
| 0ecc061d PWJ |
3208 | enum ixgbe_fc_mode current_mode; /* FC mode in effect */ |
| 3209 | enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ | |
| 9a799d71 AK |
3210 | }; |
| 3211 | ||
| 3212 | /* Statistics counters collected by the MAC */ | |
| 3213 | struct ixgbe_hw_stats { | |
| 3214 | u64 crcerrs; | |
| 3215 | u64 illerrc; | |
| 3216 | u64 errbc; | |
| 3217 | u64 mspdc; | |
| 3218 | u64 mpctotal; | |
| 3219 | u64 mpc[8]; | |
| 3220 | u64 mlfc; | |
| 3221 | u64 mrfc; | |
| 3222 | u64 rlec; | |
| 3223 | u64 lxontxc; | |
| 3224 | u64 lxonrxc; | |
| 3225 | u64 lxofftxc; | |
| 3226 | u64 lxoffrxc; | |
| 3227 | u64 pxontxc[8]; | |
| 3228 | u64 pxonrxc[8]; | |
| 3229 | u64 pxofftxc[8]; | |
| 3230 | u64 pxoffrxc[8]; | |
| 3231 | u64 prc64; | |
| 3232 | u64 prc127; | |
| 3233 | u64 prc255; | |
| 3234 | u64 prc511; | |
| 3235 | u64 prc1023; | |
| 3236 | u64 prc1522; | |
| 3237 | u64 gprc; | |
| 3238 | u64 bprc; | |
| 3239 | u64 mprc; | |
| 3240 | u64 gptc; | |
| 3241 | u64 gorc; | |
| 3242 | u64 gotc; | |
| 3243 | u64 rnbc[8]; | |
| 3244 | u64 ruc; | |
| 3245 | u64 rfc; | |
| 3246 | u64 roc; | |
| 3247 | u64 rjc; | |
| 3248 | u64 mngprc; | |
| 3249 | u64 mngpdc; | |
| 3250 | u64 mngptc; | |
| 3251 | u64 tor; | |
| 3252 | u64 tpr; | |
| 3253 | u64 tpt; | |
| 3254 | u64 ptc64; | |
| 3255 | u64 ptc127; | |
| 3256 | u64 ptc255; | |
| 3257 | u64 ptc511; | |
| 3258 | u64 ptc1023; | |
| 3259 | u64 ptc1522; | |
| 3260 | u64 mptc; | |
| 3261 | u64 bptc; | |
| 3262 | u64 xec; | |
| 3263 | u64 rqsmr[16]; | |
| 3264 | u64 tqsmr[8]; | |
| 3265 | u64 qprc[16]; | |
| 3266 | u64 qptc[16]; | |
| 3267 | u64 qbrc[16]; | |
| 3268 | u64 qbtc[16]; | |
| 11afc1b1 PW |
3269 | u64 qprdc[16]; |
| 3270 | u64 pxon2offc[8]; | |
| 3271 | u64 fdirustat_add; | |
| 3272 | u64 fdirustat_remove; | |
| 3273 | u64 fdirfstat_fadd; | |
| 3274 | u64 fdirfstat_fremove; | |
| 3275 | u64 fdirmatch; | |
| 3276 | u64 fdirmiss; | |
| 6d45522c YZ |
3277 | u64 fccrc; |
| 3278 | u64 fcoerpdc; | |
| 3279 | u64 fcoeprc; | |
| 3280 | u64 fcoeptc; | |
| 3281 | u64 fcoedwrc; | |
| 3282 | u64 fcoedwtc; | |
| 7b859ebc AH |
3283 | u64 fcoe_noddp; |
| 3284 | u64 fcoe_noddp_ext_buff; | |
| 58f6bcf9 ET |
3285 | u64 b2ospc; |
| 3286 | u64 b2ogprc; | |
| 3287 | u64 o2bgptc; | |
| 3288 | u64 o2bspc; | |
| 9a799d71 AK |
3289 | }; |
| 3290 | ||
| 3291 | /* forward declaration */ | |
| 3292 | struct ixgbe_hw; | |
| 3293 | ||
| 2c5645cf CL |
3294 | /* iterator type for walking multicast address lists */ |
| 3295 | typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, | |
| e7cf745b | 3296 | u32 *vmdq); |
| 2c5645cf | 3297 | |
| c44ade9e JB |
3298 | /* Function pointer table */ |
| 3299 | struct ixgbe_eeprom_operations { | |
| 3300 | s32 (*init_params)(struct ixgbe_hw *); | |
| 3301 | s32 (*read)(struct ixgbe_hw *, u16, u16 *); | |
| 68c7005d | 3302 | s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); |
| c44ade9e | 3303 | s32 (*write)(struct ixgbe_hw *, u16, u16); |
| 68c7005d | 3304 | s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); |
| c44ade9e JB |
3305 | s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); |
| 3306 | s32 (*update_checksum)(struct ixgbe_hw *); | |
| 735c35af | 3307 | s32 (*calc_checksum)(struct ixgbe_hw *); |
| c44ade9e JB |
3308 | }; |
| 3309 | ||
| 9a799d71 | 3310 | struct ixgbe_mac_operations { |
| c44ade9e JB |
3311 | s32 (*init_hw)(struct ixgbe_hw *); |
| 3312 | s32 (*reset_hw)(struct ixgbe_hw *); | |
| 3313 | s32 (*start_hw)(struct ixgbe_hw *); | |
| 3314 | s32 (*clear_hw_cntrs)(struct ixgbe_hw *); | |
| 9a799d71 | 3315 | enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); |
| c44ade9e | 3316 | s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); |
| 0365e6e4 | 3317 | s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); |
| 04193058 | 3318 | s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); |
| 383ff34b | 3319 | s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); |
| c44ade9e JB |
3320 | s32 (*stop_adapter)(struct ixgbe_hw *); |
| 3321 | s32 (*get_bus_info)(struct ixgbe_hw *); | |
| 11afc1b1 | 3322 | void (*set_lan_id)(struct ixgbe_hw *); |
| c44ade9e JB |
3323 | s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); |
| 3324 | s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); | |
| 11afc1b1 | 3325 | s32 (*setup_sfp)(struct ixgbe_hw *); |
| d2f5e7f3 AS |
3326 | s32 (*disable_rx_buff)(struct ixgbe_hw *); |
| 3327 | s32 (*enable_rx_buff)(struct ixgbe_hw *); | |
| 11afc1b1 | 3328 | s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); |
| 030eaece DS |
3329 | s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); |
| 3330 | void (*release_swfw_sync)(struct ixgbe_hw *, u32); | |
| dbd15b8f | 3331 | void (*init_swfw_sync)(struct ixgbe_hw *); |
| 429d6a3b DS |
3332 | s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); |
| 3333 | s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); | |
| c44ade9e JB |
3334 | |
| 3335 | /* Link */ | |
| 61fac744 PW |
3336 | void (*disable_tx_laser)(struct ixgbe_hw *); |
| 3337 | void (*enable_tx_laser)(struct ixgbe_hw *); | |
| 1097cd17 | 3338 | void (*flap_tx_laser)(struct ixgbe_hw *); |
| f4f1040a | 3339 | void (*stop_link_on_d3)(struct ixgbe_hw *); |
| fd0326f2 | 3340 | s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); |
| 6d373a1b | 3341 | s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); |
| c44ade9e JB |
3342 | s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); |
| 3343 | s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, | |
| e7cf745b | 3344 | bool *); |
| 6d373a1b | 3345 | void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); |
| c44ade9e | 3346 | |
| 80605c65 JF |
3347 | /* Packet Buffer Manipulation */ |
| 3348 | void (*set_rxpba)(struct ixgbe_hw *, int, u32, int); | |
| 3349 | ||
| c44ade9e JB |
3350 | /* LED */ |
| 3351 | s32 (*led_on)(struct ixgbe_hw *, u32); | |
| 3352 | s32 (*led_off)(struct ixgbe_hw *, u32); | |
| 3353 | s32 (*blink_led_start)(struct ixgbe_hw *, u32); | |
| 3354 | s32 (*blink_led_stop)(struct ixgbe_hw *, u32); | |
| 3355 | ||
| 3356 | /* RAR, Multicast, VLAN */ | |
| 3357 | s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); | |
| 3358 | s32 (*clear_rar)(struct ixgbe_hw *, u32); | |
| 3359 | s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); | |
| 7fa7c9dc | 3360 | s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); |
| c44ade9e JB |
3361 | s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); |
| 3362 | s32 (*init_rx_addrs)(struct ixgbe_hw *); | |
| 2853eb89 | 3363 | s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *); |
| c44ade9e JB |
3364 | s32 (*enable_mc)(struct ixgbe_hw *); |
| 3365 | s32 (*disable_mc)(struct ixgbe_hw *); | |
| 3366 | s32 (*clear_vfta)(struct ixgbe_hw *); | |
| b6488b66 | 3367 | s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool); |
| c44ade9e | 3368 | s32 (*init_uta_tables)(struct ixgbe_hw *); |
| a985b6c3 GR |
3369 | void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); |
| 3370 | void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); | |
| c44ade9e JB |
3371 | |
| 3372 | /* Flow Control */ | |
| 041441d0 | 3373 | s32 (*fc_enable)(struct ixgbe_hw *); |
| afdc71e4 | 3374 | s32 (*setup_fc)(struct ixgbe_hw *); |
| 9612de92 ET |
3375 | |
| 3376 | /* Manageability interface */ | |
| 3377 | s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8); | |
| e1ea9158 DS |
3378 | s32 (*get_thermal_sensor_data)(struct ixgbe_hw *); |
| 3379 | s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw); | |
| 1f9ac57c DS |
3380 | void (*disable_rx)(struct ixgbe_hw *hw); |
| 3381 | void (*enable_rx)(struct ixgbe_hw *hw); | |
| 6d4c96ad DS |
3382 | void (*set_source_address_pruning)(struct ixgbe_hw *, bool, |
| 3383 | unsigned int); | |
| 5b7f000f | 3384 | void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); |
| 6a14ee0c DS |
3385 | |
| 3386 | /* DMA Coalescing */ | |
| 3387 | s32 (*dmac_config)(struct ixgbe_hw *hw); | |
| 3388 | s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); | |
| 3389 | s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); | |
| 9a5c27e6 MR |
3390 | s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *); |
| 3391 | s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32); | |
| 9a799d71 AK |
3392 | }; |
| 3393 | ||
| 3394 | struct ixgbe_phy_operations { | |
| c44ade9e JB |
3395 | s32 (*identify)(struct ixgbe_hw *); |
| 3396 | s32 (*identify_sfp)(struct ixgbe_hw *); | |
| 04f165ef | 3397 | s32 (*init)(struct ixgbe_hw *); |
| c44ade9e JB |
3398 | s32 (*reset)(struct ixgbe_hw *); |
| 3399 | s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); | |
| 3400 | s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); | |
| 3dcc2f41 ET |
3401 | s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); |
| 3402 | s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); | |
| 3957d63d | 3403 | s32 (*setup_link)(struct ixgbe_hw *); |
| 6a14ee0c | 3404 | s32 (*setup_internal_link)(struct ixgbe_hw *); |
| 99b76642 | 3405 | s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); |
| 0befdb3e JB |
3406 | s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); |
| 3407 | s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); | |
| c44ade9e JB |
3408 | s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); |
| 3409 | s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); | |
| 07ce870b | 3410 | s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); |
| c44ade9e JB |
3411 | s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); |
| 3412 | s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); | |
| 28abba05 DS |
3413 | s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); |
| 3414 | s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); | |
| 119fc60a | 3415 | s32 (*check_overtemp)(struct ixgbe_hw *); |
| 961fac88 | 3416 | s32 (*set_phy_power)(struct ixgbe_hw *, bool on); |
| 6ac74394 | 3417 | s32 (*enter_lplu)(struct ixgbe_hw *); |
| c3dc4c09 | 3418 | s32 (*handle_lasi)(struct ixgbe_hw *hw); |
| bb5ce9a5 MR |
3419 | s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, |
| 3420 | u16 *value); | |
| 3421 | s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, | |
| 3422 | u16 value); | |
| 9a799d71 AK |
3423 | }; |
| 3424 | ||
| 9a799d71 | 3425 | struct ixgbe_eeprom_info { |
| c44ade9e JB |
3426 | struct ixgbe_eeprom_operations ops; |
| 3427 | enum ixgbe_eeprom_type type; | |
| 11afc1b1 | 3428 | u32 semaphore_delay; |
| c44ade9e JB |
3429 | u16 word_size; |
| 3430 | u16 address_bits; | |
| 68c7005d | 3431 | u16 word_page_size; |
| 6ac74394 | 3432 | u16 ctrl_word_3; |
| 9a799d71 AK |
3433 | }; |
| 3434 | ||
| a4297dc2 | 3435 | #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 |
| c44ade9e JB |
3436 | struct ixgbe_mac_info { |
| 3437 | struct ixgbe_mac_operations ops; | |
| 3438 | enum ixgbe_mac_type type; | |
| ea99d832 JP |
3439 | u8 addr[ETH_ALEN]; |
| 3440 | u8 perm_addr[ETH_ALEN]; | |
| 3441 | u8 san_addr[ETH_ALEN]; | |
| 383ff34b YZ |
3442 | /* prefix for World Wide Node Name (WWNN) */ |
| 3443 | u16 wwnn_prefix; | |
| 3444 | /* prefix for World Wide Port Name (WWPN) */ | |
| 3445 | u16 wwpn_prefix; | |
| 71161302 | 3446 | u16 max_msix_vectors; |
| 80960ab0 ET |
3447 | #define IXGBE_MAX_MTA 128 |
| 3448 | u32 mta_shadow[IXGBE_MAX_MTA]; | |
| c44ade9e JB |
3449 | s32 mc_filter_type; |
| 3450 | u32 mcft_size; | |
| 3451 | u32 vft_size; | |
| 3452 | u32 num_rar_entries; | |
| 21ce849b | 3453 | u32 rar_highwater; |
| e09ad236 | 3454 | u32 rx_pb_size; |
| c44ade9e JB |
3455 | u32 max_tx_queues; |
| 3456 | u32 max_rx_queues; | |
| 3201d313 PWJ |
3457 | u32 orig_autoc; |
| 3458 | u32 orig_autoc2; | |
| 3459 | bool orig_link_settings_stored; | |
| 50ac58ba | 3460 | bool autotry_restart; |
| a4297dc2 | 3461 | u8 flags; |
| 7fa7c9dc | 3462 | u8 san_mac_rar_index; |
| e1ea9158 | 3463 | struct ixgbe_thermal_sensor_data thermal_sensor_data; |
| 1f9ac57c | 3464 | bool set_lben; |
| 9a799d71 AK |
3465 | }; |
| 3466 | ||
| c44ade9e JB |
3467 | struct ixgbe_phy_info { |
| 3468 | struct ixgbe_phy_operations ops; | |
| 6b73e10d | 3469 | struct mdio_if_info mdio; |
| c44ade9e | 3470 | enum ixgbe_phy_type type; |
| c44ade9e JB |
3471 | u32 id; |
| 3472 | enum ixgbe_sfp_type sfp_type; | |
| 553b4497 | 3473 | bool sfp_setup_needed; |
| c44ade9e JB |
3474 | u32 revision; |
| 3475 | enum ixgbe_media_type media_type; | |
| 030eaece | 3476 | u32 phy_semaphore_mask; |
| c44ade9e JB |
3477 | bool reset_disable; |
| 3478 | ixgbe_autoneg_advertised autoneg_advertised; | |
| ae8140aa | 3479 | ixgbe_link_speed speeds_supported; |
| cd7e1f0b DS |
3480 | enum ixgbe_smart_speed smart_speed; |
| 3481 | bool smart_speed_active; | |
| 0ecc061d | 3482 | bool multispeed_fiber; |
| 119fc60a | 3483 | bool reset_if_overtemp; |
| 8f58332b | 3484 | bool qsfp_shared_i2c_bus; |
| c3dc4c09 | 3485 | u32 nw_mng_if_sel; |
| 9a799d71 AK |
3486 | }; |
| 3487 | ||
| 7f870475 GR |
3488 | #include "ixgbe_mbx.h" |
| 3489 | ||
| 3490 | struct ixgbe_mbx_operations { | |
| 3491 | s32 (*init_params)(struct ixgbe_hw *hw); | |
| 3492 | s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); | |
| 3493 | s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); | |
| 3494 | s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); | |
| 3495 | s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); | |
| 3496 | s32 (*check_for_msg)(struct ixgbe_hw *, u16); | |
| 3497 | s32 (*check_for_ack)(struct ixgbe_hw *, u16); | |
| 3498 | s32 (*check_for_rst)(struct ixgbe_hw *, u16); | |
| 3499 | }; | |
| 3500 | ||
| 3501 | struct ixgbe_mbx_stats { | |
| 3502 | u32 msgs_tx; | |
| 3503 | u32 msgs_rx; | |
| 3504 | ||
| 3505 | u32 acks; | |
| 3506 | u32 reqs; | |
| 3507 | u32 rsts; | |
| 3508 | }; | |
| 3509 | ||
| 3510 | struct ixgbe_mbx_info { | |
| 37689010 | 3511 | const struct ixgbe_mbx_operations *ops; |
| 7f870475 GR |
3512 | struct ixgbe_mbx_stats stats; |
| 3513 | u32 timeout; | |
| 3514 | u32 usec_delay; | |
| 3515 | u32 v2p_mailbox; | |
| 3516 | u16 size; | |
| 3517 | }; | |
| 3518 | ||
| 9a799d71 AK |
3519 | struct ixgbe_hw { |
| 3520 | u8 __iomem *hw_addr; | |
| 3521 | void *back; | |
| 3522 | struct ixgbe_mac_info mac; | |
| 3523 | struct ixgbe_addr_filter_info addr_ctrl; | |
| 3524 | struct ixgbe_fc_info fc; | |
| 3525 | struct ixgbe_phy_info phy; | |
| 3526 | struct ixgbe_eeprom_info eeprom; | |
| 11afc1b1 | 3527 | struct ixgbe_bus_info bus; |
| 7f870475 | 3528 | struct ixgbe_mbx_info mbx; |
| 9a900eca | 3529 | const u32 *mvals; |
| 9a799d71 AK |
3530 | u16 device_id; |
| 3531 | u16 vendor_id; | |
| 3532 | u16 subsystem_device_id; | |
| 3533 | u16 subsystem_vendor_id; | |
| 3534 | u8 revision_id; | |
| 3535 | bool adapter_stopped; | |
| fe15e8e1 | 3536 | bool force_full_reset; |
| 8ef78adc | 3537 | bool allow_unsupported_sfp; |
| 6b92b0ba | 3538 | bool wol_enabled; |
| aac9e053 | 3539 | bool need_crosstalk_fix; |
| 9a799d71 AK |
3540 | }; |
| 3541 | ||
| c44ade9e JB |
3542 | struct ixgbe_info { |
| 3543 | enum ixgbe_mac_type mac; | |
| 3544 | s32 (*get_invariants)(struct ixgbe_hw *); | |
| 37689010 MR |
3545 | const struct ixgbe_mac_operations *mac_ops; |
| 3546 | const struct ixgbe_eeprom_operations *eeprom_ops; | |
| 3547 | const struct ixgbe_phy_operations *phy_ops; | |
| 3548 | const struct ixgbe_mbx_operations *mbx_ops; | |
| 9a900eca | 3549 | const u32 *mvals; |
| c44ade9e JB |
3550 | }; |
| 3551 | ||
| 3552 | ||
| 9a799d71 AK |
3553 | /* Error Codes */ |
| 3554 | #define IXGBE_ERR_EEPROM -1 | |
| 3555 | #define IXGBE_ERR_EEPROM_CHECKSUM -2 | |
| 3556 | #define IXGBE_ERR_PHY -3 | |
| 3557 | #define IXGBE_ERR_CONFIG -4 | |
| 3558 | #define IXGBE_ERR_PARAM -5 | |
| 3559 | #define IXGBE_ERR_MAC_TYPE -6 | |
| 3560 | #define IXGBE_ERR_UNKNOWN_PHY -7 | |
| 3561 | #define IXGBE_ERR_LINK_SETUP -8 | |
| 3562 | #define IXGBE_ERR_ADAPTER_STOPPED -9 | |
| 3563 | #define IXGBE_ERR_INVALID_MAC_ADDR -10 | |
| 3564 | #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 | |
| 3565 | #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 | |
| 3566 | #define IXGBE_ERR_INVALID_LINK_SETTINGS -13 | |
| 3567 | #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 | |
| 3568 | #define IXGBE_ERR_RESET_FAILED -15 | |
| 3569 | #define IXGBE_ERR_SWFW_SYNC -16 | |
| 3570 | #define IXGBE_ERR_PHY_ADDR_INVALID -17 | |
| c44ade9e JB |
3571 | #define IXGBE_ERR_I2C -18 |
| 3572 | #define IXGBE_ERR_SFP_NOT_SUPPORTED -19 | |
| c4900be0 | 3573 | #define IXGBE_ERR_SFP_NOT_PRESENT -20 |
| 11afc1b1 | 3574 | #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 |
| 21ce849b | 3575 | #define IXGBE_ERR_NO_SAN_ADDR_PTR -22 |
| bfde493e | 3576 | #define IXGBE_ERR_FDIR_REINIT_FAILED -23 |
| 794caeb2 | 3577 | #define IXGBE_ERR_EEPROM_VERSION -24 |
| 21ce849b | 3578 | #define IXGBE_ERR_NO_SPACE -25 |
| 119fc60a | 3579 | #define IXGBE_ERR_OVERTEMP -26 |
| 0b0c2b31 ET |
3580 | #define IXGBE_ERR_FC_NOT_NEGOTIATED -27 |
| 3581 | #define IXGBE_ERR_FC_NOT_SUPPORTED -28 | |
| a7f5a5fc | 3582 | #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 |
| 289700db DS |
3583 | #define IXGBE_ERR_PBA_SECTION -31 |
| 3584 | #define IXGBE_ERR_INVALID_ARGUMENT -32 | |
| 9612de92 | 3585 | #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 |
| d490d158 | 3586 | #define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38 |
| 49425dfc MR |
3587 | #define IXGBE_ERR_FW_RESP_INVALID -39 |
| 3588 | #define IXGBE_ERR_TOKEN_RETRY -40 | |
| 9a799d71 AK |
3589 | #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF |
| 3590 | ||
| 6ac74394 DS |
3591 | #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) |
| 3592 | #define IXGBE_FUSES0_300MHZ BIT(5) | |
| b4f47a48 | 3593 | #define IXGBE_FUSES0_REV_MASK (3u << 6) |
| 6ac74394 | 3594 | |
| d147329b MR |
3595 | #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) |
| 3596 | #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) | |
| afdc71e4 | 3597 | #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) |
| 2d40cd17 | 3598 | #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) |
| 200157c2 | 3599 | #define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0) |
| d147329b MR |
3600 | #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) |
| 3601 | #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) | |
| 3602 | #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) | |
| 3603 | #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00) | |
| 3604 | #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) | |
| 3605 | #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) | |
| 6a14ee0c | 3606 | |
| b4f47a48 JK |
3607 | #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B BIT(9) |
| 3608 | #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS BIT(11) | |
| 6a14ee0c | 3609 | |
| b4f47a48 JK |
3610 | #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (7u << 8) |
| 3611 | #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2u << 8) | |
| 3612 | #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4u << 8) | |
| 200157c2 MR |
3613 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12) |
| 3614 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13) | |
| b4f47a48 JK |
3615 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ BIT(14) |
| 3616 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC BIT(15) | |
| 3617 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX BIT(16) | |
| 3618 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR BIT(18) | |
| 3619 | #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX BIT(24) | |
| 3620 | #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR BIT(26) | |
| 3621 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE BIT(29) | |
| 3622 | #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART BIT(31) | |
| 3623 | ||
| 3624 | #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE BIT(28) | |
| 3625 | #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE BIT(29) | |
| afdc71e4 | 3626 | |
| 2d40cd17 MR |
3627 | #define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0) |
| 3628 | #define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1) | |
| 3629 | ||
| 200157c2 MR |
3630 | #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12) |
| 3631 | #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19) | |
| 3632 | ||
| b4f47a48 JK |
3633 | #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN BIT(6) |
| 3634 | #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN BIT(15) | |
| 3635 | #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN BIT(16) | |
| 6a14ee0c | 3636 | |
| b4f47a48 JK |
3637 | #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL BIT(4) |
| 3638 | #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS BIT(2) | |
| 6a14ee0c | 3639 | |
| b4f47a48 | 3640 | #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (3u << 16) |
| 6a14ee0c | 3641 | |
| b4f47a48 JK |
3642 | #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN BIT(1) |
| 3643 | #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN BIT(2) | |
| 3644 | #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3) | |
| 3645 | #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31) | |
| 6a14ee0c DS |
3646 | |
| 3647 | #define IXGBE_KX4_LINK_CNTL_1 0x4C | |
| b4f47a48 JK |
3648 | #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX BIT(16) |
| 3649 | #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 BIT(17) | |
| 3650 | #define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX BIT(24) | |
| 3651 | #define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 BIT(25) | |
| 3652 | #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE BIT(29) | |
| 3653 | #define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP BIT(30) | |
| 3654 | #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART BIT(31) | |
| 6a14ee0c DS |
3655 | |
| 3656 | #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 | |
| 3657 | #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 | |
| 3658 | ||
| 3659 | #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 | |
| 3660 | #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF | |
| 3661 | #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 | |
| 3662 | #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ | |
| 3663 | (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) | |
| 3664 | #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 | |
| 3665 | #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ | |
| 3666 | (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) | |
| 3667 | #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 | |
| 3668 | #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 | |
| 3669 | #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 | |
| b4f47a48 | 3670 | #define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) |
| 6a14ee0c DS |
3671 | #define IXGBE_SB_IOSF_TARGET_KR_PHY 0 |
| 3672 | #define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1 | |
| 3673 | #define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2 | |
| 3674 | #define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3 | |
| 3675 | ||
| c3dc4c09 | 3676 | #define IXGBE_NW_MNG_IF_SEL 0x00011178 |
| 537cc5df MR |
3677 | #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT BIT(1) |
| 3678 | #define IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M BIT(23) | |
| c3dc4c09 | 3679 | #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24) |
| 537cc5df MR |
3680 | #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3 |
| 3681 | #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ | |
| 3682 | (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT) | |
| 9a799d71 | 3683 | #endif /* _IXGBE_TYPE_H_ */ |