[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbevf / ixgbevf.h

/*******************************************************************************

  Intel 82599 Virtual Function driver
  Copyright(c) 1999 - 2015 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, see <http://www.gnu.org/licenses/>.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBEVF_H_
#define _IXGBEVF_H_

#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#include <linux/u64_stats_sync.h>

#include "vf.h"

#ifdef CONFIG_NET_RX_BUSY_POLL
#include <net/busy_poll.h>
#define BP_EXTENDED_STATS
#endif

#define IXGBE_MAX_TXD_PWR	14
#define IXGBE_MAX_DATA_PER_TXD	BIT(IXGBE_MAX_TXD_PWR)

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
#define DESC_NEEDED (MAX_SKB_FRAGS + 4)

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer
 */
struct ixgbevf_tx_buffer {
	union ixgbe_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	unsigned short gso_segs;
	__be16 protocol;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
	u32 tx_flags;
};

struct ixgbevf_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	unsigned int page_offset;
};

struct ixgbevf_stats {
	u64 packets;
	u64 bytes;
#ifdef BP_EXTENDED_STATS
	u64 yields;
	u64 misses;
	u64 cleaned;
#endif
};

struct ixgbevf_tx_queue_stats {
	u64 restart_queue;
	u64 tx_busy;
	u64 tx_done_old;
};

struct ixgbevf_rx_queue_stats {
	u64 alloc_rx_page_failed;
	u64 alloc_rx_buff_failed;
	u64 csum_err;
};

enum ixgbevf_ring_state_t {
	__IXGBEVF_TX_DETECT_HANG,
	__IXGBEVF_HANG_CHECK_ARMED,
};

#define check_for_tx_hang(ring) \
	test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
#define set_check_for_tx_hang(ring) \
	set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
#define clear_check_for_tx_hang(ring) \
	clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)

struct ixgbevf_ring {
	struct ixgbevf_ring *next;
	struct net_device *netdev;
	struct device *dev;
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	u16 count;			/* amount of descriptors */
	u16 next_to_use;
	u16 next_to_clean;
	u16 next_to_alloc;

	union {
		struct ixgbevf_tx_buffer *tx_buffer_info;
		struct ixgbevf_rx_buffer *rx_buffer_info;
	};
	unsigned long state;
	struct ixgbevf_stats stats;
	struct u64_stats_sync syncp;
	union {
		struct ixgbevf_tx_queue_stats tx_stats;
		struct ixgbevf_rx_queue_stats rx_stats;
	};

	u64 hw_csum_rx_error;
	u8 __iomem *tail;
	struct sk_buff *skb;

	/* holds the special value that gets the hardware register offset
	 * associated with this ring, which is different for DCB and RSS modes
	 */
	u16 reg_idx;
	int queue_index; /* needed for multiqueue queue management */
};

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBEVF_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
#define IXGBEVF_MAX_RSS_QUEUES		2
#define IXGBEVF_82599_RETA_SIZE		128	/* 128 entries */
#define IXGBEVF_X550_VFRETA_SIZE	64	/* 64 entries */
#define IXGBEVF_RSS_HASH_KEY_SIZE	40
#define IXGBEVF_VFRSSRK_REGS		10	/* 10 registers for RSS key */

#define IXGBEVF_DEFAULT_TXD	1024
#define IXGBEVF_DEFAULT_RXD	512
#define IXGBEVF_MAX_TXD		4096
#define IXGBEVF_MIN_TXD		64
#define IXGBEVF_MAX_RXD		4096
#define IXGBEVF_MIN_RXD		64

/* Supported Rx Buffer Sizes */
#define IXGBEVF_RXBUFFER_256	256    /* Used for packet split */
#define IXGBEVF_RXBUFFER_2048	2048

#define IXGBEVF_RX_HDR_SIZE	IXGBEVF_RXBUFFER_256
#define IXGBEVF_RX_BUFSZ	IXGBEVF_RXBUFFER_2048

#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)

#define IXGBE_TX_FLAGS_CSUM		BIT(0)
#define IXGBE_TX_FLAGS_VLAN		BIT(1)
#define IXGBE_TX_FLAGS_TSO		BIT(2)
#define IXGBE_TX_FLAGS_IPV4		BIT(3)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK	0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

struct ixgbevf_ring_container {
	struct ixgbevf_ring *ring;	/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u8 count;			/* total number of rings in vector */
	u8 itr;				/* current ITR setting for ring */
};

/* iterator for handling rings in ring container */
#define ixgbevf_for_each_ring(pos, head) \
	for (pos = (head).ring; pos != NULL; pos = pos->next)

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbevf_q_vector {
	struct ixgbevf_adapter *adapter;
	/* index of q_vector within array, also used for finding the bit in
	 * EICR and friends that represents the vector for this ring
	 */
	u16 v_idx;
	u16 itr; /* Interrupt throttle rate written to EITR */
	struct napi_struct napi;
	struct ixgbevf_ring_container rx, tx;
	char name[IFNAMSIZ + 9];
#ifdef CONFIG_NET_RX_BUSY_POLL
	unsigned int state;
#define IXGBEVF_QV_STATE_IDLE		0
#define IXGBEVF_QV_STATE_NAPI		1    /* NAPI owns this QV */
#define IXGBEVF_QV_STATE_POLL		2    /* poll owns this QV */
#define IXGBEVF_QV_STATE_DISABLED	4    /* QV is disabled */
#define IXGBEVF_QV_OWNED	(IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
#define IXGBEVF_QV_LOCKED	(IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
#define IXGBEVF_QV_STATE_NAPI_YIELD	8    /* NAPI yielded this QV */
#define IXGBEVF_QV_STATE_POLL_YIELD	16   /* poll yielded this QV */
#define IXGBEVF_QV_YIELD	(IXGBEVF_QV_STATE_NAPI_YIELD | \
				 IXGBEVF_QV_STATE_POLL_YIELD)
#define IXGBEVF_QV_USER_PEND	(IXGBEVF_QV_STATE_POLL | \
				 IXGBEVF_QV_STATE_POLL_YIELD)
	spinlock_t lock;
#endif /* CONFIG_NET_RX_BUSY_POLL */
};

#ifdef CONFIG_NET_RX_BUSY_POLL
static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
{
	spin_lock_init(&q_vector->lock);
	q_vector->state = IXGBEVF_QV_STATE_IDLE;
}

/* called from the device poll routine to get ownership of a q_vector */
static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
{
	int rc = true;

	spin_lock_bh(&q_vector->lock);
	if (q_vector->state & IXGBEVF_QV_LOCKED) {
		WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
		q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD;
		rc = false;
#ifdef BP_EXTENDED_STATS
		q_vector->tx.ring->stats.yields++;
#endif
	} else {
		/* we don't care if someone yielded */
		q_vector->state = IXGBEVF_QV_STATE_NAPI;
	}
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* returns true is someone tried to get the qv while napi had it */
static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
{
	int rc = false;

	spin_lock_bh(&q_vector->lock);
	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL |
				   IXGBEVF_QV_STATE_NAPI_YIELD));

	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
		rc = true;
	/* reset state to idle, unless QV is disabled */
	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* called from ixgbevf_low_latency_poll() */
static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
{
	int rc = true;

	spin_lock_bh(&q_vector->lock);
	if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
		q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD;
		rc = false;
#ifdef BP_EXTENDED_STATS
		q_vector->rx.ring->stats.yields++;
#endif
	} else {
		/* preserve yield marks */
		q_vector->state |= IXGBEVF_QV_STATE_POLL;
	}
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* returns true if someone tried to get the qv while it was locked */
static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
{
	int rc = false;

	spin_lock_bh(&q_vector->lock);
	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));

	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
		rc = true;
	/* reset state to idle, unless QV is disabled */
	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* true if a socket is polling, even if it did not get the lock */
static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
{
	WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
	return q_vector->state & IXGBEVF_QV_USER_PEND;
}

/* false if QV is currently owned */
static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
{
	int rc = true;

	spin_lock_bh(&q_vector->lock);
	if (q_vector->state & IXGBEVF_QV_OWNED)
		rc = false;
	q_vector->state |= IXGBEVF_QV_STATE_DISABLED;
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

#endif /* CONFIG_NET_RX_BUSY_POLL */

/* microsecond values for various ITR rates shifted by 2 to fit itr register
 * with the first 3 bits reserved 0
 */
#define IXGBE_MIN_RSC_ITR	24
#define IXGBE_100K_ITR		40
#define IXGBE_20K_ITR		200
#define IXGBE_12K_ITR		336

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.  The lowest value
 * supported by all of the ixgbe hardware is 8.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
					  const u32 stat_err_bits)
{
	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
}

static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
{
	u16 ntc = ring->next_to_clean;
	u16 ntu = ring->next_to_use;

	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
}

static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
{
	writel(value, ring->tail);
}

#define IXGBEVF_RX_DESC(R, i)	\
	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
#define IXGBEVF_TX_DESC(R, i)	\
	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
#define IXGBEVF_TX_CTXTDESC(R, i)	\
	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE	9728 /* Maximum Supported Size 9.5KB */

#define OTHER_VECTOR	1
#define NON_Q_VECTORS	(OTHER_VECTOR)

#define MAX_MSIX_Q_VECTORS	2

#define MIN_MSIX_Q_VECTORS	1
#define MIN_MSIX_COUNT		(MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbevf_adapter {
	/* this field must be first, see ixgbevf_process_skb_fields */
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];

	/* Interrupt Throttle Rate */
	u16 rx_itr_setting;
	u16 tx_itr_setting;

	/* interrupt masks */
	u32 eims_enable_mask;
	u32 eims_other;

	/* TX */
	int num_tx_queues;
	struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
	u64 restart_queue;
	u32 tx_timeout_count;

	/* RX */
	int num_rx_queues;
	struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	int num_msix_vectors;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	struct msix_entry *msix_entries;

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;

	/* structs defined in ixgbe_vf.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	/* Interrupt Throttle Rate */
	u32 eitr_param;

	struct ixgbevf_hw_stats stats;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u8 __iomem *io_addr; /* Mainly for iounmap use */
	u32 link_speed;
	bool link_up;

	struct timer_list service_timer;
	struct work_struct service_task;

	spinlock_t mbx_lock;
	unsigned long last_reset;

	u32 rss_key[IXGBEVF_VFRSSRK_REGS];
	u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
};

enum ixbgevf_state_t {
	__IXGBEVF_TESTING,
	__IXGBEVF_RESETTING,
	__IXGBEVF_DOWN,
	__IXGBEVF_DISABLED,
	__IXGBEVF_REMOVING,
	__IXGBEVF_SERVICE_SCHED,
	__IXGBEVF_SERVICE_INITED,
	__IXGBEVF_RESET_REQUESTED,
	__IXGBEVF_QUEUE_RESET_REQUESTED,
};

enum ixgbevf_boards {
	board_82599_vf,
	board_82599_vf_hv,
	board_X540_vf,
	board_X540_vf_hv,
	board_X550_vf,
	board_X550_vf_hv,
	board_X550EM_x_vf,
	board_X550EM_x_vf_hv,
	board_x550em_a_vf,
};

enum ixgbevf_xcast_modes {
	IXGBEVF_XCAST_MODE_NONE = 0,
	IXGBEVF_XCAST_MODE_MULTI,
	IXGBEVF_XCAST_MODE_ALLMULTI,
};

extern const struct ixgbevf_info ixgbevf_82599_vf_info;
extern const struct ixgbevf_info ixgbevf_X540_vf_info;
extern const struct ixgbevf_info ixgbevf_X550_vf_info;
extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info;

extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info;
extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info;
extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info;
extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info;
extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops;

/* needed by ethtool.c */
extern const char ixgbevf_driver_name[];
extern const char ixgbevf_driver_version[];

int ixgbevf_open(struct net_device *netdev);
int ixgbevf_close(struct net_device *netdev);
void ixgbevf_up(struct ixgbevf_adapter *adapter);
void ixgbevf_down(struct ixgbevf_adapter *adapter);
void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
void ixgbevf_reset(struct ixgbevf_adapter *adapter);
void ixgbevf_set_ethtool_ops(struct net_device *netdev);
int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
int ethtool_ioctl(struct ifreq *ifr);

extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);

void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);

#define ixgbevf_hw_to_netdev(hw) \
	(((struct ixgbevf_adapter *)(hw)->back)->netdev)

#define hw_dbg(hw, format, arg...) \
	netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg)
#endif /* _IXGBEVF_H_ */
Commit	Line	Data
92915f71 GR	1	/*******************************************************************************
	2
	3	Intel 82599 Virtual Function driver
dec0d8e4	4	Copyright(c) 1999 - 2015 Intel Corporation.
92915f71 GR	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
dec0d8e4	16	this program; if not, see <http://www.gnu.org/licenses/>.
92915f71 GR	17
	18	The full GNU General Public License is included in this distribution in
	19	the file called "COPYING".
	20
	21	Contact Information:
	22	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	23	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	24
	25	*******************************************************************************/
	26
	27	#ifndef _IXGBEVF_H_
	28	#define _IXGBEVF_H_
	29
	30	#include <linux/types.h>
dadcd65f	31	#include <linux/bitops.h>
92915f71 GR	32	#include <linux/timer.h>
	33	#include <linux/io.h>
	34	#include <linux/netdevice.h>
dadcd65f	35	#include <linux/if_vlan.h>
4197aa7b	36	#include <linux/u64_stats_sync.h>
92915f71 GR	37
	38	#include "vf.h"
	39
c777cdfa JK	40	#ifdef CONFIG_NET_RX_BUSY_POLL
c777cdfa JK	41	#include <net/busy_poll.h>
3b5dca26	42	#define BP_EXTENDED_STATS
c777cdfa JK	43	#endif
c777cdfa JK	44
e08400b7 ET	45	#define IXGBE_MAX_TXD_PWR 14
	46	#define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR)
	47
	48	/* Tx Descriptors needed, worst case */
	49	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
	50	#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
	51
92915f71	52	/* wrapper around a pointer to a socket buffer,
dec0d8e4 JK	53	* so a DMA handle can be stored along with the buffer
dec0d8e4 JK	54	*/
92915f71	55	struct ixgbevf_tx_buffer {
7ad1a093 ET	56	union ixgbe_adv_tx_desc *next_to_watch;
7ad1a093 ET	57	unsigned long time_stamp;
92915f71	58	struct sk_buff *skb;
7ad1a093 ET	59	unsigned int bytecount;
	60	unsigned short gso_segs;
	61	__be16 protocol;
9bdfefd2 ET	62	DEFINE_DMA_UNMAP_ADDR(dma);
9bdfefd2 ET	63	DEFINE_DMA_UNMAP_LEN(len);
7ad1a093	64	u32 tx_flags;
92915f71 GR	65	};
	66
	67	struct ixgbevf_rx_buffer {
92915f71	68	dma_addr_t dma;
bad17234 ET	69	struct page *page;
bad17234 ET	70	unsigned int page_offset;
92915f71 GR	71	};
92915f71 GR	72
095e2617 ET	73	struct ixgbevf_stats {
	74	u64 packets;
	75	u64 bytes;
	76	#ifdef BP_EXTENDED_STATS
	77	u64 yields;
	78	u64 misses;
	79	u64 cleaned;
	80	#endif
	81	};
	82
	83	struct ixgbevf_tx_queue_stats {
	84	u64 restart_queue;
	85	u64 tx_busy;
	86	u64 tx_done_old;
	87	};
	88
	89	struct ixgbevf_rx_queue_stats {
095e2617 ET	90	u64 alloc_rx_page_failed;
	91	u64 alloc_rx_buff_failed;
	92	u64 csum_err;
	93	};
	94
e08400b7 ET	95	enum ixgbevf_ring_state_t {
	96	__IXGBEVF_TX_DETECT_HANG,
	97	__IXGBEVF_HANG_CHECK_ARMED,
	98	};
	99
	100	#define check_for_tx_hang(ring) \
	101	test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
	102	#define set_check_for_tx_hang(ring) \
	103	set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
	104	#define clear_check_for_tx_hang(ring) \
	105	clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state)
	106
92915f71	107	struct ixgbevf_ring {
6b43c446	108	struct ixgbevf_ring *next;
fb40195c AD	109	struct net_device *netdev;
fb40195c AD	110	struct device *dev;
92915f71 GR	111	void desc; / descriptor ring memory */
	112	dma_addr_t dma; /* phys. address of descriptor ring */
	113	unsigned int size; /* length in bytes */
bad17234 ET	114	u16 count; /* amount of descriptors */
	115	u16 next_to_use;
	116	u16 next_to_clean;
	117	u16 next_to_alloc;
92915f71	118
92915f71 GR	119	union {
	120	struct ixgbevf_tx_buffer *tx_buffer_info;
	121	struct ixgbevf_rx_buffer *rx_buffer_info;
	122	};
e08400b7	123	unsigned long state;
095e2617 ET	124	struct ixgbevf_stats stats;
	125	struct u64_stats_sync syncp;
	126	union {
	127	struct ixgbevf_tx_queue_stats tx_stats;
	128	struct ixgbevf_rx_queue_stats rx_stats;
	129	};
	130
55fb277c	131	u64 hw_csum_rx_error;
5cdab2f6	132	u8 __iomem *tail;
bad17234	133	struct sk_buff *skb;
92915f71	134
dec0d8e4 JK	135	/* holds the special value that gets the hardware register offset
	136	* associated with this ring, which is different for DCB and RSS modes
	137	*/
	138	u16 reg_idx;
095e2617	139	int queue_index; /* needed for multiqueue queue management */
92915f71 GR	140	};
92915f71 GR	141
92915f71 GR	142	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	143	#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	144
56e94095 AD	145	#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
56e94095 AD	146	#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
9cba434f ET	147	#define IXGBEVF_MAX_RSS_QUEUES 2
	148	#define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */
	149	#define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */
ad1431e2	150	#define IXGBEVF_RSS_HASH_KEY_SIZE 40
9cba434f	151	#define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */
92915f71	152
dec0d8e4 JK	153	#define IXGBEVF_DEFAULT_TXD 1024
	154	#define IXGBEVF_DEFAULT_RXD 512
	155	#define IXGBEVF_MAX_TXD 4096
	156	#define IXGBEVF_MIN_TXD 64
	157	#define IXGBEVF_MAX_RXD 4096
	158	#define IXGBEVF_MIN_RXD 64
92915f71 GR	159
92915f71 GR	160	/* Supported Rx Buffer Sizes */
dec0d8e4 JK	161	#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
dec0d8e4 JK	162	#define IXGBEVF_RXBUFFER_2048 2048
92915f71	163
dec0d8e4 JK	164	#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
dec0d8e4 JK	165	#define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048
92915f71 GR	166
	167	#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
	168
8d055cc0 JK	169	#define IXGBE_TX_FLAGS_CSUM BIT(0)
	170	#define IXGBE_TX_FLAGS_VLAN BIT(1)
	171	#define IXGBE_TX_FLAGS_TSO BIT(2)
	172	#define IXGBE_TX_FLAGS_IPV4 BIT(3)
92915f71 GR	173	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
	174	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
	175	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	176
6b43c446 AD	177	struct ixgbevf_ring_container {
6b43c446 AD	178	struct ixgbevf_ring ring; / pointer to linked list of rings */
5f3600eb AD	179	unsigned int total_bytes; /* total bytes processed this int */
5f3600eb AD	180	unsigned int total_packets; /* total packets processed this int */
6b43c446 AD	181	u8 count; /* total number of rings in vector */
	182	u8 itr; /* current ITR setting for ring */
	183	};
	184
	185	/* iterator for handling rings in ring container */
	186	#define ixgbevf_for_each_ring(pos, head) \
	187	for (pos = (head).ring; pos != NULL; pos = pos->next)
	188
92915f71 GR	189	/* MAX_MSIX_Q_VECTORS of these are allocated,
	190	* but we only use one per queue-specific vector.
	191	*/
	192	struct ixgbevf_q_vector {
	193	struct ixgbevf_adapter *adapter;
dec0d8e4 JK	194	/* index of q_vector within array, also used for finding the bit in
	195	* EICR and friends that represents the vector for this ring
	196	*/
	197	u16 v_idx;
	198	u16 itr; /* Interrupt throttle rate written to EITR */
92915f71	199	struct napi_struct napi;
6b43c446	200	struct ixgbevf_ring_container rx, tx;
fa71ae27	201	char name[IFNAMSIZ + 9];
c777cdfa JK	202	#ifdef CONFIG_NET_RX_BUSY_POLL
	203	unsigned int state;
	204	#define IXGBEVF_QV_STATE_IDLE 0
	205	#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
	206	#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
	207	#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
dec0d8e4 JK	208	#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI \| IXGBEVF_QV_STATE_POLL)
dec0d8e4 JK	209	#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED \| IXGBEVF_QV_STATE_DISABLED)
c777cdfa JK	210	#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
c777cdfa JK	211	#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
dec0d8e4 JK	212	#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD \| \
	213	IXGBEVF_QV_STATE_POLL_YIELD)
	214	#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL \| \
	215	IXGBEVF_QV_STATE_POLL_YIELD)
c777cdfa JK	216	spinlock_t lock;
c777cdfa JK	217	#endif /* CONFIG_NET_RX_BUSY_POLL */
92915f71	218	};
dec0d8e4	219
c777cdfa JK	220	#ifdef CONFIG_NET_RX_BUSY_POLL
	221	static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
	222	{
c777cdfa JK	223	spin_lock_init(&q_vector->lock);
	224	q_vector->state = IXGBEVF_QV_STATE_IDLE;
	225	}
	226
	227	/* called from the device poll routine to get ownership of a q_vector */
	228	static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
	229	{
	230	int rc = true;
dec0d8e4	231
c777cdfa JK	232	spin_lock_bh(&q_vector->lock);
	233	if (q_vector->state & IXGBEVF_QV_LOCKED) {
	234	WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
	235	q_vector->state \|= IXGBEVF_QV_STATE_NAPI_YIELD;
	236	rc = false;
3b5dca26	237	#ifdef BP_EXTENDED_STATS
095e2617	238	q_vector->tx.ring->stats.yields++;
3b5dca26	239	#endif
c777cdfa JK	240	} else {
	241	/* we don't care if someone yielded */
	242	q_vector->state = IXGBEVF_QV_STATE_NAPI;
	243	}
	244	spin_unlock_bh(&q_vector->lock);
	245	return rc;
	246	}
	247
	248	/* returns true is someone tried to get the qv while napi had it */
	249	static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
	250	{
	251	int rc = false;
dec0d8e4	252
c777cdfa JK	253	spin_lock_bh(&q_vector->lock);
	254	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL \|
	255	IXGBEVF_QV_STATE_NAPI_YIELD));
	256
	257	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
	258	rc = true;
	259	/* reset state to idle, unless QV is disabled */
	260	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	261	spin_unlock_bh(&q_vector->lock);
	262	return rc;
	263	}
	264
	265	/* called from ixgbevf_low_latency_poll() */
	266	static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
	267	{
	268	int rc = true;
dec0d8e4	269
c777cdfa JK	270	spin_lock_bh(&q_vector->lock);
	271	if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
	272	q_vector->state \|= IXGBEVF_QV_STATE_POLL_YIELD;
	273	rc = false;
3b5dca26	274	#ifdef BP_EXTENDED_STATS
095e2617	275	q_vector->rx.ring->stats.yields++;
3b5dca26	276	#endif
c777cdfa JK	277	} else {
	278	/* preserve yield marks */
	279	q_vector->state \|= IXGBEVF_QV_STATE_POLL;
	280	}
	281	spin_unlock_bh(&q_vector->lock);
	282	return rc;
	283	}
	284
	285	/* returns true if someone tried to get the qv while it was locked */
	286	static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
	287	{
	288	int rc = false;
dec0d8e4	289
c777cdfa JK	290	spin_lock_bh(&q_vector->lock);
	291	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));
	292
	293	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
	294	rc = true;
	295	/* reset state to idle, unless QV is disabled */
	296	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	297	spin_unlock_bh(&q_vector->lock);
	298	return rc;
	299	}
	300
	301	/* true if a socket is polling, even if it did not get the lock */
	302	static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
	303	{
	304	WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
	305	return q_vector->state & IXGBEVF_QV_USER_PEND;
	306	}
	307
	308	/* false if QV is currently owned */
	309	static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
	310	{
	311	int rc = true;
dec0d8e4	312
c777cdfa JK	313	spin_lock_bh(&q_vector->lock);
	314	if (q_vector->state & IXGBEVF_QV_OWNED)
	315	rc = false;
e689e728	316	q_vector->state \|= IXGBEVF_QV_STATE_DISABLED;
c777cdfa JK	317	spin_unlock_bh(&q_vector->lock);
	318	return rc;
	319	}
	320
	321	#endif /* CONFIG_NET_RX_BUSY_POLL */
92915f71	322
dec0d8e4	323	/* microsecond values for various ITR rates shifted by 2 to fit itr register
5f3600eb AD	324	* with the first 3 bits reserved 0
	325	*/
	326	#define IXGBE_MIN_RSC_ITR 24
	327	#define IXGBE_100K_ITR 40
	328	#define IXGBE_20K_ITR 200
8a9ca110	329	#define IXGBE_12K_ITR 336
5f3600eb	330
92915f71 GR	331	/* Helper macros to switch between ints/sec and what the register uses.
	332	* And yes, it's the same math going both ways. The lowest value
	333	* supported by all of the ixgbe hardware is 8.
	334	*/
	335	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	336	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
	337	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	338
ec62fe26 ET	339	/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
	340	static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
	341	const u32 stat_err_bits)
	342	{
	343	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
	344	}
	345
f880d07b DS	346	static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
	347	{
	348	u16 ntc = ring->next_to_clean;
	349	u16 ntu = ring->next_to_use;
	350
	351	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
	352	}
92915f71	353
06380db6 MR	354	static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
	355	{
	356	writel(value, ring->tail);
	357	}
	358
dec0d8e4	359	#define IXGBEVF_RX_DESC(R, i) \
908421f6	360	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
dec0d8e4	361	#define IXGBEVF_TX_DESC(R, i) \
908421f6	362	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
dec0d8e4	363	#define IXGBEVF_TX_CTXTDESC(R, i) \
908421f6	364	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
92915f71	365
c88887e0	366	#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
92915f71	367
dec0d8e4 JK	368	#define OTHER_VECTOR 1
dec0d8e4 JK	369	#define NON_Q_VECTORS (OTHER_VECTOR)
92915f71	370
dec0d8e4	371	#define MAX_MSIX_Q_VECTORS 2
92915f71	372
dec0d8e4 JK	373	#define MIN_MSIX_Q_VECTORS 1
dec0d8e4 JK	374	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
92915f71 GR	375
	376	/* board specific private data structure */
	377	struct ixgbevf_adapter {
dff80520	378	/* this field must be first, see ixgbevf_process_skb_fields */
dadcd65f	379	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
dff80520	380
92915f71	381	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
92915f71 GR	382
92915f71 GR	383	/* Interrupt Throttle Rate */
5f3600eb AD	384	u16 rx_itr_setting;
	385	u16 tx_itr_setting;
	386
	387	/* interrupt masks */
	388	u32 eims_enable_mask;
	389	u32 eims_other;
92915f71 GR	390
92915f71 GR	391	/* TX */
92915f71	392	int num_tx_queues;
97031922	393	struct ixgbevf_ring tx_ring[MAX_TX_QUEUES]; / One per active queue */
92915f71	394	u64 restart_queue;
92915f71	395	u32 tx_timeout_count;
92915f71 GR	396
92915f71 GR	397	/* RX */
92915f71	398	int num_rx_queues;
97031922	399	struct ixgbevf_ring rx_ring[MAX_TX_QUEUES]; / One per active queue */
92915f71 GR	400	u64 hw_csum_rx_error;
92915f71 GR	401	u64 hw_rx_no_dma_resources;
92915f71	402	int num_msix_vectors;
92915f71 GR	403	u32 alloc_rx_page_failed;
	404	u32 alloc_rx_buff_failed;
	405
97031922 ET	406	struct msix_entry *msix_entries;
97031922 ET	407
92915f71 GR	408	/* OS defined structs */
	409	struct net_device *netdev;
	410	struct pci_dev *pdev;
92915f71 GR	411
	412	/* structs defined in ixgbe_vf.h */
	413	struct ixgbe_hw hw;
	414	u16 msg_enable;
92915f71 GR	415	/* Interrupt Throttle Rate */
	416	u32 eitr_param;
	417
97031922 ET	418	struct ixgbevf_hw_stats stats;
97031922 ET	419
92915f71	420	unsigned long state;
92915f71 GR	421	u64 tx_busy;
	422	unsigned int tx_ring_count;
	423	unsigned int rx_ring_count;
	424
dbf8b0d8	425	u8 __iomem io_addr; / Mainly for iounmap use */
92915f71 GR	426	u32 link_speed;
92915f71 GR	427	bool link_up;
92915f71	428
9ac5c5cc ET	429	struct timer_list service_timer;
	430	struct work_struct service_task;
	431
1c55ed76	432	spinlock_t mbx_lock;
e66c92ad	433	unsigned long last_reset;
9cba434f ET	434
	435	u32 rss_key[IXGBEVF_VFRSSRK_REGS];
	436	u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE];
92915f71 GR	437	};
	438
	439	enum ixbgevf_state_t {
	440	__IXGBEVF_TESTING,
	441	__IXGBEVF_RESETTING,
2e7cfbdd	442	__IXGBEVF_DOWN,
bc0c7151	443	__IXGBEVF_DISABLED,
2e7cfbdd	444	__IXGBEVF_REMOVING,
9ac5c5cc ET	445	__IXGBEVF_SERVICE_SCHED,
9ac5c5cc ET	446	__IXGBEVF_SERVICE_INITED,
d5dd7c3f ET	447	__IXGBEVF_RESET_REQUESTED,
d5dd7c3f ET	448	__IXGBEVF_QUEUE_RESET_REQUESTED,
92915f71 GR	449	};
	450
	451	enum ixgbevf_boards {
	452	board_82599_vf,
c6d45171	453	board_82599_vf_hv,
2316aa2a	454	board_X540_vf,
c6d45171	455	board_X540_vf_hv,
47068b0d	456	board_X550_vf,
c6d45171	457	board_X550_vf_hv,
47068b0d	458	board_X550EM_x_vf,
c6d45171	459	board_X550EM_x_vf_hv,
1d94f987	460	board_x550em_a_vf,
92915f71 GR	461	};
92915f71 GR	462
8443c1a4 HS	463	enum ixgbevf_xcast_modes {
	464	IXGBEVF_XCAST_MODE_NONE = 0,
	465	IXGBEVF_XCAST_MODE_MULTI,
	466	IXGBEVF_XCAST_MODE_ALLMULTI,
	467	};
	468
3d8fe98f SH	469	extern const struct ixgbevf_info ixgbevf_82599_vf_info;
3d8fe98f SH	470	extern const struct ixgbevf_info ixgbevf_X540_vf_info;
47068b0d ET	471	extern const struct ixgbevf_info ixgbevf_X550_vf_info;
47068b0d ET	472	extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
b5417bf8	473	extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
1d94f987	474	extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info;
92915f71	475
c6d45171 KS	476	extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info;
	477	extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info;
	478	extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info;
	479	extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info;
	480	extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops;
	481
92915f71	482	/* needed by ethtool.c */
3d8fe98f	483	extern const char ixgbevf_driver_name[];
92915f71 GR	484	extern const char ixgbevf_driver_version[];
92915f71 GR	485
324d0867 SA	486	int ixgbevf_open(struct net_device *netdev);
324d0867 SA	487	int ixgbevf_close(struct net_device *netdev);
5ccc921a JP	488	void ixgbevf_up(struct ixgbevf_adapter *adapter);
	489	void ixgbevf_down(struct ixgbevf_adapter *adapter);
	490	void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
	491	void ixgbevf_reset(struct ixgbevf_adapter *adapter);
	492	void ixgbevf_set_ethtool_ops(struct net_device *netdev);
05d063aa ET	493	int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
	494	int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
	495	void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
	496	void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
5ccc921a JP	497	void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
	498	int ethtool_ioctl(struct ifreq *ifr);
	499
3849623e JK	500	extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
3849623e JK	501
5ccc921a JP	502	void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
5ccc921a JP	503	void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
92915f71	504
4ad6af02 ET	505	#define ixgbevf_hw_to_netdev(hw) \
4ad6af02 ET	506	(((struct ixgbevf_adapter *)(hw)->back)->netdev)
92915f71	507
4ad6af02 ET	508	#define hw_dbg(hw, format, arg...) \
4ad6af02 ET	509	netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg)
92915f71	510	#endif /* _IXGBEVF_H_ */