Commit | Line | Data |
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c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
0e03f563 JZ |
14 | #include <linux/clk.h> |
15 | #include <linux/cpu.h> | |
c5aff182 | 16 | #include <linux/etherdevice.h> |
0e03f563 | 17 | #include <linux/if_vlan.h> |
c5aff182 | 18 | #include <linux/inetdevice.h> |
c5aff182 | 19 | #include <linux/interrupt.h> |
c3f0dd38 | 20 | #include <linux/io.h> |
0e03f563 JZ |
21 | #include <linux/kernel.h> |
22 | #include <linux/mbus.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
c5aff182 | 25 | #include <linux/of.h> |
0e03f563 | 26 | #include <linux/of_address.h> |
c5aff182 TP |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> | |
29 | #include <linux/of_net.h> | |
c5aff182 | 30 | #include <linux/phy.h> |
0e03f563 JZ |
31 | #include <linux/platform_device.h> |
32 | #include <linux/skbuff.h> | |
baa11ebc | 33 | #include <net/hwbm.h> |
dc35a10f | 34 | #include "mvneta_bm.h" |
0e03f563 JZ |
35 | #include <net/ip.h> |
36 | #include <net/ipv6.h> | |
37 | #include <net/tso.h> | |
c5aff182 TP |
38 | |
39 | /* Registers */ | |
40 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 41 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
dc35a10f MW |
42 | #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 |
43 | #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 | |
44 | #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 | |
45 | #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 | |
c5aff182 TP |
46 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
47 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
48 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
49 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
50 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
51 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
52 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
53 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
54 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
55 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
56 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
57 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
58 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
dc35a10f MW |
59 | #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) |
60 | #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 | |
61 | #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 | |
c5aff182 TP |
62 | #define MVNETA_PORT_RX_RESET 0x1cc0 |
63 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
64 | #define MVNETA_PHY_ADDR 0x2000 | |
65 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
66 | #define MVNETA_MBUS_RETRY 0x2010 | |
67 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
68 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
69 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
70 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
71 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
72 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
73 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 74 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
75 | #define MVNETA_PORT_CONFIG 0x2400 |
76 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
77 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
78 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
79 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
80 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
81 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
82 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
83 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
84 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
85 | MVNETA_DEF_RXQ_ARP(q) | \ | |
86 | MVNETA_DEF_RXQ_TCP(q) | \ | |
87 | MVNETA_DEF_RXQ_UDP(q) | \ | |
88 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
89 | MVNETA_TX_UNSET_ERR_SUM | \ | |
90 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
91 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
92 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
93 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
94 | #define MVNETA_SDMA_CONFIG 0x241c | |
95 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
96 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
97 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
98 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 99 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
100 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
101 | #define MVNETA_PORT_STATUS 0x2444 | |
102 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
103 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
104 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 105 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 106 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 107 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
108 | #define MVNETA_TYPE_PRIO 0x24bc |
109 | #define MVNETA_FORCE_UNI BIT(21) | |
110 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
111 | #define MVNETA_TXQ_CMD 0x2448 | |
112 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
113 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
114 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
115 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
116 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
117 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 | 118 | #define MVNETA_ACC_MODE 0x2500 |
dc35a10f | 119 | #define MVNETA_BM_ADDRESS 0x2504 |
c5aff182 TP |
120 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) |
121 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
122 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 123 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 124 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 125 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 126 | |
2dcf75e2 GC |
127 | /* Exception Interrupt Port/Queue Cause register |
128 | * | |
129 | * Their behavior depend of the mapping done using the PCPX2Q | |
130 | * registers. For a given CPU if the bit associated to a queue is not | |
131 | * set, then for the register a read from this CPU will always return | |
132 | * 0 and a write won't do anything | |
133 | */ | |
40ba35e7 | 134 | |
c5aff182 | 135 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 136 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 137 | |
138 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
139 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
140 | * bits 16..23 = RXQ FREE, one bit per queue. | |
141 | * bit 29 = OLD_REG_SUM, see old reg ? | |
142 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
143 | * bit 31 = MISC_SUM, one bit for 4 ports | |
144 | */ | |
145 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
146 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
147 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
148 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 149 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 150 | |
c5aff182 TP |
151 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
152 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 153 | |
154 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
155 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
156 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 157 | |
158 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
159 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
160 | #define MVNETA_CAUSE_PTP BIT(4) | |
161 | ||
162 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
163 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
164 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
165 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
166 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
167 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
168 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
169 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
170 | ||
171 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
172 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
173 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
174 | ||
175 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
176 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
177 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
178 | ||
c5aff182 TP |
179 | #define MVNETA_INTR_ENABLE 0x25b8 |
180 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 181 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 182 | |
c5aff182 TP |
183 | #define MVNETA_RXQ_CMD 0x2680 |
184 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
185 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
186 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
187 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
188 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
189 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
190 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
191 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
192 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 193 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 194 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
195 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
196 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
197 | #define MVNETA_GMAC_STATUS 0x2c10 | |
198 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
199 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
200 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
201 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
202 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
203 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
204 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
205 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
206 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
207 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
208 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 209 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
c5aff182 TP |
210 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
211 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 212 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
898b2970 | 213 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 214 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 215 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
e483911f | 216 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
217 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
218 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
219 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
220 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
221 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
222 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
223 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
224 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
225 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
226 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
227 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) | |
228 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
229 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
230 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
231 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
232 | #define MVNETA_TX_MTU 0x3e0c | |
233 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
234 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
235 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
236 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
237 | ||
238 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff | |
239 | ||
240 | /* Descriptor ring Macros */ | |
241 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
242 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
243 | ||
244 | /* Various constants */ | |
245 | ||
246 | /* Coalescing */ | |
06708f81 | 247 | #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ |
c5aff182 TP |
248 | #define MVNETA_RX_COAL_PKTS 32 |
249 | #define MVNETA_RX_COAL_USEC 100 | |
250 | ||
6a20c175 | 251 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
252 | * by Marvell switches when a specific hardware mode is enabled (not |
253 | * supported by this driver) or is filled automatically by zeroes on | |
254 | * the RX side. Those two bytes being at the front of the Ethernet | |
255 | * header, they allow to have the IP header aligned on a 4 bytes | |
256 | * boundary automatically: the hardware skips those two bytes on its | |
257 | * own. | |
258 | */ | |
259 | #define MVNETA_MH_SIZE 2 | |
260 | ||
261 | #define MVNETA_VLAN_TAG_LEN 4 | |
262 | ||
9110ee07 | 263 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 | 264 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
dc35a10f MW |
265 | #define MVNETA_ACC_MODE_EXT1 1 |
266 | #define MVNETA_ACC_MODE_EXT2 2 | |
267 | ||
268 | #define MVNETA_MAX_DECODE_WIN 6 | |
c5aff182 TP |
269 | |
270 | /* Timeout constants */ | |
271 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
272 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
273 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
274 | ||
275 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
276 | ||
9a401dea GC |
277 | /* The RSS lookup table actually has 256 entries but we do not use |
278 | * them yet | |
279 | */ | |
280 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
281 | ||
2adb719d EG |
282 | /* TSO header size */ |
283 | #define TSO_HEADER_SIZE 128 | |
284 | ||
c5aff182 TP |
285 | /* Max number of Rx descriptors */ |
286 | #define MVNETA_MAX_RXD 128 | |
287 | ||
288 | /* Max number of Tx descriptors */ | |
289 | #define MVNETA_MAX_TXD 532 | |
290 | ||
8eef5f97 EG |
291 | /* Max number of allowed TCP segments for software TSO */ |
292 | #define MVNETA_MAX_TSO_SEGS 100 | |
293 | ||
294 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
295 | ||
c5aff182 TP |
296 | /* descriptor aligned size */ |
297 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
298 | ||
299 | #define MVNETA_RX_PKT_SIZE(mtu) \ | |
300 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
301 | ETH_HLEN + ETH_FCS_LEN, \ | |
c66e98c9 | 302 | cache_line_size()) |
c5aff182 | 303 | |
2e3173a3 EG |
304 | #define IS_TSO_HEADER(txq, addr) \ |
305 | ((addr >= txq->tso_hdrs_phys) && \ | |
306 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
307 | ||
dc35a10f MW |
308 | #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ |
309 | (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) | |
c5aff182 | 310 | |
9b0cdefa RK |
311 | struct mvneta_statistic { |
312 | unsigned short offset; | |
313 | unsigned short type; | |
314 | const char name[ETH_GSTRING_LEN]; | |
315 | }; | |
316 | ||
317 | #define T_REG_32 32 | |
318 | #define T_REG_64 64 | |
319 | ||
320 | static const struct mvneta_statistic mvneta_statistics[] = { | |
321 | { 0x3000, T_REG_64, "good_octets_received", }, | |
322 | { 0x3010, T_REG_32, "good_frames_received", }, | |
323 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
324 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
325 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
326 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
327 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
328 | { 0x3058, T_REG_32, "good_fc_received", }, | |
329 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
330 | { 0x3060, T_REG_32, "undersize_received", }, | |
331 | { 0x3064, T_REG_32, "fragments_received", }, | |
332 | { 0x3068, T_REG_32, "oversize_received", }, | |
333 | { 0x306c, T_REG_32, "jabber_received", }, | |
334 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
335 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
336 | { 0x3078, T_REG_32, "collision", }, | |
337 | { 0x307c, T_REG_32, "late_collision", }, | |
338 | { 0x2484, T_REG_32, "rx_discard", }, | |
339 | { 0x2488, T_REG_32, "rx_overrun", }, | |
340 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
341 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
342 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
343 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
344 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
345 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
346 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
347 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
348 | { 0x3044, T_REG_32, "excessive_collision", }, | |
349 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
350 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
351 | { 0x3054, T_REG_32, "fc_sent", }, | |
352 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
353 | }; | |
354 | ||
74c41b04 | 355 | struct mvneta_pcpu_stats { |
c5aff182 | 356 | struct u64_stats_sync syncp; |
74c41b04 | 357 | u64 rx_packets; |
358 | u64 rx_bytes; | |
359 | u64 tx_packets; | |
360 | u64 tx_bytes; | |
c5aff182 TP |
361 | }; |
362 | ||
12bb03b4 MR |
363 | struct mvneta_pcpu_port { |
364 | /* Pointer to the shared port */ | |
365 | struct mvneta_port *pp; | |
366 | ||
367 | /* Pointer to the CPU-local NAPI struct */ | |
368 | struct napi_struct napi; | |
369 | ||
370 | /* Cause of the previous interrupt */ | |
371 | u32 cause_rx_tx; | |
372 | }; | |
373 | ||
c5aff182 | 374 | struct mvneta_port { |
dc35a10f | 375 | u8 id; |
12bb03b4 MR |
376 | struct mvneta_pcpu_port __percpu *ports; |
377 | struct mvneta_pcpu_stats __percpu *stats; | |
378 | ||
c5aff182 | 379 | int pkt_size; |
8ec2cd48 | 380 | unsigned int frag_size; |
c5aff182 TP |
381 | void __iomem *base; |
382 | struct mvneta_rx_queue *rxqs; | |
383 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 384 | struct net_device *dev; |
f8642885 | 385 | struct notifier_block cpu_notifier; |
90b74c01 | 386 | int rxq_def; |
5888511e GC |
387 | /* Protect the access to the percpu interrupt registers, |
388 | * ensuring that the configuration remains coherent. | |
389 | */ | |
390 | spinlock_t lock; | |
120cfa50 | 391 | bool is_stopped; |
c5aff182 | 392 | |
c5aff182 | 393 | /* Core clock */ |
189dd626 | 394 | struct clk *clk; |
15cc4a4a JZ |
395 | /* AXI clock */ |
396 | struct clk *clk_bus; | |
c5aff182 TP |
397 | u8 mcast_count[256]; |
398 | u16 tx_ring_size; | |
399 | u16 rx_ring_size; | |
c5aff182 TP |
400 | |
401 | struct mii_bus *mii_bus; | |
c5aff182 TP |
402 | phy_interface_t phy_interface; |
403 | struct device_node *phy_node; | |
404 | unsigned int link; | |
405 | unsigned int duplex; | |
406 | unsigned int speed; | |
b65657fc | 407 | unsigned int tx_csum_limit; |
0c0744fc | 408 | unsigned int use_inband_status:1; |
9b0cdefa | 409 | |
dc35a10f MW |
410 | struct mvneta_bm *bm_priv; |
411 | struct mvneta_bm_pool *pool_long; | |
412 | struct mvneta_bm_pool *pool_short; | |
413 | int bm_win_id; | |
414 | ||
9b0cdefa | 415 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; |
9a401dea GC |
416 | |
417 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
c5aff182 TP |
418 | }; |
419 | ||
6a20c175 | 420 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
421 | * layout of the transmit and reception DMA descriptors, and their |
422 | * layout is therefore defined by the hardware design | |
423 | */ | |
6083ed44 | 424 | |
c5aff182 TP |
425 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
426 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
427 | #define MVNETA_TX_L4_UDP BIT(16) | |
428 | #define MVNETA_TX_L3_IP6 BIT(17) | |
429 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
430 | #define MVNETA_TXD_Z_PAD BIT(19) | |
431 | #define MVNETA_TXD_L_DESC BIT(20) | |
432 | #define MVNETA_TXD_F_DESC BIT(21) | |
433 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
434 | MVNETA_TXD_L_DESC | \ | |
435 | MVNETA_TXD_F_DESC) | |
436 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
437 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
438 | ||
c5aff182 | 439 | #define MVNETA_RXD_ERR_CRC 0x0 |
dc35a10f MW |
440 | #define MVNETA_RXD_BM_POOL_SHIFT 13 |
441 | #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) | |
c5aff182 TP |
442 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) |
443 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
444 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
445 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
446 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
447 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
448 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
449 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
450 | ||
9ad8fef6 | 451 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
452 | struct mvneta_tx_desc { |
453 | u32 command; /* Options used by HW for packet transmitting.*/ | |
454 | u16 reserverd1; /* csum_l4 (for future use) */ | |
455 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
456 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
457 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
458 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
459 | }; | |
460 | ||
461 | struct mvneta_rx_desc { | |
462 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
463 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
464 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 465 | |
c5aff182 TP |
466 | u32 buf_phys_addr; /* Physical address of the buffer */ |
467 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 468 | |
c5aff182 TP |
469 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
470 | u16 reserved3; /* prefetch_cmd, for future use */ | |
471 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 472 | |
c5aff182 TP |
473 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
474 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
475 | }; | |
9ad8fef6 TP |
476 | #else |
477 | struct mvneta_tx_desc { | |
478 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
479 | u16 reserverd1; /* csum_l4 (for future use) */ | |
480 | u32 command; /* Options used by HW for packet transmitting.*/ | |
481 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
482 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
483 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
484 | }; | |
485 | ||
486 | struct mvneta_rx_desc { | |
487 | u16 data_size; /* Size of received packet in bytes */ | |
488 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
489 | u32 status; /* Info about received packet */ | |
490 | ||
491 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
492 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
493 | ||
494 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
495 | u16 reserved3; /* prefetch_cmd, for future use */ | |
496 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
497 | ||
498 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
499 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
500 | }; | |
501 | #endif | |
c5aff182 TP |
502 | |
503 | struct mvneta_tx_queue { | |
504 | /* Number of this TX queue, in the range 0-7 */ | |
505 | u8 id; | |
506 | ||
507 | /* Number of TX DMA descriptors in the descriptor ring */ | |
508 | int size; | |
509 | ||
510 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
511 | * descriptor ring |
512 | */ | |
c5aff182 | 513 | int count; |
8eef5f97 EG |
514 | int tx_stop_threshold; |
515 | int tx_wake_threshold; | |
c5aff182 TP |
516 | |
517 | /* Array of transmitted skb */ | |
518 | struct sk_buff **tx_skb; | |
519 | ||
520 | /* Index of last TX DMA descriptor that was inserted */ | |
521 | int txq_put_index; | |
522 | ||
523 | /* Index of the TX DMA descriptor to be cleaned up */ | |
524 | int txq_get_index; | |
525 | ||
526 | u32 done_pkts_coal; | |
527 | ||
528 | /* Virtual address of the TX DMA descriptors array */ | |
529 | struct mvneta_tx_desc *descs; | |
530 | ||
531 | /* DMA address of the TX DMA descriptors array */ | |
532 | dma_addr_t descs_phys; | |
533 | ||
534 | /* Index of the last TX DMA descriptor */ | |
535 | int last_desc; | |
536 | ||
537 | /* Index of the next TX DMA descriptor to process */ | |
538 | int next_desc_to_proc; | |
2adb719d EG |
539 | |
540 | /* DMA buffers for TSO headers */ | |
541 | char *tso_hdrs; | |
542 | ||
543 | /* DMA address of TSO headers */ | |
544 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
545 | |
546 | /* Affinity mask for CPUs*/ | |
547 | cpumask_t affinity_mask; | |
c5aff182 TP |
548 | }; |
549 | ||
550 | struct mvneta_rx_queue { | |
551 | /* rx queue number, in the range 0-7 */ | |
552 | u8 id; | |
553 | ||
554 | /* num of rx descriptors in the rx descriptor ring */ | |
555 | int size; | |
556 | ||
557 | /* counter of times when mvneta_refill() failed */ | |
558 | int missed; | |
559 | ||
560 | u32 pkts_coal; | |
561 | u32 time_coal; | |
562 | ||
563 | /* Virtual address of the RX DMA descriptors array */ | |
564 | struct mvneta_rx_desc *descs; | |
565 | ||
566 | /* DMA address of the RX DMA descriptors array */ | |
567 | dma_addr_t descs_phys; | |
568 | ||
569 | /* Index of the last RX DMA descriptor */ | |
570 | int last_desc; | |
571 | ||
572 | /* Index of the next RX DMA descriptor to process */ | |
573 | int next_desc_to_proc; | |
574 | }; | |
575 | ||
edadb7fa EG |
576 | /* The hardware supports eight (8) rx queues, but we are only allowing |
577 | * the first one to be used. Therefore, let's just allocate one queue. | |
578 | */ | |
d8936657 | 579 | static int rxq_number = 8; |
c5aff182 TP |
580 | static int txq_number = 8; |
581 | ||
582 | static int rxq_def; | |
c5aff182 | 583 | |
f19fadfc | 584 | static int rx_copybreak __read_mostly = 256; |
585 | ||
dc35a10f MW |
586 | /* HW BM need that each port be identify by a unique ID */ |
587 | static int global_port_id; | |
588 | ||
c5aff182 TP |
589 | #define MVNETA_DRIVER_NAME "mvneta" |
590 | #define MVNETA_DRIVER_VERSION "1.0" | |
591 | ||
592 | /* Utility/helper methods */ | |
593 | ||
594 | /* Write helper method */ | |
595 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
596 | { | |
597 | writel(data, pp->base + offset); | |
598 | } | |
599 | ||
600 | /* Read helper method */ | |
601 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
602 | { | |
603 | return readl(pp->base + offset); | |
604 | } | |
605 | ||
606 | /* Increment txq get counter */ | |
607 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
608 | { | |
609 | txq->txq_get_index++; | |
610 | if (txq->txq_get_index == txq->size) | |
611 | txq->txq_get_index = 0; | |
612 | } | |
613 | ||
614 | /* Increment txq put counter */ | |
615 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
616 | { | |
617 | txq->txq_put_index++; | |
618 | if (txq->txq_put_index == txq->size) | |
619 | txq->txq_put_index = 0; | |
620 | } | |
621 | ||
622 | ||
623 | /* Clear all MIB counters */ | |
624 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
625 | { | |
626 | int i; | |
627 | u32 dummy; | |
628 | ||
629 | /* Perform dummy reads from MIB counters */ | |
630 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
631 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
e483911f AL |
632 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
633 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
634 | } |
635 | ||
636 | /* Get System Network Statistics */ | |
637 | struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, | |
638 | struct rtnl_link_stats64 *stats) | |
639 | { | |
640 | struct mvneta_port *pp = netdev_priv(dev); | |
641 | unsigned int start; | |
74c41b04 | 642 | int cpu; |
c5aff182 | 643 | |
74c41b04 | 644 | for_each_possible_cpu(cpu) { |
645 | struct mvneta_pcpu_stats *cpu_stats; | |
646 | u64 rx_packets; | |
647 | u64 rx_bytes; | |
648 | u64 tx_packets; | |
649 | u64 tx_bytes; | |
c5aff182 | 650 | |
74c41b04 | 651 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
652 | do { | |
57a7744e | 653 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 654 | rx_packets = cpu_stats->rx_packets; |
655 | rx_bytes = cpu_stats->rx_bytes; | |
656 | tx_packets = cpu_stats->tx_packets; | |
657 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 658 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 659 | |
74c41b04 | 660 | stats->rx_packets += rx_packets; |
661 | stats->rx_bytes += rx_bytes; | |
662 | stats->tx_packets += tx_packets; | |
663 | stats->tx_bytes += tx_bytes; | |
664 | } | |
c5aff182 TP |
665 | |
666 | stats->rx_errors = dev->stats.rx_errors; | |
667 | stats->rx_dropped = dev->stats.rx_dropped; | |
668 | ||
669 | stats->tx_dropped = dev->stats.tx_dropped; | |
670 | ||
671 | return stats; | |
672 | } | |
673 | ||
674 | /* Rx descriptors helper methods */ | |
675 | ||
5428213c | 676 | /* Checks whether the RX descriptor having this status is both the first |
677 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
678 | * received through a single RX descriptor, so not having each RX |
679 | * descriptor with its first and last bits set is an error | |
680 | */ | |
5428213c | 681 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 682 | { |
5428213c | 683 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
684 | MVNETA_RXD_FIRST_LAST_DESC; |
685 | } | |
686 | ||
687 | /* Add number of descriptors ready to receive new packets */ | |
688 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
689 | struct mvneta_rx_queue *rxq, | |
690 | int ndescs) | |
691 | { | |
692 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
693 | * be added at once |
694 | */ | |
c5aff182 TP |
695 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
696 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
697 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
698 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
699 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
700 | } | |
701 | ||
702 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
703 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
704 | } | |
705 | ||
706 | /* Get number of RX descriptors occupied by received packets */ | |
707 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
708 | struct mvneta_rx_queue *rxq) | |
709 | { | |
710 | u32 val; | |
711 | ||
712 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
713 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
714 | } | |
715 | ||
6a20c175 | 716 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
717 | * from mvneta_rxq_drop_pkts(). |
718 | */ | |
719 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
720 | struct mvneta_rx_queue *rxq, | |
721 | int rx_done, int rx_filled) | |
722 | { | |
723 | u32 val; | |
724 | ||
725 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
726 | val = rx_done | | |
727 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
728 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
729 | return; | |
730 | } | |
731 | ||
732 | /* Only 255 descriptors can be added at once */ | |
733 | while ((rx_done > 0) || (rx_filled > 0)) { | |
734 | if (rx_done <= 0xff) { | |
735 | val = rx_done; | |
736 | rx_done = 0; | |
737 | } else { | |
738 | val = 0xff; | |
739 | rx_done -= 0xff; | |
740 | } | |
741 | if (rx_filled <= 0xff) { | |
742 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
743 | rx_filled = 0; | |
744 | } else { | |
745 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
746 | rx_filled -= 0xff; | |
747 | } | |
748 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
749 | } | |
750 | } | |
751 | ||
752 | /* Get pointer to next RX descriptor to be processed by SW */ | |
753 | static struct mvneta_rx_desc * | |
754 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
755 | { | |
756 | int rx_desc = rxq->next_desc_to_proc; | |
757 | ||
758 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 759 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
760 | return rxq->descs + rx_desc; |
761 | } | |
762 | ||
763 | /* Change maximum receive size of the port. */ | |
764 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
765 | { | |
766 | u32 val; | |
767 | ||
768 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
769 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
770 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
771 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
772 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
773 | } | |
774 | ||
775 | ||
776 | /* Set rx queue offset */ | |
777 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
778 | struct mvneta_rx_queue *rxq, | |
779 | int offset) | |
780 | { | |
781 | u32 val; | |
782 | ||
783 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
784 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
785 | ||
786 | /* Offset is in */ | |
787 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
788 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
789 | } | |
790 | ||
791 | ||
792 | /* Tx descriptors helper methods */ | |
793 | ||
794 | /* Update HW with number of TX descriptors to be sent */ | |
795 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
796 | struct mvneta_tx_queue *txq, | |
797 | int pend_desc) | |
798 | { | |
799 | u32 val; | |
800 | ||
801 | /* Only 255 descriptors can be added at once ; Assume caller | |
6a20c175 TP |
802 | * process TX desriptors in quanta less than 256 |
803 | */ | |
c5aff182 TP |
804 | val = pend_desc; |
805 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
806 | } | |
807 | ||
808 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
809 | static struct mvneta_tx_desc * | |
810 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
811 | { | |
812 | int tx_desc = txq->next_desc_to_proc; | |
813 | ||
814 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
815 | return txq->descs + tx_desc; | |
816 | } | |
817 | ||
818 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
819 | * mapping failures in the TX path. |
820 | */ | |
c5aff182 TP |
821 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
822 | { | |
823 | if (txq->next_desc_to_proc == 0) | |
824 | txq->next_desc_to_proc = txq->last_desc - 1; | |
825 | else | |
826 | txq->next_desc_to_proc--; | |
827 | } | |
828 | ||
829 | /* Set rxq buf size */ | |
830 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
831 | struct mvneta_rx_queue *rxq, | |
832 | int buf_size) | |
833 | { | |
834 | u32 val; | |
835 | ||
836 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
837 | ||
838 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
839 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
840 | ||
841 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
842 | } | |
843 | ||
844 | /* Disable buffer management (BM) */ | |
845 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
846 | struct mvneta_rx_queue *rxq) | |
847 | { | |
848 | u32 val; | |
849 | ||
850 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
851 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
852 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
853 | } | |
854 | ||
dc35a10f MW |
855 | /* Enable buffer management (BM) */ |
856 | static void mvneta_rxq_bm_enable(struct mvneta_port *pp, | |
857 | struct mvneta_rx_queue *rxq) | |
858 | { | |
859 | u32 val; | |
860 | ||
861 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
862 | val |= MVNETA_RXQ_HW_BUF_ALLOC; | |
863 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
864 | } | |
865 | ||
866 | /* Notify HW about port's assignment of pool for bigger packets */ | |
867 | static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, | |
868 | struct mvneta_rx_queue *rxq) | |
869 | { | |
870 | u32 val; | |
871 | ||
872 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
873 | val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; | |
874 | val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); | |
875 | ||
876 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
877 | } | |
878 | ||
879 | /* Notify HW about port's assignment of pool for smaller packets */ | |
880 | static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, | |
881 | struct mvneta_rx_queue *rxq) | |
882 | { | |
883 | u32 val; | |
884 | ||
885 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
886 | val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; | |
887 | val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); | |
888 | ||
889 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
890 | } | |
891 | ||
892 | /* Set port's receive buffer size for assigned BM pool */ | |
893 | static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, | |
894 | int buf_size, | |
895 | u8 pool_id) | |
896 | { | |
897 | u32 val; | |
898 | ||
899 | if (!IS_ALIGNED(buf_size, 8)) { | |
900 | dev_warn(pp->dev->dev.parent, | |
901 | "illegal buf_size value %d, round to %d\n", | |
902 | buf_size, ALIGN(buf_size, 8)); | |
903 | buf_size = ALIGN(buf_size, 8); | |
904 | } | |
905 | ||
906 | val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); | |
907 | val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; | |
908 | mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); | |
909 | } | |
910 | ||
911 | /* Configure MBUS window in order to enable access BM internal SRAM */ | |
912 | static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, | |
913 | u8 target, u8 attr) | |
914 | { | |
915 | u32 win_enable, win_protect; | |
916 | int i; | |
917 | ||
918 | win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); | |
919 | ||
920 | if (pp->bm_win_id < 0) { | |
921 | /* Find first not occupied window */ | |
922 | for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { | |
923 | if (win_enable & (1 << i)) { | |
924 | pp->bm_win_id = i; | |
925 | break; | |
926 | } | |
927 | } | |
928 | if (i == MVNETA_MAX_DECODE_WIN) | |
929 | return -ENOMEM; | |
930 | } else { | |
931 | i = pp->bm_win_id; | |
932 | } | |
933 | ||
934 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
935 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
936 | ||
937 | if (i < 4) | |
938 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
939 | ||
940 | mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | | |
941 | (attr << 8) | target); | |
942 | ||
943 | mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); | |
944 | ||
945 | win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); | |
946 | win_protect |= 3 << (2 * i); | |
947 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); | |
948 | ||
949 | win_enable &= ~(1 << i); | |
950 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | /* Assign and initialize pools for port. In case of fail | |
956 | * buffer manager will remain disabled for current port. | |
957 | */ | |
958 | static int mvneta_bm_port_init(struct platform_device *pdev, | |
959 | struct mvneta_port *pp) | |
960 | { | |
961 | struct device_node *dn = pdev->dev.of_node; | |
962 | u32 long_pool_id, short_pool_id, wsize; | |
963 | u8 target, attr; | |
964 | int err; | |
965 | ||
966 | /* Get BM window information */ | |
967 | err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, | |
968 | &target, &attr); | |
969 | if (err < 0) | |
970 | return err; | |
971 | ||
972 | pp->bm_win_id = -1; | |
973 | ||
974 | /* Open NETA -> BM window */ | |
975 | err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, | |
976 | target, attr); | |
977 | if (err < 0) { | |
978 | netdev_info(pp->dev, "fail to configure mbus window to BM\n"); | |
979 | return err; | |
980 | } | |
981 | ||
982 | if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { | |
983 | netdev_info(pp->dev, "missing long pool id\n"); | |
984 | return -EINVAL; | |
985 | } | |
986 | ||
987 | /* Create port's long pool depending on mtu */ | |
988 | pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, | |
989 | MVNETA_BM_LONG, pp->id, | |
990 | MVNETA_RX_PKT_SIZE(pp->dev->mtu)); | |
991 | if (!pp->pool_long) { | |
992 | netdev_info(pp->dev, "fail to obtain long pool for port\n"); | |
993 | return -ENOMEM; | |
994 | } | |
995 | ||
996 | pp->pool_long->port_map |= 1 << pp->id; | |
997 | ||
998 | mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, | |
999 | pp->pool_long->id); | |
1000 | ||
1001 | /* If short pool id is not defined, assume using single pool */ | |
1002 | if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) | |
1003 | short_pool_id = long_pool_id; | |
1004 | ||
1005 | /* Create port's short pool */ | |
1006 | pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, | |
1007 | MVNETA_BM_SHORT, pp->id, | |
1008 | MVNETA_BM_SHORT_PKT_SIZE); | |
1009 | if (!pp->pool_short) { | |
1010 | netdev_info(pp->dev, "fail to obtain short pool for port\n"); | |
1011 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1012 | return -ENOMEM; | |
1013 | } | |
1014 | ||
1015 | if (short_pool_id != long_pool_id) { | |
1016 | pp->pool_short->port_map |= 1 << pp->id; | |
1017 | mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, | |
1018 | pp->pool_short->id); | |
1019 | } | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | /* Update settings of a pool for bigger packets */ | |
1025 | static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) | |
1026 | { | |
1027 | struct mvneta_bm_pool *bm_pool = pp->pool_long; | |
baa11ebc | 1028 | struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; |
dc35a10f MW |
1029 | int num; |
1030 | ||
1031 | /* Release all buffers from long pool */ | |
1032 | mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); | |
baa11ebc | 1033 | if (hwbm_pool->buf_num) { |
dc35a10f MW |
1034 | WARN(1, "cannot free all buffers in pool %d\n", |
1035 | bm_pool->id); | |
1036 | goto bm_mtu_err; | |
1037 | } | |
1038 | ||
1039 | bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); | |
1040 | bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); | |
baa11ebc GC |
1041 | hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + |
1042 | SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); | |
dc35a10f MW |
1043 | |
1044 | /* Fill entire long pool */ | |
baa11ebc GC |
1045 | num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC); |
1046 | if (num != hwbm_pool->size) { | |
dc35a10f | 1047 | WARN(1, "pool %d: %d of %d allocated\n", |
baa11ebc | 1048 | bm_pool->id, num, hwbm_pool->size); |
dc35a10f MW |
1049 | goto bm_mtu_err; |
1050 | } | |
1051 | mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); | |
1052 | ||
1053 | return; | |
1054 | ||
1055 | bm_mtu_err: | |
1056 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
1057 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); | |
1058 | ||
1059 | pp->bm_priv = NULL; | |
1060 | mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); | |
1061 | netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); | |
1062 | } | |
1063 | ||
c5aff182 TP |
1064 | /* Start the Ethernet port RX and TX activity */ |
1065 | static void mvneta_port_up(struct mvneta_port *pp) | |
1066 | { | |
1067 | int queue; | |
1068 | u32 q_map; | |
1069 | ||
1070 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
1071 | q_map = 0; |
1072 | for (queue = 0; queue < txq_number; queue++) { | |
1073 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
1074 | if (txq->descs != NULL) | |
1075 | q_map |= (1 << queue); | |
1076 | } | |
1077 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
1078 | ||
1079 | /* Enable all initialized RXQs. */ | |
2dcf75e2 GC |
1080 | for (queue = 0; queue < rxq_number; queue++) { |
1081 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1082 | ||
1083 | if (rxq->descs != NULL) | |
1084 | q_map |= (1 << queue); | |
1085 | } | |
1086 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
1087 | } |
1088 | ||
1089 | /* Stop the Ethernet port activity */ | |
1090 | static void mvneta_port_down(struct mvneta_port *pp) | |
1091 | { | |
1092 | u32 val; | |
1093 | int count; | |
1094 | ||
1095 | /* Stop Rx port activity. Check port Rx activity. */ | |
1096 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
1097 | ||
1098 | /* Issue stop command for active channels only */ | |
1099 | if (val != 0) | |
1100 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
1101 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
1102 | ||
1103 | /* Wait for all Rx activity to terminate. */ | |
1104 | count = 0; | |
1105 | do { | |
1106 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
1107 | netdev_warn(pp->dev, | |
0838abb3 | 1108 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", |
c5aff182 TP |
1109 | val); |
1110 | break; | |
1111 | } | |
1112 | mdelay(1); | |
1113 | ||
1114 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
a3703fb3 | 1115 | } while (val & MVNETA_RXQ_ENABLE_MASK); |
c5aff182 TP |
1116 | |
1117 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
1118 | * command for active channels only |
1119 | */ | |
c5aff182 TP |
1120 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
1121 | ||
1122 | if (val != 0) | |
1123 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
1124 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
1125 | ||
1126 | /* Wait for all Tx activity to terminate. */ | |
1127 | count = 0; | |
1128 | do { | |
1129 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
1130 | netdev_warn(pp->dev, | |
1131 | "TIMEOUT for TX stopped status=0x%08x\n", | |
1132 | val); | |
1133 | break; | |
1134 | } | |
1135 | mdelay(1); | |
1136 | ||
1137 | /* Check TX Command reg that all Txqs are stopped */ | |
1138 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
1139 | ||
a3703fb3 | 1140 | } while (val & MVNETA_TXQ_ENABLE_MASK); |
c5aff182 TP |
1141 | |
1142 | /* Double check to verify that TX FIFO is empty */ | |
1143 | count = 0; | |
1144 | do { | |
1145 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
1146 | netdev_warn(pp->dev, | |
0838abb3 | 1147 | "TX FIFO empty timeout status=0x%08x\n", |
c5aff182 TP |
1148 | val); |
1149 | break; | |
1150 | } | |
1151 | mdelay(1); | |
1152 | ||
1153 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
1154 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
1155 | (val & MVNETA_TX_IN_PRGRS)); | |
1156 | ||
1157 | udelay(200); | |
1158 | } | |
1159 | ||
1160 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
1161 | static void mvneta_port_enable(struct mvneta_port *pp) | |
1162 | { | |
1163 | u32 val; | |
1164 | ||
1165 | /* Enable port */ | |
1166 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1167 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
1168 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1169 | } | |
1170 | ||
1171 | /* Disable the port and wait for about 200 usec before retuning */ | |
1172 | static void mvneta_port_disable(struct mvneta_port *pp) | |
1173 | { | |
1174 | u32 val; | |
1175 | ||
1176 | /* Reset the Enable bit in the Serial Control Register */ | |
1177 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
1178 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
1179 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
1180 | ||
1181 | udelay(200); | |
1182 | } | |
1183 | ||
1184 | /* Multicast tables methods */ | |
1185 | ||
1186 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
1187 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
1188 | { | |
1189 | int offset; | |
1190 | u32 val; | |
1191 | ||
1192 | if (queue == -1) { | |
1193 | val = 0; | |
1194 | } else { | |
1195 | val = 0x1 | (queue << 1); | |
1196 | val |= (val << 24) | (val << 16) | (val << 8); | |
1197 | } | |
1198 | ||
1199 | for (offset = 0; offset <= 0xc; offset += 4) | |
1200 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
1201 | } | |
1202 | ||
1203 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
1204 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
1205 | { | |
1206 | int offset; | |
1207 | u32 val; | |
1208 | ||
1209 | if (queue == -1) { | |
1210 | val = 0; | |
1211 | } else { | |
1212 | val = 0x1 | (queue << 1); | |
1213 | val |= (val << 24) | (val << 16) | (val << 8); | |
1214 | } | |
1215 | ||
1216 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1217 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
1218 | ||
1219 | } | |
1220 | ||
1221 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
1222 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
1223 | { | |
1224 | int offset; | |
1225 | u32 val; | |
1226 | ||
1227 | if (queue == -1) { | |
1228 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
1229 | val = 0; | |
1230 | } else { | |
1231 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
1232 | val = 0x1 | (queue << 1); | |
1233 | val |= (val << 24) | (val << 16) | (val << 8); | |
1234 | } | |
1235 | ||
1236 | for (offset = 0; offset <= 0xfc; offset += 4) | |
1237 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
1238 | } | |
1239 | ||
0c0744fc SS |
1240 | static void mvneta_set_autoneg(struct mvneta_port *pp, int enable) |
1241 | { | |
1242 | u32 val; | |
1243 | ||
1244 | if (enable) { | |
1245 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1246 | val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | | |
1247 | MVNETA_GMAC_FORCE_LINK_DOWN | | |
1248 | MVNETA_GMAC_AN_FLOW_CTRL_EN); | |
1249 | val |= MVNETA_GMAC_INBAND_AN_ENABLE | | |
1250 | MVNETA_GMAC_AN_SPEED_EN | | |
1251 | MVNETA_GMAC_AN_DUPLEX_EN; | |
1252 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1253 | ||
1254 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1255 | val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1256 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1257 | ||
1258 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1259 | val |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1260 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1261 | } else { | |
1262 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1263 | val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
1264 | MVNETA_GMAC_AN_SPEED_EN | | |
1265 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1266 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1267 | ||
1268 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1269 | val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1270 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1271 | ||
1272 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1273 | val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1274 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1275 | } | |
1276 | } | |
1277 | ||
db488c10 GC |
1278 | static void mvneta_percpu_unmask_interrupt(void *arg) |
1279 | { | |
1280 | struct mvneta_port *pp = arg; | |
1281 | ||
1282 | /* All the queue are unmasked, but actually only the ones | |
1283 | * mapped to this CPU will be unmasked | |
1284 | */ | |
1285 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
1286 | MVNETA_RX_INTR_MASK_ALL | | |
1287 | MVNETA_TX_INTR_MASK_ALL | | |
1288 | MVNETA_MISCINTR_INTR_MASK); | |
1289 | } | |
1290 | ||
1291 | static void mvneta_percpu_mask_interrupt(void *arg) | |
1292 | { | |
1293 | struct mvneta_port *pp = arg; | |
1294 | ||
1295 | /* All the queue are masked, but actually only the ones | |
1296 | * mapped to this CPU will be masked | |
1297 | */ | |
1298 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1299 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1300 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1301 | } | |
1302 | ||
1303 | static void mvneta_percpu_clear_intr_cause(void *arg) | |
1304 | { | |
1305 | struct mvneta_port *pp = arg; | |
1306 | ||
1307 | /* All the queue are cleared, but actually only the ones | |
1308 | * mapped to this CPU will be cleared | |
1309 | */ | |
1310 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1311 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1312 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1313 | } | |
1314 | ||
c5aff182 TP |
1315 | /* This method sets defaults to the NETA port: |
1316 | * Clears interrupt Cause and Mask registers. | |
1317 | * Clears all MAC tables. | |
1318 | * Sets defaults to all registers. | |
1319 | * Resets RX and TX descriptor rings. | |
1320 | * Resets PHY. | |
1321 | * This method can be called after mvneta_port_down() to return the port | |
1322 | * settings to defaults. | |
1323 | */ | |
1324 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1325 | { | |
1326 | int cpu; | |
1327 | int queue; | |
1328 | u32 val; | |
2dcf75e2 | 1329 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1330 | |
1331 | /* Clear all Cause registers */ | |
db488c10 | 1332 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
1333 | |
1334 | /* Mask all interrupts */ | |
db488c10 | 1335 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
1336 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); |
1337 | ||
1338 | /* Enable MBUS Retry bit16 */ | |
1339 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1340 | ||
50bf8cb6 GC |
1341 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1342 | * TX queues modulo their number. If there is only one TX | |
1343 | * queue then it is assigned to the CPU associated to the | |
1344 | * default RX queue. | |
6a20c175 | 1345 | */ |
2dcf75e2 GC |
1346 | for_each_present_cpu(cpu) { |
1347 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1348 | int rxq, txq; |
2dcf75e2 GC |
1349 | |
1350 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1351 | if ((rxq % max_cpu) == cpu) | |
1352 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1353 | ||
50bf8cb6 GC |
1354 | for (txq = 0; txq < txq_number; txq++) |
1355 | if ((txq % max_cpu) == cpu) | |
1356 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1357 | ||
1358 | /* With only one TX queue we configure a special case | |
1359 | * which will allow to get all the irq on a single | |
1360 | * CPU | |
1361 | */ | |
1362 | if (txq_number == 1) | |
1363 | txq_map = (cpu == pp->rxq_def) ? | |
1364 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 GC |
1365 | |
1366 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1367 | } | |
c5aff182 TP |
1368 | |
1369 | /* Reset RX and TX DMAs */ | |
1370 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1371 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1372 | ||
1373 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1374 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1375 | for (queue = 0; queue < txq_number; queue++) { | |
1376 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1377 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1378 | } | |
1379 | ||
1380 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1381 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1382 | ||
1383 | /* Set Port Acceleration Mode */ | |
dc35a10f MW |
1384 | if (pp->bm_priv) |
1385 | /* HW buffer management + legacy parser */ | |
1386 | val = MVNETA_ACC_MODE_EXT2; | |
1387 | else | |
1388 | /* SW buffer management + legacy parser */ | |
1389 | val = MVNETA_ACC_MODE_EXT1; | |
c5aff182 TP |
1390 | mvreg_write(pp, MVNETA_ACC_MODE, val); |
1391 | ||
dc35a10f MW |
1392 | if (pp->bm_priv) |
1393 | mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); | |
1394 | ||
c5aff182 | 1395 | /* Update val of portCfg register accordingly with all RxQueue types */ |
90b74c01 | 1396 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1397 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1398 | ||
1399 | val = 0; | |
1400 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1401 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1402 | ||
1403 | /* Build PORT_SDMA_CONFIG_REG */ | |
1404 | val = 0; | |
1405 | ||
1406 | /* Default burst size */ | |
1407 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1408 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1409 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1410 | |
9ad8fef6 TP |
1411 | #if defined(__BIG_ENDIAN) |
1412 | val |= MVNETA_DESC_SWAP; | |
1413 | #endif | |
c5aff182 TP |
1414 | |
1415 | /* Assign port SDMA configuration */ | |
1416 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1417 | ||
71408602 TP |
1418 | /* Disable PHY polling in hardware, since we're using the |
1419 | * kernel phylib to do this. | |
1420 | */ | |
1421 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1422 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1423 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1424 | ||
0c0744fc | 1425 | mvneta_set_autoneg(pp, pp->use_inband_status); |
c5aff182 TP |
1426 | mvneta_set_ucast_table(pp, -1); |
1427 | mvneta_set_special_mcast_table(pp, -1); | |
1428 | mvneta_set_other_mcast_table(pp, -1); | |
1429 | ||
1430 | /* Set port interrupt enable register - default enable all */ | |
1431 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1432 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1433 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1434 | |
1435 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1436 | } |
1437 | ||
1438 | /* Set max sizes for tx queues */ | |
1439 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1440 | ||
1441 | { | |
1442 | u32 val, size, mtu; | |
1443 | int queue; | |
1444 | ||
1445 | mtu = max_tx_size * 8; | |
1446 | if (mtu > MVNETA_TX_MTU_MAX) | |
1447 | mtu = MVNETA_TX_MTU_MAX; | |
1448 | ||
1449 | /* Set MTU */ | |
1450 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1451 | val &= ~MVNETA_TX_MTU_MAX; | |
1452 | val |= mtu; | |
1453 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1454 | ||
1455 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1456 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1457 | ||
1458 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1459 | if (size < mtu) { | |
1460 | size = mtu; | |
1461 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1462 | val |= size; | |
1463 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1464 | } | |
1465 | for (queue = 0; queue < txq_number; queue++) { | |
1466 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1467 | ||
1468 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1469 | if (size < mtu) { | |
1470 | size = mtu; | |
1471 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1472 | val |= size; | |
1473 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1474 | } | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | /* Set unicast address */ | |
1479 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1480 | int queue) | |
1481 | { | |
1482 | unsigned int unicast_reg; | |
1483 | unsigned int tbl_offset; | |
1484 | unsigned int reg_offset; | |
1485 | ||
1486 | /* Locate the Unicast table entry */ | |
1487 | last_nibble = (0xf & last_nibble); | |
1488 | ||
1489 | /* offset from unicast tbl base */ | |
1490 | tbl_offset = (last_nibble / 4) * 4; | |
1491 | ||
1492 | /* offset within the above reg */ | |
1493 | reg_offset = last_nibble % 4; | |
1494 | ||
1495 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1496 | ||
1497 | if (queue == -1) { | |
1498 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1499 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1500 | } else { | |
1501 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1502 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1503 | } | |
1504 | ||
1505 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1506 | } | |
1507 | ||
1508 | /* Set mac address */ | |
1509 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1510 | int queue) | |
1511 | { | |
1512 | unsigned int mac_h; | |
1513 | unsigned int mac_l; | |
1514 | ||
1515 | if (queue != -1) { | |
1516 | mac_l = (addr[4] << 8) | (addr[5]); | |
1517 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1518 | (addr[2] << 8) | (addr[3] << 0); | |
1519 | ||
1520 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1521 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1522 | } | |
1523 | ||
1524 | /* Accept frames of this address */ | |
1525 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1526 | } | |
1527 | ||
6a20c175 TP |
1528 | /* Set the number of packets that will be received before RX interrupt |
1529 | * will be generated by HW. | |
c5aff182 TP |
1530 | */ |
1531 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1532 | struct mvneta_rx_queue *rxq, u32 value) | |
1533 | { | |
1534 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1535 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
1536 | rxq->pkts_coal = value; | |
1537 | } | |
1538 | ||
6a20c175 TP |
1539 | /* Set the time delay in usec before RX interrupt will be generated by |
1540 | * HW. | |
c5aff182 TP |
1541 | */ |
1542 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1543 | struct mvneta_rx_queue *rxq, u32 value) | |
1544 | { | |
189dd626 TP |
1545 | u32 val; |
1546 | unsigned long clk_rate; | |
1547 | ||
1548 | clk_rate = clk_get_rate(pp->clk); | |
1549 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1550 | |
1551 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
1552 | rxq->time_coal = value; | |
1553 | } | |
1554 | ||
1555 | /* Set threshold for TX_DONE pkts coalescing */ | |
1556 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1557 | struct mvneta_tx_queue *txq, u32 value) | |
1558 | { | |
1559 | u32 val; | |
1560 | ||
1561 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1562 | ||
1563 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1564 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1565 | ||
1566 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
1567 | ||
1568 | txq->done_pkts_coal = value; | |
1569 | } | |
1570 | ||
c5aff182 TP |
1571 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1572 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
1573 | u32 phys_addr, u32 cookie) | |
1574 | { | |
1575 | rx_desc->buf_cookie = cookie; | |
1576 | rx_desc->buf_phys_addr = phys_addr; | |
1577 | } | |
1578 | ||
1579 | /* Decrement sent descriptors counter */ | |
1580 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1581 | struct mvneta_tx_queue *txq, | |
1582 | int sent_desc) | |
1583 | { | |
1584 | u32 val; | |
1585 | ||
1586 | /* Only 255 TX descriptors can be updated at once */ | |
1587 | while (sent_desc > 0xff) { | |
1588 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1589 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1590 | sent_desc = sent_desc - 0xff; | |
1591 | } | |
1592 | ||
1593 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1594 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1595 | } | |
1596 | ||
1597 | /* Get number of TX descriptors already sent by HW */ | |
1598 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1599 | struct mvneta_tx_queue *txq) | |
1600 | { | |
1601 | u32 val; | |
1602 | int sent_desc; | |
1603 | ||
1604 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1605 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1606 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1607 | ||
1608 | return sent_desc; | |
1609 | } | |
1610 | ||
6a20c175 | 1611 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1612 | * The number of sent descriptors is returned. |
1613 | */ | |
1614 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1615 | struct mvneta_tx_queue *txq) | |
1616 | { | |
1617 | int sent_desc; | |
1618 | ||
1619 | /* Get number of sent descriptors */ | |
1620 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1621 | ||
1622 | /* Decrement sent descriptors counter */ | |
1623 | if (sent_desc) | |
1624 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1625 | ||
1626 | return sent_desc; | |
1627 | } | |
1628 | ||
1629 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1630 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1631 | int ip_hdr_len, int l4_proto) | |
1632 | { | |
1633 | u32 command; | |
1634 | ||
1635 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1636 | * G_L4_chk, L4_type; required only for checksum |
1637 | * calculation | |
1638 | */ | |
c5aff182 TP |
1639 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1640 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1641 | ||
0a198587 | 1642 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1643 | command |= MVNETA_TXD_IP_CSUM; |
1644 | else | |
1645 | command |= MVNETA_TX_L3_IP6; | |
1646 | ||
1647 | if (l4_proto == IPPROTO_TCP) | |
1648 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1649 | else if (l4_proto == IPPROTO_UDP) | |
1650 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1651 | else | |
1652 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1653 | ||
1654 | return command; | |
1655 | } | |
1656 | ||
1657 | ||
1658 | /* Display more error info */ | |
1659 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1660 | struct mvneta_rx_desc *rx_desc) | |
1661 | { | |
1662 | u32 status = rx_desc->status; | |
1663 | ||
5428213c | 1664 | if (!mvneta_rxq_desc_is_first_last(status)) { |
c5aff182 TP |
1665 | netdev_err(pp->dev, |
1666 | "bad rx status %08x (buffer oversize), size=%d\n", | |
5428213c | 1667 | status, rx_desc->data_size); |
c5aff182 TP |
1668 | return; |
1669 | } | |
1670 | ||
1671 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
1672 | case MVNETA_RXD_ERR_CRC: | |
1673 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1674 | status, rx_desc->data_size); | |
1675 | break; | |
1676 | case MVNETA_RXD_ERR_OVERRUN: | |
1677 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1678 | status, rx_desc->data_size); | |
1679 | break; | |
1680 | case MVNETA_RXD_ERR_LEN: | |
1681 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1682 | status, rx_desc->data_size); | |
1683 | break; | |
1684 | case MVNETA_RXD_ERR_RESOURCE: | |
1685 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1686 | status, rx_desc->data_size); | |
1687 | break; | |
1688 | } | |
1689 | } | |
1690 | ||
5428213c | 1691 | /* Handle RX checksum offload based on the descriptor's status */ |
1692 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1693 | struct sk_buff *skb) |
1694 | { | |
5428213c | 1695 | if ((status & MVNETA_RXD_L3_IP4) && |
1696 | (status & MVNETA_RXD_L4_CSUM_OK)) { | |
c5aff182 TP |
1697 | skb->csum = 0; |
1698 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1699 | return; | |
1700 | } | |
1701 | ||
1702 | skb->ip_summed = CHECKSUM_NONE; | |
1703 | } | |
1704 | ||
6c498974 | 1705 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1706 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1707 | * valid queue for matching the first one found in <cause>. | |
1708 | */ | |
c5aff182 TP |
1709 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1710 | u32 cause) | |
1711 | { | |
1712 | int queue = fls(cause) - 1; | |
1713 | ||
6c498974 | 1714 | return &pp->txqs[queue]; |
c5aff182 TP |
1715 | } |
1716 | ||
1717 | /* Free tx queue skbuffs */ | |
1718 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
1719 | struct mvneta_tx_queue *txq, int num) | |
1720 | { | |
1721 | int i; | |
1722 | ||
1723 | for (i = 0; i < num; i++) { | |
1724 | struct mvneta_tx_desc *tx_desc = txq->descs + | |
1725 | txq->txq_get_index; | |
1726 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; | |
1727 | ||
1728 | mvneta_txq_inc_get(txq); | |
1729 | ||
2e3173a3 EG |
1730 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
1731 | dma_unmap_single(pp->dev->dev.parent, | |
1732 | tx_desc->buf_phys_addr, | |
1733 | tx_desc->data_size, DMA_TO_DEVICE); | |
ba7e46ef EG |
1734 | if (!skb) |
1735 | continue; | |
c5aff182 TP |
1736 | dev_kfree_skb_any(skb); |
1737 | } | |
1738 | } | |
1739 | ||
1740 | /* Handle end of transmission */ | |
cd713199 | 1741 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1742 | struct mvneta_tx_queue *txq) |
1743 | { | |
1744 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1745 | int tx_done; | |
1746 | ||
1747 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1748 | if (!tx_done) |
1749 | return; | |
1750 | ||
c5aff182 TP |
1751 | mvneta_txq_bufs_free(pp, txq, tx_done); |
1752 | ||
1753 | txq->count -= tx_done; | |
1754 | ||
1755 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1756 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1757 | netif_tx_wake_queue(nq); |
1758 | } | |
c5aff182 TP |
1759 | } |
1760 | ||
dc35a10f | 1761 | void *mvneta_frag_alloc(unsigned int frag_size) |
8ec2cd48 | 1762 | { |
dc35a10f MW |
1763 | if (likely(frag_size <= PAGE_SIZE)) |
1764 | return netdev_alloc_frag(frag_size); | |
8ec2cd48 | 1765 | else |
dc35a10f | 1766 | return kmalloc(frag_size, GFP_ATOMIC); |
8ec2cd48 | 1767 | } |
dc35a10f | 1768 | EXPORT_SYMBOL_GPL(mvneta_frag_alloc); |
8ec2cd48 | 1769 | |
dc35a10f | 1770 | void mvneta_frag_free(unsigned int frag_size, void *data) |
8ec2cd48 | 1771 | { |
dc35a10f | 1772 | if (likely(frag_size <= PAGE_SIZE)) |
13dc0d2b | 1773 | skb_free_frag(data); |
8ec2cd48 | 1774 | else |
1775 | kfree(data); | |
1776 | } | |
dc35a10f | 1777 | EXPORT_SYMBOL_GPL(mvneta_frag_free); |
8ec2cd48 | 1778 | |
dc35a10f | 1779 | /* Refill processing for SW buffer management */ |
c5aff182 TP |
1780 | static int mvneta_rx_refill(struct mvneta_port *pp, |
1781 | struct mvneta_rx_desc *rx_desc) | |
1782 | ||
1783 | { | |
1784 | dma_addr_t phys_addr; | |
8ec2cd48 | 1785 | void *data; |
c5aff182 | 1786 | |
dc35a10f | 1787 | data = mvneta_frag_alloc(pp->frag_size); |
8ec2cd48 | 1788 | if (!data) |
c5aff182 TP |
1789 | return -ENOMEM; |
1790 | ||
8ec2cd48 | 1791 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
c5aff182 TP |
1792 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
1793 | DMA_FROM_DEVICE); | |
1794 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { | |
dc35a10f | 1795 | mvneta_frag_free(pp->frag_size, data); |
c5aff182 TP |
1796 | return -ENOMEM; |
1797 | } | |
1798 | ||
8ec2cd48 | 1799 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); |
c5aff182 TP |
1800 | return 0; |
1801 | } | |
1802 | ||
1803 | /* Handle tx checksum */ | |
1804 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1805 | { | |
1806 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1807 | int ip_hdr_len = 0; | |
817dbfa5 | 1808 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1809 | u8 l4_proto; |
1810 | ||
817dbfa5 | 1811 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1812 | struct iphdr *ip4h = ip_hdr(skb); |
1813 | ||
1814 | /* Calculate IPv4 checksum and L4 checksum */ | |
1815 | ip_hdr_len = ip4h->ihl; | |
1816 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1817 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1818 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1819 | ||
1820 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1821 | if (skb_network_header_len(skb) > 0) | |
1822 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1823 | l4_proto = ip6h->nexthdr; | |
1824 | } else | |
1825 | return MVNETA_TX_L4_CSUM_NOT; | |
1826 | ||
1827 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1828 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1829 | } |
1830 | ||
1831 | return MVNETA_TX_L4_CSUM_NOT; | |
1832 | } | |
1833 | ||
c5aff182 TP |
1834 | /* Drop packets received by the RXQ and free buffers */ |
1835 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1836 | struct mvneta_rx_queue *rxq) | |
1837 | { | |
1838 | int rx_done, i; | |
1839 | ||
1840 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
dc35a10f MW |
1841 | if (rx_done) |
1842 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1843 | ||
1844 | if (pp->bm_priv) { | |
1845 | for (i = 0; i < rx_done; i++) { | |
1846 | struct mvneta_rx_desc *rx_desc = | |
1847 | mvneta_rxq_next_desc_get(rxq); | |
1848 | u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); | |
1849 | struct mvneta_bm_pool *bm_pool; | |
1850 | ||
1851 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
1852 | /* Return dropped buffer to the pool */ | |
1853 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
1854 | rx_desc->buf_phys_addr); | |
1855 | } | |
1856 | return; | |
1857 | } | |
1858 | ||
c5aff182 TP |
1859 | for (i = 0; i < rxq->size; i++) { |
1860 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
8ec2cd48 | 1861 | void *data = (void *)rx_desc->buf_cookie; |
c5aff182 | 1862 | |
c5aff182 | 1863 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
a328f3a0 | 1864 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
dc35a10f | 1865 | mvneta_frag_free(pp->frag_size, data); |
c5aff182 | 1866 | } |
dc35a10f | 1867 | } |
c5aff182 | 1868 | |
dc35a10f MW |
1869 | /* Main rx processing when using software buffer management */ |
1870 | static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, | |
1871 | struct mvneta_rx_queue *rxq) | |
1872 | { | |
1873 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); | |
1874 | struct net_device *dev = pp->dev; | |
1875 | int rx_done; | |
1876 | u32 rcvd_pkts = 0; | |
1877 | u32 rcvd_bytes = 0; | |
1878 | ||
1879 | /* Get number of received packets */ | |
1880 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1881 | ||
1882 | if (rx_todo > rx_done) | |
1883 | rx_todo = rx_done; | |
1884 | ||
1885 | rx_done = 0; | |
1886 | ||
1887 | /* Fairness NAPI loop */ | |
1888 | while (rx_done < rx_todo) { | |
1889 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1890 | struct sk_buff *skb; | |
1891 | unsigned char *data; | |
1892 | dma_addr_t phys_addr; | |
1893 | u32 rx_status, frag_size; | |
1894 | int rx_bytes, err; | |
1895 | ||
1896 | rx_done++; | |
1897 | rx_status = rx_desc->status; | |
1898 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); | |
1899 | data = (unsigned char *)rx_desc->buf_cookie; | |
1900 | phys_addr = rx_desc->buf_phys_addr; | |
1901 | ||
1902 | if (!mvneta_rxq_desc_is_first_last(rx_status) || | |
1903 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { | |
1904 | err_drop_frame: | |
1905 | dev->stats.rx_errors++; | |
1906 | mvneta_rx_error(pp, rx_desc); | |
1907 | /* leave the descriptor untouched */ | |
1908 | continue; | |
1909 | } | |
1910 | ||
1911 | if (rx_bytes <= rx_copybreak) { | |
1912 | /* better copy a small frame and not unmap the DMA region */ | |
1913 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
1914 | if (unlikely(!skb)) | |
1915 | goto err_drop_frame; | |
1916 | ||
1917 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
1918 | rx_desc->buf_phys_addr, | |
1919 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
1920 | rx_bytes, | |
1921 | DMA_FROM_DEVICE); | |
1922 | memcpy(skb_put(skb, rx_bytes), | |
1923 | data + MVNETA_MH_SIZE + NET_SKB_PAD, | |
1924 | rx_bytes); | |
1925 | ||
1926 | skb->protocol = eth_type_trans(skb, dev); | |
1927 | mvneta_rx_csum(pp, rx_status, skb); | |
1928 | napi_gro_receive(&port->napi, skb); | |
1929 | ||
1930 | rcvd_pkts++; | |
1931 | rcvd_bytes += rx_bytes; | |
1932 | ||
1933 | /* leave the descriptor and buffer untouched */ | |
1934 | continue; | |
1935 | } | |
1936 | ||
1937 | /* Refill processing */ | |
1938 | err = mvneta_rx_refill(pp, rx_desc); | |
1939 | if (err) { | |
1940 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
1941 | rxq->missed++; | |
1942 | goto err_drop_frame; | |
1943 | } | |
1944 | ||
1945 | frag_size = pp->frag_size; | |
1946 | ||
1947 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
1948 | ||
1949 | /* After refill old buffer has to be unmapped regardless | |
1950 | * the skb is successfully built or not. | |
1951 | */ | |
1952 | dma_unmap_single(dev->dev.parent, phys_addr, | |
1953 | MVNETA_RX_BUF_SIZE(pp->pkt_size), | |
1954 | DMA_FROM_DEVICE); | |
1955 | ||
1956 | if (!skb) | |
1957 | goto err_drop_frame; | |
1958 | ||
1959 | rcvd_pkts++; | |
1960 | rcvd_bytes += rx_bytes; | |
1961 | ||
1962 | /* Linux processing */ | |
1963 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); | |
1964 | skb_put(skb, rx_bytes); | |
1965 | ||
1966 | skb->protocol = eth_type_trans(skb, dev); | |
1967 | ||
1968 | mvneta_rx_csum(pp, rx_status, skb); | |
1969 | ||
1970 | napi_gro_receive(&port->napi, skb); | |
1971 | } | |
1972 | ||
1973 | if (rcvd_pkts) { | |
1974 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); | |
1975 | ||
1976 | u64_stats_update_begin(&stats->syncp); | |
1977 | stats->rx_packets += rcvd_pkts; | |
1978 | stats->rx_bytes += rcvd_bytes; | |
1979 | u64_stats_update_end(&stats->syncp); | |
1980 | } | |
1981 | ||
1982 | /* Update rxq management counters */ | |
1983 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1984 | ||
1985 | return rx_done; | |
c5aff182 TP |
1986 | } |
1987 | ||
dc35a10f MW |
1988 | /* Main rx processing when using hardware buffer management */ |
1989 | static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo, | |
1990 | struct mvneta_rx_queue *rxq) | |
c5aff182 | 1991 | { |
12bb03b4 | 1992 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 | 1993 | struct net_device *dev = pp->dev; |
a84e3289 | 1994 | int rx_done; |
dc4277dd | 1995 | u32 rcvd_pkts = 0; |
1996 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
1997 | |
1998 | /* Get number of received packets */ | |
1999 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
2000 | ||
2001 | if (rx_todo > rx_done) | |
2002 | rx_todo = rx_done; | |
2003 | ||
2004 | rx_done = 0; | |
c5aff182 TP |
2005 | |
2006 | /* Fairness NAPI loop */ | |
2007 | while (rx_done < rx_todo) { | |
2008 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
dc35a10f | 2009 | struct mvneta_bm_pool *bm_pool = NULL; |
c5aff182 | 2010 | struct sk_buff *skb; |
8ec2cd48 | 2011 | unsigned char *data; |
daf158d0 | 2012 | dma_addr_t phys_addr; |
dc35a10f | 2013 | u32 rx_status, frag_size; |
c5aff182 | 2014 | int rx_bytes, err; |
dc35a10f | 2015 | u8 pool_id; |
c5aff182 | 2016 | |
c5aff182 | 2017 | rx_done++; |
c5aff182 | 2018 | rx_status = rx_desc->status; |
f19fadfc | 2019 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
8ec2cd48 | 2020 | data = (unsigned char *)rx_desc->buf_cookie; |
daf158d0 | 2021 | phys_addr = rx_desc->buf_phys_addr; |
dc35a10f MW |
2022 | pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); |
2023 | bm_pool = &pp->bm_priv->bm_pools[pool_id]; | |
c5aff182 | 2024 | |
5428213c | 2025 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 2026 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
dc35a10f MW |
2027 | err_drop_frame_ret_pool: |
2028 | /* Return the buffer to the pool */ | |
2029 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2030 | rx_desc->buf_phys_addr); | |
2031 | err_drop_frame: | |
c5aff182 TP |
2032 | dev->stats.rx_errors++; |
2033 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 2034 | /* leave the descriptor untouched */ |
c5aff182 TP |
2035 | continue; |
2036 | } | |
2037 | ||
f19fadfc | 2038 | if (rx_bytes <= rx_copybreak) { |
2039 | /* better copy a small frame and not unmap the DMA region */ | |
2040 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
2041 | if (unlikely(!skb)) | |
dc35a10f | 2042 | goto err_drop_frame_ret_pool; |
f19fadfc | 2043 | |
2044 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
2045 | rx_desc->buf_phys_addr, | |
2046 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
2047 | rx_bytes, | |
2048 | DMA_FROM_DEVICE); | |
2049 | memcpy(skb_put(skb, rx_bytes), | |
2050 | data + MVNETA_MH_SIZE + NET_SKB_PAD, | |
2051 | rx_bytes); | |
2052 | ||
2053 | skb->protocol = eth_type_trans(skb, dev); | |
2054 | mvneta_rx_csum(pp, rx_status, skb); | |
12bb03b4 | 2055 | napi_gro_receive(&port->napi, skb); |
f19fadfc | 2056 | |
2057 | rcvd_pkts++; | |
2058 | rcvd_bytes += rx_bytes; | |
2059 | ||
dc35a10f MW |
2060 | /* Return the buffer to the pool */ |
2061 | mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, | |
2062 | rx_desc->buf_phys_addr); | |
2063 | ||
f19fadfc | 2064 | /* leave the descriptor and buffer untouched */ |
2065 | continue; | |
2066 | } | |
2067 | ||
a84e3289 | 2068 | /* Refill processing */ |
baa11ebc | 2069 | err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); |
a84e3289 SG |
2070 | if (err) { |
2071 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
2072 | rxq->missed++; | |
dc35a10f | 2073 | goto err_drop_frame_ret_pool; |
a84e3289 SG |
2074 | } |
2075 | ||
baa11ebc | 2076 | frag_size = bm_pool->hwbm_pool.frag_size; |
dc35a10f MW |
2077 | |
2078 | skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); | |
f19fadfc | 2079 | |
26c17a17 MW |
2080 | /* After refill old buffer has to be unmapped regardless |
2081 | * the skb is successfully built or not. | |
2082 | */ | |
dc35a10f MW |
2083 | dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, |
2084 | bm_pool->buf_size, DMA_FROM_DEVICE); | |
26c17a17 MW |
2085 | if (!skb) |
2086 | goto err_drop_frame; | |
2087 | ||
dc4277dd | 2088 | rcvd_pkts++; |
2089 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
2090 | |
2091 | /* Linux processing */ | |
8ec2cd48 | 2092 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
2093 | skb_put(skb, rx_bytes); |
2094 | ||
2095 | skb->protocol = eth_type_trans(skb, dev); | |
2096 | ||
5428213c | 2097 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 2098 | |
12bb03b4 | 2099 | napi_gro_receive(&port->napi, skb); |
c5aff182 TP |
2100 | } |
2101 | ||
dc4277dd | 2102 | if (rcvd_pkts) { |
74c41b04 | 2103 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
2104 | ||
2105 | u64_stats_update_begin(&stats->syncp); | |
2106 | stats->rx_packets += rcvd_pkts; | |
2107 | stats->rx_bytes += rcvd_bytes; | |
2108 | u64_stats_update_end(&stats->syncp); | |
dc4277dd | 2109 | } |
2110 | ||
c5aff182 | 2111 | /* Update rxq management counters */ |
a84e3289 | 2112 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
2113 | |
2114 | return rx_done; | |
2115 | } | |
2116 | ||
2adb719d EG |
2117 | static inline void |
2118 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
2119 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
2120 | { | |
2121 | struct mvneta_tx_desc *tx_desc; | |
2122 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2123 | ||
2124 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2125 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2126 | tx_desc->data_size = hdr_len; | |
2127 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
2128 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
2129 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
2130 | txq->txq_put_index * TSO_HEADER_SIZE; | |
2131 | mvneta_txq_inc_put(txq); | |
2132 | } | |
2133 | ||
2134 | static inline int | |
2135 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
2136 | struct sk_buff *skb, char *data, int size, | |
2137 | bool last_tcp, bool is_last) | |
2138 | { | |
2139 | struct mvneta_tx_desc *tx_desc; | |
2140 | ||
2141 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2142 | tx_desc->data_size = size; | |
2143 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
2144 | size, DMA_TO_DEVICE); | |
2145 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2146 | tx_desc->buf_phys_addr))) { | |
2147 | mvneta_txq_desc_put(txq); | |
2148 | return -ENOMEM; | |
2149 | } | |
2150 | ||
2151 | tx_desc->command = 0; | |
2152 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2153 | ||
2154 | if (last_tcp) { | |
2155 | /* last descriptor in the TCP packet */ | |
2156 | tx_desc->command = MVNETA_TXD_L_DESC; | |
2157 | ||
2158 | /* last descriptor in SKB */ | |
2159 | if (is_last) | |
2160 | txq->tx_skb[txq->txq_put_index] = skb; | |
2161 | } | |
2162 | mvneta_txq_inc_put(txq); | |
2163 | return 0; | |
2164 | } | |
2165 | ||
2166 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
2167 | struct mvneta_tx_queue *txq) | |
2168 | { | |
2169 | int total_len, data_left; | |
2170 | int desc_count = 0; | |
2171 | struct mvneta_port *pp = netdev_priv(dev); | |
2172 | struct tso_t tso; | |
2173 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2174 | int i; | |
2175 | ||
2176 | /* Count needed descriptors */ | |
2177 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
2178 | return 0; | |
2179 | ||
2180 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
2181 | pr_info("*** Is this even possible???!?!?\n"); | |
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | /* Initialize the TSO handler, and prepare the first payload */ | |
2186 | tso_start(skb, &tso); | |
2187 | ||
2188 | total_len = skb->len - hdr_len; | |
2189 | while (total_len > 0) { | |
2190 | char *hdr; | |
2191 | ||
2192 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
2193 | total_len -= data_left; | |
2194 | desc_count++; | |
2195 | ||
2196 | /* prepare packet headers: MAC + IP + TCP */ | |
2197 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
2198 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
2199 | ||
2200 | mvneta_tso_put_hdr(skb, pp, txq); | |
2201 | ||
2202 | while (data_left > 0) { | |
2203 | int size; | |
2204 | desc_count++; | |
2205 | ||
2206 | size = min_t(int, tso.size, data_left); | |
2207 | ||
2208 | if (mvneta_tso_put_data(dev, txq, skb, | |
2209 | tso.data, size, | |
2210 | size == data_left, | |
2211 | total_len == 0)) | |
2212 | goto err_release; | |
2213 | data_left -= size; | |
2214 | ||
2215 | tso_build_data(skb, &tso, size); | |
2216 | } | |
2217 | } | |
2218 | ||
2219 | return desc_count; | |
2220 | ||
2221 | err_release: | |
2222 | /* Release all used data descriptors; header descriptors must not | |
2223 | * be DMA-unmapped. | |
2224 | */ | |
2225 | for (i = desc_count - 1; i >= 0; i--) { | |
2226 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 2227 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
2228 | dma_unmap_single(pp->dev->dev.parent, |
2229 | tx_desc->buf_phys_addr, | |
2230 | tx_desc->data_size, | |
2231 | DMA_TO_DEVICE); | |
2232 | mvneta_txq_desc_put(txq); | |
2233 | } | |
2234 | return 0; | |
2235 | } | |
2236 | ||
c5aff182 TP |
2237 | /* Handle tx fragmentation processing */ |
2238 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
2239 | struct mvneta_tx_queue *txq) | |
2240 | { | |
2241 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 2242 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 2243 | |
3d4ea02f | 2244 | for (i = 0; i < nr_frags; i++) { |
c5aff182 TP |
2245 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2246 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
2247 | ||
2248 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2249 | tx_desc->data_size = frag->size; | |
2250 | ||
2251 | tx_desc->buf_phys_addr = | |
2252 | dma_map_single(pp->dev->dev.parent, addr, | |
2253 | tx_desc->data_size, DMA_TO_DEVICE); | |
2254 | ||
2255 | if (dma_mapping_error(pp->dev->dev.parent, | |
2256 | tx_desc->buf_phys_addr)) { | |
2257 | mvneta_txq_desc_put(txq); | |
2258 | goto error; | |
2259 | } | |
2260 | ||
3d4ea02f | 2261 | if (i == nr_frags - 1) { |
c5aff182 TP |
2262 | /* Last descriptor */ |
2263 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
c5aff182 | 2264 | txq->tx_skb[txq->txq_put_index] = skb; |
c5aff182 TP |
2265 | } else { |
2266 | /* Descriptor in the middle: Not First, Not Last */ | |
2267 | tx_desc->command = 0; | |
c5aff182 | 2268 | txq->tx_skb[txq->txq_put_index] = NULL; |
c5aff182 | 2269 | } |
3d4ea02f | 2270 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
2271 | } |
2272 | ||
2273 | return 0; | |
2274 | ||
2275 | error: | |
2276 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
2277 | * this packet, as well as the corresponding DMA mappings |
2278 | */ | |
c5aff182 TP |
2279 | for (i = i - 1; i >= 0; i--) { |
2280 | tx_desc = txq->descs + i; | |
2281 | dma_unmap_single(pp->dev->dev.parent, | |
2282 | tx_desc->buf_phys_addr, | |
2283 | tx_desc->data_size, | |
2284 | DMA_TO_DEVICE); | |
2285 | mvneta_txq_desc_put(txq); | |
2286 | } | |
2287 | ||
2288 | return -ENOMEM; | |
2289 | } | |
2290 | ||
2291 | /* Main tx processing */ | |
2292 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) | |
2293 | { | |
2294 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
2295 | u16 txq_id = skb_get_queue_mapping(skb); |
2296 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
c5aff182 | 2297 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 2298 | int len = skb->len; |
c5aff182 TP |
2299 | int frags = 0; |
2300 | u32 tx_cmd; | |
2301 | ||
2302 | if (!netif_running(dev)) | |
2303 | goto out; | |
2304 | ||
2adb719d EG |
2305 | if (skb_is_gso(skb)) { |
2306 | frags = mvneta_tx_tso(skb, dev, txq); | |
2307 | goto out; | |
2308 | } | |
2309 | ||
c5aff182 | 2310 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
2311 | |
2312 | /* Get a descriptor for the first part of the packet */ | |
2313 | tx_desc = mvneta_txq_next_desc_get(txq); | |
2314 | ||
2315 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
2316 | ||
2317 | tx_desc->data_size = skb_headlen(skb); | |
2318 | ||
2319 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
2320 | tx_desc->data_size, | |
2321 | DMA_TO_DEVICE); | |
2322 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
2323 | tx_desc->buf_phys_addr))) { | |
2324 | mvneta_txq_desc_put(txq); | |
2325 | frags = 0; | |
2326 | goto out; | |
2327 | } | |
2328 | ||
2329 | if (frags == 1) { | |
2330 | /* First and Last descriptor */ | |
2331 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
2332 | tx_desc->command = tx_cmd; | |
2333 | txq->tx_skb[txq->txq_put_index] = skb; | |
2334 | mvneta_txq_inc_put(txq); | |
2335 | } else { | |
2336 | /* First but not Last */ | |
2337 | tx_cmd |= MVNETA_TXD_F_DESC; | |
2338 | txq->tx_skb[txq->txq_put_index] = NULL; | |
2339 | mvneta_txq_inc_put(txq); | |
2340 | tx_desc->command = tx_cmd; | |
2341 | /* Continue with other skb fragments */ | |
2342 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
2343 | dma_unmap_single(dev->dev.parent, | |
2344 | tx_desc->buf_phys_addr, | |
2345 | tx_desc->data_size, | |
2346 | DMA_TO_DEVICE); | |
2347 | mvneta_txq_desc_put(txq); | |
2348 | frags = 0; | |
2349 | goto out; | |
2350 | } | |
2351 | } | |
2352 | ||
c5aff182 TP |
2353 | out: |
2354 | if (frags > 0) { | |
74c41b04 | 2355 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
e19d2dda EG |
2356 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
2357 | ||
2358 | txq->count += frags; | |
2359 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
2360 | ||
8eef5f97 | 2361 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 2362 | netif_tx_stop_queue(nq); |
c5aff182 | 2363 | |
74c41b04 | 2364 | u64_stats_update_begin(&stats->syncp); |
2365 | stats->tx_packets++; | |
5f478b41 | 2366 | stats->tx_bytes += len; |
74c41b04 | 2367 | u64_stats_update_end(&stats->syncp); |
c5aff182 TP |
2368 | } else { |
2369 | dev->stats.tx_dropped++; | |
2370 | dev_kfree_skb_any(skb); | |
2371 | } | |
2372 | ||
c5aff182 TP |
2373 | return NETDEV_TX_OK; |
2374 | } | |
2375 | ||
2376 | ||
2377 | /* Free tx resources, when resetting a port */ | |
2378 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
2379 | struct mvneta_tx_queue *txq) | |
2380 | ||
2381 | { | |
2382 | int tx_done = txq->count; | |
2383 | ||
2384 | mvneta_txq_bufs_free(pp, txq, tx_done); | |
2385 | ||
2386 | /* reset txq */ | |
2387 | txq->count = 0; | |
2388 | txq->txq_put_index = 0; | |
2389 | txq->txq_get_index = 0; | |
2390 | } | |
2391 | ||
6c498974 | 2392 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
2393 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
2394 | */ | |
0713a86a | 2395 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
2396 | { |
2397 | struct mvneta_tx_queue *txq; | |
c5aff182 TP |
2398 | struct netdev_queue *nq; |
2399 | ||
6c498974 | 2400 | while (cause_tx_done) { |
c5aff182 | 2401 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
2402 | |
2403 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
2404 | __netif_tx_lock(nq, smp_processor_id()); | |
2405 | ||
0713a86a AE |
2406 | if (txq->count) |
2407 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
2408 | |
2409 | __netif_tx_unlock(nq); | |
2410 | cause_tx_done &= ~((1 << txq->id)); | |
2411 | } | |
c5aff182 TP |
2412 | } |
2413 | ||
6a20c175 | 2414 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
2415 | * according to hw spec, different than generic crc8 algorithm |
2416 | */ | |
2417 | static int mvneta_addr_crc(unsigned char *addr) | |
2418 | { | |
2419 | int crc = 0; | |
2420 | int i; | |
2421 | ||
2422 | for (i = 0; i < ETH_ALEN; i++) { | |
2423 | int j; | |
2424 | ||
2425 | crc = (crc ^ addr[i]) << 8; | |
2426 | for (j = 7; j >= 0; j--) { | |
2427 | if (crc & (0x100 << j)) | |
2428 | crc ^= 0x107 << j; | |
2429 | } | |
2430 | } | |
2431 | ||
2432 | return crc; | |
2433 | } | |
2434 | ||
2435 | /* This method controls the net device special MAC multicast support. | |
2436 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2437 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2438 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2439 | * Table entries in the DA-Filter table. This method set the Special | |
2440 | * Multicast Table appropriate entry. | |
2441 | */ | |
2442 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2443 | unsigned char last_byte, | |
2444 | int queue) | |
2445 | { | |
2446 | unsigned int smc_table_reg; | |
2447 | unsigned int tbl_offset; | |
2448 | unsigned int reg_offset; | |
2449 | ||
2450 | /* Register offset from SMC table base */ | |
2451 | tbl_offset = (last_byte / 4); | |
2452 | /* Entry offset within the above reg */ | |
2453 | reg_offset = last_byte % 4; | |
2454 | ||
2455 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2456 | + tbl_offset * 4)); | |
2457 | ||
2458 | if (queue == -1) | |
2459 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2460 | else { | |
2461 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2462 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2463 | } | |
2464 | ||
2465 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2466 | smc_table_reg); | |
2467 | } | |
2468 | ||
2469 | /* This method controls the network device Other MAC multicast support. | |
2470 | * The Other Multicast Table is used for multicast of another type. | |
2471 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2472 | * in the DA-Filter table. | |
2473 | * The method gets the CRC-8 value from the calling routine and | |
2474 | * sets the Other Multicast Table appropriate entry according to the | |
2475 | * specified CRC-8 . | |
2476 | */ | |
2477 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2478 | unsigned char crc8, | |
2479 | int queue) | |
2480 | { | |
2481 | unsigned int omc_table_reg; | |
2482 | unsigned int tbl_offset; | |
2483 | unsigned int reg_offset; | |
2484 | ||
2485 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2486 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2487 | ||
2488 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2489 | ||
2490 | if (queue == -1) { | |
2491 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2492 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2493 | } else { | |
2494 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2495 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2496 | } | |
2497 | ||
2498 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2499 | } | |
2500 | ||
2501 | /* The network device supports multicast using two tables: | |
2502 | * 1) Special Multicast Table for MAC addresses of the form | |
2503 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2504 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2505 | * Table entries in the DA-Filter table. | |
2506 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
2507 | * is used as an index to the Other Multicast Table entries in the | |
2508 | * DA-Filter table. | |
2509 | */ | |
2510 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
2511 | int queue) | |
2512 | { | |
2513 | unsigned char crc_result = 0; | |
2514 | ||
2515 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
2516 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
2517 | return 0; | |
2518 | } | |
2519 | ||
2520 | crc_result = mvneta_addr_crc(p_addr); | |
2521 | if (queue == -1) { | |
2522 | if (pp->mcast_count[crc_result] == 0) { | |
2523 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
2524 | crc_result); | |
2525 | return -EINVAL; | |
2526 | } | |
2527 | ||
2528 | pp->mcast_count[crc_result]--; | |
2529 | if (pp->mcast_count[crc_result] != 0) { | |
2530 | netdev_info(pp->dev, | |
2531 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
2532 | pp->mcast_count[crc_result], crc_result); | |
2533 | return -EINVAL; | |
2534 | } | |
2535 | } else | |
2536 | pp->mcast_count[crc_result]++; | |
2537 | ||
2538 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
2543 | /* Configure Fitering mode of Ethernet port */ | |
2544 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2545 | int is_promisc) | |
2546 | { | |
2547 | u32 port_cfg_reg, val; | |
2548 | ||
2549 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2550 | ||
2551 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2552 | ||
2553 | /* Set / Clear UPM bit in port configuration register */ | |
2554 | if (is_promisc) { | |
2555 | /* Accept all Unicast addresses */ | |
2556 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2557 | val |= MVNETA_FORCE_UNI; | |
2558 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2559 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2560 | } else { | |
2561 | /* Reject all Unicast addresses */ | |
2562 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2563 | val &= ~MVNETA_FORCE_UNI; | |
2564 | } | |
2565 | ||
2566 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2567 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2568 | } | |
2569 | ||
2570 | /* register unicast and multicast addresses */ | |
2571 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2572 | { | |
2573 | struct mvneta_port *pp = netdev_priv(dev); | |
2574 | struct netdev_hw_addr *ha; | |
2575 | ||
2576 | if (dev->flags & IFF_PROMISC) { | |
2577 | /* Accept all: Multicast + Unicast */ | |
2578 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
2579 | mvneta_set_ucast_table(pp, pp->rxq_def); |
2580 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
2581 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2582 | } else { |
2583 | /* Accept single Unicast */ | |
2584 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2585 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 2586 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
2587 | |
2588 | if (dev->flags & IFF_ALLMULTI) { | |
2589 | /* Accept all multicast */ | |
90b74c01 GC |
2590 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
2591 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2592 | } else { |
2593 | /* Accept only initialized multicast */ | |
2594 | mvneta_set_special_mcast_table(pp, -1); | |
2595 | mvneta_set_other_mcast_table(pp, -1); | |
2596 | ||
2597 | if (!netdev_mc_empty(dev)) { | |
2598 | netdev_for_each_mc_addr(ha, dev) { | |
2599 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 2600 | pp->rxq_def); |
c5aff182 TP |
2601 | } |
2602 | } | |
2603 | } | |
2604 | } | |
2605 | } | |
2606 | ||
2607 | /* Interrupt handling - the callback for request_irq() */ | |
2608 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2609 | { | |
12bb03b4 | 2610 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2611 | |
12bb03b4 | 2612 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 2613 | napi_schedule(&port->napi); |
c5aff182 TP |
2614 | |
2615 | return IRQ_HANDLED; | |
2616 | } | |
2617 | ||
898b2970 SS |
2618 | static int mvneta_fixed_link_update(struct mvneta_port *pp, |
2619 | struct phy_device *phy) | |
2620 | { | |
2621 | struct fixed_phy_status status; | |
2622 | struct fixed_phy_status changed = {}; | |
2623 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); | |
2624 | ||
2625 | status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
2626 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) | |
2627 | status.speed = SPEED_1000; | |
2628 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) | |
2629 | status.speed = SPEED_100; | |
2630 | else | |
2631 | status.speed = SPEED_10; | |
2632 | status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
2633 | changed.link = 1; | |
2634 | changed.speed = 1; | |
2635 | changed.duplex = 1; | |
2636 | fixed_phy_update_state(phy, &status, &changed); | |
2637 | return 0; | |
2638 | } | |
2639 | ||
c5aff182 TP |
2640 | /* NAPI handler |
2641 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
2642 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
2643 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
2644 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
2645 | * Each CPU has its own causeRxTx register | |
2646 | */ | |
2647 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
2648 | { | |
2649 | int rx_done = 0; | |
2650 | u32 cause_rx_tx; | |
2dcf75e2 | 2651 | int rx_queue; |
c5aff182 | 2652 | struct mvneta_port *pp = netdev_priv(napi->dev); |
c6c022e3 | 2653 | struct net_device *ndev = pp->dev; |
12bb03b4 | 2654 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
2655 | |
2656 | if (!netif_running(pp->dev)) { | |
12bb03b4 | 2657 | napi_complete(&port->napi); |
c5aff182 TP |
2658 | return rx_done; |
2659 | } | |
2660 | ||
2661 | /* Read cause register */ | |
898b2970 SS |
2662 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
2663 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
2664 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
2665 | ||
2666 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2667 | if (pp->use_inband_status && (cause_misc & | |
2668 | (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2669 | MVNETA_CAUSE_LINK_CHANGE | | |
2670 | MVNETA_CAUSE_PSC_SYNC_CHANGE))) { | |
c6c022e3 | 2671 | mvneta_fixed_link_update(pp, ndev->phydev); |
898b2970 SS |
2672 | } |
2673 | } | |
71f6d1b3 | 2674 | |
2675 | /* Release Tx descriptors */ | |
2676 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 2677 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 2678 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
2679 | } | |
c5aff182 | 2680 | |
6a20c175 | 2681 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
2682 | * RX packets |
2683 | */ | |
2dcf75e2 GC |
2684 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
2685 | ||
12bb03b4 | 2686 | cause_rx_tx |= port->cause_rx_tx; |
2dcf75e2 GC |
2687 | |
2688 | if (rx_queue) { | |
2689 | rx_queue = rx_queue - 1; | |
dc35a10f MW |
2690 | if (pp->bm_priv) |
2691 | rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]); | |
2692 | else | |
2693 | rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]); | |
2dcf75e2 GC |
2694 | } |
2695 | ||
d8936657 | 2696 | budget -= rx_done; |
c5aff182 TP |
2697 | |
2698 | if (budget > 0) { | |
2699 | cause_rx_tx = 0; | |
12bb03b4 MR |
2700 | napi_complete(&port->napi); |
2701 | enable_percpu_irq(pp->dev->irq, 0); | |
c5aff182 TP |
2702 | } |
2703 | ||
12bb03b4 | 2704 | port->cause_rx_tx = cause_rx_tx; |
c5aff182 TP |
2705 | return rx_done; |
2706 | } | |
2707 | ||
c5aff182 TP |
2708 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
2709 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2710 | int num) | |
2711 | { | |
c5aff182 TP |
2712 | int i; |
2713 | ||
2714 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 2715 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
2716 | if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { | |
2717 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", | |
c5aff182 TP |
2718 | __func__, rxq->id, i, num); |
2719 | break; | |
2720 | } | |
c5aff182 TP |
2721 | } |
2722 | ||
2723 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
2724 | * get packets) |
2725 | */ | |
c5aff182 TP |
2726 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
2727 | ||
2728 | return i; | |
2729 | } | |
2730 | ||
2731 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
2732 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
2733 | { | |
2734 | int queue; | |
2735 | ||
9672850b | 2736 | /* free the skb's in the tx ring */ |
c5aff182 TP |
2737 | for (queue = 0; queue < txq_number; queue++) |
2738 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
2739 | ||
2740 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
2741 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
2742 | } | |
2743 | ||
2744 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
2745 | { | |
2746 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
2747 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
2748 | } | |
2749 | ||
2750 | /* Rx/Tx queue initialization/cleanup methods */ | |
2751 | ||
2752 | /* Create a specified RX queue */ | |
2753 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
2754 | struct mvneta_rx_queue *rxq) | |
2755 | ||
2756 | { | |
2757 | rxq->size = pp->rx_ring_size; | |
2758 | ||
2759 | /* Allocate memory for RX descriptors */ | |
2760 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2761 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2762 | &rxq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2763 | if (rxq->descs == NULL) |
c5aff182 | 2764 | return -ENOMEM; |
c5aff182 | 2765 | |
c5aff182 TP |
2766 | rxq->last_desc = rxq->size - 1; |
2767 | ||
2768 | /* Set Rx descriptors queue starting address */ | |
2769 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
2770 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
2771 | ||
2772 | /* Set Offset */ | |
2773 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); | |
2774 | ||
2775 | /* Set coalescing pkts and time */ | |
2776 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2777 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2778 | ||
dc35a10f MW |
2779 | if (!pp->bm_priv) { |
2780 | /* Fill RXQ with buffers from RX pool */ | |
2781 | mvneta_rxq_buf_size_set(pp, rxq, | |
2782 | MVNETA_RX_BUF_SIZE(pp->pkt_size)); | |
2783 | mvneta_rxq_bm_disable(pp, rxq); | |
2784 | } else { | |
2785 | mvneta_rxq_bm_enable(pp, rxq); | |
2786 | mvneta_rxq_long_pool_set(pp, rxq); | |
2787 | mvneta_rxq_short_pool_set(pp, rxq); | |
2788 | } | |
2789 | ||
c5aff182 TP |
2790 | mvneta_rxq_fill(pp, rxq, rxq->size); |
2791 | ||
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | /* Cleanup Rx queue */ | |
2796 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
2797 | struct mvneta_rx_queue *rxq) | |
2798 | { | |
2799 | mvneta_rxq_drop_pkts(pp, rxq); | |
2800 | ||
2801 | if (rxq->descs) | |
2802 | dma_free_coherent(pp->dev->dev.parent, | |
2803 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2804 | rxq->descs, | |
2805 | rxq->descs_phys); | |
2806 | ||
2807 | rxq->descs = NULL; | |
2808 | rxq->last_desc = 0; | |
2809 | rxq->next_desc_to_proc = 0; | |
2810 | rxq->descs_phys = 0; | |
2811 | } | |
2812 | ||
2813 | /* Create and initialize a tx queue */ | |
2814 | static int mvneta_txq_init(struct mvneta_port *pp, | |
2815 | struct mvneta_tx_queue *txq) | |
2816 | { | |
50bf8cb6 GC |
2817 | int cpu; |
2818 | ||
c5aff182 TP |
2819 | txq->size = pp->tx_ring_size; |
2820 | ||
8eef5f97 EG |
2821 | /* A queue must always have room for at least one skb. |
2822 | * Therefore, stop the queue when the free entries reaches | |
2823 | * the maximum number of descriptors per skb. | |
2824 | */ | |
2825 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
2826 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
2827 | ||
2828 | ||
c5aff182 TP |
2829 | /* Allocate memory for TX descriptors */ |
2830 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2831 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2832 | &txq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2833 | if (txq->descs == NULL) |
c5aff182 | 2834 | return -ENOMEM; |
c5aff182 | 2835 | |
c5aff182 TP |
2836 | txq->last_desc = txq->size - 1; |
2837 | ||
2838 | /* Set maximum bandwidth for enabled TXQs */ | |
2839 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
2840 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
2841 | ||
2842 | /* Set Tx descriptors queue starting address */ | |
2843 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
2844 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
2845 | ||
2846 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); | |
2847 | if (txq->tx_skb == NULL) { | |
2848 | dma_free_coherent(pp->dev->dev.parent, | |
2849 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2850 | txq->descs, txq->descs_phys); | |
2851 | return -ENOMEM; | |
2852 | } | |
2adb719d EG |
2853 | |
2854 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
2855 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
2856 | txq->size * TSO_HEADER_SIZE, | |
2857 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
2858 | if (txq->tso_hdrs == NULL) { | |
2859 | kfree(txq->tx_skb); | |
2860 | dma_free_coherent(pp->dev->dev.parent, | |
2861 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2862 | txq->descs, txq->descs_phys); | |
2863 | return -ENOMEM; | |
2864 | } | |
c5aff182 TP |
2865 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
2866 | ||
50bf8cb6 GC |
2867 | /* Setup XPS mapping */ |
2868 | if (txq_number > 1) | |
2869 | cpu = txq->id % num_present_cpus(); | |
2870 | else | |
2871 | cpu = pp->rxq_def % num_present_cpus(); | |
2872 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
2873 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
2874 | ||
c5aff182 TP |
2875 | return 0; |
2876 | } | |
2877 | ||
2878 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
2879 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
2880 | struct mvneta_tx_queue *txq) | |
2881 | { | |
2882 | kfree(txq->tx_skb); | |
2883 | ||
2adb719d EG |
2884 | if (txq->tso_hdrs) |
2885 | dma_free_coherent(pp->dev->dev.parent, | |
2886 | txq->size * TSO_HEADER_SIZE, | |
2887 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
2888 | if (txq->descs) |
2889 | dma_free_coherent(pp->dev->dev.parent, | |
2890 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2891 | txq->descs, txq->descs_phys); | |
2892 | ||
2893 | txq->descs = NULL; | |
2894 | txq->last_desc = 0; | |
2895 | txq->next_desc_to_proc = 0; | |
2896 | txq->descs_phys = 0; | |
2897 | ||
2898 | /* Set minimum bandwidth for disabled TXQs */ | |
2899 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
2900 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
2901 | ||
2902 | /* Set Tx descriptors queue starting address and size */ | |
2903 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
2904 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
2905 | } | |
2906 | ||
2907 | /* Cleanup all Tx queues */ | |
2908 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
2909 | { | |
2910 | int queue; | |
2911 | ||
2912 | for (queue = 0; queue < txq_number; queue++) | |
2913 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
2914 | } | |
2915 | ||
2916 | /* Cleanup all Rx queues */ | |
2917 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
2918 | { | |
2dcf75e2 GC |
2919 | int queue; |
2920 | ||
2921 | for (queue = 0; queue < txq_number; queue++) | |
2922 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
c5aff182 TP |
2923 | } |
2924 | ||
2925 | ||
2926 | /* Init all Rx queues */ | |
2927 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
2928 | { | |
2dcf75e2 GC |
2929 | int queue; |
2930 | ||
2931 | for (queue = 0; queue < rxq_number; queue++) { | |
2932 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
2933 | ||
2934 | if (err) { | |
2935 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
2936 | __func__, queue); | |
2937 | mvneta_cleanup_rxqs(pp); | |
2938 | return err; | |
2939 | } | |
c5aff182 TP |
2940 | } |
2941 | ||
2942 | return 0; | |
2943 | } | |
2944 | ||
2945 | /* Init all tx queues */ | |
2946 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
2947 | { | |
2948 | int queue; | |
2949 | ||
2950 | for (queue = 0; queue < txq_number; queue++) { | |
2951 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
2952 | if (err) { | |
2953 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
2954 | __func__, queue); | |
2955 | mvneta_cleanup_txqs(pp); | |
2956 | return err; | |
2957 | } | |
2958 | } | |
2959 | ||
2960 | return 0; | |
2961 | } | |
2962 | ||
2963 | static void mvneta_start_dev(struct mvneta_port *pp) | |
2964 | { | |
6b125d63 | 2965 | int cpu; |
c6c022e3 | 2966 | struct net_device *ndev = pp->dev; |
12bb03b4 | 2967 | |
c5aff182 TP |
2968 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
2969 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
2970 | ||
2971 | /* start the Rx/Tx activity */ | |
2972 | mvneta_port_enable(pp); | |
2973 | ||
2974 | /* Enable polling on the port */ | |
129219e4 | 2975 | for_each_online_cpu(cpu) { |
12bb03b4 MR |
2976 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
2977 | ||
2978 | napi_enable(&port->napi); | |
2979 | } | |
c5aff182 | 2980 | |
2dcf75e2 | 2981 | /* Unmask interrupts. It has to be done from each CPU */ |
6b125d63 GC |
2982 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
2983 | ||
898b2970 SS |
2984 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
2985 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2986 | MVNETA_CAUSE_LINK_CHANGE | | |
2987 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
c5aff182 | 2988 | |
c6c022e3 | 2989 | phy_start(ndev->phydev); |
c5aff182 TP |
2990 | netif_tx_start_all_queues(pp->dev); |
2991 | } | |
2992 | ||
2993 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
2994 | { | |
12bb03b4 | 2995 | unsigned int cpu; |
c6c022e3 | 2996 | struct net_device *ndev = pp->dev; |
12bb03b4 | 2997 | |
c6c022e3 | 2998 | phy_stop(ndev->phydev); |
c5aff182 | 2999 | |
129219e4 | 3000 | for_each_online_cpu(cpu) { |
12bb03b4 MR |
3001 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); |
3002 | ||
3003 | napi_disable(&port->napi); | |
3004 | } | |
c5aff182 TP |
3005 | |
3006 | netif_carrier_off(pp->dev); | |
3007 | ||
3008 | mvneta_port_down(pp); | |
3009 | netif_tx_stop_all_queues(pp->dev); | |
3010 | ||
3011 | /* Stop the port activity */ | |
3012 | mvneta_port_disable(pp); | |
3013 | ||
3014 | /* Clear all ethernet port interrupts */ | |
db488c10 | 3015 | on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); |
c5aff182 TP |
3016 | |
3017 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3018 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
c5aff182 TP |
3019 | |
3020 | mvneta_tx_reset(pp); | |
3021 | mvneta_rx_reset(pp); | |
3022 | } | |
3023 | ||
c5aff182 TP |
3024 | /* Return positive if MTU is valid */ |
3025 | static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) | |
3026 | { | |
3027 | if (mtu < 68) { | |
3028 | netdev_err(dev, "cannot change mtu to less than 68\n"); | |
3029 | return -EINVAL; | |
3030 | } | |
3031 | ||
6a20c175 | 3032 | /* 9676 == 9700 - 20 and rounding to 8 */ |
c5aff182 TP |
3033 | if (mtu > 9676) { |
3034 | netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); | |
3035 | mtu = 9676; | |
3036 | } | |
3037 | ||
3038 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { | |
3039 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
3040 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
3041 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
3042 | } | |
3043 | ||
3044 | return mtu; | |
3045 | } | |
3046 | ||
db5dd0db MW |
3047 | static void mvneta_percpu_enable(void *arg) |
3048 | { | |
3049 | struct mvneta_port *pp = arg; | |
3050 | ||
3051 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
3052 | } | |
3053 | ||
3054 | static void mvneta_percpu_disable(void *arg) | |
3055 | { | |
3056 | struct mvneta_port *pp = arg; | |
3057 | ||
3058 | disable_percpu_irq(pp->dev->irq); | |
3059 | } | |
3060 | ||
c5aff182 TP |
3061 | /* Change the device mtu */ |
3062 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
3063 | { | |
3064 | struct mvneta_port *pp = netdev_priv(dev); | |
3065 | int ret; | |
3066 | ||
3067 | mtu = mvneta_check_mtu_valid(dev, mtu); | |
3068 | if (mtu < 0) | |
3069 | return -EINVAL; | |
3070 | ||
3071 | dev->mtu = mtu; | |
3072 | ||
b65657fc | 3073 | if (!netif_running(dev)) { |
dc35a10f MW |
3074 | if (pp->bm_priv) |
3075 | mvneta_bm_update_mtu(pp, mtu); | |
3076 | ||
b65657fc | 3077 | netdev_update_features(dev); |
c5aff182 | 3078 | return 0; |
b65657fc | 3079 | } |
c5aff182 | 3080 | |
6a20c175 | 3081 | /* The interface is running, so we have to force a |
a92dbd96 | 3082 | * reallocation of the queues |
c5aff182 TP |
3083 | */ |
3084 | mvneta_stop_dev(pp); | |
db5dd0db | 3085 | on_each_cpu(mvneta_percpu_disable, pp, true); |
c5aff182 TP |
3086 | |
3087 | mvneta_cleanup_txqs(pp); | |
3088 | mvneta_cleanup_rxqs(pp); | |
3089 | ||
dc35a10f MW |
3090 | if (pp->bm_priv) |
3091 | mvneta_bm_update_mtu(pp, mtu); | |
3092 | ||
a92dbd96 | 3093 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
8ec2cd48 | 3094 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
3095 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
3096 | |
3097 | ret = mvneta_setup_rxqs(pp); | |
3098 | if (ret) { | |
a92dbd96 | 3099 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
3100 | return ret; |
3101 | } | |
3102 | ||
a92dbd96 EG |
3103 | ret = mvneta_setup_txqs(pp); |
3104 | if (ret) { | |
3105 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
3106 | return ret; | |
3107 | } | |
c5aff182 | 3108 | |
db5dd0db | 3109 | on_each_cpu(mvneta_percpu_enable, pp, true); |
c5aff182 TP |
3110 | mvneta_start_dev(pp); |
3111 | mvneta_port_up(pp); | |
3112 | ||
b65657fc SG |
3113 | netdev_update_features(dev); |
3114 | ||
c5aff182 TP |
3115 | return 0; |
3116 | } | |
3117 | ||
b65657fc SG |
3118 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
3119 | netdev_features_t features) | |
3120 | { | |
3121 | struct mvneta_port *pp = netdev_priv(dev); | |
3122 | ||
3123 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
3124 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
3125 | netdev_info(dev, | |
3126 | "Disable IP checksum for MTU greater than %dB\n", | |
3127 | pp->tx_csum_limit); | |
3128 | } | |
3129 | ||
3130 | return features; | |
3131 | } | |
3132 | ||
8cc3e439 TP |
3133 | /* Get mac address */ |
3134 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
3135 | { | |
3136 | u32 mac_addr_l, mac_addr_h; | |
3137 | ||
3138 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
3139 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
3140 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
3141 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
3142 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
3143 | addr[3] = mac_addr_h & 0xFF; | |
3144 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
3145 | addr[5] = mac_addr_l & 0xFF; | |
3146 | } | |
3147 | ||
c5aff182 TP |
3148 | /* Handle setting mac address */ |
3149 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
3150 | { | |
3151 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
3152 | struct sockaddr *sockaddr = addr; |
3153 | int ret; | |
c5aff182 | 3154 | |
e68de360 EG |
3155 | ret = eth_prepare_mac_addr_change(dev, addr); |
3156 | if (ret < 0) | |
3157 | return ret; | |
c5aff182 TP |
3158 | /* Remove previous address table entry */ |
3159 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
3160 | ||
3161 | /* Set new addr in hw */ | |
90b74c01 | 3162 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 3163 | |
e68de360 | 3164 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
3165 | return 0; |
3166 | } | |
3167 | ||
3168 | static void mvneta_adjust_link(struct net_device *ndev) | |
3169 | { | |
3170 | struct mvneta_port *pp = netdev_priv(ndev); | |
c6c022e3 | 3171 | struct phy_device *phydev = ndev->phydev; |
c5aff182 TP |
3172 | int status_change = 0; |
3173 | ||
3174 | if (phydev->link) { | |
3175 | if ((pp->speed != phydev->speed) || | |
3176 | (pp->duplex != phydev->duplex)) { | |
3177 | u32 val; | |
3178 | ||
3179 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3180 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3181 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
898b2970 | 3182 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); |
c5aff182 TP |
3183 | |
3184 | if (phydev->duplex) | |
3185 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3186 | ||
3187 | if (phydev->speed == SPEED_1000) | |
3188 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
4d12bc63 | 3189 | else if (phydev->speed == SPEED_100) |
c5aff182 TP |
3190 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
3191 | ||
3192 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3193 | ||
3194 | pp->duplex = phydev->duplex; | |
3195 | pp->speed = phydev->speed; | |
3196 | } | |
3197 | } | |
3198 | ||
3199 | if (phydev->link != pp->link) { | |
3200 | if (!phydev->link) { | |
3201 | pp->duplex = -1; | |
3202 | pp->speed = 0; | |
3203 | } | |
3204 | ||
3205 | pp->link = phydev->link; | |
3206 | status_change = 1; | |
3207 | } | |
3208 | ||
3209 | if (status_change) { | |
3210 | if (phydev->link) { | |
898b2970 SS |
3211 | if (!pp->use_inband_status) { |
3212 | u32 val = mvreg_read(pp, | |
3213 | MVNETA_GMAC_AUTONEG_CONFIG); | |
3214 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
3215 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
3216 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3217 | val); | |
3218 | } | |
c5aff182 | 3219 | mvneta_port_up(pp); |
c5aff182 | 3220 | } else { |
898b2970 SS |
3221 | if (!pp->use_inband_status) { |
3222 | u32 val = mvreg_read(pp, | |
3223 | MVNETA_GMAC_AUTONEG_CONFIG); | |
3224 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
3225 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
3226 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
3227 | val); | |
3228 | } | |
c5aff182 | 3229 | mvneta_port_down(pp); |
c5aff182 | 3230 | } |
0089b745 | 3231 | phy_print_status(phydev); |
c5aff182 TP |
3232 | } |
3233 | } | |
3234 | ||
3235 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
3236 | { | |
3237 | struct phy_device *phy_dev; | |
3238 | ||
3239 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, | |
3240 | pp->phy_interface); | |
3241 | if (!phy_dev) { | |
3242 | netdev_err(pp->dev, "could not find the PHY\n"); | |
3243 | return -ENODEV; | |
3244 | } | |
3245 | ||
3246 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
3247 | phy_dev->advertising = phy_dev->supported; | |
3248 | ||
c5aff182 TP |
3249 | pp->link = 0; |
3250 | pp->duplex = 0; | |
3251 | pp->speed = 0; | |
3252 | ||
3253 | return 0; | |
3254 | } | |
3255 | ||
3256 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
3257 | { | |
c6c022e3 PR |
3258 | struct net_device *ndev = pp->dev; |
3259 | ||
3260 | phy_disconnect(ndev->phydev); | |
c5aff182 TP |
3261 | } |
3262 | ||
120cfa50 GC |
3263 | /* Electing a CPU must be done in an atomic way: it should be done |
3264 | * after or before the removal/insertion of a CPU and this function is | |
3265 | * not reentrant. | |
3266 | */ | |
f8642885 MR |
3267 | static void mvneta_percpu_elect(struct mvneta_port *pp) |
3268 | { | |
cad5d847 GC |
3269 | int elected_cpu = 0, max_cpu, cpu, i = 0; |
3270 | ||
3271 | /* Use the cpu associated to the rxq when it is online, in all | |
3272 | * the other cases, use the cpu 0 which can't be offline. | |
3273 | */ | |
3274 | if (cpu_online(pp->rxq_def)) | |
3275 | elected_cpu = pp->rxq_def; | |
f8642885 | 3276 | |
2dcf75e2 | 3277 | max_cpu = num_present_cpus(); |
f8642885 MR |
3278 | |
3279 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
3280 | int rxq_map = 0, txq_map = 0; |
3281 | int rxq; | |
3282 | ||
3283 | for (rxq = 0; rxq < rxq_number; rxq++) | |
3284 | if ((rxq % max_cpu) == cpu) | |
3285 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
3286 | ||
cad5d847 | 3287 | if (cpu == elected_cpu) |
50bf8cb6 GC |
3288 | /* Map the default receive queue queue to the |
3289 | * elected CPU | |
f8642885 | 3290 | */ |
2dcf75e2 | 3291 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
3292 | |
3293 | /* We update the TX queue map only if we have one | |
3294 | * queue. In this case we associate the TX queue to | |
3295 | * the CPU bound to the default RX queue | |
3296 | */ | |
3297 | if (txq_number == 1) | |
cad5d847 | 3298 | txq_map = (cpu == elected_cpu) ? |
50bf8cb6 GC |
3299 | MVNETA_CPU_TXQ_ACCESS(1) : 0; |
3300 | else | |
3301 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
3302 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
3303 | ||
2dcf75e2 GC |
3304 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
3305 | ||
3306 | /* Update the interrupt mask on each CPU according the | |
3307 | * new mapping | |
3308 | */ | |
3309 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
3310 | pp, true); | |
f8642885 | 3311 | i++; |
2dcf75e2 | 3312 | |
f8642885 MR |
3313 | } |
3314 | }; | |
3315 | ||
3316 | static int mvneta_percpu_notifier(struct notifier_block *nfb, | |
3317 | unsigned long action, void *hcpu) | |
3318 | { | |
3319 | struct mvneta_port *pp = container_of(nfb, struct mvneta_port, | |
3320 | cpu_notifier); | |
3321 | int cpu = (unsigned long)hcpu, other_cpu; | |
3322 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
3323 | ||
3324 | switch (action) { | |
3325 | case CPU_ONLINE: | |
3326 | case CPU_ONLINE_FROZEN: | |
0df83e7a AMG |
3327 | case CPU_DOWN_FAILED: |
3328 | case CPU_DOWN_FAILED_FROZEN: | |
120cfa50 GC |
3329 | spin_lock(&pp->lock); |
3330 | /* Configuring the driver for a new CPU while the | |
3331 | * driver is stopping is racy, so just avoid it. | |
3332 | */ | |
3333 | if (pp->is_stopped) { | |
3334 | spin_unlock(&pp->lock); | |
3335 | break; | |
3336 | } | |
f8642885 MR |
3337 | netif_tx_stop_all_queues(pp->dev); |
3338 | ||
3339 | /* We have to synchronise on tha napi of each CPU | |
3340 | * except the one just being waked up | |
3341 | */ | |
3342 | for_each_online_cpu(other_cpu) { | |
3343 | if (other_cpu != cpu) { | |
3344 | struct mvneta_pcpu_port *other_port = | |
3345 | per_cpu_ptr(pp->ports, other_cpu); | |
3346 | ||
3347 | napi_synchronize(&other_port->napi); | |
3348 | } | |
3349 | } | |
3350 | ||
3351 | /* Mask all ethernet port interrupts */ | |
db488c10 | 3352 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
f8642885 MR |
3353 | napi_enable(&port->napi); |
3354 | ||
2dcf75e2 GC |
3355 | |
3356 | /* Enable per-CPU interrupts on the CPU that is | |
3357 | * brought up. | |
3358 | */ | |
0e28bf93 | 3359 | mvneta_percpu_enable(pp); |
2dcf75e2 | 3360 | |
f8642885 MR |
3361 | /* Enable per-CPU interrupt on the one CPU we care |
3362 | * about. | |
3363 | */ | |
3364 | mvneta_percpu_elect(pp); | |
3365 | ||
db488c10 GC |
3366 | /* Unmask all ethernet port interrupts */ |
3367 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); | |
f8642885 MR |
3368 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3369 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3370 | MVNETA_CAUSE_LINK_CHANGE | | |
3371 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
3372 | netif_tx_start_all_queues(pp->dev); | |
120cfa50 | 3373 | spin_unlock(&pp->lock); |
f8642885 MR |
3374 | break; |
3375 | case CPU_DOWN_PREPARE: | |
3376 | case CPU_DOWN_PREPARE_FROZEN: | |
3377 | netif_tx_stop_all_queues(pp->dev); | |
5888511e GC |
3378 | /* Thanks to this lock we are sure that any pending |
3379 | * cpu election is done | |
3380 | */ | |
3381 | spin_lock(&pp->lock); | |
f8642885 | 3382 | /* Mask all ethernet port interrupts */ |
db488c10 | 3383 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
5888511e | 3384 | spin_unlock(&pp->lock); |
f8642885 MR |
3385 | |
3386 | napi_synchronize(&port->napi); | |
3387 | napi_disable(&port->napi); | |
3388 | /* Disable per-CPU interrupts on the CPU that is | |
3389 | * brought down. | |
3390 | */ | |
0e28bf93 | 3391 | mvneta_percpu_disable(pp); |
f8642885 MR |
3392 | |
3393 | break; | |
3394 | case CPU_DEAD: | |
3395 | case CPU_DEAD_FROZEN: | |
3396 | /* Check if a new CPU must be elected now this on is down */ | |
120cfa50 | 3397 | spin_lock(&pp->lock); |
f8642885 | 3398 | mvneta_percpu_elect(pp); |
120cfa50 | 3399 | spin_unlock(&pp->lock); |
f8642885 | 3400 | /* Unmask all ethernet port interrupts */ |
db488c10 | 3401 | on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); |
f8642885 MR |
3402 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
3403 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
3404 | MVNETA_CAUSE_LINK_CHANGE | | |
3405 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
3406 | netif_tx_start_all_queues(pp->dev); | |
3407 | break; | |
3408 | } | |
3409 | ||
3410 | return NOTIFY_OK; | |
3411 | } | |
3412 | ||
c5aff182 TP |
3413 | static int mvneta_open(struct net_device *dev) |
3414 | { | |
3415 | struct mvneta_port *pp = netdev_priv(dev); | |
6b125d63 | 3416 | int ret; |
c5aff182 | 3417 | |
c5aff182 | 3418 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
8ec2cd48 | 3419 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
3420 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
3421 | |
3422 | ret = mvneta_setup_rxqs(pp); | |
3423 | if (ret) | |
3424 | return ret; | |
3425 | ||
3426 | ret = mvneta_setup_txqs(pp); | |
3427 | if (ret) | |
3428 | goto err_cleanup_rxqs; | |
3429 | ||
3430 | /* Connect to port interrupt line */ | |
12bb03b4 MR |
3431 | ret = request_percpu_irq(pp->dev->irq, mvneta_isr, |
3432 | MVNETA_DRIVER_NAME, pp->ports); | |
c5aff182 TP |
3433 | if (ret) { |
3434 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
3435 | goto err_cleanup_txqs; | |
3436 | } | |
3437 | ||
2dcf75e2 GC |
3438 | /* Enable per-CPU interrupt on all the CPU to handle our RX |
3439 | * queue interrupts | |
3440 | */ | |
6b125d63 | 3441 | on_each_cpu(mvneta_percpu_enable, pp, true); |
2dcf75e2 | 3442 | |
120cfa50 | 3443 | pp->is_stopped = false; |
f8642885 MR |
3444 | /* Register a CPU notifier to handle the case where our CPU |
3445 | * might be taken offline. | |
3446 | */ | |
3447 | register_cpu_notifier(&pp->cpu_notifier); | |
3448 | ||
c5aff182 TP |
3449 | /* In default link is down */ |
3450 | netif_carrier_off(pp->dev); | |
3451 | ||
3452 | ret = mvneta_mdio_probe(pp); | |
3453 | if (ret < 0) { | |
3454 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
3455 | goto err_free_irq; | |
3456 | } | |
3457 | ||
3458 | mvneta_start_dev(pp); | |
3459 | ||
3460 | return 0; | |
3461 | ||
3462 | err_free_irq: | |
3d8c4530 RKAL |
3463 | unregister_cpu_notifier(&pp->cpu_notifier); |
3464 | on_each_cpu(mvneta_percpu_disable, pp, true); | |
12bb03b4 | 3465 | free_percpu_irq(pp->dev->irq, pp->ports); |
c5aff182 TP |
3466 | err_cleanup_txqs: |
3467 | mvneta_cleanup_txqs(pp); | |
3468 | err_cleanup_rxqs: | |
3469 | mvneta_cleanup_rxqs(pp); | |
3470 | return ret; | |
3471 | } | |
3472 | ||
3473 | /* Stop the port, free port interrupt line */ | |
3474 | static int mvneta_stop(struct net_device *dev) | |
3475 | { | |
3476 | struct mvneta_port *pp = netdev_priv(dev); | |
3477 | ||
120cfa50 | 3478 | /* Inform that we are stopping so we don't want to setup the |
1c2722a9 GC |
3479 | * driver for new CPUs in the notifiers. The code of the |
3480 | * notifier for CPU online is protected by the same spinlock, | |
3481 | * so when we get the lock, the notifer work is done. | |
120cfa50 GC |
3482 | */ |
3483 | spin_lock(&pp->lock); | |
3484 | pp->is_stopped = true; | |
1c2722a9 GC |
3485 | spin_unlock(&pp->lock); |
3486 | ||
c5aff182 TP |
3487 | mvneta_stop_dev(pp); |
3488 | mvneta_mdio_remove(pp); | |
f8642885 | 3489 | unregister_cpu_notifier(&pp->cpu_notifier); |
129219e4 | 3490 | on_each_cpu(mvneta_percpu_disable, pp, true); |
12bb03b4 | 3491 | free_percpu_irq(dev->irq, pp->ports); |
c5aff182 TP |
3492 | mvneta_cleanup_rxqs(pp); |
3493 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
3494 | |
3495 | return 0; | |
3496 | } | |
3497 | ||
15f59456 TP |
3498 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3499 | { | |
c6c022e3 | 3500 | if (!dev->phydev) |
15f59456 TP |
3501 | return -ENOTSUPP; |
3502 | ||
c6c022e3 | 3503 | return phy_mii_ioctl(dev->phydev, ifr, cmd); |
15f59456 TP |
3504 | } |
3505 | ||
c5aff182 TP |
3506 | /* Ethtool methods */ |
3507 | ||
013ad40d PR |
3508 | /* Set link ksettings (phy address, speed) for ethtools */ |
3509 | int mvneta_ethtool_set_link_ksettings(struct net_device *ndev, | |
3510 | const struct ethtool_link_ksettings *cmd) | |
c5aff182 | 3511 | { |
013ad40d PR |
3512 | struct mvneta_port *pp = netdev_priv(ndev); |
3513 | struct phy_device *phydev = ndev->phydev; | |
c5aff182 | 3514 | |
0c0744fc | 3515 | if (!phydev) |
c5aff182 TP |
3516 | return -ENODEV; |
3517 | ||
013ad40d | 3518 | if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) { |
0c0744fc SS |
3519 | u32 val; |
3520 | ||
013ad40d | 3521 | mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE); |
0c0744fc | 3522 | |
013ad40d | 3523 | if (cmd->base.autoneg == AUTONEG_DISABLE) { |
0c0744fc SS |
3524 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); |
3525 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3526 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3527 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); | |
3528 | ||
3529 | if (phydev->duplex) | |
3530 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3531 | ||
3532 | if (phydev->speed == SPEED_1000) | |
3533 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
3534 | else if (phydev->speed == SPEED_100) | |
3535 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
3536 | ||
3537 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3538 | } | |
3539 | ||
013ad40d | 3540 | pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE); |
0c0744fc SS |
3541 | netdev_info(pp->dev, "autoneg status set to %i\n", |
3542 | pp->use_inband_status); | |
3543 | ||
013ad40d | 3544 | if (netif_running(ndev)) { |
0c0744fc SS |
3545 | mvneta_port_down(pp); |
3546 | mvneta_port_up(pp); | |
3547 | } | |
3548 | } | |
3549 | ||
013ad40d | 3550 | return phy_ethtool_ksettings_set(ndev->phydev, cmd); |
c5aff182 TP |
3551 | } |
3552 | ||
3553 | /* Set interrupt coalescing for ethtools */ | |
3554 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
3555 | struct ethtool_coalesce *c) | |
3556 | { | |
3557 | struct mvneta_port *pp = netdev_priv(dev); | |
3558 | int queue; | |
3559 | ||
3560 | for (queue = 0; queue < rxq_number; queue++) { | |
3561 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3562 | rxq->time_coal = c->rx_coalesce_usecs; | |
3563 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
3564 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3565 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3566 | } | |
3567 | ||
3568 | for (queue = 0; queue < txq_number; queue++) { | |
3569 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3570 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
3571 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3572 | } | |
3573 | ||
3574 | return 0; | |
3575 | } | |
3576 | ||
3577 | /* get coalescing for ethtools */ | |
3578 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
3579 | struct ethtool_coalesce *c) | |
3580 | { | |
3581 | struct mvneta_port *pp = netdev_priv(dev); | |
3582 | ||
3583 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
3584 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
3585 | ||
3586 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
3587 | return 0; | |
3588 | } | |
3589 | ||
3590 | ||
3591 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
3592 | struct ethtool_drvinfo *drvinfo) | |
3593 | { | |
3594 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
3595 | sizeof(drvinfo->driver)); | |
3596 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
3597 | sizeof(drvinfo->version)); | |
3598 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
3599 | sizeof(drvinfo->bus_info)); | |
3600 | } | |
3601 | ||
3602 | ||
3603 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
3604 | struct ethtool_ringparam *ring) | |
3605 | { | |
3606 | struct mvneta_port *pp = netdev_priv(netdev); | |
3607 | ||
3608 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
3609 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
3610 | ring->rx_pending = pp->rx_ring_size; | |
3611 | ring->tx_pending = pp->tx_ring_size; | |
3612 | } | |
3613 | ||
3614 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
3615 | struct ethtool_ringparam *ring) | |
3616 | { | |
3617 | struct mvneta_port *pp = netdev_priv(dev); | |
3618 | ||
3619 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
3620 | return -EINVAL; | |
3621 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
3622 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
3623 | |
3624 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
3625 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
3626 | if (pp->tx_ring_size != ring->tx_pending) | |
3627 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
3628 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
3629 | |
3630 | if (netif_running(dev)) { | |
3631 | mvneta_stop(dev); | |
3632 | if (mvneta_open(dev)) { | |
3633 | netdev_err(dev, | |
3634 | "error on opening device after ring param change\n"); | |
3635 | return -ENOMEM; | |
3636 | } | |
3637 | } | |
3638 | ||
3639 | return 0; | |
3640 | } | |
3641 | ||
9b0cdefa RK |
3642 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
3643 | u8 *data) | |
3644 | { | |
3645 | if (sset == ETH_SS_STATS) { | |
3646 | int i; | |
3647 | ||
3648 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3649 | memcpy(data + i * ETH_GSTRING_LEN, | |
3650 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
3651 | } | |
3652 | } | |
3653 | ||
3654 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) | |
3655 | { | |
3656 | const struct mvneta_statistic *s; | |
3657 | void __iomem *base = pp->base; | |
3658 | u32 high, low, val; | |
2c832293 | 3659 | u64 val64; |
9b0cdefa RK |
3660 | int i; |
3661 | ||
3662 | for (i = 0, s = mvneta_statistics; | |
3663 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
3664 | s++, i++) { | |
9b0cdefa RK |
3665 | switch (s->type) { |
3666 | case T_REG_32: | |
3667 | val = readl_relaxed(base + s->offset); | |
2c832293 | 3668 | pp->ethtool_stats[i] += val; |
9b0cdefa RK |
3669 | break; |
3670 | case T_REG_64: | |
3671 | /* Docs say to read low 32-bit then high */ | |
3672 | low = readl_relaxed(base + s->offset); | |
3673 | high = readl_relaxed(base + s->offset + 4); | |
2c832293 JZ |
3674 | val64 = (u64)high << 32 | low; |
3675 | pp->ethtool_stats[i] += val64; | |
9b0cdefa RK |
3676 | break; |
3677 | } | |
9b0cdefa RK |
3678 | } |
3679 | } | |
3680 | ||
3681 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
3682 | struct ethtool_stats *stats, u64 *data) | |
3683 | { | |
3684 | struct mvneta_port *pp = netdev_priv(dev); | |
3685 | int i; | |
3686 | ||
3687 | mvneta_ethtool_update_stats(pp); | |
3688 | ||
3689 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3690 | *data++ = pp->ethtool_stats[i]; | |
3691 | } | |
3692 | ||
3693 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
3694 | { | |
3695 | if (sset == ETH_SS_STATS) | |
3696 | return ARRAY_SIZE(mvneta_statistics); | |
3697 | return -EOPNOTSUPP; | |
3698 | } | |
3699 | ||
9a401dea GC |
3700 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
3701 | { | |
3702 | return MVNETA_RSS_LU_TABLE_SIZE; | |
3703 | } | |
3704 | ||
3705 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
3706 | struct ethtool_rxnfc *info, | |
3707 | u32 *rules __always_unused) | |
3708 | { | |
3709 | switch (info->cmd) { | |
3710 | case ETHTOOL_GRXRINGS: | |
3711 | info->data = rxq_number; | |
3712 | return 0; | |
3713 | case ETHTOOL_GRXFH: | |
3714 | return -EOPNOTSUPP; | |
3715 | default: | |
3716 | return -EOPNOTSUPP; | |
3717 | } | |
3718 | } | |
3719 | ||
3720 | static int mvneta_config_rss(struct mvneta_port *pp) | |
3721 | { | |
3722 | int cpu; | |
3723 | u32 val; | |
3724 | ||
3725 | netif_tx_stop_all_queues(pp->dev); | |
3726 | ||
6b125d63 | 3727 | on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); |
9a401dea GC |
3728 | |
3729 | /* We have to synchronise on the napi of each CPU */ | |
3730 | for_each_online_cpu(cpu) { | |
3731 | struct mvneta_pcpu_port *pcpu_port = | |
3732 | per_cpu_ptr(pp->ports, cpu); | |
3733 | ||
3734 | napi_synchronize(&pcpu_port->napi); | |
3735 | napi_disable(&pcpu_port->napi); | |
3736 | } | |
3737 | ||
3738 | pp->rxq_def = pp->indir[0]; | |
3739 | ||
3740 | /* Update unicast mapping */ | |
3741 | mvneta_set_rx_mode(pp->dev); | |
3742 | ||
3743 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
3744 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
3745 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
3746 | ||
3747 | /* Update the elected CPU matching the new rxq_def */ | |
120cfa50 | 3748 | spin_lock(&pp->lock); |
9a401dea | 3749 | mvneta_percpu_elect(pp); |
120cfa50 | 3750 | spin_unlock(&pp->lock); |
9a401dea GC |
3751 | |
3752 | /* We have to synchronise on the napi of each CPU */ | |
3753 | for_each_online_cpu(cpu) { | |
3754 | struct mvneta_pcpu_port *pcpu_port = | |
3755 | per_cpu_ptr(pp->ports, cpu); | |
3756 | ||
3757 | napi_enable(&pcpu_port->napi); | |
3758 | } | |
3759 | ||
3760 | netif_tx_start_all_queues(pp->dev); | |
3761 | ||
3762 | return 0; | |
3763 | } | |
3764 | ||
3765 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
3766 | const u8 *key, const u8 hfunc) | |
3767 | { | |
3768 | struct mvneta_port *pp = netdev_priv(dev); | |
3769 | /* We require at least one supported parameter to be changed | |
3770 | * and no change in any of the unsupported parameters | |
3771 | */ | |
3772 | if (key || | |
3773 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
3774 | return -EOPNOTSUPP; | |
3775 | ||
3776 | if (!indir) | |
3777 | return 0; | |
3778 | ||
3779 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3780 | ||
3781 | return mvneta_config_rss(pp); | |
3782 | } | |
3783 | ||
3784 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
3785 | u8 *hfunc) | |
3786 | { | |
3787 | struct mvneta_port *pp = netdev_priv(dev); | |
3788 | ||
3789 | if (hfunc) | |
3790 | *hfunc = ETH_RSS_HASH_TOP; | |
3791 | ||
3792 | if (!indir) | |
3793 | return 0; | |
3794 | ||
3795 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3796 | ||
3797 | return 0; | |
3798 | } | |
3799 | ||
c5aff182 TP |
3800 | static const struct net_device_ops mvneta_netdev_ops = { |
3801 | .ndo_open = mvneta_open, | |
3802 | .ndo_stop = mvneta_stop, | |
3803 | .ndo_start_xmit = mvneta_tx, | |
3804 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
3805 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
3806 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 3807 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 3808 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 3809 | .ndo_do_ioctl = mvneta_ioctl, |
c5aff182 TP |
3810 | }; |
3811 | ||
3812 | const struct ethtool_ops mvneta_eth_tool_ops = { | |
3813 | .get_link = ethtool_op_get_link, | |
c5aff182 TP |
3814 | .set_coalesce = mvneta_ethtool_set_coalesce, |
3815 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
3816 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
3817 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
3818 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
9b0cdefa RK |
3819 | .get_strings = mvneta_ethtool_get_strings, |
3820 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
3821 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
3822 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
3823 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
3824 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
3825 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
013ad40d PR |
3826 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
3827 | .set_link_ksettings = mvneta_ethtool_set_link_ksettings, | |
c5aff182 TP |
3828 | }; |
3829 | ||
3830 | /* Initialize hw */ | |
9672850b | 3831 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
3832 | { |
3833 | int queue; | |
3834 | ||
3835 | /* Disable port */ | |
3836 | mvneta_port_disable(pp); | |
3837 | ||
3838 | /* Set port default values */ | |
3839 | mvneta_defaults_set(pp); | |
3840 | ||
9672850b EG |
3841 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), |
3842 | GFP_KERNEL); | |
c5aff182 TP |
3843 | if (!pp->txqs) |
3844 | return -ENOMEM; | |
3845 | ||
3846 | /* Initialize TX descriptor rings */ | |
3847 | for (queue = 0; queue < txq_number; queue++) { | |
3848 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3849 | txq->id = queue; | |
3850 | txq->size = pp->tx_ring_size; | |
3851 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
3852 | } | |
3853 | ||
9672850b EG |
3854 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), |
3855 | GFP_KERNEL); | |
3856 | if (!pp->rxqs) | |
c5aff182 | 3857 | return -ENOMEM; |
c5aff182 TP |
3858 | |
3859 | /* Create Rx descriptor rings */ | |
3860 | for (queue = 0; queue < rxq_number; queue++) { | |
3861 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3862 | rxq->id = queue; | |
3863 | rxq->size = pp->rx_ring_size; | |
3864 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
3865 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
3866 | } | |
3867 | ||
3868 | return 0; | |
3869 | } | |
3870 | ||
c5aff182 | 3871 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
3872 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
3873 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
3874 | { |
3875 | u32 win_enable; | |
3876 | u32 win_protect; | |
3877 | int i; | |
3878 | ||
3879 | for (i = 0; i < 6; i++) { | |
3880 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
3881 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
3882 | ||
3883 | if (i < 4) | |
3884 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
3885 | } | |
3886 | ||
3887 | win_enable = 0x3f; | |
3888 | win_protect = 0; | |
3889 | ||
3890 | for (i = 0; i < dram->num_cs; i++) { | |
3891 | const struct mbus_dram_window *cs = dram->cs + i; | |
3892 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | | |
3893 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); | |
3894 | ||
3895 | mvreg_write(pp, MVNETA_WIN_SIZE(i), | |
3896 | (cs->size - 1) & 0xffff0000); | |
3897 | ||
3898 | win_enable &= ~(1 << i); | |
3899 | win_protect |= 3 << (2 * i); | |
3900 | } | |
3901 | ||
3902 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 3903 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
3904 | } |
3905 | ||
3906 | /* Power up the port */ | |
3f1dd4bc | 3907 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 3908 | { |
3f1dd4bc | 3909 | u32 ctrl; |
c5aff182 TP |
3910 | |
3911 | /* MAC Cause register should be cleared */ | |
3912 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
3913 | ||
3f1dd4bc | 3914 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
c5aff182 | 3915 | |
3f1dd4bc TP |
3916 | /* Even though it might look weird, when we're configured in |
3917 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
3918 | */ | |
3919 | switch(phy_mode) { | |
3920 | case PHY_INTERFACE_MODE_QSGMII: | |
3921 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
3922 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
3923 | break; | |
3924 | case PHY_INTERFACE_MODE_SGMII: | |
3925 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
3926 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
3927 | break; | |
3928 | case PHY_INTERFACE_MODE_RGMII: | |
3929 | case PHY_INTERFACE_MODE_RGMII_ID: | |
3930 | ctrl |= MVNETA_GMAC2_PORT_RGMII; | |
3931 | break; | |
3932 | default: | |
3933 | return -EINVAL; | |
3934 | } | |
c5aff182 TP |
3935 | |
3936 | /* Cancel Port Reset */ | |
3f1dd4bc TP |
3937 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; |
3938 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
c5aff182 TP |
3939 | |
3940 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
3941 | MVNETA_GMAC2_PORT_RESET) != 0) | |
3942 | continue; | |
3f1dd4bc TP |
3943 | |
3944 | return 0; | |
c5aff182 TP |
3945 | } |
3946 | ||
3947 | /* Device initialization routine */ | |
03ce758e | 3948 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 TP |
3949 | { |
3950 | const struct mbus_dram_target_info *dram_target_info; | |
c3f0dd38 | 3951 | struct resource *res; |
c5aff182 TP |
3952 | struct device_node *dn = pdev->dev.of_node; |
3953 | struct device_node *phy_node; | |
dc35a10f | 3954 | struct device_node *bm_node; |
c5aff182 TP |
3955 | struct mvneta_port *pp; |
3956 | struct net_device *dev; | |
8cc3e439 TP |
3957 | const char *dt_mac_addr; |
3958 | char hw_mac_addr[ETH_ALEN]; | |
3959 | const char *mac_from; | |
f8af8e6e | 3960 | const char *managed; |
9110ee07 | 3961 | int tx_csum_limit; |
c5aff182 TP |
3962 | int phy_mode; |
3963 | int err; | |
12bb03b4 | 3964 | int cpu; |
c5aff182 | 3965 | |
ee40a116 | 3966 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
c5aff182 TP |
3967 | if (!dev) |
3968 | return -ENOMEM; | |
3969 | ||
3970 | dev->irq = irq_of_parse_and_map(dn, 0); | |
3971 | if (dev->irq == 0) { | |
3972 | err = -EINVAL; | |
3973 | goto err_free_netdev; | |
3974 | } | |
3975 | ||
3976 | phy_node = of_parse_phandle(dn, "phy", 0); | |
3977 | if (!phy_node) { | |
83895bed TP |
3978 | if (!of_phy_is_fixed_link(dn)) { |
3979 | dev_err(&pdev->dev, "no PHY specified\n"); | |
3980 | err = -ENODEV; | |
3981 | goto err_free_irq; | |
3982 | } | |
3983 | ||
3984 | err = of_phy_register_fixed_link(dn); | |
3985 | if (err < 0) { | |
3986 | dev_err(&pdev->dev, "cannot register fixed PHY\n"); | |
3987 | goto err_free_irq; | |
3988 | } | |
3989 | ||
3990 | /* In the case of a fixed PHY, the DT node associated | |
3991 | * to the PHY is the Ethernet MAC DT node. | |
3992 | */ | |
c891c24c | 3993 | phy_node = of_node_get(dn); |
c5aff182 TP |
3994 | } |
3995 | ||
3996 | phy_mode = of_get_phy_mode(dn); | |
3997 | if (phy_mode < 0) { | |
3998 | dev_err(&pdev->dev, "incorrect phy-mode\n"); | |
3999 | err = -EINVAL; | |
c891c24c | 4000 | goto err_put_phy_node; |
c5aff182 TP |
4001 | } |
4002 | ||
c5aff182 TP |
4003 | dev->tx_queue_len = MVNETA_MAX_TXD; |
4004 | dev->watchdog_timeo = 5 * HZ; | |
4005 | dev->netdev_ops = &mvneta_netdev_ops; | |
4006 | ||
7ad24ea4 | 4007 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 TP |
4008 | |
4009 | pp = netdev_priv(dev); | |
1c2722a9 | 4010 | spin_lock_init(&pp->lock); |
c5aff182 TP |
4011 | pp->phy_node = phy_node; |
4012 | pp->phy_interface = phy_mode; | |
f8af8e6e SS |
4013 | |
4014 | err = of_property_read_string(dn, "managed", &managed); | |
4015 | pp->use_inband_status = (err == 0 && | |
4016 | strcmp(managed, "in-band-status") == 0); | |
f8642885 | 4017 | pp->cpu_notifier.notifier_call = mvneta_percpu_notifier; |
c5aff182 | 4018 | |
90b74c01 GC |
4019 | pp->rxq_def = rxq_def; |
4020 | ||
9a401dea GC |
4021 | pp->indir[0] = rxq_def; |
4022 | ||
2804ba4e JZ |
4023 | pp->clk = devm_clk_get(&pdev->dev, "core"); |
4024 | if (IS_ERR(pp->clk)) | |
4025 | pp->clk = devm_clk_get(&pdev->dev, NULL); | |
189dd626 TP |
4026 | if (IS_ERR(pp->clk)) { |
4027 | err = PTR_ERR(pp->clk); | |
c891c24c | 4028 | goto err_put_phy_node; |
189dd626 TP |
4029 | } |
4030 | ||
4031 | clk_prepare_enable(pp->clk); | |
4032 | ||
15cc4a4a JZ |
4033 | pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); |
4034 | if (!IS_ERR(pp->clk_bus)) | |
4035 | clk_prepare_enable(pp->clk_bus); | |
4036 | ||
c3f0dd38 TP |
4037 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
4038 | pp->base = devm_ioremap_resource(&pdev->dev, res); | |
4039 | if (IS_ERR(pp->base)) { | |
4040 | err = PTR_ERR(pp->base); | |
5445eaf3 APR |
4041 | goto err_clk; |
4042 | } | |
4043 | ||
12bb03b4 MR |
4044 | /* Alloc per-cpu port structure */ |
4045 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
4046 | if (!pp->ports) { | |
4047 | err = -ENOMEM; | |
4048 | goto err_clk; | |
4049 | } | |
4050 | ||
74c41b04 | 4051 | /* Alloc per-cpu stats */ |
1c213bd2 | 4052 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 4053 | if (!pp->stats) { |
4054 | err = -ENOMEM; | |
12bb03b4 | 4055 | goto err_free_ports; |
74c41b04 | 4056 | } |
4057 | ||
8cc3e439 | 4058 | dt_mac_addr = of_get_mac_address(dn); |
6c7a9a3c | 4059 | if (dt_mac_addr) { |
8cc3e439 TP |
4060 | mac_from = "device tree"; |
4061 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); | |
4062 | } else { | |
4063 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
4064 | if (is_valid_ether_addr(hw_mac_addr)) { | |
4065 | mac_from = "hardware"; | |
4066 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
4067 | } else { | |
4068 | mac_from = "random"; | |
4069 | eth_hw_addr_random(dev); | |
4070 | } | |
4071 | } | |
4072 | ||
9110ee07 MW |
4073 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
4074 | if (tx_csum_limit < 0 || | |
4075 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
4076 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4077 | dev_info(&pdev->dev, | |
4078 | "Wrong TX csum limit in DT, set to %dB\n", | |
4079 | MVNETA_TX_CSUM_DEF_SIZE); | |
4080 | } | |
4081 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
4082 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
4083 | } else { | |
4084 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
4085 | } | |
4086 | ||
4087 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 4088 | |
dc35a10f MW |
4089 | dram_target_info = mv_mbus_dram_info(); |
4090 | if (dram_target_info) | |
4091 | mvneta_conf_mbus_windows(pp, dram_target_info); | |
4092 | ||
c5aff182 TP |
4093 | pp->tx_ring_size = MVNETA_MAX_TXD; |
4094 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
4095 | ||
4096 | pp->dev = dev; | |
4097 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4098 | ||
dc35a10f MW |
4099 | pp->id = global_port_id++; |
4100 | ||
4101 | /* Obtain access to BM resources if enabled and already initialized */ | |
4102 | bm_node = of_parse_phandle(dn, "buffer-manager", 0); | |
4103 | if (bm_node && bm_node->data) { | |
4104 | pp->bm_priv = bm_node->data; | |
4105 | err = mvneta_bm_port_init(pdev, pp); | |
4106 | if (err < 0) { | |
4107 | dev_info(&pdev->dev, "use SW buffer management\n"); | |
4108 | pp->bm_priv = NULL; | |
4109 | } | |
4110 | } | |
d4e4da00 | 4111 | of_node_put(bm_node); |
dc35a10f | 4112 | |
9672850b EG |
4113 | err = mvneta_init(&pdev->dev, pp); |
4114 | if (err < 0) | |
dc35a10f | 4115 | goto err_netdev; |
3f1dd4bc TP |
4116 | |
4117 | err = mvneta_port_power_up(pp, phy_mode); | |
4118 | if (err < 0) { | |
4119 | dev_err(&pdev->dev, "can't power up port\n"); | |
dc35a10f | 4120 | goto err_netdev; |
3f1dd4bc | 4121 | } |
c5aff182 | 4122 | |
12bb03b4 MR |
4123 | for_each_present_cpu(cpu) { |
4124 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
4125 | ||
4126 | netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
4127 | port->pp = pp; | |
4128 | } | |
c5aff182 | 4129 | |
2adb719d | 4130 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
01ef26ca EG |
4131 | dev->hw_features |= dev->features; |
4132 | dev->vlan_features |= dev->features; | |
928b6519 | 4133 | dev->priv_flags |= IFF_UNICAST_FLT | IFF_LIVE_ADDR_CHANGE; |
8eef5f97 | 4134 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 4135 | |
c5aff182 TP |
4136 | err = register_netdev(dev); |
4137 | if (err < 0) { | |
4138 | dev_err(&pdev->dev, "failed to register\n"); | |
9672850b | 4139 | goto err_free_stats; |
c5aff182 TP |
4140 | } |
4141 | ||
8cc3e439 TP |
4142 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
4143 | dev->dev_addr); | |
c5aff182 TP |
4144 | |
4145 | platform_set_drvdata(pdev, pp->dev); | |
4146 | ||
898b2970 SS |
4147 | if (pp->use_inband_status) { |
4148 | struct phy_device *phy = of_phy_find_device(dn); | |
4149 | ||
4150 | mvneta_fixed_link_update(pp, phy); | |
04d53b20 | 4151 | |
e5a03bfd | 4152 | put_device(&phy->mdio.dev); |
898b2970 SS |
4153 | } |
4154 | ||
c5aff182 TP |
4155 | return 0; |
4156 | ||
dc35a10f MW |
4157 | err_netdev: |
4158 | unregister_netdev(dev); | |
4159 | if (pp->bm_priv) { | |
4160 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
4161 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
4162 | 1 << pp->id); | |
4163 | } | |
74c41b04 | 4164 | err_free_stats: |
4165 | free_percpu(pp->stats); | |
12bb03b4 MR |
4166 | err_free_ports: |
4167 | free_percpu(pp->ports); | |
5445eaf3 | 4168 | err_clk: |
15cc4a4a | 4169 | clk_disable_unprepare(pp->clk_bus); |
5445eaf3 | 4170 | clk_disable_unprepare(pp->clk); |
c891c24c UKK |
4171 | err_put_phy_node: |
4172 | of_node_put(phy_node); | |
c5aff182 TP |
4173 | err_free_irq: |
4174 | irq_dispose_mapping(dev->irq); | |
4175 | err_free_netdev: | |
4176 | free_netdev(dev); | |
4177 | return err; | |
4178 | } | |
4179 | ||
4180 | /* Device removal routine */ | |
03ce758e | 4181 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
4182 | { |
4183 | struct net_device *dev = platform_get_drvdata(pdev); | |
4184 | struct mvneta_port *pp = netdev_priv(dev); | |
4185 | ||
4186 | unregister_netdev(dev); | |
15cc4a4a | 4187 | clk_disable_unprepare(pp->clk_bus); |
189dd626 | 4188 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 4189 | free_percpu(pp->ports); |
74c41b04 | 4190 | free_percpu(pp->stats); |
c5aff182 | 4191 | irq_dispose_mapping(dev->irq); |
c891c24c | 4192 | of_node_put(pp->phy_node); |
c5aff182 TP |
4193 | free_netdev(dev); |
4194 | ||
dc35a10f MW |
4195 | if (pp->bm_priv) { |
4196 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); | |
4197 | mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, | |
4198 | 1 << pp->id); | |
4199 | } | |
4200 | ||
c5aff182 TP |
4201 | return 0; |
4202 | } | |
4203 | ||
4204 | static const struct of_device_id mvneta_match[] = { | |
4205 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 4206 | { .compatible = "marvell,armada-xp-neta" }, |
c5aff182 TP |
4207 | { } |
4208 | }; | |
4209 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
4210 | ||
4211 | static struct platform_driver mvneta_driver = { | |
4212 | .probe = mvneta_probe, | |
03ce758e | 4213 | .remove = mvneta_remove, |
c5aff182 TP |
4214 | .driver = { |
4215 | .name = MVNETA_DRIVER_NAME, | |
4216 | .of_match_table = mvneta_match, | |
4217 | }, | |
4218 | }; | |
4219 | ||
4220 | module_platform_driver(mvneta_driver); | |
4221 | ||
4222 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
4223 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
4224 | MODULE_LICENSE("GPL"); | |
4225 | ||
4226 | module_param(rxq_number, int, S_IRUGO); | |
4227 | module_param(txq_number, int, S_IRUGO); | |
4228 | ||
4229 | module_param(rxq_def, int, S_IRUGO); | |
f19fadfc | 4230 | module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); |