Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
47a38e15 | 34 | #include <linux/bpf.h> |
c27a02cd YP |
35 | #include <linux/etherdevice.h> |
36 | #include <linux/tcp.h> | |
37 | #include <linux/if_vlan.h> | |
38 | #include <linux/delay.h> | |
5a0e3ad6 | 39 | #include <linux/slab.h> |
1eb8c695 AV |
40 | #include <linux/hash.h> |
41 | #include <net/ip.h> | |
076bb0c8 | 42 | #include <net/busy_poll.h> |
1b136de1 | 43 | #include <net/vxlan.h> |
09d4d087 | 44 | #include <net/devlink.h> |
c27a02cd YP |
45 | |
46 | #include <linux/mlx4/driver.h> | |
47 | #include <linux/mlx4/device.h> | |
48 | #include <linux/mlx4/cmd.h> | |
49 | #include <linux/mlx4/cq.h> | |
50 | ||
51 | #include "mlx4_en.h" | |
52 | #include "en_port.h" | |
53 | ||
d317966b | 54 | int mlx4_en_setup_tc(struct net_device *dev, u8 up) |
897d7846 | 55 | { |
bc6a4744 AV |
56 | struct mlx4_en_priv *priv = netdev_priv(dev); |
57 | int i; | |
d317966b | 58 | unsigned int offset = 0; |
bc6a4744 AV |
59 | |
60 | if (up && up != MLX4_EN_NUM_UP) | |
897d7846 AV |
61 | return -EINVAL; |
62 | ||
bc6a4744 AV |
63 | netdev_set_num_tc(dev, up); |
64 | ||
65 | /* Partition Tx queues evenly amongst UP's */ | |
bc6a4744 | 66 | for (i = 0; i < up; i++) { |
d317966b AV |
67 | netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset); |
68 | offset += priv->num_tx_rings_p_up; | |
bc6a4744 AV |
69 | } |
70 | ||
af7d5185 RS |
71 | #ifdef CONFIG_MLX4_EN_DCB |
72 | if (!mlx4_is_slave(priv->mdev->dev)) { | |
73 | if (up) { | |
564ed9b1 TT |
74 | if (priv->dcbx_cap) |
75 | priv->flags |= MLX4_EN_FLAG_DCB_ENABLED; | |
af7d5185 RS |
76 | } else { |
77 | priv->flags &= ~MLX4_EN_FLAG_DCB_ENABLED; | |
564ed9b1 | 78 | priv->cee_config.pfc_state = false; |
af7d5185 RS |
79 | } |
80 | } | |
81 | #endif /* CONFIG_MLX4_EN_DCB */ | |
82 | ||
897d7846 AV |
83 | return 0; |
84 | } | |
85 | ||
16e5cc64 JF |
86 | static int __mlx4_en_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
87 | struct tc_to_netdev *tc) | |
e4c6734e | 88 | { |
5eb4dce3 | 89 | if (tc->type != TC_SETUP_MQPRIO) |
e4c6734e JF |
90 | return -EINVAL; |
91 | ||
16e5cc64 | 92 | return mlx4_en_setup_tc(dev, tc->tc); |
e4c6734e JF |
93 | } |
94 | ||
1eb8c695 AV |
95 | #ifdef CONFIG_RFS_ACCEL |
96 | ||
97 | struct mlx4_en_filter { | |
98 | struct list_head next; | |
99 | struct work_struct work; | |
100 | ||
75a353d4 | 101 | u8 ip_proto; |
1eb8c695 AV |
102 | __be32 src_ip; |
103 | __be32 dst_ip; | |
104 | __be16 src_port; | |
105 | __be16 dst_port; | |
106 | ||
107 | int rxq_index; | |
108 | struct mlx4_en_priv *priv; | |
109 | u32 flow_id; /* RFS infrastructure id */ | |
110 | int id; /* mlx4_en driver id */ | |
111 | u64 reg_id; /* Flow steering API id */ | |
112 | u8 activated; /* Used to prevent expiry before filter | |
113 | * is attached | |
114 | */ | |
115 | struct hlist_node filter_chain; | |
116 | }; | |
117 | ||
118 | static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv); | |
119 | ||
75a353d4 EP |
120 | static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto) |
121 | { | |
122 | switch (ip_proto) { | |
123 | case IPPROTO_UDP: | |
124 | return MLX4_NET_TRANS_RULE_ID_UDP; | |
125 | case IPPROTO_TCP: | |
126 | return MLX4_NET_TRANS_RULE_ID_TCP; | |
127 | default: | |
c3ca5205 | 128 | return MLX4_NET_TRANS_RULE_NUM; |
75a353d4 EP |
129 | } |
130 | }; | |
131 | ||
1eb8c695 AV |
132 | static void mlx4_en_filter_work(struct work_struct *work) |
133 | { | |
134 | struct mlx4_en_filter *filter = container_of(work, | |
135 | struct mlx4_en_filter, | |
136 | work); | |
137 | struct mlx4_en_priv *priv = filter->priv; | |
75a353d4 EP |
138 | struct mlx4_spec_list spec_tcp_udp = { |
139 | .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto), | |
1eb8c695 AV |
140 | { |
141 | .tcp_udp = { | |
142 | .dst_port = filter->dst_port, | |
143 | .dst_port_msk = (__force __be16)-1, | |
144 | .src_port = filter->src_port, | |
145 | .src_port_msk = (__force __be16)-1, | |
146 | }, | |
147 | }, | |
148 | }; | |
149 | struct mlx4_spec_list spec_ip = { | |
150 | .id = MLX4_NET_TRANS_RULE_ID_IPV4, | |
151 | { | |
152 | .ipv4 = { | |
153 | .dst_ip = filter->dst_ip, | |
154 | .dst_ip_msk = (__force __be32)-1, | |
155 | .src_ip = filter->src_ip, | |
156 | .src_ip_msk = (__force __be32)-1, | |
157 | }, | |
158 | }, | |
159 | }; | |
160 | struct mlx4_spec_list spec_eth = { | |
161 | .id = MLX4_NET_TRANS_RULE_ID_ETH, | |
162 | }; | |
163 | struct mlx4_net_trans_rule rule = { | |
164 | .list = LIST_HEAD_INIT(rule.list), | |
165 | .queue_mode = MLX4_NET_TRANS_Q_LIFO, | |
166 | .exclusive = 1, | |
167 | .allow_loopback = 1, | |
f9162539 | 168 | .promisc_mode = MLX4_FS_REGULAR, |
1eb8c695 AV |
169 | .port = priv->port, |
170 | .priority = MLX4_DOMAIN_RFS, | |
171 | }; | |
172 | int rc; | |
1eb8c695 AV |
173 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); |
174 | ||
c3ca5205 | 175 | if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) { |
75a353d4 EP |
176 | en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n", |
177 | filter->ip_proto); | |
178 | goto ignore; | |
179 | } | |
1eb8c695 AV |
180 | list_add_tail(&spec_eth.list, &rule.list); |
181 | list_add_tail(&spec_ip.list, &rule.list); | |
75a353d4 | 182 | list_add_tail(&spec_tcp_udp.list, &rule.list); |
1eb8c695 | 183 | |
1eb8c695 | 184 | rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn; |
6bbb6d99 | 185 | memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN); |
1eb8c695 AV |
186 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); |
187 | ||
188 | filter->activated = 0; | |
189 | ||
190 | if (filter->reg_id) { | |
191 | rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id); | |
192 | if (rc && rc != -ENOENT) | |
193 | en_err(priv, "Error detaching flow. rc = %d\n", rc); | |
194 | } | |
195 | ||
196 | rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id); | |
197 | if (rc) | |
198 | en_err(priv, "Error attaching flow. err = %d\n", rc); | |
199 | ||
75a353d4 | 200 | ignore: |
1eb8c695 AV |
201 | mlx4_en_filter_rfs_expire(priv); |
202 | ||
203 | filter->activated = 1; | |
204 | } | |
205 | ||
206 | static inline struct hlist_head * | |
207 | filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, | |
208 | __be16 src_port, __be16 dst_port) | |
209 | { | |
210 | unsigned long l; | |
211 | int bucket_idx; | |
212 | ||
213 | l = (__force unsigned long)src_port | | |
214 | ((__force unsigned long)dst_port << 2); | |
215 | l ^= (__force unsigned long)(src_ip ^ dst_ip); | |
216 | ||
217 | bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT); | |
218 | ||
219 | return &priv->filter_hash[bucket_idx]; | |
220 | } | |
221 | ||
222 | static struct mlx4_en_filter * | |
223 | mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip, | |
75a353d4 EP |
224 | __be32 dst_ip, u8 ip_proto, __be16 src_port, |
225 | __be16 dst_port, u32 flow_id) | |
1eb8c695 AV |
226 | { |
227 | struct mlx4_en_filter *filter = NULL; | |
228 | ||
229 | filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC); | |
230 | if (!filter) | |
231 | return NULL; | |
232 | ||
233 | filter->priv = priv; | |
234 | filter->rxq_index = rxq_index; | |
235 | INIT_WORK(&filter->work, mlx4_en_filter_work); | |
236 | ||
237 | filter->src_ip = src_ip; | |
238 | filter->dst_ip = dst_ip; | |
75a353d4 | 239 | filter->ip_proto = ip_proto; |
1eb8c695 AV |
240 | filter->src_port = src_port; |
241 | filter->dst_port = dst_port; | |
242 | ||
243 | filter->flow_id = flow_id; | |
244 | ||
ee64c0ee | 245 | filter->id = priv->last_filter_id++ % RPS_NO_FILTER; |
1eb8c695 AV |
246 | |
247 | list_add_tail(&filter->next, &priv->filters); | |
248 | hlist_add_head(&filter->filter_chain, | |
249 | filter_hash_bucket(priv, src_ip, dst_ip, src_port, | |
250 | dst_port)); | |
251 | ||
252 | return filter; | |
253 | } | |
254 | ||
255 | static void mlx4_en_filter_free(struct mlx4_en_filter *filter) | |
256 | { | |
257 | struct mlx4_en_priv *priv = filter->priv; | |
258 | int rc; | |
259 | ||
260 | list_del(&filter->next); | |
261 | ||
262 | rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id); | |
263 | if (rc && rc != -ENOENT) | |
264 | en_err(priv, "Error detaching flow. rc = %d\n", rc); | |
265 | ||
266 | kfree(filter); | |
267 | } | |
268 | ||
269 | static inline struct mlx4_en_filter * | |
270 | mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, | |
75a353d4 | 271 | u8 ip_proto, __be16 src_port, __be16 dst_port) |
1eb8c695 | 272 | { |
1eb8c695 AV |
273 | struct mlx4_en_filter *filter; |
274 | struct mlx4_en_filter *ret = NULL; | |
275 | ||
b67bfe0d | 276 | hlist_for_each_entry(filter, |
1eb8c695 AV |
277 | filter_hash_bucket(priv, src_ip, dst_ip, |
278 | src_port, dst_port), | |
279 | filter_chain) { | |
280 | if (filter->src_ip == src_ip && | |
281 | filter->dst_ip == dst_ip && | |
75a353d4 | 282 | filter->ip_proto == ip_proto && |
1eb8c695 AV |
283 | filter->src_port == src_port && |
284 | filter->dst_port == dst_port) { | |
285 | ret = filter; | |
286 | break; | |
287 | } | |
288 | } | |
289 | ||
290 | return ret; | |
291 | } | |
292 | ||
293 | static int | |
294 | mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
295 | u16 rxq_index, u32 flow_id) | |
296 | { | |
297 | struct mlx4_en_priv *priv = netdev_priv(net_dev); | |
298 | struct mlx4_en_filter *filter; | |
299 | const struct iphdr *ip; | |
300 | const __be16 *ports; | |
75a353d4 | 301 | u8 ip_proto; |
1eb8c695 AV |
302 | __be32 src_ip; |
303 | __be32 dst_ip; | |
304 | __be16 src_port; | |
305 | __be16 dst_port; | |
306 | int nhoff = skb_network_offset(skb); | |
307 | int ret = 0; | |
308 | ||
309 | if (skb->protocol != htons(ETH_P_IP)) | |
310 | return -EPROTONOSUPPORT; | |
311 | ||
312 | ip = (const struct iphdr *)(skb->data + nhoff); | |
313 | if (ip_is_fragment(ip)) | |
314 | return -EPROTONOSUPPORT; | |
315 | ||
75a353d4 EP |
316 | if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP)) |
317 | return -EPROTONOSUPPORT; | |
1eb8c695 AV |
318 | ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl); |
319 | ||
75a353d4 | 320 | ip_proto = ip->protocol; |
1eb8c695 AV |
321 | src_ip = ip->saddr; |
322 | dst_ip = ip->daddr; | |
323 | src_port = ports[0]; | |
324 | dst_port = ports[1]; | |
325 | ||
1eb8c695 | 326 | spin_lock_bh(&priv->filters_lock); |
75a353d4 EP |
327 | filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto, |
328 | src_port, dst_port); | |
1eb8c695 AV |
329 | if (filter) { |
330 | if (filter->rxq_index == rxq_index) | |
331 | goto out; | |
332 | ||
333 | filter->rxq_index = rxq_index; | |
334 | } else { | |
335 | filter = mlx4_en_filter_alloc(priv, rxq_index, | |
75a353d4 | 336 | src_ip, dst_ip, ip_proto, |
1eb8c695 AV |
337 | src_port, dst_port, flow_id); |
338 | if (!filter) { | |
339 | ret = -ENOMEM; | |
340 | goto err; | |
341 | } | |
342 | } | |
343 | ||
344 | queue_work(priv->mdev->workqueue, &filter->work); | |
345 | ||
346 | out: | |
347 | ret = filter->id; | |
348 | err: | |
349 | spin_unlock_bh(&priv->filters_lock); | |
350 | ||
351 | return ret; | |
352 | } | |
353 | ||
41d942d5 | 354 | void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv) |
1eb8c695 AV |
355 | { |
356 | struct mlx4_en_filter *filter, *tmp; | |
357 | LIST_HEAD(del_list); | |
358 | ||
359 | spin_lock_bh(&priv->filters_lock); | |
360 | list_for_each_entry_safe(filter, tmp, &priv->filters, next) { | |
361 | list_move(&filter->next, &del_list); | |
362 | hlist_del(&filter->filter_chain); | |
363 | } | |
364 | spin_unlock_bh(&priv->filters_lock); | |
365 | ||
366 | list_for_each_entry_safe(filter, tmp, &del_list, next) { | |
367 | cancel_work_sync(&filter->work); | |
368 | mlx4_en_filter_free(filter); | |
369 | } | |
370 | } | |
371 | ||
372 | static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv) | |
373 | { | |
374 | struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL; | |
375 | LIST_HEAD(del_list); | |
376 | int i = 0; | |
377 | ||
378 | spin_lock_bh(&priv->filters_lock); | |
379 | list_for_each_entry_safe(filter, tmp, &priv->filters, next) { | |
380 | if (i > MLX4_EN_FILTER_EXPIRY_QUOTA) | |
381 | break; | |
382 | ||
383 | if (filter->activated && | |
384 | !work_pending(&filter->work) && | |
385 | rps_may_expire_flow(priv->dev, | |
386 | filter->rxq_index, filter->flow_id, | |
387 | filter->id)) { | |
388 | list_move(&filter->next, &del_list); | |
389 | hlist_del(&filter->filter_chain); | |
390 | } else | |
391 | last_filter = filter; | |
392 | ||
393 | i++; | |
394 | } | |
395 | ||
396 | if (last_filter && (&last_filter->next != priv->filters.next)) | |
397 | list_move(&priv->filters, &last_filter->next); | |
398 | ||
399 | spin_unlock_bh(&priv->filters_lock); | |
400 | ||
401 | list_for_each_entry_safe(filter, tmp, &del_list, next) | |
402 | mlx4_en_filter_free(filter); | |
403 | } | |
404 | #endif | |
405 | ||
80d5c368 PM |
406 | static int mlx4_en_vlan_rx_add_vid(struct net_device *dev, |
407 | __be16 proto, u16 vid) | |
c27a02cd YP |
408 | { |
409 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
410 | struct mlx4_en_dev *mdev = priv->mdev; | |
411 | int err; | |
4c3eb3ca | 412 | int idx; |
c27a02cd | 413 | |
f1b553fb | 414 | en_dbg(HW, priv, "adding VLAN:%d\n", vid); |
c27a02cd | 415 | |
f1b553fb | 416 | set_bit(vid, priv->active_vlans); |
c27a02cd YP |
417 | |
418 | /* Add VID to port VLAN filter */ | |
419 | mutex_lock(&mdev->state_lock); | |
420 | if (mdev->device_up && priv->port_up) { | |
f1b553fb | 421 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
93c098af | 422 | if (err) { |
453a6082 | 423 | en_err(priv, "Failed configuring VLAN filter\n"); |
93c098af KH |
424 | goto out; |
425 | } | |
c27a02cd | 426 | } |
93c098af KH |
427 | err = mlx4_register_vlan(mdev->dev, priv->port, vid, &idx); |
428 | if (err) | |
429 | en_dbg(HW, priv, "Failed adding vlan %d\n", vid); | |
4c3eb3ca | 430 | |
93c098af KH |
431 | out: |
432 | mutex_unlock(&mdev->state_lock); | |
433 | return err; | |
c27a02cd YP |
434 | } |
435 | ||
80d5c368 PM |
436 | static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev, |
437 | __be16 proto, u16 vid) | |
c27a02cd YP |
438 | { |
439 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
440 | struct mlx4_en_dev *mdev = priv->mdev; | |
93c098af | 441 | int err = 0; |
c27a02cd | 442 | |
f1b553fb | 443 | en_dbg(HW, priv, "Killing VID:%d\n", vid); |
c27a02cd | 444 | |
f1b553fb | 445 | clear_bit(vid, priv->active_vlans); |
c27a02cd YP |
446 | |
447 | /* Remove VID from port VLAN filter */ | |
448 | mutex_lock(&mdev->state_lock); | |
2009d005 | 449 | mlx4_unregister_vlan(mdev->dev, priv->port, vid); |
4c3eb3ca | 450 | |
c27a02cd | 451 | if (mdev->device_up && priv->port_up) { |
f1b553fb | 452 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
c27a02cd | 453 | if (err) |
453a6082 | 454 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd YP |
455 | } |
456 | mutex_unlock(&mdev->state_lock); | |
8e586137 | 457 | |
93c098af | 458 | return err; |
c27a02cd YP |
459 | } |
460 | ||
6bbb6d99 YB |
461 | static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac) |
462 | { | |
bab6a9ea YB |
463 | int i; |
464 | for (i = ETH_ALEN - 1; i >= 0; --i) { | |
6bbb6d99 YB |
465 | dst_mac[i] = src_mac & 0xff; |
466 | src_mac >>= 8; | |
467 | } | |
468 | memset(&dst_mac[ETH_ALEN], 0, 2); | |
469 | } | |
470 | ||
837052d0 OG |
471 | |
472 | static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr, | |
473 | int qpn, u64 *reg_id) | |
474 | { | |
475 | int err; | |
837052d0 | 476 | |
5eff6dad OG |
477 | if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN || |
478 | priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) | |
837052d0 OG |
479 | return 0; /* do nothing */ |
480 | ||
b95089d0 OG |
481 | err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn, |
482 | MLX4_DOMAIN_NIC, reg_id); | |
837052d0 OG |
483 | if (err) { |
484 | en_err(priv, "failed to add vxlan steering rule, err %d\n", err); | |
485 | return err; | |
486 | } | |
487 | en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id); | |
488 | return 0; | |
489 | } | |
490 | ||
491 | ||
16a10ffd YB |
492 | static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv, |
493 | unsigned char *mac, int *qpn, u64 *reg_id) | |
494 | { | |
495 | struct mlx4_en_dev *mdev = priv->mdev; | |
496 | struct mlx4_dev *dev = mdev->dev; | |
497 | int err; | |
498 | ||
499 | switch (dev->caps.steering_mode) { | |
500 | case MLX4_STEERING_MODE_B0: { | |
501 | struct mlx4_qp qp; | |
502 | u8 gid[16] = {0}; | |
503 | ||
504 | qp.qpn = *qpn; | |
505 | memcpy(&gid[10], mac, ETH_ALEN); | |
506 | gid[5] = priv->port; | |
507 | ||
508 | err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH); | |
509 | break; | |
510 | } | |
511 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
512 | struct mlx4_spec_list spec_eth = { {NULL} }; | |
513 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); | |
514 | ||
515 | struct mlx4_net_trans_rule rule = { | |
516 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
517 | .exclusive = 0, | |
518 | .allow_loopback = 1, | |
f9162539 | 519 | .promisc_mode = MLX4_FS_REGULAR, |
16a10ffd YB |
520 | .priority = MLX4_DOMAIN_NIC, |
521 | }; | |
522 | ||
523 | rule.port = priv->port; | |
524 | rule.qpn = *qpn; | |
525 | INIT_LIST_HEAD(&rule.list); | |
526 | ||
527 | spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH; | |
528 | memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN); | |
529 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); | |
530 | list_add_tail(&spec_eth.list, &rule.list); | |
531 | ||
532 | err = mlx4_flow_attach(dev, &rule, reg_id); | |
533 | break; | |
534 | } | |
535 | default: | |
536 | return -EINVAL; | |
537 | } | |
538 | if (err) | |
539 | en_warn(priv, "Failed Attaching Unicast\n"); | |
540 | ||
541 | return err; | |
542 | } | |
543 | ||
544 | static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv, | |
545 | unsigned char *mac, int qpn, u64 reg_id) | |
546 | { | |
547 | struct mlx4_en_dev *mdev = priv->mdev; | |
548 | struct mlx4_dev *dev = mdev->dev; | |
549 | ||
550 | switch (dev->caps.steering_mode) { | |
551 | case MLX4_STEERING_MODE_B0: { | |
552 | struct mlx4_qp qp; | |
553 | u8 gid[16] = {0}; | |
554 | ||
555 | qp.qpn = qpn; | |
556 | memcpy(&gid[10], mac, ETH_ALEN); | |
557 | gid[5] = priv->port; | |
558 | ||
559 | mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH); | |
560 | break; | |
561 | } | |
562 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
563 | mlx4_flow_detach(dev, reg_id); | |
564 | break; | |
565 | } | |
566 | default: | |
567 | en_err(priv, "Invalid steering mode.\n"); | |
568 | } | |
569 | } | |
570 | ||
571 | static int mlx4_en_get_qp(struct mlx4_en_priv *priv) | |
572 | { | |
573 | struct mlx4_en_dev *mdev = priv->mdev; | |
574 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd YB |
575 | int index = 0; |
576 | int err = 0; | |
16a10ffd | 577 | int *qpn = &priv->base_qpn; |
9813337a | 578 | u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr); |
16a10ffd YB |
579 | |
580 | en_dbg(DRV, priv, "Registering MAC: %pM for adding\n", | |
581 | priv->dev->dev_addr); | |
582 | index = mlx4_register_mac(dev, priv->port, mac); | |
583 | if (index < 0) { | |
584 | err = index; | |
585 | en_err(priv, "Failed adding MAC: %pM\n", | |
586 | priv->dev->dev_addr); | |
587 | return err; | |
588 | } | |
589 | ||
590 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { | |
591 | int base_qpn = mlx4_get_base_qpn(dev, priv->port); | |
592 | *qpn = base_qpn + index; | |
593 | return 0; | |
594 | } | |
595 | ||
d57febe1 | 596 | err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP); |
16a10ffd YB |
597 | en_dbg(DRV, priv, "Reserved qp %d\n", *qpn); |
598 | if (err) { | |
599 | en_err(priv, "Failed to reserve qp for mac registration\n"); | |
ba4b87ae IS |
600 | mlx4_unregister_mac(dev, priv->port, mac); |
601 | return err; | |
16a10ffd | 602 | } |
16a10ffd | 603 | |
c07cb4b0 | 604 | return 0; |
16a10ffd YB |
605 | } |
606 | ||
607 | static void mlx4_en_put_qp(struct mlx4_en_priv *priv) | |
608 | { | |
609 | struct mlx4_en_dev *mdev = priv->mdev; | |
610 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd | 611 | int qpn = priv->base_qpn; |
16a10ffd | 612 | |
83a5a6ce | 613 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { |
ba4b87ae | 614 | u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr); |
83a5a6ce YB |
615 | en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n", |
616 | priv->dev->dev_addr); | |
617 | mlx4_unregister_mac(dev, priv->port, mac); | |
618 | } else { | |
83a5a6ce YB |
619 | en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n", |
620 | priv->port, qpn); | |
621 | mlx4_qp_release_range(dev, qpn, 1); | |
622 | priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC; | |
16a10ffd YB |
623 | } |
624 | } | |
625 | ||
626 | static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn, | |
90bbb74a | 627 | unsigned char *new_mac, unsigned char *prev_mac) |
16a10ffd YB |
628 | { |
629 | struct mlx4_en_dev *mdev = priv->mdev; | |
630 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd | 631 | int err = 0; |
9813337a | 632 | u64 new_mac_u64 = mlx4_mac_to_u64(new_mac); |
16a10ffd YB |
633 | |
634 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) { | |
c07cb4b0 YB |
635 | struct hlist_head *bucket; |
636 | unsigned int mac_hash; | |
637 | struct mlx4_mac_entry *entry; | |
b67bfe0d | 638 | struct hlist_node *tmp; |
9813337a | 639 | u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac); |
c07cb4b0 YB |
640 | |
641 | bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]]; | |
b67bfe0d | 642 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { |
c07cb4b0 YB |
643 | if (ether_addr_equal_64bits(entry->mac, prev_mac)) { |
644 | mlx4_en_uc_steer_release(priv, entry->mac, | |
645 | qpn, entry->reg_id); | |
646 | mlx4_unregister_mac(dev, priv->port, | |
647 | prev_mac_u64); | |
648 | hlist_del_rcu(&entry->hlist); | |
649 | synchronize_rcu(); | |
650 | memcpy(entry->mac, new_mac, ETH_ALEN); | |
651 | entry->reg_id = 0; | |
652 | mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX]; | |
653 | hlist_add_head_rcu(&entry->hlist, | |
654 | &priv->mac_hash[mac_hash]); | |
655 | mlx4_register_mac(dev, priv->port, new_mac_u64); | |
656 | err = mlx4_en_uc_steer_add(priv, new_mac, | |
657 | &qpn, | |
658 | &entry->reg_id); | |
2a2083f7 OG |
659 | if (err) |
660 | return err; | |
661 | if (priv->tunnel_reg_id) { | |
662 | mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id); | |
663 | priv->tunnel_reg_id = 0; | |
664 | } | |
665 | err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn, | |
666 | &priv->tunnel_reg_id); | |
c07cb4b0 YB |
667 | return err; |
668 | } | |
669 | } | |
670 | return -EINVAL; | |
16a10ffd YB |
671 | } |
672 | ||
673 | return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64); | |
674 | } | |
675 | ||
2695bab2 NO |
676 | static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv, |
677 | unsigned char new_mac[ETH_ALEN + 2]) | |
c27a02cd | 678 | { |
c27a02cd YP |
679 | int err = 0; |
680 | ||
c27a02cd YP |
681 | if (priv->port_up) { |
682 | /* Remove old MAC and insert the new one */ | |
16a10ffd | 683 | err = mlx4_en_replace_mac(priv, priv->base_qpn, |
2695bab2 | 684 | new_mac, priv->current_mac); |
c27a02cd | 685 | if (err) |
453a6082 | 686 | en_err(priv, "Failed changing HW MAC address\n"); |
c27a02cd | 687 | } else |
48e551ff | 688 | en_dbg(HW, priv, "Port is down while registering mac, exiting...\n"); |
c27a02cd | 689 | |
2695bab2 NO |
690 | if (!err) |
691 | memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac)); | |
ee755324 | 692 | |
bfa8ab47 YB |
693 | return err; |
694 | } | |
695 | ||
696 | static int mlx4_en_set_mac(struct net_device *dev, void *addr) | |
697 | { | |
698 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
699 | struct mlx4_en_dev *mdev = priv->mdev; | |
700 | struct sockaddr *saddr = addr; | |
2695bab2 | 701 | unsigned char new_mac[ETH_ALEN + 2]; |
bfa8ab47 YB |
702 | int err; |
703 | ||
704 | if (!is_valid_ether_addr(saddr->sa_data)) | |
705 | return -EADDRNOTAVAIL; | |
706 | ||
bfa8ab47 | 707 | mutex_lock(&mdev->state_lock); |
2695bab2 NO |
708 | memcpy(new_mac, saddr->sa_data, ETH_ALEN); |
709 | err = mlx4_en_do_set_mac(priv, new_mac); | |
710 | if (!err) | |
711 | memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN); | |
c27a02cd | 712 | mutex_unlock(&mdev->state_lock); |
bfa8ab47 YB |
713 | |
714 | return err; | |
c27a02cd YP |
715 | } |
716 | ||
717 | static void mlx4_en_clear_list(struct net_device *dev) | |
718 | { | |
719 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
6d199937 | 720 | struct mlx4_en_mc_list *tmp, *mc_to_del; |
c27a02cd | 721 | |
6d199937 YP |
722 | list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) { |
723 | list_del(&mc_to_del->list); | |
724 | kfree(mc_to_del); | |
725 | } | |
c27a02cd YP |
726 | } |
727 | ||
728 | static void mlx4_en_cache_mclist(struct net_device *dev) | |
729 | { | |
730 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
22bedad3 | 731 | struct netdev_hw_addr *ha; |
6d199937 | 732 | struct mlx4_en_mc_list *tmp; |
ff6e2163 | 733 | |
0e03567a | 734 | mlx4_en_clear_list(dev); |
6d199937 YP |
735 | netdev_for_each_mc_addr(ha, dev) { |
736 | tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC); | |
737 | if (!tmp) { | |
6d199937 YP |
738 | mlx4_en_clear_list(dev); |
739 | return; | |
740 | } | |
741 | memcpy(tmp->addr, ha->addr, ETH_ALEN); | |
742 | list_add_tail(&tmp->list, &priv->mc_list); | |
743 | } | |
c27a02cd YP |
744 | } |
745 | ||
6d199937 YP |
746 | static void update_mclist_flags(struct mlx4_en_priv *priv, |
747 | struct list_head *dst, | |
748 | struct list_head *src) | |
749 | { | |
750 | struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc; | |
751 | bool found; | |
752 | ||
753 | /* Find all the entries that should be removed from dst, | |
754 | * These are the entries that are not found in src | |
755 | */ | |
756 | list_for_each_entry(dst_tmp, dst, list) { | |
757 | found = false; | |
758 | list_for_each_entry(src_tmp, src, list) { | |
c0623e58 | 759 | if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) { |
6d199937 YP |
760 | found = true; |
761 | break; | |
762 | } | |
763 | } | |
764 | if (!found) | |
765 | dst_tmp->action = MCLIST_REM; | |
766 | } | |
767 | ||
768 | /* Add entries that exist in src but not in dst | |
769 | * mark them as need to add | |
770 | */ | |
771 | list_for_each_entry(src_tmp, src, list) { | |
772 | found = false; | |
773 | list_for_each_entry(dst_tmp, dst, list) { | |
c0623e58 | 774 | if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) { |
6d199937 YP |
775 | dst_tmp->action = MCLIST_NONE; |
776 | found = true; | |
777 | break; | |
778 | } | |
779 | } | |
780 | if (!found) { | |
14f8dc49 JP |
781 | new_mc = kmemdup(src_tmp, |
782 | sizeof(struct mlx4_en_mc_list), | |
6d199937 | 783 | GFP_KERNEL); |
14f8dc49 | 784 | if (!new_mc) |
6d199937 | 785 | return; |
14f8dc49 | 786 | |
6d199937 YP |
787 | new_mc->action = MCLIST_ADD; |
788 | list_add_tail(&new_mc->list, dst); | |
789 | } | |
790 | } | |
791 | } | |
c27a02cd | 792 | |
0eb74fdd | 793 | static void mlx4_en_set_rx_mode(struct net_device *dev) |
c27a02cd YP |
794 | { |
795 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
796 | ||
797 | if (!priv->port_up) | |
798 | return; | |
799 | ||
0eb74fdd | 800 | queue_work(priv->mdev->workqueue, &priv->rx_mode_task); |
c27a02cd YP |
801 | } |
802 | ||
0eb74fdd YB |
803 | static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv, |
804 | struct mlx4_en_dev *mdev) | |
c27a02cd | 805 | { |
c96d97f4 | 806 | int err = 0; |
c27a02cd | 807 | |
0eb74fdd | 808 | if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) { |
c27a02cd | 809 | if (netif_msg_rx_status(priv)) |
0eb74fdd YB |
810 | en_warn(priv, "Entering promiscuous mode\n"); |
811 | priv->flags |= MLX4_EN_FLAG_PROMISC; | |
c27a02cd | 812 | |
0eb74fdd | 813 | /* Enable promiscouos mode */ |
c96d97f4 | 814 | switch (mdev->dev->caps.steering_mode) { |
592e49dd | 815 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
0eb74fdd YB |
816 | err = mlx4_flow_steer_promisc_add(mdev->dev, |
817 | priv->port, | |
818 | priv->base_qpn, | |
f9162539 | 819 | MLX4_FS_ALL_DEFAULT); |
592e49dd | 820 | if (err) |
0eb74fdd YB |
821 | en_err(priv, "Failed enabling promiscuous mode\n"); |
822 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
592e49dd HHZ |
823 | break; |
824 | ||
c96d97f4 | 825 | case MLX4_STEERING_MODE_B0: |
0eb74fdd YB |
826 | err = mlx4_unicast_promisc_add(mdev->dev, |
827 | priv->base_qpn, | |
828 | priv->port); | |
c96d97f4 | 829 | if (err) |
0eb74fdd YB |
830 | en_err(priv, "Failed enabling unicast promiscuous mode\n"); |
831 | ||
832 | /* Add the default qp number as multicast | |
833 | * promisc | |
834 | */ | |
835 | if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) { | |
836 | err = mlx4_multicast_promisc_add(mdev->dev, | |
837 | priv->base_qpn, | |
838 | priv->port); | |
c96d97f4 | 839 | if (err) |
0eb74fdd YB |
840 | en_err(priv, "Failed enabling multicast promiscuous mode\n"); |
841 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
c96d97f4 HHZ |
842 | } |
843 | break; | |
c27a02cd | 844 | |
c96d97f4 HHZ |
845 | case MLX4_STEERING_MODE_A0: |
846 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, | |
847 | priv->port, | |
0eb74fdd YB |
848 | priv->base_qpn, |
849 | 1); | |
1679200f | 850 | if (err) |
0eb74fdd | 851 | en_err(priv, "Failed enabling promiscuous mode\n"); |
c96d97f4 | 852 | break; |
1679200f YP |
853 | } |
854 | ||
0eb74fdd YB |
855 | /* Disable port multicast filter (unconditionally) */ |
856 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
857 | 0, MLX4_MCAST_DISABLE); | |
858 | if (err) | |
859 | en_err(priv, "Failed disabling multicast filter\n"); | |
0eb74fdd YB |
860 | } |
861 | } | |
862 | ||
863 | static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv, | |
864 | struct mlx4_en_dev *mdev) | |
865 | { | |
866 | int err = 0; | |
867 | ||
868 | if (netif_msg_rx_status(priv)) | |
869 | en_warn(priv, "Leaving promiscuous mode\n"); | |
870 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; | |
871 | ||
872 | /* Disable promiscouos mode */ | |
873 | switch (mdev->dev->caps.steering_mode) { | |
874 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
875 | err = mlx4_flow_steer_promisc_remove(mdev->dev, | |
876 | priv->port, | |
f9162539 | 877 | MLX4_FS_ALL_DEFAULT); |
0eb74fdd YB |
878 | if (err) |
879 | en_err(priv, "Failed disabling promiscuous mode\n"); | |
880 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
881 | break; | |
882 | ||
883 | case MLX4_STEERING_MODE_B0: | |
884 | err = mlx4_unicast_promisc_remove(mdev->dev, | |
885 | priv->base_qpn, | |
886 | priv->port); | |
887 | if (err) | |
888 | en_err(priv, "Failed disabling unicast promiscuous mode\n"); | |
889 | /* Disable Multicast promisc */ | |
890 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
891 | err = mlx4_multicast_promisc_remove(mdev->dev, | |
892 | priv->base_qpn, | |
893 | priv->port); | |
894 | if (err) | |
895 | en_err(priv, "Failed disabling multicast promiscuous mode\n"); | |
896 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
897 | } | |
898 | break; | |
899 | ||
900 | case MLX4_STEERING_MODE_A0: | |
901 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, | |
902 | priv->port, | |
903 | priv->base_qpn, 0); | |
904 | if (err) | |
905 | en_err(priv, "Failed disabling promiscuous mode\n"); | |
906 | break; | |
c27a02cd | 907 | } |
0eb74fdd YB |
908 | } |
909 | ||
910 | static void mlx4_en_do_multicast(struct mlx4_en_priv *priv, | |
911 | struct net_device *dev, | |
912 | struct mlx4_en_dev *mdev) | |
913 | { | |
914 | struct mlx4_en_mc_list *mclist, *tmp; | |
915 | u64 mcast_addr = 0; | |
916 | u8 mc_list[16] = {0}; | |
917 | int err = 0; | |
918 | ||
c27a02cd YP |
919 | /* Enable/disable the multicast filter according to IFF_ALLMULTI */ |
920 | if (dev->flags & IFF_ALLMULTI) { | |
921 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
922 | 0, MLX4_MCAST_DISABLE); | |
923 | if (err) | |
453a6082 | 924 | en_err(priv, "Failed disabling multicast filter\n"); |
1679200f YP |
925 | |
926 | /* Add the default qp number as multicast promisc */ | |
927 | if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) { | |
c96d97f4 | 928 | switch (mdev->dev->caps.steering_mode) { |
592e49dd HHZ |
929 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
930 | err = mlx4_flow_steer_promisc_add(mdev->dev, | |
931 | priv->port, | |
932 | priv->base_qpn, | |
f9162539 | 933 | MLX4_FS_MC_DEFAULT); |
592e49dd HHZ |
934 | break; |
935 | ||
c96d97f4 HHZ |
936 | case MLX4_STEERING_MODE_B0: |
937 | err = mlx4_multicast_promisc_add(mdev->dev, | |
938 | priv->base_qpn, | |
939 | priv->port); | |
940 | break; | |
941 | ||
942 | case MLX4_STEERING_MODE_A0: | |
943 | break; | |
944 | } | |
1679200f YP |
945 | if (err) |
946 | en_err(priv, "Failed entering multicast promisc mode\n"); | |
947 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
948 | } | |
c27a02cd | 949 | } else { |
1679200f YP |
950 | /* Disable Multicast promisc */ |
951 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
c96d97f4 | 952 | switch (mdev->dev->caps.steering_mode) { |
592e49dd HHZ |
953 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
954 | err = mlx4_flow_steer_promisc_remove(mdev->dev, | |
955 | priv->port, | |
f9162539 | 956 | MLX4_FS_MC_DEFAULT); |
592e49dd HHZ |
957 | break; |
958 | ||
c96d97f4 HHZ |
959 | case MLX4_STEERING_MODE_B0: |
960 | err = mlx4_multicast_promisc_remove(mdev->dev, | |
961 | priv->base_qpn, | |
962 | priv->port); | |
963 | break; | |
964 | ||
965 | case MLX4_STEERING_MODE_A0: | |
966 | break; | |
967 | } | |
1679200f | 968 | if (err) |
25985edc | 969 | en_err(priv, "Failed disabling multicast promiscuous mode\n"); |
1679200f YP |
970 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; |
971 | } | |
ff6e2163 | 972 | |
c27a02cd YP |
973 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, |
974 | 0, MLX4_MCAST_DISABLE); | |
975 | if (err) | |
453a6082 | 976 | en_err(priv, "Failed disabling multicast filter\n"); |
c27a02cd YP |
977 | |
978 | /* Flush mcast filter and init it with broadcast address */ | |
979 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST, | |
980 | 1, MLX4_MCAST_CONFIG); | |
981 | ||
982 | /* Update multicast list - we cache all addresses so they won't | |
983 | * change while HW is updated holding the command semaphor */ | |
dbd501a8 | 984 | netif_addr_lock_bh(dev); |
c27a02cd | 985 | mlx4_en_cache_mclist(dev); |
dbd501a8 | 986 | netif_addr_unlock_bh(dev); |
6d199937 | 987 | list_for_each_entry(mclist, &priv->mc_list, list) { |
9813337a | 988 | mcast_addr = mlx4_mac_to_u64(mclist->addr); |
c27a02cd YP |
989 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, |
990 | mcast_addr, 0, MLX4_MCAST_CONFIG); | |
991 | } | |
992 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
993 | 0, MLX4_MCAST_ENABLE); | |
994 | if (err) | |
453a6082 | 995 | en_err(priv, "Failed enabling multicast filter\n"); |
6d199937 YP |
996 | |
997 | update_mclist_flags(priv, &priv->curr_list, &priv->mc_list); | |
998 | list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) { | |
999 | if (mclist->action == MCLIST_REM) { | |
1000 | /* detach this address and delete from list */ | |
1001 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
1002 | mc_list[5] = priv->port; | |
1003 | err = mlx4_multicast_detach(mdev->dev, | |
1004 | &priv->rss_map.indir_qp, | |
1005 | mc_list, | |
0ff1fb65 HHZ |
1006 | MLX4_PROT_ETH, |
1007 | mclist->reg_id); | |
6d199937 YP |
1008 | if (err) |
1009 | en_err(priv, "Fail to detach multicast address\n"); | |
1010 | ||
837052d0 OG |
1011 | if (mclist->tunnel_reg_id) { |
1012 | err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id); | |
1013 | if (err) | |
1014 | en_err(priv, "Failed to detach multicast address\n"); | |
1015 | } | |
1016 | ||
6d199937 YP |
1017 | /* remove from list */ |
1018 | list_del(&mclist->list); | |
1019 | kfree(mclist); | |
9c64508a | 1020 | } else if (mclist->action == MCLIST_ADD) { |
6d199937 YP |
1021 | /* attach the address */ |
1022 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
0ff1fb65 | 1023 | /* needed for B0 steering support */ |
6d199937 YP |
1024 | mc_list[5] = priv->port; |
1025 | err = mlx4_multicast_attach(mdev->dev, | |
1026 | &priv->rss_map.indir_qp, | |
0ff1fb65 HHZ |
1027 | mc_list, |
1028 | priv->port, 0, | |
1029 | MLX4_PROT_ETH, | |
1030 | &mclist->reg_id); | |
6d199937 YP |
1031 | if (err) |
1032 | en_err(priv, "Fail to attach multicast address\n"); | |
1033 | ||
837052d0 OG |
1034 | err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn, |
1035 | &mclist->tunnel_reg_id); | |
1036 | if (err) | |
1037 | en_err(priv, "Failed to attach multicast address\n"); | |
6d199937 YP |
1038 | } |
1039 | } | |
c27a02cd | 1040 | } |
0eb74fdd YB |
1041 | } |
1042 | ||
cc5387f7 YB |
1043 | static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv, |
1044 | struct net_device *dev, | |
1045 | struct mlx4_en_dev *mdev) | |
1046 | { | |
1047 | struct netdev_hw_addr *ha; | |
1048 | struct mlx4_mac_entry *entry; | |
b67bfe0d | 1049 | struct hlist_node *tmp; |
cc5387f7 YB |
1050 | bool found; |
1051 | u64 mac; | |
1052 | int err = 0; | |
1053 | struct hlist_head *bucket; | |
1054 | unsigned int i; | |
1055 | int removed = 0; | |
1056 | u32 prev_flags; | |
1057 | ||
1058 | /* Note that we do not need to protect our mac_hash traversal with rcu, | |
1059 | * since all modification code is protected by mdev->state_lock | |
1060 | */ | |
1061 | ||
1062 | /* find what to remove */ | |
1063 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) { | |
1064 | bucket = &priv->mac_hash[i]; | |
b67bfe0d | 1065 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { |
cc5387f7 YB |
1066 | found = false; |
1067 | netdev_for_each_uc_addr(ha, dev) { | |
1068 | if (ether_addr_equal_64bits(entry->mac, | |
1069 | ha->addr)) { | |
1070 | found = true; | |
1071 | break; | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | /* MAC address of the port is not in uc list */ | |
2695bab2 NO |
1076 | if (ether_addr_equal_64bits(entry->mac, |
1077 | priv->current_mac)) | |
cc5387f7 YB |
1078 | found = true; |
1079 | ||
1080 | if (!found) { | |
9813337a | 1081 | mac = mlx4_mac_to_u64(entry->mac); |
cc5387f7 YB |
1082 | mlx4_en_uc_steer_release(priv, entry->mac, |
1083 | priv->base_qpn, | |
1084 | entry->reg_id); | |
1085 | mlx4_unregister_mac(mdev->dev, priv->port, mac); | |
1086 | ||
1087 | hlist_del_rcu(&entry->hlist); | |
1088 | kfree_rcu(entry, rcu); | |
1089 | en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n", | |
1090 | entry->mac, priv->port); | |
1091 | ++removed; | |
1092 | } | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | /* if we didn't remove anything, there is no use in trying to add | |
1097 | * again once we are in a forced promisc mode state | |
1098 | */ | |
1099 | if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed) | |
1100 | return; | |
1101 | ||
1102 | prev_flags = priv->flags; | |
1103 | priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC; | |
1104 | ||
1105 | /* find what to add */ | |
1106 | netdev_for_each_uc_addr(ha, dev) { | |
1107 | found = false; | |
1108 | bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]]; | |
b67bfe0d | 1109 | hlist_for_each_entry(entry, bucket, hlist) { |
cc5387f7 YB |
1110 | if (ether_addr_equal_64bits(entry->mac, ha->addr)) { |
1111 | found = true; | |
1112 | break; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | if (!found) { | |
1117 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
1118 | if (!entry) { | |
1119 | en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n", | |
1120 | ha->addr, priv->port); | |
1121 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1122 | break; | |
1123 | } | |
9813337a | 1124 | mac = mlx4_mac_to_u64(ha->addr); |
cc5387f7 YB |
1125 | memcpy(entry->mac, ha->addr, ETH_ALEN); |
1126 | err = mlx4_register_mac(mdev->dev, priv->port, mac); | |
1127 | if (err < 0) { | |
1128 | en_err(priv, "Failed registering MAC %pM on port %d: %d\n", | |
1129 | ha->addr, priv->port, err); | |
1130 | kfree(entry); | |
1131 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1132 | break; | |
1133 | } | |
1134 | err = mlx4_en_uc_steer_add(priv, ha->addr, | |
1135 | &priv->base_qpn, | |
1136 | &entry->reg_id); | |
1137 | if (err) { | |
1138 | en_err(priv, "Failed adding MAC %pM on port %d: %d\n", | |
1139 | ha->addr, priv->port, err); | |
1140 | mlx4_unregister_mac(mdev->dev, priv->port, mac); | |
1141 | kfree(entry); | |
1142 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1143 | break; | |
1144 | } else { | |
1145 | unsigned int mac_hash; | |
1146 | en_dbg(DRV, priv, "Added MAC %pM on port:%d\n", | |
1147 | ha->addr, priv->port); | |
1148 | mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX]; | |
1149 | bucket = &priv->mac_hash[mac_hash]; | |
1150 | hlist_add_head_rcu(&entry->hlist, bucket); | |
1151 | } | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) { | |
1156 | en_warn(priv, "Forcing promiscuous mode on port:%d\n", | |
1157 | priv->port); | |
1158 | } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) { | |
1159 | en_warn(priv, "Stop forcing promiscuous mode on port:%d\n", | |
1160 | priv->port); | |
1161 | } | |
1162 | } | |
1163 | ||
0eb74fdd YB |
1164 | static void mlx4_en_do_set_rx_mode(struct work_struct *work) |
1165 | { | |
1166 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1167 | rx_mode_task); | |
1168 | struct mlx4_en_dev *mdev = priv->mdev; | |
1169 | struct net_device *dev = priv->dev; | |
1170 | ||
1171 | mutex_lock(&mdev->state_lock); | |
1172 | if (!mdev->device_up) { | |
1173 | en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n"); | |
1174 | goto out; | |
1175 | } | |
1176 | if (!priv->port_up) { | |
1177 | en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n"); | |
1178 | goto out; | |
1179 | } | |
1180 | ||
1181 | if (!netif_carrier_ok(dev)) { | |
1182 | if (!mlx4_en_QUERY_PORT(mdev, priv->port)) { | |
1183 | if (priv->port_state.link_state) { | |
1184 | priv->last_link_state = MLX4_DEV_EVENT_PORT_UP; | |
1185 | netif_carrier_on(dev); | |
1186 | en_dbg(LINK, priv, "Link Up\n"); | |
1187 | } | |
1188 | } | |
1189 | } | |
1190 | ||
cc5387f7 YB |
1191 | if (dev->priv_flags & IFF_UNICAST_FLT) |
1192 | mlx4_en_do_uc_filter(priv, dev, mdev); | |
1193 | ||
0eb74fdd | 1194 | /* Promsicuous mode: disable all filters */ |
cc5387f7 YB |
1195 | if ((dev->flags & IFF_PROMISC) || |
1196 | (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) { | |
0eb74fdd YB |
1197 | mlx4_en_set_promisc_mode(priv, mdev); |
1198 | goto out; | |
1199 | } | |
1200 | ||
1201 | /* Not in promiscuous mode */ | |
1202 | if (priv->flags & MLX4_EN_FLAG_PROMISC) | |
1203 | mlx4_en_clear_promisc_mode(priv, mdev); | |
1204 | ||
1205 | mlx4_en_do_multicast(priv, dev, mdev); | |
c27a02cd YP |
1206 | out: |
1207 | mutex_unlock(&mdev->state_lock); | |
1208 | } | |
1209 | ||
1210 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1211 | static void mlx4_en_netpoll(struct net_device *dev) | |
1212 | { | |
1213 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1214 | struct mlx4_en_cq *cq; | |
c27a02cd YP |
1215 | int i; |
1216 | ||
7d71e994 ED |
1217 | for (i = 0; i < priv->tx_ring_num; i++) { |
1218 | cq = priv->tx_cq[i]; | |
c98235cb | 1219 | napi_schedule(&cq->napi); |
c27a02cd YP |
1220 | } |
1221 | } | |
1222 | #endif | |
1223 | ||
ba4b87ae IS |
1224 | static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv) |
1225 | { | |
1226 | u64 reg_id; | |
1227 | int err = 0; | |
1228 | int *qpn = &priv->base_qpn; | |
1229 | struct mlx4_mac_entry *entry; | |
1230 | ||
1231 | err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, ®_id); | |
1232 | if (err) | |
1233 | return err; | |
1234 | ||
1235 | err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn, | |
1236 | &priv->tunnel_reg_id); | |
1237 | if (err) | |
1238 | goto tunnel_err; | |
1239 | ||
1240 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
1241 | if (!entry) { | |
1242 | err = -ENOMEM; | |
1243 | goto alloc_err; | |
1244 | } | |
1245 | ||
1246 | memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac)); | |
1247 | memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac)); | |
1248 | entry->reg_id = reg_id; | |
1249 | hlist_add_head_rcu(&entry->hlist, | |
1250 | &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]); | |
1251 | ||
1252 | return 0; | |
1253 | ||
1254 | alloc_err: | |
1255 | if (priv->tunnel_reg_id) | |
1256 | mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id); | |
1257 | ||
1258 | tunnel_err: | |
1259 | mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id); | |
1260 | return err; | |
1261 | } | |
1262 | ||
1263 | static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv) | |
1264 | { | |
1265 | u64 mac; | |
1266 | unsigned int i; | |
1267 | int qpn = priv->base_qpn; | |
1268 | struct hlist_head *bucket; | |
1269 | struct hlist_node *tmp; | |
1270 | struct mlx4_mac_entry *entry; | |
1271 | ||
1272 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) { | |
1273 | bucket = &priv->mac_hash[i]; | |
1274 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { | |
1275 | mac = mlx4_mac_to_u64(entry->mac); | |
1276 | en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n", | |
1277 | entry->mac); | |
1278 | mlx4_en_uc_steer_release(priv, entry->mac, | |
1279 | qpn, entry->reg_id); | |
1280 | ||
1281 | mlx4_unregister_mac(priv->mdev->dev, priv->port, mac); | |
1282 | hlist_del_rcu(&entry->hlist); | |
1283 | kfree_rcu(entry, rcu); | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | if (priv->tunnel_reg_id) { | |
1288 | mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id); | |
1289 | priv->tunnel_reg_id = 0; | |
1290 | } | |
1291 | } | |
1292 | ||
c27a02cd YP |
1293 | static void mlx4_en_tx_timeout(struct net_device *dev) |
1294 | { | |
1295 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1296 | struct mlx4_en_dev *mdev = priv->mdev; | |
b944ebec | 1297 | int i; |
c27a02cd YP |
1298 | |
1299 | if (netif_msg_timer(priv)) | |
453a6082 | 1300 | en_warn(priv, "Tx timeout called on port:%d\n", priv->port); |
c27a02cd | 1301 | |
b944ebec YP |
1302 | for (i = 0; i < priv->tx_ring_num; i++) { |
1303 | if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i))) | |
1304 | continue; | |
1305 | en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n", | |
41d942d5 EE |
1306 | i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn, |
1307 | priv->tx_ring[i]->cons, priv->tx_ring[i]->prod); | |
b944ebec YP |
1308 | } |
1309 | ||
1e338db5 | 1310 | priv->port_stats.tx_timeout++; |
453a6082 | 1311 | en_dbg(DRV, priv, "Scheduling watchdog\n"); |
1e338db5 | 1312 | queue_work(mdev->workqueue, &priv->watchdog_task); |
c27a02cd YP |
1313 | } |
1314 | ||
1315 | ||
9ed17db1 ED |
1316 | static struct rtnl_link_stats64 * |
1317 | mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
c27a02cd YP |
1318 | { |
1319 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1320 | ||
1321 | spin_lock_bh(&priv->stats_lock); | |
f73a6f43 | 1322 | netdev_stats_to_stats64(stats, &dev->stats); |
c27a02cd YP |
1323 | spin_unlock_bh(&priv->stats_lock); |
1324 | ||
9ed17db1 | 1325 | return stats; |
c27a02cd YP |
1326 | } |
1327 | ||
1328 | static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv) | |
1329 | { | |
c27a02cd YP |
1330 | struct mlx4_en_cq *cq; |
1331 | int i; | |
1332 | ||
1333 | /* If we haven't received a specific coalescing setting | |
98a1708d | 1334 | * (module param), we set the moderation parameters as follows: |
c27a02cd | 1335 | * - moder_cnt is set to the number of mtu sized packets to |
ecfd2ce1 | 1336 | * satisfy our coalescing target. |
c27a02cd YP |
1337 | * - moder_time is set to a fixed value. |
1338 | */ | |
3db36fb2 | 1339 | priv->rx_frames = MLX4_EN_RX_COAL_TARGET; |
60b9f9e5 | 1340 | priv->rx_usecs = MLX4_EN_RX_COAL_TIME; |
a19a848a YP |
1341 | priv->tx_frames = MLX4_EN_TX_COAL_PKTS; |
1342 | priv->tx_usecs = MLX4_EN_TX_COAL_TIME; | |
48e551ff YB |
1343 | en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n", |
1344 | priv->dev->mtu, priv->rx_frames, priv->rx_usecs); | |
c27a02cd YP |
1345 | |
1346 | /* Setup cq moderation params */ | |
1347 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 1348 | cq = priv->rx_cq[i]; |
c27a02cd YP |
1349 | cq->moder_cnt = priv->rx_frames; |
1350 | cq->moder_time = priv->rx_usecs; | |
6b4d8d9f AG |
1351 | priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; |
1352 | priv->last_moder_packets[i] = 0; | |
1353 | priv->last_moder_bytes[i] = 0; | |
c27a02cd YP |
1354 | } |
1355 | ||
1356 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 | 1357 | cq = priv->tx_cq[i]; |
a19a848a YP |
1358 | cq->moder_cnt = priv->tx_frames; |
1359 | cq->moder_time = priv->tx_usecs; | |
c27a02cd YP |
1360 | } |
1361 | ||
1362 | /* Reset auto-moderation params */ | |
1363 | priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW; | |
1364 | priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW; | |
1365 | priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH; | |
1366 | priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH; | |
1367 | priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL; | |
60b9f9e5 | 1368 | priv->adaptive_rx_coal = 1; |
c27a02cd | 1369 | priv->last_moder_jiffies = 0; |
c27a02cd | 1370 | priv->last_moder_tx_packets = 0; |
c27a02cd YP |
1371 | } |
1372 | ||
1373 | static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv) | |
1374 | { | |
1375 | unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies); | |
c27a02cd YP |
1376 | struct mlx4_en_cq *cq; |
1377 | unsigned long packets; | |
1378 | unsigned long rate; | |
1379 | unsigned long avg_pkt_size; | |
1380 | unsigned long rx_packets; | |
1381 | unsigned long rx_bytes; | |
c27a02cd YP |
1382 | unsigned long rx_pkt_diff; |
1383 | int moder_time; | |
6b4d8d9f | 1384 | int ring, err; |
c27a02cd YP |
1385 | |
1386 | if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ) | |
1387 | return; | |
1388 | ||
6b4d8d9f AG |
1389 | for (ring = 0; ring < priv->rx_ring_num; ring++) { |
1390 | spin_lock_bh(&priv->stats_lock); | |
41d942d5 EE |
1391 | rx_packets = priv->rx_ring[ring]->packets; |
1392 | rx_bytes = priv->rx_ring[ring]->bytes; | |
6b4d8d9f AG |
1393 | spin_unlock_bh(&priv->stats_lock); |
1394 | ||
1395 | rx_pkt_diff = ((unsigned long) (rx_packets - | |
1396 | priv->last_moder_packets[ring])); | |
1397 | packets = rx_pkt_diff; | |
1398 | rate = packets * HZ / period; | |
1399 | avg_pkt_size = packets ? ((unsigned long) (rx_bytes - | |
1400 | priv->last_moder_bytes[ring])) / packets : 0; | |
1401 | ||
1402 | /* Apply auto-moderation only when packet rate | |
1403 | * exceeds a rate that it matters */ | |
1404 | if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) && | |
1405 | avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) { | |
c27a02cd YP |
1406 | if (rate < priv->pkt_rate_low) |
1407 | moder_time = priv->rx_usecs_low; | |
1408 | else if (rate > priv->pkt_rate_high) | |
1409 | moder_time = priv->rx_usecs_high; | |
1410 | else | |
1411 | moder_time = (rate - priv->pkt_rate_low) * | |
1412 | (priv->rx_usecs_high - priv->rx_usecs_low) / | |
1413 | (priv->pkt_rate_high - priv->pkt_rate_low) + | |
1414 | priv->rx_usecs_low; | |
6b4d8d9f AG |
1415 | } else { |
1416 | moder_time = priv->rx_usecs_low; | |
c27a02cd | 1417 | } |
c27a02cd | 1418 | |
6b4d8d9f AG |
1419 | if (moder_time != priv->last_moder_time[ring]) { |
1420 | priv->last_moder_time[ring] = moder_time; | |
41d942d5 | 1421 | cq = priv->rx_cq[ring]; |
c27a02cd | 1422 | cq->moder_time = moder_time; |
a1c6693a | 1423 | cq->moder_cnt = priv->rx_frames; |
c27a02cd | 1424 | err = mlx4_en_set_cq_moder(priv, cq); |
6b4d8d9f | 1425 | if (err) |
48e551ff YB |
1426 | en_err(priv, "Failed modifying moderation for cq:%d\n", |
1427 | ring); | |
c27a02cd | 1428 | } |
6b4d8d9f AG |
1429 | priv->last_moder_packets[ring] = rx_packets; |
1430 | priv->last_moder_bytes[ring] = rx_bytes; | |
c27a02cd YP |
1431 | } |
1432 | ||
c27a02cd YP |
1433 | priv->last_moder_jiffies = jiffies; |
1434 | } | |
1435 | ||
1436 | static void mlx4_en_do_get_stats(struct work_struct *work) | |
1437 | { | |
bf6aede7 | 1438 | struct delayed_work *delay = to_delayed_work(work); |
c27a02cd YP |
1439 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, |
1440 | stats_task); | |
1441 | struct mlx4_en_dev *mdev = priv->mdev; | |
1442 | int err; | |
1443 | ||
c27a02cd YP |
1444 | mutex_lock(&mdev->state_lock); |
1445 | if (mdev->device_up) { | |
6123db2e JM |
1446 | if (priv->port_up) { |
1447 | err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0); | |
1448 | if (err) | |
1449 | en_dbg(HW, priv, "Could not update stats\n"); | |
2d51837f | 1450 | |
c27a02cd | 1451 | mlx4_en_auto_moderation(priv); |
6123db2e | 1452 | } |
c27a02cd YP |
1453 | |
1454 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); | |
1455 | } | |
d7e1a487 | 1456 | if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) { |
2695bab2 | 1457 | mlx4_en_do_set_mac(priv, priv->current_mac); |
d7e1a487 YP |
1458 | mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0; |
1459 | } | |
c27a02cd YP |
1460 | mutex_unlock(&mdev->state_lock); |
1461 | } | |
1462 | ||
b6c39bfc AV |
1463 | /* mlx4_en_service_task - Run service task for tasks that needed to be done |
1464 | * periodically | |
1465 | */ | |
1466 | static void mlx4_en_service_task(struct work_struct *work) | |
1467 | { | |
1468 | struct delayed_work *delay = to_delayed_work(work); | |
1469 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, | |
1470 | service_task); | |
1471 | struct mlx4_en_dev *mdev = priv->mdev; | |
1472 | ||
1473 | mutex_lock(&mdev->state_lock); | |
1474 | if (mdev->device_up) { | |
dc8142ea AV |
1475 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) |
1476 | mlx4_en_ptp_overflow_check(mdev); | |
b6c39bfc | 1477 | |
07841f9d | 1478 | mlx4_en_recover_from_oom(priv); |
b6c39bfc AV |
1479 | queue_delayed_work(mdev->workqueue, &priv->service_task, |
1480 | SERVICE_TASK_DELAY); | |
1481 | } | |
1482 | mutex_unlock(&mdev->state_lock); | |
1483 | } | |
1484 | ||
c27a02cd YP |
1485 | static void mlx4_en_linkstate(struct work_struct *work) |
1486 | { | |
1487 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1488 | linkstate_task); | |
1489 | struct mlx4_en_dev *mdev = priv->mdev; | |
1490 | int linkstate = priv->link_state; | |
1491 | ||
1492 | mutex_lock(&mdev->state_lock); | |
1493 | /* If observable port state changed set carrier state and | |
1494 | * report to system log */ | |
1495 | if (priv->last_link_state != linkstate) { | |
1496 | if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) { | |
e5cc44b2 | 1497 | en_info(priv, "Link Down\n"); |
c27a02cd YP |
1498 | netif_carrier_off(priv->dev); |
1499 | } else { | |
e5cc44b2 | 1500 | en_info(priv, "Link Up\n"); |
c27a02cd YP |
1501 | netif_carrier_on(priv->dev); |
1502 | } | |
1503 | } | |
1504 | priv->last_link_state = linkstate; | |
1505 | mutex_unlock(&mdev->state_lock); | |
1506 | } | |
1507 | ||
9e311e77 YA |
1508 | static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx) |
1509 | { | |
1510 | struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx]; | |
1511 | int numa_node = priv->mdev->dev->numa_node; | |
9e311e77 YA |
1512 | |
1513 | if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL)) | |
1514 | return -ENOMEM; | |
1515 | ||
f36963c9 RR |
1516 | cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node), |
1517 | ring->affinity_mask); | |
1518 | return 0; | |
9e311e77 YA |
1519 | } |
1520 | ||
1521 | static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx) | |
1522 | { | |
1523 | free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask); | |
1524 | } | |
c27a02cd | 1525 | |
9ecc2d86 BB |
1526 | static void mlx4_en_init_recycle_ring(struct mlx4_en_priv *priv, |
1527 | int tx_ring_idx) | |
1528 | { | |
1529 | struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[tx_ring_idx]; | |
1530 | int rr_index; | |
1531 | ||
1532 | rr_index = (priv->xdp_ring_num - priv->tx_ring_num) + tx_ring_idx; | |
1533 | if (rr_index >= 0) { | |
1534 | tx_ring->free_tx_desc = mlx4_en_recycle_tx_desc; | |
1535 | tx_ring->recycle_ring = priv->rx_ring[rr_index]; | |
1536 | en_dbg(DRV, priv, | |
1537 | "Set tx_ring[%d]->recycle_ring = rx_ring[%d]\n", | |
1538 | tx_ring_idx, rr_index); | |
1539 | } else { | |
1540 | tx_ring->recycle_ring = NULL; | |
1541 | } | |
1542 | } | |
1543 | ||
18cc42a3 | 1544 | int mlx4_en_start_port(struct net_device *dev) |
c27a02cd YP |
1545 | { |
1546 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1547 | struct mlx4_en_dev *mdev = priv->mdev; | |
1548 | struct mlx4_en_cq *cq; | |
1549 | struct mlx4_en_tx_ring *tx_ring; | |
c27a02cd YP |
1550 | int rx_index = 0; |
1551 | int tx_index = 0; | |
c27a02cd YP |
1552 | int err = 0; |
1553 | int i; | |
1554 | int j; | |
1679200f | 1555 | u8 mc_list[16] = {0}; |
c27a02cd YP |
1556 | |
1557 | if (priv->port_up) { | |
453a6082 | 1558 | en_dbg(DRV, priv, "start port called while port already up\n"); |
c27a02cd YP |
1559 | return 0; |
1560 | } | |
1561 | ||
6d199937 YP |
1562 | INIT_LIST_HEAD(&priv->mc_list); |
1563 | INIT_LIST_HEAD(&priv->curr_list); | |
0d256c0e HHZ |
1564 | INIT_LIST_HEAD(&priv->ethtool_list); |
1565 | memset(&priv->ethtool_rules[0], 0, | |
1566 | sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES); | |
6d199937 | 1567 | |
c27a02cd YP |
1568 | /* Calculate Rx buf size */ |
1569 | dev->mtu = min(dev->mtu, priv->max_mtu); | |
1570 | mlx4_en_calc_rx_buf(dev); | |
453a6082 | 1571 | en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size); |
38aab07c | 1572 | |
c27a02cd | 1573 | /* Configure rx cq's and rings */ |
38aab07c YP |
1574 | err = mlx4_en_activate_rx_rings(priv); |
1575 | if (err) { | |
453a6082 | 1576 | en_err(priv, "Failed to activate RX rings\n"); |
38aab07c YP |
1577 | return err; |
1578 | } | |
c27a02cd | 1579 | for (i = 0; i < priv->rx_ring_num; i++) { |
41d942d5 | 1580 | cq = priv->rx_cq[i]; |
c27a02cd | 1581 | |
9e311e77 YA |
1582 | err = mlx4_en_init_affinity_hint(priv, i); |
1583 | if (err) { | |
1584 | en_err(priv, "Failed preparing IRQ affinity hint\n"); | |
1585 | goto cq_err; | |
1586 | } | |
1587 | ||
76532d0c | 1588 | err = mlx4_en_activate_cq(priv, cq, i); |
c27a02cd | 1589 | if (err) { |
453a6082 | 1590 | en_err(priv, "Failed activating Rx CQ\n"); |
9e311e77 | 1591 | mlx4_en_free_affinity_hint(priv, i); |
a4233304 | 1592 | goto cq_err; |
c27a02cd | 1593 | } |
c3f2511f IS |
1594 | |
1595 | for (j = 0; j < cq->size; j++) { | |
1596 | struct mlx4_cqe *cqe = NULL; | |
1597 | ||
1598 | cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) + | |
1599 | priv->cqe_factor; | |
1600 | cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK; | |
1601 | } | |
1602 | ||
c27a02cd YP |
1603 | err = mlx4_en_set_cq_moder(priv, cq); |
1604 | if (err) { | |
1a91de28 | 1605 | en_err(priv, "Failed setting cq moderation parameters\n"); |
c27a02cd | 1606 | mlx4_en_deactivate_cq(priv, cq); |
9e311e77 | 1607 | mlx4_en_free_affinity_hint(priv, i); |
c27a02cd YP |
1608 | goto cq_err; |
1609 | } | |
1610 | mlx4_en_arm_cq(priv, cq); | |
41d942d5 | 1611 | priv->rx_ring[i]->cqn = cq->mcq.cqn; |
c27a02cd YP |
1612 | ++rx_index; |
1613 | } | |
1614 | ||
ffe455ad EE |
1615 | /* Set qp number */ |
1616 | en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port); | |
16a10ffd | 1617 | err = mlx4_en_get_qp(priv); |
1679200f | 1618 | if (err) { |
ffe455ad | 1619 | en_err(priv, "Failed getting eth qp\n"); |
1679200f YP |
1620 | goto cq_err; |
1621 | } | |
1622 | mdev->mac_removed[priv->port] = 0; | |
1623 | ||
6de5f7f6 EBE |
1624 | priv->counter_index = |
1625 | mlx4_get_default_counter_index(mdev->dev, priv->port); | |
1626 | ||
c27a02cd YP |
1627 | err = mlx4_en_config_rss_steer(priv); |
1628 | if (err) { | |
453a6082 | 1629 | en_err(priv, "Failed configuring rss steering\n"); |
1679200f | 1630 | goto mac_err; |
c27a02cd YP |
1631 | } |
1632 | ||
cabdc8ee HHZ |
1633 | err = mlx4_en_create_drop_qp(priv); |
1634 | if (err) | |
1635 | goto rss_err; | |
1636 | ||
c27a02cd YP |
1637 | /* Configure tx cq's and rings */ |
1638 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1639 | /* Configure cq */ | |
41d942d5 | 1640 | cq = priv->tx_cq[i]; |
76532d0c | 1641 | err = mlx4_en_activate_cq(priv, cq, i); |
c27a02cd | 1642 | if (err) { |
453a6082 | 1643 | en_err(priv, "Failed allocating Tx CQ\n"); |
c27a02cd YP |
1644 | goto tx_err; |
1645 | } | |
1646 | err = mlx4_en_set_cq_moder(priv, cq); | |
1647 | if (err) { | |
1a91de28 | 1648 | en_err(priv, "Failed setting cq moderation parameters\n"); |
c27a02cd YP |
1649 | mlx4_en_deactivate_cq(priv, cq); |
1650 | goto tx_err; | |
1651 | } | |
453a6082 | 1652 | en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i); |
c27a02cd YP |
1653 | cq->buf->wqe_index = cpu_to_be16(0xffff); |
1654 | ||
1655 | /* Configure ring */ | |
41d942d5 | 1656 | tx_ring = priv->tx_ring[i]; |
0e98b523 | 1657 | err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn, |
d317966b | 1658 | i / priv->num_tx_rings_p_up); |
c27a02cd | 1659 | if (err) { |
453a6082 | 1660 | en_err(priv, "Failed allocating Tx ring\n"); |
c27a02cd YP |
1661 | mlx4_en_deactivate_cq(priv, cq); |
1662 | goto tx_err; | |
1663 | } | |
5b263f53 | 1664 | tx_ring->tx_queue = netdev_get_tx_queue(dev, i); |
e22979d9 | 1665 | |
9ecc2d86 BB |
1666 | mlx4_en_init_recycle_ring(priv, i); |
1667 | ||
e22979d9 YP |
1668 | /* Arm CQ for TX completions */ |
1669 | mlx4_en_arm_cq(priv, cq); | |
1670 | ||
c27a02cd YP |
1671 | /* Set initial ownership of all Tx TXBBs to SW (1) */ |
1672 | for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE) | |
1673 | *((u32 *) (tx_ring->buf + j)) = 0xffffffff; | |
1674 | ++tx_index; | |
1675 | } | |
1676 | ||
1677 | /* Configure port */ | |
1678 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, | |
1679 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
1680 | priv->prof->tx_pause, |
1681 | priv->prof->tx_ppp, | |
1682 | priv->prof->rx_pause, | |
1683 | priv->prof->rx_ppp); | |
c27a02cd | 1684 | if (err) { |
48e551ff YB |
1685 | en_err(priv, "Failed setting port general configurations for port %d, with error %d\n", |
1686 | priv->port, err); | |
c27a02cd YP |
1687 | goto tx_err; |
1688 | } | |
1689 | /* Set default qp number */ | |
1690 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0); | |
1691 | if (err) { | |
453a6082 | 1692 | en_err(priv, "Failed setting default qp numbers\n"); |
c27a02cd YP |
1693 | goto tx_err; |
1694 | } | |
c27a02cd | 1695 | |
837052d0 | 1696 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { |
1b136de1 | 1697 | err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1); |
837052d0 OG |
1698 | if (err) { |
1699 | en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n", | |
1700 | err); | |
1701 | goto tx_err; | |
1702 | } | |
1703 | } | |
1704 | ||
c27a02cd | 1705 | /* Init port */ |
453a6082 | 1706 | en_dbg(HW, priv, "Initializing port\n"); |
c27a02cd YP |
1707 | err = mlx4_INIT_PORT(mdev->dev, priv->port); |
1708 | if (err) { | |
453a6082 | 1709 | en_err(priv, "Failed Initializing port\n"); |
1679200f | 1710 | goto tx_err; |
c27a02cd YP |
1711 | } |
1712 | ||
ba4b87ae IS |
1713 | /* Set Unicast and VXLAN steering rules */ |
1714 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 && | |
1715 | mlx4_en_set_rss_steer_rules(priv)) | |
1716 | mlx4_warn(mdev, "Failed setting steering rules\n"); | |
1717 | ||
1679200f | 1718 | /* Attach rx QP to bradcast address */ |
c7bf7169 | 1719 | eth_broadcast_addr(&mc_list[10]); |
0ff1fb65 | 1720 | mc_list[5] = priv->port; /* needed for B0 steering support */ |
1679200f | 1721 | if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list, |
0ff1fb65 HHZ |
1722 | priv->port, 0, MLX4_PROT_ETH, |
1723 | &priv->broadcast_id)) | |
1679200f YP |
1724 | mlx4_warn(mdev, "Failed Attaching Broadcast\n"); |
1725 | ||
b5845f98 HX |
1726 | /* Must redo promiscuous mode setup. */ |
1727 | priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC); | |
1728 | ||
c27a02cd | 1729 | /* Schedule multicast task to populate multicast list */ |
0eb74fdd | 1730 | queue_work(mdev->workqueue, &priv->rx_mode_task); |
c27a02cd | 1731 | |
9737c6ab | 1732 | if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) |
a831274a AD |
1733 | udp_tunnel_get_rx_info(dev); |
1734 | ||
c27a02cd | 1735 | priv->port_up = true; |
a11faac7 | 1736 | netif_tx_start_all_queues(dev); |
3484aac1 AV |
1737 | netif_device_attach(dev); |
1738 | ||
c27a02cd YP |
1739 | return 0; |
1740 | ||
c27a02cd YP |
1741 | tx_err: |
1742 | while (tx_index--) { | |
41d942d5 EE |
1743 | mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]); |
1744 | mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]); | |
c27a02cd | 1745 | } |
cabdc8ee HHZ |
1746 | mlx4_en_destroy_drop_qp(priv); |
1747 | rss_err: | |
c27a02cd | 1748 | mlx4_en_release_rss_steer(priv); |
1679200f | 1749 | mac_err: |
16a10ffd | 1750 | mlx4_en_put_qp(priv); |
c27a02cd | 1751 | cq_err: |
9e311e77 | 1752 | while (rx_index--) { |
41d942d5 | 1753 | mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]); |
f94813f3 | 1754 | mlx4_en_free_affinity_hint(priv, rx_index); |
9e311e77 | 1755 | } |
38aab07c | 1756 | for (i = 0; i < priv->rx_ring_num; i++) |
41d942d5 | 1757 | mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]); |
c27a02cd YP |
1758 | |
1759 | return err; /* need to close devices */ | |
1760 | } | |
1761 | ||
1762 | ||
3484aac1 | 1763 | void mlx4_en_stop_port(struct net_device *dev, int detach) |
c27a02cd YP |
1764 | { |
1765 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1766 | struct mlx4_en_dev *mdev = priv->mdev; | |
6d199937 | 1767 | struct mlx4_en_mc_list *mclist, *tmp; |
0d256c0e | 1768 | struct ethtool_flow_id *flow, *tmp_flow; |
c27a02cd | 1769 | int i; |
1679200f | 1770 | u8 mc_list[16] = {0}; |
c27a02cd YP |
1771 | |
1772 | if (!priv->port_up) { | |
453a6082 | 1773 | en_dbg(DRV, priv, "stop port called while port already down\n"); |
c27a02cd YP |
1774 | return; |
1775 | } | |
c27a02cd | 1776 | |
0cc5c8bf EE |
1777 | /* close port*/ |
1778 | mlx4_CLOSE_PORT(mdev->dev, priv->port); | |
1779 | ||
c27a02cd YP |
1780 | /* Synchronize with tx routine */ |
1781 | netif_tx_lock_bh(dev); | |
3484aac1 AV |
1782 | if (detach) |
1783 | netif_device_detach(dev); | |
3c05f5ef | 1784 | netif_tx_stop_all_queues(dev); |
c27a02cd YP |
1785 | netif_tx_unlock_bh(dev); |
1786 | ||
3484aac1 AV |
1787 | netif_tx_disable(dev); |
1788 | ||
7c287380 | 1789 | /* Set port as not active */ |
3c05f5ef | 1790 | priv->port_up = false; |
6de5f7f6 | 1791 | priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev); |
c27a02cd | 1792 | |
db0e7cba AY |
1793 | /* Promsicuous mode */ |
1794 | if (mdev->dev->caps.steering_mode == | |
1795 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1796 | priv->flags &= ~(MLX4_EN_FLAG_PROMISC | | |
1797 | MLX4_EN_FLAG_MC_PROMISC); | |
1798 | mlx4_flow_steer_promisc_remove(mdev->dev, | |
1799 | priv->port, | |
f9162539 | 1800 | MLX4_FS_ALL_DEFAULT); |
db0e7cba AY |
1801 | mlx4_flow_steer_promisc_remove(mdev->dev, |
1802 | priv->port, | |
f9162539 | 1803 | MLX4_FS_MC_DEFAULT); |
db0e7cba AY |
1804 | } else if (priv->flags & MLX4_EN_FLAG_PROMISC) { |
1805 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; | |
1806 | ||
1807 | /* Disable promiscouos mode */ | |
1808 | mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn, | |
1809 | priv->port); | |
1810 | ||
1811 | /* Disable Multicast promisc */ | |
1812 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
1813 | mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn, | |
1814 | priv->port); | |
1815 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
1816 | } | |
1817 | } | |
1818 | ||
1679200f | 1819 | /* Detach All multicasts */ |
c7bf7169 | 1820 | eth_broadcast_addr(&mc_list[10]); |
0ff1fb65 | 1821 | mc_list[5] = priv->port; /* needed for B0 steering support */ |
1679200f | 1822 | mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list, |
0ff1fb65 | 1823 | MLX4_PROT_ETH, priv->broadcast_id); |
6d199937 YP |
1824 | list_for_each_entry(mclist, &priv->curr_list, list) { |
1825 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
1679200f YP |
1826 | mc_list[5] = priv->port; |
1827 | mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, | |
0ff1fb65 | 1828 | mc_list, MLX4_PROT_ETH, mclist->reg_id); |
de123268 OG |
1829 | if (mclist->tunnel_reg_id) |
1830 | mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id); | |
1679200f YP |
1831 | } |
1832 | mlx4_en_clear_list(dev); | |
6d199937 YP |
1833 | list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) { |
1834 | list_del(&mclist->list); | |
1835 | kfree(mclist); | |
1836 | } | |
1837 | ||
1679200f YP |
1838 | /* Flush multicast filter */ |
1839 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG); | |
1840 | ||
6efb5fac HHZ |
1841 | /* Remove flow steering rules for the port*/ |
1842 | if (mdev->dev->caps.steering_mode == | |
1843 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1844 | ASSERT_RTNL(); | |
1845 | list_for_each_entry_safe(flow, tmp_flow, | |
1846 | &priv->ethtool_list, list) { | |
1847 | mlx4_flow_detach(mdev->dev, flow->id); | |
1848 | list_del(&flow->list); | |
1849 | } | |
1850 | } | |
1851 | ||
cabdc8ee HHZ |
1852 | mlx4_en_destroy_drop_qp(priv); |
1853 | ||
c27a02cd YP |
1854 | /* Free TX Rings */ |
1855 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 EE |
1856 | mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]); |
1857 | mlx4_en_deactivate_cq(priv, priv->tx_cq[i]); | |
c27a02cd YP |
1858 | } |
1859 | msleep(10); | |
1860 | ||
1861 | for (i = 0; i < priv->tx_ring_num; i++) | |
41d942d5 | 1862 | mlx4_en_free_tx_buf(dev, priv->tx_ring[i]); |
c27a02cd | 1863 | |
ba4b87ae IS |
1864 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
1865 | mlx4_en_delete_rss_steer_rules(priv); | |
1866 | ||
c27a02cd YP |
1867 | /* Free RSS qps */ |
1868 | mlx4_en_release_rss_steer(priv); | |
1869 | ||
ffe455ad | 1870 | /* Unregister Mac address for the port */ |
16a10ffd | 1871 | mlx4_en_put_qp(priv); |
5930e8d0 | 1872 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN)) |
955154fa | 1873 | mdev->mac_removed[priv->port] = 1; |
ffe455ad | 1874 | |
c27a02cd YP |
1875 | /* Free RX Rings */ |
1876 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 1877 | struct mlx4_en_cq *cq = priv->rx_cq[i]; |
9e77a2b8 | 1878 | |
f4a36751 | 1879 | napi_synchronize(&cq->napi); |
41d942d5 | 1880 | mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]); |
9e77a2b8 | 1881 | mlx4_en_deactivate_cq(priv, cq); |
9e311e77 YA |
1882 | |
1883 | mlx4_en_free_affinity_hint(priv, i); | |
c27a02cd YP |
1884 | } |
1885 | } | |
1886 | ||
1887 | static void mlx4_en_restart(struct work_struct *work) | |
1888 | { | |
1889 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1890 | watchdog_task); | |
1891 | struct mlx4_en_dev *mdev = priv->mdev; | |
1892 | struct net_device *dev = priv->dev; | |
1893 | ||
453a6082 | 1894 | en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port); |
1e338db5 | 1895 | |
0c5c3252 | 1896 | rtnl_lock(); |
1e338db5 YP |
1897 | mutex_lock(&mdev->state_lock); |
1898 | if (priv->port_up) { | |
3484aac1 | 1899 | mlx4_en_stop_port(dev, 1); |
1e338db5 | 1900 | if (mlx4_en_start_port(dev)) |
453a6082 | 1901 | en_err(priv, "Failed restarting port %d\n", priv->port); |
1e338db5 YP |
1902 | } |
1903 | mutex_unlock(&mdev->state_lock); | |
0c5c3252 | 1904 | rtnl_unlock(); |
c27a02cd YP |
1905 | } |
1906 | ||
b477ba62 | 1907 | static void mlx4_en_clear_stats(struct net_device *dev) |
c27a02cd YP |
1908 | { |
1909 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1910 | struct mlx4_en_dev *mdev = priv->mdev; | |
1911 | int i; | |
c27a02cd | 1912 | |
c27a02cd | 1913 | if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1)) |
453a6082 | 1914 | en_dbg(HW, priv, "Failed dumping statistics\n"); |
c27a02cd | 1915 | |
c27a02cd | 1916 | memset(&priv->pstats, 0, sizeof(priv->pstats)); |
b477ba62 EE |
1917 | memset(&priv->pkstats, 0, sizeof(priv->pkstats)); |
1918 | memset(&priv->port_stats, 0, sizeof(priv->port_stats)); | |
0b131561 MB |
1919 | memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats)); |
1920 | memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats)); | |
1921 | memset(&priv->rx_priority_flowstats, 0, | |
1922 | sizeof(priv->rx_priority_flowstats)); | |
1923 | memset(&priv->tx_priority_flowstats, 0, | |
1924 | sizeof(priv->tx_priority_flowstats)); | |
b42de4d0 | 1925 | memset(&priv->pf_stats, 0, sizeof(priv->pf_stats)); |
c27a02cd YP |
1926 | |
1927 | for (i = 0; i < priv->tx_ring_num; i++) { | |
41d942d5 EE |
1928 | priv->tx_ring[i]->bytes = 0; |
1929 | priv->tx_ring[i]->packets = 0; | |
1930 | priv->tx_ring[i]->tx_csum = 0; | |
63a664b7 | 1931 | priv->tx_ring[i]->tx_dropped = 0; |
45acbac6 ED |
1932 | priv->tx_ring[i]->queue_stopped = 0; |
1933 | priv->tx_ring[i]->wake_queue = 0; | |
1934 | priv->tx_ring[i]->tso_packets = 0; | |
1935 | priv->tx_ring[i]->xmit_more = 0; | |
c27a02cd YP |
1936 | } |
1937 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 EE |
1938 | priv->rx_ring[i]->bytes = 0; |
1939 | priv->rx_ring[i]->packets = 0; | |
1940 | priv->rx_ring[i]->csum_ok = 0; | |
1941 | priv->rx_ring[i]->csum_none = 0; | |
f8c6455b | 1942 | priv->rx_ring[i]->csum_complete = 0; |
c27a02cd | 1943 | } |
b477ba62 EE |
1944 | } |
1945 | ||
1946 | static int mlx4_en_open(struct net_device *dev) | |
1947 | { | |
1948 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1949 | struct mlx4_en_dev *mdev = priv->mdev; | |
1950 | int err = 0; | |
1951 | ||
1952 | mutex_lock(&mdev->state_lock); | |
1953 | ||
1954 | if (!mdev->device_up) { | |
1955 | en_err(priv, "Cannot open - device down/disabled\n"); | |
1956 | err = -EBUSY; | |
1957 | goto out; | |
1958 | } | |
1959 | ||
1960 | /* Reset HW statistics and SW counters */ | |
1961 | mlx4_en_clear_stats(dev); | |
c27a02cd | 1962 | |
c27a02cd YP |
1963 | err = mlx4_en_start_port(dev); |
1964 | if (err) | |
453a6082 | 1965 | en_err(priv, "Failed starting port:%d\n", priv->port); |
c27a02cd YP |
1966 | |
1967 | out: | |
1968 | mutex_unlock(&mdev->state_lock); | |
1969 | return err; | |
1970 | } | |
1971 | ||
1972 | ||
1973 | static int mlx4_en_close(struct net_device *dev) | |
1974 | { | |
1975 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1976 | struct mlx4_en_dev *mdev = priv->mdev; | |
1977 | ||
453a6082 | 1978 | en_dbg(IFDOWN, priv, "Close port called\n"); |
c27a02cd YP |
1979 | |
1980 | mutex_lock(&mdev->state_lock); | |
1981 | ||
3484aac1 | 1982 | mlx4_en_stop_port(dev, 0); |
c27a02cd YP |
1983 | netif_carrier_off(dev); |
1984 | ||
1985 | mutex_unlock(&mdev->state_lock); | |
1986 | return 0; | |
1987 | } | |
1988 | ||
ec25bc04 | 1989 | static void mlx4_en_free_resources(struct mlx4_en_priv *priv) |
c27a02cd YP |
1990 | { |
1991 | int i; | |
1992 | ||
1eb8c695 | 1993 | #ifdef CONFIG_RFS_ACCEL |
1eb8c695 AV |
1994 | priv->dev->rx_cpu_rmap = NULL; |
1995 | #endif | |
1996 | ||
c27a02cd | 1997 | for (i = 0; i < priv->tx_ring_num; i++) { |
41d942d5 | 1998 | if (priv->tx_ring && priv->tx_ring[i]) |
c27a02cd | 1999 | mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); |
41d942d5 | 2000 | if (priv->tx_cq && priv->tx_cq[i]) |
fe0af03c | 2001 | mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); |
c27a02cd YP |
2002 | } |
2003 | ||
2004 | for (i = 0; i < priv->rx_ring_num; i++) { | |
41d942d5 | 2005 | if (priv->rx_ring[i]) |
68355f71 TLSC |
2006 | mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], |
2007 | priv->prof->rx_ring_size, priv->stride); | |
41d942d5 | 2008 | if (priv->rx_cq[i]) |
fe0af03c | 2009 | mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); |
c27a02cd | 2010 | } |
044ca2a5 | 2011 | |
c27a02cd YP |
2012 | } |
2013 | ||
ec25bc04 | 2014 | static int mlx4_en_alloc_resources(struct mlx4_en_priv *priv) |
c27a02cd | 2015 | { |
c27a02cd YP |
2016 | struct mlx4_en_port_profile *prof = priv->prof; |
2017 | int i; | |
163561a4 | 2018 | int node; |
87a5c389 | 2019 | |
c27a02cd YP |
2020 | /* Create tx Rings */ |
2021 | for (i = 0; i < priv->tx_ring_num; i++) { | |
163561a4 | 2022 | node = cpu_to_node(i % num_online_cpus()); |
c27a02cd | 2023 | if (mlx4_en_create_cq(priv, &priv->tx_cq[i], |
163561a4 | 2024 | prof->tx_ring_size, i, TX, node)) |
c27a02cd YP |
2025 | goto err; |
2026 | ||
d03a68f8 | 2027 | if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], |
d03a68f8 IS |
2028 | prof->tx_ring_size, TXBB_SIZE, |
2029 | node, i)) | |
c27a02cd YP |
2030 | goto err; |
2031 | } | |
2032 | ||
2033 | /* Create rx Rings */ | |
2034 | for (i = 0; i < priv->rx_ring_num; i++) { | |
163561a4 | 2035 | node = cpu_to_node(i % num_online_cpus()); |
c27a02cd | 2036 | if (mlx4_en_create_cq(priv, &priv->rx_cq[i], |
163561a4 | 2037 | prof->rx_ring_size, i, RX, node)) |
c27a02cd YP |
2038 | goto err; |
2039 | ||
2040 | if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i], | |
163561a4 EE |
2041 | prof->rx_ring_size, priv->stride, |
2042 | node)) | |
c27a02cd YP |
2043 | goto err; |
2044 | } | |
2045 | ||
1eb8c695 | 2046 | #ifdef CONFIG_RFS_ACCEL |
c66fa19c | 2047 | priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port); |
1eb8c695 AV |
2048 | #endif |
2049 | ||
c27a02cd YP |
2050 | return 0; |
2051 | ||
2052 | err: | |
453a6082 | 2053 | en_err(priv, "Failed to allocate NIC resources\n"); |
41d942d5 EE |
2054 | for (i = 0; i < priv->rx_ring_num; i++) { |
2055 | if (priv->rx_ring[i]) | |
2056 | mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], | |
2057 | prof->rx_ring_size, | |
2058 | priv->stride); | |
2059 | if (priv->rx_cq[i]) | |
2060 | mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); | |
2061 | } | |
2062 | for (i = 0; i < priv->tx_ring_num; i++) { | |
2063 | if (priv->tx_ring[i]) | |
2064 | mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); | |
2065 | if (priv->tx_cq[i]) | |
2066 | mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); | |
2067 | } | |
c27a02cd YP |
2068 | return -ENOMEM; |
2069 | } | |
2070 | ||
9d769311 EBE |
2071 | static void mlx4_en_shutdown(struct net_device *dev) |
2072 | { | |
2073 | rtnl_lock(); | |
2074 | netif_device_detach(dev); | |
2075 | mlx4_en_close(dev); | |
2076 | rtnl_unlock(); | |
2077 | } | |
c27a02cd | 2078 | |
ec25bc04 EE |
2079 | static int mlx4_en_copy_priv(struct mlx4_en_priv *dst, |
2080 | struct mlx4_en_priv *src, | |
2081 | struct mlx4_en_port_profile *prof) | |
2082 | { | |
2083 | memcpy(&dst->hwtstamp_config, &prof->hwtstamp_config, | |
2084 | sizeof(dst->hwtstamp_config)); | |
2085 | dst->num_tx_rings_p_up = src->mdev->profile.num_tx_rings_p_up; | |
2086 | dst->tx_ring_num = prof->tx_ring_num; | |
2087 | dst->rx_ring_num = prof->rx_ring_num; | |
2088 | dst->flags = prof->flags; | |
2089 | dst->mdev = src->mdev; | |
2090 | dst->port = src->port; | |
2091 | dst->dev = src->dev; | |
2092 | dst->prof = prof; | |
2093 | dst->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
2094 | DS_SIZE * MLX4_EN_MAX_RX_FRAGS); | |
2095 | ||
2096 | dst->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS, | |
2097 | GFP_KERNEL); | |
2098 | if (!dst->tx_ring) | |
2099 | return -ENOMEM; | |
2100 | ||
2101 | dst->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS, | |
2102 | GFP_KERNEL); | |
2103 | if (!dst->tx_cq) { | |
2104 | kfree(dst->tx_ring); | |
2105 | return -ENOMEM; | |
2106 | } | |
2107 | return 0; | |
2108 | } | |
2109 | ||
2110 | static void mlx4_en_update_priv(struct mlx4_en_priv *dst, | |
2111 | struct mlx4_en_priv *src) | |
2112 | { | |
2113 | memcpy(dst->rx_ring, src->rx_ring, | |
2114 | sizeof(struct mlx4_en_rx_ring *) * src->rx_ring_num); | |
2115 | memcpy(dst->rx_cq, src->rx_cq, | |
2116 | sizeof(struct mlx4_en_cq *) * src->rx_ring_num); | |
2117 | memcpy(&dst->hwtstamp_config, &src->hwtstamp_config, | |
2118 | sizeof(dst->hwtstamp_config)); | |
2119 | dst->tx_ring_num = src->tx_ring_num; | |
2120 | dst->rx_ring_num = src->rx_ring_num; | |
2121 | dst->tx_ring = src->tx_ring; | |
2122 | dst->tx_cq = src->tx_cq; | |
2123 | memcpy(dst->prof, src->prof, sizeof(struct mlx4_en_port_profile)); | |
2124 | } | |
2125 | ||
2126 | int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, | |
2127 | struct mlx4_en_priv *tmp, | |
2128 | struct mlx4_en_port_profile *prof) | |
2129 | { | |
2130 | mlx4_en_copy_priv(tmp, priv, prof); | |
2131 | ||
2132 | if (mlx4_en_alloc_resources(tmp)) { | |
2133 | en_warn(priv, | |
2134 | "%s: Resource allocation failed, using previous configuration\n", | |
2135 | __func__); | |
2136 | kfree(tmp->tx_ring); | |
2137 | kfree(tmp->tx_cq); | |
2138 | return -ENOMEM; | |
2139 | } | |
2140 | return 0; | |
2141 | } | |
2142 | ||
2143 | void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, | |
2144 | struct mlx4_en_priv *tmp) | |
2145 | { | |
2146 | mlx4_en_free_resources(priv); | |
2147 | mlx4_en_update_priv(priv, tmp); | |
2148 | } | |
2149 | ||
c27a02cd YP |
2150 | void mlx4_en_destroy_netdev(struct net_device *dev) |
2151 | { | |
2152 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2153 | struct mlx4_en_dev *mdev = priv->mdev; | |
9d769311 EBE |
2154 | bool shutdown = mdev->dev->persist->interface_state & |
2155 | MLX4_INTERFACE_STATE_SHUTDOWN; | |
c27a02cd | 2156 | |
453a6082 | 2157 | en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port); |
c27a02cd YP |
2158 | |
2159 | /* Unregister device - this will close the port if it was up */ | |
09d4d087 JP |
2160 | if (priv->registered) { |
2161 | devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev, | |
2162 | priv->port)); | |
9d769311 EBE |
2163 | if (shutdown) |
2164 | mlx4_en_shutdown(dev); | |
2165 | else | |
2166 | unregister_netdev(dev); | |
09d4d087 | 2167 | } |
c27a02cd YP |
2168 | |
2169 | if (priv->allocated) | |
2170 | mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE); | |
2171 | ||
2172 | cancel_delayed_work(&priv->stats_task); | |
b6c39bfc | 2173 | cancel_delayed_work(&priv->service_task); |
c27a02cd YP |
2174 | /* flush any pending task for this netdev */ |
2175 | flush_workqueue(mdev->workqueue); | |
2176 | ||
90683061 EE |
2177 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) |
2178 | mlx4_en_remove_timestamp(mdev); | |
2179 | ||
c27a02cd YP |
2180 | /* Detach the netdev so tasks would not attempt to access it */ |
2181 | mutex_lock(&mdev->state_lock); | |
2182 | mdev->pndev[priv->port] = NULL; | |
5da03547 | 2183 | mdev->upper[priv->port] = NULL; |
c27a02cd YP |
2184 | mutex_unlock(&mdev->state_lock); |
2185 | ||
30f56e3c EE |
2186 | #ifdef CONFIG_RFS_ACCEL |
2187 | mlx4_en_cleanup_filters(priv); | |
2188 | #endif | |
2189 | ||
fe0af03c | 2190 | mlx4_en_free_resources(priv); |
564c274c | 2191 | |
bc6a4744 AV |
2192 | kfree(priv->tx_ring); |
2193 | kfree(priv->tx_cq); | |
2194 | ||
9d769311 EBE |
2195 | if (!shutdown) |
2196 | free_netdev(dev); | |
c27a02cd YP |
2197 | } |
2198 | ||
2199 | static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu) | |
2200 | { | |
2201 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2202 | struct mlx4_en_dev *mdev = priv->mdev; | |
2203 | int err = 0; | |
2204 | ||
453a6082 | 2205 | en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n", |
c27a02cd YP |
2206 | dev->mtu, new_mtu); |
2207 | ||
2208 | if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) { | |
453a6082 | 2209 | en_err(priv, "Bad MTU size:%d.\n", new_mtu); |
c27a02cd YP |
2210 | return -EPERM; |
2211 | } | |
47a38e15 BB |
2212 | if (priv->xdp_ring_num && MLX4_EN_EFF_MTU(new_mtu) > FRAG_SZ0) { |
2213 | en_err(priv, "MTU size:%d requires frags but XDP running\n", | |
2214 | new_mtu); | |
2215 | return -EOPNOTSUPP; | |
2216 | } | |
c27a02cd YP |
2217 | dev->mtu = new_mtu; |
2218 | ||
2219 | if (netif_running(dev)) { | |
2220 | mutex_lock(&mdev->state_lock); | |
2221 | if (!mdev->device_up) { | |
2222 | /* NIC is probably restarting - let watchdog task reset | |
2223 | * the port */ | |
453a6082 | 2224 | en_dbg(DRV, priv, "Change MTU called with card down!?\n"); |
c27a02cd | 2225 | } else { |
3484aac1 | 2226 | mlx4_en_stop_port(dev, 1); |
c27a02cd YP |
2227 | err = mlx4_en_start_port(dev); |
2228 | if (err) { | |
453a6082 | 2229 | en_err(priv, "Failed restarting port:%d\n", |
c27a02cd YP |
2230 | priv->port); |
2231 | queue_work(mdev->workqueue, &priv->watchdog_task); | |
2232 | } | |
2233 | } | |
2234 | mutex_unlock(&mdev->state_lock); | |
2235 | } | |
2236 | return 0; | |
2237 | } | |
2238 | ||
100dbda8 | 2239 | static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) |
ec693d47 AV |
2240 | { |
2241 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2242 | struct mlx4_en_dev *mdev = priv->mdev; | |
2243 | struct hwtstamp_config config; | |
2244 | ||
2245 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
2246 | return -EFAULT; | |
2247 | ||
2248 | /* reserved for future extensions */ | |
2249 | if (config.flags) | |
2250 | return -EINVAL; | |
2251 | ||
2252 | /* device doesn't support time stamping */ | |
2253 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)) | |
2254 | return -EINVAL; | |
2255 | ||
2256 | /* TX HW timestamp */ | |
2257 | switch (config.tx_type) { | |
2258 | case HWTSTAMP_TX_OFF: | |
2259 | case HWTSTAMP_TX_ON: | |
2260 | break; | |
2261 | default: | |
2262 | return -ERANGE; | |
2263 | } | |
2264 | ||
2265 | /* RX HW timestamp */ | |
2266 | switch (config.rx_filter) { | |
2267 | case HWTSTAMP_FILTER_NONE: | |
2268 | break; | |
2269 | case HWTSTAMP_FILTER_ALL: | |
2270 | case HWTSTAMP_FILTER_SOME: | |
2271 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
2272 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
2273 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
2274 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
2275 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
2276 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
2277 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
2278 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
2279 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
2280 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
2281 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
2282 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
2283 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
2284 | break; | |
2285 | default: | |
2286 | return -ERANGE; | |
2287 | } | |
2288 | ||
7787fa66 | 2289 | if (mlx4_en_reset_config(dev, config, dev->features)) { |
ec693d47 AV |
2290 | config.tx_type = HWTSTAMP_TX_OFF; |
2291 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
2292 | } | |
2293 | ||
2294 | return copy_to_user(ifr->ifr_data, &config, | |
2295 | sizeof(config)) ? -EFAULT : 0; | |
2296 | } | |
2297 | ||
100dbda8 BH |
2298 | static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) |
2299 | { | |
2300 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2301 | ||
2302 | return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config, | |
2303 | sizeof(priv->hwtstamp_config)) ? -EFAULT : 0; | |
2304 | } | |
2305 | ||
ec693d47 AV |
2306 | static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2307 | { | |
2308 | switch (cmd) { | |
2309 | case SIOCSHWTSTAMP: | |
100dbda8 BH |
2310 | return mlx4_en_hwtstamp_set(dev, ifr); |
2311 | case SIOCGHWTSTAMP: | |
2312 | return mlx4_en_hwtstamp_get(dev, ifr); | |
ec693d47 AV |
2313 | default: |
2314 | return -EOPNOTSUPP; | |
2315 | } | |
2316 | } | |
2317 | ||
e38af4fa HHZ |
2318 | static netdev_features_t mlx4_en_fix_features(struct net_device *netdev, |
2319 | netdev_features_t features) | |
2320 | { | |
2321 | struct mlx4_en_priv *en_priv = netdev_priv(netdev); | |
2322 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2323 | ||
2324 | /* Since there is no support for separate RX C-TAG/S-TAG vlan accel | |
2325 | * enable/disable make sure S-TAG flag is always in same state as | |
2326 | * C-TAG. | |
2327 | */ | |
2328 | if (features & NETIF_F_HW_VLAN_CTAG_RX && | |
2329 | !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) | |
2330 | features |= NETIF_F_HW_VLAN_STAG_RX; | |
2331 | else | |
2332 | features &= ~NETIF_F_HW_VLAN_STAG_RX; | |
2333 | ||
2334 | return features; | |
2335 | } | |
2336 | ||
60d6fe99 AV |
2337 | static int mlx4_en_set_features(struct net_device *netdev, |
2338 | netdev_features_t features) | |
2339 | { | |
2340 | struct mlx4_en_priv *priv = netdev_priv(netdev); | |
f0df3503 | 2341 | bool reset = false; |
537f6f95 SM |
2342 | int ret = 0; |
2343 | ||
f0df3503 MM |
2344 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) { |
2345 | en_info(priv, "Turn %s RX-FCS\n", | |
2346 | (features & NETIF_F_RXFCS) ? "ON" : "OFF"); | |
2347 | reset = true; | |
2348 | } | |
2349 | ||
78500b8c MM |
2350 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) { |
2351 | u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0; | |
2352 | ||
2353 | en_info(priv, "Turn %s RX-ALL\n", | |
2354 | ignore_fcs_value ? "ON" : "OFF"); | |
2355 | ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev, | |
2356 | priv->port, ignore_fcs_value); | |
2357 | if (ret) | |
2358 | return ret; | |
2359 | } | |
2360 | ||
537f6f95 SM |
2361 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) { |
2362 | en_info(priv, "Turn %s RX vlan strip offload\n", | |
2363 | (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF"); | |
f0df3503 | 2364 | reset = true; |
537f6f95 | 2365 | } |
60d6fe99 | 2366 | |
cfb53f36 IS |
2367 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX)) |
2368 | en_info(priv, "Turn %s TX vlan strip offload\n", | |
2369 | (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF"); | |
2370 | ||
e38af4fa HHZ |
2371 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX)) |
2372 | en_info(priv, "Turn %s TX S-VLAN strip offload\n", | |
2373 | (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF"); | |
2374 | ||
241a08c3 IS |
2375 | if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) { |
2376 | en_info(priv, "Turn %s loopback\n", | |
2377 | (features & NETIF_F_LOOPBACK) ? "ON" : "OFF"); | |
2378 | mlx4_en_update_loopback_state(netdev, features); | |
2379 | } | |
79aeaccd | 2380 | |
f0df3503 MM |
2381 | if (reset) { |
2382 | ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config, | |
2383 | features); | |
2384 | if (ret) | |
2385 | return ret; | |
2386 | } | |
60d6fe99 | 2387 | |
f0df3503 | 2388 | return 0; |
60d6fe99 AV |
2389 | } |
2390 | ||
8f7ba3ca RE |
2391 | static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac) |
2392 | { | |
2393 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2394 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
9813337a | 2395 | u64 mac_u64 = mlx4_mac_to_u64(mac); |
8f7ba3ca | 2396 | |
6e522422 | 2397 | if (is_multicast_ether_addr(mac)) |
8f7ba3ca RE |
2398 | return -EINVAL; |
2399 | ||
2400 | return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64); | |
2401 | } | |
2402 | ||
3f7fb021 RE |
2403 | static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) |
2404 | { | |
2405 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2406 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2407 | ||
2408 | return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos); | |
2409 | } | |
2410 | ||
cda373f4 IS |
2411 | static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, |
2412 | int max_tx_rate) | |
2413 | { | |
2414 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2415 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2416 | ||
2417 | return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate, | |
2418 | max_tx_rate); | |
2419 | } | |
2420 | ||
e6b6a231 RE |
2421 | static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
2422 | { | |
2423 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2424 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2425 | ||
2426 | return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting); | |
2427 | } | |
2428 | ||
2cccb9e4 RE |
2429 | static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf) |
2430 | { | |
2431 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2432 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2433 | ||
2434 | return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf); | |
2435 | } | |
8f7ba3ca | 2436 | |
948e306d RE |
2437 | static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state) |
2438 | { | |
2439 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2440 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2441 | ||
2442 | return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state); | |
2443 | } | |
84c86403 | 2444 | |
62a89055 EBE |
2445 | static int mlx4_en_get_vf_stats(struct net_device *dev, int vf, |
2446 | struct ifla_vf_stats *vf_stats) | |
2447 | { | |
2448 | struct mlx4_en_priv *en_priv = netdev_priv(dev); | |
2449 | struct mlx4_en_dev *mdev = en_priv->mdev; | |
2450 | ||
2451 | return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats); | |
2452 | } | |
2453 | ||
84c86403 HHZ |
2454 | #define PORT_ID_BYTE_LEN 8 |
2455 | static int mlx4_en_get_phys_port_id(struct net_device *dev, | |
02637fce | 2456 | struct netdev_phys_item_id *ppid) |
84c86403 HHZ |
2457 | { |
2458 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2459 | struct mlx4_dev *mdev = priv->mdev->dev; | |
2460 | int i; | |
2461 | u64 phys_port_id = mdev->caps.phys_port_id[priv->port]; | |
2462 | ||
2463 | if (!phys_port_id) | |
2464 | return -EOPNOTSUPP; | |
2465 | ||
2466 | ppid->id_len = sizeof(phys_port_id); | |
2467 | for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) { | |
2468 | ppid->id[i] = phys_port_id & 0xff; | |
2469 | phys_port_id >>= 8; | |
2470 | } | |
2471 | return 0; | |
2472 | } | |
2473 | ||
1b136de1 OG |
2474 | static void mlx4_en_add_vxlan_offloads(struct work_struct *work) |
2475 | { | |
2476 | int ret; | |
2477 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
2478 | vxlan_add_task); | |
2479 | ||
2480 | ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port); | |
2481 | if (ret) | |
2482 | goto out; | |
2483 | ||
2484 | ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port, | |
2485 | VXLAN_STEER_BY_OUTER_MAC, 1); | |
2486 | out: | |
f4a1edd5 | 2487 | if (ret) { |
1b136de1 | 2488 | en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret); |
f4a1edd5 OG |
2489 | return; |
2490 | } | |
2491 | ||
2492 | /* set offloads */ | |
09067122 AD |
2493 | priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2494 | NETIF_F_RXCSUM | | |
2495 | NETIF_F_TSO | NETIF_F_TSO6 | | |
2496 | NETIF_F_GSO_UDP_TUNNEL | | |
3c9346b2 AD |
2497 | NETIF_F_GSO_UDP_TUNNEL_CSUM | |
2498 | NETIF_F_GSO_PARTIAL; | |
1b136de1 OG |
2499 | } |
2500 | ||
2501 | static void mlx4_en_del_vxlan_offloads(struct work_struct *work) | |
2502 | { | |
2503 | int ret; | |
2504 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
2505 | vxlan_del_task); | |
f4a1edd5 | 2506 | /* unset offloads */ |
09067122 AD |
2507 | priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2508 | NETIF_F_RXCSUM | | |
2509 | NETIF_F_TSO | NETIF_F_TSO6 | | |
2510 | NETIF_F_GSO_UDP_TUNNEL | | |
3c9346b2 AD |
2511 | NETIF_F_GSO_UDP_TUNNEL_CSUM | |
2512 | NETIF_F_GSO_PARTIAL); | |
1b136de1 OG |
2513 | |
2514 | ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port, | |
2515 | VXLAN_STEER_BY_OUTER_MAC, 0); | |
2516 | if (ret) | |
2517 | en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret); | |
2518 | ||
2519 | priv->vxlan_port = 0; | |
2520 | } | |
2521 | ||
2522 | static void mlx4_en_add_vxlan_port(struct net_device *dev, | |
a831274a | 2523 | struct udp_tunnel_info *ti) |
1b136de1 OG |
2524 | { |
2525 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
a831274a | 2526 | __be16 port = ti->port; |
1b136de1 OG |
2527 | __be16 current_port; |
2528 | ||
a831274a | 2529 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
1b136de1 OG |
2530 | return; |
2531 | ||
a831274a AD |
2532 | if (ti->sa_family != AF_INET) |
2533 | return; | |
2534 | ||
2535 | if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) | |
1b136de1 OG |
2536 | return; |
2537 | ||
2538 | current_port = priv->vxlan_port; | |
2539 | if (current_port && current_port != port) { | |
2540 | en_warn(priv, "vxlan port %d configured, can't add port %d\n", | |
2541 | ntohs(current_port), ntohs(port)); | |
2542 | return; | |
2543 | } | |
2544 | ||
2545 | priv->vxlan_port = port; | |
2546 | queue_work(priv->mdev->workqueue, &priv->vxlan_add_task); | |
2547 | } | |
2548 | ||
2549 | static void mlx4_en_del_vxlan_port(struct net_device *dev, | |
a831274a | 2550 | struct udp_tunnel_info *ti) |
1b136de1 OG |
2551 | { |
2552 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
a831274a | 2553 | __be16 port = ti->port; |
1b136de1 OG |
2554 | __be16 current_port; |
2555 | ||
a831274a | 2556 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
1b136de1 OG |
2557 | return; |
2558 | ||
a831274a AD |
2559 | if (ti->sa_family != AF_INET) |
2560 | return; | |
2561 | ||
2562 | if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) | |
1b136de1 OG |
2563 | return; |
2564 | ||
2565 | current_port = priv->vxlan_port; | |
2566 | if (current_port != port) { | |
2567 | en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port)); | |
2568 | return; | |
2569 | } | |
2570 | ||
2571 | queue_work(priv->mdev->workqueue, &priv->vxlan_del_task); | |
2572 | } | |
956bdab2 | 2573 | |
5f35227e JG |
2574 | static netdev_features_t mlx4_en_features_check(struct sk_buff *skb, |
2575 | struct net_device *dev, | |
2576 | netdev_features_t features) | |
956bdab2 | 2577 | { |
8cb65d00 | 2578 | features = vlan_features_check(skb, features); |
09067122 AD |
2579 | features = vxlan_features_check(skb, features); |
2580 | ||
2581 | /* The ConnectX-3 doesn't support outer IPv6 checksums but it does | |
2582 | * support inner IPv6 checksums and segmentation so we need to | |
2583 | * strip that feature if this is an IPv6 encapsulated frame. | |
2584 | */ | |
2585 | if (skb->encapsulation && | |
a547224d AD |
2586 | (skb->ip_summed == CHECKSUM_PARTIAL)) { |
2587 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2588 | ||
2589 | if (!priv->vxlan_port || | |
2590 | (ip_hdr(skb)->version != 4) || | |
2591 | (udp_hdr(skb)->dest != priv->vxlan_port)) | |
2592 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2593 | } | |
09067122 AD |
2594 | |
2595 | return features; | |
956bdab2 | 2596 | } |
1b136de1 | 2597 | |
de1cf8a7 | 2598 | static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate) |
c10e4fc6 OG |
2599 | { |
2600 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2601 | struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index]; | |
2602 | struct mlx4_update_qp_params params; | |
2603 | int err; | |
2604 | ||
2605 | if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT)) | |
2606 | return -EOPNOTSUPP; | |
2607 | ||
2608 | /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */ | |
2609 | if (maxrate >> 12) { | |
2610 | params.rate_unit = MLX4_QP_RATE_LIMIT_GBS; | |
2611 | params.rate_val = maxrate / 1000; | |
2612 | } else if (maxrate) { | |
2613 | params.rate_unit = MLX4_QP_RATE_LIMIT_MBS; | |
2614 | params.rate_val = maxrate; | |
2615 | } else { /* zero serves to revoke the QP rate-limitation */ | |
2616 | params.rate_unit = 0; | |
2617 | params.rate_val = 0; | |
2618 | } | |
2619 | ||
2620 | err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT, | |
2621 | ¶ms); | |
2622 | return err; | |
2623 | } | |
2624 | ||
47a38e15 BB |
2625 | static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog) |
2626 | { | |
2627 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
d576acf0 | 2628 | struct mlx4_en_dev *mdev = priv->mdev; |
47a38e15 BB |
2629 | struct bpf_prog *old_prog; |
2630 | int xdp_ring_num; | |
d576acf0 BB |
2631 | int port_up = 0; |
2632 | int err; | |
47a38e15 BB |
2633 | int i; |
2634 | ||
2635 | xdp_ring_num = prog ? ALIGN(priv->rx_ring_num, MLX4_EN_NUM_UP) : 0; | |
2636 | ||
d576acf0 BB |
2637 | /* No need to reconfigure buffers when simply swapping the |
2638 | * program for a new one. | |
2639 | */ | |
2640 | if (priv->xdp_ring_num == xdp_ring_num) { | |
2641 | if (prog) { | |
2642 | prog = bpf_prog_add(prog, priv->rx_ring_num - 1); | |
2643 | if (IS_ERR(prog)) | |
2644 | return PTR_ERR(prog); | |
2645 | } | |
326fe02d | 2646 | mutex_lock(&mdev->state_lock); |
d576acf0 | 2647 | for (i = 0; i < priv->rx_ring_num; i++) { |
326fe02d BB |
2648 | old_prog = rcu_dereference_protected( |
2649 | priv->rx_ring[i]->xdp_prog, | |
2650 | lockdep_is_held(&mdev->state_lock)); | |
2651 | rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog); | |
d576acf0 BB |
2652 | if (old_prog) |
2653 | bpf_prog_put(old_prog); | |
2654 | } | |
326fe02d | 2655 | mutex_unlock(&mdev->state_lock); |
d576acf0 BB |
2656 | return 0; |
2657 | } | |
2658 | ||
47a38e15 BB |
2659 | if (priv->num_frags > 1) { |
2660 | en_err(priv, "Cannot set XDP if MTU requires multiple frags\n"); | |
2661 | return -EOPNOTSUPP; | |
2662 | } | |
2663 | ||
9ecc2d86 BB |
2664 | if (priv->tx_ring_num < xdp_ring_num + MLX4_EN_NUM_UP) { |
2665 | en_err(priv, | |
2666 | "Minimum %d tx channels required to run XDP\n", | |
2667 | (xdp_ring_num + MLX4_EN_NUM_UP) / MLX4_EN_NUM_UP); | |
2668 | return -EINVAL; | |
2669 | } | |
2670 | ||
47a38e15 BB |
2671 | if (prog) { |
2672 | prog = bpf_prog_add(prog, priv->rx_ring_num - 1); | |
2673 | if (IS_ERR(prog)) | |
2674 | return PTR_ERR(prog); | |
2675 | } | |
2676 | ||
d576acf0 BB |
2677 | mutex_lock(&mdev->state_lock); |
2678 | if (priv->port_up) { | |
2679 | port_up = 1; | |
2680 | mlx4_en_stop_port(dev, 1); | |
2681 | } | |
2682 | ||
47a38e15 | 2683 | priv->xdp_ring_num = xdp_ring_num; |
9ecc2d86 BB |
2684 | netif_set_real_num_tx_queues(dev, priv->tx_ring_num - |
2685 | priv->xdp_ring_num); | |
47a38e15 | 2686 | |
47a38e15 | 2687 | for (i = 0; i < priv->rx_ring_num; i++) { |
326fe02d BB |
2688 | old_prog = rcu_dereference_protected( |
2689 | priv->rx_ring[i]->xdp_prog, | |
2690 | lockdep_is_held(&mdev->state_lock)); | |
2691 | rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog); | |
47a38e15 BB |
2692 | if (old_prog) |
2693 | bpf_prog_put(old_prog); | |
2694 | } | |
2695 | ||
d576acf0 BB |
2696 | if (port_up) { |
2697 | err = mlx4_en_start_port(dev); | |
2698 | if (err) { | |
2699 | en_err(priv, "Failed starting port %d for XDP change\n", | |
2700 | priv->port); | |
2701 | queue_work(mdev->workqueue, &priv->watchdog_task); | |
2702 | } | |
2703 | } | |
2704 | ||
2705 | mutex_unlock(&mdev->state_lock); | |
47a38e15 BB |
2706 | return 0; |
2707 | } | |
2708 | ||
2709 | static bool mlx4_xdp_attached(struct net_device *dev) | |
2710 | { | |
2711 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
2712 | ||
2713 | return !!priv->xdp_ring_num; | |
2714 | } | |
2715 | ||
2716 | static int mlx4_xdp(struct net_device *dev, struct netdev_xdp *xdp) | |
2717 | { | |
2718 | switch (xdp->command) { | |
2719 | case XDP_SETUP_PROG: | |
2720 | return mlx4_xdp_set(dev, xdp->prog); | |
2721 | case XDP_QUERY_PROG: | |
2722 | xdp->prog_attached = mlx4_xdp_attached(dev); | |
2723 | return 0; | |
2724 | default: | |
2725 | return -EINVAL; | |
2726 | } | |
2727 | } | |
2728 | ||
3addc568 SH |
2729 | static const struct net_device_ops mlx4_netdev_ops = { |
2730 | .ndo_open = mlx4_en_open, | |
2731 | .ndo_stop = mlx4_en_close, | |
2732 | .ndo_start_xmit = mlx4_en_xmit, | |
f813cad8 | 2733 | .ndo_select_queue = mlx4_en_select_queue, |
9ed17db1 | 2734 | .ndo_get_stats64 = mlx4_en_get_stats64, |
0eb74fdd | 2735 | .ndo_set_rx_mode = mlx4_en_set_rx_mode, |
3addc568 | 2736 | .ndo_set_mac_address = mlx4_en_set_mac, |
52255bbe | 2737 | .ndo_validate_addr = eth_validate_addr, |
3addc568 | 2738 | .ndo_change_mtu = mlx4_en_change_mtu, |
ec693d47 | 2739 | .ndo_do_ioctl = mlx4_en_ioctl, |
3addc568 | 2740 | .ndo_tx_timeout = mlx4_en_tx_timeout, |
3addc568 SH |
2741 | .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid, |
2742 | .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid, | |
2743 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2744 | .ndo_poll_controller = mlx4_en_netpoll, | |
2745 | #endif | |
60d6fe99 | 2746 | .ndo_set_features = mlx4_en_set_features, |
e38af4fa | 2747 | .ndo_fix_features = mlx4_en_fix_features, |
e4c6734e | 2748 | .ndo_setup_tc = __mlx4_en_setup_tc, |
1eb8c695 AV |
2749 | #ifdef CONFIG_RFS_ACCEL |
2750 | .ndo_rx_flow_steer = mlx4_en_filter_rfs, | |
9e77a2b8 | 2751 | #endif |
84c86403 | 2752 | .ndo_get_phys_port_id = mlx4_en_get_phys_port_id, |
a831274a AD |
2753 | .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port, |
2754 | .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port, | |
5f35227e | 2755 | .ndo_features_check = mlx4_en_features_check, |
c10e4fc6 | 2756 | .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate, |
47a38e15 | 2757 | .ndo_xdp = mlx4_xdp, |
3addc568 SH |
2758 | }; |
2759 | ||
8f7ba3ca RE |
2760 | static const struct net_device_ops mlx4_netdev_ops_master = { |
2761 | .ndo_open = mlx4_en_open, | |
2762 | .ndo_stop = mlx4_en_close, | |
2763 | .ndo_start_xmit = mlx4_en_xmit, | |
2764 | .ndo_select_queue = mlx4_en_select_queue, | |
9ed17db1 | 2765 | .ndo_get_stats64 = mlx4_en_get_stats64, |
8f7ba3ca RE |
2766 | .ndo_set_rx_mode = mlx4_en_set_rx_mode, |
2767 | .ndo_set_mac_address = mlx4_en_set_mac, | |
2768 | .ndo_validate_addr = eth_validate_addr, | |
2769 | .ndo_change_mtu = mlx4_en_change_mtu, | |
2770 | .ndo_tx_timeout = mlx4_en_tx_timeout, | |
2771 | .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid, | |
2772 | .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid, | |
2773 | .ndo_set_vf_mac = mlx4_en_set_vf_mac, | |
3f7fb021 | 2774 | .ndo_set_vf_vlan = mlx4_en_set_vf_vlan, |
cda373f4 | 2775 | .ndo_set_vf_rate = mlx4_en_set_vf_rate, |
e6b6a231 | 2776 | .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk, |
948e306d | 2777 | .ndo_set_vf_link_state = mlx4_en_set_vf_link_state, |
62a89055 | 2778 | .ndo_get_vf_stats = mlx4_en_get_vf_stats, |
2cccb9e4 | 2779 | .ndo_get_vf_config = mlx4_en_get_vf_config, |
8f7ba3ca RE |
2780 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2781 | .ndo_poll_controller = mlx4_en_netpoll, | |
2782 | #endif | |
2783 | .ndo_set_features = mlx4_en_set_features, | |
e38af4fa | 2784 | .ndo_fix_features = mlx4_en_fix_features, |
e4c6734e | 2785 | .ndo_setup_tc = __mlx4_en_setup_tc, |
8f7ba3ca RE |
2786 | #ifdef CONFIG_RFS_ACCEL |
2787 | .ndo_rx_flow_steer = mlx4_en_filter_rfs, | |
2788 | #endif | |
84c86403 | 2789 | .ndo_get_phys_port_id = mlx4_en_get_phys_port_id, |
a831274a AD |
2790 | .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port, |
2791 | .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port, | |
5f35227e | 2792 | .ndo_features_check = mlx4_en_features_check, |
c10e4fc6 | 2793 | .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate, |
47a38e15 | 2794 | .ndo_xdp = mlx4_xdp, |
8f7ba3ca RE |
2795 | }; |
2796 | ||
5da03547 MS |
2797 | struct mlx4_en_bond { |
2798 | struct work_struct work; | |
2799 | struct mlx4_en_priv *priv; | |
2800 | int is_bonded; | |
2801 | struct mlx4_port_map port_map; | |
2802 | }; | |
2803 | ||
2804 | static void mlx4_en_bond_work(struct work_struct *work) | |
2805 | { | |
2806 | struct mlx4_en_bond *bond = container_of(work, | |
2807 | struct mlx4_en_bond, | |
2808 | work); | |
2809 | int err = 0; | |
2810 | struct mlx4_dev *dev = bond->priv->mdev->dev; | |
2811 | ||
2812 | if (bond->is_bonded) { | |
2813 | if (!mlx4_is_bonded(dev)) { | |
2814 | err = mlx4_bond(dev); | |
2815 | if (err) | |
2816 | en_err(bond->priv, "Fail to bond device\n"); | |
2817 | } | |
2818 | if (!err) { | |
2819 | err = mlx4_port_map_set(dev, &bond->port_map); | |
2820 | if (err) | |
2821 | en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n", | |
2822 | bond->port_map.port1, | |
2823 | bond->port_map.port2, | |
2824 | err); | |
2825 | } | |
2826 | } else if (mlx4_is_bonded(dev)) { | |
2827 | err = mlx4_unbond(dev); | |
2828 | if (err) | |
2829 | en_err(bond->priv, "Fail to unbond device\n"); | |
2830 | } | |
2831 | dev_put(bond->priv->dev); | |
2832 | kfree(bond); | |
2833 | } | |
2834 | ||
2835 | static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded, | |
2836 | u8 v2p_p1, u8 v2p_p2) | |
2837 | { | |
2838 | struct mlx4_en_bond *bond = NULL; | |
2839 | ||
2840 | bond = kzalloc(sizeof(*bond), GFP_ATOMIC); | |
2841 | if (!bond) | |
2842 | return -ENOMEM; | |
2843 | ||
2844 | INIT_WORK(&bond->work, mlx4_en_bond_work); | |
2845 | bond->priv = priv; | |
2846 | bond->is_bonded = is_bonded; | |
2847 | bond->port_map.port1 = v2p_p1; | |
2848 | bond->port_map.port2 = v2p_p2; | |
2849 | dev_hold(priv->dev); | |
2850 | queue_work(priv->mdev->workqueue, &bond->work); | |
2851 | return 0; | |
2852 | } | |
2853 | ||
2854 | int mlx4_en_netdev_event(struct notifier_block *this, | |
2855 | unsigned long event, void *ptr) | |
2856 | { | |
2857 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
2858 | u8 port = 0; | |
2859 | struct mlx4_en_dev *mdev; | |
2860 | struct mlx4_dev *dev; | |
2861 | int i, num_eth_ports = 0; | |
2862 | bool do_bond = true; | |
2863 | struct mlx4_en_priv *priv; | |
2864 | u8 v2p_port1 = 0; | |
2865 | u8 v2p_port2 = 0; | |
2866 | ||
2867 | if (!net_eq(dev_net(ndev), &init_net)) | |
2868 | return NOTIFY_DONE; | |
2869 | ||
2870 | mdev = container_of(this, struct mlx4_en_dev, nb); | |
2871 | dev = mdev->dev; | |
2872 | ||
2873 | /* Go into this mode only when two network devices set on two ports | |
2874 | * of the same mlx4 device are slaves of the same bonding master | |
2875 | */ | |
2876 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
2877 | ++num_eth_ports; | |
2878 | if (!port && (mdev->pndev[i] == ndev)) | |
2879 | port = i; | |
2880 | mdev->upper[i] = mdev->pndev[i] ? | |
2881 | netdev_master_upper_dev_get(mdev->pndev[i]) : NULL; | |
2882 | /* condition not met: network device is a slave */ | |
2883 | if (!mdev->upper[i]) | |
2884 | do_bond = false; | |
2885 | if (num_eth_ports < 2) | |
2886 | continue; | |
2887 | /* condition not met: same master */ | |
2888 | if (mdev->upper[i] != mdev->upper[i-1]) | |
2889 | do_bond = false; | |
2890 | } | |
2891 | /* condition not met: 2 salves */ | |
2892 | do_bond = (num_eth_ports == 2) ? do_bond : false; | |
2893 | ||
2894 | /* handle only events that come with enough info */ | |
2895 | if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port) | |
2896 | return NOTIFY_DONE; | |
2897 | ||
2898 | priv = netdev_priv(ndev); | |
2899 | if (do_bond) { | |
2900 | struct netdev_notifier_bonding_info *notifier_info = ptr; | |
2901 | struct netdev_bonding_info *bonding_info = | |
2902 | ¬ifier_info->bonding_info; | |
2903 | ||
2904 | /* required mode 1, 2 or 4 */ | |
2905 | if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) && | |
2906 | (bonding_info->master.bond_mode != BOND_MODE_XOR) && | |
2907 | (bonding_info->master.bond_mode != BOND_MODE_8023AD)) | |
2908 | do_bond = false; | |
2909 | ||
2910 | /* require exactly 2 slaves */ | |
2911 | if (bonding_info->master.num_slaves != 2) | |
2912 | do_bond = false; | |
2913 | ||
2914 | /* calc v2p */ | |
2915 | if (do_bond) { | |
2916 | if (bonding_info->master.bond_mode == | |
2917 | BOND_MODE_ACTIVEBACKUP) { | |
2918 | /* in active-backup mode virtual ports are | |
2919 | * mapped to the physical port of the active | |
2920 | * slave */ | |
2921 | if (bonding_info->slave.state == | |
2922 | BOND_STATE_BACKUP) { | |
2923 | if (port == 1) { | |
2924 | v2p_port1 = 2; | |
2925 | v2p_port2 = 2; | |
2926 | } else { | |
2927 | v2p_port1 = 1; | |
2928 | v2p_port2 = 1; | |
2929 | } | |
2930 | } else { /* BOND_STATE_ACTIVE */ | |
2931 | if (port == 1) { | |
2932 | v2p_port1 = 1; | |
2933 | v2p_port2 = 1; | |
2934 | } else { | |
2935 | v2p_port1 = 2; | |
2936 | v2p_port2 = 2; | |
2937 | } | |
2938 | } | |
2939 | } else { /* Active-Active */ | |
2940 | /* in active-active mode a virtual port is | |
2941 | * mapped to the native physical port if and only | |
2942 | * if the physical port is up */ | |
2943 | __s8 link = bonding_info->slave.link; | |
2944 | ||
2945 | if (port == 1) | |
2946 | v2p_port2 = 2; | |
2947 | else | |
2948 | v2p_port1 = 1; | |
2949 | if ((link == BOND_LINK_UP) || | |
2950 | (link == BOND_LINK_FAIL)) { | |
2951 | if (port == 1) | |
2952 | v2p_port1 = 1; | |
2953 | else | |
2954 | v2p_port2 = 2; | |
2955 | } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */ | |
2956 | if (port == 1) | |
2957 | v2p_port1 = 2; | |
2958 | else | |
2959 | v2p_port2 = 1; | |
2960 | } | |
2961 | } | |
2962 | } | |
2963 | } | |
2964 | ||
2965 | mlx4_en_queue_bond_work(priv, do_bond, | |
2966 | v2p_port1, v2p_port2); | |
2967 | ||
2968 | return NOTIFY_DONE; | |
2969 | } | |
2970 | ||
0b131561 MB |
2971 | void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, |
2972 | struct mlx4_en_stats_bitmap *stats_bitmap, | |
2973 | u8 rx_ppp, u8 rx_pause, | |
2974 | u8 tx_ppp, u8 tx_pause) | |
2975 | { | |
b42de4d0 | 2976 | int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS; |
0b131561 MB |
2977 | |
2978 | if (!mlx4_is_slave(dev) && | |
2979 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) { | |
2980 | mutex_lock(&stats_bitmap->mutex); | |
2981 | bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS); | |
2982 | ||
2983 | if (rx_ppp) | |
2984 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2985 | NUM_FLOW_PRIORITY_STATS_RX); | |
2986 | last_i += NUM_FLOW_PRIORITY_STATS_RX; | |
2987 | ||
2988 | if (rx_pause && !(rx_ppp)) | |
2989 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2990 | NUM_FLOW_STATS_RX); | |
2991 | last_i += NUM_FLOW_STATS_RX; | |
2992 | ||
2993 | if (tx_ppp) | |
2994 | bitmap_set(stats_bitmap->bitmap, last_i, | |
2995 | NUM_FLOW_PRIORITY_STATS_TX); | |
2996 | last_i += NUM_FLOW_PRIORITY_STATS_TX; | |
2997 | ||
2998 | if (tx_pause && !(tx_ppp)) | |
2999 | bitmap_set(stats_bitmap->bitmap, last_i, | |
3000 | NUM_FLOW_STATS_TX); | |
3001 | last_i += NUM_FLOW_STATS_TX; | |
3002 | ||
3003 | mutex_unlock(&stats_bitmap->mutex); | |
3004 | } | |
3005 | } | |
3006 | ||
6fcd2735 | 3007 | void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, |
0b131561 MB |
3008 | struct mlx4_en_stats_bitmap *stats_bitmap, |
3009 | u8 rx_ppp, u8 rx_pause, | |
3010 | u8 tx_ppp, u8 tx_pause) | |
ffa88f37 | 3011 | { |
6fcd2735 EBE |
3012 | int last_i = 0; |
3013 | ||
3da8a36c EBE |
3014 | mutex_init(&stats_bitmap->mutex); |
3015 | bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS); | |
6fcd2735 EBE |
3016 | |
3017 | if (mlx4_is_slave(dev)) { | |
3da8a36c | 3018 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 3019 | MLX4_FIND_NETDEV_STAT(rx_packets), 1); |
3da8a36c | 3020 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 3021 | MLX4_FIND_NETDEV_STAT(tx_packets), 1); |
3da8a36c | 3022 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 3023 | MLX4_FIND_NETDEV_STAT(rx_bytes), 1); |
3da8a36c | 3024 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 3025 | MLX4_FIND_NETDEV_STAT(tx_bytes), 1); |
3da8a36c | 3026 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 | 3027 | MLX4_FIND_NETDEV_STAT(rx_dropped), 1); |
3da8a36c | 3028 | bitmap_set(stats_bitmap->bitmap, last_i + |
6fcd2735 EBE |
3029 | MLX4_FIND_NETDEV_STAT(tx_dropped), 1); |
3030 | } else { | |
3da8a36c | 3031 | bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS); |
ffa88f37 | 3032 | } |
6fcd2735 | 3033 | last_i += NUM_MAIN_STATS; |
ffa88f37 | 3034 | |
3da8a36c | 3035 | bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS); |
6fcd2735 | 3036 | last_i += NUM_PORT_STATS; |
ffa88f37 | 3037 | |
b42de4d0 EBE |
3038 | if (mlx4_is_master(dev)) |
3039 | bitmap_set(stats_bitmap->bitmap, last_i, | |
3040 | NUM_PF_STATS); | |
3041 | last_i += NUM_PF_STATS; | |
3042 | ||
0b131561 MB |
3043 | mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap, |
3044 | rx_ppp, rx_pause, | |
3045 | tx_ppp, tx_pause); | |
3046 | last_i += NUM_FLOW_STATS; | |
3047 | ||
6fcd2735 | 3048 | if (!mlx4_is_slave(dev)) |
3da8a36c | 3049 | bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS); |
ffa88f37 EBE |
3050 | } |
3051 | ||
c27a02cd YP |
3052 | int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, |
3053 | struct mlx4_en_port_profile *prof) | |
3054 | { | |
3055 | struct net_device *dev; | |
3056 | struct mlx4_en_priv *priv; | |
c07cb4b0 | 3057 | int i; |
c27a02cd YP |
3058 | int err; |
3059 | ||
f1593d22 | 3060 | dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv), |
d317966b | 3061 | MAX_TX_RINGS, MAX_RX_RINGS); |
41de8d4c | 3062 | if (dev == NULL) |
c27a02cd | 3063 | return -ENOMEM; |
c27a02cd | 3064 | |
d317966b AV |
3065 | netif_set_real_num_tx_queues(dev, prof->tx_ring_num); |
3066 | netif_set_real_num_rx_queues(dev, prof->rx_ring_num); | |
3067 | ||
872bf2fb | 3068 | SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev); |
76a066f2 | 3069 | dev->dev_port = port - 1; |
c27a02cd YP |
3070 | |
3071 | /* | |
3072 | * Initialize driver private data | |
3073 | */ | |
3074 | ||
3075 | priv = netdev_priv(dev); | |
3076 | memset(priv, 0, sizeof(struct mlx4_en_priv)); | |
6de5f7f6 | 3077 | priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev); |
207af6c5 EE |
3078 | spin_lock_init(&priv->stats_lock); |
3079 | INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode); | |
3080 | INIT_WORK(&priv->watchdog_task, mlx4_en_restart); | |
3081 | INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate); | |
3082 | INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats); | |
3083 | INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task); | |
207af6c5 EE |
3084 | INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads); |
3085 | INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads); | |
207af6c5 EE |
3086 | #ifdef CONFIG_RFS_ACCEL |
3087 | INIT_LIST_HEAD(&priv->filters); | |
3088 | spin_lock_init(&priv->filters_lock); | |
3089 | #endif | |
3090 | ||
c27a02cd YP |
3091 | priv->dev = dev; |
3092 | priv->mdev = mdev; | |
ebf8c9aa | 3093 | priv->ddev = &mdev->pdev->dev; |
c27a02cd YP |
3094 | priv->prof = prof; |
3095 | priv->port = port; | |
3096 | priv->port_up = false; | |
c27a02cd | 3097 | priv->flags = prof->flags; |
0fef9d03 | 3098 | priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME; |
60d6fe99 AV |
3099 | priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | |
3100 | MLX4_WQE_CTRL_SOLICITED); | |
d317966b | 3101 | priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up; |
c27a02cd | 3102 | priv->tx_ring_num = prof->tx_ring_num; |
fbc6daf1 | 3103 | priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK; |
bd635c35 | 3104 | netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key)); |
d317966b | 3105 | |
41d942d5 | 3106 | priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS, |
d317966b | 3107 | GFP_KERNEL); |
bc6a4744 AV |
3108 | if (!priv->tx_ring) { |
3109 | err = -ENOMEM; | |
3110 | goto out; | |
3111 | } | |
41d942d5 | 3112 | priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS, |
d317966b | 3113 | GFP_KERNEL); |
bc6a4744 AV |
3114 | if (!priv->tx_cq) { |
3115 | err = -ENOMEM; | |
3116 | goto out; | |
3117 | } | |
c27a02cd | 3118 | priv->rx_ring_num = prof->rx_ring_num; |
08ff3235 | 3119 | priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0; |
b1b6b4da | 3120 | priv->cqe_size = mdev->dev->caps.cqe_size; |
c27a02cd YP |
3121 | priv->mac_index = -1; |
3122 | priv->msg_enable = MLX4_EN_MSG_LEVEL; | |
564c274c | 3123 | #ifdef CONFIG_MLX4_EN_DCB |
540b3a39 | 3124 | if (!mlx4_is_slave(priv->mdev->dev)) { |
564ed9b1 TT |
3125 | priv->dcbx_cap = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_HOST | |
3126 | DCB_CAP_DCBX_VER_IEEE; | |
af7d5185 | 3127 | priv->flags |= MLX4_EN_DCB_ENABLED; |
564ed9b1 | 3128 | priv->cee_config.pfc_state = false; |
af7d5185 | 3129 | |
564ed9b1 TT |
3130 | for (i = 0; i < MLX4_EN_NUM_UP; i++) |
3131 | priv->cee_config.dcb_pfc[i] = pfc_disabled; | |
af7d5185 | 3132 | |
3742cc65 | 3133 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) { |
540b3a39 OG |
3134 | dev->dcbnl_ops = &mlx4_en_dcbnl_ops; |
3135 | } else { | |
3136 | en_info(priv, "enabling only PFC DCB ops\n"); | |
3137 | dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops; | |
3138 | } | |
3139 | } | |
564c274c | 3140 | #endif |
c27a02cd | 3141 | |
c07cb4b0 YB |
3142 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) |
3143 | INIT_HLIST_HEAD(&priv->mac_hash[i]); | |
16a10ffd | 3144 | |
c27a02cd YP |
3145 | /* Query for default mac and max mtu */ |
3146 | priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port]; | |
6bbb6d99 | 3147 | |
f8c6455b SM |
3148 | if (mdev->dev->caps.rx_checksum_flags_port[priv->port] & |
3149 | MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP) | |
3150 | priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP; | |
3151 | ||
6bbb6d99 YB |
3152 | /* Set default MAC */ |
3153 | dev->addr_len = ETH_ALEN; | |
3154 | mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]); | |
3155 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
2b3ddf27 JM |
3156 | en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n", |
3157 | priv->port, dev->dev_addr); | |
3158 | err = -EINVAL; | |
3159 | goto out; | |
3160 | } else if (mlx4_is_slave(priv->mdev->dev) && | |
3161 | (priv->mdev->dev->port_random_macs & 1 << priv->port)) { | |
3162 | /* Random MAC was assigned in mlx4_slave_cap | |
3163 | * in mlx4_core module | |
3164 | */ | |
3165 | dev->addr_assign_type |= NET_ADDR_RANDOM; | |
3166 | en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr); | |
c27a02cd YP |
3167 | } |
3168 | ||
2695bab2 | 3169 | memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac)); |
6bbb6d99 | 3170 | |
c27a02cd YP |
3171 | priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + |
3172 | DS_SIZE * MLX4_EN_MAX_RX_FRAGS); | |
3173 | err = mlx4_en_alloc_resources(priv); | |
3174 | if (err) | |
3175 | goto out; | |
3176 | ||
ec693d47 AV |
3177 | /* Initialize time stamping config */ |
3178 | priv->hwtstamp_config.flags = 0; | |
3179 | priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
3180 | priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; | |
3181 | ||
c27a02cd YP |
3182 | /* Allocate page for receive rings */ |
3183 | err = mlx4_alloc_hwq_res(mdev->dev, &priv->res, | |
73898db0 | 3184 | MLX4_EN_PAGE_SIZE); |
c27a02cd | 3185 | if (err) { |
453a6082 | 3186 | en_err(priv, "Failed to allocate page for rx qps\n"); |
c27a02cd YP |
3187 | goto out; |
3188 | } | |
3189 | priv->allocated = 1; | |
3190 | ||
c27a02cd YP |
3191 | /* |
3192 | * Initialize netdev entry points | |
3193 | */ | |
8f7ba3ca RE |
3194 | if (mlx4_is_master(priv->mdev->dev)) |
3195 | dev->netdev_ops = &mlx4_netdev_ops_master; | |
3196 | else | |
3197 | dev->netdev_ops = &mlx4_netdev_ops; | |
c27a02cd | 3198 | dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT; |
1eb63a28 BH |
3199 | netif_set_real_num_tx_queues(dev, priv->tx_ring_num); |
3200 | netif_set_real_num_rx_queues(dev, priv->rx_ring_num); | |
3addc568 | 3201 | |
7ad24ea4 | 3202 | dev->ethtool_ops = &mlx4_en_ethtool_ops; |
c27a02cd | 3203 | |
c27a02cd YP |
3204 | /* |
3205 | * Set driver features | |
3206 | */ | |
c8c64cff MM |
3207 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
3208 | if (mdev->LSO_support) | |
3209 | dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; | |
3210 | ||
3211 | dev->vlan_features = dev->hw_features; | |
3212 | ||
ad86107f | 3213 | dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH; |
c8c64cff | 3214 | dev->features = dev->hw_features | NETIF_F_HIGHDMA | |
f646968f PM |
3215 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
3216 | NETIF_F_HW_VLAN_CTAG_FILTER; | |
537f6f95 SM |
3217 | dev->hw_features |= NETIF_F_LOOPBACK | |
3218 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; | |
c27a02cd | 3219 | |
e38af4fa HHZ |
3220 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { |
3221 | dev->features |= NETIF_F_HW_VLAN_STAG_RX | | |
3222 | NETIF_F_HW_VLAN_STAG_FILTER; | |
3223 | dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX; | |
3224 | } | |
3225 | ||
3226 | if (mlx4_is_slave(mdev->dev)) { | |
3227 | int phv; | |
3228 | ||
3229 | err = get_phv_bit(mdev->dev, port, &phv); | |
3230 | if (!err && phv) { | |
3231 | dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; | |
3232 | priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV; | |
3233 | } | |
3234 | } else { | |
3235 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && | |
3236 | !(mdev->dev->caps.flags2 & | |
3237 | MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) | |
3238 | dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; | |
3239 | } | |
3240 | ||
f0df3503 MM |
3241 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) |
3242 | dev->hw_features |= NETIF_F_RXFCS; | |
3243 | ||
78500b8c MM |
3244 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS) |
3245 | dev->hw_features |= NETIF_F_RXALL; | |
3246 | ||
1eb8c695 | 3247 | if (mdev->dev->caps.steering_mode == |
7d077cd3 MB |
3248 | MLX4_STEERING_MODE_DEVICE_MANAGED && |
3249 | mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC) | |
1eb8c695 AV |
3250 | dev->hw_features |= NETIF_F_NTUPLE; |
3251 | ||
cc5387f7 YB |
3252 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
3253 | dev->priv_flags |= IFF_UNICAST_FLT; | |
3254 | ||
947cbb0a EP |
3255 | /* Setting a default hash function value */ |
3256 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) { | |
3257 | priv->rss_hash_fn = ETH_RSS_HASH_TOP; | |
3258 | } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) { | |
3259 | priv->rss_hash_fn = ETH_RSS_HASH_XOR; | |
3260 | } else { | |
3261 | en_warn(priv, | |
3262 | "No RSS hash capabilities exposed, using Toeplitz\n"); | |
3263 | priv->rss_hash_fn = ETH_RSS_HASH_TOP; | |
3264 | } | |
3265 | ||
925ab1aa | 3266 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { |
3c9346b2 AD |
3267 | dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
3268 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3269 | NETIF_F_GSO_PARTIAL; | |
3270 | dev->features |= NETIF_F_GSO_UDP_TUNNEL | | |
3271 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3272 | NETIF_F_GSO_PARTIAL; | |
3273 | dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
925ab1aa EE |
3274 | } |
3275 | ||
c27a02cd | 3276 | mdev->pndev[port] = dev; |
5da03547 | 3277 | mdev->upper[port] = NULL; |
c27a02cd YP |
3278 | |
3279 | netif_carrier_off(dev); | |
4801ae70 EE |
3280 | mlx4_en_set_default_moderation(priv); |
3281 | ||
453a6082 YP |
3282 | en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num); |
3283 | en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num); | |
3284 | ||
79aeaccd YB |
3285 | mlx4_en_update_loopback_state(priv->dev, priv->dev->features); |
3286 | ||
90822265 | 3287 | /* Configure port */ |
5c8e9046 | 3288 | mlx4_en_calc_rx_buf(dev); |
90822265 | 3289 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, |
5c8e9046 YP |
3290 | priv->rx_skb_size + ETH_FCS_LEN, |
3291 | prof->tx_pause, prof->tx_ppp, | |
3292 | prof->rx_pause, prof->rx_ppp); | |
90822265 | 3293 | if (err) { |
1a91de28 JP |
3294 | en_err(priv, "Failed setting port general configurations for port %d, with error %d\n", |
3295 | priv->port, err); | |
90822265 YP |
3296 | goto out; |
3297 | } | |
3298 | ||
837052d0 | 3299 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { |
1b136de1 | 3300 | err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1); |
837052d0 OG |
3301 | if (err) { |
3302 | en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n", | |
3303 | err); | |
3304 | goto out; | |
3305 | } | |
3306 | } | |
3307 | ||
90822265 YP |
3308 | /* Init port */ |
3309 | en_warn(priv, "Initializing port\n"); | |
3310 | err = mlx4_INIT_PORT(mdev->dev, priv->port); | |
3311 | if (err) { | |
3312 | en_err(priv, "Failed Initializing port\n"); | |
3313 | goto out; | |
3314 | } | |
c27a02cd | 3315 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); |
dc8142ea | 3316 | |
90683061 | 3317 | /* Initialize time stamp mechanism */ |
dc8142ea | 3318 | if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) |
90683061 EE |
3319 | mlx4_en_init_timestamp(mdev); |
3320 | ||
fc9f5ea9 EE |
3321 | queue_delayed_work(mdev->workqueue, &priv->service_task, |
3322 | SERVICE_TASK_DELAY); | |
dc8142ea | 3323 | |
0b131561 MB |
3324 | mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap, |
3325 | mdev->profile.prof[priv->port].rx_ppp, | |
3326 | mdev->profile.prof[priv->port].rx_pause, | |
3327 | mdev->profile.prof[priv->port].tx_ppp, | |
3328 | mdev->profile.prof[priv->port].tx_pause); | |
39de961a | 3329 | |
e5eda89d IS |
3330 | err = register_netdev(dev); |
3331 | if (err) { | |
3332 | en_err(priv, "Netdev registration failed for port %d\n", port); | |
3333 | goto out; | |
3334 | } | |
3335 | ||
3336 | priv->registered = 1; | |
09d4d087 JP |
3337 | devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port), |
3338 | dev); | |
e5eda89d | 3339 | |
c27a02cd YP |
3340 | return 0; |
3341 | ||
3342 | out: | |
3343 | mlx4_en_destroy_netdev(dev); | |
3344 | return err; | |
3345 | } | |
3346 | ||
537f6f95 SM |
3347 | int mlx4_en_reset_config(struct net_device *dev, |
3348 | struct hwtstamp_config ts_config, | |
3349 | netdev_features_t features) | |
3350 | { | |
3351 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
3352 | struct mlx4_en_dev *mdev = priv->mdev; | |
ec25bc04 EE |
3353 | struct mlx4_en_port_profile new_prof; |
3354 | struct mlx4_en_priv *tmp; | |
537f6f95 SM |
3355 | int port_up = 0; |
3356 | int err = 0; | |
3357 | ||
3358 | if (priv->hwtstamp_config.tx_type == ts_config.tx_type && | |
3359 | priv->hwtstamp_config.rx_filter == ts_config.rx_filter && | |
f0df3503 MM |
3360 | !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) && |
3361 | !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) | |
537f6f95 SM |
3362 | return 0; /* Nothing to change */ |
3363 | ||
3364 | if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) && | |
3365 | (features & NETIF_F_HW_VLAN_CTAG_RX) && | |
3366 | (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) { | |
3367 | en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n"); | |
3368 | return -EINVAL; | |
3369 | } | |
3370 | ||
ec25bc04 EE |
3371 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
3372 | if (!tmp) | |
3373 | return -ENOMEM; | |
3374 | ||
537f6f95 | 3375 | mutex_lock(&mdev->state_lock); |
ec25bc04 EE |
3376 | |
3377 | memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); | |
3378 | memcpy(&new_prof.hwtstamp_config, &ts_config, sizeof(ts_config)); | |
3379 | ||
3380 | err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof); | |
3381 | if (err) | |
3382 | goto out; | |
3383 | ||
537f6f95 SM |
3384 | if (priv->port_up) { |
3385 | port_up = 1; | |
3386 | mlx4_en_stop_port(dev, 1); | |
3387 | } | |
3388 | ||
537f6f95 | 3389 | en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n", |
ec25bc04 EE |
3390 | ts_config.rx_filter, |
3391 | !!(features & NETIF_F_HW_VLAN_CTAG_RX)); | |
537f6f95 | 3392 | |
ec25bc04 | 3393 | mlx4_en_safe_replace_resources(priv, tmp); |
537f6f95 SM |
3394 | |
3395 | if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) { | |
3396 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
3397 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
3398 | else | |
3399 | dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3400 | } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) { | |
3401 | /* RX time-stamping is OFF, update the RX vlan offload | |
3402 | * to the latest wanted state | |
3403 | */ | |
3404 | if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX) | |
3405 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
3406 | else | |
3407 | dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3408 | } | |
3409 | ||
f0df3503 MM |
3410 | if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) { |
3411 | if (features & NETIF_F_RXFCS) | |
3412 | dev->features |= NETIF_F_RXFCS; | |
3413 | else | |
3414 | dev->features &= ~NETIF_F_RXFCS; | |
3415 | } | |
3416 | ||
537f6f95 SM |
3417 | /* RX vlan offload and RX time-stamping can't co-exist ! |
3418 | * Regardless of the caller's choice, | |
3419 | * Turn Off RX vlan offload in case of time-stamping is ON | |
3420 | */ | |
3421 | if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) { | |
3422 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
3423 | en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n"); | |
3424 | dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3425 | } | |
3426 | ||
537f6f95 SM |
3427 | if (port_up) { |
3428 | err = mlx4_en_start_port(dev); | |
3429 | if (err) | |
3430 | en_err(priv, "Failed starting port\n"); | |
3431 | } | |
3432 | ||
3433 | out: | |
3434 | mutex_unlock(&mdev->state_lock); | |
ec25bc04 EE |
3435 | kfree(tmp); |
3436 | if (!err) | |
3437 | netdev_features_change(dev); | |
537f6f95 SM |
3438 | return err; |
3439 | } |