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IB/mlx4_ib: Remove local invalidate segment unused fields
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
4af1c048 42#include <linux/rbtree.h>
ee49bd93 43#include <linux/timer.h>
3142788b 44#include <linux/semaphore.h>
27bf91d6 45#include <linux/workqueue.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
37608eea 48#include <linux/mlx4/driver.h>
225c7b1f 49#include <linux/mlx4/doorbell.h>
623ed84b 50#include <linux/mlx4/cmd.h>
225c7b1f
RD		 51
52#define DRV_NAME "mlx4_core"
ab9c17a0 53#define PFX DRV_NAME ": "
7d4b6bcc
YP		 54#define DRV_VERSION "1.1"
55#define DRV_RELDATE "Dec, 2011"
225c7b1f 56
0ff1fb65
HHZ		 57#define MLX4_FS_UDP_UC_EN (1 << 1)
58#define MLX4_FS_TCP_UC_EN (1 << 2)
59#define MLX4_FS_NUM_OF_L2_ADDR 8
60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61#define MLX4_FS_NUM_MCG (1 << 17)
62
63enum {
64 MLX4_FS_L2_HASH = 0,
65 MLX4_FS_L2_L3_L4_HASH,
66};
67
e5395e92
AV		 68#define MLX4_NUM_UP 8
69#define MLX4_NUM_TC 8
70#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71#define MLX4_RATELIMIT_DEFAULT 0xffff
72
73struct mlx4_set_port_prio2tc_context {
74 u8 prio2tc[4];
75};
76
77struct mlx4_port_scheduler_tc_cfg_be {
78 __be16 pg;
79 __be16 bw_precentage;
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 __be16 max_bw_value;
82};
83
84struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86};
87
225c7b1f
RD		 88enum {
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 94};
95
225c7b1f 96enum {
3c439b55
JM		 97 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
98 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
99 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
100 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
0ec2c0f8 101 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 102};
103
225c7b1f
RD		 104enum {
105 MLX4_NUM_PDS = 1 << 15
106};
107
108enum {
109 MLX4_CMPT_TYPE_QP = 0,
110 MLX4_CMPT_TYPE_SRQ = 1,
111 MLX4_CMPT_TYPE_CQ = 2,
112 MLX4_CMPT_TYPE_EQ = 3,
113 MLX4_CMPT_NUM_TYPE
114};
115
116enum {
117 MLX4_CMPT_SHIFT = 24,
118 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
119};
120
623ed84b
JM		 121enum mlx4_mr_state {
122 MLX4_MR_DISABLED = 0,
123 MLX4_MR_EN_HW,
124 MLX4_MR_EN_SW
125};
126
127#define MLX4_COMM_TIME 10000
128enum {
129 MLX4_COMM_CMD_RESET,
130 MLX4_COMM_CMD_VHCR0,
131 MLX4_COMM_CMD_VHCR1,
132 MLX4_COMM_CMD_VHCR2,
133 MLX4_COMM_CMD_VHCR_EN,
134 MLX4_COMM_CMD_VHCR_POST,
135 MLX4_COMM_CMD_FLR = 254
136};
137
138/*The flag indicates that the slave should delay the RESET cmd*/
139#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
140/*indicates how many retries will be done if we are in the middle of FLR*/
141#define NUM_OF_RESET_RETRIES 10
142#define SLEEP_TIME_IN_RESET (2 * 1000)
143enum mlx4_resource {
144 RES_QP,
145 RES_CQ,
146 RES_SRQ,
147 RES_XRCD,
148 RES_MPT,
149 RES_MTT,
150 RES_MAC,
151 RES_VLAN,
152 RES_EQ,
153 RES_COUNTER,
1b9c6b06 154 RES_FS_RULE,
623ed84b
JM		 155 MLX4_NUM_OF_RESOURCE_TYPE
156};
157
158enum mlx4_alloc_mode {
159 RES_OP_RESERVE,
160 RES_OP_RESERVE_AND_MAP,
161 RES_OP_MAP_ICM,
162};
163
b8924951
JM		 164enum mlx4_res_tracker_free_type {
165 RES_TR_FREE_ALL,
166 RES_TR_FREE_SLAVES_ONLY,
167 RES_TR_FREE_STRUCTS_ONLY,
168};
623ed84b
JM		 169
170/*
171 *Virtual HCR structures.
172 * mlx4_vhcr is the sw representation, in machine endianess
173 *
174 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
175 * to FW to go through communication channel.
176 * It is big endian, and has the same structure as the physical HCR
177 * used by command interface
178 */
179struct mlx4_vhcr {
180 u64 in_param;
181 u64 out_param;
182 u32 in_modifier;
183 u32 errno;
184 u16 op;
185 u16 token;
186 u8 op_modifier;
187 u8 e_bit;
188};
189
190struct mlx4_vhcr_cmd {
191 __be64 in_param;
192 __be32 in_modifier;
193 __be64 out_param;
194 __be16 token;
195 u16 reserved;
196 u8 status;
197 u8 flags;
198 __be16 opcode;
199};
200
201struct mlx4_cmd_info {
202 u16 opcode;
203 bool has_inbox;
204 bool has_outbox;
205 bool out_is_imm;
206 bool encode_slave_id;
207 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox);
209 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
210 struct mlx4_cmd_mailbox *inbox,
211 struct mlx4_cmd_mailbox *outbox,
212 struct mlx4_cmd_info *cmd);
213};
214
225c7b1f
RD		 215#ifdef CONFIG_MLX4_DEBUG
216extern int mlx4_debug_level;
7b0f5df4
RD		 217#else /* CONFIG_MLX4_DEBUG */
218#define mlx4_debug_level (0)
219#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 220
221#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 222do { \
223 if (mlx4_debug_level) \
224 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225} while (0)
225c7b1f 226
225c7b1f 227#define mlx4_err(mdev, format, arg...) \
0a645e80 228 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 229#define mlx4_info(mdev, format, arg...) \
0a645e80 230 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 231#define mlx4_warn(mdev, format, arg...) \
0a645e80 232 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 233
0ec2c0f8 234extern int mlx4_log_num_mgm_entry_size;
2b8fb286 235extern int log_mtts_per_seg;
0ec2c0f8 236
623ed84b
JM		 237#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
238#define ALL_SLAVES 0xff
239
225c7b1f
RD		 240struct mlx4_bitmap {
241 u32 last;
242 u32 top;
243 u32 max;
93fc9e1b 244 u32 reserved_top;
225c7b1f 245 u32 mask;
42d1e017 246 u32 avail;
225c7b1f
RD		 247 spinlock_t lock;
248 unsigned long *table;
249};
250
251struct mlx4_buddy {
252 unsigned long **bits;
e4044cfc 253 unsigned int *num_free;
3de819e6 254 u32 max_order;
225c7b1f
RD		 255 spinlock_t lock;
256};
257
258struct mlx4_icm;
259
260struct mlx4_icm_table {
261 u64 virt;
262 int num_icm;
3de819e6 263 u32 num_obj;
225c7b1f
RD		 264 int obj_size;
265 int lowmem;
5b0bf5e2 266 int coherent;
225c7b1f
RD		 267 struct mutex mutex;
268 struct mlx4_icm **icm;
269};
270
c82e9aa0
EC		 271/*
272 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
273 */
274struct mlx4_mpt_entry {
275 __be32 flags;
276 __be32 qpn;
277 __be32 key;
278 __be32 pd_flags;
279 __be64 start;
280 __be64 length;
281 __be32 lkey;
282 __be32 win_cnt;
283 u8 reserved1[3];
284 u8 mtt_rep;
2b8fb286 285 __be64 mtt_addr;
c82e9aa0
EC		 286 __be32 mtt_sz;
287 __be32 entity_size;
288 __be32 first_byte_offset;
289} __packed;
290
291/*
292 * Must be packed because start is 64 bits but only aligned to 32 bits.
293 */
294struct mlx4_eq_context {
295 __be32 flags;
296 u16 reserved1[3];
297 __be16 page_offset;
298 u8 log_eq_size;
299 u8 reserved2[4];
300 u8 eq_period;
301 u8 reserved3;
302 u8 eq_max_count;
303 u8 reserved4[3];
304 u8 intr;
305 u8 log_page_size;
306 u8 reserved5[2];
307 u8 mtt_base_addr_h;
308 __be32 mtt_base_addr_l;
309 u32 reserved6[2];
310 __be32 consumer_index;
311 __be32 producer_index;
312 u32 reserved7[4];
313};
314
315struct mlx4_cq_context {
316 __be32 flags;
317 u16 reserved1[3];
318 __be16 page_offset;
319 __be32 logsize_usrpage;
320 __be16 cq_period;
321 __be16 cq_max_count;
322 u8 reserved2[3];
323 u8 comp_eqn;
324 u8 log_page_size;
325 u8 reserved3[2];
326 u8 mtt_base_addr_h;
327 __be32 mtt_base_addr_l;
328 __be32 last_notified_index;
329 __be32 solicit_producer_index;
330 __be32 consumer_index;
331 __be32 producer_index;
332 u32 reserved4[2];
333 __be64 db_rec_addr;
334};
335
336struct mlx4_srq_context {
337 __be32 state_logsize_srqn;
338 u8 logstride;
339 u8 reserved1;
340 __be16 xrcd;
341 __be32 pg_offset_cqn;
342 u32 reserved2;
343 u8 log_page_size;
344 u8 reserved3[2];
345 u8 mtt_base_addr_h;
346 __be32 mtt_base_addr_l;
347 __be32 pd;
348 __be16 limit_watermark;
349 __be16 wqe_cnt;
350 u16 reserved4;
351 __be16 wqe_counter;
352 u32 reserved5;
353 __be64 db_rec_addr;
354};
355
225c7b1f
RD		 356struct mlx4_eq {
357 struct mlx4_dev *dev;
358 void __iomem *doorbell;
359 int eqn;
360 u32 cons_index;
361 u16 irq;
362 u16 have_irq;
363 int nent;
364 struct mlx4_buf_list *page_list;
365 struct mlx4_mtt mtt;
366};
367
623ed84b
JM		 368struct mlx4_slave_eqe {
369 u8 type;
370 u8 port;
371 u32 param;
372};
373
374struct mlx4_slave_event_eq_info {
803143fb 375 int eqn;
623ed84b 376 u16 token;
623ed84b
JM		 377};
378
225c7b1f
RD		 379struct mlx4_profile {
380 int num_qp;
381 int rdmarc_per_qp;
382 int num_srq;
383 int num_cq;
384 int num_mcg;
385 int num_mpt;
db5a7a65 386 unsigned num_mtt;
225c7b1f
RD		 387};
388
389struct mlx4_fw {
390 u64 clr_int_base;
391 u64 catas_offset;
623ed84b 392 u64 comm_base;
225c7b1f
RD		 393 struct mlx4_icm *fw_icm;
394 struct mlx4_icm *aux_icm;
395 u32 catas_size;
396 u16 fw_pages;
397 u8 clr_int_bar;
398 u8 catas_bar;
623ed84b
JM		 399 u8 comm_bar;
400};
401
402struct mlx4_comm {
403 u32 slave_write;
404 u32 slave_read;
225c7b1f
RD		 405};
406
ffe455ad
EE		 407enum {
408 MLX4_MCAST_CONFIG = 0,
409 MLX4_MCAST_DISABLE = 1,
410 MLX4_MCAST_ENABLE = 2,
411};
412
623ed84b
JM		 413#define VLAN_FLTR_SIZE 128
414
415struct mlx4_vlan_fltr {
416 __be32 entry[VLAN_FLTR_SIZE];
417};
418
ffe455ad
EE		 419struct mlx4_mcast_entry {
420 struct list_head list;
421 u64 addr;
422};
423
b12d93d6
YP		 424struct mlx4_promisc_qp {
425 struct list_head list;
426 u32 qpn;
427};
428
429struct mlx4_steer_index {
430 struct list_head list;
431 unsigned int index;
432 struct list_head duplicates;
433};
434
803143fb
MA		 435#define MLX4_EVENT_TYPES_NUM 64
436
623ed84b
JM		 437struct mlx4_slave_state {
438 u8 comm_toggle;
439 u8 last_cmd;
440 u8 init_port_mask;
441 bool active;
442 u8 function;
443 dma_addr_t vhcr_dma;
444 u16 mtu[MLX4_MAX_PORTS + 1];
445 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
446 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
447 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
448 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 449 /* event type to eq number lookup */
450 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 451 u16 eq_pi;
452 u16 eq_ci;
453 spinlock_t lock;
454 /*initialized via the kzalloc*/
455 u8 is_slave_going_down;
456 u32 cookie;
993c401e 457 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
623ed84b
JM		 458};
459
460struct slave_list {
461 struct mutex mutex;
462 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
463};
464
465struct mlx4_resource_tracker {
466 spinlock_t lock;
467 /* tree for each resources */
4af1c048 468 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
623ed84b
JM		 469 /* num_of_slave's lists, one per slave */
470 struct slave_list *slave_list;
471};
472
473#define SLAVE_EVENT_EQ_SIZE 128
474struct mlx4_slave_event_eq {
475 u32 eqn;
476 u32 cons;
477 u32 prod;
992e8e6e 478 spinlock_t event_lock;
623ed84b
JM		 479 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
480};
481
482struct mlx4_master_qp0_state {
483 int proxy_qp0_active;
484 int qp0_active;
485 int port_active;
486};
487
488struct mlx4_mfunc_master_ctx {
489 struct mlx4_slave_state *slave_state;
490 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
491 int init_port_ref[MLX4_MAX_PORTS + 1];
492 u16 max_mtu[MLX4_MAX_PORTS + 1];
493 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
494 struct mlx4_resource_tracker res_tracker;
495 struct workqueue_struct *comm_wq;
496 struct work_struct comm_work;
497 struct work_struct slave_event_work;
498 struct work_struct slave_flr_event_work;
499 spinlock_t slave_state_lock;
f5311ac1 500 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 501 struct mlx4_eqe cmd_eqe;
502 struct mlx4_slave_event_eq slave_eq;
503 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
504};
505
506struct mlx4_mfunc {
507 struct mlx4_comm __iomem *comm;
508 struct mlx4_vhcr_cmd *vhcr;
509 dma_addr_t vhcr_dma;
510
511 struct mlx4_mfunc_master_ctx master;
512};
513
225c7b1f
RD		 514struct mlx4_cmd {
515 struct pci_pool *pool;
516 void __iomem *hcr;
517 struct mutex hcr_mutex;
f3d4c89e 518 struct mutex slave_cmd_mutex;
225c7b1f
RD		 519 struct semaphore poll_sem;
520 struct semaphore event_sem;
521 int max_cmds;
522 spinlock_t context_lock;
523 int free_head;
524 struct mlx4_cmd_context *context;
525 u16 token_mask;
526 u8 use_events;
527 u8 toggle;
623ed84b 528 u8 comm_toggle;
225c7b1f
RD		 529};
530
531struct mlx4_uar_table {
532 struct mlx4_bitmap bitmap;
533};
534
535struct mlx4_mr_table {
536 struct mlx4_bitmap mpt_bitmap;
537 struct mlx4_buddy mtt_buddy;
538 u64 mtt_base;
539 u64 mpt_base;
540 struct mlx4_icm_table mtt_table;
541 struct mlx4_icm_table dmpt_table;
542};
543
544struct mlx4_cq_table {
545 struct mlx4_bitmap bitmap;
546 spinlock_t lock;
547 struct radix_tree_root tree;
548 struct mlx4_icm_table table;
549 struct mlx4_icm_table cmpt_table;
550};
551
552struct mlx4_eq_table {
553 struct mlx4_bitmap bitmap;
b8dd786f 554 char *irq_names;
225c7b1f 555 void __iomem *clr_int;
b8dd786f 556 void __iomem **uar_map;
225c7b1f 557 u32 clr_mask;
b8dd786f 558 struct mlx4_eq *eq;
fa0681d2 559 struct mlx4_icm_table table;
225c7b1f
RD		 560 struct mlx4_icm_table cmpt_table;
561 int have_irq;
562 u8 inta_pin;
563};
564
565struct mlx4_srq_table {
566 struct mlx4_bitmap bitmap;
567 spinlock_t lock;
568 struct radix_tree_root tree;
569 struct mlx4_icm_table table;
570 struct mlx4_icm_table cmpt_table;
571};
572
573struct mlx4_qp_table {
574 struct mlx4_bitmap bitmap;
575 u32 rdmarc_base;
576 int rdmarc_shift;
577 spinlock_t lock;
578 struct mlx4_icm_table qp_table;
579 struct mlx4_icm_table auxc_table;
580 struct mlx4_icm_table altc_table;
581 struct mlx4_icm_table rdmarc_table;
582 struct mlx4_icm_table cmpt_table;
583};
584
585struct mlx4_mcg_table {
586 struct mutex mutex;
587 struct mlx4_bitmap bitmap;
588 struct mlx4_icm_table table;
589};
590
591struct mlx4_catas_err {
592 u32 __iomem *map;
ee49bd93
JM		 593 struct timer_list timer;
594 struct list_head list;
225c7b1f
RD		 595};
596
2a2336f8
YP		 597#define MLX4_MAX_MAC_NUM 128
598#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
599
600struct mlx4_mac_table {
601 __be64 entries[MLX4_MAX_MAC_NUM];
602 int refs[MLX4_MAX_MAC_NUM];
603 struct mutex mutex;
604 int total;
605 int max;
606};
607
608#define MLX4_MAX_VLAN_NUM 128
609#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
610
611struct mlx4_vlan_table {
612 __be32 entries[MLX4_MAX_VLAN_NUM];
613 int refs[MLX4_MAX_VLAN_NUM];
614 struct mutex mutex;
615 int total;
616 int max;
617};
618
ffe455ad
EE		 619#define SET_PORT_GEN_ALL_VALID 0x7
620#define SET_PORT_PROMISC_SHIFT 31
621#define SET_PORT_MC_PROMISC_SHIFT 30
622
623enum {
624 MCAST_DIRECT_ONLY = 0,
625 MCAST_DIRECT = 1,
626 MCAST_DEFAULT = 2
627};
628
629
630struct mlx4_set_port_general_context {
631 u8 reserved[3];
632 u8 flags;
633 u16 reserved2;
634 __be16 mtu;
635 u8 pptx;
636 u8 pfctx;
637 u16 reserved3;
638 u8 pprx;
639 u8 pfcrx;
640 u16 reserved4;
641};
642
643struct mlx4_set_port_rqp_calc_context {
644 __be32 base_qpn;
645 u8 rererved;
646 u8 n_mac;
647 u8 n_vlan;
648 u8 n_prio;
649 u8 reserved2[3];
650 u8 mac_miss;
651 u8 intra_no_vlan;
652 u8 no_vlan;
653 u8 intra_vlan_miss;
654 u8 vlan_miss;
655 u8 reserved3[3];
656 u8 no_vlan_prio;
657 __be32 promisc;
658 __be32 mcast;
659};
660
1679200f
YP		 661struct mlx4_mac_entry {
662 u64 mac;
0ff1fb65 663 u64 reg_id;
1679200f
YP		 664};
665
2a2336f8
YP		 666struct mlx4_port_info {
667 struct mlx4_dev *dev;
668 int port;
7ff93f8b
YP		 669 char dev_name[16];
670 struct device_attribute port_attr;
671 enum mlx4_port_type tmp_type;
096335b3
OG		 672 char dev_mtu_name[16];
673 struct device_attribute port_mtu_attr;
2a2336f8 674 struct mlx4_mac_table mac_table;
1679200f 675 struct radix_tree_root mac_tree;
2a2336f8 676 struct mlx4_vlan_table vlan_table;
1679200f 677 int base_qpn;
2a2336f8
YP		 678};
679
27bf91d6
YP		 680struct mlx4_sense {
681 struct mlx4_dev *dev;
682 u8 do_sense_port[MLX4_MAX_PORTS + 1];
683 u8 sense_allowed[MLX4_MAX_PORTS + 1];
684 struct delayed_work sense_poll;
685};
686
0b7ca5a9
YP		 687struct mlx4_msix_ctl {
688 u64 pool_bm;
730c41d5 689 struct mutex pool_lock;
0b7ca5a9
YP		 690};
691
b12d93d6
YP		 692struct mlx4_steer {
693 struct list_head promisc_qps[MLX4_NUM_STEERS];
694 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 695};
696
a8edc3bf
HHZ		 697struct mlx4_net_trans_rule_hw_ctrl {
698 __be32 ctrl;
699 __be32 vf_vep_port;
700 __be32 qpn;
701 __be32 reserved;
702};
703
704struct mlx4_net_trans_rule_hw_ib {
705 u8 size;
706 u8 rsvd1;
707 __be16 id;
708 u32 rsvd2;
709 __be32 qpn;
710 __be32 qpn_mask;
711 u8 dst_gid[16];
712 u8 dst_gid_msk[16];
713} __packed;
714
715struct mlx4_net_trans_rule_hw_eth {
716 u8 size;
717 u8 rsvd;
718 __be16 id;
719 u8 rsvd1[6];
720 u8 dst_mac[6];
721 u16 rsvd2;
722 u8 dst_mac_msk[6];
723 u16 rsvd3;
724 u8 src_mac[6];
725 u16 rsvd4;
726 u8 src_mac_msk[6];
727 u8 rsvd5;
728 u8 ether_type_enable;
729 __be16 ether_type;
730 __be16 vlan_id_msk;
731 __be16 vlan_id;
732} __packed;
733
734struct mlx4_net_trans_rule_hw_tcp_udp {
735 u8 size;
736 u8 rsvd;
737 __be16 id;
738 __be16 rsvd1[3];
739 __be16 dst_port;
740 __be16 rsvd2;
741 __be16 dst_port_msk;
742 __be16 rsvd3;
743 __be16 src_port;
744 __be16 rsvd4;
745 __be16 src_port_msk;
746} __packed;
747
748struct mlx4_net_trans_rule_hw_ipv4 {
749 u8 size;
750 u8 rsvd;
751 __be16 id;
752 __be32 rsvd1;
753 __be32 dst_ip;
754 __be32 dst_ip_msk;
755 __be32 src_ip;
756 __be32 src_ip_msk;
757} __packed;
758
759struct _rule_hw {
760 union {
761 struct {
762 u8 size;
763 u8 rsvd;
764 __be16 id;
765 };
766 struct mlx4_net_trans_rule_hw_eth eth;
767 struct mlx4_net_trans_rule_hw_ib ib;
768 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
769 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
770 };
771};
772
839f1243
RD		 773enum {
774 MLX4_PCI_DEV_IS_VF = 1 << 0,
ca3e57a5 775 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
839f1243
RD		 776};
777
225c7b1f
RD		 778struct mlx4_priv {
779 struct mlx4_dev dev;
780
781 struct list_head dev_list;
782 struct list_head ctx_list;
783 spinlock_t ctx_lock;
784
839f1243
RD		 785 int pci_dev_data;
786
6296883c
YP		 787 struct list_head pgdir_list;
788 struct mutex pgdir_mutex;
789
225c7b1f
RD		 790 struct mlx4_fw fw;
791 struct mlx4_cmd cmd;
623ed84b 792 struct mlx4_mfunc mfunc;
225c7b1f
RD		 793
794 struct mlx4_bitmap pd_bitmap;
012a8ff5 795 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 796 struct mlx4_uar_table uar_table;
797 struct mlx4_mr_table mr_table;
798 struct mlx4_cq_table cq_table;
799 struct mlx4_eq_table eq_table;
800 struct mlx4_srq_table srq_table;
801 struct mlx4_qp_table qp_table;
802 struct mlx4_mcg_table mcg_table;
f2a3f6a3 803 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 804
805 struct mlx4_catas_err catas_err;
806
807 void __iomem *clr_base;
808
809 struct mlx4_uar driver_uar;
810 void __iomem *kar;
2a2336f8 811 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 812 struct mlx4_sense sense;
7ff93f8b 813 struct mutex port_mutex;
0b7ca5a9 814 struct mlx4_msix_ctl msix_ctl;
b12d93d6 815 struct mlx4_steer *steer;
c1b43dca
EC		 816 struct list_head bf_list;
817 struct mutex bf_mutex;
818 struct io_mapping *bf_mapping;
ea51b377 819 int reserved_mtts;
0ff1fb65 820 int fs_hash_mode;
54679e14 821 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
afa8fd1d 822 __be64 slave_node_guids[MLX4_MFUNC_MAX];
54679e14 823
225c7b1f
RD		 824};
825
826static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
827{
828 return container_of(dev, struct mlx4_priv, dev);
829}
830
27bf91d6
YP		 831#define MLX4_SENSE_RANGE (HZ * 3)
832
833extern struct workqueue_struct *mlx4_wq;
834
225c7b1f
RD		 835u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
836void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 837u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
838void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 839u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 840int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
841 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 842void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
843
844int mlx4_reset(struct mlx4_dev *dev);
845
b8dd786f
YP		 846int mlx4_alloc_eq_table(struct mlx4_dev *dev);
847void mlx4_free_eq_table(struct mlx4_dev *dev);
848
225c7b1f 849int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 850int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 851int mlx4_init_uar_table(struct mlx4_dev *dev);
852int mlx4_init_mr_table(struct mlx4_dev *dev);
853int mlx4_init_eq_table(struct mlx4_dev *dev);
854int mlx4_init_cq_table(struct mlx4_dev *dev);
855int mlx4_init_qp_table(struct mlx4_dev *dev);
856int mlx4_init_srq_table(struct mlx4_dev *dev);
857int mlx4_init_mcg_table(struct mlx4_dev *dev);
858
859void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 860void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 861void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
862void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
863void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
864void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
865void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
866void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
867void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 868int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
869void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
870int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
871void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
872int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
873void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
874int __mlx4_mr_reserve(struct mlx4_dev *dev);
875void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
876int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
877void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
878u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
879void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 880
623ed84b
JM		 881int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
882 struct mlx4_vhcr *vhcr,
883 struct mlx4_cmd_mailbox *inbox,
884 struct mlx4_cmd_mailbox *outbox,
885 struct mlx4_cmd_info *cmd);
886int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
887 struct mlx4_vhcr *vhcr,
888 struct mlx4_cmd_mailbox *inbox,
889 struct mlx4_cmd_mailbox *outbox,
890 struct mlx4_cmd_info *cmd);
891int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
892 struct mlx4_vhcr *vhcr,
893 struct mlx4_cmd_mailbox *inbox,
894 struct mlx4_cmd_mailbox *outbox,
895 struct mlx4_cmd_info *cmd);
896int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
897 struct mlx4_vhcr *vhcr,
898 struct mlx4_cmd_mailbox *inbox,
899 struct mlx4_cmd_mailbox *outbox,
900 struct mlx4_cmd_info *cmd);
901int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
902 struct mlx4_vhcr *vhcr,
903 struct mlx4_cmd_mailbox *inbox,
904 struct mlx4_cmd_mailbox *outbox,
905 struct mlx4_cmd_info *cmd);
906int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
907 struct mlx4_vhcr *vhcr,
908 struct mlx4_cmd_mailbox *inbox,
909 struct mlx4_cmd_mailbox *outbox,
910 struct mlx4_cmd_info *cmd);
911int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
912 struct mlx4_vhcr *vhcr,
913 struct mlx4_cmd_mailbox *inbox,
914 struct mlx4_cmd_mailbox *outbox,
915 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 916int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
917 int *base);
918void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
919int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
920void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
921int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
922int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
923 int start_index, int npages, u64 *page_list);
ba062d52
JM		 924int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
925void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
926int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
927void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 928
ee49bd93
JM		 929void mlx4_start_catas_poll(struct mlx4_dev *dev);
930void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 931void mlx4_catas_init(void);
ee49bd93 932int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 933int mlx4_register_device(struct mlx4_dev *dev);
934void mlx4_unregister_device(struct mlx4_dev *dev);
00f5ce99
JM		 935void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
936 unsigned long param);
225c7b1f
RD		 937
938struct mlx4_dev_cap;
939struct mlx4_init_hca_param;
940
941u64 mlx4_make_profile(struct mlx4_dev *dev,
942 struct mlx4_profile *request,
943 struct mlx4_dev_cap *dev_cap,
944 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 945void mlx4_master_comm_channel(struct work_struct *work);
946void mlx4_gen_slave_eqe(struct work_struct *work);
947void mlx4_master_handle_slave_flr(struct work_struct *work);
948
949int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
950 struct mlx4_vhcr *vhcr,
951 struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
954int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
955 struct mlx4_vhcr *vhcr,
956 struct mlx4_cmd_mailbox *inbox,
957 struct mlx4_cmd_mailbox *outbox,
958 struct mlx4_cmd_info *cmd);
959int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
960 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr,
970 struct mlx4_cmd_mailbox *inbox,
971 struct mlx4_cmd_mailbox *outbox,
972 struct mlx4_cmd_info *cmd);
973int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
974 struct mlx4_vhcr *vhcr,
975 struct mlx4_cmd_mailbox *inbox,
976 struct mlx4_cmd_mailbox *outbox,
977 struct mlx4_cmd_info *cmd);
978int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
979 struct mlx4_vhcr *vhcr,
980 struct mlx4_cmd_mailbox *inbox,
981 struct mlx4_cmd_mailbox *outbox,
982 struct mlx4_cmd_info *cmd);
983int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
984 struct mlx4_vhcr *vhcr,
985 struct mlx4_cmd_mailbox *inbox,
986 struct mlx4_cmd_mailbox *outbox,
987 struct mlx4_cmd_info *cmd);
988int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
989 struct mlx4_vhcr *vhcr,
990 struct mlx4_cmd_mailbox *inbox,
991 struct mlx4_cmd_mailbox *outbox,
992 struct mlx4_cmd_info *cmd);
993int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
994 struct mlx4_vhcr *vhcr,
995 struct mlx4_cmd_mailbox *inbox,
996 struct mlx4_cmd_mailbox *outbox,
997 struct mlx4_cmd_info *cmd);
998int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
1003int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
1018int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1019 struct mlx4_vhcr *vhcr,
1020 struct mlx4_cmd_mailbox *inbox,
1021 struct mlx4_cmd_mailbox *outbox,
1022 struct mlx4_cmd_info *cmd);
1023int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd);
54679e14
JM		 1028int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1029 struct mlx4_vhcr *vhcr,
1030 struct mlx4_cmd_mailbox *inbox,
1031 struct mlx4_cmd_mailbox *outbox,
1032 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1033int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1034 struct mlx4_vhcr *vhcr,
1035 struct mlx4_cmd_mailbox *inbox,
1036 struct mlx4_cmd_mailbox *outbox,
1037 struct mlx4_cmd_info *cmd);
54679e14
JM		 1038int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1039 struct mlx4_vhcr *vhcr,
1040 struct mlx4_cmd_mailbox *inbox,
1041 struct mlx4_cmd_mailbox *outbox,
1042 struct mlx4_cmd_info *cmd);
1043int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1044 struct mlx4_vhcr *vhcr,
1045 struct mlx4_cmd_mailbox *inbox,
1046 struct mlx4_cmd_mailbox *outbox,
1047 struct mlx4_cmd_info *cmd);
1048int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1049 struct mlx4_vhcr *vhcr,
1050 struct mlx4_cmd_mailbox *inbox,
1051 struct mlx4_cmd_mailbox *outbox,
1052 struct mlx4_cmd_info *cmd);
1053int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1054 struct mlx4_vhcr *vhcr,
1055 struct mlx4_cmd_mailbox *inbox,
1056 struct mlx4_cmd_mailbox *outbox,
1057 struct mlx4_cmd_info *cmd);
1058int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1059 struct mlx4_vhcr *vhcr,
1060 struct mlx4_cmd_mailbox *inbox,
1061 struct mlx4_cmd_mailbox *outbox,
1062 struct mlx4_cmd_info *cmd);
1063int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1064 struct mlx4_vhcr *vhcr,
1065 struct mlx4_cmd_mailbox *inbox,
1066 struct mlx4_cmd_mailbox *outbox,
1067 struct mlx4_cmd_info *cmd);
1068int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1069 struct mlx4_vhcr *vhcr,
1070 struct mlx4_cmd_mailbox *inbox,
1071 struct mlx4_cmd_mailbox *outbox,
1072 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1073int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1074 struct mlx4_vhcr *vhcr,
1075 struct mlx4_cmd_mailbox *inbox,
1076 struct mlx4_cmd_mailbox *outbox,
1077 struct mlx4_cmd_info *cmd);
54679e14
JM		 1078int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1079 struct mlx4_vhcr *vhcr,
1080 struct mlx4_cmd_mailbox *inbox,
1081 struct mlx4_cmd_mailbox *outbox,
1082 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1083
1084int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 1085
225c7b1f
RD		 1086int mlx4_cmd_init(struct mlx4_dev *dev);
1087void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 1088int mlx4_multi_func_init(struct mlx4_dev *dev);
1089void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 1090void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1091int mlx4_cmd_use_events(struct mlx4_dev *dev);
1092void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1093
ab9c17a0
JM		 1094int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1095 unsigned long timeout);
1096
225c7b1f
RD		 1097void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1098void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1099
1100void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1101
1102void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1103
1104void mlx4_handle_catas_err(struct mlx4_dev *dev);
1105
ab6dc30d
YP		 1106int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1107 enum mlx4_port_type *type);
27bf91d6
YP		 1108void mlx4_do_sense_ports(struct mlx4_dev *dev,
1109 enum mlx4_port_type *stype,
1110 enum mlx4_port_type *defaults);
1111void mlx4_start_sense(struct mlx4_dev *dev);
1112void mlx4_stop_sense(struct mlx4_dev *dev);
1113void mlx4_sense_init(struct mlx4_dev *dev);
1114int mlx4_check_port_params(struct mlx4_dev *dev,
1115 enum mlx4_port_type *port_type);
1116int mlx4_change_port_types(struct mlx4_dev *dev,
1117 enum mlx4_port_type *port_types);
1118
2a2336f8
YP		 1119void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1120void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1121
6634961c 1122int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
623ed84b
JM		 1123/* resource tracker functions*/
1124int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1125 enum mlx4_resource resource_type,
aa1ec3dd 1126 u64 resource_id, int *slave);
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JM		 1127void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1128int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1129
b8924951
JM		 1130void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1131 enum mlx4_res_tracker_free_type type);
623ed84b 1132
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JM		 1133int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1134 struct mlx4_vhcr *vhcr,
1135 struct mlx4_cmd_mailbox *inbox,
1136 struct mlx4_cmd_mailbox *outbox,
1137 struct mlx4_cmd_info *cmd);
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JM		 1138int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1139 struct mlx4_vhcr *vhcr,
1140 struct mlx4_cmd_mailbox *inbox,
1141 struct mlx4_cmd_mailbox *outbox,
1142 struct mlx4_cmd_info *cmd);
1143int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1144 struct mlx4_vhcr *vhcr,
1145 struct mlx4_cmd_mailbox *inbox,
1146 struct mlx4_cmd_mailbox *outbox,
1147 struct mlx4_cmd_info *cmd);
1148int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1149 struct mlx4_vhcr *vhcr,
1150 struct mlx4_cmd_mailbox *inbox,
1151 struct mlx4_cmd_mailbox *outbox,
1152 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1153int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1154 struct mlx4_vhcr *vhcr,
1155 struct mlx4_cmd_mailbox *inbox,
1156 struct mlx4_cmd_mailbox *outbox,
1157 struct mlx4_cmd_info *cmd);
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JM		 1158int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1159 struct mlx4_vhcr *vhcr,
1160 struct mlx4_cmd_mailbox *inbox,
1161 struct mlx4_cmd_mailbox *outbox,
1162 struct mlx4_cmd_info *cmd);
9a5aa622 1163int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1164
6634961c
JM		 1165int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1166 int *gid_tbl_len, int *pkey_tbl_len);
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JM		 1167
1168int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1169 struct mlx4_vhcr *vhcr,
1170 struct mlx4_cmd_mailbox *inbox,
1171 struct mlx4_cmd_mailbox *outbox,
1172 struct mlx4_cmd_info *cmd);
1173
1174int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1175 struct mlx4_vhcr *vhcr,
1176 struct mlx4_cmd_mailbox *inbox,
1177 struct mlx4_cmd_mailbox *outbox,
1178 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1179int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1180 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1181int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1182 int block_mcast_loopback, enum mlx4_protocol prot,
1183 enum mlx4_steer_type steer);
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JM		 1184int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1185 struct mlx4_vhcr *vhcr,
1186 struct mlx4_cmd_mailbox *inbox,
1187 struct mlx4_cmd_mailbox *outbox,
1188 struct mlx4_cmd_info *cmd);
1189int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1190 struct mlx4_vhcr *vhcr,
1191 struct mlx4_cmd_mailbox *inbox,
1192 struct mlx4_cmd_mailbox *outbox,
1193 struct mlx4_cmd_info *cmd);
1194int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1195 int port, void *buf);
1196int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1197 struct mlx4_cmd_mailbox *outbox);
1198int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1199 struct mlx4_vhcr *vhcr,
1200 struct mlx4_cmd_mailbox *inbox,
1201 struct mlx4_cmd_mailbox *outbox,
1202 struct mlx4_cmd_info *cmd);
1203int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1204 struct mlx4_vhcr *vhcr,
1205 struct mlx4_cmd_mailbox *inbox,
1206 struct mlx4_cmd_mailbox *outbox,
1207 struct mlx4_cmd_info *cmd);
1208int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1209 struct mlx4_vhcr *vhcr,
1210 struct mlx4_cmd_mailbox *inbox,
1211 struct mlx4_cmd_mailbox *outbox,
1212 struct mlx4_cmd_info *cmd);
8fcfb4db
HHZ		 1213int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1214 struct mlx4_vhcr *vhcr,
1215 struct mlx4_cmd_mailbox *inbox,
1216 struct mlx4_cmd_mailbox *outbox,
1217 struct mlx4_cmd_info *cmd);
1218int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1219 struct mlx4_vhcr *vhcr,
1220 struct mlx4_cmd_mailbox *inbox,
1221 struct mlx4_cmd_mailbox *outbox,
1222 struct mlx4_cmd_info *cmd);
f5311ac1 1223
0ec2c0f8
EE		 1224int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1225int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1226
5cc914f1
MA		 1227static inline void set_param_l(u64 *arg, u32 val)
1228{
1229 *((u32 *)arg) = val;
1230}
1231
1232static inline void set_param_h(u64 *arg, u32 val)
1233{
1234 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1235}
1236
1237static inline u32 get_param_l(u64 *arg)
1238{
1239 return (u32) (*arg & 0xffffffff);
1240}
1241
1242static inline u32 get_param_h(u64 *arg)
1243{
1244 return (u32)(*arg >> 32);
1245}
1246
c82e9aa0
EC		 1247static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1248{
1249 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1250}
1251
f5311ac1
JM		 1252#define NOT_MASKED_PD_BITS 17
1253
225c7b1f 1254#endif /* MLX4_H */
Linux kernel - Deliverables
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