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mlx4_core: adjust catas operation for SRIOV mode
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
ee49bd93 42#include <linux/timer.h>
3142788b 43#include <linux/semaphore.h>
27bf91d6 44#include <linux/workqueue.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
37608eea 47#include <linux/mlx4/driver.h>
225c7b1f 48#include <linux/mlx4/doorbell.h>
623ed84b 49#include <linux/mlx4/cmd.h>
225c7b1f
RD		 50
51#define DRV_NAME "mlx4_core"
e1892fa8
DB		 52#define DRV_VERSION "1.0"
53#define DRV_RELDATE "July 14, 2011"
225c7b1f
RD		 54
55enum {
56 MLX4_HCR_BASE = 0x80680,
57 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 58 MLX4_CLR_INT_SIZE = 0x00008,
59 MLX4_SLAVE_COMM_BASE = 0x0,
60 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 61};
62
225c7b1f 63enum {
0ec2c0f8
EE		 64 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
65 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
66 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 67};
68
225c7b1f
RD		 69enum {
70 MLX4_NUM_PDS = 1 << 15
71};
72
73enum {
74 MLX4_CMPT_TYPE_QP = 0,
75 MLX4_CMPT_TYPE_SRQ = 1,
76 MLX4_CMPT_TYPE_CQ = 2,
77 MLX4_CMPT_TYPE_EQ = 3,
78 MLX4_CMPT_NUM_TYPE
79};
80
81enum {
82 MLX4_CMPT_SHIFT = 24,
83 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
84};
85
623ed84b
JM		 86enum mlx4_mr_state {
87 MLX4_MR_DISABLED = 0,
88 MLX4_MR_EN_HW,
89 MLX4_MR_EN_SW
90};
91
92#define MLX4_COMM_TIME 10000
93enum {
94 MLX4_COMM_CMD_RESET,
95 MLX4_COMM_CMD_VHCR0,
96 MLX4_COMM_CMD_VHCR1,
97 MLX4_COMM_CMD_VHCR2,
98 MLX4_COMM_CMD_VHCR_EN,
99 MLX4_COMM_CMD_VHCR_POST,
100 MLX4_COMM_CMD_FLR = 254
101};
102
103/*The flag indicates that the slave should delay the RESET cmd*/
104#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
105/*indicates how many retries will be done if we are in the middle of FLR*/
106#define NUM_OF_RESET_RETRIES 10
107#define SLEEP_TIME_IN_RESET (2 * 1000)
108enum mlx4_resource {
109 RES_QP,
110 RES_CQ,
111 RES_SRQ,
112 RES_XRCD,
113 RES_MPT,
114 RES_MTT,
115 RES_MAC,
116 RES_VLAN,
117 RES_EQ,
118 RES_COUNTER,
119 MLX4_NUM_OF_RESOURCE_TYPE
120};
121
122enum mlx4_alloc_mode {
123 RES_OP_RESERVE,
124 RES_OP_RESERVE_AND_MAP,
125 RES_OP_MAP_ICM,
126};
127
128
129/*
130 *Virtual HCR structures.
131 * mlx4_vhcr is the sw representation, in machine endianess
132 *
133 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
134 * to FW to go through communication channel.
135 * It is big endian, and has the same structure as the physical HCR
136 * used by command interface
137 */
138struct mlx4_vhcr {
139 u64 in_param;
140 u64 out_param;
141 u32 in_modifier;
142 u32 errno;
143 u16 op;
144 u16 token;
145 u8 op_modifier;
146 u8 e_bit;
147};
148
149struct mlx4_vhcr_cmd {
150 __be64 in_param;
151 __be32 in_modifier;
152 __be64 out_param;
153 __be16 token;
154 u16 reserved;
155 u8 status;
156 u8 flags;
157 __be16 opcode;
158};
159
160struct mlx4_cmd_info {
161 u16 opcode;
162 bool has_inbox;
163 bool has_outbox;
164 bool out_is_imm;
165 bool encode_slave_id;
166 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox);
168 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
169 struct mlx4_cmd_mailbox *inbox,
170 struct mlx4_cmd_mailbox *outbox,
171 struct mlx4_cmd_info *cmd);
172};
173
225c7b1f
RD		 174#ifdef CONFIG_MLX4_DEBUG
175extern int mlx4_debug_level;
7b0f5df4
RD		 176#else /* CONFIG_MLX4_DEBUG */
177#define mlx4_debug_level (0)
178#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 179
180#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 181do { \
182 if (mlx4_debug_level) \
183 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
184} while (0)
225c7b1f 185
225c7b1f 186#define mlx4_err(mdev, format, arg...) \
0a645e80 187 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 188#define mlx4_info(mdev, format, arg...) \
0a645e80 189 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 190#define mlx4_warn(mdev, format, arg...) \
0a645e80 191 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 192
0ec2c0f8 193extern int mlx4_log_num_mgm_entry_size;
2b8fb286 194extern int log_mtts_per_seg;
0ec2c0f8 195
623ed84b
JM		 196#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
197#define ALL_SLAVES 0xff
198
225c7b1f
RD		 199struct mlx4_bitmap {
200 u32 last;
201 u32 top;
202 u32 max;
93fc9e1b 203 u32 reserved_top;
225c7b1f 204 u32 mask;
42d1e017 205 u32 avail;
225c7b1f
RD		 206 spinlock_t lock;
207 unsigned long *table;
208};
209
210struct mlx4_buddy {
211 unsigned long **bits;
e4044cfc 212 unsigned int *num_free;
225c7b1f
RD		 213 int max_order;
214 spinlock_t lock;
215};
216
217struct mlx4_icm;
218
219struct mlx4_icm_table {
220 u64 virt;
221 int num_icm;
222 int num_obj;
223 int obj_size;
224 int lowmem;
5b0bf5e2 225 int coherent;
225c7b1f
RD		 226 struct mutex mutex;
227 struct mlx4_icm **icm;
228};
229
c82e9aa0
EC		 230/*
231 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
232 */
233struct mlx4_mpt_entry {
234 __be32 flags;
235 __be32 qpn;
236 __be32 key;
237 __be32 pd_flags;
238 __be64 start;
239 __be64 length;
240 __be32 lkey;
241 __be32 win_cnt;
242 u8 reserved1[3];
243 u8 mtt_rep;
2b8fb286 244 __be64 mtt_addr;
c82e9aa0
EC		 245 __be32 mtt_sz;
246 __be32 entity_size;
247 __be32 first_byte_offset;
248} __packed;
249
250/*
251 * Must be packed because start is 64 bits but only aligned to 32 bits.
252 */
253struct mlx4_eq_context {
254 __be32 flags;
255 u16 reserved1[3];
256 __be16 page_offset;
257 u8 log_eq_size;
258 u8 reserved2[4];
259 u8 eq_period;
260 u8 reserved3;
261 u8 eq_max_count;
262 u8 reserved4[3];
263 u8 intr;
264 u8 log_page_size;
265 u8 reserved5[2];
266 u8 mtt_base_addr_h;
267 __be32 mtt_base_addr_l;
268 u32 reserved6[2];
269 __be32 consumer_index;
270 __be32 producer_index;
271 u32 reserved7[4];
272};
273
274struct mlx4_cq_context {
275 __be32 flags;
276 u16 reserved1[3];
277 __be16 page_offset;
278 __be32 logsize_usrpage;
279 __be16 cq_period;
280 __be16 cq_max_count;
281 u8 reserved2[3];
282 u8 comp_eqn;
283 u8 log_page_size;
284 u8 reserved3[2];
285 u8 mtt_base_addr_h;
286 __be32 mtt_base_addr_l;
287 __be32 last_notified_index;
288 __be32 solicit_producer_index;
289 __be32 consumer_index;
290 __be32 producer_index;
291 u32 reserved4[2];
292 __be64 db_rec_addr;
293};
294
295struct mlx4_srq_context {
296 __be32 state_logsize_srqn;
297 u8 logstride;
298 u8 reserved1;
299 __be16 xrcd;
300 __be32 pg_offset_cqn;
301 u32 reserved2;
302 u8 log_page_size;
303 u8 reserved3[2];
304 u8 mtt_base_addr_h;
305 __be32 mtt_base_addr_l;
306 __be32 pd;
307 __be16 limit_watermark;
308 __be16 wqe_cnt;
309 u16 reserved4;
310 __be16 wqe_counter;
311 u32 reserved5;
312 __be64 db_rec_addr;
313};
314
623ed84b
JM		 315struct mlx4_eqe {
316 u8 reserved1;
317 u8 type;
318 u8 reserved2;
319 u8 subtype;
320 union {
321 u32 raw[6];
322 struct {
323 __be32 cqn;
324 } __packed comp;
325 struct {
326 u16 reserved1;
327 __be16 token;
328 u32 reserved2;
329 u8 reserved3[3];
330 u8 status;
331 __be64 out_param;
332 } __packed cmd;
333 struct {
334 __be32 qpn;
335 } __packed qp;
336 struct {
337 __be32 srqn;
338 } __packed srq;
339 struct {
340 __be32 cqn;
341 u32 reserved1;
342 u8 reserved2[3];
343 u8 syndrome;
344 } __packed cq_err;
345 struct {
346 u32 reserved1[2];
347 __be32 port;
348 } __packed port_change;
349 struct {
350 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
351 u32 reserved;
352 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
353 } __packed comm_channel_arm;
354 struct {
355 u8 port;
356 u8 reserved[3];
357 __be64 mac;
358 } __packed mac_update;
359 struct {
360 u8 port;
361 } __packed sw_event;
362 struct {
363 __be32 slave_id;
364 } __packed flr_event;
365 } event;
366 u8 slave_id;
367 u8 reserved3[2];
368 u8 owner;
369} __packed;
370
225c7b1f
RD		 371struct mlx4_eq {
372 struct mlx4_dev *dev;
373 void __iomem *doorbell;
374 int eqn;
375 u32 cons_index;
376 u16 irq;
377 u16 have_irq;
378 int nent;
379 struct mlx4_buf_list *page_list;
380 struct mlx4_mtt mtt;
381};
382
623ed84b
JM		 383struct mlx4_slave_eqe {
384 u8 type;
385 u8 port;
386 u32 param;
387};
388
389struct mlx4_slave_event_eq_info {
390 u32 eqn;
391 u16 token;
392 u64 event_type;
393};
394
225c7b1f
RD		 395struct mlx4_profile {
396 int num_qp;
397 int rdmarc_per_qp;
398 int num_srq;
399 int num_cq;
400 int num_mcg;
401 int num_mpt;
402 int num_mtt;
403};
404
405struct mlx4_fw {
406 u64 clr_int_base;
407 u64 catas_offset;
623ed84b 408 u64 comm_base;
225c7b1f
RD		 409 struct mlx4_icm *fw_icm;
410 struct mlx4_icm *aux_icm;
411 u32 catas_size;
412 u16 fw_pages;
413 u8 clr_int_bar;
414 u8 catas_bar;
623ed84b
JM		 415 u8 comm_bar;
416};
417
418struct mlx4_comm {
419 u32 slave_write;
420 u32 slave_read;
225c7b1f
RD		 421};
422
ffe455ad
EE		 423enum {
424 MLX4_MCAST_CONFIG = 0,
425 MLX4_MCAST_DISABLE = 1,
426 MLX4_MCAST_ENABLE = 2,
427};
428
623ed84b
JM		 429#define VLAN_FLTR_SIZE 128
430
431struct mlx4_vlan_fltr {
432 __be32 entry[VLAN_FLTR_SIZE];
433};
434
ffe455ad
EE		 435struct mlx4_mcast_entry {
436 struct list_head list;
437 u64 addr;
438};
439
b12d93d6
YP		 440struct mlx4_promisc_qp {
441 struct list_head list;
442 u32 qpn;
443};
444
445struct mlx4_steer_index {
446 struct list_head list;
447 unsigned int index;
448 struct list_head duplicates;
449};
450
623ed84b
JM		 451struct mlx4_slave_state {
452 u8 comm_toggle;
453 u8 last_cmd;
454 u8 init_port_mask;
455 bool active;
456 u8 function;
457 dma_addr_t vhcr_dma;
458 u16 mtu[MLX4_MAX_PORTS + 1];
459 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
460 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
461 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
462 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
463 struct mlx4_slave_event_eq_info event_eq;
464 u16 eq_pi;
465 u16 eq_ci;
466 spinlock_t lock;
467 /*initialized via the kzalloc*/
468 u8 is_slave_going_down;
469 u32 cookie;
470};
471
472struct slave_list {
473 struct mutex mutex;
474 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
475};
476
477struct mlx4_resource_tracker {
478 spinlock_t lock;
479 /* tree for each resources */
480 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
481 /* num_of_slave's lists, one per slave */
482 struct slave_list *slave_list;
483};
484
485#define SLAVE_EVENT_EQ_SIZE 128
486struct mlx4_slave_event_eq {
487 u32 eqn;
488 u32 cons;
489 u32 prod;
490 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
491};
492
493struct mlx4_master_qp0_state {
494 int proxy_qp0_active;
495 int qp0_active;
496 int port_active;
497};
498
499struct mlx4_mfunc_master_ctx {
500 struct mlx4_slave_state *slave_state;
501 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
502 int init_port_ref[MLX4_MAX_PORTS + 1];
503 u16 max_mtu[MLX4_MAX_PORTS + 1];
504 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
505 struct mlx4_resource_tracker res_tracker;
506 struct workqueue_struct *comm_wq;
507 struct work_struct comm_work;
508 struct work_struct slave_event_work;
509 struct work_struct slave_flr_event_work;
510 spinlock_t slave_state_lock;
f5311ac1 511 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 512 struct mlx4_eqe cmd_eqe;
513 struct mlx4_slave_event_eq slave_eq;
514 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
515};
516
517struct mlx4_mfunc {
518 struct mlx4_comm __iomem *comm;
519 struct mlx4_vhcr_cmd *vhcr;
520 dma_addr_t vhcr_dma;
521
522 struct mlx4_mfunc_master_ctx master;
523};
524
225c7b1f
RD		 525struct mlx4_cmd {
526 struct pci_pool *pool;
527 void __iomem *hcr;
528 struct mutex hcr_mutex;
529 struct semaphore poll_sem;
530 struct semaphore event_sem;
623ed84b 531 struct semaphore slave_sem;
225c7b1f
RD		 532 int max_cmds;
533 spinlock_t context_lock;
534 int free_head;
535 struct mlx4_cmd_context *context;
536 u16 token_mask;
537 u8 use_events;
538 u8 toggle;
623ed84b 539 u8 comm_toggle;
225c7b1f
RD		 540};
541
542struct mlx4_uar_table {
543 struct mlx4_bitmap bitmap;
544};
545
546struct mlx4_mr_table {
547 struct mlx4_bitmap mpt_bitmap;
548 struct mlx4_buddy mtt_buddy;
549 u64 mtt_base;
550 u64 mpt_base;
551 struct mlx4_icm_table mtt_table;
552 struct mlx4_icm_table dmpt_table;
553};
554
555struct mlx4_cq_table {
556 struct mlx4_bitmap bitmap;
557 spinlock_t lock;
558 struct radix_tree_root tree;
559 struct mlx4_icm_table table;
560 struct mlx4_icm_table cmpt_table;
561};
562
563struct mlx4_eq_table {
564 struct mlx4_bitmap bitmap;
b8dd786f 565 char *irq_names;
225c7b1f 566 void __iomem *clr_int;
b8dd786f 567 void __iomem **uar_map;
225c7b1f 568 u32 clr_mask;
b8dd786f 569 struct mlx4_eq *eq;
fa0681d2 570 struct mlx4_icm_table table;
225c7b1f
RD		 571 struct mlx4_icm_table cmpt_table;
572 int have_irq;
573 u8 inta_pin;
574};
575
576struct mlx4_srq_table {
577 struct mlx4_bitmap bitmap;
578 spinlock_t lock;
579 struct radix_tree_root tree;
580 struct mlx4_icm_table table;
581 struct mlx4_icm_table cmpt_table;
582};
583
584struct mlx4_qp_table {
585 struct mlx4_bitmap bitmap;
586 u32 rdmarc_base;
587 int rdmarc_shift;
588 spinlock_t lock;
589 struct mlx4_icm_table qp_table;
590 struct mlx4_icm_table auxc_table;
591 struct mlx4_icm_table altc_table;
592 struct mlx4_icm_table rdmarc_table;
593 struct mlx4_icm_table cmpt_table;
594};
595
596struct mlx4_mcg_table {
597 struct mutex mutex;
598 struct mlx4_bitmap bitmap;
599 struct mlx4_icm_table table;
600};
601
602struct mlx4_catas_err {
603 u32 __iomem *map;
ee49bd93
JM		 604 struct timer_list timer;
605 struct list_head list;
225c7b1f
RD		 606};
607
2a2336f8
YP		 608#define MLX4_MAX_MAC_NUM 128
609#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
610
611struct mlx4_mac_table {
612 __be64 entries[MLX4_MAX_MAC_NUM];
613 int refs[MLX4_MAX_MAC_NUM];
614 struct mutex mutex;
615 int total;
616 int max;
617};
618
619#define MLX4_MAX_VLAN_NUM 128
620#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
621
622struct mlx4_vlan_table {
623 __be32 entries[MLX4_MAX_VLAN_NUM];
624 int refs[MLX4_MAX_VLAN_NUM];
625 struct mutex mutex;
626 int total;
627 int max;
628};
629
ffe455ad
EE		 630#define SET_PORT_GEN_ALL_VALID 0x7
631#define SET_PORT_PROMISC_SHIFT 31
632#define SET_PORT_MC_PROMISC_SHIFT 30
633
634enum {
635 MCAST_DIRECT_ONLY = 0,
636 MCAST_DIRECT = 1,
637 MCAST_DEFAULT = 2
638};
639
640
641struct mlx4_set_port_general_context {
642 u8 reserved[3];
643 u8 flags;
644 u16 reserved2;
645 __be16 mtu;
646 u8 pptx;
647 u8 pfctx;
648 u16 reserved3;
649 u8 pprx;
650 u8 pfcrx;
651 u16 reserved4;
652};
653
654struct mlx4_set_port_rqp_calc_context {
655 __be32 base_qpn;
656 u8 rererved;
657 u8 n_mac;
658 u8 n_vlan;
659 u8 n_prio;
660 u8 reserved2[3];
661 u8 mac_miss;
662 u8 intra_no_vlan;
663 u8 no_vlan;
664 u8 intra_vlan_miss;
665 u8 vlan_miss;
666 u8 reserved3[3];
667 u8 no_vlan_prio;
668 __be32 promisc;
669 __be32 mcast;
670};
671
1679200f
YP		 672struct mlx4_mac_entry {
673 u64 mac;
674};
675
2a2336f8
YP		 676struct mlx4_port_info {
677 struct mlx4_dev *dev;
678 int port;
7ff93f8b
YP		 679 char dev_name[16];
680 struct device_attribute port_attr;
681 enum mlx4_port_type tmp_type;
2a2336f8 682 struct mlx4_mac_table mac_table;
1679200f 683 struct radix_tree_root mac_tree;
2a2336f8 684 struct mlx4_vlan_table vlan_table;
1679200f 685 int base_qpn;
2a2336f8
YP		 686};
687
27bf91d6
YP		 688struct mlx4_sense {
689 struct mlx4_dev *dev;
690 u8 do_sense_port[MLX4_MAX_PORTS + 1];
691 u8 sense_allowed[MLX4_MAX_PORTS + 1];
692 struct delayed_work sense_poll;
693};
694
0b7ca5a9
YP		 695struct mlx4_msix_ctl {
696 u64 pool_bm;
697 spinlock_t pool_lock;
698};
699
b12d93d6
YP		 700struct mlx4_steer {
701 struct list_head promisc_qps[MLX4_NUM_STEERS];
702 struct list_head steer_entries[MLX4_NUM_STEERS];
703 struct list_head high_prios;
704};
705
225c7b1f
RD		 706struct mlx4_priv {
707 struct mlx4_dev dev;
708
709 struct list_head dev_list;
710 struct list_head ctx_list;
711 spinlock_t ctx_lock;
712
6296883c
YP		 713 struct list_head pgdir_list;
714 struct mutex pgdir_mutex;
715
225c7b1f
RD		 716 struct mlx4_fw fw;
717 struct mlx4_cmd cmd;
623ed84b 718 struct mlx4_mfunc mfunc;
225c7b1f
RD		 719
720 struct mlx4_bitmap pd_bitmap;
012a8ff5 721 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 722 struct mlx4_uar_table uar_table;
723 struct mlx4_mr_table mr_table;
724 struct mlx4_cq_table cq_table;
725 struct mlx4_eq_table eq_table;
726 struct mlx4_srq_table srq_table;
727 struct mlx4_qp_table qp_table;
728 struct mlx4_mcg_table mcg_table;
f2a3f6a3 729 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 730
731 struct mlx4_catas_err catas_err;
732
733 void __iomem *clr_base;
734
735 struct mlx4_uar driver_uar;
736 void __iomem *kar;
2a2336f8 737 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 738 struct mlx4_sense sense;
7ff93f8b 739 struct mutex port_mutex;
0b7ca5a9 740 struct mlx4_msix_ctl msix_ctl;
b12d93d6 741 struct mlx4_steer *steer;
c1b43dca
EC		 742 struct list_head bf_list;
743 struct mutex bf_mutex;
744 struct io_mapping *bf_mapping;
ea51b377 745 int reserved_mtts;
225c7b1f
RD		 746};
747
748static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
749{
750 return container_of(dev, struct mlx4_priv, dev);
751}
752
27bf91d6
YP		 753#define MLX4_SENSE_RANGE (HZ * 3)
754
755extern struct workqueue_struct *mlx4_wq;
756
225c7b1f
RD		 757u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
758void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 759u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
760void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 761u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 762int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
763 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 764void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
765
766int mlx4_reset(struct mlx4_dev *dev);
767
b8dd786f
YP		 768int mlx4_alloc_eq_table(struct mlx4_dev *dev);
769void mlx4_free_eq_table(struct mlx4_dev *dev);
770
225c7b1f 771int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 772int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 773int mlx4_init_uar_table(struct mlx4_dev *dev);
774int mlx4_init_mr_table(struct mlx4_dev *dev);
775int mlx4_init_eq_table(struct mlx4_dev *dev);
776int mlx4_init_cq_table(struct mlx4_dev *dev);
777int mlx4_init_qp_table(struct mlx4_dev *dev);
778int mlx4_init_srq_table(struct mlx4_dev *dev);
779int mlx4_init_mcg_table(struct mlx4_dev *dev);
780
781void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 782void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 783void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
784void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
785void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
786void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
787void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
788void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
789void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 790int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
791void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
792int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
793void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
794int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
795void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
796int __mlx4_mr_reserve(struct mlx4_dev *dev);
797void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
798int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
799void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
800u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
801void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 802
623ed84b
JM		 803int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
804 struct mlx4_vhcr *vhcr,
805 struct mlx4_cmd_mailbox *inbox,
806 struct mlx4_cmd_mailbox *outbox,
807 struct mlx4_cmd_info *cmd);
808int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
809 struct mlx4_vhcr *vhcr,
810 struct mlx4_cmd_mailbox *inbox,
811 struct mlx4_cmd_mailbox *outbox,
812 struct mlx4_cmd_info *cmd);
813int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
814 struct mlx4_vhcr *vhcr,
815 struct mlx4_cmd_mailbox *inbox,
816 struct mlx4_cmd_mailbox *outbox,
817 struct mlx4_cmd_info *cmd);
818int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
819 struct mlx4_vhcr *vhcr,
820 struct mlx4_cmd_mailbox *inbox,
821 struct mlx4_cmd_mailbox *outbox,
822 struct mlx4_cmd_info *cmd);
823int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
824 struct mlx4_vhcr *vhcr,
825 struct mlx4_cmd_mailbox *inbox,
826 struct mlx4_cmd_mailbox *outbox,
827 struct mlx4_cmd_info *cmd);
828int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
829 struct mlx4_vhcr *vhcr,
830 struct mlx4_cmd_mailbox *inbox,
831 struct mlx4_cmd_mailbox *outbox,
832 struct mlx4_cmd_info *cmd);
833int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
834 struct mlx4_vhcr *vhcr,
835 struct mlx4_cmd_mailbox *inbox,
836 struct mlx4_cmd_mailbox *outbox,
837 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 838int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
839 int *base);
840void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
841int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
842void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
843int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
844int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
845 int start_index, int npages, u64 *page_list);
623ed84b 846
ee49bd93
JM		 847void mlx4_start_catas_poll(struct mlx4_dev *dev);
848void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 849void mlx4_catas_init(void);
ee49bd93 850int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 851int mlx4_register_device(struct mlx4_dev *dev);
852void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea 853void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f
RD		 854
855struct mlx4_dev_cap;
856struct mlx4_init_hca_param;
857
858u64 mlx4_make_profile(struct mlx4_dev *dev,
859 struct mlx4_profile *request,
860 struct mlx4_dev_cap *dev_cap,
861 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 862void mlx4_master_comm_channel(struct work_struct *work);
863void mlx4_gen_slave_eqe(struct work_struct *work);
864void mlx4_master_handle_slave_flr(struct work_struct *work);
865
866int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd);
871int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
872 struct mlx4_vhcr *vhcr,
873 struct mlx4_cmd_mailbox *inbox,
874 struct mlx4_cmd_mailbox *outbox,
875 struct mlx4_cmd_info *cmd);
876int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
877 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
878 struct mlx4_cmd_mailbox *outbox,
879 struct mlx4_cmd_info *cmd);
880int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
881 struct mlx4_vhcr *vhcr,
882 struct mlx4_cmd_mailbox *inbox,
883 struct mlx4_cmd_mailbox *outbox,
884 struct mlx4_cmd_info *cmd);
885int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
886 struct mlx4_vhcr *vhcr,
887 struct mlx4_cmd_mailbox *inbox,
888 struct mlx4_cmd_mailbox *outbox,
889 struct mlx4_cmd_info *cmd);
890int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
891 struct mlx4_vhcr *vhcr,
892 struct mlx4_cmd_mailbox *inbox,
893 struct mlx4_cmd_mailbox *outbox,
894 struct mlx4_cmd_info *cmd);
895int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
896 struct mlx4_vhcr *vhcr,
897 struct mlx4_cmd_mailbox *inbox,
898 struct mlx4_cmd_mailbox *outbox,
899 struct mlx4_cmd_info *cmd);
900int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
901 struct mlx4_vhcr *vhcr,
902 struct mlx4_cmd_mailbox *inbox,
903 struct mlx4_cmd_mailbox *outbox,
904 struct mlx4_cmd_info *cmd);
905int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
906 struct mlx4_vhcr *vhcr,
907 struct mlx4_cmd_mailbox *inbox,
908 struct mlx4_cmd_mailbox *outbox,
909 struct mlx4_cmd_info *cmd);
910int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
911 struct mlx4_vhcr *vhcr,
912 struct mlx4_cmd_mailbox *inbox,
913 struct mlx4_cmd_mailbox *outbox,
914 struct mlx4_cmd_info *cmd);
915int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
916 struct mlx4_vhcr *vhcr,
917 struct mlx4_cmd_mailbox *inbox,
918 struct mlx4_cmd_mailbox *outbox,
919 struct mlx4_cmd_info *cmd);
920int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
921 struct mlx4_vhcr *vhcr,
922 struct mlx4_cmd_mailbox *inbox,
923 struct mlx4_cmd_mailbox *outbox,
924 struct mlx4_cmd_info *cmd);
925int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
926 struct mlx4_vhcr *vhcr,
927 struct mlx4_cmd_mailbox *inbox,
928 struct mlx4_cmd_mailbox *outbox,
929 struct mlx4_cmd_info *cmd);
930int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
931 struct mlx4_vhcr *vhcr,
932 struct mlx4_cmd_mailbox *inbox,
933 struct mlx4_cmd_mailbox *outbox,
934 struct mlx4_cmd_info *cmd);
935int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
936 struct mlx4_vhcr *vhcr,
937 struct mlx4_cmd_mailbox *inbox,
938 struct mlx4_cmd_mailbox *outbox,
939 struct mlx4_cmd_info *cmd);
940int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
941 struct mlx4_vhcr *vhcr,
942 struct mlx4_cmd_mailbox *inbox,
943 struct mlx4_cmd_mailbox *outbox,
944 struct mlx4_cmd_info *cmd);
945int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
946 struct mlx4_vhcr *vhcr,
947 struct mlx4_cmd_mailbox *inbox,
948 struct mlx4_cmd_mailbox *outbox,
949 struct mlx4_cmd_info *cmd);
950int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
951 struct mlx4_vhcr *vhcr,
952 struct mlx4_cmd_mailbox *inbox,
953 struct mlx4_cmd_mailbox *outbox,
954 struct mlx4_cmd_info *cmd);
955
956int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 957
225c7b1f
RD		 958int mlx4_cmd_init(struct mlx4_dev *dev);
959void mlx4_cmd_cleanup(struct mlx4_dev *dev);
960void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
961int mlx4_cmd_use_events(struct mlx4_dev *dev);
962void mlx4_cmd_use_polling(struct mlx4_dev *dev);
963
964void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
965void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
966
967void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
968
969void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
970
971void mlx4_handle_catas_err(struct mlx4_dev *dev);
972
ab6dc30d
YP		 973int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
974 enum mlx4_port_type *type);
27bf91d6
YP		 975void mlx4_do_sense_ports(struct mlx4_dev *dev,
976 enum mlx4_port_type *stype,
977 enum mlx4_port_type *defaults);
978void mlx4_start_sense(struct mlx4_dev *dev);
979void mlx4_stop_sense(struct mlx4_dev *dev);
980void mlx4_sense_init(struct mlx4_dev *dev);
981int mlx4_check_port_params(struct mlx4_dev *dev,
982 enum mlx4_port_type *port_type);
983int mlx4_change_port_types(struct mlx4_dev *dev,
984 enum mlx4_port_type *port_types);
985
2a2336f8
YP		 986void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
987void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
988
7ff93f8b 989int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 990/* resource tracker functions*/
991int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
992 enum mlx4_resource resource_type,
993 int resource_id, int *slave);
994void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
995int mlx4_init_resource_tracker(struct mlx4_dev *dev);
996
997void mlx4_free_resource_tracker(struct mlx4_dev *dev);
998
999int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1000 struct mlx4_vhcr *vhcr,
1001 struct mlx4_cmd_mailbox *inbox,
1002 struct mlx4_cmd_mailbox *outbox,
1003 struct mlx4_cmd_info *cmd);
1004int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1005 struct mlx4_vhcr *vhcr,
1006 struct mlx4_cmd_mailbox *inbox,
1007 struct mlx4_cmd_mailbox *outbox,
1008 struct mlx4_cmd_info *cmd);
1009int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1010 struct mlx4_vhcr *vhcr,
1011 struct mlx4_cmd_mailbox *inbox,
1012 struct mlx4_cmd_mailbox *outbox,
1013 struct mlx4_cmd_info *cmd);
1014int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1015 struct mlx4_vhcr *vhcr,
1016 struct mlx4_cmd_mailbox *inbox,
1017 struct mlx4_cmd_mailbox *outbox,
1018 struct mlx4_cmd_info *cmd);
9a5aa622 1019int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
97285b78 1020int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
7ff93f8b 1021
623ed84b
JM		 1022
1023int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd);
1028
1029int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1034int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1035 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1036int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1037 int block_mcast_loopback, enum mlx4_protocol prot,
1038 enum mlx4_steer_type steer);
623ed84b
JM		 1039int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1040 struct mlx4_vhcr *vhcr,
1041 struct mlx4_cmd_mailbox *inbox,
1042 struct mlx4_cmd_mailbox *outbox,
1043 struct mlx4_cmd_info *cmd);
1044int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1045 struct mlx4_vhcr *vhcr,
1046 struct mlx4_cmd_mailbox *inbox,
1047 struct mlx4_cmd_mailbox *outbox,
1048 struct mlx4_cmd_info *cmd);
1049int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1050 int port, void *buf);
1051int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1052 struct mlx4_cmd_mailbox *outbox);
1053int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1054 struct mlx4_vhcr *vhcr,
1055 struct mlx4_cmd_mailbox *inbox,
1056 struct mlx4_cmd_mailbox *outbox,
1057 struct mlx4_cmd_info *cmd);
1058int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1059 struct mlx4_vhcr *vhcr,
1060 struct mlx4_cmd_mailbox *inbox,
1061 struct mlx4_cmd_mailbox *outbox,
1062 struct mlx4_cmd_info *cmd);
1063int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1064 struct mlx4_vhcr *vhcr,
1065 struct mlx4_cmd_mailbox *inbox,
1066 struct mlx4_cmd_mailbox *outbox,
1067 struct mlx4_cmd_info *cmd);
f5311ac1 1068
0ec2c0f8
EE		 1069int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1070int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1071
5cc914f1
MA		 1072static inline void set_param_l(u64 *arg, u32 val)
1073{
1074 *((u32 *)arg) = val;
1075}
1076
1077static inline void set_param_h(u64 *arg, u32 val)
1078{
1079 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1080}
1081
1082static inline u32 get_param_l(u64 *arg)
1083{
1084 return (u32) (*arg & 0xffffffff);
1085}
1086
1087static inline u32 get_param_h(u64 *arg)
1088{
1089 return (u32)(*arg >> 32);
1090}
1091
c82e9aa0
EC		 1092static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1093{
1094 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1095}
1096
f5311ac1
JM		 1097#define NOT_MASKED_PD_BITS 17
1098
225c7b1f 1099#endif /* MLX4_H */
Linux kernel - Deliverables
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