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net/mlx4: Correctly configure single ported VFs from the host
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / resource_tracker.c
CommitLineData
c82e9aa0
EC		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
4 * All rights reserved.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/sched.h>
37#include <linux/pci.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/io.h>
e143a1ad 41#include <linux/slab.h>
c82e9aa0
EC		 42#include <linux/mlx4/cmd.h>
43#include <linux/mlx4/qp.h>
af22d9de 44#include <linux/if_ether.h>
7fb40f87 45#include <linux/etherdevice.h>
c82e9aa0
EC		 46
47#include "mlx4.h"
48#include "fw.h"
49
50#define MLX4_MAC_VALID (1ull << 63)
c82e9aa0
EC		 51
52struct mac_res {
53 struct list_head list;
54 u64 mac;
2f5bb473
JM		 55 int ref_count;
56 u8 smac_index;
c82e9aa0
EC		 57 u8 port;
58};
59
4874080d
JM		 60struct vlan_res {
61 struct list_head list;
62 u16 vlan;
63 int ref_count;
64 int vlan_index;
65 u8 port;
66};
67
c82e9aa0
EC		 68struct res_common {
69 struct list_head list;
4af1c048 70 struct rb_node node;
aa1ec3dd 71 u64 res_id;
c82e9aa0
EC		 72 int owner;
73 int state;
74 int from_state;
75 int to_state;
76 int removing;
77};
78
79enum {
80 RES_ANY_BUSY = 1
81};
82
83struct res_gid {
84 struct list_head list;
85 u8 gid[16];
86 enum mlx4_protocol prot;
9f5b6c63 87 enum mlx4_steer_type steer;
fab1e24a 88 u64 reg_id;
c82e9aa0
EC		 89};
90
91enum res_qp_states {
92 RES_QP_BUSY = RES_ANY_BUSY,
93
94 /* QP number was allocated */
95 RES_QP_RESERVED,
96
97 /* ICM memory for QP context was mapped */
98 RES_QP_MAPPED,
99
100 /* QP is in hw ownership */
101 RES_QP_HW
102};
103
c82e9aa0
EC		 104struct res_qp {
105 struct res_common com;
106 struct res_mtt *mtt;
107 struct res_cq *rcq;
108 struct res_cq *scq;
109 struct res_srq *srq;
110 struct list_head mcg_list;
111 spinlock_t mcg_spl;
112 int local_qpn;
2c473ae7 113 atomic_t ref_count;
b01978ca 114 u32 qpc_flags;
f0f829bf 115 /* saved qp params before VST enforcement in order to restore on VGT */
b01978ca 116 u8 sched_queue;
f0f829bf
RE		 117 __be32 param3;
118 u8 vlan_control;
119 u8 fvl_rx;
120 u8 pri_path_fl;
121 u8 vlan_index;
122 u8 feup;
c82e9aa0
EC		 123};
124
125enum res_mtt_states {
126 RES_MTT_BUSY = RES_ANY_BUSY,
127 RES_MTT_ALLOCATED,
128};
129
130static inline const char *mtt_states_str(enum res_mtt_states state)
131{
132 switch (state) {
133 case RES_MTT_BUSY: return "RES_MTT_BUSY";
134 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
135 default: return "Unknown";
136 }
137}
138
139struct res_mtt {
140 struct res_common com;
141 int order;
142 atomic_t ref_count;
143};
144
145enum res_mpt_states {
146 RES_MPT_BUSY = RES_ANY_BUSY,
147 RES_MPT_RESERVED,
148 RES_MPT_MAPPED,
149 RES_MPT_HW,
150};
151
152struct res_mpt {
153 struct res_common com;
154 struct res_mtt *mtt;
155 int key;
156};
157
158enum res_eq_states {
159 RES_EQ_BUSY = RES_ANY_BUSY,
160 RES_EQ_RESERVED,
161 RES_EQ_HW,
162};
163
164struct res_eq {
165 struct res_common com;
166 struct res_mtt *mtt;
167};
168
169enum res_cq_states {
170 RES_CQ_BUSY = RES_ANY_BUSY,
171 RES_CQ_ALLOCATED,
172 RES_CQ_HW,
173};
174
175struct res_cq {
176 struct res_common com;
177 struct res_mtt *mtt;
178 atomic_t ref_count;
179};
180
181enum res_srq_states {
182 RES_SRQ_BUSY = RES_ANY_BUSY,
183 RES_SRQ_ALLOCATED,
184 RES_SRQ_HW,
185};
186
c82e9aa0
EC		 187struct res_srq {
188 struct res_common com;
189 struct res_mtt *mtt;
190 struct res_cq *cq;
191 atomic_t ref_count;
192};
193
194enum res_counter_states {
195 RES_COUNTER_BUSY = RES_ANY_BUSY,
196 RES_COUNTER_ALLOCATED,
197};
198
c82e9aa0
EC		 199struct res_counter {
200 struct res_common com;
201 int port;
202};
203
ba062d52
JM		 204enum res_xrcdn_states {
205 RES_XRCD_BUSY = RES_ANY_BUSY,
206 RES_XRCD_ALLOCATED,
207};
208
209struct res_xrcdn {
210 struct res_common com;
211 int port;
212};
213
1b9c6b06
HHZ		 214enum res_fs_rule_states {
215 RES_FS_RULE_BUSY = RES_ANY_BUSY,
216 RES_FS_RULE_ALLOCATED,
217};
218
219struct res_fs_rule {
220 struct res_common com;
2c473ae7 221 int qpn;
1b9c6b06
HHZ		 222};
223
b6ffaeff
JM		 224static int mlx4_is_eth(struct mlx4_dev *dev, int port)
225{
226 return dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
227}
228
4af1c048
HHZ		 229static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
230{
231 struct rb_node *node = root->rb_node;
232
233 while (node) {
234 struct res_common *res = container_of(node, struct res_common,
235 node);
236
237 if (res_id < res->res_id)
238 node = node->rb_left;
239 else if (res_id > res->res_id)
240 node = node->rb_right;
241 else
242 return res;
243 }
244 return NULL;
245}
246
247static int res_tracker_insert(struct rb_root *root, struct res_common *res)
248{
249 struct rb_node **new = &(root->rb_node), *parent = NULL;
250
251 /* Figure out where to put new node */
252 while (*new) {
253 struct res_common *this = container_of(*new, struct res_common,
254 node);
255
256 parent = *new;
257 if (res->res_id < this->res_id)
258 new = &((*new)->rb_left);
259 else if (res->res_id > this->res_id)
260 new = &((*new)->rb_right);
261 else
262 return -EEXIST;
263 }
264
265 /* Add new node and rebalance tree. */
266 rb_link_node(&res->node, parent, new);
267 rb_insert_color(&res->node, root);
268
269 return 0;
270}
271
54679e14
JM		 272enum qp_transition {
273 QP_TRANS_INIT2RTR,
274 QP_TRANS_RTR2RTS,
275 QP_TRANS_RTS2RTS,
276 QP_TRANS_SQERR2RTS,
277 QP_TRANS_SQD2SQD,
278 QP_TRANS_SQD2RTS
279};
280
c82e9aa0 281/* For Debug uses */
95646373 282static const char *resource_str(enum mlx4_resource rt)
c82e9aa0
EC		 283{
284 switch (rt) {
285 case RES_QP: return "RES_QP";
286 case RES_CQ: return "RES_CQ";
287 case RES_SRQ: return "RES_SRQ";
288 case RES_MPT: return "RES_MPT";
289 case RES_MTT: return "RES_MTT";
290 case RES_MAC: return "RES_MAC";
4874080d 291 case RES_VLAN: return "RES_VLAN";
c82e9aa0
EC		 292 case RES_EQ: return "RES_EQ";
293 case RES_COUNTER: return "RES_COUNTER";
1b9c6b06 294 case RES_FS_RULE: return "RES_FS_RULE";
ba062d52 295 case RES_XRCD: return "RES_XRCD";
c82e9aa0
EC		 296 default: return "Unknown resource type !!!";
297 };
298}
299
4874080d 300static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
146f3ef4
JM		 301static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
302 enum mlx4_resource res_type, int count,
303 int port)
304{
305 struct mlx4_priv *priv = mlx4_priv(dev);
306 struct resource_allocator *res_alloc =
307 &priv->mfunc.master.res_tracker.res_alloc[res_type];
308 int err = -EINVAL;
309 int allocated, free, reserved, guaranteed, from_free;
95646373 310 int from_rsvd;
146f3ef4
JM		 311
312 if (slave > dev->num_vfs)
313 return -EINVAL;
314
315 spin_lock(&res_alloc->alloc_lock);
316 allocated = (port > 0) ?
317 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] :
318 res_alloc->allocated[slave];
319 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
320 res_alloc->res_free;
321 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
322 res_alloc->res_reserved;
323 guaranteed = res_alloc->guaranteed[slave];
324
95646373
JM		 325 if (allocated + count > res_alloc->quota[slave]) {
326 mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
327 slave, port, resource_str(res_type), count,
328 allocated, res_alloc->quota[slave]);
146f3ef4 329 goto out;
95646373 330 }
146f3ef4
JM		 331
332 if (allocated + count <= guaranteed) {
333 err = 0;
95646373 334 from_rsvd = count;
146f3ef4
JM		 335 } else {
336 /* portion may need to be obtained from free area */
337 if (guaranteed - allocated > 0)
338 from_free = count - (guaranteed - allocated);
339 else
340 from_free = count;
341
95646373
JM		 342 from_rsvd = count - from_free;
343
344 if (free - from_free >= reserved)
146f3ef4 345 err = 0;
95646373
JM		 346 else
347 mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
348 slave, port, resource_str(res_type), free,
349 from_free, reserved);
146f3ef4
JM		 350 }
351
352 if (!err) {
353 /* grant the request */
354 if (port > 0) {
355 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] += count;
356 res_alloc->res_port_free[port - 1] -= count;
95646373 357 res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
146f3ef4
JM		 358 } else {
359 res_alloc->allocated[slave] += count;
360 res_alloc->res_free -= count;
95646373 361 res_alloc->res_reserved -= from_rsvd;
146f3ef4
JM		 362 }
363 }
364
365out:
366 spin_unlock(&res_alloc->alloc_lock);
367 return err;
368}
369
370static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
371 enum mlx4_resource res_type, int count,
372 int port)
373{
374 struct mlx4_priv *priv = mlx4_priv(dev);
375 struct resource_allocator *res_alloc =
376 &priv->mfunc.master.res_tracker.res_alloc[res_type];
95646373 377 int allocated, guaranteed, from_rsvd;
146f3ef4
JM		 378
379 if (slave > dev->num_vfs)
380 return;
381
382 spin_lock(&res_alloc->alloc_lock);
95646373
JM		 383
384 allocated = (port > 0) ?
385 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] :
386 res_alloc->allocated[slave];
387 guaranteed = res_alloc->guaranteed[slave];
388
389 if (allocated - count >= guaranteed) {
390 from_rsvd = 0;
391 } else {
392 /* portion may need to be returned to reserved area */
393 if (allocated - guaranteed > 0)
394 from_rsvd = count - (allocated - guaranteed);
395 else
396 from_rsvd = count;
397 }
398
146f3ef4
JM		 399 if (port > 0) {
400 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] -= count;
401 res_alloc->res_port_free[port - 1] += count;
95646373 402 res_alloc->res_port_rsvd[port - 1] += from_rsvd;
146f3ef4
JM		 403 } else {
404 res_alloc->allocated[slave] -= count;
405 res_alloc->res_free += count;
95646373 406 res_alloc->res_reserved += from_rsvd;
146f3ef4
JM		 407 }
408
409 spin_unlock(&res_alloc->alloc_lock);
410 return;
411}
412
5a0d0a61
JM		 413static inline void initialize_res_quotas(struct mlx4_dev *dev,
414 struct resource_allocator *res_alloc,
415 enum mlx4_resource res_type,
416 int vf, int num_instances)
417{
418 res_alloc->guaranteed[vf] = num_instances / (2 * (dev->num_vfs + 1));
419 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
420 if (vf == mlx4_master_func_num(dev)) {
421 res_alloc->res_free = num_instances;
422 if (res_type == RES_MTT) {
423 /* reserved mtts will be taken out of the PF allocation */
424 res_alloc->res_free += dev->caps.reserved_mtts;
425 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
426 res_alloc->quota[vf] += dev->caps.reserved_mtts;
427 }
428 }
429}
430
431void mlx4_init_quotas(struct mlx4_dev *dev)
432{
433 struct mlx4_priv *priv = mlx4_priv(dev);
434 int pf;
435
436 /* quotas for VFs are initialized in mlx4_slave_cap */
437 if (mlx4_is_slave(dev))
438 return;
439
440 if (!mlx4_is_mfunc(dev)) {
441 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
442 mlx4_num_reserved_sqps(dev);
443 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
444 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
445 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
446 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
447 return;
448 }
449
450 pf = mlx4_master_func_num(dev);
451 dev->quotas.qp =
452 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
453 dev->quotas.cq =
454 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
455 dev->quotas.srq =
456 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
457 dev->quotas.mtt =
458 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
459 dev->quotas.mpt =
460 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
461}
c82e9aa0
EC		 462int mlx4_init_resource_tracker(struct mlx4_dev *dev)
463{
464 struct mlx4_priv *priv = mlx4_priv(dev);
5a0d0a61 465 int i, j;
c82e9aa0
EC		 466 int t;
467
468 priv->mfunc.master.res_tracker.slave_list =
469 kzalloc(dev->num_slaves * sizeof(struct slave_list),
470 GFP_KERNEL);
471 if (!priv->mfunc.master.res_tracker.slave_list)
472 return -ENOMEM;
473
474 for (i = 0 ; i < dev->num_slaves; i++) {
475 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
476 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
477 slave_list[i].res_list[t]);
478 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
479 }
480
481 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
482 dev->num_slaves);
483 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
4af1c048 484 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
c82e9aa0 485
5a0d0a61
JM		 486 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
487 struct resource_allocator *res_alloc =
488 &priv->mfunc.master.res_tracker.res_alloc[i];
489 res_alloc->quota = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
490 res_alloc->guaranteed = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
491 if (i == RES_MAC || i == RES_VLAN)
492 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
493 (dev->num_vfs + 1) * sizeof(int),
494 GFP_KERNEL);
495 else
496 res_alloc->allocated = kzalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
497
498 if (!res_alloc->quota || !res_alloc->guaranteed ||
499 !res_alloc->allocated)
500 goto no_mem_err;
501
146f3ef4 502 spin_lock_init(&res_alloc->alloc_lock);
5a0d0a61 503 for (t = 0; t < dev->num_vfs + 1; t++) {
449fc488
MB		 504 struct mlx4_active_ports actv_ports =
505 mlx4_get_active_ports(dev, t);
5a0d0a61
JM		 506 switch (i) {
507 case RES_QP:
508 initialize_res_quotas(dev, res_alloc, RES_QP,
509 t, dev->caps.num_qps -
510 dev->caps.reserved_qps -
511 mlx4_num_reserved_sqps(dev));
512 break;
513 case RES_CQ:
514 initialize_res_quotas(dev, res_alloc, RES_CQ,
515 t, dev->caps.num_cqs -
516 dev->caps.reserved_cqs);
517 break;
518 case RES_SRQ:
519 initialize_res_quotas(dev, res_alloc, RES_SRQ,
520 t, dev->caps.num_srqs -
521 dev->caps.reserved_srqs);
522 break;
523 case RES_MPT:
524 initialize_res_quotas(dev, res_alloc, RES_MPT,
525 t, dev->caps.num_mpts -
526 dev->caps.reserved_mrws);
527 break;
528 case RES_MTT:
529 initialize_res_quotas(dev, res_alloc, RES_MTT,
530 t, dev->caps.num_mtts -
531 dev->caps.reserved_mtts);
532 break;
533 case RES_MAC:
534 if (t == mlx4_master_func_num(dev)) {
449fc488
MB		 535 int max_vfs_pport = 0;
536 /* Calculate the max vfs per port for */
537 /* both ports. */
538 for (j = 0; j < dev->caps.num_ports;
539 j++) {
540 struct mlx4_slaves_pport slaves_pport =
541 mlx4_phys_to_slaves_pport(dev, j + 1);
542 unsigned current_slaves =
543 bitmap_weight(slaves_pport.slaves,
544 dev->caps.num_ports) - 1;
545 if (max_vfs_pport < current_slaves)
546 max_vfs_pport =
547 current_slaves;
548 }
549 res_alloc->quota[t] =
550 MLX4_MAX_MAC_NUM -
551 2 * max_vfs_pport;
5a0d0a61
JM		 552 res_alloc->guaranteed[t] = 2;
553 for (j = 0; j < MLX4_MAX_PORTS; j++)
449fc488
MB		 554 res_alloc->res_port_free[j] =
555 MLX4_MAX_MAC_NUM;
5a0d0a61
JM		 556 } else {
557 res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
558 res_alloc->guaranteed[t] = 2;
559 }
560 break;
561 case RES_VLAN:
562 if (t == mlx4_master_func_num(dev)) {
563 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
564 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
565 for (j = 0; j < MLX4_MAX_PORTS; j++)
566 res_alloc->res_port_free[j] =
567 res_alloc->quota[t];
568 } else {
569 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
570 res_alloc->guaranteed[t] = 0;
571 }
572 break;
573 case RES_COUNTER:
574 res_alloc->quota[t] = dev->caps.max_counters;
575 res_alloc->guaranteed[t] = 0;
576 if (t == mlx4_master_func_num(dev))
577 res_alloc->res_free = res_alloc->quota[t];
578 break;
579 default:
580 break;
581 }
582 if (i == RES_MAC || i == RES_VLAN) {
449fc488
MB		 583 for (j = 0; j < dev->caps.num_ports; j++)
584 if (test_bit(j, actv_ports.ports))
585 res_alloc->res_port_rsvd[j] +=
586 res_alloc->guaranteed[t];
5a0d0a61
JM		 587 } else {
588 res_alloc->res_reserved += res_alloc->guaranteed[t];
589 }
590 }
591 }
c82e9aa0 592 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
5a0d0a61
JM		 593 return 0;
594
595no_mem_err:
596 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
597 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
598 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
599 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
600 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
601 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
602 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
603 }
604 return -ENOMEM;
c82e9aa0
EC		 605}
606
b8924951
JM		 607void mlx4_free_resource_tracker(struct mlx4_dev *dev,
608 enum mlx4_res_tracker_free_type type)
c82e9aa0
EC		 609{
610 struct mlx4_priv *priv = mlx4_priv(dev);
611 int i;
612
613 if (priv->mfunc.master.res_tracker.slave_list) {
4874080d
JM		 614 if (type != RES_TR_FREE_STRUCTS_ONLY) {
615 for (i = 0; i < dev->num_slaves; i++) {
b8924951
JM		 616 if (type == RES_TR_FREE_ALL ||
617 dev->caps.function != i)
618 mlx4_delete_all_resources_for_slave(dev, i);
4874080d
JM		 619 }
620 /* free master's vlans */
621 i = dev->caps.function;
111c6094 622 mlx4_reset_roce_gids(dev, i);
4874080d
JM		 623 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
624 rem_slave_vlans(dev, i);
625 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
626 }
b8924951
JM		 627
628 if (type != RES_TR_FREE_SLAVES_ONLY) {
5a0d0a61
JM		 629 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
630 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
631 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
632 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
633 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
634 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
635 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
636 }
b8924951
JM		 637 kfree(priv->mfunc.master.res_tracker.slave_list);
638 priv->mfunc.master.res_tracker.slave_list = NULL;
639 }
c82e9aa0
EC		 640 }
641}
642
54679e14
JM		 643static void update_pkey_index(struct mlx4_dev *dev, int slave,
644 struct mlx4_cmd_mailbox *inbox)
c82e9aa0 645{
54679e14
JM		 646 u8 sched = *(u8 *)(inbox->buf + 64);
647 u8 orig_index = *(u8 *)(inbox->buf + 35);
648 u8 new_index;
649 struct mlx4_priv *priv = mlx4_priv(dev);
650 int port;
651
652 port = (sched >> 6 & 1) + 1;
653
654 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
655 *(u8 *)(inbox->buf + 35) = new_index;
54679e14
JM		 656}
657
658static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
659 u8 slave)
660{
661 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
662 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
663 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
b6ffaeff 664 int port;
c82e9aa0 665
b6ffaeff
JM		 666 if (MLX4_QP_ST_UD == ts) {
667 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
668 if (mlx4_is_eth(dev, port))
449fc488
MB		 669 qp_ctx->pri_path.mgid_index =
670 mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
b6ffaeff
JM		 671 else
672 qp_ctx->pri_path.mgid_index = slave | 0x80;
673
674 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
675 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
676 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
677 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 678 qp_ctx->pri_path.mgid_index +=
679 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 680 qp_ctx->pri_path.mgid_index &= 0x7f;
681 } else {
682 qp_ctx->pri_path.mgid_index = slave & 0x7F;
683 }
684 }
685 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
686 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
687 if (mlx4_is_eth(dev, port)) {
449fc488
MB		 688 qp_ctx->alt_path.mgid_index +=
689 mlx4_get_base_gid_ix(dev, slave, port);
b6ffaeff
JM		 690 qp_ctx->alt_path.mgid_index &= 0x7f;
691 } else {
692 qp_ctx->alt_path.mgid_index = slave & 0x7F;
693 }
694 }
54679e14 695 }
c82e9aa0
EC		 696}
697
3f7fb021
RE		 698static int update_vport_qp_param(struct mlx4_dev *dev,
699 struct mlx4_cmd_mailbox *inbox,
b01978ca 700 u8 slave, u32 qpn)
3f7fb021
RE		 701{
702 struct mlx4_qp_context *qpc = inbox->buf + 8;
703 struct mlx4_vport_oper_state *vp_oper;
704 struct mlx4_priv *priv;
3f7fb021
RE		 705 int port;
706
707 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
708 priv = mlx4_priv(dev);
709 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
710
711 if (MLX4_VGT != vp_oper->state.default_vlan) {
b01978ca
JM		 712 /* the reserved QPs (special, proxy, tunnel)
713 * do not operate over vlans
714 */
715 if (mlx4_is_qp_reserved(dev, qpn))
716 return 0;
717
7677fc96
RE		 718 /* force strip vlan by clear vsd */
719 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
0a6eac24
RE		 720
721 if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
722 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
723 qpc->pri_path.vlan_control =
724 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
725 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
726 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
727 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
728 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
729 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
730 } else if (0 != vp_oper->state.default_vlan) {
7677fc96
RE		 731 qpc->pri_path.vlan_control =
732 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
733 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
734 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
735 } else { /* priority tagged */
736 qpc->pri_path.vlan_control =
737 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
738 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
739 }
740
741 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
3f7fb021 742 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
7677fc96
RE		 743 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
744 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
3f7fb021
RE		 745 qpc->pri_path.sched_queue &= 0xC7;
746 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
3f7fb021 747 }
e6b6a231 748 if (vp_oper->state.spoofchk) {
7677fc96 749 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
e6b6a231 750 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
e6b6a231 751 }
3f7fb021
RE		 752 return 0;
753}
754
c82e9aa0
EC		 755static int mpt_mask(struct mlx4_dev *dev)
756{
757 return dev->caps.num_mpts - 1;
758}
759
1e3f7b32 760static void *find_res(struct mlx4_dev *dev, u64 res_id,
c82e9aa0
EC		 761 enum mlx4_resource type)
762{
763 struct mlx4_priv *priv = mlx4_priv(dev);
764
4af1c048
HHZ		 765 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
766 res_id);
c82e9aa0
EC		 767}
768
aa1ec3dd 769static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 770 enum mlx4_resource type,
771 void *res)
772{
773 struct res_common *r;
774 int err = 0;
775
776 spin_lock_irq(mlx4_tlock(dev));
777 r = find_res(dev, res_id, type);
778 if (!r) {
779 err = -ENONET;
780 goto exit;
781 }
782
783 if (r->state == RES_ANY_BUSY) {
784 err = -EBUSY;
785 goto exit;
786 }
787
788 if (r->owner != slave) {
789 err = -EPERM;
790 goto exit;
791 }
792
793 r->from_state = r->state;
794 r->state = RES_ANY_BUSY;
c82e9aa0
EC		 795
796 if (res)
797 *((struct res_common **)res) = r;
798
799exit:
800 spin_unlock_irq(mlx4_tlock(dev));
801 return err;
802}
803
804int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
805 enum mlx4_resource type,
aa1ec3dd 806 u64 res_id, int *slave)
c82e9aa0
EC		 807{
808
809 struct res_common *r;
810 int err = -ENOENT;
811 int id = res_id;
812
813 if (type == RES_QP)
814 id &= 0x7fffff;
996b0541 815 spin_lock(mlx4_tlock(dev));
c82e9aa0
EC		 816
817 r = find_res(dev, id, type);
818 if (r) {
819 *slave = r->owner;
820 err = 0;
821 }
996b0541 822 spin_unlock(mlx4_tlock(dev));
c82e9aa0
EC		 823
824 return err;
825}
826
aa1ec3dd 827static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
c82e9aa0
EC		 828 enum mlx4_resource type)
829{
830 struct res_common *r;
831
832 spin_lock_irq(mlx4_tlock(dev));
833 r = find_res(dev, res_id, type);
834 if (r)
835 r->state = r->from_state;
836 spin_unlock_irq(mlx4_tlock(dev));
837}
838
839static struct res_common *alloc_qp_tr(int id)
840{
841 struct res_qp *ret;
842
843 ret = kzalloc(sizeof *ret, GFP_KERNEL);
844 if (!ret)
845 return NULL;
846
847 ret->com.res_id = id;
848 ret->com.state = RES_QP_RESERVED;
2531188b 849 ret->local_qpn = id;
c82e9aa0
EC		 850 INIT_LIST_HEAD(&ret->mcg_list);
851 spin_lock_init(&ret->mcg_spl);
2c473ae7 852 atomic_set(&ret->ref_count, 0);
c82e9aa0
EC		 853
854 return &ret->com;
855}
856
857static struct res_common *alloc_mtt_tr(int id, int order)
858{
859 struct res_mtt *ret;
860
861 ret = kzalloc(sizeof *ret, GFP_KERNEL);
862 if (!ret)
863 return NULL;
864
865 ret->com.res_id = id;
866 ret->order = order;
867 ret->com.state = RES_MTT_ALLOCATED;
868 atomic_set(&ret->ref_count, 0);
869
870 return &ret->com;
871}
872
873static struct res_common *alloc_mpt_tr(int id, int key)
874{
875 struct res_mpt *ret;
876
877 ret = kzalloc(sizeof *ret, GFP_KERNEL);
878 if (!ret)
879 return NULL;
880
881 ret->com.res_id = id;
882 ret->com.state = RES_MPT_RESERVED;
883 ret->key = key;
884
885 return &ret->com;
886}
887
888static struct res_common *alloc_eq_tr(int id)
889{
890 struct res_eq *ret;
891
892 ret = kzalloc(sizeof *ret, GFP_KERNEL);
893 if (!ret)
894 return NULL;
895
896 ret->com.res_id = id;
897 ret->com.state = RES_EQ_RESERVED;
898
899 return &ret->com;
900}
901
902static struct res_common *alloc_cq_tr(int id)
903{
904 struct res_cq *ret;
905
906 ret = kzalloc(sizeof *ret, GFP_KERNEL);
907 if (!ret)
908 return NULL;
909
910 ret->com.res_id = id;
911 ret->com.state = RES_CQ_ALLOCATED;
912 atomic_set(&ret->ref_count, 0);
913
914 return &ret->com;
915}
916
917static struct res_common *alloc_srq_tr(int id)
918{
919 struct res_srq *ret;
920
921 ret = kzalloc(sizeof *ret, GFP_KERNEL);
922 if (!ret)
923 return NULL;
924
925 ret->com.res_id = id;
926 ret->com.state = RES_SRQ_ALLOCATED;
927 atomic_set(&ret->ref_count, 0);
928
929 return &ret->com;
930}
931
932static struct res_common *alloc_counter_tr(int id)
933{
934 struct res_counter *ret;
935
936 ret = kzalloc(sizeof *ret, GFP_KERNEL);
937 if (!ret)
938 return NULL;
939
940 ret->com.res_id = id;
941 ret->com.state = RES_COUNTER_ALLOCATED;
942
943 return &ret->com;
944}
945
ba062d52
JM		 946static struct res_common *alloc_xrcdn_tr(int id)
947{
948 struct res_xrcdn *ret;
949
950 ret = kzalloc(sizeof *ret, GFP_KERNEL);
951 if (!ret)
952 return NULL;
953
954 ret->com.res_id = id;
955 ret->com.state = RES_XRCD_ALLOCATED;
956
957 return &ret->com;
958}
959
2c473ae7 960static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
1b9c6b06
HHZ		 961{
962 struct res_fs_rule *ret;
963
964 ret = kzalloc(sizeof *ret, GFP_KERNEL);
965 if (!ret)
966 return NULL;
967
968 ret->com.res_id = id;
969 ret->com.state = RES_FS_RULE_ALLOCATED;
2c473ae7 970 ret->qpn = qpn;
1b9c6b06
HHZ		 971 return &ret->com;
972}
973
aa1ec3dd 974static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
c82e9aa0
EC		 975 int extra)
976{
977 struct res_common *ret;
978
979 switch (type) {
980 case RES_QP:
981 ret = alloc_qp_tr(id);
982 break;
983 case RES_MPT:
984 ret = alloc_mpt_tr(id, extra);
985 break;
986 case RES_MTT:
987 ret = alloc_mtt_tr(id, extra);
988 break;
989 case RES_EQ:
990 ret = alloc_eq_tr(id);
991 break;
992 case RES_CQ:
993 ret = alloc_cq_tr(id);
994 break;
995 case RES_SRQ:
996 ret = alloc_srq_tr(id);
997 break;
998 case RES_MAC:
c20862c8 999 pr_err("implementation missing\n");
c82e9aa0
EC		 1000 return NULL;
1001 case RES_COUNTER:
1002 ret = alloc_counter_tr(id);
1003 break;
ba062d52
JM		 1004 case RES_XRCD:
1005 ret = alloc_xrcdn_tr(id);
1006 break;
1b9c6b06 1007 case RES_FS_RULE:
2c473ae7 1008 ret = alloc_fs_rule_tr(id, extra);
1b9c6b06 1009 break;
c82e9aa0
EC		 1010 default:
1011 return NULL;
1012 }
1013 if (ret)
1014 ret->owner = slave;
1015
1016 return ret;
1017}
1018
aa1ec3dd 1019static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1020 enum mlx4_resource type, int extra)
1021{
1022 int i;
1023 int err;
1024 struct mlx4_priv *priv = mlx4_priv(dev);
1025 struct res_common **res_arr;
1026 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4af1c048 1027 struct rb_root *root = &tracker->res_tree[type];
c82e9aa0
EC		 1028
1029 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1030 if (!res_arr)
1031 return -ENOMEM;
1032
1033 for (i = 0; i < count; ++i) {
1034 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1035 if (!res_arr[i]) {
1036 for (--i; i >= 0; --i)
1037 kfree(res_arr[i]);
1038
1039 kfree(res_arr);
1040 return -ENOMEM;
1041 }
1042 }
1043
1044 spin_lock_irq(mlx4_tlock(dev));
1045 for (i = 0; i < count; ++i) {
1046 if (find_res(dev, base + i, type)) {
1047 err = -EEXIST;
1048 goto undo;
1049 }
4af1c048 1050 err = res_tracker_insert(root, res_arr[i]);
c82e9aa0
EC		 1051 if (err)
1052 goto undo;
1053 list_add_tail(&res_arr[i]->list,
1054 &tracker->slave_list[slave].res_list[type]);
1055 }
1056 spin_unlock_irq(mlx4_tlock(dev));
1057 kfree(res_arr);
1058
1059 return 0;
1060
1061undo:
1062 for (--i; i >= base; --i)
4af1c048 1063 rb_erase(&res_arr[i]->node, root);
c82e9aa0
EC		 1064
1065 spin_unlock_irq(mlx4_tlock(dev));
1066
1067 for (i = 0; i < count; ++i)
1068 kfree(res_arr[i]);
1069
1070 kfree(res_arr);
1071
1072 return err;
1073}
1074
1075static int remove_qp_ok(struct res_qp *res)
1076{
2c473ae7
HHZ		 1077 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1078 !list_empty(&res->mcg_list)) {
1079 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1080 res->com.state, atomic_read(&res->ref_count));
c82e9aa0 1081 return -EBUSY;
2c473ae7 1082 } else if (res->com.state != RES_QP_RESERVED) {
c82e9aa0 1083 return -EPERM;
2c473ae7 1084 }
c82e9aa0
EC		 1085
1086 return 0;
1087}
1088
1089static int remove_mtt_ok(struct res_mtt *res, int order)
1090{
1091 if (res->com.state == RES_MTT_BUSY ||
1092 atomic_read(&res->ref_count)) {
c20862c8
AV		 1093 pr_devel("%s-%d: state %s, ref_count %d\n",
1094 __func__, __LINE__,
1095 mtt_states_str(res->com.state),
1096 atomic_read(&res->ref_count));
c82e9aa0
EC		 1097 return -EBUSY;
1098 } else if (res->com.state != RES_MTT_ALLOCATED)
1099 return -EPERM;
1100 else if (res->order != order)
1101 return -EINVAL;
1102
1103 return 0;
1104}
1105
1106static int remove_mpt_ok(struct res_mpt *res)
1107{
1108 if (res->com.state == RES_MPT_BUSY)
1109 return -EBUSY;
1110 else if (res->com.state != RES_MPT_RESERVED)
1111 return -EPERM;
1112
1113 return 0;
1114}
1115
1116static int remove_eq_ok(struct res_eq *res)
1117{
1118 if (res->com.state == RES_MPT_BUSY)
1119 return -EBUSY;
1120 else if (res->com.state != RES_MPT_RESERVED)
1121 return -EPERM;
1122
1123 return 0;
1124}
1125
1126static int remove_counter_ok(struct res_counter *res)
1127{
1128 if (res->com.state == RES_COUNTER_BUSY)
1129 return -EBUSY;
1130 else if (res->com.state != RES_COUNTER_ALLOCATED)
1131 return -EPERM;
1132
1133 return 0;
1134}
1135
ba062d52
JM		 1136static int remove_xrcdn_ok(struct res_xrcdn *res)
1137{
1138 if (res->com.state == RES_XRCD_BUSY)
1139 return -EBUSY;
1140 else if (res->com.state != RES_XRCD_ALLOCATED)
1141 return -EPERM;
1142
1143 return 0;
1144}
1145
1b9c6b06
HHZ		 1146static int remove_fs_rule_ok(struct res_fs_rule *res)
1147{
1148 if (res->com.state == RES_FS_RULE_BUSY)
1149 return -EBUSY;
1150 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1151 return -EPERM;
1152
1153 return 0;
1154}
1155
c82e9aa0
EC		 1156static int remove_cq_ok(struct res_cq *res)
1157{
1158 if (res->com.state == RES_CQ_BUSY)
1159 return -EBUSY;
1160 else if (res->com.state != RES_CQ_ALLOCATED)
1161 return -EPERM;
1162
1163 return 0;
1164}
1165
1166static int remove_srq_ok(struct res_srq *res)
1167{
1168 if (res->com.state == RES_SRQ_BUSY)
1169 return -EBUSY;
1170 else if (res->com.state != RES_SRQ_ALLOCATED)
1171 return -EPERM;
1172
1173 return 0;
1174}
1175
1176static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1177{
1178 switch (type) {
1179 case RES_QP:
1180 return remove_qp_ok((struct res_qp *)res);
1181 case RES_CQ:
1182 return remove_cq_ok((struct res_cq *)res);
1183 case RES_SRQ:
1184 return remove_srq_ok((struct res_srq *)res);
1185 case RES_MPT:
1186 return remove_mpt_ok((struct res_mpt *)res);
1187 case RES_MTT:
1188 return remove_mtt_ok((struct res_mtt *)res, extra);
1189 case RES_MAC:
1190 return -ENOSYS;
1191 case RES_EQ:
1192 return remove_eq_ok((struct res_eq *)res);
1193 case RES_COUNTER:
1194 return remove_counter_ok((struct res_counter *)res);
ba062d52
JM		 1195 case RES_XRCD:
1196 return remove_xrcdn_ok((struct res_xrcdn *)res);
1b9c6b06
HHZ		 1197 case RES_FS_RULE:
1198 return remove_fs_rule_ok((struct res_fs_rule *)res);
c82e9aa0
EC		 1199 default:
1200 return -EINVAL;
1201 }
1202}
1203
aa1ec3dd 1204static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
c82e9aa0
EC		 1205 enum mlx4_resource type, int extra)
1206{
aa1ec3dd 1207 u64 i;
c82e9aa0
EC		 1208 int err;
1209 struct mlx4_priv *priv = mlx4_priv(dev);
1210 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1211 struct res_common *r;
1212
1213 spin_lock_irq(mlx4_tlock(dev));
1214 for (i = base; i < base + count; ++i) {
4af1c048 1215 r = res_tracker_lookup(&tracker->res_tree[type], i);
c82e9aa0
EC		 1216 if (!r) {
1217 err = -ENOENT;
1218 goto out;
1219 }
1220 if (r->owner != slave) {
1221 err = -EPERM;
1222 goto out;
1223 }
1224 err = remove_ok(r, type, extra);
1225 if (err)
1226 goto out;
1227 }
1228
1229 for (i = base; i < base + count; ++i) {
4af1c048
HHZ		 1230 r = res_tracker_lookup(&tracker->res_tree[type], i);
1231 rb_erase(&r->node, &tracker->res_tree[type]);
c82e9aa0
EC		 1232 list_del(&r->list);
1233 kfree(r);
1234 }
1235 err = 0;
1236
1237out:
1238 spin_unlock_irq(mlx4_tlock(dev));
1239
1240 return err;
1241}
1242
1243static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1244 enum res_qp_states state, struct res_qp **qp,
1245 int alloc)
1246{
1247 struct mlx4_priv *priv = mlx4_priv(dev);
1248 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1249 struct res_qp *r;
1250 int err = 0;
1251
1252 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1253 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
c82e9aa0
EC		 1254 if (!r)
1255 err = -ENOENT;
1256 else if (r->com.owner != slave)
1257 err = -EPERM;
1258 else {
1259 switch (state) {
1260 case RES_QP_BUSY:
aa1ec3dd 1261 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1262 __func__, r->com.res_id);
1263 err = -EBUSY;
1264 break;
1265
1266 case RES_QP_RESERVED:
1267 if (r->com.state == RES_QP_MAPPED && !alloc)
1268 break;
1269
aa1ec3dd 1270 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
c82e9aa0
EC		 1271 err = -EINVAL;
1272 break;
1273
1274 case RES_QP_MAPPED:
1275 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1276 r->com.state == RES_QP_HW)
1277 break;
1278 else {
aa1ec3dd 1279 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
c82e9aa0
EC		 1280 r->com.res_id);
1281 err = -EINVAL;
1282 }
1283
1284 break;
1285
1286 case RES_QP_HW:
1287 if (r->com.state != RES_QP_MAPPED)
1288 err = -EINVAL;
1289 break;
1290 default:
1291 err = -EINVAL;
1292 }
1293
1294 if (!err) {
1295 r->com.from_state = r->com.state;
1296 r->com.to_state = state;
1297 r->com.state = RES_QP_BUSY;
1298 if (qp)
64699336 1299 *qp = r;
c82e9aa0
EC		 1300 }
1301 }
1302
1303 spin_unlock_irq(mlx4_tlock(dev));
1304
1305 return err;
1306}
1307
1308static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1309 enum res_mpt_states state, struct res_mpt **mpt)
1310{
1311 struct mlx4_priv *priv = mlx4_priv(dev);
1312 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1313 struct res_mpt *r;
1314 int err = 0;
1315
1316 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1317 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
c82e9aa0
EC		 1318 if (!r)
1319 err = -ENOENT;
1320 else if (r->com.owner != slave)
1321 err = -EPERM;
1322 else {
1323 switch (state) {
1324 case RES_MPT_BUSY:
1325 err = -EINVAL;
1326 break;
1327
1328 case RES_MPT_RESERVED:
1329 if (r->com.state != RES_MPT_MAPPED)
1330 err = -EINVAL;
1331 break;
1332
1333 case RES_MPT_MAPPED:
1334 if (r->com.state != RES_MPT_RESERVED &&
1335 r->com.state != RES_MPT_HW)
1336 err = -EINVAL;
1337 break;
1338
1339 case RES_MPT_HW:
1340 if (r->com.state != RES_MPT_MAPPED)
1341 err = -EINVAL;
1342 break;
1343 default:
1344 err = -EINVAL;
1345 }
1346
1347 if (!err) {
1348 r->com.from_state = r->com.state;
1349 r->com.to_state = state;
1350 r->com.state = RES_MPT_BUSY;
1351 if (mpt)
64699336 1352 *mpt = r;
c82e9aa0
EC		 1353 }
1354 }
1355
1356 spin_unlock_irq(mlx4_tlock(dev));
1357
1358 return err;
1359}
1360
1361static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1362 enum res_eq_states state, struct res_eq **eq)
1363{
1364 struct mlx4_priv *priv = mlx4_priv(dev);
1365 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1366 struct res_eq *r;
1367 int err = 0;
1368
1369 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1370 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
c82e9aa0
EC		 1371 if (!r)
1372 err = -ENOENT;
1373 else if (r->com.owner != slave)
1374 err = -EPERM;
1375 else {
1376 switch (state) {
1377 case RES_EQ_BUSY:
1378 err = -EINVAL;
1379 break;
1380
1381 case RES_EQ_RESERVED:
1382 if (r->com.state != RES_EQ_HW)
1383 err = -EINVAL;
1384 break;
1385
1386 case RES_EQ_HW:
1387 if (r->com.state != RES_EQ_RESERVED)
1388 err = -EINVAL;
1389 break;
1390
1391 default:
1392 err = -EINVAL;
1393 }
1394
1395 if (!err) {
1396 r->com.from_state = r->com.state;
1397 r->com.to_state = state;
1398 r->com.state = RES_EQ_BUSY;
1399 if (eq)
1400 *eq = r;
1401 }
1402 }
1403
1404 spin_unlock_irq(mlx4_tlock(dev));
1405
1406 return err;
1407}
1408
1409static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1410 enum res_cq_states state, struct res_cq **cq)
1411{
1412 struct mlx4_priv *priv = mlx4_priv(dev);
1413 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1414 struct res_cq *r;
1415 int err;
1416
1417 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1418 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
c9218a9e 1419 if (!r) {
c82e9aa0 1420 err = -ENOENT;
c9218a9e 1421 } else if (r->com.owner != slave) {
c82e9aa0 1422 err = -EPERM;
c9218a9e
PB		 1423 } else if (state == RES_CQ_ALLOCATED) {
1424 if (r->com.state != RES_CQ_HW)
c82e9aa0 1425 err = -EINVAL;
c9218a9e
PB		 1426 else if (atomic_read(&r->ref_count))
1427 err = -EBUSY;
1428 else
1429 err = 0;
1430 } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
1431 err = -EINVAL;
1432 } else {
1433 err = 0;
1434 }
c82e9aa0 1435
c9218a9e
PB		 1436 if (!err) {
1437 r->com.from_state = r->com.state;
1438 r->com.to_state = state;
1439 r->com.state = RES_CQ_BUSY;
1440 if (cq)
1441 *cq = r;
c82e9aa0
EC		 1442 }
1443
1444 spin_unlock_irq(mlx4_tlock(dev));
1445
1446 return err;
1447}
1448
1449static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
f088cbb8 1450 enum res_srq_states state, struct res_srq **srq)
c82e9aa0
EC		 1451{
1452 struct mlx4_priv *priv = mlx4_priv(dev);
1453 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1454 struct res_srq *r;
1455 int err = 0;
1456
1457 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1458 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
f088cbb8 1459 if (!r) {
c82e9aa0 1460 err = -ENOENT;
f088cbb8 1461 } else if (r->com.owner != slave) {
c82e9aa0 1462 err = -EPERM;
f088cbb8
PB		 1463 } else if (state == RES_SRQ_ALLOCATED) {
1464 if (r->com.state != RES_SRQ_HW)
c82e9aa0 1465 err = -EINVAL;
f088cbb8
PB		 1466 else if (atomic_read(&r->ref_count))
1467 err = -EBUSY;
1468 } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
1469 err = -EINVAL;
1470 }
c82e9aa0 1471
f088cbb8
PB		 1472 if (!err) {
1473 r->com.from_state = r->com.state;
1474 r->com.to_state = state;
1475 r->com.state = RES_SRQ_BUSY;
1476 if (srq)
1477 *srq = r;
c82e9aa0
EC		 1478 }
1479
1480 spin_unlock_irq(mlx4_tlock(dev));
1481
1482 return err;
1483}
1484
1485static void res_abort_move(struct mlx4_dev *dev, int slave,
1486 enum mlx4_resource type, int id)
1487{
1488 struct mlx4_priv *priv = mlx4_priv(dev);
1489 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1490 struct res_common *r;
1491
1492 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1493 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1494 if (r && (r->owner == slave))
1495 r->state = r->from_state;
1496 spin_unlock_irq(mlx4_tlock(dev));
1497}
1498
1499static void res_end_move(struct mlx4_dev *dev, int slave,
1500 enum mlx4_resource type, int id)
1501{
1502 struct mlx4_priv *priv = mlx4_priv(dev);
1503 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1504 struct res_common *r;
1505
1506 spin_lock_irq(mlx4_tlock(dev));
4af1c048 1507 r = res_tracker_lookup(&tracker->res_tree[type], id);
c82e9aa0
EC		 1508 if (r && (r->owner == slave))
1509 r->state = r->to_state;
1510 spin_unlock_irq(mlx4_tlock(dev));
1511}
1512
1513static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1514{
e2c76824
JM		 1515 return mlx4_is_qp_reserved(dev, qpn) &&
1516 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
c82e9aa0
EC		 1517}
1518
54679e14
JM		 1519static int fw_reserved(struct mlx4_dev *dev, int qpn)
1520{
1521 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
c82e9aa0
EC		 1522}
1523
1524static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1525 u64 in_param, u64 *out_param)
1526{
1527 int err;
1528 int count;
1529 int align;
1530 int base;
1531 int qpn;
1532
1533 switch (op) {
1534 case RES_OP_RESERVE:
1535 count = get_param_l(&in_param);
1536 align = get_param_h(&in_param);
146f3ef4 1537 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1538 if (err)
1539 return err;
1540
146f3ef4
JM		 1541 err = __mlx4_qp_reserve_range(dev, count, align, &base);
1542 if (err) {
1543 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1544 return err;
1545 }
1546
c82e9aa0
EC		 1547 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1548 if (err) {
146f3ef4 1549 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 1550 __mlx4_qp_release_range(dev, base, count);
1551 return err;
1552 }
1553 set_param_l(out_param, base);
1554 break;
1555 case RES_OP_MAP_ICM:
1556 qpn = get_param_l(&in_param) & 0x7fffff;
1557 if (valid_reserved(dev, slave, qpn)) {
1558 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1559 if (err)
1560 return err;
1561 }
1562
1563 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1564 NULL, 1);
1565 if (err)
1566 return err;
1567
54679e14 1568 if (!fw_reserved(dev, qpn)) {
40f2287b 1569 err = __mlx4_qp_alloc_icm(dev, qpn, GFP_KERNEL);
c82e9aa0
EC		 1570 if (err) {
1571 res_abort_move(dev, slave, RES_QP, qpn);
1572 return err;
1573 }
1574 }
1575
1576 res_end_move(dev, slave, RES_QP, qpn);
1577 break;
1578
1579 default:
1580 err = -EINVAL;
1581 break;
1582 }
1583 return err;
1584}
1585
1586static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1587 u64 in_param, u64 *out_param)
1588{
1589 int err = -EINVAL;
1590 int base;
1591 int order;
1592
1593 if (op != RES_OP_RESERVE_AND_MAP)
1594 return err;
1595
1596 order = get_param_l(&in_param);
146f3ef4
JM		 1597
1598 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1599 if (err)
1600 return err;
1601
c82e9aa0 1602 base = __mlx4_alloc_mtt_range(dev, order);
146f3ef4
JM		 1603 if (base == -1) {
1604 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1605 return -ENOMEM;
146f3ef4 1606 }
c82e9aa0
EC		 1607
1608 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 1609 if (err) {
1610 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 1611 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 1612 } else {
c82e9aa0 1613 set_param_l(out_param, base);
146f3ef4 1614 }
c82e9aa0
EC		 1615
1616 return err;
1617}
1618
1619static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1620 u64 in_param, u64 *out_param)
1621{
1622 int err = -EINVAL;
1623 int index;
1624 int id;
1625 struct res_mpt *mpt;
1626
1627 switch (op) {
1628 case RES_OP_RESERVE:
146f3ef4
JM		 1629 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1630 if (err)
1631 break;
1632
b20e519a 1633 index = __mlx4_mpt_reserve(dev);
146f3ef4
JM		 1634 if (index == -1) {
1635 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
c82e9aa0 1636 break;
146f3ef4 1637 }
c82e9aa0
EC		 1638 id = index & mpt_mask(dev);
1639
1640 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1641 if (err) {
146f3ef4 1642 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 1643 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 1644 break;
1645 }
1646 set_param_l(out_param, index);
1647 break;
1648 case RES_OP_MAP_ICM:
1649 index = get_param_l(&in_param);
1650 id = index & mpt_mask(dev);
1651 err = mr_res_start_move_to(dev, slave, id,
1652 RES_MPT_MAPPED, &mpt);
1653 if (err)
1654 return err;
1655
40f2287b 1656 err = __mlx4_mpt_alloc_icm(dev, mpt->key, GFP_KERNEL);
c82e9aa0
EC		 1657 if (err) {
1658 res_abort_move(dev, slave, RES_MPT, id);
1659 return err;
1660 }
1661
1662 res_end_move(dev, slave, RES_MPT, id);
1663 break;
1664 }
1665 return err;
1666}
1667
1668static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1669 u64 in_param, u64 *out_param)
1670{
1671 int cqn;
1672 int err;
1673
1674 switch (op) {
1675 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1676 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1677 if (err)
1678 break;
1679
146f3ef4
JM		 1680 err = __mlx4_cq_alloc_icm(dev, &cqn);
1681 if (err) {
1682 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1683 break;
1684 }
1685
c82e9aa0
EC		 1686 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1687 if (err) {
146f3ef4 1688 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 1689 __mlx4_cq_free_icm(dev, cqn);
1690 break;
1691 }
1692
1693 set_param_l(out_param, cqn);
1694 break;
1695
1696 default:
1697 err = -EINVAL;
1698 }
1699
1700 return err;
1701}
1702
1703static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1704 u64 in_param, u64 *out_param)
1705{
1706 int srqn;
1707 int err;
1708
1709 switch (op) {
1710 case RES_OP_RESERVE_AND_MAP:
146f3ef4 1711 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1712 if (err)
1713 break;
1714
146f3ef4
JM		 1715 err = __mlx4_srq_alloc_icm(dev, &srqn);
1716 if (err) {
1717 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1718 break;
1719 }
1720
c82e9aa0
EC		 1721 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1722 if (err) {
146f3ef4 1723 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 1724 __mlx4_srq_free_icm(dev, srqn);
1725 break;
1726 }
1727
1728 set_param_l(out_param, srqn);
1729 break;
1730
1731 default:
1732 err = -EINVAL;
1733 }
1734
1735 return err;
1736}
1737
2f5bb473
JM		 1738static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1739 u8 smac_index, u64 *mac)
1740{
1741 struct mlx4_priv *priv = mlx4_priv(dev);
1742 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1743 struct list_head *mac_list =
1744 &tracker->slave_list[slave].res_list[RES_MAC];
1745 struct mac_res *res, *tmp;
1746
1747 list_for_each_entry_safe(res, tmp, mac_list, list) {
1748 if (res->smac_index == smac_index && res->port == (u8) port) {
1749 *mac = res->mac;
1750 return 0;
1751 }
1752 }
1753 return -ENOENT;
1754}
1755
1756static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
c82e9aa0
EC		 1757{
1758 struct mlx4_priv *priv = mlx4_priv(dev);
1759 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2f5bb473
JM		 1760 struct list_head *mac_list =
1761 &tracker->slave_list[slave].res_list[RES_MAC];
1762 struct mac_res *res, *tmp;
1763
1764 list_for_each_entry_safe(res, tmp, mac_list, list) {
1765 if (res->mac == mac && res->port == (u8) port) {
1766 /* mac found. update ref count */
1767 ++res->ref_count;
1768 return 0;
1769 }
1770 }
c82e9aa0 1771
146f3ef4
JM		 1772 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1773 return -EINVAL;
c82e9aa0 1774 res = kzalloc(sizeof *res, GFP_KERNEL);
146f3ef4
JM		 1775 if (!res) {
1776 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
c82e9aa0 1777 return -ENOMEM;
146f3ef4 1778 }
c82e9aa0
EC		 1779 res->mac = mac;
1780 res->port = (u8) port;
2f5bb473
JM		 1781 res->smac_index = smac_index;
1782 res->ref_count = 1;
c82e9aa0
EC		 1783 list_add_tail(&res->list,
1784 &tracker->slave_list[slave].res_list[RES_MAC]);
1785 return 0;
1786}
1787
1788static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1789 int port)
1790{
1791 struct mlx4_priv *priv = mlx4_priv(dev);
1792 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1793 struct list_head *mac_list =
1794 &tracker->slave_list[slave].res_list[RES_MAC];
1795 struct mac_res *res, *tmp;
1796
1797 list_for_each_entry_safe(res, tmp, mac_list, list) {
1798 if (res->mac == mac && res->port == (u8) port) {
2f5bb473
JM		 1799 if (!--res->ref_count) {
1800 list_del(&res->list);
1801 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1802 kfree(res);
1803 }
c82e9aa0
EC		 1804 break;
1805 }
1806 }
1807}
1808
1809static void rem_slave_macs(struct mlx4_dev *dev, int slave)
1810{
1811 struct mlx4_priv *priv = mlx4_priv(dev);
1812 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1813 struct list_head *mac_list =
1814 &tracker->slave_list[slave].res_list[RES_MAC];
1815 struct mac_res *res, *tmp;
2f5bb473 1816 int i;
c82e9aa0
EC		 1817
1818 list_for_each_entry_safe(res, tmp, mac_list, list) {
1819 list_del(&res->list);
2f5bb473
JM		 1820 /* dereference the mac the num times the slave referenced it */
1821 for (i = 0; i < res->ref_count; i++)
1822 __mlx4_unregister_mac(dev, res->port, res->mac);
146f3ef4 1823 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
c82e9aa0
EC		 1824 kfree(res);
1825 }
1826}
1827
1828static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 1829 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 1830{
1831 int err = -EINVAL;
1832 int port;
1833 u64 mac;
2f5bb473 1834 u8 smac_index;
c82e9aa0
EC		 1835
1836 if (op != RES_OP_RESERVE_AND_MAP)
1837 return err;
1838
acddd5dd 1839 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 1840 port = mlx4_slave_convert_port(
1841 dev, slave, port);
1842
1843 if (port < 0)
1844 return -EINVAL;
c82e9aa0
EC		 1845 mac = in_param;
1846
1847 err = __mlx4_register_mac(dev, port, mac);
1848 if (err >= 0) {
2f5bb473 1849 smac_index = err;
c82e9aa0
EC		 1850 set_param_l(out_param, err);
1851 err = 0;
1852 }
1853
1854 if (!err) {
2f5bb473 1855 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
c82e9aa0
EC		 1856 if (err)
1857 __mlx4_unregister_mac(dev, port, mac);
1858 }
1859 return err;
1860}
1861
4874080d
JM		 1862static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1863 int port, int vlan_index)
ffe455ad 1864{
4874080d
JM		 1865 struct mlx4_priv *priv = mlx4_priv(dev);
1866 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1867 struct list_head *vlan_list =
1868 &tracker->slave_list[slave].res_list[RES_VLAN];
1869 struct vlan_res *res, *tmp;
1870
1871 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1872 if (res->vlan == vlan && res->port == (u8) port) {
1873 /* vlan found. update ref count */
1874 ++res->ref_count;
1875 return 0;
1876 }
1877 }
1878
146f3ef4
JM		 1879 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
1880 return -EINVAL;
4874080d 1881 res = kzalloc(sizeof(*res), GFP_KERNEL);
146f3ef4
JM		 1882 if (!res) {
1883 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
4874080d 1884 return -ENOMEM;
146f3ef4 1885 }
4874080d
JM		 1886 res->vlan = vlan;
1887 res->port = (u8) port;
1888 res->vlan_index = vlan_index;
1889 res->ref_count = 1;
1890 list_add_tail(&res->list,
1891 &tracker->slave_list[slave].res_list[RES_VLAN]);
ffe455ad
EE		 1892 return 0;
1893}
1894
4874080d
JM		 1895
1896static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1897 int port)
1898{
1899 struct mlx4_priv *priv = mlx4_priv(dev);
1900 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1901 struct list_head *vlan_list =
1902 &tracker->slave_list[slave].res_list[RES_VLAN];
1903 struct vlan_res *res, *tmp;
1904
1905 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1906 if (res->vlan == vlan && res->port == (u8) port) {
1907 if (!--res->ref_count) {
1908 list_del(&res->list);
146f3ef4
JM		 1909 mlx4_release_resource(dev, slave, RES_VLAN,
1910 1, port);
4874080d
JM		 1911 kfree(res);
1912 }
1913 break;
1914 }
1915 }
1916}
1917
1918static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
1919{
1920 struct mlx4_priv *priv = mlx4_priv(dev);
1921 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1922 struct list_head *vlan_list =
1923 &tracker->slave_list[slave].res_list[RES_VLAN];
1924 struct vlan_res *res, *tmp;
1925 int i;
1926
1927 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1928 list_del(&res->list);
1929 /* dereference the vlan the num times the slave referenced it */
1930 for (i = 0; i < res->ref_count; i++)
1931 __mlx4_unregister_vlan(dev, res->port, res->vlan);
146f3ef4 1932 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
4874080d
JM		 1933 kfree(res);
1934 }
1935}
1936
1937static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2c957ff2 1938 u64 in_param, u64 *out_param, int in_port)
4874080d 1939{
2c957ff2
JM		 1940 struct mlx4_priv *priv = mlx4_priv(dev);
1941 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 1942 int err;
1943 u16 vlan;
1944 int vlan_index;
2c957ff2
JM		 1945 int port;
1946
1947 port = !in_port ? get_param_l(out_param) : in_port;
4874080d
JM		 1948
1949 if (!port || op != RES_OP_RESERVE_AND_MAP)
1950 return -EINVAL;
1951
449fc488
MB		 1952 port = mlx4_slave_convert_port(
1953 dev, slave, port);
1954
1955 if (port < 0)
1956 return -EINVAL;
2c957ff2
JM		 1957 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
1958 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
1959 slave_state[slave].old_vlan_api = true;
1960 return 0;
1961 }
1962
4874080d
JM		 1963 vlan = (u16) in_param;
1964
1965 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
1966 if (!err) {
1967 set_param_l(out_param, (u32) vlan_index);
1968 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
1969 if (err)
1970 __mlx4_unregister_vlan(dev, port, vlan);
1971 }
1972 return err;
1973}
1974
ba062d52
JM		 1975static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1976 u64 in_param, u64 *out_param)
1977{
1978 u32 index;
1979 int err;
1980
1981 if (op != RES_OP_RESERVE)
1982 return -EINVAL;
1983
146f3ef4 1984 err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 1985 if (err)
1986 return err;
1987
146f3ef4
JM		 1988 err = __mlx4_counter_alloc(dev, &index);
1989 if (err) {
1990 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
1991 return err;
1992 }
1993
ba062d52 1994 err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
146f3ef4 1995 if (err) {
ba062d52 1996 __mlx4_counter_free(dev, index);
146f3ef4
JM		 1997 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
1998 } else {
ba062d52 1999 set_param_l(out_param, index);
146f3ef4 2000 }
ba062d52
JM		 2001
2002 return err;
2003}
2004
2005static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2006 u64 in_param, u64 *out_param)
2007{
2008 u32 xrcdn;
2009 int err;
2010
2011 if (op != RES_OP_RESERVE)
2012 return -EINVAL;
2013
2014 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2015 if (err)
2016 return err;
2017
2018 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2019 if (err)
2020 __mlx4_xrcd_free(dev, xrcdn);
2021 else
2022 set_param_l(out_param, xrcdn);
2023
2024 return err;
2025}
2026
c82e9aa0
EC		 2027int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2028 struct mlx4_vhcr *vhcr,
2029 struct mlx4_cmd_mailbox *inbox,
2030 struct mlx4_cmd_mailbox *outbox,
2031 struct mlx4_cmd_info *cmd)
2032{
2033 int err;
2034 int alop = vhcr->op_modifier;
2035
acddd5dd 2036 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2037 case RES_QP:
2038 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2039 vhcr->in_param, &vhcr->out_param);
2040 break;
2041
2042 case RES_MTT:
2043 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2044 vhcr->in_param, &vhcr->out_param);
2045 break;
2046
2047 case RES_MPT:
2048 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2049 vhcr->in_param, &vhcr->out_param);
2050 break;
2051
2052 case RES_CQ:
2053 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2054 vhcr->in_param, &vhcr->out_param);
2055 break;
2056
2057 case RES_SRQ:
2058 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2059 vhcr->in_param, &vhcr->out_param);
2060 break;
2061
2062 case RES_MAC:
2063 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2064 vhcr->in_param, &vhcr->out_param,
2065 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2066 break;
2067
ffe455ad
EE		 2068 case RES_VLAN:
2069 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2070 vhcr->in_param, &vhcr->out_param,
2071 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2072 break;
2073
ba062d52
JM		 2074 case RES_COUNTER:
2075 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2076 vhcr->in_param, &vhcr->out_param);
2077 break;
2078
2079 case RES_XRCD:
2080 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2081 vhcr->in_param, &vhcr->out_param);
2082 break;
2083
c82e9aa0
EC		 2084 default:
2085 err = -EINVAL;
2086 break;
2087 }
2088
2089 return err;
2090}
2091
2092static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2093 u64 in_param)
2094{
2095 int err;
2096 int count;
2097 int base;
2098 int qpn;
2099
2100 switch (op) {
2101 case RES_OP_RESERVE:
2102 base = get_param_l(&in_param) & 0x7fffff;
2103 count = get_param_h(&in_param);
2104 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2105 if (err)
2106 break;
146f3ef4 2107 mlx4_release_resource(dev, slave, RES_QP, count, 0);
c82e9aa0
EC		 2108 __mlx4_qp_release_range(dev, base, count);
2109 break;
2110 case RES_OP_MAP_ICM:
2111 qpn = get_param_l(&in_param) & 0x7fffff;
2112 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2113 NULL, 0);
2114 if (err)
2115 return err;
2116
54679e14 2117 if (!fw_reserved(dev, qpn))
c82e9aa0
EC		 2118 __mlx4_qp_free_icm(dev, qpn);
2119
2120 res_end_move(dev, slave, RES_QP, qpn);
2121
2122 if (valid_reserved(dev, slave, qpn))
2123 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2124 break;
2125 default:
2126 err = -EINVAL;
2127 break;
2128 }
2129 return err;
2130}
2131
2132static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2133 u64 in_param, u64 *out_param)
2134{
2135 int err = -EINVAL;
2136 int base;
2137 int order;
2138
2139 if (op != RES_OP_RESERVE_AND_MAP)
2140 return err;
2141
2142 base = get_param_l(&in_param);
2143 order = get_param_h(&in_param);
2144 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
146f3ef4
JM		 2145 if (!err) {
2146 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
c82e9aa0 2147 __mlx4_free_mtt_range(dev, base, order);
146f3ef4 2148 }
c82e9aa0
EC		 2149 return err;
2150}
2151
2152static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2153 u64 in_param)
2154{
2155 int err = -EINVAL;
2156 int index;
2157 int id;
2158 struct res_mpt *mpt;
2159
2160 switch (op) {
2161 case RES_OP_RESERVE:
2162 index = get_param_l(&in_param);
2163 id = index & mpt_mask(dev);
2164 err = get_res(dev, slave, id, RES_MPT, &mpt);
2165 if (err)
2166 break;
2167 index = mpt->key;
2168 put_res(dev, slave, id, RES_MPT);
2169
2170 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2171 if (err)
2172 break;
146f3ef4 2173 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
b20e519a 2174 __mlx4_mpt_release(dev, index);
c82e9aa0
EC		 2175 break;
2176 case RES_OP_MAP_ICM:
2177 index = get_param_l(&in_param);
2178 id = index & mpt_mask(dev);
2179 err = mr_res_start_move_to(dev, slave, id,
2180 RES_MPT_RESERVED, &mpt);
2181 if (err)
2182 return err;
2183
b20e519a 2184 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 2185 res_end_move(dev, slave, RES_MPT, id);
2186 return err;
2187 break;
2188 default:
2189 err = -EINVAL;
2190 break;
2191 }
2192 return err;
2193}
2194
2195static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2196 u64 in_param, u64 *out_param)
2197{
2198 int cqn;
2199 int err;
2200
2201 switch (op) {
2202 case RES_OP_RESERVE_AND_MAP:
2203 cqn = get_param_l(&in_param);
2204 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2205 if (err)
2206 break;
2207
146f3ef4 2208 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
c82e9aa0
EC		 2209 __mlx4_cq_free_icm(dev, cqn);
2210 break;
2211
2212 default:
2213 err = -EINVAL;
2214 break;
2215 }
2216
2217 return err;
2218}
2219
2220static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2221 u64 in_param, u64 *out_param)
2222{
2223 int srqn;
2224 int err;
2225
2226 switch (op) {
2227 case RES_OP_RESERVE_AND_MAP:
2228 srqn = get_param_l(&in_param);
2229 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2230 if (err)
2231 break;
2232
146f3ef4 2233 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
c82e9aa0
EC		 2234 __mlx4_srq_free_icm(dev, srqn);
2235 break;
2236
2237 default:
2238 err = -EINVAL;
2239 break;
2240 }
2241
2242 return err;
2243}
2244
2245static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2246 u64 in_param, u64 *out_param, int in_port)
c82e9aa0
EC		 2247{
2248 int port;
2249 int err = 0;
2250
2251 switch (op) {
2252 case RES_OP_RESERVE_AND_MAP:
acddd5dd 2253 port = !in_port ? get_param_l(out_param) : in_port;
449fc488
MB		 2254 port = mlx4_slave_convert_port(
2255 dev, slave, port);
2256
2257 if (port < 0)
2258 return -EINVAL;
c82e9aa0
EC		 2259 mac_del_from_slave(dev, slave, in_param, port);
2260 __mlx4_unregister_mac(dev, port, in_param);
2261 break;
2262 default:
2263 err = -EINVAL;
2264 break;
2265 }
2266
2267 return err;
2268
2269}
2270
ffe455ad 2271static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
acddd5dd 2272 u64 in_param, u64 *out_param, int port)
ffe455ad 2273{
2c957ff2
JM		 2274 struct mlx4_priv *priv = mlx4_priv(dev);
2275 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
4874080d
JM		 2276 int err = 0;
2277
449fc488
MB		 2278 port = mlx4_slave_convert_port(
2279 dev, slave, port);
2280
2281 if (port < 0)
2282 return -EINVAL;
4874080d
JM		 2283 switch (op) {
2284 case RES_OP_RESERVE_AND_MAP:
2c957ff2
JM		 2285 if (slave_state[slave].old_vlan_api)
2286 return 0;
4874080d
JM		 2287 if (!port)
2288 return -EINVAL;
2289 vlan_del_from_slave(dev, slave, in_param, port);
2290 __mlx4_unregister_vlan(dev, port, in_param);
2291 break;
2292 default:
2293 err = -EINVAL;
2294 break;
2295 }
2296
2297 return err;
ffe455ad
EE		 2298}
2299
ba062d52
JM		 2300static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2301 u64 in_param, u64 *out_param)
2302{
2303 int index;
2304 int err;
2305
2306 if (op != RES_OP_RESERVE)
2307 return -EINVAL;
2308
2309 index = get_param_l(&in_param);
2310 err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
2311 if (err)
2312 return err;
2313
2314 __mlx4_counter_free(dev, index);
146f3ef4 2315 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 2316
2317 return err;
2318}
2319
2320static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2321 u64 in_param, u64 *out_param)
2322{
2323 int xrcdn;
2324 int err;
2325
2326 if (op != RES_OP_RESERVE)
2327 return -EINVAL;
2328
2329 xrcdn = get_param_l(&in_param);
2330 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2331 if (err)
2332 return err;
2333
2334 __mlx4_xrcd_free(dev, xrcdn);
2335
2336 return err;
2337}
2338
c82e9aa0
EC		 2339int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2340 struct mlx4_vhcr *vhcr,
2341 struct mlx4_cmd_mailbox *inbox,
2342 struct mlx4_cmd_mailbox *outbox,
2343 struct mlx4_cmd_info *cmd)
2344{
2345 int err = -EINVAL;
2346 int alop = vhcr->op_modifier;
2347
acddd5dd 2348 switch (vhcr->in_modifier & 0xFF) {
c82e9aa0
EC		 2349 case RES_QP:
2350 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2351 vhcr->in_param);
2352 break;
2353
2354 case RES_MTT:
2355 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2356 vhcr->in_param, &vhcr->out_param);
2357 break;
2358
2359 case RES_MPT:
2360 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2361 vhcr->in_param);
2362 break;
2363
2364 case RES_CQ:
2365 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2366 vhcr->in_param, &vhcr->out_param);
2367 break;
2368
2369 case RES_SRQ:
2370 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2371 vhcr->in_param, &vhcr->out_param);
2372 break;
2373
2374 case RES_MAC:
2375 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2376 vhcr->in_param, &vhcr->out_param,
2377 (vhcr->in_modifier >> 8) & 0xFF);
c82e9aa0
EC		 2378 break;
2379
ffe455ad
EE		 2380 case RES_VLAN:
2381 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
acddd5dd
JM		 2382 vhcr->in_param, &vhcr->out_param,
2383 (vhcr->in_modifier >> 8) & 0xFF);
ffe455ad
EE		 2384 break;
2385
ba062d52
JM		 2386 case RES_COUNTER:
2387 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2388 vhcr->in_param, &vhcr->out_param);
2389 break;
2390
2391 case RES_XRCD:
2392 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2393 vhcr->in_param, &vhcr->out_param);
2394
c82e9aa0
EC		 2395 default:
2396 break;
2397 }
2398 return err;
2399}
2400
2401/* ugly but other choices are uglier */
2402static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2403{
2404 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2405}
2406
2b8fb286 2407static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
c82e9aa0 2408{
2b8fb286 2409 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
c82e9aa0
EC		 2410}
2411
2412static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2413{
2414 return be32_to_cpu(mpt->mtt_sz);
2415}
2416
cc1ade94
SM		 2417static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2418{
2419 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2420}
2421
2422static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2423{
2424 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2425}
2426
2427static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2428{
2429 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2430}
2431
2432static int mr_is_region(struct mlx4_mpt_entry *mpt)
2433{
2434 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2435}
2436
2b8fb286 2437static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
c82e9aa0
EC		 2438{
2439 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2440}
2441
2b8fb286 2442static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
c82e9aa0
EC		 2443{
2444 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2445}
2446
2447static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2448{
2449 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2450 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2451 int log_sq_sride = qpc->sq_size_stride & 7;
2452 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2453 int log_rq_stride = qpc->rq_size_stride & 7;
2454 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2455 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
5c5f3f0a
YH		 2456 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2457 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
c82e9aa0
EC		 2458 int sq_size;
2459 int rq_size;
2460 int total_pages;
2461 int total_mem;
2462 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2463
2464 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2465 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2466 total_mem = sq_size + rq_size;
2467 total_pages =
2468 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2469 page_shift);
2470
2471 return total_pages;
2472}
2473
c82e9aa0
EC		 2474static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2475 int size, struct res_mtt *mtt)
2476{
2b8fb286
MA		 2477 int res_start = mtt->com.res_id;
2478 int res_size = (1 << mtt->order);
c82e9aa0
EC		 2479
2480 if (start < res_start || start + size > res_start + res_size)
2481 return -EPERM;
2482 return 0;
2483}
2484
2485int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2486 struct mlx4_vhcr *vhcr,
2487 struct mlx4_cmd_mailbox *inbox,
2488 struct mlx4_cmd_mailbox *outbox,
2489 struct mlx4_cmd_info *cmd)
2490{
2491 int err;
2492 int index = vhcr->in_modifier;
2493 struct res_mtt *mtt;
2494 struct res_mpt *mpt;
2b8fb286 2495 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2496 int phys;
2497 int id;
cc1ade94
SM		 2498 u32 pd;
2499 int pd_slave;
c82e9aa0
EC		 2500
2501 id = index & mpt_mask(dev);
2502 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2503 if (err)
2504 return err;
2505
cc1ade94
SM		 2506 /* Disable memory windows for VFs. */
2507 if (!mr_is_region(inbox->buf)) {
2508 err = -EPERM;
2509 goto ex_abort;
2510 }
2511
2512 /* Make sure that the PD bits related to the slave id are zeros. */
2513 pd = mr_get_pd(inbox->buf);
2514 pd_slave = (pd >> 17) & 0x7f;
2515 if (pd_slave != 0 && pd_slave != slave) {
2516 err = -EPERM;
2517 goto ex_abort;
2518 }
2519
2520 if (mr_is_fmr(inbox->buf)) {
2521 /* FMR and Bind Enable are forbidden in slave devices. */
2522 if (mr_is_bind_enabled(inbox->buf)) {
2523 err = -EPERM;
2524 goto ex_abort;
2525 }
2526 /* FMR and Memory Windows are also forbidden. */
2527 if (!mr_is_region(inbox->buf)) {
2528 err = -EPERM;
2529 goto ex_abort;
2530 }
2531 }
2532
c82e9aa0
EC		 2533 phys = mr_phys_mpt(inbox->buf);
2534 if (!phys) {
2b8fb286 2535 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2536 if (err)
2537 goto ex_abort;
2538
2539 err = check_mtt_range(dev, slave, mtt_base,
2540 mr_get_mtt_size(inbox->buf), mtt);
2541 if (err)
2542 goto ex_put;
2543
2544 mpt->mtt = mtt;
2545 }
2546
c82e9aa0
EC		 2547 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2548 if (err)
2549 goto ex_put;
2550
2551 if (!phys) {
2552 atomic_inc(&mtt->ref_count);
2553 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2554 }
2555
2556 res_end_move(dev, slave, RES_MPT, id);
2557 return 0;
2558
2559ex_put:
2560 if (!phys)
2561 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2562ex_abort:
2563 res_abort_move(dev, slave, RES_MPT, id);
2564
2565 return err;
2566}
2567
2568int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2569 struct mlx4_vhcr *vhcr,
2570 struct mlx4_cmd_mailbox *inbox,
2571 struct mlx4_cmd_mailbox *outbox,
2572 struct mlx4_cmd_info *cmd)
2573{
2574 int err;
2575 int index = vhcr->in_modifier;
2576 struct res_mpt *mpt;
2577 int id;
2578
2579 id = index & mpt_mask(dev);
2580 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2581 if (err)
2582 return err;
2583
2584 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2585 if (err)
2586 goto ex_abort;
2587
2588 if (mpt->mtt)
2589 atomic_dec(&mpt->mtt->ref_count);
2590
2591 res_end_move(dev, slave, RES_MPT, id);
2592 return 0;
2593
2594ex_abort:
2595 res_abort_move(dev, slave, RES_MPT, id);
2596
2597 return err;
2598}
2599
2600int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2601 struct mlx4_vhcr *vhcr,
2602 struct mlx4_cmd_mailbox *inbox,
2603 struct mlx4_cmd_mailbox *outbox,
2604 struct mlx4_cmd_info *cmd)
2605{
2606 int err;
2607 int index = vhcr->in_modifier;
2608 struct res_mpt *mpt;
2609 int id;
2610
2611 id = index & mpt_mask(dev);
2612 err = get_res(dev, slave, id, RES_MPT, &mpt);
2613 if (err)
2614 return err;
2615
e630664c
MB		 2616 if (mpt->com.from_state == RES_MPT_MAPPED) {
2617 /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
2618 * that, the VF must read the MPT. But since the MPT entry memory is not
2619 * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
2620 * entry contents. To guarantee that the MPT cannot be changed, the driver
2621 * must perform HW2SW_MPT before this query and return the MPT entry to HW
2622 * ownership fofollowing the change. The change here allows the VF to
2623 * perform QUERY_MPT also when the entry is in SW ownership.
2624 */
2625 struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
2626 &mlx4_priv(dev)->mr_table.dmpt_table,
2627 mpt->key, NULL);
2628
2629 if (NULL == mpt_entry || NULL == outbox->buf) {
2630 err = -EINVAL;
2631 goto out;
2632 }
2633
2634 memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
2635
2636 err = 0;
2637 } else if (mpt->com.from_state == RES_MPT_HW) {
2638 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2639 } else {
c82e9aa0
EC		 2640 err = -EBUSY;
2641 goto out;
2642 }
2643
c82e9aa0
EC		 2644
2645out:
2646 put_res(dev, slave, id, RES_MPT);
2647 return err;
2648}
2649
2650static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2651{
2652 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2653}
2654
2655static int qp_get_scqn(struct mlx4_qp_context *qpc)
2656{
2657 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2658}
2659
2660static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2661{
2662 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2663}
2664
54679e14
JM		 2665static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2666 struct mlx4_qp_context *context)
2667{
2668 u32 qpn = vhcr->in_modifier & 0xffffff;
2669 u32 qkey = 0;
2670
2671 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2672 return;
2673
2674 /* adjust qkey in qp context */
2675 context->qkey = cpu_to_be32(qkey);
2676}
2677
c82e9aa0
EC		 2678int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2679 struct mlx4_vhcr *vhcr,
2680 struct mlx4_cmd_mailbox *inbox,
2681 struct mlx4_cmd_mailbox *outbox,
2682 struct mlx4_cmd_info *cmd)
2683{
2684 int err;
2685 int qpn = vhcr->in_modifier & 0x7fffff;
2686 struct res_mtt *mtt;
2687 struct res_qp *qp;
2688 struct mlx4_qp_context *qpc = inbox->buf + 8;
2b8fb286 2689 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2690 int mtt_size = qp_get_mtt_size(qpc);
2691 struct res_cq *rcq;
2692 struct res_cq *scq;
2693 int rcqn = qp_get_rcqn(qpc);
2694 int scqn = qp_get_scqn(qpc);
2695 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2696 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2697 struct res_srq *srq;
2698 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2699
2700 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2701 if (err)
2702 return err;
2703 qp->local_qpn = local_qpn;
b01978ca 2704 qp->sched_queue = 0;
f0f829bf
RE		 2705 qp->param3 = 0;
2706 qp->vlan_control = 0;
2707 qp->fvl_rx = 0;
2708 qp->pri_path_fl = 0;
2709 qp->vlan_index = 0;
2710 qp->feup = 0;
b01978ca 2711 qp->qpc_flags = be32_to_cpu(qpc->flags);
c82e9aa0 2712
2b8fb286 2713 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2714 if (err)
2715 goto ex_abort;
2716
2717 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2718 if (err)
2719 goto ex_put_mtt;
2720
c82e9aa0
EC		 2721 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2722 if (err)
2723 goto ex_put_mtt;
2724
2725 if (scqn != rcqn) {
2726 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2727 if (err)
2728 goto ex_put_rcq;
2729 } else
2730 scq = rcq;
2731
2732 if (use_srq) {
2733 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2734 if (err)
2735 goto ex_put_scq;
2736 }
2737
54679e14
JM		 2738 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2739 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 2740 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2741 if (err)
2742 goto ex_put_srq;
2743 atomic_inc(&mtt->ref_count);
2744 qp->mtt = mtt;
2745 atomic_inc(&rcq->ref_count);
2746 qp->rcq = rcq;
2747 atomic_inc(&scq->ref_count);
2748 qp->scq = scq;
2749
2750 if (scqn != rcqn)
2751 put_res(dev, slave, scqn, RES_CQ);
2752
2753 if (use_srq) {
2754 atomic_inc(&srq->ref_count);
2755 put_res(dev, slave, srqn, RES_SRQ);
2756 qp->srq = srq;
2757 }
2758 put_res(dev, slave, rcqn, RES_CQ);
2b8fb286 2759 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2760 res_end_move(dev, slave, RES_QP, qpn);
2761
2762 return 0;
2763
2764ex_put_srq:
2765 if (use_srq)
2766 put_res(dev, slave, srqn, RES_SRQ);
2767ex_put_scq:
2768 if (scqn != rcqn)
2769 put_res(dev, slave, scqn, RES_CQ);
2770ex_put_rcq:
2771 put_res(dev, slave, rcqn, RES_CQ);
2772ex_put_mtt:
2b8fb286 2773 put_res(dev, slave, mtt_base, RES_MTT);
c82e9aa0
EC		 2774ex_abort:
2775 res_abort_move(dev, slave, RES_QP, qpn);
2776
2777 return err;
2778}
2779
2b8fb286 2780static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
c82e9aa0
EC		 2781{
2782 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2783}
2784
2785static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2786{
2787 int log_eq_size = eqc->log_eq_size & 0x1f;
2788 int page_shift = (eqc->log_page_size & 0x3f) + 12;
2789
2790 if (log_eq_size + 5 < page_shift)
2791 return 1;
2792
2793 return 1 << (log_eq_size + 5 - page_shift);
2794}
2795
2b8fb286 2796static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
c82e9aa0
EC		 2797{
2798 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
2799}
2800
2801static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
2802{
2803 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
2804 int page_shift = (cqc->log_page_size & 0x3f) + 12;
2805
2806 if (log_cq_size + 5 < page_shift)
2807 return 1;
2808
2809 return 1 << (log_cq_size + 5 - page_shift);
2810}
2811
2812int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2813 struct mlx4_vhcr *vhcr,
2814 struct mlx4_cmd_mailbox *inbox,
2815 struct mlx4_cmd_mailbox *outbox,
2816 struct mlx4_cmd_info *cmd)
2817{
2818 int err;
2819 int eqn = vhcr->in_modifier;
2820 int res_id = (slave << 8) | eqn;
2821 struct mlx4_eq_context *eqc = inbox->buf;
2b8fb286 2822 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 2823 int mtt_size = eq_get_mtt_size(eqc);
2824 struct res_eq *eq;
2825 struct res_mtt *mtt;
2826
2827 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2828 if (err)
2829 return err;
2830 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
2831 if (err)
2832 goto out_add;
2833
2b8fb286 2834 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 2835 if (err)
2836 goto out_move;
2837
2838 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2839 if (err)
2840 goto out_put;
2841
2842 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2843 if (err)
2844 goto out_put;
2845
2846 atomic_inc(&mtt->ref_count);
2847 eq->mtt = mtt;
2848 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2849 res_end_move(dev, slave, RES_EQ, res_id);
2850 return 0;
2851
2852out_put:
2853 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2854out_move:
2855 res_abort_move(dev, slave, RES_EQ, res_id);
2856out_add:
2857 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2858 return err;
2859}
2860
2861static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
2862 int len, struct res_mtt **res)
2863{
2864 struct mlx4_priv *priv = mlx4_priv(dev);
2865 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2866 struct res_mtt *mtt;
2867 int err = -EINVAL;
2868
2869 spin_lock_irq(mlx4_tlock(dev));
2870 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
2871 com.list) {
2872 if (!check_mtt_range(dev, slave, start, len, mtt)) {
2873 *res = mtt;
2874 mtt->com.from_state = mtt->com.state;
2875 mtt->com.state = RES_MTT_BUSY;
2876 err = 0;
2877 break;
2878 }
2879 }
2880 spin_unlock_irq(mlx4_tlock(dev));
2881
2882 return err;
2883}
2884
54679e14 2885static int verify_qp_parameters(struct mlx4_dev *dev,
99ec41d0 2886 struct mlx4_vhcr *vhcr,
54679e14
JM		 2887 struct mlx4_cmd_mailbox *inbox,
2888 enum qp_transition transition, u8 slave)
2889{
2890 u32 qp_type;
99ec41d0 2891 u32 qpn;
54679e14
JM		 2892 struct mlx4_qp_context *qp_ctx;
2893 enum mlx4_qp_optpar optpar;
b6ffaeff
JM		 2894 int port;
2895 int num_gids;
54679e14
JM		 2896
2897 qp_ctx = inbox->buf + 8;
2898 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
2899 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
2900
2901 switch (qp_type) {
2902 case MLX4_QP_ST_RC:
b6ffaeff 2903 case MLX4_QP_ST_XRC:
54679e14
JM		 2904 case MLX4_QP_ST_UC:
2905 switch (transition) {
2906 case QP_TRANS_INIT2RTR:
2907 case QP_TRANS_RTR2RTS:
2908 case QP_TRANS_RTS2RTS:
2909 case QP_TRANS_SQD2SQD:
2910 case QP_TRANS_SQD2RTS:
2911 if (slave != mlx4_master_func_num(dev))
b6ffaeff
JM		 2912 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
2913 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
2914 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 2915 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 2916 else
2917 num_gids = 1;
2918 if (qp_ctx->pri_path.mgid_index >= num_gids)
54679e14 2919 return -EINVAL;
b6ffaeff
JM		 2920 }
2921 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
2922 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
2923 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
449fc488 2924 num_gids = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 2925 else
2926 num_gids = 1;
2927 if (qp_ctx->alt_path.mgid_index >= num_gids)
54679e14 2928 return -EINVAL;
b6ffaeff 2929 }
54679e14
JM		 2930 break;
2931 default:
2932 break;
2933 }
165cb465 2934 break;
54679e14 2935
165cb465
RD		 2936 case MLX4_QP_ST_MLX:
2937 qpn = vhcr->in_modifier & 0x7fffff;
2938 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
2939 if (transition == QP_TRANS_INIT2RTR &&
2940 slave != mlx4_master_func_num(dev) &&
2941 mlx4_is_qp_reserved(dev, qpn) &&
2942 !mlx4_vf_smi_enabled(dev, slave, port)) {
2943 /* only enabled VFs may create MLX proxy QPs */
2944 mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
2945 __func__, slave, port);
2946 return -EPERM;
2947 }
54679e14 2948 break;
165cb465 2949
54679e14
JM		 2950 default:
2951 break;
2952 }
2953
2954 return 0;
2955}
2956
c82e9aa0
EC		 2957int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
2958 struct mlx4_vhcr *vhcr,
2959 struct mlx4_cmd_mailbox *inbox,
2960 struct mlx4_cmd_mailbox *outbox,
2961 struct mlx4_cmd_info *cmd)
2962{
2963 struct mlx4_mtt mtt;
2964 __be64 *page_list = inbox->buf;
2965 u64 *pg_list = (u64 *)page_list;
2966 int i;
2967 struct res_mtt *rmtt = NULL;
2968 int start = be64_to_cpu(page_list[0]);
2969 int npages = vhcr->in_modifier;
2970 int err;
2971
2972 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
2973 if (err)
2974 return err;
2975
2976 /* Call the SW implementation of write_mtt:
2977 * - Prepare a dummy mtt struct
2978 * - Translate inbox contents to simple addresses in host endianess */
2b8fb286
MA		 2979 mtt.offset = 0; /* TBD this is broken but I don't handle it since
2980 we don't really use it */
c82e9aa0
EC		 2981 mtt.order = 0;
2982 mtt.page_shift = 0;
2983 for (i = 0; i < npages; ++i)
2984 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
2985
2986 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
2987 ((u64 *)page_list + 2));
2988
2989 if (rmtt)
2990 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
2991
2992 return err;
2993}
2994
2995int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2996 struct mlx4_vhcr *vhcr,
2997 struct mlx4_cmd_mailbox *inbox,
2998 struct mlx4_cmd_mailbox *outbox,
2999 struct mlx4_cmd_info *cmd)
3000{
3001 int eqn = vhcr->in_modifier;
3002 int res_id = eqn | (slave << 8);
3003 struct res_eq *eq;
3004 int err;
3005
3006 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
3007 if (err)
3008 return err;
3009
3010 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
3011 if (err)
3012 goto ex_abort;
3013
3014 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3015 if (err)
3016 goto ex_put;
3017
3018 atomic_dec(&eq->mtt->ref_count);
3019 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3020 res_end_move(dev, slave, RES_EQ, res_id);
3021 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
3022
3023 return 0;
3024
3025ex_put:
3026 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
3027ex_abort:
3028 res_abort_move(dev, slave, RES_EQ, res_id);
3029
3030 return err;
3031}
3032
3033int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
3034{
3035 struct mlx4_priv *priv = mlx4_priv(dev);
3036 struct mlx4_slave_event_eq_info *event_eq;
3037 struct mlx4_cmd_mailbox *mailbox;
3038 u32 in_modifier = 0;
3039 int err;
3040 int res_id;
3041 struct res_eq *req;
3042
3043 if (!priv->mfunc.master.slave_state)
3044 return -EINVAL;
3045
803143fb 3046 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
c82e9aa0
EC		 3047
3048 /* Create the event only if the slave is registered */
803143fb 3049 if (event_eq->eqn < 0)
c82e9aa0
EC		 3050 return 0;
3051
3052 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3053 res_id = (slave << 8) | event_eq->eqn;
3054 err = get_res(dev, slave, res_id, RES_EQ, &req);
3055 if (err)
3056 goto unlock;
3057
3058 if (req->com.from_state != RES_EQ_HW) {
3059 err = -EINVAL;
3060 goto put;
3061 }
3062
3063 mailbox = mlx4_alloc_cmd_mailbox(dev);
3064 if (IS_ERR(mailbox)) {
3065 err = PTR_ERR(mailbox);
3066 goto put;
3067 }
3068
3069 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3070 ++event_eq->token;
3071 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3072 }
3073
3074 memcpy(mailbox->buf, (u8 *) eqe, 28);
3075
3076 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
3077
3078 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3079 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3080 MLX4_CMD_NATIVE);
3081
3082 put_res(dev, slave, res_id, RES_EQ);
3083 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3084 mlx4_free_cmd_mailbox(dev, mailbox);
3085 return err;
3086
3087put:
3088 put_res(dev, slave, res_id, RES_EQ);
3089
3090unlock:
3091 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3092 return err;
3093}
3094
3095int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3096 struct mlx4_vhcr *vhcr,
3097 struct mlx4_cmd_mailbox *inbox,
3098 struct mlx4_cmd_mailbox *outbox,
3099 struct mlx4_cmd_info *cmd)
3100{
3101 int eqn = vhcr->in_modifier;
3102 int res_id = eqn | (slave << 8);
3103 struct res_eq *eq;
3104 int err;
3105
3106 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3107 if (err)
3108 return err;
3109
3110 if (eq->com.from_state != RES_EQ_HW) {
3111 err = -EINVAL;
3112 goto ex_put;
3113 }
3114
3115 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3116
3117ex_put:
3118 put_res(dev, slave, res_id, RES_EQ);
3119 return err;
3120}
3121
3122int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3123 struct mlx4_vhcr *vhcr,
3124 struct mlx4_cmd_mailbox *inbox,
3125 struct mlx4_cmd_mailbox *outbox,
3126 struct mlx4_cmd_info *cmd)
3127{
3128 int err;
3129 int cqn = vhcr->in_modifier;
3130 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3131 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3132 struct res_cq *cq;
3133 struct res_mtt *mtt;
3134
3135 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3136 if (err)
3137 return err;
2b8fb286 3138 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3139 if (err)
3140 goto out_move;
3141 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3142 if (err)
3143 goto out_put;
3144 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3145 if (err)
3146 goto out_put;
3147 atomic_inc(&mtt->ref_count);
3148 cq->mtt = mtt;
3149 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3150 res_end_move(dev, slave, RES_CQ, cqn);
3151 return 0;
3152
3153out_put:
3154 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3155out_move:
3156 res_abort_move(dev, slave, RES_CQ, cqn);
3157 return err;
3158}
3159
3160int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3161 struct mlx4_vhcr *vhcr,
3162 struct mlx4_cmd_mailbox *inbox,
3163 struct mlx4_cmd_mailbox *outbox,
3164 struct mlx4_cmd_info *cmd)
3165{
3166 int err;
3167 int cqn = vhcr->in_modifier;
3168 struct res_cq *cq;
3169
3170 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3171 if (err)
3172 return err;
3173 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3174 if (err)
3175 goto out_move;
3176 atomic_dec(&cq->mtt->ref_count);
3177 res_end_move(dev, slave, RES_CQ, cqn);
3178 return 0;
3179
3180out_move:
3181 res_abort_move(dev, slave, RES_CQ, cqn);
3182 return err;
3183}
3184
3185int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3186 struct mlx4_vhcr *vhcr,
3187 struct mlx4_cmd_mailbox *inbox,
3188 struct mlx4_cmd_mailbox *outbox,
3189 struct mlx4_cmd_info *cmd)
3190{
3191 int cqn = vhcr->in_modifier;
3192 struct res_cq *cq;
3193 int err;
3194
3195 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3196 if (err)
3197 return err;
3198
3199 if (cq->com.from_state != RES_CQ_HW)
3200 goto ex_put;
3201
3202 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3203ex_put:
3204 put_res(dev, slave, cqn, RES_CQ);
3205
3206 return err;
3207}
3208
3209static int handle_resize(struct mlx4_dev *dev, int slave,
3210 struct mlx4_vhcr *vhcr,
3211 struct mlx4_cmd_mailbox *inbox,
3212 struct mlx4_cmd_mailbox *outbox,
3213 struct mlx4_cmd_info *cmd,
3214 struct res_cq *cq)
3215{
3216 int err;
3217 struct res_mtt *orig_mtt;
3218 struct res_mtt *mtt;
3219 struct mlx4_cq_context *cqc = inbox->buf;
2b8fb286 3220 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3221
3222 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3223 if (err)
3224 return err;
3225
3226 if (orig_mtt != cq->mtt) {
3227 err = -EINVAL;
3228 goto ex_put;
3229 }
3230
2b8fb286 3231 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3232 if (err)
3233 goto ex_put;
3234
3235 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3236 if (err)
3237 goto ex_put1;
3238 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3239 if (err)
3240 goto ex_put1;
3241 atomic_dec(&orig_mtt->ref_count);
3242 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3243 atomic_inc(&mtt->ref_count);
3244 cq->mtt = mtt;
3245 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3246 return 0;
3247
3248ex_put1:
3249 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3250ex_put:
3251 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3252
3253 return err;
3254
3255}
3256
3257int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3258 struct mlx4_vhcr *vhcr,
3259 struct mlx4_cmd_mailbox *inbox,
3260 struct mlx4_cmd_mailbox *outbox,
3261 struct mlx4_cmd_info *cmd)
3262{
3263 int cqn = vhcr->in_modifier;
3264 struct res_cq *cq;
3265 int err;
3266
3267 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3268 if (err)
3269 return err;
3270
3271 if (cq->com.from_state != RES_CQ_HW)
3272 goto ex_put;
3273
3274 if (vhcr->op_modifier == 0) {
3275 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
dcf353b1 3276 goto ex_put;
c82e9aa0
EC		 3277 }
3278
3279 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3280ex_put:
3281 put_res(dev, slave, cqn, RES_CQ);
3282
3283 return err;
3284}
3285
c82e9aa0
EC		 3286static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3287{
3288 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3289 int log_rq_stride = srqc->logstride & 7;
3290 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3291
3292 if (log_srq_size + log_rq_stride + 4 < page_shift)
3293 return 1;
3294
3295 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3296}
3297
3298int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3299 struct mlx4_vhcr *vhcr,
3300 struct mlx4_cmd_mailbox *inbox,
3301 struct mlx4_cmd_mailbox *outbox,
3302 struct mlx4_cmd_info *cmd)
3303{
3304 int err;
3305 int srqn = vhcr->in_modifier;
3306 struct res_mtt *mtt;
3307 struct res_srq *srq;
3308 struct mlx4_srq_context *srqc = inbox->buf;
2b8fb286 3309 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
c82e9aa0
EC		 3310
3311 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3312 return -EINVAL;
3313
3314 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3315 if (err)
3316 return err;
2b8fb286 3317 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
c82e9aa0
EC		 3318 if (err)
3319 goto ex_abort;
3320 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3321 mtt);
3322 if (err)
3323 goto ex_put_mtt;
3324
c82e9aa0
EC		 3325 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3326 if (err)
3327 goto ex_put_mtt;
3328
3329 atomic_inc(&mtt->ref_count);
3330 srq->mtt = mtt;
3331 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3332 res_end_move(dev, slave, RES_SRQ, srqn);
3333 return 0;
3334
3335ex_put_mtt:
3336 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3337ex_abort:
3338 res_abort_move(dev, slave, RES_SRQ, srqn);
3339
3340 return err;
3341}
3342
3343int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3344 struct mlx4_vhcr *vhcr,
3345 struct mlx4_cmd_mailbox *inbox,
3346 struct mlx4_cmd_mailbox *outbox,
3347 struct mlx4_cmd_info *cmd)
3348{
3349 int err;
3350 int srqn = vhcr->in_modifier;
3351 struct res_srq *srq;
3352
3353 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3354 if (err)
3355 return err;
3356 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3357 if (err)
3358 goto ex_abort;
3359 atomic_dec(&srq->mtt->ref_count);
3360 if (srq->cq)
3361 atomic_dec(&srq->cq->ref_count);
3362 res_end_move(dev, slave, RES_SRQ, srqn);
3363
3364 return 0;
3365
3366ex_abort:
3367 res_abort_move(dev, slave, RES_SRQ, srqn);
3368
3369 return err;
3370}
3371
3372int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3373 struct mlx4_vhcr *vhcr,
3374 struct mlx4_cmd_mailbox *inbox,
3375 struct mlx4_cmd_mailbox *outbox,
3376 struct mlx4_cmd_info *cmd)
3377{
3378 int err;
3379 int srqn = vhcr->in_modifier;
3380 struct res_srq *srq;
3381
3382 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3383 if (err)
3384 return err;
3385 if (srq->com.from_state != RES_SRQ_HW) {
3386 err = -EBUSY;
3387 goto out;
3388 }
3389 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3390out:
3391 put_res(dev, slave, srqn, RES_SRQ);
3392 return err;
3393}
3394
3395int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3396 struct mlx4_vhcr *vhcr,
3397 struct mlx4_cmd_mailbox *inbox,
3398 struct mlx4_cmd_mailbox *outbox,
3399 struct mlx4_cmd_info *cmd)
3400{
3401 int err;
3402 int srqn = vhcr->in_modifier;
3403 struct res_srq *srq;
3404
3405 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3406 if (err)
3407 return err;
3408
3409 if (srq->com.from_state != RES_SRQ_HW) {
3410 err = -EBUSY;
3411 goto out;
3412 }
3413
3414 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3415out:
3416 put_res(dev, slave, srqn, RES_SRQ);
3417 return err;
3418}
3419
3420int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3421 struct mlx4_vhcr *vhcr,
3422 struct mlx4_cmd_mailbox *inbox,
3423 struct mlx4_cmd_mailbox *outbox,
3424 struct mlx4_cmd_info *cmd)
3425{
3426 int err;
3427 int qpn = vhcr->in_modifier & 0x7fffff;
3428 struct res_qp *qp;
3429
3430 err = get_res(dev, slave, qpn, RES_QP, &qp);
3431 if (err)
3432 return err;
3433 if (qp->com.from_state != RES_QP_HW) {
3434 err = -EBUSY;
3435 goto out;
3436 }
3437
3438 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3439out:
3440 put_res(dev, slave, qpn, RES_QP);
3441 return err;
3442}
3443
54679e14
JM		 3444int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3445 struct mlx4_vhcr *vhcr,
3446 struct mlx4_cmd_mailbox *inbox,
3447 struct mlx4_cmd_mailbox *outbox,
3448 struct mlx4_cmd_info *cmd)
3449{
3450 struct mlx4_qp_context *context = inbox->buf + 8;
3451 adjust_proxy_tun_qkey(dev, vhcr, context);
3452 update_pkey_index(dev, slave, inbox);
3453 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3454}
3455
449fc488
MB		 3456static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
3457 struct mlx4_qp_context *qpc,
3458 struct mlx4_cmd_mailbox *inbox)
3459{
3460 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
3461 u8 pri_sched_queue;
3462 int port = mlx4_slave_convert_port(
3463 dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
3464
3465 if (port < 0)
3466 return -EINVAL;
3467
3468 pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
3469 ((port & 1) << 6);
3470
3471 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH ||
3472 mlx4_is_eth(dev, port + 1)) {
3473 qpc->pri_path.sched_queue = pri_sched_queue;
3474 }
3475
3476 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
3477 port = mlx4_slave_convert_port(
3478 dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
3479 + 1) - 1;
3480 if (port < 0)
3481 return -EINVAL;
3482 qpc->alt_path.sched_queue =
3483 (qpc->alt_path.sched_queue & ~(1 << 6)) |
3484 (port & 1) << 6;
3485 }
3486 return 0;
3487}
3488
2f5bb473
JM		 3489static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3490 struct mlx4_qp_context *qpc,
3491 struct mlx4_cmd_mailbox *inbox)
3492{
3493 u64 mac;
3494 int port;
3495 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3496 u8 sched = *(u8 *)(inbox->buf + 64);
3497 u8 smac_ix;
3498
3499 port = (sched >> 6 & 1) + 1;
3500 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3501 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3502 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3503 return -ENOENT;
3504 }
3505 return 0;
3506}
3507
c82e9aa0
EC		 3508int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3509 struct mlx4_vhcr *vhcr,
3510 struct mlx4_cmd_mailbox *inbox,
3511 struct mlx4_cmd_mailbox *outbox,
3512 struct mlx4_cmd_info *cmd)
3513{
54679e14 3514 int err;
c82e9aa0 3515 struct mlx4_qp_context *qpc = inbox->buf + 8;
b01978ca
JM		 3516 int qpn = vhcr->in_modifier & 0x7fffff;
3517 struct res_qp *qp;
3518 u8 orig_sched_queue;
f0f829bf
RE		 3519 __be32 orig_param3 = qpc->param3;
3520 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3521 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3522 u8 orig_pri_path_fl = qpc->pri_path.fl;
3523 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3524 u8 orig_feup = qpc->pri_path.feup;
c82e9aa0 3525
449fc488
MB		 3526 err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
3527 if (err)
3528 return err;
99ec41d0 3529 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
54679e14
JM		 3530 if (err)
3531 return err;
3532
2f5bb473
JM		 3533 if (roce_verify_mac(dev, slave, qpc, inbox))
3534 return -EINVAL;
3535
54679e14
JM		 3536 update_pkey_index(dev, slave, inbox);
3537 update_gid(dev, inbox, (u8)slave);
3538 adjust_proxy_tun_qkey(dev, vhcr, qpc);
b01978ca
JM		 3539 orig_sched_queue = qpc->pri_path.sched_queue;
3540 err = update_vport_qp_param(dev, inbox, slave, qpn);
3f7fb021
RE		 3541 if (err)
3542 return err;
54679e14 3543
b01978ca
JM		 3544 err = get_res(dev, slave, qpn, RES_QP, &qp);
3545 if (err)
3546 return err;
3547 if (qp->com.from_state != RES_QP_HW) {
3548 err = -EBUSY;
3549 goto out;
3550 }
3551
3552 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3553out:
3554 /* if no error, save sched queue value passed in by VF. This is
3555 * essentially the QOS value provided by the VF. This will be useful
3556 * if we allow dynamic changes from VST back to VGT
3557 */
f0f829bf 3558 if (!err) {
b01978ca 3559 qp->sched_queue = orig_sched_queue;
f0f829bf
RE		 3560 qp->param3 = orig_param3;
3561 qp->vlan_control = orig_vlan_control;
3562 qp->fvl_rx = orig_fvl_rx;
3563 qp->pri_path_fl = orig_pri_path_fl;
3564 qp->vlan_index = orig_vlan_index;
3565 qp->feup = orig_feup;
3566 }
b01978ca
JM		 3567 put_res(dev, slave, qpn, RES_QP);
3568 return err;
54679e14
JM		 3569}
3570
3571int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3572 struct mlx4_vhcr *vhcr,
3573 struct mlx4_cmd_mailbox *inbox,
3574 struct mlx4_cmd_mailbox *outbox,
3575 struct mlx4_cmd_info *cmd)
3576{
3577 int err;
3578 struct mlx4_qp_context *context = inbox->buf + 8;
3579
449fc488
MB		 3580 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3581 if (err)
3582 return err;
99ec41d0 3583 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
54679e14
JM		 3584 if (err)
3585 return err;
3586
3587 update_pkey_index(dev, slave, inbox);
3588 update_gid(dev, inbox, (u8)slave);
3589 adjust_proxy_tun_qkey(dev, vhcr, context);
3590 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3591}
3592
3593int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3594 struct mlx4_vhcr *vhcr,
3595 struct mlx4_cmd_mailbox *inbox,
3596 struct mlx4_cmd_mailbox *outbox,
3597 struct mlx4_cmd_info *cmd)
3598{
3599 int err;
3600 struct mlx4_qp_context *context = inbox->buf + 8;
3601
449fc488
MB		 3602 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3603 if (err)
3604 return err;
99ec41d0 3605 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
54679e14
JM		 3606 if (err)
3607 return err;
3608
3609 update_pkey_index(dev, slave, inbox);
3610 update_gid(dev, inbox, (u8)slave);
3611 adjust_proxy_tun_qkey(dev, vhcr, context);
3612 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3613}
3614
3615
3616int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3617 struct mlx4_vhcr *vhcr,
3618 struct mlx4_cmd_mailbox *inbox,
3619 struct mlx4_cmd_mailbox *outbox,
3620 struct mlx4_cmd_info *cmd)
3621{
3622 struct mlx4_qp_context *context = inbox->buf + 8;
449fc488
MB		 3623 int err = adjust_qp_sched_queue(dev, slave, context, inbox);
3624 if (err)
3625 return err;
54679e14
JM		 3626 adjust_proxy_tun_qkey(dev, vhcr, context);
3627 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3628}
3629
3630int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3631 struct mlx4_vhcr *vhcr,
3632 struct mlx4_cmd_mailbox *inbox,
3633 struct mlx4_cmd_mailbox *outbox,
3634 struct mlx4_cmd_info *cmd)
3635{
3636 int err;
3637 struct mlx4_qp_context *context = inbox->buf + 8;
3638
449fc488
MB		 3639 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3640 if (err)
3641 return err;
99ec41d0 3642 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
54679e14
JM		 3643 if (err)
3644 return err;
3645
3646 adjust_proxy_tun_qkey(dev, vhcr, context);
3647 update_gid(dev, inbox, (u8)slave);
3648 update_pkey_index(dev, slave, inbox);
3649 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3650}
3651
3652int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3653 struct mlx4_vhcr *vhcr,
3654 struct mlx4_cmd_mailbox *inbox,
3655 struct mlx4_cmd_mailbox *outbox,
3656 struct mlx4_cmd_info *cmd)
3657{
3658 int err;
3659 struct mlx4_qp_context *context = inbox->buf + 8;
3660
449fc488
MB		 3661 err = adjust_qp_sched_queue(dev, slave, context, inbox);
3662 if (err)
3663 return err;
99ec41d0 3664 err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
54679e14
JM		 3665 if (err)
3666 return err;
c82e9aa0 3667
54679e14
JM		 3668 adjust_proxy_tun_qkey(dev, vhcr, context);
3669 update_gid(dev, inbox, (u8)slave);
3670 update_pkey_index(dev, slave, inbox);
c82e9aa0
EC		 3671 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3672}
3673
3674int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3675 struct mlx4_vhcr *vhcr,
3676 struct mlx4_cmd_mailbox *inbox,
3677 struct mlx4_cmd_mailbox *outbox,
3678 struct mlx4_cmd_info *cmd)
3679{
3680 int err;
3681 int qpn = vhcr->in_modifier & 0x7fffff;
3682 struct res_qp *qp;
3683
3684 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3685 if (err)
3686 return err;
3687 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3688 if (err)
3689 goto ex_abort;
3690
3691 atomic_dec(&qp->mtt->ref_count);
3692 atomic_dec(&qp->rcq->ref_count);
3693 atomic_dec(&qp->scq->ref_count);
3694 if (qp->srq)
3695 atomic_dec(&qp->srq->ref_count);
3696 res_end_move(dev, slave, RES_QP, qpn);
3697 return 0;
3698
3699ex_abort:
3700 res_abort_move(dev, slave, RES_QP, qpn);
3701
3702 return err;
3703}
3704
3705static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3706 struct res_qp *rqp, u8 *gid)
3707{
3708 struct res_gid *res;
3709
3710 list_for_each_entry(res, &rqp->mcg_list, list) {
3711 if (!memcmp(res->gid, gid, 16))
3712 return res;
3713 }
3714 return NULL;
3715}
3716
3717static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3718 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3719 enum mlx4_steer_type steer, u64 reg_id)
c82e9aa0
EC		 3720{
3721 struct res_gid *res;
3722 int err;
3723
3724 res = kzalloc(sizeof *res, GFP_KERNEL);
3725 if (!res)
3726 return -ENOMEM;
3727
3728 spin_lock_irq(&rqp->mcg_spl);
3729 if (find_gid(dev, slave, rqp, gid)) {
3730 kfree(res);
3731 err = -EEXIST;
3732 } else {
3733 memcpy(res->gid, gid, 16);
3734 res->prot = prot;
9f5b6c63 3735 res->steer = steer;
fab1e24a 3736 res->reg_id = reg_id;
c82e9aa0
EC		 3737 list_add_tail(&res->list, &rqp->mcg_list);
3738 err = 0;
3739 }
3740 spin_unlock_irq(&rqp->mcg_spl);
3741
3742 return err;
3743}
3744
3745static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
9f5b6c63 3746 u8 *gid, enum mlx4_protocol prot,
fab1e24a 3747 enum mlx4_steer_type steer, u64 *reg_id)
c82e9aa0
EC		 3748{
3749 struct res_gid *res;
3750 int err;
3751
3752 spin_lock_irq(&rqp->mcg_spl);
3753 res = find_gid(dev, slave, rqp, gid);
9f5b6c63 3754 if (!res || res->prot != prot || res->steer != steer)
c82e9aa0
EC		 3755 err = -EINVAL;
3756 else {
fab1e24a 3757 *reg_id = res->reg_id;
c82e9aa0
EC		 3758 list_del(&res->list);
3759 kfree(res);
3760 err = 0;
3761 }
3762 spin_unlock_irq(&rqp->mcg_spl);
3763
3764 return err;
3765}
3766
449fc488
MB		 3767static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
3768 u8 gid[16], int block_loopback, enum mlx4_protocol prot,
fab1e24a
HHZ		 3769 enum mlx4_steer_type type, u64 *reg_id)
3770{
3771 switch (dev->caps.steering_mode) {
449fc488
MB		 3772 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
3773 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3774 if (port < 0)
3775 return port;
3776 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
fab1e24a
HHZ		 3777 block_loopback, prot,
3778 reg_id);
449fc488 3779 }
fab1e24a 3780 case MLX4_STEERING_MODE_B0:
449fc488
MB		 3781 if (prot == MLX4_PROT_ETH) {
3782 int port = mlx4_slave_convert_port(dev, slave, gid[5]);
3783 if (port < 0)
3784 return port;
3785 gid[5] = port;
3786 }
fab1e24a
HHZ		 3787 return mlx4_qp_attach_common(dev, qp, gid,
3788 block_loopback, prot, type);
3789 default:
3790 return -EINVAL;
3791 }
3792}
3793
449fc488
MB		 3794static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
3795 u8 gid[16], enum mlx4_protocol prot,
3796 enum mlx4_steer_type type, u64 reg_id)
fab1e24a
HHZ		 3797{
3798 switch (dev->caps.steering_mode) {
3799 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3800 return mlx4_flow_detach(dev, reg_id);
3801 case MLX4_STEERING_MODE_B0:
3802 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
3803 default:
3804 return -EINVAL;
3805 }
3806}
3807
531d9014
JM		 3808static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
3809 u8 *gid, enum mlx4_protocol prot)
3810{
3811 int real_port;
3812
3813 if (prot != MLX4_PROT_ETH)
3814 return 0;
3815
3816 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
3817 dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3818 real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
3819 if (real_port < 0)
3820 return -EINVAL;
3821 gid[5] = real_port;
3822 }
3823
3824 return 0;
3825}
3826
c82e9aa0
EC		 3827int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3828 struct mlx4_vhcr *vhcr,
3829 struct mlx4_cmd_mailbox *inbox,
3830 struct mlx4_cmd_mailbox *outbox,
3831 struct mlx4_cmd_info *cmd)
3832{
3833 struct mlx4_qp qp; /* dummy for calling attach/detach */
3834 u8 *gid = inbox->buf;
3835 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
162344ed 3836 int err;
c82e9aa0
EC		 3837 int qpn;
3838 struct res_qp *rqp;
fab1e24a 3839 u64 reg_id = 0;
c82e9aa0
EC		 3840 int attach = vhcr->op_modifier;
3841 int block_loopback = vhcr->in_modifier >> 31;
3842 u8 steer_type_mask = 2;
75c6062c 3843 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
c82e9aa0
EC		 3844
3845 qpn = vhcr->in_modifier & 0xffffff;
3846 err = get_res(dev, slave, qpn, RES_QP, &rqp);
3847 if (err)
3848 return err;
3849
3850 qp.qpn = qpn;
3851 if (attach) {
449fc488 3852 err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
fab1e24a
HHZ		 3853 type, &reg_id);
3854 if (err) {
3855 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
c82e9aa0 3856 goto ex_put;
fab1e24a
HHZ		 3857 }
3858 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
c82e9aa0 3859 if (err)
fab1e24a 3860 goto ex_detach;
c82e9aa0 3861 } else {
531d9014
JM		 3862 err = mlx4_adjust_port(dev, slave, gid, prot);
3863 if (err)
3864 goto ex_put;
3865
fab1e24a 3866 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
c82e9aa0
EC		 3867 if (err)
3868 goto ex_put;
c82e9aa0 3869
fab1e24a
HHZ		 3870 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
3871 if (err)
3872 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
3873 qpn, reg_id);
3874 }
c82e9aa0 3875 put_res(dev, slave, qpn, RES_QP);
fab1e24a 3876 return err;
c82e9aa0 3877
fab1e24a
HHZ		 3878ex_detach:
3879 qp_detach(dev, &qp, gid, prot, type, reg_id);
c82e9aa0
EC		 3880ex_put:
3881 put_res(dev, slave, qpn, RES_QP);
c82e9aa0
EC		 3882 return err;
3883}
3884
7fb40f87
HHZ		 3885/*
3886 * MAC validation for Flow Steering rules.
3887 * VF can attach rules only with a mac address which is assigned to it.
3888 */
3889static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
3890 struct list_head *rlist)
3891{
3892 struct mac_res *res, *tmp;
3893 __be64 be_mac;
3894
3895 /* make sure it isn't multicast or broadcast mac*/
3896 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
3897 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
3898 list_for_each_entry_safe(res, tmp, rlist, list) {
3899 be_mac = cpu_to_be64(res->mac << 16);
c0623e58 3900 if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
7fb40f87
HHZ		 3901 return 0;
3902 }
3903 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
3904 eth_header->eth.dst_mac, slave);
3905 return -EINVAL;
3906 }
3907 return 0;
3908}
3909
3910/*
3911 * In case of missing eth header, append eth header with a MAC address
3912 * assigned to the VF.
3913 */
3914static int add_eth_header(struct mlx4_dev *dev, int slave,
3915 struct mlx4_cmd_mailbox *inbox,
3916 struct list_head *rlist, int header_id)
3917{
3918 struct mac_res *res, *tmp;
3919 u8 port;
3920 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3921 struct mlx4_net_trans_rule_hw_eth *eth_header;
3922 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
3923 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
3924 __be64 be_mac = 0;
3925 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
3926
3927 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
015465f8 3928 port = ctrl->port;
7fb40f87
HHZ		 3929 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
3930
3931 /* Clear a space in the inbox for eth header */
3932 switch (header_id) {
3933 case MLX4_NET_TRANS_RULE_ID_IPV4:
3934 ip_header =
3935 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
3936 memmove(ip_header, eth_header,
3937 sizeof(*ip_header) + sizeof(*l4_header));
3938 break;
3939 case MLX4_NET_TRANS_RULE_ID_TCP:
3940 case MLX4_NET_TRANS_RULE_ID_UDP:
3941 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
3942 (eth_header + 1);
3943 memmove(l4_header, eth_header, sizeof(*l4_header));
3944 break;
3945 default:
3946 return -EINVAL;
3947 }
3948 list_for_each_entry_safe(res, tmp, rlist, list) {
3949 if (port == res->port) {
3950 be_mac = cpu_to_be64(res->mac << 16);
3951 break;
3952 }
3953 }
3954 if (!be_mac) {
1a91de28 3955 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
7fb40f87
HHZ		 3956 port);
3957 return -EINVAL;
3958 }
3959
3960 memset(eth_header, 0, sizeof(*eth_header));
3961 eth_header->size = sizeof(*eth_header) >> 2;
3962 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
3963 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
3964 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
3965
3966 return 0;
3967
3968}
3969
ce8d9e0d
MB		 3970#define MLX4_UPD_QP_PATH_MASK_SUPPORTED (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)
3971int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
3972 struct mlx4_vhcr *vhcr,
3973 struct mlx4_cmd_mailbox *inbox,
3974 struct mlx4_cmd_mailbox *outbox,
3975 struct mlx4_cmd_info *cmd_info)
3976{
3977 int err;
3978 u32 qpn = vhcr->in_modifier & 0xffffff;
3979 struct res_qp *rqp;
3980 u64 mac;
3981 unsigned port;
3982 u64 pri_addr_path_mask;
3983 struct mlx4_update_qp_context *cmd;
3984 int smac_index;
3985
3986 cmd = (struct mlx4_update_qp_context *)inbox->buf;
3987
3988 pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
3989 if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
3990 (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
3991 return -EPERM;
3992
3993 /* Just change the smac for the QP */
3994 err = get_res(dev, slave, qpn, RES_QP, &rqp);
3995 if (err) {
3996 mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
3997 return err;
3998 }
3999
4000 port = (rqp->sched_queue >> 6 & 1) + 1;
4001 smac_index = cmd->qp_context.pri_path.grh_mylmc;
4002 err = mac_find_smac_ix_in_slave(dev, slave, port,
4003 smac_index, &mac);
4004 if (err) {
4005 mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
4006 qpn, smac_index);
4007 goto err_mac;
4008 }
4009
4010 err = mlx4_cmd(dev, inbox->dma,
4011 vhcr->in_modifier, 0,
4012 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
4013 MLX4_CMD_NATIVE);
4014 if (err) {
4015 mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
4016 goto err_mac;
4017 }
4018
4019err_mac:
4020 put_res(dev, slave, qpn, RES_QP);
4021 return err;
4022}
4023
8fcfb4db
HHZ		 4024int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
4025 struct mlx4_vhcr *vhcr,
4026 struct mlx4_cmd_mailbox *inbox,
4027 struct mlx4_cmd_mailbox *outbox,
4028 struct mlx4_cmd_info *cmd)
4029{
7fb40f87
HHZ		 4030
4031 struct mlx4_priv *priv = mlx4_priv(dev);
4032 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4033 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
1b9c6b06 4034 int err;
a9c01e7a 4035 int qpn;
2c473ae7 4036 struct res_qp *rqp;
7fb40f87
HHZ		 4037 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
4038 struct _rule_hw *rule_header;
4039 int header_id;
1b9c6b06 4040
0ff1fb65
HHZ		 4041 if (dev->caps.steering_mode !=
4042 MLX4_STEERING_MODE_DEVICE_MANAGED)
4043 return -EOPNOTSUPP;
1b9c6b06 4044
7fb40f87 4045 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
449fc488
MB		 4046 ctrl->port = mlx4_slave_convert_port(dev, slave, ctrl->port);
4047 if (ctrl->port <= 0)
4048 return -EINVAL;
a9c01e7a 4049 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
2c473ae7 4050 err = get_res(dev, slave, qpn, RES_QP, &rqp);
a9c01e7a 4051 if (err) {
1a91de28 4052 pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
a9c01e7a
HHZ		 4053 return err;
4054 }
7fb40f87
HHZ		 4055 rule_header = (struct _rule_hw *)(ctrl + 1);
4056 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
4057
4058 switch (header_id) {
4059 case MLX4_NET_TRANS_RULE_ID_ETH:
a9c01e7a
HHZ		 4060 if (validate_eth_header_mac(slave, rule_header, rlist)) {
4061 err = -EINVAL;
4062 goto err_put;
4063 }
7fb40f87 4064 break;
60396683
JM		 4065 case MLX4_NET_TRANS_RULE_ID_IB:
4066 break;
7fb40f87
HHZ		 4067 case MLX4_NET_TRANS_RULE_ID_IPV4:
4068 case MLX4_NET_TRANS_RULE_ID_TCP:
4069 case MLX4_NET_TRANS_RULE_ID_UDP:
1a91de28 4070 pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
a9c01e7a
HHZ		 4071 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
4072 err = -EINVAL;
4073 goto err_put;
4074 }
7fb40f87
HHZ		 4075 vhcr->in_modifier +=
4076 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
4077 break;
4078 default:
1a91de28 4079 pr_err("Corrupted mailbox\n");
a9c01e7a
HHZ		 4080 err = -EINVAL;
4081 goto err_put;
7fb40f87
HHZ		 4082 }
4083
1b9c6b06
HHZ		 4084 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
4085 vhcr->in_modifier, 0,
4086 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
4087 MLX4_CMD_NATIVE);
4088 if (err)
a9c01e7a 4089 goto err_put;
1b9c6b06 4090
2c473ae7 4091 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
1b9c6b06 4092 if (err) {
1a91de28 4093 mlx4_err(dev, "Fail to add flow steering resources\n");
1b9c6b06
HHZ		 4094 /* detach rule*/
4095 mlx4_cmd(dev, vhcr->out_param, 0, 0,
2065b38b 4096 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1b9c6b06 4097 MLX4_CMD_NATIVE);
2c473ae7 4098 goto err_put;
1b9c6b06 4099 }
2c473ae7 4100 atomic_inc(&rqp->ref_count);
a9c01e7a
HHZ		 4101err_put:
4102 put_res(dev, slave, qpn, RES_QP);
1b9c6b06 4103 return err;
8fcfb4db
HHZ		 4104}
4105
4106int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
4107 struct mlx4_vhcr *vhcr,
4108 struct mlx4_cmd_mailbox *inbox,
4109 struct mlx4_cmd_mailbox *outbox,
4110 struct mlx4_cmd_info *cmd)
4111{
1b9c6b06 4112 int err;
2c473ae7
HHZ		 4113 struct res_qp *rqp;
4114 struct res_fs_rule *rrule;
1b9c6b06 4115
0ff1fb65
HHZ		 4116 if (dev->caps.steering_mode !=
4117 MLX4_STEERING_MODE_DEVICE_MANAGED)
4118 return -EOPNOTSUPP;
1b9c6b06 4119
2c473ae7
HHZ		 4120 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
4121 if (err)
4122 return err;
4123 /* Release the rule form busy state before removal */
4124 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
4125 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
4126 if (err)
4127 return err;
4128
1b9c6b06
HHZ		 4129 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
4130 if (err) {
1a91de28 4131 mlx4_err(dev, "Fail to remove flow steering resources\n");
2c473ae7 4132 goto out;
1b9c6b06
HHZ		 4133 }
4134
4135 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4136 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
4137 MLX4_CMD_NATIVE);
2c473ae7
HHZ		 4138 if (!err)
4139 atomic_dec(&rqp->ref_count);
4140out:
4141 put_res(dev, slave, rrule->qpn, RES_QP);
1b9c6b06 4142 return err;
8fcfb4db
HHZ		 4143}
4144
c82e9aa0
EC		 4145enum {
4146 BUSY_MAX_RETRIES = 10
4147};
4148
4149int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
4150 struct mlx4_vhcr *vhcr,
4151 struct mlx4_cmd_mailbox *inbox,
4152 struct mlx4_cmd_mailbox *outbox,
4153 struct mlx4_cmd_info *cmd)
4154{
4155 int err;
4156 int index = vhcr->in_modifier & 0xffff;
4157
4158 err = get_res(dev, slave, index, RES_COUNTER, NULL);
4159 if (err)
4160 return err;
4161
4162 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
4163 put_res(dev, slave, index, RES_COUNTER);
4164 return err;
4165}
4166
4167static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
4168{
4169 struct res_gid *rgid;
4170 struct res_gid *tmp;
c82e9aa0
EC		 4171 struct mlx4_qp qp; /* dummy for calling attach/detach */
4172
4173 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
fab1e24a
HHZ		 4174 switch (dev->caps.steering_mode) {
4175 case MLX4_STEERING_MODE_DEVICE_MANAGED:
4176 mlx4_flow_detach(dev, rgid->reg_id);
4177 break;
4178 case MLX4_STEERING_MODE_B0:
4179 qp.qpn = rqp->local_qpn;
4180 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
4181 rgid->prot, rgid->steer);
4182 break;
4183 }
c82e9aa0
EC		 4184 list_del(&rgid->list);
4185 kfree(rgid);
4186 }
4187}
4188
4189static int _move_all_busy(struct mlx4_dev *dev, int slave,
4190 enum mlx4_resource type, int print)
4191{
4192 struct mlx4_priv *priv = mlx4_priv(dev);
4193 struct mlx4_resource_tracker *tracker =
4194 &priv->mfunc.master.res_tracker;
4195 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4196 struct res_common *r;
4197 struct res_common *tmp;
4198 int busy;
4199
4200 busy = 0;
4201 spin_lock_irq(mlx4_tlock(dev));
4202 list_for_each_entry_safe(r, tmp, rlist, list) {
4203 if (r->owner == slave) {
4204 if (!r->removing) {
4205 if (r->state == RES_ANY_BUSY) {
4206 if (print)
4207 mlx4_dbg(dev,
aa1ec3dd 4208 "%s id 0x%llx is busy\n",
95646373 4209 resource_str(type),
c82e9aa0
EC		 4210 r->res_id);
4211 ++busy;
4212 } else {
4213 r->from_state = r->state;
4214 r->state = RES_ANY_BUSY;
4215 r->removing = 1;
4216 }
4217 }
4218 }
4219 }
4220 spin_unlock_irq(mlx4_tlock(dev));
4221
4222 return busy;
4223}
4224
4225static int move_all_busy(struct mlx4_dev *dev, int slave,
4226 enum mlx4_resource type)
4227{
4228 unsigned long begin;
4229 int busy;
4230
4231 begin = jiffies;
4232 do {
4233 busy = _move_all_busy(dev, slave, type, 0);
4234 if (time_after(jiffies, begin + 5 * HZ))
4235 break;
4236 if (busy)
4237 cond_resched();
4238 } while (busy);
4239
4240 if (busy)
4241 busy = _move_all_busy(dev, slave, type, 1);
4242
4243 return busy;
4244}
4245static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4246{
4247 struct mlx4_priv *priv = mlx4_priv(dev);
4248 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4249 struct list_head *qp_list =
4250 &tracker->slave_list[slave].res_list[RES_QP];
4251 struct res_qp *qp;
4252 struct res_qp *tmp;
4253 int state;
4254 u64 in_param;
4255 int qpn;
4256 int err;
4257
4258 err = move_all_busy(dev, slave, RES_QP);
4259 if (err)
1a91de28
JP		 4260 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
4261 slave);
c82e9aa0
EC		 4262
4263 spin_lock_irq(mlx4_tlock(dev));
4264 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4265 spin_unlock_irq(mlx4_tlock(dev));
4266 if (qp->com.owner == slave) {
4267 qpn = qp->com.res_id;
4268 detach_qp(dev, slave, qp);
4269 state = qp->com.from_state;
4270 while (state != 0) {
4271 switch (state) {
4272 case RES_QP_RESERVED:
4273 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4274 rb_erase(&qp->com.node,
4275 &tracker->res_tree[RES_QP]);
c82e9aa0
EC		 4276 list_del(&qp->com.list);
4277 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4278 if (!valid_reserved(dev, slave, qpn)) {
4279 __mlx4_qp_release_range(dev, qpn, 1);
4280 mlx4_release_resource(dev, slave,
4281 RES_QP, 1, 0);
4282 }
c82e9aa0
EC		 4283 kfree(qp);
4284 state = 0;
4285 break;
4286 case RES_QP_MAPPED:
4287 if (!valid_reserved(dev, slave, qpn))
4288 __mlx4_qp_free_icm(dev, qpn);
4289 state = RES_QP_RESERVED;
4290 break;
4291 case RES_QP_HW:
4292 in_param = slave;
4293 err = mlx4_cmd(dev, in_param,
4294 qp->local_qpn, 2,
4295 MLX4_CMD_2RST_QP,
4296 MLX4_CMD_TIME_CLASS_A,
4297 MLX4_CMD_NATIVE);
4298 if (err)
1a91de28
JP		 4299 mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
4300 slave, qp->local_qpn);
c82e9aa0
EC		 4301 atomic_dec(&qp->rcq->ref_count);
4302 atomic_dec(&qp->scq->ref_count);
4303 atomic_dec(&qp->mtt->ref_count);
4304 if (qp->srq)
4305 atomic_dec(&qp->srq->ref_count);
4306 state = RES_QP_MAPPED;
4307 break;
4308 default:
4309 state = 0;
4310 }
4311 }
4312 }
4313 spin_lock_irq(mlx4_tlock(dev));
4314 }
4315 spin_unlock_irq(mlx4_tlock(dev));
4316}
4317
4318static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4319{
4320 struct mlx4_priv *priv = mlx4_priv(dev);
4321 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4322 struct list_head *srq_list =
4323 &tracker->slave_list[slave].res_list[RES_SRQ];
4324 struct res_srq *srq;
4325 struct res_srq *tmp;
4326 int state;
4327 u64 in_param;
4328 LIST_HEAD(tlist);
4329 int srqn;
4330 int err;
4331
4332 err = move_all_busy(dev, slave, RES_SRQ);
4333 if (err)
1a91de28
JP		 4334 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
4335 slave);
c82e9aa0
EC		 4336
4337 spin_lock_irq(mlx4_tlock(dev));
4338 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4339 spin_unlock_irq(mlx4_tlock(dev));
4340 if (srq->com.owner == slave) {
4341 srqn = srq->com.res_id;
4342 state = srq->com.from_state;
4343 while (state != 0) {
4344 switch (state) {
4345 case RES_SRQ_ALLOCATED:
4346 __mlx4_srq_free_icm(dev, srqn);
4347 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4348 rb_erase(&srq->com.node,
4349 &tracker->res_tree[RES_SRQ]);
c82e9aa0
EC		 4350 list_del(&srq->com.list);
4351 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4352 mlx4_release_resource(dev, slave,
4353 RES_SRQ, 1, 0);
c82e9aa0
EC		 4354 kfree(srq);
4355 state = 0;
4356 break;
4357
4358 case RES_SRQ_HW:
4359 in_param = slave;
4360 err = mlx4_cmd(dev, in_param, srqn, 1,
4361 MLX4_CMD_HW2SW_SRQ,
4362 MLX4_CMD_TIME_CLASS_A,
4363 MLX4_CMD_NATIVE);
4364 if (err)
1a91de28 4365 mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
c82e9aa0
EC		 4366 slave, srqn);
4367
4368 atomic_dec(&srq->mtt->ref_count);
4369 if (srq->cq)
4370 atomic_dec(&srq->cq->ref_count);
4371 state = RES_SRQ_ALLOCATED;
4372 break;
4373
4374 default:
4375 state = 0;
4376 }
4377 }
4378 }
4379 spin_lock_irq(mlx4_tlock(dev));
4380 }
4381 spin_unlock_irq(mlx4_tlock(dev));
4382}
4383
4384static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4385{
4386 struct mlx4_priv *priv = mlx4_priv(dev);
4387 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4388 struct list_head *cq_list =
4389 &tracker->slave_list[slave].res_list[RES_CQ];
4390 struct res_cq *cq;
4391 struct res_cq *tmp;
4392 int state;
4393 u64 in_param;
4394 LIST_HEAD(tlist);
4395 int cqn;
4396 int err;
4397
4398 err = move_all_busy(dev, slave, RES_CQ);
4399 if (err)
1a91de28
JP		 4400 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
4401 slave);
c82e9aa0
EC		 4402
4403 spin_lock_irq(mlx4_tlock(dev));
4404 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4405 spin_unlock_irq(mlx4_tlock(dev));
4406 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4407 cqn = cq->com.res_id;
4408 state = cq->com.from_state;
4409 while (state != 0) {
4410 switch (state) {
4411 case RES_CQ_ALLOCATED:
4412 __mlx4_cq_free_icm(dev, cqn);
4413 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4414 rb_erase(&cq->com.node,
4415 &tracker->res_tree[RES_CQ]);
c82e9aa0
EC		 4416 list_del(&cq->com.list);
4417 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4418 mlx4_release_resource(dev, slave,
4419 RES_CQ, 1, 0);
c82e9aa0
EC		 4420 kfree(cq);
4421 state = 0;
4422 break;
4423
4424 case RES_CQ_HW:
4425 in_param = slave;
4426 err = mlx4_cmd(dev, in_param, cqn, 1,
4427 MLX4_CMD_HW2SW_CQ,
4428 MLX4_CMD_TIME_CLASS_A,
4429 MLX4_CMD_NATIVE);
4430 if (err)
1a91de28 4431 mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
c82e9aa0
EC		 4432 slave, cqn);
4433 atomic_dec(&cq->mtt->ref_count);
4434 state = RES_CQ_ALLOCATED;
4435 break;
4436
4437 default:
4438 state = 0;
4439 }
4440 }
4441 }
4442 spin_lock_irq(mlx4_tlock(dev));
4443 }
4444 spin_unlock_irq(mlx4_tlock(dev));
4445}
4446
4447static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4448{
4449 struct mlx4_priv *priv = mlx4_priv(dev);
4450 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4451 struct list_head *mpt_list =
4452 &tracker->slave_list[slave].res_list[RES_MPT];
4453 struct res_mpt *mpt;
4454 struct res_mpt *tmp;
4455 int state;
4456 u64 in_param;
4457 LIST_HEAD(tlist);
4458 int mptn;
4459 int err;
4460
4461 err = move_all_busy(dev, slave, RES_MPT);
4462 if (err)
1a91de28
JP		 4463 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
4464 slave);
c82e9aa0
EC		 4465
4466 spin_lock_irq(mlx4_tlock(dev));
4467 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4468 spin_unlock_irq(mlx4_tlock(dev));
4469 if (mpt->com.owner == slave) {
4470 mptn = mpt->com.res_id;
4471 state = mpt->com.from_state;
4472 while (state != 0) {
4473 switch (state) {
4474 case RES_MPT_RESERVED:
b20e519a 4475 __mlx4_mpt_release(dev, mpt->key);
c82e9aa0 4476 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4477 rb_erase(&mpt->com.node,
4478 &tracker->res_tree[RES_MPT]);
c82e9aa0
EC		 4479 list_del(&mpt->com.list);
4480 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4481 mlx4_release_resource(dev, slave,
4482 RES_MPT, 1, 0);
c82e9aa0
EC		 4483 kfree(mpt);
4484 state = 0;
4485 break;
4486
4487 case RES_MPT_MAPPED:
b20e519a 4488 __mlx4_mpt_free_icm(dev, mpt->key);
c82e9aa0
EC		 4489 state = RES_MPT_RESERVED;
4490 break;
4491
4492 case RES_MPT_HW:
4493 in_param = slave;
4494 err = mlx4_cmd(dev, in_param, mptn, 0,
4495 MLX4_CMD_HW2SW_MPT,
4496 MLX4_CMD_TIME_CLASS_A,
4497 MLX4_CMD_NATIVE);
4498 if (err)
1a91de28 4499 mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
c82e9aa0
EC		 4500 slave, mptn);
4501 if (mpt->mtt)
4502 atomic_dec(&mpt->mtt->ref_count);
4503 state = RES_MPT_MAPPED;
4504 break;
4505 default:
4506 state = 0;
4507 }
4508 }
4509 }
4510 spin_lock_irq(mlx4_tlock(dev));
4511 }
4512 spin_unlock_irq(mlx4_tlock(dev));
4513}
4514
4515static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4516{
4517 struct mlx4_priv *priv = mlx4_priv(dev);
4518 struct mlx4_resource_tracker *tracker =
4519 &priv->mfunc.master.res_tracker;
4520 struct list_head *mtt_list =
4521 &tracker->slave_list[slave].res_list[RES_MTT];
4522 struct res_mtt *mtt;
4523 struct res_mtt *tmp;
4524 int state;
4525 LIST_HEAD(tlist);
4526 int base;
4527 int err;
4528
4529 err = move_all_busy(dev, slave, RES_MTT);
4530 if (err)
1a91de28
JP		 4531 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
4532 slave);
c82e9aa0
EC		 4533
4534 spin_lock_irq(mlx4_tlock(dev));
4535 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4536 spin_unlock_irq(mlx4_tlock(dev));
4537 if (mtt->com.owner == slave) {
4538 base = mtt->com.res_id;
4539 state = mtt->com.from_state;
4540 while (state != 0) {
4541 switch (state) {
4542 case RES_MTT_ALLOCATED:
4543 __mlx4_free_mtt_range(dev, base,
4544 mtt->order);
4545 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4546 rb_erase(&mtt->com.node,
4547 &tracker->res_tree[RES_MTT]);
c82e9aa0
EC		 4548 list_del(&mtt->com.list);
4549 spin_unlock_irq(mlx4_tlock(dev));
146f3ef4
JM		 4550 mlx4_release_resource(dev, slave, RES_MTT,
4551 1 << mtt->order, 0);
c82e9aa0
EC		 4552 kfree(mtt);
4553 state = 0;
4554 break;
4555
4556 default:
4557 state = 0;
4558 }
4559 }
4560 }
4561 spin_lock_irq(mlx4_tlock(dev));
4562 }
4563 spin_unlock_irq(mlx4_tlock(dev));
4564}
4565
1b9c6b06
HHZ		 4566static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
4567{
4568 struct mlx4_priv *priv = mlx4_priv(dev);
4569 struct mlx4_resource_tracker *tracker =
4570 &priv->mfunc.master.res_tracker;
4571 struct list_head *fs_rule_list =
4572 &tracker->slave_list[slave].res_list[RES_FS_RULE];
4573 struct res_fs_rule *fs_rule;
4574 struct res_fs_rule *tmp;
4575 int state;
4576 u64 base;
4577 int err;
4578
4579 err = move_all_busy(dev, slave, RES_FS_RULE);
4580 if (err)
4581 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
4582 slave);
4583
4584 spin_lock_irq(mlx4_tlock(dev));
4585 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
4586 spin_unlock_irq(mlx4_tlock(dev));
4587 if (fs_rule->com.owner == slave) {
4588 base = fs_rule->com.res_id;
4589 state = fs_rule->com.from_state;
4590 while (state != 0) {
4591 switch (state) {
4592 case RES_FS_RULE_ALLOCATED:
4593 /* detach rule */
4594 err = mlx4_cmd(dev, base, 0, 0,
4595 MLX4_QP_FLOW_STEERING_DETACH,
4596 MLX4_CMD_TIME_CLASS_A,
4597 MLX4_CMD_NATIVE);
4598
4599 spin_lock_irq(mlx4_tlock(dev));
4600 rb_erase(&fs_rule->com.node,
4601 &tracker->res_tree[RES_FS_RULE]);
4602 list_del(&fs_rule->com.list);
4603 spin_unlock_irq(mlx4_tlock(dev));
4604 kfree(fs_rule);
4605 state = 0;
4606 break;
4607
4608 default:
4609 state = 0;
4610 }
4611 }
4612 }
4613 spin_lock_irq(mlx4_tlock(dev));
4614 }
4615 spin_unlock_irq(mlx4_tlock(dev));
4616}
4617
c82e9aa0
EC		 4618static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
4619{
4620 struct mlx4_priv *priv = mlx4_priv(dev);
4621 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4622 struct list_head *eq_list =
4623 &tracker->slave_list[slave].res_list[RES_EQ];
4624 struct res_eq *eq;
4625 struct res_eq *tmp;
4626 int err;
4627 int state;
4628 LIST_HEAD(tlist);
4629 int eqn;
4630 struct mlx4_cmd_mailbox *mailbox;
4631
4632 err = move_all_busy(dev, slave, RES_EQ);
4633 if (err)
1a91de28
JP		 4634 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
4635 slave);
c82e9aa0
EC		 4636
4637 spin_lock_irq(mlx4_tlock(dev));
4638 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
4639 spin_unlock_irq(mlx4_tlock(dev));
4640 if (eq->com.owner == slave) {
4641 eqn = eq->com.res_id;
4642 state = eq->com.from_state;
4643 while (state != 0) {
4644 switch (state) {
4645 case RES_EQ_RESERVED:
4646 spin_lock_irq(mlx4_tlock(dev));
4af1c048
HHZ		 4647 rb_erase(&eq->com.node,
4648 &tracker->res_tree[RES_EQ]);
c82e9aa0
EC		 4649 list_del(&eq->com.list);
4650 spin_unlock_irq(mlx4_tlock(dev));
4651 kfree(eq);
4652 state = 0;
4653 break;
4654
4655 case RES_EQ_HW:
4656 mailbox = mlx4_alloc_cmd_mailbox(dev);
4657 if (IS_ERR(mailbox)) {
4658 cond_resched();
4659 continue;
4660 }
4661 err = mlx4_cmd_box(dev, slave, 0,
4662 eqn & 0xff, 0,
4663 MLX4_CMD_HW2SW_EQ,
4664 MLX4_CMD_TIME_CLASS_A,
4665 MLX4_CMD_NATIVE);
eb71d0d6 4666 if (err)
1a91de28
JP		 4667 mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
4668 slave, eqn);
c82e9aa0 4669 mlx4_free_cmd_mailbox(dev, mailbox);
eb71d0d6
JM		 4670 atomic_dec(&eq->mtt->ref_count);
4671 state = RES_EQ_RESERVED;
c82e9aa0
EC		 4672 break;
4673
4674 default:
4675 state = 0;
4676 }
4677 }
4678 }
4679 spin_lock_irq(mlx4_tlock(dev));
4680 }
4681 spin_unlock_irq(mlx4_tlock(dev));
4682}
4683
ba062d52
JM		 4684static void rem_slave_counters(struct mlx4_dev *dev, int slave)
4685{
4686 struct mlx4_priv *priv = mlx4_priv(dev);
4687 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4688 struct list_head *counter_list =
4689 &tracker->slave_list[slave].res_list[RES_COUNTER];
4690 struct res_counter *counter;
4691 struct res_counter *tmp;
4692 int err;
4693 int index;
4694
4695 err = move_all_busy(dev, slave, RES_COUNTER);
4696 if (err)
1a91de28
JP		 4697 mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
4698 slave);
ba062d52
JM		 4699
4700 spin_lock_irq(mlx4_tlock(dev));
4701 list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
4702 if (counter->com.owner == slave) {
4703 index = counter->com.res_id;
4af1c048
HHZ		 4704 rb_erase(&counter->com.node,
4705 &tracker->res_tree[RES_COUNTER]);
ba062d52
JM		 4706 list_del(&counter->com.list);
4707 kfree(counter);
4708 __mlx4_counter_free(dev, index);
146f3ef4 4709 mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
ba062d52
JM		 4710 }
4711 }
4712 spin_unlock_irq(mlx4_tlock(dev));
4713}
4714
4715static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
4716{
4717 struct mlx4_priv *priv = mlx4_priv(dev);
4718 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4719 struct list_head *xrcdn_list =
4720 &tracker->slave_list[slave].res_list[RES_XRCD];
4721 struct res_xrcdn *xrcd;
4722 struct res_xrcdn *tmp;
4723 int err;
4724 int xrcdn;
4725
4726 err = move_all_busy(dev, slave, RES_XRCD);
4727 if (err)
1a91de28
JP		 4728 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
4729 slave);
ba062d52
JM		 4730
4731 spin_lock_irq(mlx4_tlock(dev));
4732 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
4733 if (xrcd->com.owner == slave) {
4734 xrcdn = xrcd->com.res_id;
4af1c048 4735 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
ba062d52
JM		 4736 list_del(&xrcd->com.list);
4737 kfree(xrcd);
4738 __mlx4_xrcd_free(dev, xrcdn);
4739 }
4740 }
4741 spin_unlock_irq(mlx4_tlock(dev));
4742}
4743
c82e9aa0
EC		 4744void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
4745{
4746 struct mlx4_priv *priv = mlx4_priv(dev);
111c6094 4747 mlx4_reset_roce_gids(dev, slave);
c82e9aa0 4748 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4874080d 4749 rem_slave_vlans(dev, slave);
c82e9aa0 4750 rem_slave_macs(dev, slave);
80cb0021 4751 rem_slave_fs_rule(dev, slave);
c82e9aa0
EC		 4752 rem_slave_qps(dev, slave);
4753 rem_slave_srqs(dev, slave);
4754 rem_slave_cqs(dev, slave);
4755 rem_slave_mrs(dev, slave);
4756 rem_slave_eqs(dev, slave);
4757 rem_slave_mtts(dev, slave);
ba062d52
JM		 4758 rem_slave_counters(dev, slave);
4759 rem_slave_xrcdns(dev, slave);
c82e9aa0
EC		 4760 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4761}
b01978ca
JM		 4762
4763void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
4764{
4765 struct mlx4_vf_immed_vlan_work *work =
4766 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
4767 struct mlx4_cmd_mailbox *mailbox;
4768 struct mlx4_update_qp_context *upd_context;
4769 struct mlx4_dev *dev = &work->priv->dev;
4770 struct mlx4_resource_tracker *tracker =
4771 &work->priv->mfunc.master.res_tracker;
4772 struct list_head *qp_list =
4773 &tracker->slave_list[work->slave].res_list[RES_QP];
4774 struct res_qp *qp;
4775 struct res_qp *tmp;
f0f829bf
RE		 4776 u64 qp_path_mask_vlan_ctrl =
4777 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
b01978ca
JM		 4778 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
4779 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
4780 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
4781 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
f0f829bf
RE		 4782 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
4783
4784 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
4785 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
4786 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
4787 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
4788 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
4789 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
b01978ca
JM		 4790 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
4791
4792 int err;
4793 int port, errors = 0;
4794 u8 vlan_control;
4795
4796 if (mlx4_is_slave(dev)) {
4797 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
4798 work->slave);
4799 goto out;
4800 }
4801
4802 mailbox = mlx4_alloc_cmd_mailbox(dev);
4803 if (IS_ERR(mailbox))
4804 goto out;
0a6eac24
RE		 4805 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
4806 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4807 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
4808 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
4809 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4810 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
4811 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4812 else if (!work->vlan_id)
b01978ca
JM		 4813 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4814 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4815 else
4816 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4817 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4818 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
4819
4820 upd_context = mailbox->buf;
f0f829bf 4821 upd_context->qp_mask = cpu_to_be64(MLX4_UPD_QP_MASK_VSD);
b01978ca
JM		 4822
4823 spin_lock_irq(mlx4_tlock(dev));
4824 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4825 spin_unlock_irq(mlx4_tlock(dev));
4826 if (qp->com.owner == work->slave) {
4827 if (qp->com.from_state != RES_QP_HW ||
4828 !qp->sched_queue || /* no INIT2RTR trans yet */
4829 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
4830 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
4831 spin_lock_irq(mlx4_tlock(dev));
4832 continue;
4833 }
4834 port = (qp->sched_queue >> 6 & 1) + 1;
4835 if (port != work->port) {
4836 spin_lock_irq(mlx4_tlock(dev));
4837 continue;
4838 }
f0f829bf
RE		 4839 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
4840 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
4841 else
4842 upd_context->primary_addr_path_mask =
4843 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
4844 if (work->vlan_id == MLX4_VGT) {
4845 upd_context->qp_context.param3 = qp->param3;
4846 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
4847 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
4848 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
4849 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
4850 upd_context->qp_context.pri_path.feup = qp->feup;
4851 upd_context->qp_context.pri_path.sched_queue =
4852 qp->sched_queue;
4853 } else {
4854 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
4855 upd_context->qp_context.pri_path.vlan_control = vlan_control;
4856 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
4857 upd_context->qp_context.pri_path.fvl_rx =
4858 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
4859 upd_context->qp_context.pri_path.fl =
4860 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
4861 upd_context->qp_context.pri_path.feup =
4862 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
4863 upd_context->qp_context.pri_path.sched_queue =
4864 qp->sched_queue & 0xC7;
4865 upd_context->qp_context.pri_path.sched_queue |=
4866 ((work->qos & 0x7) << 3);
4867 }
b01978ca
JM		 4868
4869 err = mlx4_cmd(dev, mailbox->dma,
4870 qp->local_qpn & 0xffffff,
4871 0, MLX4_CMD_UPDATE_QP,
4872 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
4873 if (err) {
1a91de28
JP		 4874 mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
4875 work->slave, port, qp->local_qpn, err);
b01978ca
JM		 4876 errors++;
4877 }
4878 }
4879 spin_lock_irq(mlx4_tlock(dev));
4880 }
4881 spin_unlock_irq(mlx4_tlock(dev));
4882 mlx4_free_cmd_mailbox(dev, mailbox);
4883
4884 if (errors)
4885 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
4886 errors, work->slave, work->port);
4887
4888 /* unregister previous vlan_id if needed and we had no errors
4889 * while updating the QPs
4890 */
4891 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
4892 NO_INDX != work->orig_vlan_ix)
4893 __mlx4_unregister_vlan(&work->priv->dev, work->port,
2009d005 4894 work->orig_vlan_id);
b01978ca
JM		 4895out:
4896 kfree(work);
4897 return;
4898}
Linux kernel - Deliverables
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