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Merge remote-tracking branch 'mmc-uh/next'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
34
35static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
37{
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45 "%d.%d.%d",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
49}
50
665bc539
GP		 51struct ptys2ethtool_config {
52 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 54 u32 speed;
f62b8bb8
AV		 55};
56
665bc539
GP		 57static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
58
59#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
60 ({ \
61 struct ptys2ethtool_config *cfg; \
62 const unsigned int modes[] = { __VA_ARGS__ }; \
63 unsigned int i; \
64 cfg = &ptys2ethtool_table[reg_]; \
65 cfg->speed = speed_; \
66 bitmap_zero(cfg->supported, \
67 __ETHTOOL_LINK_MODE_MASK_NBITS); \
68 bitmap_zero(cfg->advertised, \
69 __ETHTOOL_LINK_MODE_MASK_NBITS); \
70 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
71 __set_bit(modes[i], cfg->supported); \
72 __set_bit(modes[i], cfg->advertised); \
73 } \
74 })
75
76void mlx5e_build_ptys2ethtool_map(void)
77{
78 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
128}
129
cf678570
GP		 130static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
131{
132 struct mlx5_core_dev *mdev = priv->mdev;
133 u8 pfc_en_tx;
134 u8 pfc_en_rx;
135 int err;
136
137 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
138
139 return err ? 0 : pfc_en_tx | pfc_en_rx;
140}
141
e989d5a5
GP		 142static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
143{
144 struct mlx5_core_dev *mdev = priv->mdev;
145 u32 rx_pause;
146 u32 tx_pause;
147 int err;
148
149 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
150
151 return err ? false : rx_pause | tx_pause;
152}
153
593cf338 154#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
9218b44d
GP		 155#define MLX5E_NUM_RQ_STATS(priv) \
156 (NUM_RQ_STATS * priv->params.num_channels * \
157 test_bit(MLX5E_STATE_OPENED, &priv->state))
158#define MLX5E_NUM_SQ_STATS(priv) \
159 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
160 test_bit(MLX5E_STATE_OPENED, &priv->state))
ed80ec4c 161#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 162 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
163 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 164
f62b8bb8
AV		 165static int mlx5e_get_sset_count(struct net_device *dev, int sset)
166{
167 struct mlx5e_priv *priv = netdev_priv(dev);
168
169 switch (sset) {
170 case ETH_SS_STATS:
9218b44d 171 return NUM_SW_COUNTERS +
593cf338 172 MLX5E_NUM_Q_CNTRS(priv) +
9218b44d
GP		 173 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
174 MLX5E_NUM_RQ_STATS(priv) +
cf678570
GP		 175 MLX5E_NUM_SQ_STATS(priv) +
176 MLX5E_NUM_PFC_COUNTERS(priv);
4e59e288
GP		 177 case ETH_SS_PRIV_FLAGS:
178 return ARRAY_SIZE(mlx5e_priv_flags);
f62b8bb8
AV		 179 /* fallthrough */
180 default:
181 return -EOPNOTSUPP;
182 }
183}
184
9218b44d
GP		 185static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
186{
cf678570
GP		 187 int i, j, tc, prio, idx = 0;
188 unsigned long pfc_combined;
9218b44d
GP		 189
190 /* SW counters */
191 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 192 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 193
194 /* Q counters */
195 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 196 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 197
198 /* VPORT counters */
199 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
200 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 201 vport_stats_desc[i].format);
9218b44d
GP		 202
203 /* PPORT counters */
204 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
205 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 206 pport_802_3_stats_desc[i].format);
9218b44d
GP		 207
208 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
209 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 210 pport_2863_stats_desc[i].format);
9218b44d
GP		 211
212 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
213 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 214 pport_2819_stats_desc[i].format);
9218b44d 215
cf678570
GP		 216 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
217 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 218 sprintf(data + (idx++) * ETH_GSTRING_LEN,
219 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 220 }
221
222 pfc_combined = mlx5e_query_pfc_combined(priv);
223 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
224 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 225 char pfc_string[ETH_GSTRING_LEN];
226
227 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 228 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 229 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
230 }
231 }
232
233 if (mlx5e_query_global_pause_combined(priv)) {
234 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
235 sprintf(data + (idx++) * ETH_GSTRING_LEN,
236 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 237 }
238 }
239
9218b44d
GP		 240 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
241 return;
242
243 /* per channel counters */
244 for (i = 0; i < priv->params.num_channels; i++)
245 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 246 sprintf(data + (idx++) * ETH_GSTRING_LEN,
247 rq_stats_desc[j].format, i);
9218b44d
GP		 248
249 for (tc = 0; tc < priv->params.num_tc; tc++)
250 for (i = 0; i < priv->params.num_channels; i++)
251 for (j = 0; j < NUM_SQ_STATS; j++)
252 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1
GP		 253 sq_stats_desc[j].format,
254 priv->channeltc_to_txq_map[i][tc]);
9218b44d
GP		 255}
256
f62b8bb8
AV		 257static void mlx5e_get_strings(struct net_device *dev,
258 uint32_t stringset, uint8_t *data)
259{
f62b8bb8 260 struct mlx5e_priv *priv = netdev_priv(dev);
4e59e288 261 int i;
f62b8bb8
AV		 262
263 switch (stringset) {
264 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 265 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
266 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 267 break;
268
269 case ETH_SS_TEST:
270 break;
271
272 case ETH_SS_STATS:
9218b44d 273 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 274 break;
275 }
276}
277
278static void mlx5e_get_ethtool_stats(struct net_device *dev,
279 struct ethtool_stats *stats, u64 *data)
280{
281 struct mlx5e_priv *priv = netdev_priv(dev);
cf678570
GP		 282 int i, j, tc, prio, idx = 0;
283 unsigned long pfc_combined;
f62b8bb8
AV		 284
285 if (!data)
286 return;
287
288 mutex_lock(&priv->state_lock);
289 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
290 mlx5e_update_stats(priv);
291 mutex_unlock(&priv->state_lock);
292
9218b44d
GP		 293 for (i = 0; i < NUM_SW_COUNTERS; i++)
294 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
295 sw_stats_desc, i);
f62b8bb8 296
593cf338 297 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 298 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
299 q_stats_desc, i);
300
301 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
302 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
303 vport_stats_desc, i);
593cf338 304
9218b44d
GP		 305 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
306 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
307 pport_802_3_stats_desc, i);
308
309 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
310 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
311 pport_2863_stats_desc, i);
312
313 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
314 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
315 pport_2819_stats_desc, i);
316
cf678570
GP		 317 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
318 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
319 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
320 pport_per_prio_traffic_stats_desc, i);
321 }
322
323 pfc_combined = mlx5e_query_pfc_combined(priv);
324 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
325 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
326 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
327 pport_per_prio_pfc_stats_desc, i);
328 }
329 }
330
e989d5a5
GP		 331 if (mlx5e_query_global_pause_combined(priv)) {
332 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
333 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 334 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 335 }
336 }
337
9218b44d
GP		 338 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
339 return;
efea389d 340
f62b8bb8
AV		 341 /* per channel counters */
342 for (i = 0; i < priv->params.num_channels; i++)
343 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d
GP		 344 data[idx++] =
345 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
346 rq_stats_desc, j);
f62b8bb8 347
3b619524
TT		 348 for (tc = 0; tc < priv->params.num_tc; tc++)
349 for (i = 0; i < priv->params.num_channels; i++)
f62b8bb8 350 for (j = 0; j < NUM_SQ_STATS; j++)
9218b44d
GP		 351 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
352 sq_stats_desc, j);
f62b8bb8
AV		 353}
354
cc8e9ebf
EBE		 355static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
356 int num_wqe)
357{
358 int packets_per_wqe;
359 int stride_size;
360 int num_strides;
361 int wqe_size;
362
363 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
364 return num_wqe;
365
366 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
367 num_strides = 1 << priv->params.mpwqe_log_num_strides;
368 wqe_size = stride_size * num_strides;
369
370 packets_per_wqe = wqe_size /
371 ALIGN(ETH_DATA_LEN, stride_size);
372 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
373}
374
375static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
376 int num_packets)
377{
378 int packets_per_wqe;
379 int stride_size;
380 int num_strides;
381 int wqe_size;
382 int num_wqes;
383
384 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
385 return num_packets;
386
387 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
388 num_strides = 1 << priv->params.mpwqe_log_num_strides;
389 wqe_size = stride_size * num_strides;
390
391 num_packets = (1 << order_base_2(num_packets));
392
393 packets_per_wqe = wqe_size /
394 ALIGN(ETH_DATA_LEN, stride_size);
395 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
396 return 1 << (order_base_2(num_wqes));
397}
398
f62b8bb8
AV		 399static void mlx5e_get_ringparam(struct net_device *dev,
400 struct ethtool_ringparam *param)
401{
402 struct mlx5e_priv *priv = netdev_priv(dev);
461017cb 403 int rq_wq_type = priv->params.rq_wq_type;
f62b8bb8 404
cc8e9ebf
EBE		 405 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
406 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 407 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf
EBE		 408 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
409 1 << priv->params.log_rq_size);
f62b8bb8
AV		 410 param->tx_pending = 1 << priv->params.log_sq_size;
411}
412
413static int mlx5e_set_ringparam(struct net_device *dev,
414 struct ethtool_ringparam *param)
415{
416 struct mlx5e_priv *priv = netdev_priv(dev);
98e81b0a 417 bool was_opened;
461017cb 418 int rq_wq_type = priv->params.rq_wq_type;
cc8e9ebf
EBE		 419 u32 rx_pending_wqes;
420 u32 min_rq_size;
421 u32 max_rq_size;
f62b8bb8
AV		 422 u16 min_rx_wqes;
423 u8 log_rq_size;
424 u8 log_sq_size;
fe4c988b 425 u32 num_mtts;
f62b8bb8
AV		 426 int err = 0;
427
428 if (param->rx_jumbo_pending) {
429 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
430 __func__);
431 return -EINVAL;
432 }
433 if (param->rx_mini_pending) {
434 netdev_info(dev, "%s: rx_mini_pending not supported\n",
435 __func__);
436 return -EINVAL;
437 }
cc8e9ebf
EBE		 438
439 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
440 1 << mlx5_min_log_rq_size(rq_wq_type));
441 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
442 1 << mlx5_max_log_rq_size(rq_wq_type));
443 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
444 param->rx_pending);
445
446 if (param->rx_pending < min_rq_size) {
f62b8bb8
AV		 447 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
448 __func__, param->rx_pending,
cc8e9ebf 449 min_rq_size);
f62b8bb8
AV		 450 return -EINVAL;
451 }
cc8e9ebf 452 if (param->rx_pending > max_rq_size) {
f62b8bb8
AV		 453 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
454 __func__, param->rx_pending,
cc8e9ebf 455 max_rq_size);
f62b8bb8
AV		 456 return -EINVAL;
457 }
fe4c988b 458
cc8e9ebf
EBE		 459 num_mtts = MLX5E_REQUIRED_MTTS(priv->params.num_channels,
460 rx_pending_wqes);
fe4c988b
SM		 461 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
462 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
463 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
464 __func__, param->rx_pending);
465 return -EINVAL;
466 }
467
f62b8bb8
AV		 468 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
469 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
470 __func__, param->tx_pending,
471 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
472 return -EINVAL;
473 }
474 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
475 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
476 __func__, param->tx_pending,
477 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
478 return -EINVAL;
479 }
480
cc8e9ebf 481 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 482 log_sq_size = order_base_2(param->tx_pending);
cc8e9ebf 483 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
f62b8bb8
AV		 484
485 if (log_rq_size == priv->params.log_rq_size &&
486 log_sq_size == priv->params.log_sq_size &&
487 min_rx_wqes == priv->params.min_rx_wqes)
488 return 0;
489
490 mutex_lock(&priv->state_lock);
98e81b0a
AS		 491
492 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
493 if (was_opened)
494 mlx5e_close_locked(dev);
495
496 priv->params.log_rq_size = log_rq_size;
497 priv->params.log_sq_size = log_sq_size;
498 priv->params.min_rx_wqes = min_rx_wqes;
499
500 if (was_opened)
501 err = mlx5e_open_locked(dev);
502
f62b8bb8
AV		 503 mutex_unlock(&priv->state_lock);
504
505 return err;
506}
507
508static void mlx5e_get_channels(struct net_device *dev,
509 struct ethtool_channels *ch)
510{
511 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 512
3435ab59 513 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8
AV		 514 ch->combined_count = priv->params.num_channels;
515}
516
517static int mlx5e_set_channels(struct net_device *dev,
518 struct ethtool_channels *ch)
519{
520 struct mlx5e_priv *priv = netdev_priv(dev);
3435ab59 521 int ncv = mlx5e_get_max_num_channels(priv->mdev);
f62b8bb8 522 unsigned int count = ch->combined_count;
45bf454a 523 bool arfs_enabled;
98e81b0a 524 bool was_opened;
fe4c988b 525 u32 num_mtts;
f62b8bb8
AV		 526 int err = 0;
527
528 if (!count) {
529 netdev_info(dev, "%s: combined_count=0 not supported\n",
530 __func__);
531 return -EINVAL;
532 }
533 if (ch->rx_count || ch->tx_count) {
534 netdev_info(dev, "%s: separate rx/tx count not supported\n",
535 __func__);
536 return -EINVAL;
537 }
538 if (count > ncv) {
539 netdev_info(dev, "%s: count (%d) > max (%d)\n",
540 __func__, count, ncv);
541 return -EINVAL;
542 }
543
fe4c988b
SM		 544 num_mtts = MLX5E_REQUIRED_MTTS(count, BIT(priv->params.log_rq_size));
545 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
546 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
547 netdev_info(dev, "%s: rx count (%d) request can't be satisfied, try to reduce.\n",
548 __func__, count);
549 return -EINVAL;
550 }
551
f62b8bb8
AV		 552 if (priv->params.num_channels == count)
553 return 0;
554
555 mutex_lock(&priv->state_lock);
98e81b0a
AS		 556
557 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
558 if (was_opened)
559 mlx5e_close_locked(dev);
560
45bf454a
MG		 561 arfs_enabled = dev->features & NETIF_F_NTUPLE;
562 if (arfs_enabled)
563 mlx5e_arfs_disable(priv);
564
98e81b0a 565 priv->params.num_channels = count;
d8c9660d 566 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
85082dba 567 MLX5E_INDIR_RQT_SIZE, count);
98e81b0a
AS		 568
569 if (was_opened)
570 err = mlx5e_open_locked(dev);
45bf454a
MG		 571 if (err)
572 goto out;
573
574 if (arfs_enabled) {
575 err = mlx5e_arfs_enable(priv);
576 if (err)
577 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
578 __func__, err);
579 }
98e81b0a 580
45bf454a 581out:
f62b8bb8
AV		 582 mutex_unlock(&priv->state_lock);
583
584 return err;
585}
586
587static int mlx5e_get_coalesce(struct net_device *netdev,
588 struct ethtool_coalesce *coal)
589{
590 struct mlx5e_priv *priv = netdev_priv(netdev);
591
7524a5d8
GP		 592 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
593 return -ENOTSUPP;
594
9908aa29
TT		 595 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation.usec;
596 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
597 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation.usec;
598 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
cb3c7fd4 599 coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
f62b8bb8
AV		 600
601 return 0;
602}
603
604static int mlx5e_set_coalesce(struct net_device *netdev,
605 struct ethtool_coalesce *coal)
606{
607 struct mlx5e_priv *priv = netdev_priv(netdev);
608 struct mlx5_core_dev *mdev = priv->mdev;
609 struct mlx5e_channel *c;
cb3c7fd4
GR		 610 bool restart =
611 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
612 bool was_opened;
613 int err = 0;
f62b8bb8
AV		 614 int tc;
615 int i;
616
7524a5d8
GP		 617 if (!MLX5_CAP_GEN(mdev, cq_moderation))
618 return -ENOTSUPP;
619
2fcb92fb 620 mutex_lock(&priv->state_lock);
9908aa29 621
cb3c7fd4
GR		 622 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
623 if (was_opened && restart) {
624 mlx5e_close_locked(netdev);
625 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
626 }
627
9908aa29
TT		 628 priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
629 priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
630 priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
631 priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
f62b8bb8 632
cb3c7fd4 633 if (!was_opened || restart)
2fcb92fb
GP		 634 goto out;
635
f62b8bb8
AV		 636 for (i = 0; i < priv->params.num_channels; ++i) {
637 c = priv->channel[i];
638
639 for (tc = 0; tc < c->num_tc; tc++) {
640 mlx5_core_modify_cq_moderation(mdev,
641 &c->sq[tc].cq.mcq,
642 coal->tx_coalesce_usecs,
643 coal->tx_max_coalesced_frames);
644 }
645
646 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
647 coal->rx_coalesce_usecs,
648 coal->rx_max_coalesced_frames);
649 }
650
2fcb92fb 651out:
cb3c7fd4
GR		 652 if (was_opened && restart)
653 err = mlx5e_open_locked(netdev);
654
2fcb92fb 655 mutex_unlock(&priv->state_lock);
cb3c7fd4 656 return err;
f62b8bb8
AV		 657}
658
665bc539
GP		 659static void ptys2ethtool_supported_link(unsigned long *supported_modes,
660 u32 eth_proto_cap)
f62b8bb8 661{
7abc2110 662 unsigned long proto_cap = eth_proto_cap;
665bc539 663 int proto;
f62b8bb8 664
7abc2110 665 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 666 bitmap_or(supported_modes, supported_modes,
667 ptys2ethtool_table[proto].supported,
668 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 669}
670
665bc539
GP		 671static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
672 u32 eth_proto_cap)
f62b8bb8 673{
7abc2110 674 unsigned long proto_cap = eth_proto_cap;
665bc539 675 int proto;
f62b8bb8 676
7abc2110 677 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 678 bitmap_or(advertising_modes, advertising_modes,
679 ptys2ethtool_table[proto].advertised,
680 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 681}
682
665bc539
GP		 683static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
684 u32 eth_proto_cap)
f62b8bb8
AV		 685{
686 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
687 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
688 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
689 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
690 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
691 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
665bc539 692 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
f62b8bb8
AV		 693 }
694
695 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
696 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
697 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
698 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
699 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
665bc539 700 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
f62b8bb8 701 }
f62b8bb8
AV		 702}
703
b797a684
SM		 704int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
705{
706 u32 max_speed = 0;
707 u32 proto_cap;
708 int err;
709 int i;
710
711 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
712 if (err)
713 return err;
714
715 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
716 if (proto_cap & MLX5E_PROT_MASK(i))
717 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
718
719 *speed = max_speed;
720 return 0;
721}
722
f62b8bb8
AV		 723static void get_speed_duplex(struct net_device *netdev,
724 u32 eth_proto_oper,
665bc539 725 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 726{
727 int i;
728 u32 speed = SPEED_UNKNOWN;
729 u8 duplex = DUPLEX_UNKNOWN;
730
731 if (!netif_carrier_ok(netdev))
732 goto out;
733
734 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
735 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
736 speed = ptys2ethtool_table[i].speed;
737 duplex = DUPLEX_FULL;
738 break;
739 }
740 }
741out:
665bc539
GP		 742 link_ksettings->base.speed = speed;
743 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 744}
745
665bc539
GP		 746static void get_supported(u32 eth_proto_cap,
747 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 748{
665bc539
GP		 749 unsigned long *supported = link_ksettings->link_modes.supported;
750
751 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
752 ptys2ethtool_supported_link(supported, eth_proto_cap);
753 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
754 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
f62b8bb8
AV		 755}
756
757static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 758 u8 rx_pause,
759 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 760{
665bc539
GP		 761 unsigned long *advertising = link_ksettings->link_modes.advertising;
762
763 ptys2ethtool_adver_link(advertising, eth_proto_cap);
764 if (tx_pause)
765 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
766 if (tx_pause ^ rx_pause)
767 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 768}
769
770static u8 get_connector_port(u32 eth_proto)
771{
772 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
773 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
774 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
775 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
776 return PORT_FIBRE;
777 }
778
779 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
780 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
781 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
782 return PORT_DA;
783 }
784
785 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
786 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
787 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
788 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
789 return PORT_NONE;
790 }
791
792 return PORT_OTHER;
793}
794
665bc539
GP		 795static void get_lp_advertising(u32 eth_proto_lp,
796 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 797{
665bc539
GP		 798 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
799
800 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 801}
802
665bc539
GP		 803static int mlx5e_get_link_ksettings(struct net_device *netdev,
804 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 805{
806 struct mlx5e_priv *priv = netdev_priv(netdev);
807 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 808 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
f62b8bb8
AV		 809 u32 eth_proto_cap;
810 u32 eth_proto_admin;
811 u32 eth_proto_lp;
812 u32 eth_proto_oper;
52244d96
GP		 813 u8 an_disable_admin;
814 u8 an_status;
f62b8bb8
AV		 815 int err;
816
a05bdefa 817 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 818 if (err) {
819 netdev_err(netdev, "%s: query port ptys failed: %d\n",
820 __func__, err);
821 goto err_query_ptys;
822 }
823
52244d96
GP		 824 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
825 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
826 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
827 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
828 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
829 an_status = MLX5_GET(ptys_reg, out, an_status);
f62b8bb8 830
665bc539
GP		 831 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
832 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 833
665bc539
GP		 834 get_supported(eth_proto_cap, link_ksettings);
835 get_advertising(eth_proto_admin, 0, 0, link_ksettings);
836 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 837
838 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
839
665bc539
GP		 840 link_ksettings->base.port = get_connector_port(eth_proto_oper);
841 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 842
52244d96
GP		 843 if (an_status == MLX5_AN_COMPLETE)
844 ethtool_link_ksettings_add_link_mode(link_ksettings,
845 lp_advertising, Autoneg);
846
847 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
848 AUTONEG_ENABLE;
849 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
850 Autoneg);
851 if (!an_disable_admin)
852 ethtool_link_ksettings_add_link_mode(link_ksettings,
853 advertising, Autoneg);
854
f62b8bb8
AV		 855err_query_ptys:
856 return err;
857}
858
665bc539 859static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 860{
861 u32 i, ptys_modes = 0;
862
863 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 864 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
865 link_modes,
866 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 867 ptys_modes |= MLX5E_PROT_MASK(i);
868 }
869
870 return ptys_modes;
871}
872
873static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
874{
875 u32 i, speed_links = 0;
876
877 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
878 if (ptys2ethtool_table[i].speed == speed)
879 speed_links |= MLX5E_PROT_MASK(i);
880 }
881
882 return speed_links;
883}
884
665bc539
GP		 885static int mlx5e_set_link_ksettings(struct net_device *netdev,
886 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 887{
888 struct mlx5e_priv *priv = netdev_priv(netdev);
889 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 890 u32 eth_proto_cap, eth_proto_admin;
891 bool an_changes = false;
892 u8 an_disable_admin;
893 u8 an_disable_cap;
894 bool an_disable;
f62b8bb8 895 u32 link_modes;
52244d96 896 u8 an_status;
f62b8bb8 897 u32 speed;
f62b8bb8
AV		 898 int err;
899
665bc539 900 speed = link_ksettings->base.speed;
f62b8bb8 901
665bc539
GP		 902 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
903 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 904 mlx5e_ethtool2ptys_speed_link(speed);
905
906 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
907 if (err) {
908 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
909 __func__, err);
910 goto out;
911 }
912
913 link_modes = link_modes & eth_proto_cap;
914 if (!link_modes) {
915 netdev_err(netdev, "%s: Not supported link mode(s) requested",
916 __func__);
917 err = -EINVAL;
918 goto out;
919 }
920
921 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
922 if (err) {
923 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
924 __func__, err);
925 goto out;
926 }
927
52244d96
GP		 928 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
929 &an_disable_cap, &an_disable_admin);
930
931 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
932 an_changes = ((!an_disable && an_disable_admin) ||
933 (an_disable && !an_disable_admin));
934
935 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 936 goto out;
937
52244d96 938 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 939 mlx5_toggle_port_link(mdev);
f62b8bb8 940
f62b8bb8
AV		 941out:
942 return err;
943}
944
2d75b2bc
AS		 945static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
946{
947 struct mlx5e_priv *priv = netdev_priv(netdev);
948
949 return sizeof(priv->params.toeplitz_hash_key);
950}
951
952static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
953{
954 return MLX5E_INDIR_RQT_SIZE;
955}
956
2be6967c
SM		 957static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
958 u8 *hfunc)
959{
960 struct mlx5e_priv *priv = netdev_priv(netdev);
961
2d75b2bc
AS		 962 if (indir)
963 memcpy(indir, priv->params.indirection_rqt,
964 sizeof(priv->params.indirection_rqt));
965
966 if (key)
967 memcpy(key, priv->params.toeplitz_hash_key,
968 sizeof(priv->params.toeplitz_hash_key));
969
2be6967c
SM		 970 if (hfunc)
971 *hfunc = priv->params.rss_hfunc;
972
973 return 0;
974}
975
bdfc028d
TT		 976static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
977{
978 struct mlx5_core_dev *mdev = priv->mdev;
979 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
980 int i;
981
982 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
983 mlx5e_build_tir_ctx_hash(tirc, priv);
984
1da36696 985 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 986 mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
bdfc028d
TT		 987}
988
98e81b0a 989static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 990 const u8 *key, const u8 hfunc)
991{
98e81b0a 992 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d
TT		 993 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
994 void *in;
2be6967c 995
2d75b2bc
AS		 996 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
997 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 998 (hfunc != ETH_RSS_HASH_TOP))
999 return -EINVAL;
1000
bdfc028d
TT		 1001 in = mlx5_vzalloc(inlen);
1002 if (!in)
1003 return -ENOMEM;
1004
2be6967c
SM		 1005 mutex_lock(&priv->state_lock);
1006
2d75b2bc 1007 if (indir) {
398f3351 1008 u32 rqtn = priv->indir_rqt.rqtn;
1da36696 1009
2d75b2bc
AS		 1010 memcpy(priv->params.indirection_rqt, indir,
1011 sizeof(priv->params.indirection_rqt));
1da36696 1012 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
2be6967c
SM		 1013 }
1014
2d75b2bc
AS		 1015 if (key)
1016 memcpy(priv->params.toeplitz_hash_key, key,
1017 sizeof(priv->params.toeplitz_hash_key));
1018
1019 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1020 priv->params.rss_hfunc = hfunc;
1021
bdfc028d 1022 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1023
2be6967c
SM		 1024 mutex_unlock(&priv->state_lock);
1025
bdfc028d
TT		 1026 kvfree(in);
1027
1028 return 0;
2be6967c
SM		 1029}
1030
2d75b2bc
AS		 1031static int mlx5e_get_rxnfc(struct net_device *netdev,
1032 struct ethtool_rxnfc *info, u32 *rule_locs)
1033{
1034 struct mlx5e_priv *priv = netdev_priv(netdev);
1035 int err = 0;
1036
1037 switch (info->cmd) {
1038 case ETHTOOL_GRXRINGS:
1039 info->data = priv->params.num_channels;
1040 break;
f913a72a
MG		 1041 case ETHTOOL_GRXCLSRLCNT:
1042 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1043 break;
1044 case ETHTOOL_GRXCLSRULE:
1045 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1046 break;
1047 case ETHTOOL_GRXCLSRLALL:
1048 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1049 break;
2d75b2bc
AS		 1050 default:
1051 err = -EOPNOTSUPP;
1052 break;
1053 }
1054
1055 return err;
1056}
1057
58d52291
AS		 1058static int mlx5e_get_tunable(struct net_device *dev,
1059 const struct ethtool_tunable *tuna,
1060 void *data)
1061{
1062 const struct mlx5e_priv *priv = netdev_priv(dev);
1063 int err = 0;
1064
1065 switch (tuna->id) {
1066 case ETHTOOL_TX_COPYBREAK:
1067 *(u32 *)data = priv->params.tx_max_inline;
1068 break;
1069 default:
1070 err = -EINVAL;
1071 break;
1072 }
1073
1074 return err;
1075}
1076
1077static int mlx5e_set_tunable(struct net_device *dev,
1078 const struct ethtool_tunable *tuna,
1079 const void *data)
1080{
1081 struct mlx5e_priv *priv = netdev_priv(dev);
1082 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1083 bool was_opened;
58d52291
AS		 1084 u32 val;
1085 int err = 0;
1086
1087 switch (tuna->id) {
1088 case ETHTOOL_TX_COPYBREAK:
1089 val = *(u32 *)data;
1090 if (val > mlx5e_get_max_inline_cap(mdev)) {
1091 err = -EINVAL;
1092 break;
1093 }
1094
1095 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1096
1097 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1098 if (was_opened)
1099 mlx5e_close_locked(dev);
1100
1101 priv->params.tx_max_inline = val;
1102
1103 if (was_opened)
1104 err = mlx5e_open_locked(dev);
1105
58d52291
AS		 1106 mutex_unlock(&priv->state_lock);
1107 break;
1108 default:
1109 err = -EINVAL;
1110 break;
1111 }
1112
1113 return err;
1114}
1115
3c2d18ef
AS		 1116static void mlx5e_get_pauseparam(struct net_device *netdev,
1117 struct ethtool_pauseparam *pauseparam)
1118{
1119 struct mlx5e_priv *priv = netdev_priv(netdev);
1120 struct mlx5_core_dev *mdev = priv->mdev;
1121 int err;
1122
1123 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1124 &pauseparam->tx_pause);
1125 if (err) {
1126 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1127 __func__, err);
1128 }
1129}
1130
1131static int mlx5e_set_pauseparam(struct net_device *netdev,
1132 struct ethtool_pauseparam *pauseparam)
1133{
1134 struct mlx5e_priv *priv = netdev_priv(netdev);
1135 struct mlx5_core_dev *mdev = priv->mdev;
1136 int err;
1137
1138 if (pauseparam->autoneg)
1139 return -EINVAL;
1140
1141 err = mlx5_set_port_pause(mdev,
1142 pauseparam->rx_pause ? 1 : 0,
1143 pauseparam->tx_pause ? 1 : 0);
1144 if (err) {
1145 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1146 __func__, err);
1147 }
1148
1149 return err;
1150}
1151
ef9814de
EBE		 1152static int mlx5e_get_ts_info(struct net_device *dev,
1153 struct ethtool_ts_info *info)
1154{
1155 struct mlx5e_priv *priv = netdev_priv(dev);
1156 int ret;
1157
1158 ret = ethtool_op_get_ts_info(dev, info);
1159 if (ret)
1160 return ret;
1161
3d8c38af
EBE		 1162 info->phc_index = priv->tstamp.ptp ?
1163 ptp_clock_index(priv->tstamp.ptp) : -1;
ef9814de
EBE		 1164
1165 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1166 return 0;
1167
1168 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1169 SOF_TIMESTAMPING_RX_HARDWARE |
1170 SOF_TIMESTAMPING_RAW_HARDWARE;
1171
1172 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1173 (BIT(1) << HWTSTAMP_TX_ON);
1174
1175 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1176 (BIT(1) << HWTSTAMP_FILTER_ALL);
1177
1178 return 0;
1179}
1180
928cfe87
TT		 1181static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1182{
1183 __u32 ret = 0;
1184
1185 if (MLX5_CAP_GEN(mdev, wol_g))
1186 ret |= WAKE_MAGIC;
1187
1188 if (MLX5_CAP_GEN(mdev, wol_s))
1189 ret |= WAKE_MAGICSECURE;
1190
1191 if (MLX5_CAP_GEN(mdev, wol_a))
1192 ret |= WAKE_ARP;
1193
1194 if (MLX5_CAP_GEN(mdev, wol_b))
1195 ret |= WAKE_BCAST;
1196
1197 if (MLX5_CAP_GEN(mdev, wol_m))
1198 ret |= WAKE_MCAST;
1199
1200 if (MLX5_CAP_GEN(mdev, wol_u))
1201 ret |= WAKE_UCAST;
1202
1203 if (MLX5_CAP_GEN(mdev, wol_p))
1204 ret |= WAKE_PHY;
1205
1206 return ret;
1207}
1208
1209static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1210{
1211 __u32 ret = 0;
1212
1213 if (mode & MLX5_WOL_MAGIC)
1214 ret |= WAKE_MAGIC;
1215
1216 if (mode & MLX5_WOL_SECURED_MAGIC)
1217 ret |= WAKE_MAGICSECURE;
1218
1219 if (mode & MLX5_WOL_ARP)
1220 ret |= WAKE_ARP;
1221
1222 if (mode & MLX5_WOL_BROADCAST)
1223 ret |= WAKE_BCAST;
1224
1225 if (mode & MLX5_WOL_MULTICAST)
1226 ret |= WAKE_MCAST;
1227
1228 if (mode & MLX5_WOL_UNICAST)
1229 ret |= WAKE_UCAST;
1230
1231 if (mode & MLX5_WOL_PHY_ACTIVITY)
1232 ret |= WAKE_PHY;
1233
1234 return ret;
1235}
1236
1237static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1238{
1239 u8 ret = 0;
1240
1241 if (mode & WAKE_MAGIC)
1242 ret |= MLX5_WOL_MAGIC;
1243
1244 if (mode & WAKE_MAGICSECURE)
1245 ret |= MLX5_WOL_SECURED_MAGIC;
1246
1247 if (mode & WAKE_ARP)
1248 ret |= MLX5_WOL_ARP;
1249
1250 if (mode & WAKE_BCAST)
1251 ret |= MLX5_WOL_BROADCAST;
1252
1253 if (mode & WAKE_MCAST)
1254 ret |= MLX5_WOL_MULTICAST;
1255
1256 if (mode & WAKE_UCAST)
1257 ret |= MLX5_WOL_UNICAST;
1258
1259 if (mode & WAKE_PHY)
1260 ret |= MLX5_WOL_PHY_ACTIVITY;
1261
1262 return ret;
1263}
1264
1265static void mlx5e_get_wol(struct net_device *netdev,
1266 struct ethtool_wolinfo *wol)
1267{
1268 struct mlx5e_priv *priv = netdev_priv(netdev);
1269 struct mlx5_core_dev *mdev = priv->mdev;
1270 u8 mlx5_wol_mode;
1271 int err;
1272
1273 memset(wol, 0, sizeof(*wol));
1274
1275 wol->supported = mlx5e_get_wol_supported(mdev);
1276 if (!wol->supported)
1277 return;
1278
1279 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1280 if (err)
1281 return;
1282
1283 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1284}
1285
1286static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1287{
1288 struct mlx5e_priv *priv = netdev_priv(netdev);
1289 struct mlx5_core_dev *mdev = priv->mdev;
1290 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1291 u32 mlx5_wol_mode;
1292
1293 if (!wol_supported)
1294 return -ENOTSUPP;
1295
1296 if (wol->wolopts & ~wol_supported)
1297 return -EINVAL;
1298
1299 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1300
1301 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1302}
1303
da54d24e
GP		 1304static int mlx5e_set_phys_id(struct net_device *dev,
1305 enum ethtool_phys_id_state state)
1306{
1307 struct mlx5e_priv *priv = netdev_priv(dev);
1308 struct mlx5_core_dev *mdev = priv->mdev;
1309 u16 beacon_duration;
1310
1311 if (!MLX5_CAP_GEN(mdev, beacon_led))
1312 return -EOPNOTSUPP;
1313
1314 switch (state) {
1315 case ETHTOOL_ID_ACTIVE:
1316 beacon_duration = MLX5_BEACON_DURATION_INF;
1317 break;
1318 case ETHTOOL_ID_INACTIVE:
1319 beacon_duration = MLX5_BEACON_DURATION_OFF;
1320 break;
1321 default:
1322 return -EOPNOTSUPP;
1323 }
1324
1325 return mlx5_set_port_beacon(mdev, beacon_duration);
1326}
1327
bb64143e
GP		 1328static int mlx5e_get_module_info(struct net_device *netdev,
1329 struct ethtool_modinfo *modinfo)
1330{
1331 struct mlx5e_priv *priv = netdev_priv(netdev);
1332 struct mlx5_core_dev *dev = priv->mdev;
1333 int size_read = 0;
1334 u8 data[4];
1335
1336 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1337 if (size_read < 2)
1338 return -EIO;
1339
1340 /* data[0] = identifier byte */
1341 switch (data[0]) {
1342 case MLX5_MODULE_ID_QSFP:
1343 modinfo->type = ETH_MODULE_SFF_8436;
1344 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1345 break;
1346 case MLX5_MODULE_ID_QSFP_PLUS:
1347 case MLX5_MODULE_ID_QSFP28:
1348 /* data[1] = revision id */
1349 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1350 modinfo->type = ETH_MODULE_SFF_8636;
1351 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1352 } else {
1353 modinfo->type = ETH_MODULE_SFF_8436;
1354 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1355 }
1356 break;
1357 case MLX5_MODULE_ID_SFP:
1358 modinfo->type = ETH_MODULE_SFF_8472;
1359 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1360 break;
1361 default:
1362 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1363 __func__, data[0]);
1364 return -EINVAL;
1365 }
1366
1367 return 0;
1368}
1369
1370static int mlx5e_get_module_eeprom(struct net_device *netdev,
1371 struct ethtool_eeprom *ee,
1372 u8 *data)
1373{
1374 struct mlx5e_priv *priv = netdev_priv(netdev);
1375 struct mlx5_core_dev *mdev = priv->mdev;
1376 int offset = ee->offset;
1377 int size_read;
1378 int i = 0;
1379
1380 if (!ee->len)
1381 return -EINVAL;
1382
1383 memset(data, 0, ee->len);
1384
1385 while (i < ee->len) {
1386 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1387 data + i);
1388
1389 if (!size_read)
1390 /* Done reading */
1391 return 0;
1392
1393 if (size_read < 0) {
1394 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1395 __func__, size_read);
1396 return 0;
1397 }
1398
1399 i += size_read;
1400 offset += size_read;
1401 }
1402
1403 return 0;
1404}
1405
4e59e288
GP		 1406typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1407
9908aa29 1408static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1409{
9908aa29
TT		 1410 struct mlx5e_priv *priv = netdev_priv(netdev);
1411 struct mlx5_core_dev *mdev = priv->mdev;
1412 bool rx_mode_changed;
1413 u8 rx_cq_period_mode;
1414 int err = 0;
1415 bool reset;
1416
1417 rx_cq_period_mode = enable ?
1418 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1419 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1420 rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1421
1422 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1423 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1424 return -ENOTSUPP;
1425
1426 if (!rx_mode_changed)
1427 return 0;
1428
1429 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1430 if (reset)
1431 mlx5e_close_locked(netdev);
1432
1433 mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1434
1435 if (reset)
1436 err = mlx5e_open_locked(netdev);
1437
1438 return err;
4e59e288
GP		 1439}
1440
1441static int mlx5e_handle_pflag(struct net_device *netdev,
1442 u32 wanted_flags,
1443 enum mlx5e_priv_flag flag,
1444 mlx5e_pflag_handler pflag_handler)
1445{
1446 struct mlx5e_priv *priv = netdev_priv(netdev);
1447 bool enable = !!(wanted_flags & flag);
1448 u32 changes = wanted_flags ^ priv->pflags;
1449 int err;
1450
1451 if (!(changes & flag))
1452 return 0;
1453
1454 err = pflag_handler(netdev, enable);
1455 if (err) {
1456 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1457 enable ? "Enable" : "Disable", flag, err);
1458 return err;
1459 }
1460
1461 MLX5E_SET_PRIV_FLAG(priv, flag, enable);
1462 return 0;
1463}
1464
1465static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1466{
1467 struct mlx5e_priv *priv = netdev_priv(netdev);
1468 int err;
1469
1470 mutex_lock(&priv->state_lock);
1471
9908aa29
TT		 1472 err = mlx5e_handle_pflag(netdev, pflags,
1473 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1474 set_pflag_rx_cqe_based_moder);
4e59e288
GP		 1475
1476 mutex_unlock(&priv->state_lock);
1477 return err ? -EINVAL : 0;
1478}
1479
1480static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1481{
1482 struct mlx5e_priv *priv = netdev_priv(netdev);
1483
1484 return priv->pflags;
1485}
1486
6dc6071c
MG		 1487static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1488{
1489 int err = 0;
1490 struct mlx5e_priv *priv = netdev_priv(dev);
1491
1492 switch (cmd->cmd) {
1493 case ETHTOOL_SRXCLSRLINS:
1494 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1495 break;
1496 case ETHTOOL_SRXCLSRLDEL:
1497 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1498 break;
1499 default:
1500 err = -EOPNOTSUPP;
1501 break;
1502 }
1503
1504 return err;
1505}
1506
f62b8bb8
AV		 1507const struct ethtool_ops mlx5e_ethtool_ops = {
1508 .get_drvinfo = mlx5e_get_drvinfo,
1509 .get_link = ethtool_op_get_link,
1510 .get_strings = mlx5e_get_strings,
1511 .get_sset_count = mlx5e_get_sset_count,
1512 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1513 .get_ringparam = mlx5e_get_ringparam,
1514 .set_ringparam = mlx5e_set_ringparam,
1515 .get_channels = mlx5e_get_channels,
1516 .set_channels = mlx5e_set_channels,
1517 .get_coalesce = mlx5e_get_coalesce,
1518 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1519 .get_link_ksettings = mlx5e_get_link_ksettings,
1520 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1521 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1522 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1523 .get_rxfh = mlx5e_get_rxfh,
1524 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1525 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1526 .set_rxnfc = mlx5e_set_rxnfc,
58d52291
AS		 1527 .get_tunable = mlx5e_get_tunable,
1528 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1529 .get_pauseparam = mlx5e_get_pauseparam,
1530 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1531 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1532 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1533 .get_wol = mlx5e_get_wol,
1534 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1535 .get_module_info = mlx5e_get_module_info,
1536 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288
GP		 1537 .get_priv_flags = mlx5e_get_priv_flags,
1538 .set_priv_flags = mlx5e_set_priv_flags
f62b8bb8 1539};
Linux kernel - Deliverables
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