projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'regmap/for-next'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8
AV		 41
42struct mlx5e_rq_param {
cb3c7fd4
GR		 43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45 bool am_enabled;
f62b8bb8
AV		 46};
47
48struct mlx5e_sq_param {
49 u32 sqc[MLX5_ST_SZ_DW(sqc)];
50 struct mlx5_wq_param wq;
58d52291 51 u16 max_inline;
cff92d7c 52 u8 min_inline_mode;
d3c9bc27 53 bool icosq;
f62b8bb8
AV		 54};
55
56struct mlx5e_cq_param {
57 u32 cqc[MLX5_ST_SZ_DW(cqc)];
58 struct mlx5_wq_param wq;
59 u16 eq_ix;
9908aa29 60 u8 cq_period_mode;
f62b8bb8
AV		 61};
62
63struct mlx5e_channel_param {
64 struct mlx5e_rq_param rq;
65 struct mlx5e_sq_param sq;
d3c9bc27 66 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 67 struct mlx5e_cq_param rx_cq;
68 struct mlx5e_cq_param tx_cq;
d3c9bc27 69 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 70};
71
72static void mlx5e_update_carrier(struct mlx5e_priv *priv)
73{
74 struct mlx5_core_dev *mdev = priv->mdev;
75 u8 port_state;
76
77 port_state = mlx5_query_vport_state(mdev,
e7546514 78 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 79
87424ad5
SD		 80 if (port_state == VPORT_STATE_UP) {
81 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 82 netif_carrier_on(priv->netdev);
87424ad5
SD		 83 } else {
84 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 85 netif_carrier_off(priv->netdev);
87424ad5 86 }
f62b8bb8
AV		 87}
88
89static void mlx5e_update_carrier_work(struct work_struct *work)
90{
91 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
92 update_carrier_work);
93
94 mutex_lock(&priv->state_lock);
95 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
96 mlx5e_update_carrier(priv);
97 mutex_unlock(&priv->state_lock);
98}
99
3947ca18
DJ		 100static void mlx5e_tx_timeout_work(struct work_struct *work)
101{
102 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
103 tx_timeout_work);
104 int err;
105
106 rtnl_lock();
107 mutex_lock(&priv->state_lock);
108 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
109 goto unlock;
110 mlx5e_close_locked(priv->netdev);
111 err = mlx5e_open_locked(priv->netdev);
112 if (err)
113 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
114 err);
115unlock:
116 mutex_unlock(&priv->state_lock);
117 rtnl_unlock();
118}
119
9218b44d 120static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 121{
9218b44d 122 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 123 struct mlx5e_rq_stats *rq_stats;
124 struct mlx5e_sq_stats *sq_stats;
9218b44d 125 u64 tx_offload_none = 0;
f62b8bb8
AV		 126 int i, j;
127
9218b44d 128 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 129 for (i = 0; i < priv->params.num_channels; i++) {
130 rq_stats = &priv->channel[i]->rq.stats;
131
faf4478b
GP		 132 s->rx_packets += rq_stats->packets;
133 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 134 s->rx_lro_packets += rq_stats->lro_packets;
135 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 136 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 137 s->rx_csum_complete += rq_stats->csum_complete;
138 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
f62b8bb8 139 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 140 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 141 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 142 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 143 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
144 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
f62b8bb8 145
a4418a6c 146 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 147 sq_stats = &priv->channel[i]->sq[j].stats;
148
faf4478b
GP		 149 s->tx_packets += sq_stats->packets;
150 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 151 s->tx_tso_packets += sq_stats->tso_packets;
152 s->tx_tso_bytes += sq_stats->tso_bytes;
153 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
154 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 155 s->tx_queue_stopped += sq_stats->stopped;
156 s->tx_queue_wake += sq_stats->wake;
157 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 158 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 159 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
160 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 161 }
162 }
163
9218b44d 164 /* Update calculated offload counters */
bfe6d8d1
GP		 165 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
166 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 167
bfe6d8d1 168 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 169 priv->stats.pport.phy_counters,
170 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 171}
172
173static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
174{
175 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
176 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 177 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 178 struct mlx5_core_dev *mdev = priv->mdev;
179
f62b8bb8
AV		 180 MLX5_SET(query_vport_counter_in, in, opcode,
181 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
182 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
183 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
184
185 memset(out, 0, outlen);
9218b44d
GP		 186 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
187}
188
189static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
190{
191 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
192 struct mlx5_core_dev *mdev = priv->mdev;
193 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 194 int prio;
9218b44d
GP		 195 void *out;
196 u32 *in;
197
198 in = mlx5_vzalloc(sz);
199 if (!in)
f62b8bb8
AV		 200 goto free_out;
201
9218b44d 202 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 203
9218b44d
GP		 204 out = pstats->IEEE_802_3_counters;
205 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
206 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 207
9218b44d
GP		 208 out = pstats->RFC_2863_counters;
209 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
210 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
211
212 out = pstats->RFC_2819_counters;
213 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
214 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 215
121fcdc8
GP		 216 out = pstats->phy_counters;
217 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
218 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
219
cf678570
GP		 220 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
221 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
222 out = pstats->per_prio_counters[prio];
223 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
224 mlx5_core_access_reg(mdev, in, sz, out, sz,
225 MLX5_REG_PPCNT, 0, 0);
226 }
227
f62b8bb8 228free_out:
9218b44d
GP		 229 kvfree(in);
230}
231
232static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
233{
234 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
235
236 if (!priv->q_counter)
237 return;
238
239 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
240 &qcnt->rx_out_of_buffer);
241}
242
243void mlx5e_update_stats(struct mlx5e_priv *priv)
244{
9218b44d
GP		 245 mlx5e_update_q_counter(priv);
246 mlx5e_update_vport_counters(priv);
247 mlx5e_update_pport_counters(priv);
121fcdc8 248 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 249}
250
cb67b832 251void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 252{
253 struct delayed_work *dwork = to_delayed_work(work);
254 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
255 update_stats_work);
256 mutex_lock(&priv->state_lock);
257 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 258 priv->profile->update_stats(priv);
7bb29755
MF		 259 queue_delayed_work(priv->wq, dwork,
260 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 261 }
262 mutex_unlock(&priv->state_lock);
263}
264
daa21560
TT		 265static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
266 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 267{
daa21560
TT		 268 struct mlx5e_priv *priv = vpriv;
269
e0f46eb9 270 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 271 return;
272
f62b8bb8
AV		 273 switch (event) {
274 case MLX5_DEV_EVENT_PORT_UP:
275 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 276 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 277 break;
278
279 default:
280 break;
281 }
282}
283
f62b8bb8
AV		 284static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
285{
e0f46eb9 286 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 287}
288
289static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
290{
e0f46eb9 291 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 292 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 293}
294
facc9699
SM		 295#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
296#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
297
f62b8bb8
AV		 298static int mlx5e_create_rq(struct mlx5e_channel *c,
299 struct mlx5e_rq_param *param,
300 struct mlx5e_rq *rq)
301{
302 struct mlx5e_priv *priv = c->priv;
303 struct mlx5_core_dev *mdev = priv->mdev;
304 void *rqc = param->rqc;
305 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 306 u32 byte_count;
f62b8bb8
AV		 307 int wq_sz;
308 int err;
309 int i;
310
311c7c71
SM		 311 param->wq.db_numa_node = cpu_to_node(c->cpu);
312
f62b8bb8
AV		 313 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
314 &rq->wq_ctrl);
315 if (err)
316 return err;
317
318 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
319
320 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 321
461017cb
TT		 322 switch (priv->params.rq_wq_type) {
323 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
324 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
325 GFP_KERNEL, cpu_to_node(c->cpu));
326 if (!rq->wqe_info) {
327 err = -ENOMEM;
328 goto err_rq_wq_destroy;
329 }
330 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
331 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 332 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 333
fe4c988b
SM		 334 rq->mpwqe_mtt_offset = c->ix *
335 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
336
d9d9f156
TT		 337 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
338 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
339 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
461017cb
TT		 340 byte_count = rq->wqe_sz;
341 break;
342 default: /* MLX5_WQ_TYPE_LINKED_LIST */
343 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
344 cpu_to_node(c->cpu));
345 if (!rq->skb) {
346 err = -ENOMEM;
347 goto err_rq_wq_destroy;
348 }
349 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
350 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 351 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb
TT		 352
353 rq->wqe_sz = (priv->params.lro_en) ?
354 priv->params.lro_wqe_sz :
355 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 356 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
357 byte_count = rq->wqe_sz;
461017cb
TT		 358 byte_count |= MLX5_HW_START_PADDING;
359 }
f62b8bb8
AV		 360
361 for (i = 0; i < wq_sz; i++) {
362 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
363
461017cb 364 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 365 }
366
cb3c7fd4
GR		 367 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
368 rq->am.mode = priv->params.rx_cq_period_mode;
369
461017cb 370 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 371 rq->pdev = c->pdev;
372 rq->netdev = c->netdev;
ef9814de 373 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 374 rq->channel = c;
375 rq->ix = c->ix;
50cfa25a 376 rq->priv = c->priv;
bc77b240
TT		 377 rq->mkey_be = c->mkey_be;
378 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 379
380 return 0;
381
382err_rq_wq_destroy:
383 mlx5_wq_destroy(&rq->wq_ctrl);
384
385 return err;
386}
387
388static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
389{
461017cb
TT		 390 switch (rq->wq_type) {
391 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
392 kfree(rq->wqe_info);
393 break;
394 default: /* MLX5_WQ_TYPE_LINKED_LIST */
395 kfree(rq->skb);
396 }
397
f62b8bb8
AV		 398 mlx5_wq_destroy(&rq->wq_ctrl);
399}
400
401static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
402{
50cfa25a 403 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 404 struct mlx5_core_dev *mdev = priv->mdev;
405
406 void *in;
407 void *rqc;
408 void *wq;
409 int inlen;
410 int err;
411
412 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
413 sizeof(u64) * rq->wq_ctrl.buf.npages;
414 in = mlx5_vzalloc(inlen);
415 if (!in)
416 return -ENOMEM;
417
418 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
419 wq = MLX5_ADDR_OF(rqc, rqc, wq);
420
421 memcpy(rqc, param->rqc, sizeof(param->rqc));
422
97de9f31 423 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 424 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 425 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 426 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 427 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 428 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
429
430 mlx5_fill_page_array(&rq->wq_ctrl.buf,
431 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
432
7db22ffb 433 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 434
435 kvfree(in);
436
437 return err;
438}
439
36350114
GP		 440static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
441 int next_state)
f62b8bb8
AV		 442{
443 struct mlx5e_channel *c = rq->channel;
444 struct mlx5e_priv *priv = c->priv;
445 struct mlx5_core_dev *mdev = priv->mdev;
446
447 void *in;
448 void *rqc;
449 int inlen;
450 int err;
451
452 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
453 in = mlx5_vzalloc(inlen);
454 if (!in)
455 return -ENOMEM;
456
457 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
458
459 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
460 MLX5_SET(rqc, rqc, state, next_state);
461
7db22ffb 462 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 463
464 kvfree(in);
465
466 return err;
467}
468
36350114
GP		 469static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
470{
471 struct mlx5e_channel *c = rq->channel;
472 struct mlx5e_priv *priv = c->priv;
473 struct mlx5_core_dev *mdev = priv->mdev;
474
475 void *in;
476 void *rqc;
477 int inlen;
478 int err;
479
480 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
481 in = mlx5_vzalloc(inlen);
482 if (!in)
483 return -ENOMEM;
484
485 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
486
487 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 488 MLX5_SET64(modify_rq_in, in, modify_bitmask,
489 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 490 MLX5_SET(rqc, rqc, vsd, vsd);
491 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
492
493 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
494
495 kvfree(in);
496
497 return err;
498}
499
f62b8bb8
AV		 500static void mlx5e_disable_rq(struct mlx5e_rq *rq)
501{
50cfa25a 502 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 503}
504
505static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
506{
01c196a2 507 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 508 struct mlx5e_channel *c = rq->channel;
509 struct mlx5e_priv *priv = c->priv;
510 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 511
01c196a2 512 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 513 if (wq->cur_sz >= priv->params.min_rx_wqes)
514 return 0;
515
516 msleep(20);
517 }
518
519 return -ETIMEDOUT;
520}
521
f2fde18c
SM		 522static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
523{
524 struct mlx5_wq_ll *wq = &rq->wq;
525 struct mlx5e_rx_wqe *wqe;
526 __be16 wqe_ix_be;
527 u16 wqe_ix;
528
8484f9ed
SM		 529 /* UMR WQE (if in progress) is always at wq->head */
530 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
531 mlx5e_free_rx_fragmented_mpwqe(rq, &rq->wqe_info[wq->head]);
532
f2fde18c
SM		 533 while (!mlx5_wq_ll_is_empty(wq)) {
534 wqe_ix_be = *wq->tail_next;
535 wqe_ix = be16_to_cpu(wqe_ix_be);
536 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
537 rq->dealloc_wqe(rq, wqe_ix);
538 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
539 &wqe->next.next_wqe_index);
540 }
541}
542
f62b8bb8
AV		 543static int mlx5e_open_rq(struct mlx5e_channel *c,
544 struct mlx5e_rq_param *param,
545 struct mlx5e_rq *rq)
546{
d3c9bc27
TT		 547 struct mlx5e_sq *sq = &c->icosq;
548 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 549 int err;
550
551 err = mlx5e_create_rq(c, param, rq);
552 if (err)
553 return err;
554
555 err = mlx5e_enable_rq(rq, param);
556 if (err)
557 goto err_destroy_rq;
558
36350114 559 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 560 if (err)
561 goto err_disable_rq;
562
cb3c7fd4
GR		 563 if (param->am_enabled)
564 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
565
d3c9bc27
TT		 566 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
567 sq->ico_wqe_info[pi].num_wqebbs = 1;
568 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 569
570 return 0;
571
572err_disable_rq:
573 mlx5e_disable_rq(rq);
574err_destroy_rq:
575 mlx5e_destroy_rq(rq);
576
577 return err;
578}
579
580static void mlx5e_close_rq(struct mlx5e_rq *rq)
581{
f2fde18c 582 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
f62b8bb8 583 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 584 cancel_work_sync(&rq->am.work);
585
f62b8bb8 586 mlx5e_disable_rq(rq);
6cd392a0 587 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 588 mlx5e_destroy_rq(rq);
589}
590
591static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
592{
34802a42 593 kfree(sq->wqe_info);
f62b8bb8
AV		 594 kfree(sq->dma_fifo);
595 kfree(sq->skb);
596}
597
598static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
599{
600 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
601 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
602
603 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
604 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
605 numa);
34802a42
AS		 606 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
607 numa);
f62b8bb8 608
34802a42 609 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 610 mlx5e_free_sq_db(sq);
611 return -ENOMEM;
612 }
613
614 sq->dma_fifo_mask = df_sz - 1;
615
616 return 0;
617}
618
619static int mlx5e_create_sq(struct mlx5e_channel *c,
620 int tc,
621 struct mlx5e_sq_param *param,
622 struct mlx5e_sq *sq)
623{
624 struct mlx5e_priv *priv = c->priv;
625 struct mlx5_core_dev *mdev = priv->mdev;
626
627 void *sqc = param->sqc;
628 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
629 int err;
630
fd4782c2 631 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 632 if (err)
633 return err;
634
311c7c71
SM		 635 param->wq.db_numa_node = cpu_to_node(c->cpu);
636
f62b8bb8
AV		 637 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
638 &sq->wq_ctrl);
639 if (err)
640 goto err_unmap_free_uar;
641
642 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 643 if (sq->uar.bf_map) {
644 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
645 sq->uar_map = sq->uar.bf_map;
646 } else {
647 sq->uar_map = sq->uar.map;
648 }
f62b8bb8 649 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 650 sq->max_inline = param->max_inline;
cff92d7c
HHZ		 651 sq->min_inline_mode =
652 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
653 param->min_inline_mode : 0;
f62b8bb8 654
7ec0bb22
DC		 655 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
656 if (err)
f62b8bb8
AV		 657 goto err_sq_wq_destroy;
658
d3c9bc27
TT		 659 if (param->icosq) {
660 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
661
662 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
663 wq_sz,
664 GFP_KERNEL,
665 cpu_to_node(c->cpu));
666 if (!sq->ico_wqe_info) {
667 err = -ENOMEM;
668 goto err_free_sq_db;
669 }
670 } else {
671 int txq_ix;
672
673 txq_ix = c->ix + tc * priv->params.num_channels;
674 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
675 priv->txq_to_sq_map[txq_ix] = sq;
676 }
f62b8bb8 677
88a85f99 678 sq->pdev = c->pdev;
ef9814de 679 sq->tstamp = &priv->tstamp;
88a85f99
AS		 680 sq->mkey_be = c->mkey_be;
681 sq->channel = c;
682 sq->tc = tc;
683 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
684 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 685
686 return 0;
687
d3c9bc27
TT		 688err_free_sq_db:
689 mlx5e_free_sq_db(sq);
690
f62b8bb8
AV		 691err_sq_wq_destroy:
692 mlx5_wq_destroy(&sq->wq_ctrl);
693
694err_unmap_free_uar:
695 mlx5_unmap_free_uar(mdev, &sq->uar);
696
697 return err;
698}
699
700static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
701{
702 struct mlx5e_channel *c = sq->channel;
703 struct mlx5e_priv *priv = c->priv;
704
d3c9bc27 705 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 706 mlx5e_free_sq_db(sq);
707 mlx5_wq_destroy(&sq->wq_ctrl);
708 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
709}
710
711static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
712{
713 struct mlx5e_channel *c = sq->channel;
714 struct mlx5e_priv *priv = c->priv;
715 struct mlx5_core_dev *mdev = priv->mdev;
716
717 void *in;
718 void *sqc;
719 void *wq;
720 int inlen;
721 int err;
722
723 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
724 sizeof(u64) * sq->wq_ctrl.buf.npages;
725 in = mlx5_vzalloc(inlen);
726 if (!in)
727 return -ENOMEM;
728
729 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
730 wq = MLX5_ADDR_OF(sqc, sqc, wq);
731
732 memcpy(sqc, param->sqc, sizeof(param->sqc));
733
d3c9bc27
TT		 734 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
735 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 736 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 737 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 738 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 739 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
740
741 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
742 MLX5_SET(wq, wq, uar_page, sq->uar.index);
743 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 744 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 745 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
746
747 mlx5_fill_page_array(&sq->wq_ctrl.buf,
748 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
749
7db22ffb 750 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 751
752 kvfree(in);
753
754 return err;
755}
756
507f0c81
YP		 757static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
758 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 759{
760 struct mlx5e_channel *c = sq->channel;
761 struct mlx5e_priv *priv = c->priv;
762 struct mlx5_core_dev *mdev = priv->mdev;
763
764 void *in;
765 void *sqc;
766 int inlen;
767 int err;
768
769 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
770 in = mlx5_vzalloc(inlen);
771 if (!in)
772 return -ENOMEM;
773
774 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
775
776 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
777 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 778 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
779 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
780 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
781 }
f62b8bb8 782
7db22ffb 783 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 784
785 kvfree(in);
786
787 return err;
788}
789
790static void mlx5e_disable_sq(struct mlx5e_sq *sq)
791{
792 struct mlx5e_channel *c = sq->channel;
793 struct mlx5e_priv *priv = c->priv;
794 struct mlx5_core_dev *mdev = priv->mdev;
795
7db22ffb 796 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 797 if (sq->rate_limit)
798 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 799}
800
801static int mlx5e_open_sq(struct mlx5e_channel *c,
802 int tc,
803 struct mlx5e_sq_param *param,
804 struct mlx5e_sq *sq)
805{
806 int err;
807
808 err = mlx5e_create_sq(c, tc, param, sq);
809 if (err)
810 return err;
811
812 err = mlx5e_enable_sq(sq, param);
813 if (err)
814 goto err_destroy_sq;
815
507f0c81
YP		 816 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
817 false, 0);
f62b8bb8
AV		 818 if (err)
819 goto err_disable_sq;
820
d3c9bc27 821 if (sq->txq) {
d3c9bc27
TT		 822 netdev_tx_reset_queue(sq->txq);
823 netif_tx_start_queue(sq->txq);
824 }
f62b8bb8
AV		 825
826 return 0;
827
828err_disable_sq:
829 mlx5e_disable_sq(sq);
830err_destroy_sq:
831 mlx5e_destroy_sq(sq);
832
833 return err;
834}
835
836static inline void netif_tx_disable_queue(struct netdev_queue *txq)
837{
838 __netif_tx_lock_bh(txq);
839 netif_tx_stop_queue(txq);
840 __netif_tx_unlock_bh(txq);
841}
842
843static void mlx5e_close_sq(struct mlx5e_sq *sq)
844{
6e8dd6d6
SM		 845 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
846 /* prevent netif_tx_wake_queue */
847 napi_synchronize(&sq->channel->napi);
29429f33 848
d3c9bc27 849 if (sq->txq) {
d3c9bc27 850 netif_tx_disable_queue(sq->txq);
f62b8bb8 851
6e8dd6d6 852 /* last doorbell out, godspeed .. */
d3c9bc27
TT		 853 if (mlx5e_sq_has_room_for(sq, 1))
854 mlx5e_send_nop(sq, true);
29429f33 855 }
f62b8bb8 856
f62b8bb8 857 mlx5e_disable_sq(sq);
6e8dd6d6 858 mlx5e_free_tx_descs(sq);
f62b8bb8
AV		 859 mlx5e_destroy_sq(sq);
860}
861
862static int mlx5e_create_cq(struct mlx5e_channel *c,
863 struct mlx5e_cq_param *param,
864 struct mlx5e_cq *cq)
865{
866 struct mlx5e_priv *priv = c->priv;
867 struct mlx5_core_dev *mdev = priv->mdev;
868 struct mlx5_core_cq *mcq = &cq->mcq;
869 int eqn_not_used;
0b6e26ce 870 unsigned int irqn;
f62b8bb8
AV		 871 int err;
872 u32 i;
873
311c7c71
SM		 874 param->wq.buf_numa_node = cpu_to_node(c->cpu);
875 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 876 param->eq_ix = c->ix;
877
878 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
879 &cq->wq_ctrl);
880 if (err)
881 return err;
882
883 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
884
885 cq->napi = &c->napi;
886
887 mcq->cqe_sz = 64;
888 mcq->set_ci_db = cq->wq_ctrl.db.db;
889 mcq->arm_db = cq->wq_ctrl.db.db + 1;
890 *mcq->set_ci_db = 0;
891 *mcq->arm_db = 0;
892 mcq->vector = param->eq_ix;
893 mcq->comp = mlx5e_completion_event;
894 mcq->event = mlx5e_cq_error_event;
895 mcq->irqn = irqn;
b50d292b 896 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 897
898 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
899 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
900
901 cqe->op_own = 0xf1;
902 }
903
904 cq->channel = c;
50cfa25a 905 cq->priv = priv;
f62b8bb8
AV		 906
907 return 0;
908}
909
910static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
911{
912 mlx5_wq_destroy(&cq->wq_ctrl);
913}
914
915static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
916{
50cfa25a 917 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 918 struct mlx5_core_dev *mdev = priv->mdev;
919 struct mlx5_core_cq *mcq = &cq->mcq;
920
921 void *in;
922 void *cqc;
923 int inlen;
0b6e26ce 924 unsigned int irqn_not_used;
f62b8bb8
AV		 925 int eqn;
926 int err;
927
928 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
929 sizeof(u64) * cq->wq_ctrl.buf.npages;
930 in = mlx5_vzalloc(inlen);
931 if (!in)
932 return -ENOMEM;
933
934 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
935
936 memcpy(cqc, param->cqc, sizeof(param->cqc));
937
938 mlx5_fill_page_array(&cq->wq_ctrl.buf,
939 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
940
941 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
942
9908aa29 943 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 944 MLX5_SET(cqc, cqc, c_eqn, eqn);
945 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
946 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 947 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 948 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
949
950 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
951
952 kvfree(in);
953
954 if (err)
955 return err;
956
957 mlx5e_cq_arm(cq);
958
959 return 0;
960}
961
962static void mlx5e_disable_cq(struct mlx5e_cq *cq)
963{
50cfa25a 964 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 965 struct mlx5_core_dev *mdev = priv->mdev;
966
967 mlx5_core_destroy_cq(mdev, &cq->mcq);
968}
969
970static int mlx5e_open_cq(struct mlx5e_channel *c,
971 struct mlx5e_cq_param *param,
972 struct mlx5e_cq *cq,
9908aa29 973 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 974{
975 int err;
976 struct mlx5e_priv *priv = c->priv;
977 struct mlx5_core_dev *mdev = priv->mdev;
978
979 err = mlx5e_create_cq(c, param, cq);
980 if (err)
981 return err;
982
983 err = mlx5e_enable_cq(cq, param);
984 if (err)
985 goto err_destroy_cq;
986
7524a5d8
GP		 987 if (MLX5_CAP_GEN(mdev, cq_moderation))
988 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 989 moderation.usec,
990 moderation.pkts);
f62b8bb8
AV		 991 return 0;
992
993err_destroy_cq:
994 mlx5e_destroy_cq(cq);
995
996 return err;
997}
998
999static void mlx5e_close_cq(struct mlx5e_cq *cq)
1000{
1001 mlx5e_disable_cq(cq);
1002 mlx5e_destroy_cq(cq);
1003}
1004
1005static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1006{
1007 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1008}
1009
1010static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1011 struct mlx5e_channel_param *cparam)
1012{
1013 struct mlx5e_priv *priv = c->priv;
1014 int err;
1015 int tc;
1016
1017 for (tc = 0; tc < c->num_tc; tc++) {
1018 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1019 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1020 if (err)
1021 goto err_close_tx_cqs;
f62b8bb8
AV		 1022 }
1023
1024 return 0;
1025
1026err_close_tx_cqs:
1027 for (tc--; tc >= 0; tc--)
1028 mlx5e_close_cq(&c->sq[tc].cq);
1029
1030 return err;
1031}
1032
1033static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1034{
1035 int tc;
1036
1037 for (tc = 0; tc < c->num_tc; tc++)
1038 mlx5e_close_cq(&c->sq[tc].cq);
1039}
1040
1041static int mlx5e_open_sqs(struct mlx5e_channel *c,
1042 struct mlx5e_channel_param *cparam)
1043{
1044 int err;
1045 int tc;
1046
1047 for (tc = 0; tc < c->num_tc; tc++) {
1048 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1049 if (err)
1050 goto err_close_sqs;
1051 }
1052
1053 return 0;
1054
1055err_close_sqs:
1056 for (tc--; tc >= 0; tc--)
1057 mlx5e_close_sq(&c->sq[tc]);
1058
1059 return err;
1060}
1061
1062static void mlx5e_close_sqs(struct mlx5e_channel *c)
1063{
1064 int tc;
1065
1066 for (tc = 0; tc < c->num_tc; tc++)
1067 mlx5e_close_sq(&c->sq[tc]);
1068}
1069
5283af89 1070static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1071{
1072 int i;
1073
6bfd390b 1074 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1075 priv->channeltc_to_txq_map[ix][i] =
1076 ix + i * priv->params.num_channels;
03289b88
SM		 1077}
1078
507f0c81
YP		 1079static int mlx5e_set_sq_maxrate(struct net_device *dev,
1080 struct mlx5e_sq *sq, u32 rate)
1081{
1082 struct mlx5e_priv *priv = netdev_priv(dev);
1083 struct mlx5_core_dev *mdev = priv->mdev;
1084 u16 rl_index = 0;
1085 int err;
1086
1087 if (rate == sq->rate_limit)
1088 /* nothing to do */
1089 return 0;
1090
1091 if (sq->rate_limit)
1092 /* remove current rl index to free space to next ones */
1093 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1094
1095 sq->rate_limit = 0;
1096
1097 if (rate) {
1098 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1099 if (err) {
1100 netdev_err(dev, "Failed configuring rate %u: %d\n",
1101 rate, err);
1102 return err;
1103 }
1104 }
1105
1106 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1107 MLX5_SQC_STATE_RDY, true, rl_index);
1108 if (err) {
1109 netdev_err(dev, "Failed configuring rate %u: %d\n",
1110 rate, err);
1111 /* remove the rate from the table */
1112 if (rate)
1113 mlx5_rl_remove_rate(mdev, rate);
1114 return err;
1115 }
1116
1117 sq->rate_limit = rate;
1118 return 0;
1119}
1120
1121static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1122{
1123 struct mlx5e_priv *priv = netdev_priv(dev);
1124 struct mlx5_core_dev *mdev = priv->mdev;
1125 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1126 int err = 0;
1127
1128 if (!mlx5_rl_is_supported(mdev)) {
1129 netdev_err(dev, "Rate limiting is not supported on this device\n");
1130 return -EINVAL;
1131 }
1132
1133 /* rate is given in Mb/sec, HW config is in Kb/sec */
1134 rate = rate << 10;
1135
1136 /* Check whether rate in valid range, 0 is always valid */
1137 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1138 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1139 return -ERANGE;
1140 }
1141
1142 mutex_lock(&priv->state_lock);
1143 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1144 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1145 if (!err)
1146 priv->tx_rates[index] = rate;
1147 mutex_unlock(&priv->state_lock);
1148
1149 return err;
1150}
1151
f62b8bb8
AV		 1152static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1153 struct mlx5e_channel_param *cparam,
1154 struct mlx5e_channel **cp)
1155{
9908aa29 1156 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1157 struct net_device *netdev = priv->netdev;
cb3c7fd4 1158 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1159 int cpu = mlx5e_get_cpu(priv, ix);
1160 struct mlx5e_channel *c;
507f0c81 1161 struct mlx5e_sq *sq;
f62b8bb8 1162 int err;
507f0c81 1163 int i;
f62b8bb8
AV		 1164
1165 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1166 if (!c)
1167 return -ENOMEM;
1168
1169 c->priv = priv;
1170 c->ix = ix;
1171 c->cpu = cpu;
1172 c->pdev = &priv->mdev->pdev->dev;
1173 c->netdev = priv->netdev;
b50d292b 1174 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1175 c->num_tc = priv->params.num_tc;
f62b8bb8 1176
cb3c7fd4
GR		 1177 if (priv->params.rx_am_enabled)
1178 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1179 else
1180 rx_cq_profile = priv->params.rx_cq_moderation;
1181
5283af89 1182 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1183
f62b8bb8
AV		 1184 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1185
9908aa29 1186 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1187 if (err)
1188 goto err_napi_del;
1189
d3c9bc27
TT		 1190 err = mlx5e_open_tx_cqs(c, cparam);
1191 if (err)
1192 goto err_close_icosq_cq;
1193
f62b8bb8 1194 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1195 rx_cq_profile);
f62b8bb8
AV		 1196 if (err)
1197 goto err_close_tx_cqs;
f62b8bb8
AV		 1198
1199 napi_enable(&c->napi);
1200
d3c9bc27 1201 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1202 if (err)
1203 goto err_disable_napi;
1204
d3c9bc27
TT		 1205 err = mlx5e_open_sqs(c, cparam);
1206 if (err)
1207 goto err_close_icosq;
1208
507f0c81
YP		 1209 for (i = 0; i < priv->params.num_tc; i++) {
1210 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1211
1212 if (priv->tx_rates[txq_ix]) {
1213 sq = priv->txq_to_sq_map[txq_ix];
1214 mlx5e_set_sq_maxrate(priv->netdev, sq,
1215 priv->tx_rates[txq_ix]);
1216 }
1217 }
1218
f62b8bb8
AV		 1219 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1220 if (err)
1221 goto err_close_sqs;
1222
1223 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1224 *cp = c;
1225
1226 return 0;
1227
1228err_close_sqs:
1229 mlx5e_close_sqs(c);
1230
d3c9bc27
TT		 1231err_close_icosq:
1232 mlx5e_close_sq(&c->icosq);
1233
f62b8bb8
AV		 1234err_disable_napi:
1235 napi_disable(&c->napi);
1236 mlx5e_close_cq(&c->rq.cq);
1237
1238err_close_tx_cqs:
1239 mlx5e_close_tx_cqs(c);
1240
d3c9bc27
TT		 1241err_close_icosq_cq:
1242 mlx5e_close_cq(&c->icosq.cq);
1243
f62b8bb8
AV		 1244err_napi_del:
1245 netif_napi_del(&c->napi);
7ae92ae5 1246 napi_hash_del(&c->napi);
f62b8bb8
AV		 1247 kfree(c);
1248
1249 return err;
1250}
1251
1252static void mlx5e_close_channel(struct mlx5e_channel *c)
1253{
1254 mlx5e_close_rq(&c->rq);
1255 mlx5e_close_sqs(c);
d3c9bc27 1256 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1257 napi_disable(&c->napi);
1258 mlx5e_close_cq(&c->rq.cq);
1259 mlx5e_close_tx_cqs(c);
d3c9bc27 1260 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1261 netif_napi_del(&c->napi);
7ae92ae5
ED		 1262
1263 napi_hash_del(&c->napi);
1264 synchronize_rcu();
1265
f62b8bb8
AV		 1266 kfree(c);
1267}
1268
1269static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1270 struct mlx5e_rq_param *param)
1271{
1272 void *rqc = param->rqc;
1273 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1274
461017cb
TT		 1275 switch (priv->params.rq_wq_type) {
1276 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1277 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1278 priv->params.mpwqe_log_num_strides - 9);
461017cb 1279 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1280 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1281 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1282 break;
1283 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1284 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1285 }
1286
f62b8bb8
AV		 1287 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1288 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1289 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1290 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1291 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1292
311c7c71 1293 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1294 param->wq.linear = 1;
cb3c7fd4
GR		 1295
1296 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1297}
1298
556dd1b9
TT		 1299static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1300{
1301 void *rqc = param->rqc;
1302 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1303
1304 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1305 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1306}
1307
d3c9bc27
TT		 1308static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1309 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1310{
1311 void *sqc = param->sqc;
1312 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1313
f62b8bb8 1314 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1315 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1316
311c7c71 1317 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1318}
1319
1320static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1321 struct mlx5e_sq_param *param)
1322{
1323 void *sqc = param->sqc;
1324 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1325
1326 mlx5e_build_sq_param_common(priv, param);
1327 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1328
58d52291 1329 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1330 param->min_inline_mode = priv->params.tx_min_inline_mode;
f62b8bb8
AV		 1331}
1332
1333static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1334 struct mlx5e_cq_param *param)
1335{
1336 void *cqc = param->cqc;
1337
b50d292b 1338 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1339}
1340
1341static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1342 struct mlx5e_cq_param *param)
1343{
1344 void *cqc = param->cqc;
461017cb 1345 u8 log_cq_size;
f62b8bb8 1346
461017cb
TT		 1347 switch (priv->params.rq_wq_type) {
1348 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1349 log_cq_size = priv->params.log_rq_size +
d9d9f156 1350 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1351 break;
1352 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1353 log_cq_size = priv->params.log_rq_size;
1354 }
1355
1356 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1357 if (priv->params.rx_cqe_compress) {
1358 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1359 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1360 }
f62b8bb8
AV		 1361
1362 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1363
1364 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1365}
1366
1367static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1368 struct mlx5e_cq_param *param)
1369{
1370 void *cqc = param->cqc;
1371
d3c9bc27 1372 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1373
1374 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1375
1376 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1377}
1378
d3c9bc27
TT		 1379static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1380 struct mlx5e_cq_param *param,
1381 u8 log_wq_size)
1382{
1383 void *cqc = param->cqc;
1384
1385 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1386
1387 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1388
1389 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1390}
1391
1392static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1393 struct mlx5e_sq_param *param,
1394 u8 log_wq_size)
1395{
1396 void *sqc = param->sqc;
1397 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1398
1399 mlx5e_build_sq_param_common(priv, param);
1400
1401 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1402 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1403
1404 param->icosq = true;
1405}
1406
6b87663f 1407static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1408{
bc77b240 1409 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1410
f62b8bb8
AV		 1411 mlx5e_build_rq_param(priv, &cparam->rq);
1412 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1413 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1414 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1415 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1416 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1417}
1418
1419static int mlx5e_open_channels(struct mlx5e_priv *priv)
1420{
6b87663f 1421 struct mlx5e_channel_param *cparam;
a4418a6c 1422 int nch = priv->params.num_channels;
03289b88 1423 int err = -ENOMEM;
f62b8bb8
AV		 1424 int i;
1425 int j;
1426
a4418a6c
AS		 1427 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1428 GFP_KERNEL);
03289b88 1429
a4418a6c 1430 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1431 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1432
6b87663f
AB		 1433 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1434
1435 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1436 goto err_free_txq_to_sq_map;
f62b8bb8 1437
6b87663f
AB		 1438 mlx5e_build_channel_param(priv, cparam);
1439
a4418a6c 1440 for (i = 0; i < nch; i++) {
6b87663f 1441 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1442 if (err)
1443 goto err_close_channels;
1444 }
1445
a4418a6c 1446 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1447 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1448 if (err)
1449 goto err_close_channels;
1450 }
1451
c3b7c5c9
MHY		 1452 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1453 * polling for inactive tx queues.
1454 */
1455 netif_tx_start_all_queues(priv->netdev);
1456
6b87663f 1457 kfree(cparam);
f62b8bb8
AV		 1458 return 0;
1459
1460err_close_channels:
1461 for (i--; i >= 0; i--)
1462 mlx5e_close_channel(priv->channel[i]);
1463
03289b88
SM		 1464err_free_txq_to_sq_map:
1465 kfree(priv->txq_to_sq_map);
f62b8bb8 1466 kfree(priv->channel);
6b87663f 1467 kfree(cparam);
f62b8bb8
AV		 1468
1469 return err;
1470}
1471
1472static void mlx5e_close_channels(struct mlx5e_priv *priv)
1473{
1474 int i;
1475
c3b7c5c9
MHY		 1476 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1477 * polling for inactive tx queues.
1478 */
1479 netif_tx_stop_all_queues(priv->netdev);
1480 netif_tx_disable(priv->netdev);
1481
f62b8bb8
AV		 1482 for (i = 0; i < priv->params.num_channels; i++)
1483 mlx5e_close_channel(priv->channel[i]);
1484
03289b88 1485 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1486 kfree(priv->channel);
1487}
1488
2be6967c
SM		 1489static int mlx5e_rx_hash_fn(int hfunc)
1490{
1491 return (hfunc == ETH_RSS_HASH_TOP) ?
1492 MLX5_RX_HASH_FN_TOEPLITZ :
1493 MLX5_RX_HASH_FN_INVERTED_XOR8;
1494}
1495
1496static int mlx5e_bits_invert(unsigned long a, int size)
1497{
1498 int inv = 0;
1499 int i;
1500
1501 for (i = 0; i < size; i++)
1502 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1503
1504 return inv;
1505}
1506
936896e9
AS		 1507static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1508{
1509 int i;
1510
1511 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1512 int ix = i;
1da36696 1513 u32 rqn;
936896e9
AS		 1514
1515 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1516 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1517
2d75b2bc 1518 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1519 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1520 priv->channel[ix]->rq.rqn :
1521 priv->drop_rq.rqn;
1522 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1523 }
1524}
1525
1da36696
TT		 1526static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1527 int ix)
4cbeaff5 1528{
1da36696
TT		 1529 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1530 priv->channel[ix]->rq.rqn :
1531 priv->drop_rq.rqn;
4cbeaff5 1532
1da36696 1533 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1534}
1535
398f3351
HHZ		 1536static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1537 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1538{
1539 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1540 void *rqtc;
1541 int inlen;
1542 int err;
1da36696 1543 u32 *in;
f62b8bb8 1544
f62b8bb8
AV		 1545 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1546 in = mlx5_vzalloc(inlen);
1547 if (!in)
1548 return -ENOMEM;
1549
1550 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1551
1552 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1553 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1554
1da36696
TT		 1555 if (sz > 1) /* RSS */
1556 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1557 else
1558 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1559
398f3351
HHZ		 1560 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1561 if (!err)
1562 rqt->enabled = true;
f62b8bb8
AV		 1563
1564 kvfree(in);
1da36696
TT		 1565 return err;
1566}
1567
cb67b832 1568void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1569{
398f3351
HHZ		 1570 rqt->enabled = false;
1571 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1572}
1573
6bfd390b
HHZ		 1574static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1575{
1576 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1577
1578 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1579}
1580
cb67b832 1581int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1582{
398f3351 1583 struct mlx5e_rqt *rqt;
1da36696
TT		 1584 int err;
1585 int ix;
1586
6bfd390b 1587 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1588 rqt = &priv->direct_tir[ix].rqt;
1589 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1590 if (err)
1591 goto err_destroy_rqts;
1592 }
1593
1594 return 0;
1595
1596err_destroy_rqts:
1597 for (ix--; ix >= 0; ix--)
398f3351 1598 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1599
f62b8bb8
AV		 1600 return err;
1601}
1602
1da36696 1603int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1604{
1605 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1606 void *rqtc;
1607 int inlen;
1da36696 1608 u32 *in;
5c50368f
AS		 1609 int err;
1610
5c50368f
AS		 1611 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1612 in = mlx5_vzalloc(inlen);
1613 if (!in)
1614 return -ENOMEM;
1615
1616 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1617
1618 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1619 if (sz > 1) /* RSS */
1620 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1621 else
1622 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1623
1624 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1625
1da36696 1626 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1627
1628 kvfree(in);
1629
1630 return err;
1631}
1632
40ab6a6e
AS		 1633static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1634{
1da36696
TT		 1635 u32 rqtn;
1636 int ix;
1637
398f3351
HHZ		 1638 if (priv->indir_rqt.enabled) {
1639 rqtn = priv->indir_rqt.rqtn;
1640 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1641 }
1642
1da36696 1643 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1644 if (!priv->direct_tir[ix].rqt.enabled)
1645 continue;
1646 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1647 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1648 }
40ab6a6e
AS		 1649}
1650
5c50368f
AS		 1651static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1652{
1653 if (!priv->params.lro_en)
1654 return;
1655
1656#define ROUGH_MAX_L2_L3_HDR_SZ 256
1657
1658 MLX5_SET(tirc, tirc, lro_enable_mask,
1659 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1660 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1661 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1662 (priv->params.lro_wqe_sz -
1663 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1664 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1665 MLX5_CAP_ETH(priv->mdev,
d9a40271 1666 lro_timer_supported_periods[2]));
5c50368f
AS		 1667}
1668
bdfc028d
TT		 1669void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1670{
1671 MLX5_SET(tirc, tirc, rx_hash_fn,
1672 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1673 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1674 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1675 rx_hash_toeplitz_key);
1676 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1677 rx_hash_toeplitz_key);
1678
1679 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1680 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1681 }
1682}
1683
ab0394fe 1684static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1685{
1686 struct mlx5_core_dev *mdev = priv->mdev;
1687
1688 void *in;
1689 void *tirc;
1690 int inlen;
1691 int err;
ab0394fe 1692 int tt;
1da36696 1693 int ix;
5c50368f
AS		 1694
1695 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1696 in = mlx5_vzalloc(inlen);
1697 if (!in)
1698 return -ENOMEM;
1699
1700 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1701 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1702
1703 mlx5e_build_tir_ctx_lro(tirc, priv);
1704
1da36696 1705 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 1706 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 1707 inlen);
ab0394fe 1708 if (err)
1da36696 1709 goto free_in;
ab0394fe 1710 }
5c50368f 1711
6bfd390b 1712 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 1713 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1714 in, inlen);
1715 if (err)
1716 goto free_in;
1717 }
1718
1719free_in:
5c50368f
AS		 1720 kvfree(in);
1721
1722 return err;
1723}
1724
cd255eff 1725static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1726{
40ab6a6e 1727 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1728 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1729 int err;
1730
cd255eff 1731 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1732 if (err)
1733 return err;
1734
cd255eff
SM		 1735 /* Update vport context MTU */
1736 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1737 return 0;
1738}
40ab6a6e 1739
cd255eff
SM		 1740static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1741{
1742 struct mlx5_core_dev *mdev = priv->mdev;
1743 u16 hw_mtu = 0;
1744 int err;
40ab6a6e 1745
cd255eff
SM		 1746 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1747 if (err || !hw_mtu) /* fallback to port oper mtu */
1748 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1749
1750 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1751}
1752
1753static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1754{
1755 struct mlx5e_priv *priv = netdev_priv(netdev);
1756 u16 mtu;
1757 int err;
1758
1759 err = mlx5e_set_mtu(priv, netdev->mtu);
1760 if (err)
1761 return err;
40ab6a6e 1762
cd255eff
SM		 1763 mlx5e_query_mtu(priv, &mtu);
1764 if (mtu != netdev->mtu)
1765 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1766 __func__, mtu, netdev->mtu);
40ab6a6e 1767
cd255eff 1768 netdev->mtu = mtu;
40ab6a6e
AS		 1769 return 0;
1770}
1771
08fb1dac
SM		 1772static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1773{
1774 struct mlx5e_priv *priv = netdev_priv(netdev);
1775 int nch = priv->params.num_channels;
1776 int ntc = priv->params.num_tc;
1777 int tc;
1778
1779 netdev_reset_tc(netdev);
1780
1781 if (ntc == 1)
1782 return;
1783
1784 netdev_set_num_tc(netdev, ntc);
1785
7ccdd084
RS		 1786 /* Map netdev TCs to offset 0
1787 * We have our own UP to TXQ mapping for QoS
1788 */
08fb1dac 1789 for (tc = 0; tc < ntc; tc++)
7ccdd084 1790 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 1791}
1792
40ab6a6e
AS		 1793int mlx5e_open_locked(struct net_device *netdev)
1794{
1795 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 1796 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 1797 int num_txqs;
1798 int err;
1799
1800 set_bit(MLX5E_STATE_OPENED, &priv->state);
1801
08fb1dac
SM		 1802 mlx5e_netdev_set_tcs(netdev);
1803
40ab6a6e
AS		 1804 num_txqs = priv->params.num_channels * priv->params.num_tc;
1805 netif_set_real_num_tx_queues(netdev, num_txqs);
1806 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1807
40ab6a6e
AS		 1808 err = mlx5e_open_channels(priv);
1809 if (err) {
1810 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1811 __func__, err);
343b29f3 1812 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1813 }
1814
724b2aa1 1815 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
66189961
TT		 1816 if (err) {
1817 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1818 __func__, err);
1819 goto err_close_channels;
1820 }
1821
40ab6a6e 1822 mlx5e_redirect_rqts(priv);
ce89ef36 1823 mlx5e_update_carrier(priv);
ef9814de 1824 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1825#ifdef CONFIG_RFS_ACCEL
1826 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1827#endif
cb67b832
HHZ		 1828 if (priv->profile->update_stats)
1829 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 1830
cb67b832
HHZ		 1831 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1832 err = mlx5e_add_sqs_fwd_rules(priv);
1833 if (err)
1834 goto err_close_channels;
1835 }
9b37b07f 1836 return 0;
343b29f3 1837
66189961
TT		 1838err_close_channels:
1839 mlx5e_close_channels(priv);
343b29f3
AS		 1840err_clear_state_opened_flag:
1841 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1842 return err;
40ab6a6e
AS		 1843}
1844
cb67b832 1845int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 1846{
1847 struct mlx5e_priv *priv = netdev_priv(netdev);
1848 int err;
1849
1850 mutex_lock(&priv->state_lock);
1851 err = mlx5e_open_locked(netdev);
1852 mutex_unlock(&priv->state_lock);
1853
1854 return err;
1855}
1856
1857int mlx5e_close_locked(struct net_device *netdev)
1858{
1859 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 1860 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 1861
a1985740
AS		 1862 /* May already be CLOSED in case a previous configuration operation
1863 * (e.g RX/TX queue size change) that involves close&open failed.
1864 */
1865 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1866 return 0;
1867
40ab6a6e
AS		 1868 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1869
cb67b832
HHZ		 1870 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1871 mlx5e_remove_sqs_fwd_rules(priv);
1872
ef9814de 1873 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1874 netif_carrier_off(priv->netdev);
ce89ef36 1875 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1876 mlx5e_close_channels(priv);
1877
1878 return 0;
1879}
1880
cb67b832 1881int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 1882{
1883 struct mlx5e_priv *priv = netdev_priv(netdev);
1884 int err;
1885
26e59d80
MHY		 1886 if (!netif_device_present(netdev))
1887 return -ENODEV;
1888
40ab6a6e
AS		 1889 mutex_lock(&priv->state_lock);
1890 err = mlx5e_close_locked(netdev);
1891 mutex_unlock(&priv->state_lock);
1892
1893 return err;
1894}
1895
1896static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1897 struct mlx5e_rq *rq,
1898 struct mlx5e_rq_param *param)
1899{
1900 struct mlx5_core_dev *mdev = priv->mdev;
1901 void *rqc = param->rqc;
1902 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1903 int err;
1904
1905 param->wq.db_numa_node = param->wq.buf_numa_node;
1906
1907 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1908 &rq->wq_ctrl);
1909 if (err)
1910 return err;
1911
1912 rq->priv = priv;
1913
1914 return 0;
1915}
1916
1917static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1918 struct mlx5e_cq *cq,
1919 struct mlx5e_cq_param *param)
1920{
1921 struct mlx5_core_dev *mdev = priv->mdev;
1922 struct mlx5_core_cq *mcq = &cq->mcq;
1923 int eqn_not_used;
0b6e26ce 1924 unsigned int irqn;
40ab6a6e
AS		 1925 int err;
1926
1927 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1928 &cq->wq_ctrl);
1929 if (err)
1930 return err;
1931
1932 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1933
1934 mcq->cqe_sz = 64;
1935 mcq->set_ci_db = cq->wq_ctrl.db.db;
1936 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1937 *mcq->set_ci_db = 0;
1938 *mcq->arm_db = 0;
1939 mcq->vector = param->eq_ix;
1940 mcq->comp = mlx5e_completion_event;
1941 mcq->event = mlx5e_cq_error_event;
1942 mcq->irqn = irqn;
b50d292b 1943 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 1944
1945 cq->priv = priv;
1946
1947 return 0;
1948}
1949
1950static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1951{
1952 struct mlx5e_cq_param cq_param;
1953 struct mlx5e_rq_param rq_param;
1954 struct mlx5e_rq *rq = &priv->drop_rq;
1955 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1956 int err;
1957
1958 memset(&cq_param, 0, sizeof(cq_param));
1959 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1960 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1961
1962 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1963 if (err)
1964 return err;
1965
1966 err = mlx5e_enable_cq(cq, &cq_param);
1967 if (err)
1968 goto err_destroy_cq;
1969
1970 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1971 if (err)
1972 goto err_disable_cq;
1973
1974 err = mlx5e_enable_rq(rq, &rq_param);
1975 if (err)
1976 goto err_destroy_rq;
1977
1978 return 0;
1979
1980err_destroy_rq:
1981 mlx5e_destroy_rq(&priv->drop_rq);
1982
1983err_disable_cq:
1984 mlx5e_disable_cq(&priv->drop_rq.cq);
1985
1986err_destroy_cq:
1987 mlx5e_destroy_cq(&priv->drop_rq.cq);
1988
1989 return err;
1990}
1991
1992static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1993{
1994 mlx5e_disable_rq(&priv->drop_rq);
1995 mlx5e_destroy_rq(&priv->drop_rq);
1996 mlx5e_disable_cq(&priv->drop_rq.cq);
1997 mlx5e_destroy_cq(&priv->drop_rq.cq);
1998}
1999
2000static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2001{
2002 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2003 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2004 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2005
08fb1dac 2006 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2007 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2008
2009 if (mlx5_lag_is_lacp_owner(mdev))
2010 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2011
40ab6a6e
AS		 2012 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2013}
2014
2015static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2016{
2017 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2018}
2019
cb67b832 2020int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2021{
2022 int err;
2023 int tc;
2024
6bfd390b 2025 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2026 err = mlx5e_create_tis(priv, tc);
2027 if (err)
2028 goto err_close_tises;
2029 }
2030
2031 return 0;
2032
2033err_close_tises:
2034 for (tc--; tc >= 0; tc--)
2035 mlx5e_destroy_tis(priv, tc);
2036
2037 return err;
2038}
2039
cb67b832 2040void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2041{
2042 int tc;
2043
6bfd390b 2044 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2045 mlx5e_destroy_tis(priv, tc);
2046}
2047
1da36696
TT		 2048static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2049 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2050{
2051 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2052
b50d292b 2053 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2054
5a6f8aef
AS		 2055#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2056 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2057
5a6f8aef
AS		 2058#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2059 MLX5_HASH_FIELD_SEL_DST_IP |\
2060 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2061 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2062
a741749f
AS		 2063#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2064 MLX5_HASH_FIELD_SEL_DST_IP |\
2065 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2066
5c50368f 2067 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2068
4cbeaff5 2069 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2070 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2071 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2072
2073 switch (tt) {
2074 case MLX5E_TT_IPV4_TCP:
2075 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2076 MLX5_L3_PROT_TYPE_IPV4);
2077 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2078 MLX5_L4_PROT_TYPE_TCP);
2079 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2080 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2081 break;
2082
2083 case MLX5E_TT_IPV6_TCP:
2084 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2085 MLX5_L3_PROT_TYPE_IPV6);
2086 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2087 MLX5_L4_PROT_TYPE_TCP);
2088 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2089 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2090 break;
2091
2092 case MLX5E_TT_IPV4_UDP:
2093 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2094 MLX5_L3_PROT_TYPE_IPV4);
2095 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2096 MLX5_L4_PROT_TYPE_UDP);
2097 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2098 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2099 break;
2100
2101 case MLX5E_TT_IPV6_UDP:
2102 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2103 MLX5_L3_PROT_TYPE_IPV6);
2104 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2105 MLX5_L4_PROT_TYPE_UDP);
2106 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2107 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2108 break;
2109
a741749f
AS		 2110 case MLX5E_TT_IPV4_IPSEC_AH:
2111 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2112 MLX5_L3_PROT_TYPE_IPV4);
2113 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2114 MLX5_HASH_IP_IPSEC_SPI);
2115 break;
2116
2117 case MLX5E_TT_IPV6_IPSEC_AH:
2118 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2119 MLX5_L3_PROT_TYPE_IPV6);
2120 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2121 MLX5_HASH_IP_IPSEC_SPI);
2122 break;
2123
2124 case MLX5E_TT_IPV4_IPSEC_ESP:
2125 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2126 MLX5_L3_PROT_TYPE_IPV4);
2127 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2128 MLX5_HASH_IP_IPSEC_SPI);
2129 break;
2130
2131 case MLX5E_TT_IPV6_IPSEC_ESP:
2132 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2133 MLX5_L3_PROT_TYPE_IPV6);
2134 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2135 MLX5_HASH_IP_IPSEC_SPI);
2136 break;
2137
f62b8bb8
AV		 2138 case MLX5E_TT_IPV4:
2139 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2140 MLX5_L3_PROT_TYPE_IPV4);
2141 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2142 MLX5_HASH_IP);
2143 break;
2144
2145 case MLX5E_TT_IPV6:
2146 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2147 MLX5_L3_PROT_TYPE_IPV6);
2148 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2149 MLX5_HASH_IP);
2150 break;
1da36696
TT		 2151 default:
2152 WARN_ONCE(true,
2153 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2154 }
2155}
2156
1da36696
TT		 2157static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2158 u32 rqtn)
f62b8bb8 2159{
b50d292b 2160 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2161
2162 mlx5e_build_tir_ctx_lro(tirc, priv);
2163
2164 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2165 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2166 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2167}
2168
6bfd390b 2169static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2170{
724b2aa1 2171 struct mlx5e_tir *tir;
f62b8bb8
AV		 2172 void *tirc;
2173 int inlen;
2174 int err;
1da36696 2175 u32 *in;
1da36696 2176 int tt;
f62b8bb8
AV		 2177
2178 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2179 in = mlx5_vzalloc(inlen);
2180 if (!in)
2181 return -ENOMEM;
2182
1da36696
TT		 2183 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2184 memset(in, 0, inlen);
724b2aa1 2185 tir = &priv->indir_tir[tt];
1da36696
TT		 2186 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2187 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2188 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2189 if (err)
40ab6a6e 2190 goto err_destroy_tirs;
f62b8bb8
AV		 2191 }
2192
6bfd390b
HHZ		 2193 kvfree(in);
2194
2195 return 0;
2196
2197err_destroy_tirs:
2198 for (tt--; tt >= 0; tt--)
2199 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2200
2201 kvfree(in);
2202
2203 return err;
2204}
2205
cb67b832 2206int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2207{
2208 int nch = priv->profile->max_nch(priv->mdev);
2209 struct mlx5e_tir *tir;
2210 void *tirc;
2211 int inlen;
2212 int err;
2213 u32 *in;
2214 int ix;
2215
2216 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2217 in = mlx5_vzalloc(inlen);
2218 if (!in)
2219 return -ENOMEM;
2220
1da36696
TT		 2221 for (ix = 0; ix < nch; ix++) {
2222 memset(in, 0, inlen);
724b2aa1 2223 tir = &priv->direct_tir[ix];
1da36696
TT		 2224 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2225 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2226 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2227 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2228 if (err)
2229 goto err_destroy_ch_tirs;
2230 }
2231
2232 kvfree(in);
2233
f62b8bb8
AV		 2234 return 0;
2235
1da36696
TT		 2236err_destroy_ch_tirs:
2237 for (ix--; ix >= 0; ix--)
724b2aa1 2238 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2239
1da36696 2240 kvfree(in);
f62b8bb8
AV		 2241
2242 return err;
2243}
2244
6bfd390b 2245static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2246{
2247 int i;
2248
1da36696 2249 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2250 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2251}
2252
cb67b832 2253void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2254{
2255 int nch = priv->profile->max_nch(priv->mdev);
2256 int i;
2257
2258 for (i = 0; i < nch; i++)
2259 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2260}
2261
36350114
GP		 2262int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2263{
2264 int err = 0;
2265 int i;
2266
2267 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2268 return 0;
2269
2270 for (i = 0; i < priv->params.num_channels; i++) {
2271 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2272 if (err)
2273 return err;
2274 }
2275
2276 return 0;
2277}
2278
08fb1dac
SM		 2279static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2280{
2281 struct mlx5e_priv *priv = netdev_priv(netdev);
2282 bool was_opened;
2283 int err = 0;
2284
2285 if (tc && tc != MLX5E_MAX_NUM_TC)
2286 return -EINVAL;
2287
2288 mutex_lock(&priv->state_lock);
2289
2290 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2291 if (was_opened)
2292 mlx5e_close_locked(priv->netdev);
2293
2294 priv->params.num_tc = tc ? tc : 1;
2295
2296 if (was_opened)
2297 err = mlx5e_open_locked(priv->netdev);
2298
2299 mutex_unlock(&priv->state_lock);
2300
2301 return err;
2302}
2303
2304static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2305 __be16 proto, struct tc_to_netdev *tc)
2306{
e8f887ac
AV		 2307 struct mlx5e_priv *priv = netdev_priv(dev);
2308
2309 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2310 goto mqprio;
2311
2312 switch (tc->type) {
e3a2b7ed
AV		 2313 case TC_SETUP_CLSFLOWER:
2314 switch (tc->cls_flower->command) {
2315 case TC_CLSFLOWER_REPLACE:
2316 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2317 case TC_CLSFLOWER_DESTROY:
2318 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2319 case TC_CLSFLOWER_STATS:
2320 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2321 }
e8f887ac
AV		 2322 default:
2323 return -EOPNOTSUPP;
2324 }
2325
2326mqprio:
67ba422e 2327 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2328 return -EINVAL;
2329
2330 return mlx5e_setup_tc(dev, tc->tc);
2331}
2332
cb67b832 2333struct rtnl_link_stats64 *
f62b8bb8
AV		 2334mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2335{
2336 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2337 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2338 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2339 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2340
9218b44d
GP		 2341 stats->rx_packets = sstats->rx_packets;
2342 stats->rx_bytes = sstats->rx_bytes;
2343 stats->tx_packets = sstats->tx_packets;
2344 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2345
2346 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2347 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2348
2349 stats->rx_length_errors =
9218b44d
GP		 2350 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2351 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2352 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2353 stats->rx_crc_errors =
9218b44d
GP		 2354 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2355 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2356 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2357 stats->tx_carrier_errors =
9218b44d 2358 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2359 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2360 stats->rx_frame_errors;
2361 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2362
2363 /* vport multicast also counts packets that are dropped due to steering
2364 * or rx out of buffer
2365 */
9218b44d
GP		 2366 stats->multicast =
2367 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2368
2369 return stats;
2370}
2371
2372static void mlx5e_set_rx_mode(struct net_device *dev)
2373{
2374 struct mlx5e_priv *priv = netdev_priv(dev);
2375
7bb29755 2376 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2377}
2378
2379static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2380{
2381 struct mlx5e_priv *priv = netdev_priv(netdev);
2382 struct sockaddr *saddr = addr;
2383
2384 if (!is_valid_ether_addr(saddr->sa_data))
2385 return -EADDRNOTAVAIL;
2386
2387 netif_addr_lock_bh(netdev);
2388 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2389 netif_addr_unlock_bh(netdev);
2390
7bb29755 2391 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2392
2393 return 0;
2394}
2395
0e405443
GP		 2396#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2397 do { \
2398 if (enable) \
2399 netdev->features |= feature; \
2400 else \
2401 netdev->features &= ~feature; \
2402 } while (0)
2403
2404typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2405
2406static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2407{
2408 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2409 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2410 int err;
f62b8bb8
AV		 2411
2412 mutex_lock(&priv->state_lock);
f62b8bb8 2413
0e405443
GP		 2414 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2415 mlx5e_close_locked(priv->netdev);
98e81b0a 2416
0e405443
GP		 2417 priv->params.lro_en = enable;
2418 err = mlx5e_modify_tirs_lro(priv);
2419 if (err) {
2420 netdev_err(netdev, "lro modify failed, %d\n", err);
2421 priv->params.lro_en = !enable;
98e81b0a 2422 }
f62b8bb8 2423
0e405443
GP		 2424 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2425 mlx5e_open_locked(priv->netdev);
2426
9b37b07f
AS		 2427 mutex_unlock(&priv->state_lock);
2428
0e405443
GP		 2429 return err;
2430}
2431
2432static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2433{
2434 struct mlx5e_priv *priv = netdev_priv(netdev);
2435
2436 if (enable)
2437 mlx5e_enable_vlan_filter(priv);
2438 else
2439 mlx5e_disable_vlan_filter(priv);
2440
2441 return 0;
2442}
2443
2444static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2445{
2446 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2447
0e405443 2448 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2449 netdev_err(netdev,
2450 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2451 return -EINVAL;
2452 }
2453
0e405443
GP		 2454 return 0;
2455}
2456
94cb1ebb
EBE		 2457static int set_feature_rx_all(struct net_device *netdev, bool enable)
2458{
2459 struct mlx5e_priv *priv = netdev_priv(netdev);
2460 struct mlx5_core_dev *mdev = priv->mdev;
2461
2462 return mlx5_set_port_fcs(mdev, !enable);
2463}
2464
36350114
GP		 2465static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2466{
2467 struct mlx5e_priv *priv = netdev_priv(netdev);
2468 int err;
2469
2470 mutex_lock(&priv->state_lock);
2471
2472 priv->params.vlan_strip_disable = !enable;
2473 err = mlx5e_modify_rqs_vsd(priv, !enable);
2474 if (err)
2475 priv->params.vlan_strip_disable = enable;
2476
2477 mutex_unlock(&priv->state_lock);
2478
2479 return err;
2480}
2481
45bf454a
MG		 2482#ifdef CONFIG_RFS_ACCEL
2483static int set_feature_arfs(struct net_device *netdev, bool enable)
2484{
2485 struct mlx5e_priv *priv = netdev_priv(netdev);
2486 int err;
2487
2488 if (enable)
2489 err = mlx5e_arfs_enable(priv);
2490 else
2491 err = mlx5e_arfs_disable(priv);
2492
2493 return err;
2494}
2495#endif
2496
0e405443
GP		 2497static int mlx5e_handle_feature(struct net_device *netdev,
2498 netdev_features_t wanted_features,
2499 netdev_features_t feature,
2500 mlx5e_feature_handler feature_handler)
2501{
2502 netdev_features_t changes = wanted_features ^ netdev->features;
2503 bool enable = !!(wanted_features & feature);
2504 int err;
2505
2506 if (!(changes & feature))
2507 return 0;
2508
2509 err = feature_handler(netdev, enable);
2510 if (err) {
2511 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2512 enable ? "Enable" : "Disable", feature, err);
2513 return err;
2514 }
2515
2516 MLX5E_SET_FEATURE(netdev, feature, enable);
2517 return 0;
2518}
2519
2520static int mlx5e_set_features(struct net_device *netdev,
2521 netdev_features_t features)
2522{
2523 int err;
2524
2525 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2526 set_feature_lro);
2527 err |= mlx5e_handle_feature(netdev, features,
2528 NETIF_F_HW_VLAN_CTAG_FILTER,
2529 set_feature_vlan_filter);
2530 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2531 set_feature_tc_num_filters);
94cb1ebb
EBE		 2532 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2533 set_feature_rx_all);
36350114
GP		 2534 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2535 set_feature_rx_vlan);
45bf454a
MG		 2536#ifdef CONFIG_RFS_ACCEL
2537 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2538 set_feature_arfs);
2539#endif
0e405443
GP		 2540
2541 return err ? -EINVAL : 0;
f62b8bb8
AV		 2542}
2543
d8edd246
SM		 2544#define MXL5_HW_MIN_MTU 64
2545#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2546
f62b8bb8
AV		 2547static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2548{
2549 struct mlx5e_priv *priv = netdev_priv(netdev);
2550 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2551 bool was_opened;
046339ea 2552 u16 max_mtu;
d8edd246 2553 u16 min_mtu;
98e81b0a 2554 int err = 0;
506753b0 2555 bool reset;
f62b8bb8 2556
facc9699 2557 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2558
50a9eea6 2559 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2560 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2561
d8edd246 2562 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2563 netdev_err(netdev,
d8edd246
SM		 2564 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2565 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2566 return -EINVAL;
2567 }
2568
2569 mutex_lock(&priv->state_lock);
98e81b0a 2570
506753b0
TT		 2571 reset = !priv->params.lro_en &&
2572 (priv->params.rq_wq_type !=
2573 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2574
98e81b0a 2575 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2576 if (was_opened && reset)
98e81b0a
AS		 2577 mlx5e_close_locked(netdev);
2578
f62b8bb8 2579 netdev->mtu = new_mtu;
13f9bba7 2580 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2581
506753b0 2582 if (was_opened && reset)
98e81b0a
AS		 2583 err = mlx5e_open_locked(netdev);
2584
f62b8bb8
AV		 2585 mutex_unlock(&priv->state_lock);
2586
2587 return err;
2588}
2589
ef9814de
EBE		 2590static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2591{
2592 switch (cmd) {
2593 case SIOCSHWTSTAMP:
2594 return mlx5e_hwstamp_set(dev, ifr);
2595 case SIOCGHWTSTAMP:
2596 return mlx5e_hwstamp_get(dev, ifr);
2597 default:
2598 return -EOPNOTSUPP;
2599 }
2600}
2601
66e49ded
SM		 2602static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2603{
2604 struct mlx5e_priv *priv = netdev_priv(dev);
2605 struct mlx5_core_dev *mdev = priv->mdev;
2606
2607 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2608}
2609
2610static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2611{
2612 struct mlx5e_priv *priv = netdev_priv(dev);
2613 struct mlx5_core_dev *mdev = priv->mdev;
2614
2615 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2616 vlan, qos);
2617}
2618
f942380c
MHY		 2619static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2620{
2621 struct mlx5e_priv *priv = netdev_priv(dev);
2622 struct mlx5_core_dev *mdev = priv->mdev;
2623
2624 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2625}
2626
1edc57e2
MHY		 2627static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2628{
2629 struct mlx5e_priv *priv = netdev_priv(dev);
2630 struct mlx5_core_dev *mdev = priv->mdev;
2631
2632 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2633}
66e49ded
SM		 2634static int mlx5_vport_link2ifla(u8 esw_link)
2635{
2636 switch (esw_link) {
2637 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2638 return IFLA_VF_LINK_STATE_DISABLE;
2639 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2640 return IFLA_VF_LINK_STATE_ENABLE;
2641 }
2642 return IFLA_VF_LINK_STATE_AUTO;
2643}
2644
2645static int mlx5_ifla_link2vport(u8 ifla_link)
2646{
2647 switch (ifla_link) {
2648 case IFLA_VF_LINK_STATE_DISABLE:
2649 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2650 case IFLA_VF_LINK_STATE_ENABLE:
2651 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2652 }
2653 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2654}
2655
2656static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2657 int link_state)
2658{
2659 struct mlx5e_priv *priv = netdev_priv(dev);
2660 struct mlx5_core_dev *mdev = priv->mdev;
2661
2662 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2663 mlx5_ifla_link2vport(link_state));
2664}
2665
2666static int mlx5e_get_vf_config(struct net_device *dev,
2667 int vf, struct ifla_vf_info *ivi)
2668{
2669 struct mlx5e_priv *priv = netdev_priv(dev);
2670 struct mlx5_core_dev *mdev = priv->mdev;
2671 int err;
2672
2673 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2674 if (err)
2675 return err;
2676 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2677 return 0;
2678}
2679
2680static int mlx5e_get_vf_stats(struct net_device *dev,
2681 int vf, struct ifla_vf_stats *vf_stats)
2682{
2683 struct mlx5e_priv *priv = netdev_priv(dev);
2684 struct mlx5_core_dev *mdev = priv->mdev;
2685
2686 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2687 vf_stats);
2688}
2689
b3f63c3d 2690static void mlx5e_add_vxlan_port(struct net_device *netdev,
974c3f30 2691 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2692{
2693 struct mlx5e_priv *priv = netdev_priv(netdev);
2694
974c3f30
AD		 2695 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2696 return;
2697
b3f63c3d
MF		 2698 if (!mlx5e_vxlan_allowed(priv->mdev))
2699 return;
2700
974c3f30 2701 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 2702}
2703
2704static void mlx5e_del_vxlan_port(struct net_device *netdev,
974c3f30 2705 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2706{
2707 struct mlx5e_priv *priv = netdev_priv(netdev);
2708
974c3f30
AD		 2709 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2710 return;
2711
b3f63c3d
MF		 2712 if (!mlx5e_vxlan_allowed(priv->mdev))
2713 return;
2714
974c3f30 2715 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 2716}
2717
2718static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2719 struct sk_buff *skb,
2720 netdev_features_t features)
2721{
2722 struct udphdr *udph;
2723 u16 proto;
2724 u16 port = 0;
2725
2726 switch (vlan_get_protocol(skb)) {
2727 case htons(ETH_P_IP):
2728 proto = ip_hdr(skb)->protocol;
2729 break;
2730 case htons(ETH_P_IPV6):
2731 proto = ipv6_hdr(skb)->nexthdr;
2732 break;
2733 default:
2734 goto out;
2735 }
2736
2737 if (proto == IPPROTO_UDP) {
2738 udph = udp_hdr(skb);
2739 port = be16_to_cpu(udph->dest);
2740 }
2741
2742 /* Verify if UDP port is being offloaded by HW */
2743 if (port && mlx5e_vxlan_lookup_port(priv, port))
2744 return features;
2745
2746out:
2747 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2748 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2749}
2750
2751static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2752 struct net_device *netdev,
2753 netdev_features_t features)
2754{
2755 struct mlx5e_priv *priv = netdev_priv(netdev);
2756
2757 features = vlan_features_check(skb, features);
2758 features = vxlan_features_check(skb, features);
2759
2760 /* Validate if the tunneled packet is being offloaded by HW */
2761 if (skb->encapsulation &&
2762 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2763 return mlx5e_vxlan_features_check(priv, skb, features);
2764
2765 return features;
2766}
2767
3947ca18
DJ		 2768static void mlx5e_tx_timeout(struct net_device *dev)
2769{
2770 struct mlx5e_priv *priv = netdev_priv(dev);
2771 bool sched_work = false;
2772 int i;
2773
2774 netdev_err(dev, "TX timeout detected\n");
2775
2776 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2777 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2778
2c1ccc99 2779 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 2780 continue;
2781 sched_work = true;
6e8dd6d6 2782 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3947ca18
DJ		 2783 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2784 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2785 }
2786
2787 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2788 schedule_work(&priv->tx_timeout_work);
2789}
2790
b0eed40e 2791static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2792 .ndo_open = mlx5e_open,
2793 .ndo_stop = mlx5e_close,
2794 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2795 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2796 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2797 .ndo_get_stats64 = mlx5e_get_stats,
2798 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2799 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2800 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2801 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2802 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2803 .ndo_change_mtu = mlx5e_change_mtu,
2804 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 2805 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 2806#ifdef CONFIG_RFS_ACCEL
2807 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2808#endif
3947ca18 2809 .ndo_tx_timeout = mlx5e_tx_timeout,
b0eed40e
SM		 2810};
2811
2812static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2813 .ndo_open = mlx5e_open,
2814 .ndo_stop = mlx5e_close,
2815 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2816 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2817 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2818 .ndo_get_stats64 = mlx5e_get_stats,
2819 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2820 .ndo_set_mac_address = mlx5e_set_mac,
2821 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2822 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2823 .ndo_set_features = mlx5e_set_features,
2824 .ndo_change_mtu = mlx5e_change_mtu,
2825 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 2826 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2827 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 2828 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 2829 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 2830#ifdef CONFIG_RFS_ACCEL
2831 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2832#endif
b0eed40e
SM		 2833 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2834 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 2835 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 2836 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 2837 .ndo_get_vf_config = mlx5e_get_vf_config,
2838 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2839 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 2840 .ndo_tx_timeout = mlx5e_tx_timeout,
f62b8bb8
AV		 2841};
2842
2843static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2844{
2845 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2846 return -ENOTSUPP;
2847 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2848 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2849 !MLX5_CAP_ETH(mdev, csum_cap) ||
2850 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2851 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2852 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2853 MLX5_CAP_FLOWTABLE(mdev,
2854 flow_table_properties_nic_receive.max_ft_level)
2855 < 3) {
f62b8bb8
AV		 2856 mlx5_core_warn(mdev,
2857 "Not creating net device, some required device capabilities are missing\n");
2858 return -ENOTSUPP;
2859 }
66189961
TT		 2860 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2861 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2862 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2863 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2864
f62b8bb8
AV		 2865 return 0;
2866}
2867
58d52291
AS		 2868u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2869{
2870 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2871
2872 return bf_buf_size -
2873 sizeof(struct mlx5e_tx_wqe) +
2874 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2875}
2876
08fb1dac
SM		 2877#ifdef CONFIG_MLX5_CORE_EN_DCB
2878static void mlx5e_ets_init(struct mlx5e_priv *priv)
2879{
2880 int i;
2881
2882 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2883 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2884 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2885 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2886 priv->params.ets.prio_tc[i] = i;
2887 }
2888
2889 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2890 priv->params.ets.prio_tc[0] = 1;
2891 priv->params.ets.prio_tc[1] = 0;
2892}
2893#endif
2894
d8c9660d
TT		 2895void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2896 u32 *indirection_rqt, int len,
85082dba
TT		 2897 int num_channels)
2898{
d8c9660d
TT		 2899 int node = mdev->priv.numa_node;
2900 int node_num_of_cores;
85082dba
TT		 2901 int i;
2902
d8c9660d
TT		 2903 if (node == -1)
2904 node = first_online_node;
2905
2906 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2907
2908 if (node_num_of_cores)
2909 num_channels = min_t(int, num_channels, node_num_of_cores);
2910
85082dba
TT		 2911 for (i = 0; i < len; i++)
2912 indirection_rqt[i] = i % num_channels;
2913}
2914
bc77b240
TT		 2915static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2916{
2917 return MLX5_CAP_GEN(mdev, striding_rq) &&
2918 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2919 MLX5_CAP_ETH(mdev, reg_umr_sq);
2920}
2921
b797a684
SM		 2922static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2923{
2924 enum pcie_link_width width;
2925 enum pci_bus_speed speed;
2926 int err = 0;
2927
2928 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2929 if (err)
2930 return err;
2931
2932 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2933 return -EINVAL;
2934
2935 switch (speed) {
2936 case PCIE_SPEED_2_5GT:
2937 *pci_bw = 2500 * width;
2938 break;
2939 case PCIE_SPEED_5_0GT:
2940 *pci_bw = 5000 * width;
2941 break;
2942 case PCIE_SPEED_8_0GT:
2943 *pci_bw = 8000 * width;
2944 break;
2945 default:
2946 return -EINVAL;
2947 }
2948
2949 return 0;
2950}
2951
2952static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2953{
2954 return (link_speed && pci_bw &&
2955 (pci_bw < 40000) && (pci_bw < link_speed));
2956}
2957
9908aa29
TT		 2958void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2959{
2960 params->rx_cq_period_mode = cq_period_mode;
2961
2962 params->rx_cq_moderation.pkts =
2963 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2964 params->rx_cq_moderation.usec =
2965 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2966
2967 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2968 params->rx_cq_moderation.usec =
2969 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2970}
2971
cff92d7c
HHZ		 2972static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2973 u8 *min_inline_mode)
2974{
2975 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2976 case MLX5E_INLINE_MODE_L2:
2977 *min_inline_mode = MLX5_INLINE_MODE_L2;
2978 break;
2979 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2980 mlx5_query_nic_vport_min_inline(mdev,
2981 min_inline_mode);
2982 break;
2983 case MLX5_INLINE_MODE_NOT_REQUIRED:
2984 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2985 break;
2986 }
2987}
2988
6bfd390b
HHZ		 2989static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
2990 struct net_device *netdev,
127ea380
HHZ		 2991 const struct mlx5e_profile *profile,
2992 void *ppriv)
f62b8bb8
AV		 2993{
2994 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 2995 u32 link_speed = 0;
2996 u32 pci_bw = 0;
cb3c7fd4
GR		 2997 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2998 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
2999 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 3000
3001 priv->params.log_sq_size =
3002 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 3003 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 3004 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3005 MLX5_WQ_TYPE_LINKED_LIST;
3006
b797a684
SM		 3007 /* set CQE compression */
3008 priv->params.rx_cqe_compress_admin = false;
3009 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3010 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3011 mlx5e_get_max_linkspeed(mdev, &link_speed);
3012 mlx5e_get_pci_bw(mdev, &pci_bw);
3013 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3014 link_speed, pci_bw);
3015 priv->params.rx_cqe_compress_admin =
3016 cqe_compress_heuristic(link_speed, pci_bw);
3017 }
3018
3019 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3020
461017cb
TT		 3021 switch (priv->params.rq_wq_type) {
3022 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3023 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
d9d9f156
TT		 3024 priv->params.mpwqe_log_stride_sz =
3025 priv->params.rx_cqe_compress ?
3026 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3027 MLX5_MPWRQ_LOG_STRIDE_SIZE;
3028 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3029 priv->params.mpwqe_log_stride_sz;
461017cb
TT		 3030 priv->params.lro_en = true;
3031 break;
3032 default: /* MLX5_WQ_TYPE_LINKED_LIST */
3033 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3034 }
3035
d9d9f156
TT		 3036 mlx5_core_info(mdev,
3037 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3038 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3039 BIT(priv->params.log_rq_size),
3040 BIT(priv->params.mpwqe_log_stride_sz),
3041 priv->params.rx_cqe_compress_admin);
3042
461017cb
TT		 3043 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3044 BIT(priv->params.log_rq_size));
9908aa29 3045
cb3c7fd4
GR		 3046 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3047 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3048
3049 priv->params.tx_cq_moderation.usec =
f62b8bb8 3050 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3051 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3052 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3053 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3054 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3055 priv->params.num_tc = 1;
2be6967c 3056 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3057
57afead5
AS		 3058 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3059 sizeof(priv->params.toeplitz_hash_key));
3060
d8c9660d 3061 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3062 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3063
f62b8bb8
AV		 3064 priv->params.lro_wqe_sz =
3065 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3066
9908aa29
TT		 3067 /* Initialize pflags */
3068 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3069 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3070
f62b8bb8
AV		 3071 priv->mdev = mdev;
3072 priv->netdev = netdev;
6bfd390b
HHZ		 3073 priv->params.num_channels = profile->max_nch(mdev);
3074 priv->profile = profile;
127ea380 3075 priv->ppriv = ppriv;
f62b8bb8 3076
08fb1dac
SM		 3077#ifdef CONFIG_MLX5_CORE_EN_DCB
3078 mlx5e_ets_init(priv);
3079#endif
f62b8bb8 3080
f62b8bb8
AV		 3081 mutex_init(&priv->state_lock);
3082
3083 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3084 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3085 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3086 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3087}
3088
3089static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3090{
3091 struct mlx5e_priv *priv = netdev_priv(netdev);
3092
e1d7d349 3093 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3094 if (is_zero_ether_addr(netdev->dev_addr) &&
3095 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3096 eth_hw_addr_random(netdev);
3097 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3098 }
f62b8bb8
AV		 3099}
3100
cb67b832
HHZ		 3101static const struct switchdev_ops mlx5e_switchdev_ops = {
3102 .switchdev_port_attr_get = mlx5e_attr_get,
3103};
3104
6bfd390b 3105static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3106{
3107 struct mlx5e_priv *priv = netdev_priv(netdev);
3108 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3109 bool fcs_supported;
3110 bool fcs_enabled;
f62b8bb8
AV		 3111
3112 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3113
08fb1dac 3114 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3115 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 3116#ifdef CONFIG_MLX5_CORE_EN_DCB
3117 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3118#endif
3119 } else {
b0eed40e 3120 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3121 }
66e49ded 3122
f62b8bb8
AV		 3123 netdev->watchdog_timeo = 15 * HZ;
3124
3125 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3126
12be4b21 3127 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3128 netdev->vlan_features |= NETIF_F_IP_CSUM;
3129 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3130 netdev->vlan_features |= NETIF_F_GRO;
3131 netdev->vlan_features |= NETIF_F_TSO;
3132 netdev->vlan_features |= NETIF_F_TSO6;
3133 netdev->vlan_features |= NETIF_F_RXCSUM;
3134 netdev->vlan_features |= NETIF_F_RXHASH;
3135
3136 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3137 netdev->vlan_features |= NETIF_F_LRO;
3138
3139 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3140 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3141 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3142 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3143
b3f63c3d 3144 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3145 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3146 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3147 NETIF_F_GSO_PARTIAL;
b3f63c3d 3148 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3149 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3150 netdev->hw_enc_features |= NETIF_F_TSO;
3151 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3152 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3153 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3154 NETIF_F_GSO_PARTIAL;
3155 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3156 }
3157
94cb1ebb
EBE		 3158 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3159
3160 if (fcs_supported)
3161 netdev->hw_features |= NETIF_F_RXALL;
3162
f62b8bb8
AV		 3163 netdev->features = netdev->hw_features;
3164 if (!priv->params.lro_en)
3165 netdev->features &= ~NETIF_F_LRO;
3166
94cb1ebb
EBE		 3167 if (fcs_enabled)
3168 netdev->features &= ~NETIF_F_RXALL;
3169
e8f887ac
AV		 3170#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3171 if (FT_CAP(flow_modify_en) &&
3172 FT_CAP(modify_root) &&
3173 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3174 FT_CAP(flow_table_modify)) {
3175 netdev->hw_features |= NETIF_F_HW_TC;
3176#ifdef CONFIG_RFS_ACCEL
3177 netdev->hw_features |= NETIF_F_NTUPLE;
3178#endif
3179 }
e8f887ac 3180
f62b8bb8
AV		 3181 netdev->features |= NETIF_F_HIGHDMA;
3182
3183 netdev->priv_flags |= IFF_UNICAST_FLT;
3184
3185 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3186
3187#ifdef CONFIG_NET_SWITCHDEV
3188 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3189 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3190#endif
f62b8bb8
AV		 3191}
3192
593cf338
RS		 3193static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3194{
3195 struct mlx5_core_dev *mdev = priv->mdev;
3196 int err;
3197
3198 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3199 if (err) {
3200 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3201 priv->q_counter = 0;
3202 }
3203}
3204
3205static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3206{
3207 if (!priv->q_counter)
3208 return;
3209
3210 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3211}
3212
bc77b240
TT		 3213static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3214{
3215 struct mlx5_core_dev *mdev = priv->mdev;
fe4c988b
SM		 3216 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3217 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
ec22eb53
SM		 3218 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3219 void *mkc;
3220 u32 *in;
bc77b240
TT		 3221 int err;
3222
3223 in = mlx5_vzalloc(inlen);
3224 if (!in)
3225 return -ENOMEM;
3226
ec22eb53 3227 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
bc77b240 3228
fe4c988b
SM		 3229 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3230
ec22eb53
SM		 3231 MLX5_SET(mkc, mkc, free, 1);
3232 MLX5_SET(mkc, mkc, umr_en, 1);
3233 MLX5_SET(mkc, mkc, lw, 1);
3234 MLX5_SET(mkc, mkc, lr, 1);
3235 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
bc77b240 3236
ec22eb53
SM		 3237 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3238 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3239 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3240 MLX5_SET(mkc, mkc, translations_octword_size,
6abdd5f5 3241 MLX5_MTT_OCTW(npages));
ec22eb53 3242 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
bc77b240 3243
ec22eb53 3244 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
bc77b240 3245
ec22eb53 3246 kvfree(in);
bc77b240
TT		 3247 return err;
3248}
3249
6bfd390b
HHZ		 3250static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3251 struct net_device *netdev,
127ea380
HHZ		 3252 const struct mlx5e_profile *profile,
3253 void *ppriv)
6bfd390b
HHZ		 3254{
3255 struct mlx5e_priv *priv = netdev_priv(netdev);
3256
127ea380 3257 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3258 mlx5e_build_nic_netdev(netdev);
3259 mlx5e_vxlan_init(priv);
3260}
3261
3262static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3263{
127ea380
HHZ		 3264 struct mlx5_core_dev *mdev = priv->mdev;
3265 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3266
6bfd390b 3267 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3268
3269 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3270 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b
HHZ		 3271}
3272
3273static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3274{
3275 struct mlx5_core_dev *mdev = priv->mdev;
3276 int err;
3277 int i;
3278
3279 err = mlx5e_create_indirect_rqts(priv);
3280 if (err) {
3281 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3282 return err;
3283 }
3284
3285 err = mlx5e_create_direct_rqts(priv);
3286 if (err) {
3287 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3288 goto err_destroy_indirect_rqts;
3289 }
3290
3291 err = mlx5e_create_indirect_tirs(priv);
3292 if (err) {
3293 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3294 goto err_destroy_direct_rqts;
3295 }
3296
3297 err = mlx5e_create_direct_tirs(priv);
3298 if (err) {
3299 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3300 goto err_destroy_indirect_tirs;
3301 }
3302
3303 err = mlx5e_create_flow_steering(priv);
3304 if (err) {
3305 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3306 goto err_destroy_direct_tirs;
3307 }
3308
3309 err = mlx5e_tc_init(priv);
3310 if (err)
3311 goto err_destroy_flow_steering;
3312
3313 return 0;
3314
3315err_destroy_flow_steering:
3316 mlx5e_destroy_flow_steering(priv);
3317err_destroy_direct_tirs:
3318 mlx5e_destroy_direct_tirs(priv);
3319err_destroy_indirect_tirs:
3320 mlx5e_destroy_indirect_tirs(priv);
3321err_destroy_direct_rqts:
3322 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3323 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3324err_destroy_indirect_rqts:
3325 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3326 return err;
3327}
3328
3329static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3330{
3331 int i;
3332
3333 mlx5e_tc_cleanup(priv);
3334 mlx5e_destroy_flow_steering(priv);
3335 mlx5e_destroy_direct_tirs(priv);
3336 mlx5e_destroy_indirect_tirs(priv);
3337 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3338 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3339 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3340}
3341
3342static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3343{
3344 int err;
3345
3346 err = mlx5e_create_tises(priv);
3347 if (err) {
3348 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3349 return err;
3350 }
3351
3352#ifdef CONFIG_MLX5_CORE_EN_DCB
3353 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3354#endif
3355 return 0;
3356}
3357
3358static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3359{
3360 struct net_device *netdev = priv->netdev;
3361 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3362 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3363 struct mlx5_eswitch_rep rep;
6bfd390b 3364
7907f23a
AH		 3365 mlx5_lag_add(mdev, netdev);
3366
6bfd390b
HHZ		 3367 if (mlx5e_vxlan_allowed(mdev)) {
3368 rtnl_lock();
3369 udp_tunnel_get_rx_info(netdev);
3370 rtnl_unlock();
3371 }
3372
3373 mlx5e_enable_async_events(priv);
3374 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3375
3376 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3377 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3378 rep.load = mlx5e_nic_rep_load;
3379 rep.unload = mlx5e_nic_rep_unload;
127ea380
HHZ		 3380 rep.vport = 0;
3381 rep.priv_data = priv;
3382 mlx5_eswitch_register_vport_rep(esw, &rep);
3383 }
6bfd390b
HHZ		 3384}
3385
3386static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3387{
3388 queue_work(priv->wq, &priv->set_rx_mode_work);
3389 mlx5e_disable_async_events(priv);
7907f23a 3390 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3391}
3392
3393static const struct mlx5e_profile mlx5e_nic_profile = {
3394 .init = mlx5e_nic_init,
3395 .cleanup = mlx5e_nic_cleanup,
3396 .init_rx = mlx5e_init_nic_rx,
3397 .cleanup_rx = mlx5e_cleanup_nic_rx,
3398 .init_tx = mlx5e_init_nic_tx,
3399 .cleanup_tx = mlx5e_cleanup_nic_tx,
3400 .enable = mlx5e_nic_enable,
3401 .disable = mlx5e_nic_disable,
3402 .update_stats = mlx5e_update_stats,
3403 .max_nch = mlx5e_get_max_num_channels,
3404 .max_tc = MLX5E_MAX_NUM_TC,
3405};
3406
26e59d80
MHY		 3407struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3408 const struct mlx5e_profile *profile,
3409 void *ppriv)
f62b8bb8 3410{
26e59d80 3411 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3412 struct net_device *netdev;
3413 struct mlx5e_priv *priv;
f62b8bb8 3414
08fb1dac 3415 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3416 nch * profile->max_tc,
08fb1dac 3417 nch);
f62b8bb8
AV		 3418 if (!netdev) {
3419 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3420 return NULL;
3421 }
3422
127ea380 3423 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3424
3425 netif_carrier_off(netdev);
3426
3427 priv = netdev_priv(netdev);
3428
7bb29755
MF		 3429 priv->wq = create_singlethread_workqueue("mlx5e");
3430 if (!priv->wq)
26e59d80
MHY		 3431 goto err_cleanup_nic;
3432
3433 return netdev;
3434
3435err_cleanup_nic:
3436 profile->cleanup(priv);
3437 free_netdev(netdev);
3438
3439 return NULL;
3440}
3441
3442int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3443{
3444 const struct mlx5e_profile *profile;
3445 struct mlx5e_priv *priv;
3446 int err;
3447
3448 priv = netdev_priv(netdev);
3449 profile = priv->profile;
3450 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3451
bc77b240
TT		 3452 err = mlx5e_create_umr_mkey(priv);
3453 if (err) {
3454 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
26e59d80 3455 goto out;
bc77b240
TT		 3456 }
3457
6bfd390b
HHZ		 3458 err = profile->init_tx(priv);
3459 if (err)
bc77b240 3460 goto err_destroy_umr_mkey;
5c50368f
AS		 3461
3462 err = mlx5e_open_drop_rq(priv);
3463 if (err) {
3464 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3465 goto err_cleanup_tx;
5c50368f
AS		 3466 }
3467
6bfd390b
HHZ		 3468 err = profile->init_rx(priv);
3469 if (err)
5c50368f 3470 goto err_close_drop_rq;
5c50368f 3471
593cf338
RS		 3472 mlx5e_create_q_counter(priv);
3473
33cfaaa8 3474 mlx5e_init_l2_addr(priv);
5c50368f 3475
13f9bba7
SM		 3476 mlx5e_set_dev_port_mtu(netdev);
3477
6bfd390b
HHZ		 3478 if (profile->enable)
3479 profile->enable(priv);
f62b8bb8 3480
26e59d80
MHY		 3481 rtnl_lock();
3482 if (netif_running(netdev))
3483 mlx5e_open(netdev);
3484 netif_device_attach(netdev);
3485 rtnl_unlock();
f62b8bb8 3486
26e59d80 3487 return 0;
5c50368f
AS		 3488
3489err_close_drop_rq:
3490 mlx5e_close_drop_rq(priv);
3491
6bfd390b
HHZ		 3492err_cleanup_tx:
3493 profile->cleanup_tx(priv);
5c50368f 3494
bc77b240
TT		 3495err_destroy_umr_mkey:
3496 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3497
26e59d80
MHY		 3498out:
3499 return err;
f62b8bb8
AV		 3500}
3501
127ea380
HHZ		 3502static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3503{
3504 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3505 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3506 int vport;
dbe413e3 3507 u8 mac[ETH_ALEN];
127ea380
HHZ		 3508
3509 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3510 return;
3511
dbe413e3
HHZ		 3512 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3513
127ea380
HHZ		 3514 for (vport = 1; vport < total_vfs; vport++) {
3515 struct mlx5_eswitch_rep rep;
3516
cb67b832
HHZ		 3517 rep.load = mlx5e_vport_rep_load;
3518 rep.unload = mlx5e_vport_rep_unload;
127ea380 3519 rep.vport = vport;
dbe413e3 3520 ether_addr_copy(rep.hw_id, mac);
127ea380
HHZ		 3521 mlx5_eswitch_register_vport_rep(esw, &rep);
3522 }
3523}
3524
26e59d80
MHY		 3525void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3526{
3527 struct mlx5e_priv *priv = netdev_priv(netdev);
3528 const struct mlx5e_profile *profile = priv->profile;
3529
3530 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3531 if (profile->disable)
3532 profile->disable(priv);
3533
3534 flush_workqueue(priv->wq);
3535
3536 rtnl_lock();
3537 if (netif_running(netdev))
3538 mlx5e_close(netdev);
3539 netif_device_detach(netdev);
3540 rtnl_unlock();
3541
3542 mlx5e_destroy_q_counter(priv);
3543 profile->cleanup_rx(priv);
3544 mlx5e_close_drop_rq(priv);
3545 profile->cleanup_tx(priv);
3546 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3547 cancel_delayed_work_sync(&priv->update_stats_work);
3548}
3549
3550/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3551 * hardware contexts and to connect it to the current netdev.
3552 */
3553static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3554{
3555 struct mlx5e_priv *priv = vpriv;
3556 struct net_device *netdev = priv->netdev;
3557 int err;
3558
3559 if (netif_device_present(netdev))
3560 return 0;
3561
3562 err = mlx5e_create_mdev_resources(mdev);
3563 if (err)
3564 return err;
3565
3566 err = mlx5e_attach_netdev(mdev, netdev);
3567 if (err) {
3568 mlx5e_destroy_mdev_resources(mdev);
3569 return err;
3570 }
3571
3572 return 0;
3573}
3574
3575static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3576{
3577 struct mlx5e_priv *priv = vpriv;
3578 struct net_device *netdev = priv->netdev;
3579
3580 if (!netif_device_present(netdev))
3581 return;
3582
3583 mlx5e_detach_netdev(mdev, netdev);
3584 mlx5e_destroy_mdev_resources(mdev);
3585}
3586
b50d292b
HHZ		 3587static void *mlx5e_add(struct mlx5_core_dev *mdev)
3588{
127ea380 3589 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 3590 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 3591 void *ppriv = NULL;
26e59d80
MHY		 3592 void *priv;
3593 int vport;
3594 int err;
3595 struct net_device *netdev;
b50d292b 3596
26e59d80
MHY		 3597 err = mlx5e_check_required_hca_cap(mdev);
3598 if (err)
b50d292b
HHZ		 3599 return NULL;
3600
127ea380
HHZ		 3601 mlx5e_register_vport_rep(mdev);
3602
3603 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3604 ppriv = &esw->offloads.vport_reps[0];
3605
26e59d80
MHY		 3606 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3607 if (!netdev) {
3608 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
3609 goto err_unregister_reps;
3610 }
3611
3612 priv = netdev_priv(netdev);
3613
3614 err = mlx5e_attach(mdev, priv);
3615 if (err) {
3616 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
3617 goto err_destroy_netdev;
3618 }
3619
3620 err = register_netdev(netdev);
3621 if (err) {
3622 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3623 goto err_detach;
b50d292b 3624 }
26e59d80
MHY		 3625
3626 return priv;
3627
3628err_detach:
3629 mlx5e_detach(mdev, priv);
3630
3631err_destroy_netdev:
3632 mlx5e_destroy_netdev(mdev, priv);
3633
3634err_unregister_reps:
3635 for (vport = 1; vport < total_vfs; vport++)
3636 mlx5_eswitch_unregister_vport_rep(esw, vport);
3637
3638 return NULL;
b50d292b
HHZ		 3639}
3640
cb67b832 3641void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 3642{
6bfd390b 3643 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 3644 struct net_device *netdev = priv->netdev;
3645
26e59d80 3646 unregister_netdev(netdev);
7bb29755 3647 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 3648 if (profile->cleanup)
3649 profile->cleanup(priv);
26e59d80 3650 free_netdev(netdev);
f62b8bb8
AV		 3651}
3652
b50d292b
HHZ		 3653static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3654{
127ea380
HHZ		 3655 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3656 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 3657 struct mlx5e_priv *priv = vpriv;
127ea380 3658 int vport;
b50d292b 3659
127ea380
HHZ		 3660 for (vport = 1; vport < total_vfs; vport++)
3661 mlx5_eswitch_unregister_vport_rep(esw, vport);
3662
26e59d80
MHY		 3663 mlx5e_detach(mdev, vpriv);
3664 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 3665}
3666
f62b8bb8
AV		 3667static void *mlx5e_get_netdev(void *vpriv)
3668{
3669 struct mlx5e_priv *priv = vpriv;
3670
3671 return priv->netdev;
3672}
3673
3674static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 3675 .add = mlx5e_add,
3676 .remove = mlx5e_remove,
26e59d80
MHY		 3677 .attach = mlx5e_attach,
3678 .detach = mlx5e_detach,
f62b8bb8
AV		 3679 .event = mlx5e_async_event,
3680 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3681 .get_dev = mlx5e_get_netdev,
3682};
3683
3684void mlx5e_init(void)
3685{
665bc539 3686 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 3687 mlx5_register_interface(&mlx5e_interface);
3688}
3689
3690void mlx5e_cleanup(void)
3691{
3692 mlx5_unregister_interface(&mlx5e_interface);
3693}
Linux kernel - Deliverables
This page took 0.390625 seconds and 5 git commands to generate.